drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c

   1 /* Copyright 2015 Advanced Micro Devices, Inc. */
   2 #include "dm_services.h"
   3 #include "dc.h"
   4 #include "dc_link_dp.h"
   5 #include "dm_helpers.h"
   6 #include "opp.h"
   7 #include "dsc.h"
   8 #include "resource.h"
   9
  10 #include "inc/core_types.h"
  11 #include "link_hwss.h"
  12 #include "dc_link_ddc.h"
  13 #include "core_status.h"
  14 #include "dpcd_defs.h"
  15
  16 #include "resource.h"
  17 #define DC_LOGGER \
  18         link->ctx->logger
  19
  20
  21 #define DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE   0x50
  22
  23 /* maximum pre emphasis level allowed for each voltage swing level*/
  24 static const enum dc_pre_emphasis voltage_swing_to_pre_emphasis[] = {
  25                 PRE_EMPHASIS_LEVEL3,
  26                 PRE_EMPHASIS_LEVEL2,
  27                 PRE_EMPHASIS_LEVEL1,
  28                 PRE_EMPHASIS_DISABLED };
  29
  30 enum {
  31         POST_LT_ADJ_REQ_LIMIT = 6,
  32         POST_LT_ADJ_REQ_TIMEOUT = 200
  33 };
  34
  35 enum {
  36         LINK_TRAINING_MAX_RETRY_COUNT = 5,
  37         /* to avoid infinite loop where-in the receiver
  38          * switches between different VS
  39          */
  40         LINK_TRAINING_MAX_CR_RETRY = 100
  41 };
  42
  43 static bool decide_fallback_link_setting(
  44                 struct dc_link_settings initial_link_settings,
  45                 struct dc_link_settings *current_link_setting,
  46                 enum link_training_result training_result);
  47 static struct dc_link_settings get_common_supported_link_settings(
  48                 struct dc_link_settings link_setting_a,
  49                 struct dc_link_settings link_setting_b);
  50
  51 static uint32_t get_training_aux_rd_interval(
  52         struct dc_link *link,
  53         uint32_t default_wait_in_micro_secs)
  54 {
  55         union training_aux_rd_interval training_rd_interval;
  56
  57         memset(&training_rd_interval, 0, sizeof(training_rd_interval));
  58
  59         /* overwrite the delay if rev > 1.1*/
  60         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
  61                 /* DP 1.2 or later - retrieve delay through
  62                  * "DPCD_ADDR_TRAINING_AUX_RD_INTERVAL" register */
  63                 core_link_read_dpcd(
  64                         link,
  65                         DP_TRAINING_AUX_RD_INTERVAL,
  66                         (uint8_t *)&training_rd_interval,
  67                         sizeof(training_rd_interval));
  68
  69                 if (training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL)
  70                         default_wait_in_micro_secs = training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000;
  71         }
  72
  73         return default_wait_in_micro_secs;
  74 }
  75
  76 static void wait_for_training_aux_rd_interval(
  77         struct dc_link *link,
  78         uint32_t wait_in_micro_secs)
  79 {
  80         udelay(wait_in_micro_secs);
  81
  82         DC_LOG_HW_LINK_TRAINING("%s:\n wait = %d\n",
  83                 __func__,
  84                 wait_in_micro_secs);
  85 }
  86
  87 static void dpcd_set_training_pattern(
  88         struct dc_link *link,
  89         union dpcd_training_pattern dpcd_pattern)
  90 {
  91         core_link_write_dpcd(
  92                 link,
  93                 DP_TRAINING_PATTERN_SET,
  94                 &dpcd_pattern.raw,
  95                 1);
  96
  97         DC_LOG_HW_LINK_TRAINING("%s\n %x pattern = %x\n",
  98                 __func__,
  99                 DP_TRAINING_PATTERN_SET,
 100                 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
 101 }
 102
 103 static enum dc_dp_training_pattern get_supported_tp(struct dc_link *link)
 104 {
 105         enum dc_dp_training_pattern highest_tp = DP_TRAINING_PATTERN_SEQUENCE_2;
 106         struct encoder_feature_support *features = &link->link_enc->features;
 107         struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
 108
 109         if (features->flags.bits.IS_TPS3_CAPABLE)
 110                 highest_tp = DP_TRAINING_PATTERN_SEQUENCE_3;
 111
 112         if (features->flags.bits.IS_TPS4_CAPABLE)
 113                 highest_tp = DP_TRAINING_PATTERN_SEQUENCE_4;
 114
 115         if (dpcd_caps->max_down_spread.bits.TPS4_SUPPORTED &&
 116                 highest_tp >= DP_TRAINING_PATTERN_SEQUENCE_4)
 117                 return DP_TRAINING_PATTERN_SEQUENCE_4;
 118
 119         if (dpcd_caps->max_ln_count.bits.TPS3_SUPPORTED &&
 120                 highest_tp >= DP_TRAINING_PATTERN_SEQUENCE_3)
 121                 return DP_TRAINING_PATTERN_SEQUENCE_3;
 122
 123         return DP_TRAINING_PATTERN_SEQUENCE_2;
 124 }
 125
 126 static void dpcd_set_link_settings(
 127         struct dc_link *link,
 128         const struct link_training_settings *lt_settings)
 129 {
 130         uint8_t rate;
 131
 132         union down_spread_ctrl downspread = { {0} };
 133         union lane_count_set lane_count_set = { {0} };
 134         enum dc_dp_training_pattern dp_tr_pattern;
 135
 136         downspread.raw = (uint8_t)
 137         (lt_settings->link_settings.link_spread);
 138
 139         lane_count_set.bits.LANE_COUNT_SET =
 140         lt_settings->link_settings.lane_count;
 141
 142         lane_count_set.bits.ENHANCED_FRAMING = lt_settings->enhanced_framing;
 143         lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
 144
 145         dp_tr_pattern = get_supported_tp(link);
 146
 147         if (dp_tr_pattern != DP_TRAINING_PATTERN_SEQUENCE_4) {
 148                 lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED =
 149                                 link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED;
 150         }
 151
 152         core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
 153                 &downspread.raw, sizeof(downspread));
 154
 155         core_link_write_dpcd(link, DP_LANE_COUNT_SET,
 156                 &lane_count_set.raw, 1);
 157
 158         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14 &&
 159                         lt_settings->link_settings.use_link_rate_set == true) {
 160                 rate = 0;
 161                 core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
 162                 core_link_write_dpcd(link, DP_LINK_RATE_SET,
 163                                 &lt_settings->link_settings.link_rate_set, 1);
 164         } else {
 165                 rate = (uint8_t) (lt_settings->link_settings.link_rate);
 166                 core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
 167         }
 168
 169         if (rate) {
 170                 DC_LOG_HW_LINK_TRAINING("%s\n %x rate = %x\n %x lane = %x framing = %x\n %x spread = %x\n",
 171                         __func__,
 172                         DP_LINK_BW_SET,
 173                         lt_settings->link_settings.link_rate,
 174                         DP_LANE_COUNT_SET,
 175                         lt_settings->link_settings.lane_count,
 176                         lt_settings->enhanced_framing,
 177                         DP_DOWNSPREAD_CTRL,
 178                         lt_settings->link_settings.link_spread);
 179         } else {
 180                 DC_LOG_HW_LINK_TRAINING("%s\n %x rate set = %x\n %x lane = %x framing = %x\n %x spread = %x\n",
 181                         __func__,
 182                         DP_LINK_RATE_SET,
 183                         lt_settings->link_settings.link_rate_set,
 184                         DP_LANE_COUNT_SET,
 185                         lt_settings->link_settings.lane_count,
 186                         lt_settings->enhanced_framing,
 187                         DP_DOWNSPREAD_CTRL,
 188                         lt_settings->link_settings.link_spread);
 189         }
 190 }
 191
 192 static enum dpcd_training_patterns
 193         dc_dp_training_pattern_to_dpcd_training_pattern(
 194         struct dc_link *link,
 195         enum dc_dp_training_pattern pattern)
 196 {
 197         enum dpcd_training_patterns dpcd_tr_pattern =
 198         DPCD_TRAINING_PATTERN_VIDEOIDLE;
 199
 200         switch (pattern) {
 201         case DP_TRAINING_PATTERN_SEQUENCE_1:
 202                 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_1;
 203                 break;
 204         case DP_TRAINING_PATTERN_SEQUENCE_2:
 205                 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_2;
 206                 break;
 207         case DP_TRAINING_PATTERN_SEQUENCE_3:
 208                 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_3;
 209                 break;
 210         case DP_TRAINING_PATTERN_SEQUENCE_4:
 211                 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_4;
 212                 break;
 213         default:
 214                 ASSERT(0);
 215                 DC_LOG_HW_LINK_TRAINING("%s: Invalid HW Training pattern: %d\n",
 216                         __func__, pattern);
 217                 break;
 218         }
 219
 220         return dpcd_tr_pattern;
 221 }
 222
 223 static inline bool is_repeater(struct dc_link *link, uint32_t offset)
 224 {
 225         return (!link->is_lttpr_mode_transparent && offset != 0);
 226 }
 227
 228 static void dpcd_set_lt_pattern_and_lane_settings(
 229         struct dc_link *link,
 230         const struct link_training_settings *lt_settings,
 231         enum dc_dp_training_pattern pattern,
 232         uint32_t offset)
 233 {
 234         union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = { { {0} } };
 235
 236         uint32_t dpcd_base_lt_offset;
 237
 238         uint8_t dpcd_lt_buffer[5] = {0};
 239         union dpcd_training_pattern dpcd_pattern = { {0} };
 240         uint32_t lane;
 241         uint32_t size_in_bytes;
 242         bool edp_workaround = false; /* TODO link_prop.INTERNAL */
 243         dpcd_base_lt_offset = DP_TRAINING_PATTERN_SET;
 244
 245         if (is_repeater(link, offset))
 246                 dpcd_base_lt_offset = DP_TRAINING_PATTERN_SET_PHY_REPEATER1 +
 247                         ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
 248
 249         /*****************************************************************
 250         * DpcdAddress_TrainingPatternSet
 251         *****************************************************************/
 252         dpcd_pattern.v1_4.TRAINING_PATTERN_SET =
 253                 dc_dp_training_pattern_to_dpcd_training_pattern(link, pattern);
 254
 255         dpcd_lt_buffer[DP_TRAINING_PATTERN_SET - DP_TRAINING_PATTERN_SET]
 256                 = dpcd_pattern.raw;
 257
 258         if (is_repeater(link, offset)) {
 259                 DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Repeater ID: %d\n 0x%X pattern = %x\n",
 260                         __func__,
 261                         offset,
 262                         dpcd_base_lt_offset,
 263                         dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
 264         } else {
 265                 DC_LOG_HW_LINK_TRAINING("%s\n 0x%X pattern = %x\n",
 266                         __func__,
 267                         dpcd_base_lt_offset,
 268                         dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
 269         }
 270         /*****************************************************************
 271         * DpcdAddress_Lane0Set -> DpcdAddress_Lane3Set
 272         *****************************************************************/
 273         for (lane = 0; lane <
 274                 (uint32_t)(lt_settings->link_settings.lane_count); lane++) {
 275
 276                 dpcd_lane[lane].bits.VOLTAGE_SWING_SET =
 277                 (uint8_t)(lt_settings->lane_settings[lane].VOLTAGE_SWING);
 278                 dpcd_lane[lane].bits.PRE_EMPHASIS_SET =
 279                 (uint8_t)(lt_settings->lane_settings[lane].PRE_EMPHASIS);
 280
 281                 dpcd_lane[lane].bits.MAX_SWING_REACHED =
 282                 (lt_settings->lane_settings[lane].VOLTAGE_SWING ==
 283                 VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
 284                 dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED =
 285                 (lt_settings->lane_settings[lane].PRE_EMPHASIS ==
 286                 PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
 287         }
 288
 289         /* concatenate everything into one buffer*/
 290
 291         size_in_bytes = lt_settings->link_settings.lane_count * sizeof(dpcd_lane[0]);
 292
 293          // 0x00103 - 0x00102
 294         memmove(
 295                 &dpcd_lt_buffer[DP_TRAINING_LANE0_SET - DP_TRAINING_PATTERN_SET],
 296                 dpcd_lane,
 297                 size_in_bytes);
 298
 299         if (is_repeater(link, offset)) {
 300                 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
 301                                 " 0x%X VS set = %x PE set = %x max VS Reached = %x  max PE Reached = %x\n",
 302                         __func__,
 303                         offset,
 304                         dpcd_base_lt_offset,
 305                         dpcd_lane[0].bits.VOLTAGE_SWING_SET,
 306                         dpcd_lane[0].bits.PRE_EMPHASIS_SET,
 307                         dpcd_lane[0].bits.MAX_SWING_REACHED,
 308                         dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
 309         } else {
 310                 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X VS set = %x  PE set = %x max VS Reached = %x  max PE Reached = %x\n",
 311                         __func__,
 312                         dpcd_base_lt_offset,
 313                         dpcd_lane[0].bits.VOLTAGE_SWING_SET,
 314                         dpcd_lane[0].bits.PRE_EMPHASIS_SET,
 315                         dpcd_lane[0].bits.MAX_SWING_REACHED,
 316                         dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
 317         }
 318         if (edp_workaround) {
 319                 /* for eDP write in 2 parts because the 5-byte burst is
 320                 * causing issues on some eDP panels (EPR#366724)
 321                 */
 322                 core_link_write_dpcd(
 323                         link,
 324                         DP_TRAINING_PATTERN_SET,
 325                         &dpcd_pattern.raw,
 326                         sizeof(dpcd_pattern.raw));
 327
 328                 core_link_write_dpcd(
 329                         link,
 330                         DP_TRAINING_LANE0_SET,
 331                         (uint8_t *)(dpcd_lane),
 332                         size_in_bytes);
 333
 334                 } else
 335                 /* write it all in (1 + number-of-lanes)-byte burst*/
 336                         core_link_write_dpcd(
 337                                 link,
 338                                 dpcd_base_lt_offset,
 339                                 dpcd_lt_buffer,
 340                                 size_in_bytes + sizeof(dpcd_pattern.raw));
 341
 342         link->cur_lane_setting = lt_settings->lane_settings[0];
 343 }
 344
 345 static bool is_cr_done(enum dc_lane_count ln_count,
 346         union lane_status *dpcd_lane_status)
 347 {
 348         bool done = true;
 349         uint32_t lane;
 350         /*LANEx_CR_DONE bits All 1's?*/
 351         for (lane = 0; lane < (uint32_t)(ln_count); lane++) {
 352                 if (!dpcd_lane_status[lane].bits.CR_DONE_0)
 353                         done = false;
 354         }
 355         return done;
 356
 357 }
 358
 359 static bool is_ch_eq_done(enum dc_lane_count ln_count,
 360         union lane_status *dpcd_lane_status,
 361         union lane_align_status_updated *lane_status_updated)
 362 {
 363         bool done = true;
 364         uint32_t lane;
 365         if (!lane_status_updated->bits.INTERLANE_ALIGN_DONE)
 366                 done = false;
 367         else {
 368                 for (lane = 0; lane < (uint32_t)(ln_count); lane++) {
 369                         if (!dpcd_lane_status[lane].bits.SYMBOL_LOCKED_0 ||
 370                                 !dpcd_lane_status[lane].bits.CHANNEL_EQ_DONE_0)
 371                                 done = false;
 372                 }
 373         }
 374         return done;
 375
 376 }
 377
 378 static void update_drive_settings(
 379                 struct link_training_settings *dest,
 380                 struct link_training_settings src)
 381 {
 382         uint32_t lane;
 383         for (lane = 0; lane < src.link_settings.lane_count; lane++) {
 384                 if (dest->voltage_swing == NULL)
 385                         dest->lane_settings[lane].VOLTAGE_SWING = src.lane_settings[lane].VOLTAGE_SWING;
 386                 else
 387                         dest->lane_settings[lane].VOLTAGE_SWING = *dest->voltage_swing;
 388
 389                 if (dest->pre_emphasis == NULL)
 390                         dest->lane_settings[lane].PRE_EMPHASIS = src.lane_settings[lane].PRE_EMPHASIS;
 391                 else
 392                         dest->lane_settings[lane].PRE_EMPHASIS = *dest->pre_emphasis;
 393
 394                 if (dest->post_cursor2 == NULL)
 395                         dest->lane_settings[lane].POST_CURSOR2 = src.lane_settings[lane].POST_CURSOR2;
 396                 else
 397                         dest->lane_settings[lane].POST_CURSOR2 = *dest->post_cursor2;
 398         }
 399 }
 400
 401 static uint8_t get_nibble_at_index(const uint8_t *buf,
 402         uint32_t index)
 403 {
 404         uint8_t nibble;
 405         nibble = buf[index / 2];
 406
 407         if (index % 2)
 408                 nibble >>= 4;
 409         else
 410                 nibble &= 0x0F;
 411
 412         return nibble;
 413 }
 414
 415 static enum dc_pre_emphasis get_max_pre_emphasis_for_voltage_swing(
 416         enum dc_voltage_swing voltage)
 417 {
 418         enum dc_pre_emphasis pre_emphasis;
 419         pre_emphasis = PRE_EMPHASIS_MAX_LEVEL;
 420
 421         if (voltage <= VOLTAGE_SWING_MAX_LEVEL)
 422                 pre_emphasis = voltage_swing_to_pre_emphasis[voltage];
 423
 424         return pre_emphasis;
 425
 426 }
 427
 428 static void find_max_drive_settings(
 429         const struct link_training_settings *link_training_setting,
 430         struct link_training_settings *max_lt_setting)
 431 {
 432         uint32_t lane;
 433         struct dc_lane_settings max_requested;
 434
 435         max_requested.VOLTAGE_SWING =
 436                 link_training_setting->
 437                 lane_settings[0].VOLTAGE_SWING;
 438         max_requested.PRE_EMPHASIS =
 439                 link_training_setting->
 440                 lane_settings[0].PRE_EMPHASIS;
 441         /*max_requested.postCursor2 =
 442          * link_training_setting->laneSettings[0].postCursor2;*/
 443
 444         /* Determine what the maximum of the requested settings are*/
 445         for (lane = 1; lane < link_training_setting->link_settings.lane_count;
 446                         lane++) {
 447                 if (link_training_setting->lane_settings[lane].VOLTAGE_SWING >
 448                         max_requested.VOLTAGE_SWING)
 449
 450                         max_requested.VOLTAGE_SWING =
 451                         link_training_setting->
 452                         lane_settings[lane].VOLTAGE_SWING;
 453
 454                 if (link_training_setting->lane_settings[lane].PRE_EMPHASIS >
 455                                 max_requested.PRE_EMPHASIS)
 456                         max_requested.PRE_EMPHASIS =
 457                         link_training_setting->
 458                         lane_settings[lane].PRE_EMPHASIS;
 459
 460                 /*
 461                 if (link_training_setting->laneSettings[lane].postCursor2 >
 462                  max_requested.postCursor2)
 463                 {
 464                 max_requested.postCursor2 =
 465                 link_training_setting->laneSettings[lane].postCursor2;
 466                 }
 467                 */
 468         }
 469
 470         /* make sure the requested settings are
 471          * not higher than maximum settings*/
 472         if (max_requested.VOLTAGE_SWING > VOLTAGE_SWING_MAX_LEVEL)
 473                 max_requested.VOLTAGE_SWING = VOLTAGE_SWING_MAX_LEVEL;
 474
 475         if (max_requested.PRE_EMPHASIS > PRE_EMPHASIS_MAX_LEVEL)
 476                 max_requested.PRE_EMPHASIS = PRE_EMPHASIS_MAX_LEVEL;
 477         /*
 478         if (max_requested.postCursor2 > PostCursor2_MaxLevel)
 479         max_requested.postCursor2 = PostCursor2_MaxLevel;
 480         */
 481
 482         /* make sure the pre-emphasis matches the voltage swing*/
 483         if (max_requested.PRE_EMPHASIS >
 484                 get_max_pre_emphasis_for_voltage_swing(
 485                         max_requested.VOLTAGE_SWING))
 486                 max_requested.PRE_EMPHASIS =
 487                 get_max_pre_emphasis_for_voltage_swing(
 488                         max_requested.VOLTAGE_SWING);
 489
 490         /*
 491          * Post Cursor2 levels are completely independent from
 492          * pre-emphasis (Post Cursor1) levels. But Post Cursor2 levels
 493          * can only be applied to each allowable combination of voltage
 494          * swing and pre-emphasis levels */
 495          /* if ( max_requested.postCursor2 >
 496           *  getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing))
 497           *  max_requested.postCursor2 =
 498           *  getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing);
 499           */
 500
 501         max_lt_setting->link_settings.link_rate =
 502                 link_training_setting->link_settings.link_rate;
 503         max_lt_setting->link_settings.lane_count =
 504         link_training_setting->link_settings.lane_count;
 505         max_lt_setting->link_settings.link_spread =
 506                 link_training_setting->link_settings.link_spread;
 507
 508         for (lane = 0; lane <
 509                 link_training_setting->link_settings.lane_count;
 510                 lane++) {
 511                 max_lt_setting->lane_settings[lane].VOLTAGE_SWING =
 512                         max_requested.VOLTAGE_SWING;
 513                 max_lt_setting->lane_settings[lane].PRE_EMPHASIS =
 514                         max_requested.PRE_EMPHASIS;
 515                 /*max_lt_setting->laneSettings[lane].postCursor2 =
 516                  * max_requested.postCursor2;
 517                  */
 518         }
 519
 520 }
 521
 522 static void get_lane_status_and_drive_settings(
 523         struct dc_link *link,
 524         const struct link_training_settings *link_training_setting,
 525         union lane_status *ln_status,
 526         union lane_align_status_updated *ln_status_updated,
 527         struct link_training_settings *req_settings,
 528         uint32_t offset)
 529 {
 530         unsigned int lane01_status_address = DP_LANE0_1_STATUS;
 531         uint8_t lane_adjust_offset = 4;
 532         unsigned int lane01_adjust_address;
 533         uint8_t dpcd_buf[6] = {0};
 534         union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } };
 535         struct link_training_settings request_settings = { {0} };
 536         uint32_t lane;
 537
 538         memset(req_settings, '\0', sizeof(struct link_training_settings));
 539
 540         if (is_repeater(link, offset)) {
 541                 lane01_status_address =
 542                                 DP_LANE0_1_STATUS_PHY_REPEATER1 +
 543                                 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
 544                 lane_adjust_offset = 3;
 545         }
 546
 547         core_link_read_dpcd(
 548                 link,
 549                 lane01_status_address,
 550                 (uint8_t *)(dpcd_buf),
 551                 sizeof(dpcd_buf));
 552
 553         for (lane = 0; lane <
 554                 (uint32_t)(link_training_setting->link_settings.lane_count);
 555                 lane++) {
 556
 557                 ln_status[lane].raw =
 558                         get_nibble_at_index(&dpcd_buf[0], lane);
 559                 dpcd_lane_adjust[lane].raw =
 560                         get_nibble_at_index(&dpcd_buf[lane_adjust_offset], lane);
 561         }
 562
 563         ln_status_updated->raw = dpcd_buf[2];
 564
 565         if (is_repeater(link, offset)) {
 566                 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
 567                                 " 0x%X Lane01Status = %x\n 0x%X Lane23Status = %x\n ",
 568                         __func__,
 569                         offset,
 570                         lane01_status_address, dpcd_buf[0],
 571                         lane01_status_address + 1, dpcd_buf[1]);
 572         } else {
 573                 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01Status = %x\n 0x%X Lane23Status = %x\n ",
 574                         __func__,
 575                         lane01_status_address, dpcd_buf[0],
 576                         lane01_status_address + 1, dpcd_buf[1]);
 577         }
 578         lane01_adjust_address = DP_ADJUST_REQUEST_LANE0_1;
 579
 580         if (is_repeater(link, offset))
 581                 lane01_adjust_address = DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1 +
 582                                 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
 583
 584         if (is_repeater(link, offset)) {
 585                 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
 586                                 " 0x%X Lane01AdjustRequest = %x\n 0x%X Lane23AdjustRequest = %x\n",
 587                                         __func__,
 588                                         offset,
 589                                         lane01_adjust_address,
 590                                         dpcd_buf[lane_adjust_offset],
 591                                         lane01_adjust_address + 1,
 592                                         dpcd_buf[lane_adjust_offset + 1]);
 593         } else {
 594                 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01AdjustRequest = %x\n 0x%X Lane23AdjustRequest = %x\n",
 595                         __func__,
 596                         lane01_adjust_address,
 597                         dpcd_buf[lane_adjust_offset],
 598                         lane01_adjust_address + 1,
 599                         dpcd_buf[lane_adjust_offset + 1]);
 600         }
 601
 602         /*copy to req_settings*/
 603         request_settings.link_settings.lane_count =
 604                 link_training_setting->link_settings.lane_count;
 605         request_settings.link_settings.link_rate =
 606                 link_training_setting->link_settings.link_rate;
 607         request_settings.link_settings.link_spread =
 608                 link_training_setting->link_settings.link_spread;
 609
 610         for (lane = 0; lane <
 611                 (uint32_t)(link_training_setting->link_settings.lane_count);
 612                 lane++) {
 613
 614                 request_settings.lane_settings[lane].VOLTAGE_SWING =
 615                         (enum dc_voltage_swing)(dpcd_lane_adjust[lane].bits.
 616                                 VOLTAGE_SWING_LANE);
 617                 request_settings.lane_settings[lane].PRE_EMPHASIS =
 618                         (enum dc_pre_emphasis)(dpcd_lane_adjust[lane].bits.
 619                                 PRE_EMPHASIS_LANE);
 620         }
 621
 622         /*Note: for postcursor2, read adjusted
 623          * postcursor2 settings from*/
 624         /*DpcdAddress_AdjustRequestPostCursor2 =
 625          *0x020C (not implemented yet)*/
 626
 627         /* we find the maximum of the requested settings across all lanes*/
 628         /* and set this maximum for all lanes*/
 629         find_max_drive_settings(&request_settings, req_settings);
 630
 631         /* if post cursor 2 is needed in the future,
 632          * read DpcdAddress_AdjustRequestPostCursor2 = 0x020C
 633          */
 634
 635 }
 636
 637 static void dpcd_set_lane_settings(
 638         struct dc_link *link,
 639         const struct link_training_settings *link_training_setting,
 640         uint32_t offset)
 641 {
 642         union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = {{{0}}};
 643         uint32_t lane;
 644         unsigned int lane0_set_address;
 645
 646         lane0_set_address = DP_TRAINING_LANE0_SET;
 647
 648         if (is_repeater(link, offset))
 649                 lane0_set_address = DP_TRAINING_LANE0_SET_PHY_REPEATER1 +
 650                 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
 651
 652         for (lane = 0; lane <
 653                 (uint32_t)(link_training_setting->
 654                 link_settings.lane_count);
 655                 lane++) {
 656                 dpcd_lane[lane].bits.VOLTAGE_SWING_SET =
 657                         (uint8_t)(link_training_setting->
 658                         lane_settings[lane].VOLTAGE_SWING);
 659                 dpcd_lane[lane].bits.PRE_EMPHASIS_SET =
 660                         (uint8_t)(link_training_setting->
 661                         lane_settings[lane].PRE_EMPHASIS);
 662                 dpcd_lane[lane].bits.MAX_SWING_REACHED =
 663                         (link_training_setting->
 664                         lane_settings[lane].VOLTAGE_SWING ==
 665                         VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
 666                 dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED =
 667                         (link_training_setting->
 668                         lane_settings[lane].PRE_EMPHASIS ==
 669                         PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
 670         }
 671
 672         core_link_write_dpcd(link,
 673                 lane0_set_address,
 674                 (uint8_t *)(dpcd_lane),
 675                 link_training_setting->link_settings.lane_count);
 676
 677         /*
 678         if (LTSettings.link.rate == LinkRate_High2)
 679         {
 680                 DpcdTrainingLaneSet2 dpcd_lane2[lane_count_DPMax] = {0};
 681                 for ( uint32_t lane = 0;
 682                 lane < lane_count_DPMax; lane++)
 683                 {
 684                         dpcd_lane2[lane].bits.post_cursor2_set =
 685                         static_cast<unsigned char>(
 686                         LTSettings.laneSettings[lane].postCursor2);
 687                         dpcd_lane2[lane].bits.max_post_cursor2_reached = 0;
 688                 }
 689                 m_pDpcdAccessSrv->WriteDpcdData(
 690                 DpcdAddress_Lane0Set2,
 691                 reinterpret_cast<unsigned char*>(dpcd_lane2),
 692                 LTSettings.link.lanes);
 693         }
 694         */
 695
 696         if (is_repeater(link, offset)) {
 697                 DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Repeater ID: %d\n"
 698                                 " 0x%X VS set = %x  PE set = %x max VS Reached = %x  max PE Reached = %x\n",
 699                         __func__,
 700                         offset,
 701                         lane0_set_address,
 702                         dpcd_lane[0].bits.VOLTAGE_SWING_SET,
 703                         dpcd_lane[0].bits.PRE_EMPHASIS_SET,
 704                         dpcd_lane[0].bits.MAX_SWING_REACHED,
 705                         dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
 706
 707         } else {
 708                 DC_LOG_HW_LINK_TRAINING("%s\n 0x%X VS set = %x  PE set = %x max VS Reached = %x  max PE Reached = %x\n",
 709                         __func__,
 710                         lane0_set_address,
 711                         dpcd_lane[0].bits.VOLTAGE_SWING_SET,
 712                         dpcd_lane[0].bits.PRE_EMPHASIS_SET,
 713                         dpcd_lane[0].bits.MAX_SWING_REACHED,
 714                         dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
 715         }
 716         link->cur_lane_setting = link_training_setting->lane_settings[0];
 717
 718 }
 719
 720 static bool is_max_vs_reached(
 721         const struct link_training_settings *lt_settings)
 722 {
 723         uint32_t lane;
 724         for (lane = 0; lane <
 725                 (uint32_t)(lt_settings->link_settings.lane_count);
 726                 lane++) {
 727                 if (lt_settings->lane_settings[lane].VOLTAGE_SWING
 728                         == VOLTAGE_SWING_MAX_LEVEL)
 729                         return true;
 730         }
 731         return false;
 732
 733 }
 734
 735 static bool perform_post_lt_adj_req_sequence(
 736         struct dc_link *link,
 737         struct link_training_settings *lt_settings)
 738 {
 739         enum dc_lane_count lane_count =
 740         lt_settings->link_settings.lane_count;
 741
 742         uint32_t adj_req_count;
 743         uint32_t adj_req_timer;
 744         bool req_drv_setting_changed;
 745         uint32_t lane;
 746
 747         req_drv_setting_changed = false;
 748         for (adj_req_count = 0; adj_req_count < POST_LT_ADJ_REQ_LIMIT;
 749         adj_req_count++) {
 750
 751                 req_drv_setting_changed = false;
 752
 753                 for (adj_req_timer = 0;
 754                         adj_req_timer < POST_LT_ADJ_REQ_TIMEOUT;
 755                         adj_req_timer++) {
 756
 757                         struct link_training_settings req_settings;
 758                         union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
 759                         union lane_align_status_updated
 760                                 dpcd_lane_status_updated;
 761
 762                         get_lane_status_and_drive_settings(
 763                         link,
 764                         lt_settings,
 765                         dpcd_lane_status,
 766                         &dpcd_lane_status_updated,
 767                         &req_settings,
 768                         DPRX);
 769
 770                         if (dpcd_lane_status_updated.bits.
 771                                         POST_LT_ADJ_REQ_IN_PROGRESS == 0)
 772                                 return true;
 773
 774                         if (!is_cr_done(lane_count, dpcd_lane_status))
 775                                 return false;
 776
 777                         if (!is_ch_eq_done(
 778                                 lane_count,
 779                                 dpcd_lane_status,
 780                                 &dpcd_lane_status_updated))
 781                                 return false;
 782
 783                         for (lane = 0; lane < (uint32_t)(lane_count); lane++) {
 784
 785                                 if (lt_settings->
 786                                 lane_settings[lane].VOLTAGE_SWING !=
 787                                 req_settings.lane_settings[lane].
 788                                 VOLTAGE_SWING ||
 789                                 lt_settings->lane_settings[lane].PRE_EMPHASIS !=
 790                                 req_settings.lane_settings[lane].PRE_EMPHASIS) {
 791
 792                                         req_drv_setting_changed = true;
 793                                         break;
 794                                 }
 795                         }
 796
 797                         if (req_drv_setting_changed) {
 798                                 update_drive_settings(
 799                                         lt_settings, req_settings);
 800
 801                                 dc_link_dp_set_drive_settings(link,
 802                                                 lt_settings);
 803                                 break;
 804                         }
 805
 806                         msleep(1);
 807                 }
 808
 809                 if (!req_drv_setting_changed) {
 810                         DC_LOG_WARNING("%s: Post Link Training Adjust Request Timed out\n",
 811                                 __func__);
 812
 813                         ASSERT(0);
 814                         return true;
 815                 }
 816         }
 817         DC_LOG_WARNING("%s: Post Link Training Adjust Request limit reached\n",
 818                 __func__);
 819
 820         ASSERT(0);
 821         return true;
 822
 823 }
 824
 825 /* Only used for channel equalization */
 826 static uint32_t translate_training_aux_read_interval(uint32_t dpcd_aux_read_interval)
 827 {
 828         unsigned int aux_rd_interval_us = 400;
 829
 830         switch (dpcd_aux_read_interval) {
 831         case 0x01:
 832                 aux_rd_interval_us = 400;
 833                 break;
 834         case 0x02:
 835                 aux_rd_interval_us = 4000;
 836                 break;
 837         case 0x03:
 838                 aux_rd_interval_us = 8000;
 839                 break;
 840         case 0x04:
 841                 aux_rd_interval_us = 16000;
 842                 break;
 843         default:
 844                 break;
 845         }
 846
 847         return aux_rd_interval_us;
 848 }
 849
 850 static enum link_training_result get_cr_failure(enum dc_lane_count ln_count,
 851                                         union lane_status *dpcd_lane_status)
 852 {
 853         enum link_training_result result = LINK_TRAINING_SUCCESS;
 854
 855         if (ln_count >= LANE_COUNT_ONE && !dpcd_lane_status[0].bits.CR_DONE_0)
 856                 result = LINK_TRAINING_CR_FAIL_LANE0;
 857         else if (ln_count >= LANE_COUNT_TWO && !dpcd_lane_status[1].bits.CR_DONE_0)
 858                 result = LINK_TRAINING_CR_FAIL_LANE1;
 859         else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[2].bits.CR_DONE_0)
 860                 result = LINK_TRAINING_CR_FAIL_LANE23;
 861         else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[3].bits.CR_DONE_0)
 862                 result = LINK_TRAINING_CR_FAIL_LANE23;
 863         return result;
 864 }
 865
 866 static enum link_training_result perform_channel_equalization_sequence(
 867         struct dc_link *link,
 868         struct link_training_settings *lt_settings,
 869         uint32_t offset)
 870 {
 871         struct link_training_settings req_settings;
 872         enum dc_dp_training_pattern tr_pattern;
 873         uint32_t retries_ch_eq;
 874         uint32_t wait_time_microsec;
 875         enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
 876         union lane_align_status_updated dpcd_lane_status_updated = { {0} };
 877         union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = { { {0} } };
 878
 879         /* Note: also check that TPS4 is a supported feature*/
 880
 881         tr_pattern = lt_settings->pattern_for_eq;
 882
 883         if (is_repeater(link, offset))
 884                 tr_pattern = DP_TRAINING_PATTERN_SEQUENCE_4;
 885
 886         dp_set_hw_training_pattern(link, tr_pattern, offset);
 887
 888         for (retries_ch_eq = 0; retries_ch_eq <= LINK_TRAINING_MAX_RETRY_COUNT;
 889                 retries_ch_eq++) {
 890
 891                 dp_set_hw_lane_settings(link, lt_settings, offset);
 892
 893                 /* 2. update DPCD*/
 894                 if (!retries_ch_eq)
 895                         /* EPR #361076 - write as a 5-byte burst,
 896                          * but only for the 1-st iteration
 897                          */
 898
 899                         dpcd_set_lt_pattern_and_lane_settings(
 900                                 link,
 901                                 lt_settings,
 902                                 tr_pattern, offset);
 903                 else
 904                         dpcd_set_lane_settings(link, lt_settings, offset);
 905
 906                 /* 3. wait for receiver to lock-on*/
 907                 wait_time_microsec = lt_settings->eq_pattern_time;
 908
 909                 if (is_repeater(link, offset))
 910                         wait_time_microsec =
 911                                         translate_training_aux_read_interval(
 912                                                 link->dpcd_caps.lttpr_caps.aux_rd_interval[offset - 1]);
 913
 914                 wait_for_training_aux_rd_interval(
 915                                 link,
 916                                 wait_time_microsec);
 917
 918                 /* 4. Read lane status and requested
 919                  * drive settings as set by the sink*/
 920
 921                 get_lane_status_and_drive_settings(
 922                         link,
 923                         lt_settings,
 924                         dpcd_lane_status,
 925                         &dpcd_lane_status_updated,
 926                         &req_settings,
 927                         offset);
 928
 929                 /* 5. check CR done*/
 930                 if (!is_cr_done(lane_count, dpcd_lane_status))
 931                         return LINK_TRAINING_EQ_FAIL_CR;
 932
 933                 /* 6. check CHEQ done*/
 934                 if (is_ch_eq_done(lane_count,
 935                         dpcd_lane_status,
 936                         &dpcd_lane_status_updated))
 937                         return LINK_TRAINING_SUCCESS;
 938
 939                 /* 7. update VS/PE/PC2 in lt_settings*/
 940                 update_drive_settings(lt_settings, req_settings);
 941         }
 942
 943         return LINK_TRAINING_EQ_FAIL_EQ;
 944
 945 }
 946 #define TRAINING_AUX_RD_INTERVAL 100 //us
 947
 948 static void start_clock_recovery_pattern_early(struct dc_link *link,
 949                 struct link_training_settings *lt_settings,
 950                 uint32_t offset)
 951 {
 952         DC_LOG_HW_LINK_TRAINING("%s\n GPU sends TPS1. Wait 400us.\n",
 953                         __func__);
 954         dp_set_hw_training_pattern(link, DP_TRAINING_PATTERN_SEQUENCE_1, offset);
 955         dp_set_hw_lane_settings(link, lt_settings, offset);
 956         udelay(400);
 957 }
 958
 959 static enum link_training_result perform_clock_recovery_sequence(
 960         struct dc_link *link,
 961         struct link_training_settings *lt_settings,
 962         uint32_t offset)
 963 {
 964         uint32_t retries_cr;
 965         uint32_t retry_count;
 966         uint32_t wait_time_microsec;
 967         struct link_training_settings req_settings;
 968         enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
 969         enum dc_dp_training_pattern tr_pattern = DP_TRAINING_PATTERN_SEQUENCE_1;
 970         union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
 971         union lane_align_status_updated dpcd_lane_status_updated;
 972
 973         retries_cr = 0;
 974         retry_count = 0;
 975
 976         if (!link->ctx->dc->work_arounds.lt_early_cr_pattern)
 977                 dp_set_hw_training_pattern(link, tr_pattern, offset);
 978
 979         /* najeeb - The synaptics MST hub can put the LT in
 980         * infinite loop by switching the VS
 981         */
 982         /* between level 0 and level 1 continuously, here
 983         * we try for CR lock for LinkTrainingMaxCRRetry count*/
 984         while ((retries_cr < LINK_TRAINING_MAX_RETRY_COUNT) &&
 985                 (retry_count < LINK_TRAINING_MAX_CR_RETRY)) {
 986
 987                 memset(&dpcd_lane_status, '\0', sizeof(dpcd_lane_status));
 988                 memset(&dpcd_lane_status_updated, '\0',
 989                 sizeof(dpcd_lane_status_updated));
 990
 991                 /* 1. call HWSS to set lane settings*/
 992                 dp_set_hw_lane_settings(
 993                                 link,
 994                                 lt_settings,
 995                                 offset);
 996
 997                 /* 2. update DPCD of the receiver*/
 998                 if (!retry_count)
 999                         /* EPR #361076 - write as a 5-byte burst,
1000                          * but only for the 1-st iteration.*/
1001                         dpcd_set_lt_pattern_and_lane_settings(
1002                                         link,
1003                                         lt_settings,
1004                                         tr_pattern,
1005                                         offset);
1006                 else
1007                         dpcd_set_lane_settings(
1008                                         link,
1009                                         lt_settings,
1010                                         offset);
1011
1012                 /* 3. wait receiver to lock-on*/
1013                 wait_time_microsec = lt_settings->cr_pattern_time;
1014
1015                 if (!link->is_lttpr_mode_transparent)
1016                         wait_time_microsec = TRAINING_AUX_RD_INTERVAL;
1017
1018                 wait_for_training_aux_rd_interval(
1019                                 link,
1020                                 wait_time_microsec);
1021
1022                 /* 4. Read lane status and requested drive
1023                 * settings as set by the sink
1024                 */
1025                 get_lane_status_and_drive_settings(
1026                                 link,
1027                                 lt_settings,
1028                                 dpcd_lane_status,
1029                                 &dpcd_lane_status_updated,
1030                                 &req_settings,
1031                                 offset);
1032
1033                 /* 5. check CR done*/
1034                 if (is_cr_done(lane_count, dpcd_lane_status))
1035                         return LINK_TRAINING_SUCCESS;
1036
1037                 /* 6. max VS reached*/
1038                 if (is_max_vs_reached(lt_settings))
1039                         break;
1040
1041                 /* 7. same voltage*/
1042                 /* Note: VS same for all lanes,
1043                 * so comparing first lane is sufficient*/
1044                 if (lt_settings->lane_settings[0].VOLTAGE_SWING ==
1045                         req_settings.lane_settings[0].VOLTAGE_SWING)
1046                         retries_cr++;
1047                 else
1048                         retries_cr = 0;
1049
1050                 /* 8. update VS/PE/PC2 in lt_settings*/
1051                 update_drive_settings(lt_settings, req_settings);
1052
1053                 retry_count++;
1054         }
1055
1056         if (retry_count >= LINK_TRAINING_MAX_CR_RETRY) {
1057                 ASSERT(0);
1058                 DC_LOG_ERROR("%s: Link Training Error, could not get CR after %d tries. Possibly voltage swing issue",
1059                         __func__,
1060                         LINK_TRAINING_MAX_CR_RETRY);
1061
1062         }
1063
1064         return get_cr_failure(lane_count, dpcd_lane_status);
1065 }
1066
1067 static inline enum link_training_result perform_link_training_int(
1068         struct dc_link *link,
1069         struct link_training_settings *lt_settings,
1070         enum link_training_result status)
1071 {
1072         union lane_count_set lane_count_set = { {0} };
1073         union dpcd_training_pattern dpcd_pattern = { {0} };
1074
1075         /* 3. set training not in progress*/
1076         dpcd_pattern.v1_4.TRAINING_PATTERN_SET = DPCD_TRAINING_PATTERN_VIDEOIDLE;
1077         dpcd_set_training_pattern(link, dpcd_pattern);
1078
1079         /* 4. mainlink output idle pattern*/
1080         dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
1081
1082         /*
1083          * 5. post training adjust if required
1084          * If the upstream DPTX and downstream DPRX both support TPS4,
1085          * TPS4 must be used instead of POST_LT_ADJ_REQ.
1086          */
1087         if (link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED != 1 ||
1088                         get_supported_tp(link) == DP_TRAINING_PATTERN_SEQUENCE_4)
1089                 return status;
1090
1091         if (status == LINK_TRAINING_SUCCESS &&
1092                 perform_post_lt_adj_req_sequence(link, lt_settings) == false)
1093                 status = LINK_TRAINING_LQA_FAIL;
1094
1095         lane_count_set.bits.LANE_COUNT_SET = lt_settings->link_settings.lane_count;
1096         lane_count_set.bits.ENHANCED_FRAMING = lt_settings->enhanced_framing;
1097         lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
1098
1099         core_link_write_dpcd(
1100                 link,
1101                 DP_LANE_COUNT_SET,
1102                 &lane_count_set.raw,
1103                 sizeof(lane_count_set));
1104
1105         return status;
1106 }
1107
1108 static void initialize_training_settings(
1109          struct dc_link *link,
1110         const struct dc_link_settings *link_setting,
1111         const struct dc_link_training_overrides *overrides,
1112         struct link_training_settings *lt_settings)
1113 {
1114         uint32_t lane;
1115
1116         memset(lt_settings, '\0', sizeof(struct link_training_settings));
1117
1118         /* Initialize link settings */
1119         lt_settings->link_settings.use_link_rate_set = link_setting->use_link_rate_set;
1120         lt_settings->link_settings.link_rate_set = link_setting->link_rate_set;
1121
1122         if (link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN)
1123                 lt_settings->link_settings.link_rate = link->preferred_link_setting.link_rate;
1124         else
1125                 lt_settings->link_settings.link_rate = link_setting->link_rate;
1126
1127         if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN)
1128                 lt_settings->link_settings.lane_count = link->preferred_link_setting.lane_count;
1129         else
1130                 lt_settings->link_settings.lane_count = link_setting->lane_count;
1131
1132         /*@todo[vdevulap] move SS to LS, should not be handled by displaypath*/
1133
1134         /* TODO hard coded to SS for now
1135          * lt_settings.link_settings.link_spread =
1136          * dal_display_path_is_ss_supported(
1137          * path_mode->display_path) ?
1138          * LINK_SPREAD_05_DOWNSPREAD_30KHZ :
1139          * LINK_SPREAD_DISABLED;
1140          */
1141         /* Initialize link spread */
1142         if (link->dp_ss_off)
1143                 lt_settings->link_settings.link_spread = LINK_SPREAD_DISABLED;
1144         else if (overrides->downspread != NULL)
1145                 lt_settings->link_settings.link_spread
1146                         = *overrides->downspread
1147                         ? LINK_SPREAD_05_DOWNSPREAD_30KHZ
1148                         : LINK_SPREAD_DISABLED;
1149         else
1150                 lt_settings->link_settings.link_spread = LINK_SPREAD_05_DOWNSPREAD_30KHZ;
1151
1152         /* Initialize lane settings overrides */
1153         if (overrides->voltage_swing != NULL)
1154                 lt_settings->voltage_swing = overrides->voltage_swing;
1155
1156         if (overrides->pre_emphasis != NULL)
1157                 lt_settings->pre_emphasis = overrides->pre_emphasis;
1158
1159         if (overrides->post_cursor2 != NULL)
1160                 lt_settings->post_cursor2 = overrides->post_cursor2;
1161
1162         /* Initialize lane settings (VS/PE/PC2) */
1163         for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
1164                 lt_settings->lane_settings[lane].VOLTAGE_SWING =
1165                         lt_settings->voltage_swing != NULL ?
1166                         *lt_settings->voltage_swing :
1167                         VOLTAGE_SWING_LEVEL0;
1168                 lt_settings->lane_settings[lane].PRE_EMPHASIS =
1169                         lt_settings->pre_emphasis != NULL ?
1170                         *lt_settings->pre_emphasis
1171                         : PRE_EMPHASIS_DISABLED;
1172                 lt_settings->lane_settings[lane].POST_CURSOR2 =
1173                         lt_settings->post_cursor2 != NULL ?
1174                         *lt_settings->post_cursor2
1175                         : POST_CURSOR2_DISABLED;
1176         }
1177
1178         /* Initialize training timings */
1179         if (overrides->cr_pattern_time != NULL)
1180                 lt_settings->cr_pattern_time = *overrides->cr_pattern_time;
1181         else
1182                 lt_settings->cr_pattern_time = get_training_aux_rd_interval(link, 100);
1183
1184         if (overrides->eq_pattern_time != NULL)
1185                 lt_settings->eq_pattern_time = *overrides->eq_pattern_time;
1186         else
1187                 lt_settings->eq_pattern_time = get_training_aux_rd_interval(link, 400);
1188
1189         if (overrides->pattern_for_eq != NULL)
1190                 lt_settings->pattern_for_eq = *overrides->pattern_for_eq;
1191         else
1192                 lt_settings->pattern_for_eq = get_supported_tp(link);
1193
1194         if (overrides->enhanced_framing != NULL)
1195                 lt_settings->enhanced_framing = *overrides->enhanced_framing;
1196         else
1197                 lt_settings->enhanced_framing = 1;
1198 }
1199
1200 static uint8_t convert_to_count(uint8_t lttpr_repeater_count)
1201 {
1202         switch (lttpr_repeater_count) {
1203         case 0x80: // 1 lttpr repeater
1204                 return 1;
1205         case 0x40: // 2 lttpr repeaters
1206                 return 2;
1207         case 0x20: // 3 lttpr repeaters
1208                 return 3;
1209         case 0x10: // 4 lttpr repeaters
1210                 return 4;
1211         case 0x08: // 5 lttpr repeaters
1212                 return 5;
1213         case 0x04: // 6 lttpr repeaters
1214                 return 6;
1215         case 0x02: // 7 lttpr repeaters
1216                 return 7;
1217         case 0x01: // 8 lttpr repeaters
1218                 return 8;
1219         default:
1220                 break;
1221         }
1222         return 0; // invalid value
1223 }
1224
1225 static void configure_lttpr_mode(struct dc_link *link)
1226 {
1227         /* aux timeout is already set to extended */
1228         /* RESET/SET lttpr mode to enable non transparent mode */
1229         uint8_t repeater_cnt;
1230         uint32_t aux_interval_address;
1231         uint8_t repeater_id;
1232         enum dc_status result = DC_ERROR_UNEXPECTED;
1233         uint8_t repeater_mode = DP_PHY_REPEATER_MODE_TRANSPARENT;
1234
1235         DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Transparent Mode\n", __func__);
1236         result = core_link_write_dpcd(link,
1237                         DP_PHY_REPEATER_MODE,
1238                         (uint8_t *)&repeater_mode,
1239                         sizeof(repeater_mode));
1240
1241         if (result == DC_OK) {
1242                 link->dpcd_caps.lttpr_caps.mode = repeater_mode;
1243         }
1244
1245         if (!link->is_lttpr_mode_transparent) {
1246
1247                 DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Non Transparent Mode\n", __func__);
1248
1249                 repeater_mode = DP_PHY_REPEATER_MODE_NON_TRANSPARENT;
1250                 result = core_link_write_dpcd(link,
1251                                 DP_PHY_REPEATER_MODE,
1252                                 (uint8_t *)&repeater_mode,
1253                                 sizeof(repeater_mode));
1254
1255                 if (result == DC_OK) {
1256                         link->dpcd_caps.lttpr_caps.mode = repeater_mode;
1257                 }
1258
1259                 repeater_cnt = convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
1260                 for (repeater_id = repeater_cnt; repeater_id > 0; repeater_id--) {
1261                         aux_interval_address = DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 +
1262                                                 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (repeater_id - 1));
1263                         core_link_read_dpcd(
1264                                 link,
1265                                 aux_interval_address,
1266                                 (uint8_t *)&link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1],
1267                                 sizeof(link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1]));
1268                         link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1] &= 0x7F;
1269                 }
1270         }
1271 }
1272
1273 static void repeater_training_done(struct dc_link *link, uint32_t offset)
1274 {
1275         union dpcd_training_pattern dpcd_pattern = { {0} };
1276
1277         const uint32_t dpcd_base_lt_offset =
1278                         DP_TRAINING_PATTERN_SET_PHY_REPEATER1 +
1279                                 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
1280         /* Set training not in progress*/
1281         dpcd_pattern.v1_4.TRAINING_PATTERN_SET = DPCD_TRAINING_PATTERN_VIDEOIDLE;
1282
1283         core_link_write_dpcd(
1284                 link,
1285                 dpcd_base_lt_offset,
1286                 &dpcd_pattern.raw,
1287                 1);
1288
1289         DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Id: %d 0x%X pattern = %x\n",
1290                 __func__,
1291                 offset,
1292                 dpcd_base_lt_offset,
1293                 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
1294 }
1295
1296 static void print_status_message(
1297         struct dc_link *link,
1298         const struct link_training_settings *lt_settings,
1299         enum link_training_result status)
1300 {
1301         char *link_rate = "Unknown";
1302         char *lt_result = "Unknown";
1303         char *lt_spread = "Disabled";
1304
1305         switch (lt_settings->link_settings.link_rate) {
1306         case LINK_RATE_LOW:
1307                 link_rate = "RBR";
1308                 break;
1309         case LINK_RATE_HIGH:
1310                 link_rate = "HBR";
1311                 break;
1312         case LINK_RATE_HIGH2:
1313                 link_rate = "HBR2";
1314                 break;
1315         case LINK_RATE_RBR2:
1316                 link_rate = "RBR2";
1317                 break;
1318         case LINK_RATE_HIGH3:
1319                 link_rate = "HBR3";
1320                 break;
1321         default:
1322                 break;
1323         }
1324
1325         switch (status) {
1326         case LINK_TRAINING_SUCCESS:
1327                 lt_result = "pass";
1328                 break;
1329         case LINK_TRAINING_CR_FAIL_LANE0:
1330                 lt_result = "CR failed lane0";
1331                 break;
1332         case LINK_TRAINING_CR_FAIL_LANE1:
1333                 lt_result = "CR failed lane1";
1334                 break;
1335         case LINK_TRAINING_CR_FAIL_LANE23:
1336                 lt_result = "CR failed lane23";
1337                 break;
1338         case LINK_TRAINING_EQ_FAIL_CR:
1339                 lt_result = "CR failed in EQ";
1340                 break;
1341         case LINK_TRAINING_EQ_FAIL_EQ:
1342                 lt_result = "EQ failed";
1343                 break;
1344         case LINK_TRAINING_LQA_FAIL:
1345                 lt_result = "LQA failed";
1346                 break;
1347         default:
1348                 break;
1349         }
1350
1351         switch (lt_settings->link_settings.link_spread) {
1352         case LINK_SPREAD_DISABLED:
1353                 lt_spread = "Disabled";
1354                 break;
1355         case LINK_SPREAD_05_DOWNSPREAD_30KHZ:
1356                 lt_spread = "0.5% 30KHz";
1357                 break;
1358         case LINK_SPREAD_05_DOWNSPREAD_33KHZ:
1359                 lt_spread = "0.5% 33KHz";
1360                 break;
1361         default:
1362                 break;
1363         }
1364
1365         /* Connectivity log: link training */
1366         CONN_MSG_LT(link, "%sx%d %s VS=%d, PE=%d, DS=%s",
1367                                 link_rate,
1368                                 lt_settings->link_settings.lane_count,
1369                                 lt_result,
1370                                 lt_settings->lane_settings[0].VOLTAGE_SWING,
1371                                 lt_settings->lane_settings[0].PRE_EMPHASIS,
1372                                 lt_spread);
1373 }
1374
1375 void dc_link_dp_set_drive_settings(
1376         struct dc_link *link,
1377         struct link_training_settings *lt_settings)
1378 {
1379         /* program ASIC PHY settings*/
1380         dp_set_hw_lane_settings(link, lt_settings, DPRX);
1381
1382         /* Notify DP sink the PHY settings from source */
1383         dpcd_set_lane_settings(link, lt_settings, DPRX);
1384 }
1385
1386 bool dc_link_dp_perform_link_training_skip_aux(
1387         struct dc_link *link,
1388         const struct dc_link_settings *link_setting)
1389 {
1390         struct link_training_settings lt_settings;
1391         enum dc_dp_training_pattern pattern_for_cr = DP_TRAINING_PATTERN_SEQUENCE_1;
1392
1393         initialize_training_settings(
1394                         link,
1395                         link_setting,
1396                         &link->preferred_training_settings,
1397                         &lt_settings);
1398
1399         /* 1. Perform_clock_recovery_sequence. */
1400
1401         /* transmit training pattern for clock recovery */
1402         dp_set_hw_training_pattern(link, pattern_for_cr, DPRX);
1403
1404         /* call HWSS to set lane settings*/
1405         dp_set_hw_lane_settings(link, &lt_settings, DPRX);
1406
1407         /* wait receiver to lock-on*/
1408         wait_for_training_aux_rd_interval(link, lt_settings.cr_pattern_time);
1409
1410         /* 2. Perform_channel_equalization_sequence. */
1411
1412         /* transmit training pattern for channel equalization. */
1413         dp_set_hw_training_pattern(link, lt_settings.pattern_for_eq, DPRX);
1414
1415         /* call HWSS to set lane settings*/
1416         dp_set_hw_lane_settings(link, &lt_settings, DPRX);
1417
1418         /* wait receiver to lock-on. */
1419         wait_for_training_aux_rd_interval(link, lt_settings.eq_pattern_time);
1420
1421         /* 3. Perform_link_training_int. */
1422
1423         /* Mainlink output idle pattern. */
1424         dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
1425
1426         print_status_message(link, &lt_settings, LINK_TRAINING_SUCCESS);
1427
1428         return true;
1429 }
1430
1431 enum link_training_result dc_link_dp_perform_link_training(
1432         struct dc_link *link,
1433         const struct dc_link_settings *link_setting,
1434         bool skip_video_pattern)
1435 {
1436         enum link_training_result status = LINK_TRAINING_SUCCESS;
1437         struct link_training_settings lt_settings;
1438
1439         bool fec_enable;
1440         uint8_t repeater_cnt;
1441         uint8_t repeater_id;
1442
1443         initialize_training_settings(
1444                         link,
1445                         link_setting,
1446                         &link->preferred_training_settings,
1447                         &lt_settings);
1448
1449         /* Configure lttpr mode */
1450         if (!link->is_lttpr_mode_transparent)
1451                 configure_lttpr_mode(link);
1452
1453         if (link->ctx->dc->work_arounds.lt_early_cr_pattern)
1454                 start_clock_recovery_pattern_early(link, &lt_settings, DPRX);
1455
1456         /* 1. set link rate, lane count and spread. */
1457         dpcd_set_link_settings(link, &lt_settings);
1458
1459         if (link->preferred_training_settings.fec_enable != NULL)
1460                 fec_enable = *link->preferred_training_settings.fec_enable;
1461         else
1462                 fec_enable = true;
1463
1464         dp_set_fec_ready(link, fec_enable);
1465
1466         if (!link->is_lttpr_mode_transparent) {
1467
1468                 /* 2. perform link training (set link training done
1469                  *  to false is done as well)
1470                  */
1471                 repeater_cnt = convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
1472
1473                 for (repeater_id = repeater_cnt; (repeater_id > 0 && status == LINK_TRAINING_SUCCESS);
1474                                 repeater_id--) {
1475                         status = perform_clock_recovery_sequence(link, &lt_settings, repeater_id);
1476
1477                         if (status != LINK_TRAINING_SUCCESS)
1478                                 break;
1479
1480                         status = perform_channel_equalization_sequence(link,
1481                                         &lt_settings,
1482                                         repeater_id);
1483
1484                         if (status != LINK_TRAINING_SUCCESS)
1485                                 break;
1486
1487                         repeater_training_done(link, repeater_id);
1488                 }
1489         }
1490
1491         if (status == LINK_TRAINING_SUCCESS) {
1492                 status = perform_clock_recovery_sequence(link, &lt_settings, DPRX);
1493         if (status == LINK_TRAINING_SUCCESS) {
1494                 status = perform_channel_equalization_sequence(link,
1495                                         &lt_settings,
1496                                         DPRX);
1497                 }
1498         }
1499
1500         if ((status == LINK_TRAINING_SUCCESS) || !skip_video_pattern) {
1501                 status = perform_link_training_int(link,
1502                                 &lt_settings,
1503                                 status);
1504         }
1505
1506         /* 6. print status message*/
1507         print_status_message(link, &lt_settings, status);
1508
1509         if (status != LINK_TRAINING_SUCCESS)
1510                 link->ctx->dc->debug_data.ltFailCount++;
1511
1512         return status;
1513 }
1514
1515 bool perform_link_training_with_retries(
1516         const struct dc_link_settings *link_setting,
1517         bool skip_video_pattern,
1518         int attempts,
1519         struct pipe_ctx *pipe_ctx,
1520         enum signal_type signal)
1521 {
1522         uint8_t j;
1523         uint8_t delay_between_attempts = LINK_TRAINING_RETRY_DELAY;
1524         struct dc_stream_state *stream = pipe_ctx->stream;
1525         struct dc_link *link = stream->link;
1526         enum dp_panel_mode panel_mode = dp_get_panel_mode(link);
1527
1528         for (j = 0; j < attempts; ++j) {
1529
1530                 dp_enable_link_phy(
1531                         link,
1532                         signal,
1533                         pipe_ctx->clock_source->id,
1534                         link_setting);
1535
1536                 if (stream->sink_patches.dppowerup_delay > 0) {
1537                         int delay_dp_power_up_in_ms = stream->sink_patches.dppowerup_delay;
1538
1539                         msleep(delay_dp_power_up_in_ms);
1540                 }
1541
1542                 dp_set_panel_mode(link, panel_mode);
1543
1544                 /* We need to do this before the link training to ensure the idle pattern in SST
1545                  * mode will be sent right after the link training
1546                  */
1547                 link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
1548                                                                 pipe_ctx->stream_res.stream_enc->id, true);
1549
1550                 if (link->aux_access_disabled) {
1551                         dc_link_dp_perform_link_training_skip_aux(link, link_setting);
1552                         return true;
1553                 } else if (dc_link_dp_perform_link_training(
1554                                 link,
1555                                 link_setting,
1556                                 skip_video_pattern) == LINK_TRAINING_SUCCESS)
1557                         return true;
1558
1559                 /* latest link training still fail, skip delay and keep PHY on
1560                  */
1561                 if (j == (attempts - 1))
1562                         break;
1563
1564                 dp_disable_link_phy(link, signal);
1565
1566                 msleep(delay_between_attempts);
1567
1568                 delay_between_attempts += LINK_TRAINING_RETRY_DELAY;
1569         }
1570
1571         return false;
1572 }
1573
1574 static enum clock_source_id get_clock_source_id(struct dc_link *link)
1575 {
1576         enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_UNDEFINED;
1577         struct clock_source *dp_cs = link->dc->res_pool->dp_clock_source;
1578
1579         if (dp_cs != NULL) {
1580                 dp_cs_id = dp_cs->id;
1581         } else {
1582                 /*
1583                  * dp clock source is not initialized for some reason.
1584                  * Should not happen, CLOCK_SOURCE_ID_EXTERNAL will be used
1585                  */
1586                 ASSERT(dp_cs);
1587         }
1588
1589         return dp_cs_id;
1590 }
1591
1592 static void set_dp_mst_mode(struct dc_link *link, bool mst_enable)
1593 {
1594         if (mst_enable == false &&
1595                 link->type == dc_connection_mst_branch) {
1596                 /* Disable MST on link. Use only local sink. */
1597                 dp_disable_link_phy_mst(link, link->connector_signal);
1598
1599                 link->type = dc_connection_single;
1600                 link->local_sink = link->remote_sinks[0];
1601                 link->local_sink->sink_signal = SIGNAL_TYPE_DISPLAY_PORT;
1602         } else if (mst_enable == true &&
1603                         link->type == dc_connection_single &&
1604                         link->remote_sinks[0] != NULL) {
1605                 /* Re-enable MST on link. */
1606                 dp_disable_link_phy(link, link->connector_signal);
1607                 dp_enable_mst_on_sink(link, true);
1608
1609                 link->type = dc_connection_mst_branch;
1610                 link->local_sink->sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
1611         }
1612 }
1613
1614 bool dc_link_dp_sync_lt_begin(struct dc_link *link)
1615 {
1616         /* Begin Sync LT. During this time,
1617          * DPCD:600h must not be powered down.
1618          */
1619         link->sync_lt_in_progress = true;
1620
1621         /*Clear any existing preferred settings.*/
1622         memset(&link->preferred_training_settings, 0,
1623                 sizeof(struct dc_link_training_overrides));
1624         memset(&link->preferred_link_setting, 0,
1625                 sizeof(struct dc_link_settings));
1626
1627         return true;
1628 }
1629
1630 enum link_training_result dc_link_dp_sync_lt_attempt(
1631     struct dc_link *link,
1632     struct dc_link_settings *link_settings,
1633     struct dc_link_training_overrides *lt_overrides)
1634 {
1635         struct link_training_settings lt_settings;
1636         enum link_training_result lt_status = LINK_TRAINING_SUCCESS;
1637         enum dp_panel_mode panel_mode = DP_PANEL_MODE_DEFAULT;
1638         enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_EXTERNAL;
1639         bool fec_enable = false;
1640
1641         initialize_training_settings(
1642                 link,
1643                 link_settings,
1644                 lt_overrides,
1645                 &lt_settings);
1646
1647         /* Setup MST Mode */
1648         if (lt_overrides->mst_enable)
1649                 set_dp_mst_mode(link, *lt_overrides->mst_enable);
1650
1651         /* Disable link */
1652         dp_disable_link_phy(link, link->connector_signal);
1653
1654         /* Enable link */
1655         dp_cs_id = get_clock_source_id(link);
1656         dp_enable_link_phy(link, link->connector_signal,
1657                 dp_cs_id, link_settings);
1658
1659         /* Set FEC enable */
1660         fec_enable = lt_overrides->fec_enable && *lt_overrides->fec_enable;
1661         dp_set_fec_ready(link, fec_enable);
1662
1663         if (lt_overrides->alternate_scrambler_reset) {
1664                 if (*lt_overrides->alternate_scrambler_reset)
1665                         panel_mode = DP_PANEL_MODE_EDP;
1666                 else
1667                         panel_mode = DP_PANEL_MODE_DEFAULT;
1668         } else
1669                 panel_mode = dp_get_panel_mode(link);
1670
1671         dp_set_panel_mode(link, panel_mode);
1672
1673         /* Attempt to train with given link training settings */
1674         if (link->ctx->dc->work_arounds.lt_early_cr_pattern)
1675                 start_clock_recovery_pattern_early(link, &lt_settings, DPRX);
1676
1677         /* Set link rate, lane count and spread. */
1678         dpcd_set_link_settings(link, &lt_settings);
1679
1680         /* 2. perform link training (set link training done
1681          *  to false is done as well)
1682          */
1683         lt_status = perform_clock_recovery_sequence(link, &lt_settings, DPRX);
1684         if (lt_status == LINK_TRAINING_SUCCESS) {
1685                 lt_status = perform_channel_equalization_sequence(link,
1686                                                 &lt_settings,
1687                                                 DPRX);
1688         }
1689
1690         /* 3. Sync LT must skip TRAINING_PATTERN_SET:0 (video pattern)*/
1691         /* 4. print status message*/
1692         print_status_message(link, &lt_settings, lt_status);
1693
1694         return lt_status;
1695 }
1696
1697 bool dc_link_dp_sync_lt_end(struct dc_link *link, bool link_down)
1698 {
1699         /* If input parameter is set, shut down phy.
1700          * Still shouldn't turn off dp_receiver (DPCD:600h)
1701          */
1702         if (link_down == true) {
1703                 dp_disable_link_phy(link, link->connector_signal);
1704                 dp_set_fec_ready(link, false);
1705         }
1706
1707         link->sync_lt_in_progress = false;
1708         return true;
1709 }
1710
1711 static struct dc_link_settings get_max_link_cap(struct dc_link *link)
1712 {
1713         struct dc_link_settings max_link_cap = {0};
1714
1715         /* get max link encoder capability */
1716         link->link_enc->funcs->get_max_link_cap(link->link_enc, &max_link_cap);
1717
1718         /* Lower link settings based on sink's link cap */
1719         if (link->reported_link_cap.lane_count < max_link_cap.lane_count)
1720                 max_link_cap.lane_count =
1721                                 link->reported_link_cap.lane_count;
1722         if (link->reported_link_cap.link_rate < max_link_cap.link_rate)
1723                 max_link_cap.link_rate =
1724                                 link->reported_link_cap.link_rate;
1725         if (link->reported_link_cap.link_spread <
1726                         max_link_cap.link_spread)
1727                 max_link_cap.link_spread =
1728                                 link->reported_link_cap.link_spread;
1729         /*
1730          * account for lttpr repeaters cap
1731          * notes: repeaters do not snoop in the DPRX Capabilities addresses (3.6.3).
1732          */
1733         if (!link->is_lttpr_mode_transparent) {
1734                 if (link->dpcd_caps.lttpr_caps.max_lane_count < max_link_cap.lane_count)
1735                         max_link_cap.lane_count = link->dpcd_caps.lttpr_caps.max_lane_count;
1736
1737                 if (link->dpcd_caps.lttpr_caps.max_link_rate < max_link_cap.link_rate)
1738                         max_link_cap.link_rate = link->dpcd_caps.lttpr_caps.max_link_rate;
1739
1740                 DC_LOG_HW_LINK_TRAINING("%s\n Training with LTTPR,  max_lane count %d max_link rate %d \n",
1741                                                 __func__,
1742                                                 max_link_cap.lane_count,
1743                                                 max_link_cap.link_rate);
1744         }
1745         return max_link_cap;
1746 }
1747
1748 static enum dc_status read_hpd_rx_irq_data(
1749         struct dc_link *link,
1750         union hpd_irq_data *irq_data)
1751 {
1752         static enum dc_status retval;
1753
1754         /* The HW reads 16 bytes from 200h on HPD,
1755          * but if we get an AUX_DEFER, the HW cannot retry
1756          * and this causes the CTS tests 4.3.2.1 - 3.2.4 to
1757          * fail, so we now explicitly read 6 bytes which is
1758          * the req from the above mentioned test cases.
1759          *
1760          * For DP 1.4 we need to read those from 2002h range.
1761          */
1762         if (link->dpcd_caps.dpcd_rev.raw < DPCD_REV_14)
1763                 retval = core_link_read_dpcd(
1764                         link,
1765                         DP_SINK_COUNT,
1766                         irq_data->raw,
1767                         sizeof(union hpd_irq_data));
1768         else {
1769                 /* Read 14 bytes in a single read and then copy only the required fields.
1770                  * This is more efficient than doing it in two separate AUX reads. */
1771
1772                 uint8_t tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI + 1];
1773
1774                 retval = core_link_read_dpcd(
1775                         link,
1776                         DP_SINK_COUNT_ESI,
1777                         tmp,
1778                         sizeof(tmp));
1779
1780                 if (retval != DC_OK)
1781                         return retval;
1782
1783                 irq_data->bytes.sink_cnt.raw = tmp[DP_SINK_COUNT_ESI - DP_SINK_COUNT_ESI];
1784                 irq_data->bytes.device_service_irq.raw = tmp[DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 - DP_SINK_COUNT_ESI];
1785                 irq_data->bytes.lane01_status.raw = tmp[DP_LANE0_1_STATUS_ESI - DP_SINK_COUNT_ESI];
1786                 irq_data->bytes.lane23_status.raw = tmp[DP_LANE2_3_STATUS_ESI - DP_SINK_COUNT_ESI];
1787                 irq_data->bytes.lane_status_updated.raw = tmp[DP_LANE_ALIGN_STATUS_UPDATED_ESI - DP_SINK_COUNT_ESI];
1788                 irq_data->bytes.sink_status.raw = tmp[DP_SINK_STATUS_ESI - DP_SINK_COUNT_ESI];
1789         }
1790
1791         return retval;
1792 }
1793
1794 static bool hpd_rx_irq_check_link_loss_status(
1795         struct dc_link *link,
1796         union hpd_irq_data *hpd_irq_dpcd_data)
1797 {
1798         uint8_t irq_reg_rx_power_state = 0;
1799         enum dc_status dpcd_result = DC_ERROR_UNEXPECTED;
1800         union lane_status lane_status;
1801         uint32_t lane;
1802         bool sink_status_changed;
1803         bool return_code;
1804
1805         sink_status_changed = false;
1806         return_code = false;
1807
1808         if (link->cur_link_settings.lane_count == 0)
1809                 return return_code;
1810
1811         /*1. Check that Link Status changed, before re-training.*/
1812
1813         /*parse lane status*/
1814         for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) {
1815                 /* check status of lanes 0,1
1816                  * changed DpcdAddress_Lane01Status (0x202)
1817                  */
1818                 lane_status.raw = get_nibble_at_index(
1819                         &hpd_irq_dpcd_data->bytes.lane01_status.raw,
1820                         lane);
1821
1822                 if (!lane_status.bits.CHANNEL_EQ_DONE_0 ||
1823                         !lane_status.bits.CR_DONE_0 ||
1824                         !lane_status.bits.SYMBOL_LOCKED_0) {
1825                         /* if one of the channel equalization, clock
1826                          * recovery or symbol lock is dropped
1827                          * consider it as (link has been
1828                          * dropped) dp sink status has changed
1829                          */
1830                         sink_status_changed = true;
1831                         break;
1832                 }
1833         }
1834
1835         /* Check interlane align.*/
1836         if (sink_status_changed ||
1837                 !hpd_irq_dpcd_data->bytes.lane_status_updated.bits.INTERLANE_ALIGN_DONE) {
1838
1839                 DC_LOG_HW_HPD_IRQ("%s: Link Status changed.\n", __func__);
1840
1841                 return_code = true;
1842
1843                 /*2. Check that we can handle interrupt: Not in FS DOS,
1844                  *  Not in "Display Timeout" state, Link is trained.
1845                  */
1846                 dpcd_result = core_link_read_dpcd(link,
1847                         DP_SET_POWER,
1848                         &irq_reg_rx_power_state,
1849                         sizeof(irq_reg_rx_power_state));
1850
1851                 if (dpcd_result != DC_OK) {
1852                         DC_LOG_HW_HPD_IRQ("%s: DPCD read failed to obtain power state.\n",
1853                                 __func__);
1854                 } else {
1855                         if (irq_reg_rx_power_state != DP_SET_POWER_D0)
1856                                 return_code = false;
1857                 }
1858         }
1859
1860         return return_code;
1861 }
1862
1863 bool dp_verify_link_cap(
1864         struct dc_link *link,
1865         struct dc_link_settings *known_limit_link_setting,
1866         int *fail_count)
1867 {
1868         struct dc_link_settings max_link_cap = {0};
1869         struct dc_link_settings cur_link_setting = {0};
1870         struct dc_link_settings *cur = &cur_link_setting;
1871         struct dc_link_settings initial_link_settings = {0};
1872         bool success;
1873         bool skip_link_training;
1874         bool skip_video_pattern;
1875         enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_EXTERNAL;
1876         enum link_training_result status;
1877         union hpd_irq_data irq_data;
1878
1879         if (link->dc->debug.skip_detection_link_training) {
1880                 link->verified_link_cap = *known_limit_link_setting;
1881                 return true;
1882         }
1883
1884         memset(&irq_data, 0, sizeof(irq_data));
1885         success = false;
1886         skip_link_training = false;
1887
1888         max_link_cap = get_max_link_cap(link);
1889
1890         /* Grant extended timeout request */
1891         if (!link->is_lttpr_mode_transparent && link->dpcd_caps.lttpr_caps.max_ext_timeout > 0) {
1892                 uint8_t grant = link->dpcd_caps.lttpr_caps.max_ext_timeout & 0x80;
1893
1894                 core_link_write_dpcd(link, DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT, &grant, sizeof(grant));
1895         }
1896
1897         /* TODO implement override and monitor patch later */
1898
1899         /* try to train the link from high to low to
1900          * find the physical link capability
1901          */
1902         /* disable PHY done possible by BIOS, will be done by driver itself */
1903         dp_disable_link_phy(link, link->connector_signal);
1904
1905         dp_cs_id = get_clock_source_id(link);
1906
1907         /* link training starts with the maximum common settings
1908          * supported by both sink and ASIC.
1909          */
1910         initial_link_settings = get_common_supported_link_settings(
1911                         *known_limit_link_setting,
1912                         max_link_cap);
1913         cur_link_setting = initial_link_settings;
1914
1915         /* Temporary Renoir-specific workaround for SWDEV-215184;
1916          * PHY will sometimes be in bad state on hotplugging display from certain USB-C dongle,
1917          * so add extra cycle of enabling and disabling the PHY before first link training.
1918          */
1919         if (link->link_enc->features.flags.bits.DP_IS_USB_C &&
1920                         link->dc->debug.usbc_combo_phy_reset_wa) {
1921                 dp_enable_link_phy(link, link->connector_signal, dp_cs_id, cur);
1922                 dp_disable_link_phy(link, link->connector_signal);
1923         }
1924
1925         do {
1926                 skip_video_pattern = true;
1927
1928                 if (cur->link_rate == LINK_RATE_LOW)
1929                         skip_video_pattern = false;
1930
1931                 dp_enable_link_phy(
1932                                 link,
1933                                 link->connector_signal,
1934                                 dp_cs_id,
1935                                 cur);
1936
1937
1938                 if (skip_link_training)
1939                         success = true;
1940                 else {
1941                         status = dc_link_dp_perform_link_training(
1942                                                         link,
1943                                                         cur,
1944                                                         skip_video_pattern);
1945                         if (status == LINK_TRAINING_SUCCESS)
1946                                 success = true;
1947                         else
1948                                 (*fail_count)++;
1949                 }
1950
1951                 if (success) {
1952                         link->verified_link_cap = *cur;
1953                         udelay(1000);
1954                         if (read_hpd_rx_irq_data(link, &irq_data) == DC_OK)
1955                                 if (hpd_rx_irq_check_link_loss_status(
1956                                                 link,
1957                                                 &irq_data))
1958                                         (*fail_count)++;
1959                 }
1960                 /* always disable the link before trying another
1961                  * setting or before returning we'll enable it later
1962                  * based on the actual mode we're driving
1963                  */
1964                 dp_disable_link_phy(link, link->connector_signal);
1965         } while (!success && decide_fallback_link_setting(
1966                         initial_link_settings, cur, status));
1967
1968         /* Link Training failed for all Link Settings
1969          *  (Lane Count is still unknown)
1970          */
1971         if (!success) {
1972                 /* If all LT fails for all settings,
1973                  * set verified = failed safe (1 lane low)
1974                  */
1975                 link->verified_link_cap.lane_count = LANE_COUNT_ONE;
1976                 link->verified_link_cap.link_rate = LINK_RATE_LOW;
1977
1978                 link->verified_link_cap.link_spread =
1979                 LINK_SPREAD_DISABLED;
1980         }
1981
1982
1983         return success;
1984 }
1985
1986 bool dp_verify_link_cap_with_retries(
1987         struct dc_link *link,
1988         struct dc_link_settings *known_limit_link_setting,
1989         int attempts)
1990 {
1991         uint8_t i = 0;
1992         bool success = false;
1993
1994         for (i = 0; i < attempts; i++) {
1995                 int fail_count = 0;
1996                 enum dc_connection_type type = dc_connection_none;
1997
1998                 memset(&link->verified_link_cap, 0,
1999                                 sizeof(struct dc_link_settings));
2000                 if (!dc_link_detect_sink(link, &type) || type == dc_connection_none) {
2001                         link->verified_link_cap.lane_count = LANE_COUNT_ONE;
2002                         link->verified_link_cap.link_rate = LINK_RATE_LOW;
2003                         link->verified_link_cap.link_spread = LINK_SPREAD_DISABLED;
2004                         break;
2005                 } else if (dp_verify_link_cap(link,
2006                                 &link->reported_link_cap,
2007                                 &fail_count) && fail_count == 0) {
2008                         success = true;
2009                         break;
2010                 }
2011                 msleep(10);
2012         }
2013         return success;
2014 }
2015
2016 bool dp_verify_mst_link_cap(
2017         struct dc_link *link)
2018 {
2019         struct dc_link_settings max_link_cap = {0};
2020
2021         max_link_cap = get_max_link_cap(link);
2022         link->verified_link_cap = get_common_supported_link_settings(
2023                 link->reported_link_cap,
2024                 max_link_cap);
2025
2026         return true;
2027 }
2028
2029 static struct dc_link_settings get_common_supported_link_settings(
2030                 struct dc_link_settings link_setting_a,
2031                 struct dc_link_settings link_setting_b)
2032 {
2033         struct dc_link_settings link_settings = {0};
2034
2035         link_settings.lane_count =
2036                 (link_setting_a.lane_count <=
2037                         link_setting_b.lane_count) ?
2038                         link_setting_a.lane_count :
2039                         link_setting_b.lane_count;
2040         link_settings.link_rate =
2041                 (link_setting_a.link_rate <=
2042                         link_setting_b.link_rate) ?
2043                         link_setting_a.link_rate :
2044                         link_setting_b.link_rate;
2045         link_settings.link_spread = LINK_SPREAD_DISABLED;
2046
2047         /* in DP compliance test, DPR-120 may have
2048          * a random value in its MAX_LINK_BW dpcd field.
2049          * We map it to the maximum supported link rate that
2050          * is smaller than MAX_LINK_BW in this case.
2051          */
2052         if (link_settings.link_rate > LINK_RATE_HIGH3) {
2053                 link_settings.link_rate = LINK_RATE_HIGH3;
2054         } else if (link_settings.link_rate < LINK_RATE_HIGH3
2055                         && link_settings.link_rate > LINK_RATE_HIGH2) {
2056                 link_settings.link_rate = LINK_RATE_HIGH2;
2057         } else if (link_settings.link_rate < LINK_RATE_HIGH2
2058                         && link_settings.link_rate > LINK_RATE_HIGH) {
2059                 link_settings.link_rate = LINK_RATE_HIGH;
2060         } else if (link_settings.link_rate < LINK_RATE_HIGH
2061                         && link_settings.link_rate > LINK_RATE_LOW) {
2062                 link_settings.link_rate = LINK_RATE_LOW;
2063         } else if (link_settings.link_rate < LINK_RATE_LOW) {
2064                 link_settings.link_rate = LINK_RATE_UNKNOWN;
2065         }
2066
2067         return link_settings;
2068 }
2069
2070 static inline bool reached_minimum_lane_count(enum dc_lane_count lane_count)
2071 {
2072         return lane_count <= LANE_COUNT_ONE;
2073 }
2074
2075 static inline bool reached_minimum_link_rate(enum dc_link_rate link_rate)
2076 {
2077         return link_rate <= LINK_RATE_LOW;
2078 }
2079
2080 static enum dc_lane_count reduce_lane_count(enum dc_lane_count lane_count)
2081 {
2082         switch (lane_count) {
2083         case LANE_COUNT_FOUR:
2084                 return LANE_COUNT_TWO;
2085         case LANE_COUNT_TWO:
2086                 return LANE_COUNT_ONE;
2087         case LANE_COUNT_ONE:
2088                 return LANE_COUNT_UNKNOWN;
2089         default:
2090                 return LANE_COUNT_UNKNOWN;
2091         }
2092 }
2093
2094 static enum dc_link_rate reduce_link_rate(enum dc_link_rate link_rate)
2095 {
2096         switch (link_rate) {
2097         case LINK_RATE_HIGH3:
2098                 return LINK_RATE_HIGH2;
2099         case LINK_RATE_HIGH2:
2100                 return LINK_RATE_HIGH;
2101         case LINK_RATE_HIGH:
2102                 return LINK_RATE_LOW;
2103         case LINK_RATE_LOW:
2104                 return LINK_RATE_UNKNOWN;
2105         default:
2106                 return LINK_RATE_UNKNOWN;
2107         }
2108 }
2109
2110 static enum dc_lane_count increase_lane_count(enum dc_lane_count lane_count)
2111 {
2112         switch (lane_count) {
2113         case LANE_COUNT_ONE:
2114                 return LANE_COUNT_TWO;
2115         case LANE_COUNT_TWO:
2116                 return LANE_COUNT_FOUR;
2117         default:
2118                 return LANE_COUNT_UNKNOWN;
2119         }
2120 }
2121
2122 static enum dc_link_rate increase_link_rate(enum dc_link_rate link_rate)
2123 {
2124         switch (link_rate) {
2125         case LINK_RATE_LOW:
2126                 return LINK_RATE_HIGH;
2127         case LINK_RATE_HIGH:
2128                 return LINK_RATE_HIGH2;
2129         case LINK_RATE_HIGH2:
2130                 return LINK_RATE_HIGH3;
2131         default:
2132                 return LINK_RATE_UNKNOWN;
2133         }
2134 }
2135
2136 /*
2137  * function: set link rate and lane count fallback based
2138  * on current link setting and last link training result
2139  * return value:
2140  *                      true - link setting could be set
2141  *                      false - has reached minimum setting
2142  *                                      and no further fallback could be done
2143  */
2144 static bool decide_fallback_link_setting(
2145                 struct dc_link_settings initial_link_settings,
2146                 struct dc_link_settings *current_link_setting,
2147                 enum link_training_result training_result)
2148 {
2149         if (!current_link_setting)
2150                 return false;
2151
2152         switch (training_result) {
2153         case LINK_TRAINING_CR_FAIL_LANE0:
2154         case LINK_TRAINING_CR_FAIL_LANE1:
2155         case LINK_TRAINING_CR_FAIL_LANE23:
2156         case LINK_TRAINING_LQA_FAIL:
2157         {
2158                 if (!reached_minimum_link_rate
2159                                 (current_link_setting->link_rate)) {
2160                         current_link_setting->link_rate =
2161                                 reduce_link_rate(
2162                                         current_link_setting->link_rate);
2163                 } else if (!reached_minimum_lane_count
2164                                 (current_link_setting->lane_count)) {
2165                         current_link_setting->link_rate =
2166                                 initial_link_settings.link_rate;
2167                         if (training_result == LINK_TRAINING_CR_FAIL_LANE0)
2168                                 return false;
2169                         else if (training_result == LINK_TRAINING_CR_FAIL_LANE1)
2170                                 current_link_setting->lane_count =
2171                                                 LANE_COUNT_ONE;
2172                         else if (training_result ==
2173                                         LINK_TRAINING_CR_FAIL_LANE23)
2174                                 current_link_setting->lane_count =
2175                                                 LANE_COUNT_TWO;
2176                         else
2177                                 current_link_setting->lane_count =
2178                                         reduce_lane_count(
2179                                         current_link_setting->lane_count);
2180                 } else {
2181                         return false;
2182                 }
2183                 break;
2184         }
2185         case LINK_TRAINING_EQ_FAIL_EQ:
2186         {
2187                 if (!reached_minimum_lane_count
2188                                 (current_link_setting->lane_count)) {
2189                         current_link_setting->lane_count =
2190                                 reduce_lane_count(
2191                                         current_link_setting->lane_count);
2192                 } else if (!reached_minimum_link_rate
2193                                 (current_link_setting->link_rate)) {
2194                         current_link_setting->link_rate =
2195                                 reduce_link_rate(
2196                                         current_link_setting->link_rate);
2197                 } else {
2198                         return false;
2199                 }
2200                 break;
2201         }
2202         case LINK_TRAINING_EQ_FAIL_CR:
2203         {
2204                 if (!reached_minimum_link_rate
2205                                 (current_link_setting->link_rate)) {
2206                         current_link_setting->link_rate =
2207                                 reduce_link_rate(
2208                                         current_link_setting->link_rate);
2209                 } else {
2210                         return false;
2211                 }
2212                 break;
2213         }
2214         default:
2215                 return false;
2216         }
2217         return true;
2218 }
2219
2220 bool dp_validate_mode_timing(
2221         struct dc_link *link,
2222         const struct dc_crtc_timing *timing)
2223 {
2224         uint32_t req_bw;
2225         uint32_t max_bw;
2226
2227         const struct dc_link_settings *link_setting;
2228
2229         /*always DP fail safe mode*/
2230         if ((timing->pix_clk_100hz / 10) == (uint32_t) 25175 &&
2231                 timing->h_addressable == (uint32_t) 640 &&
2232                 timing->v_addressable == (uint32_t) 480)
2233                 return true;
2234
2235         link_setting = dc_link_get_link_cap(link);
2236
2237         /* TODO: DYNAMIC_VALIDATION needs to be implemented */
2238         /*if (flags.DYNAMIC_VALIDATION == 1 &&
2239                 link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN)
2240                 link_setting = &link->verified_link_cap;
2241         */
2242
2243         req_bw = dc_bandwidth_in_kbps_from_timing(timing);
2244         max_bw = dc_link_bandwidth_kbps(link, link_setting);
2245
2246         if (req_bw <= max_bw) {
2247                 /* remember the biggest mode here, during
2248                  * initial link training (to get
2249                  * verified_link_cap), LS sends event about
2250                  * cannot train at reported cap to upper
2251                  * layer and upper layer will re-enumerate modes.
2252                  * this is not necessary if the lower
2253                  * verified_link_cap is enough to drive
2254                  * all the modes */
2255
2256                 /* TODO: DYNAMIC_VALIDATION needs to be implemented */
2257                 /* if (flags.DYNAMIC_VALIDATION == 1)
2258                         dpsst->max_req_bw_for_verified_linkcap = dal_max(
2259                                 dpsst->max_req_bw_for_verified_linkcap, req_bw); */
2260                 return true;
2261         } else
2262                 return false;
2263 }
2264
2265 static bool decide_dp_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw)
2266 {
2267         struct dc_link_settings initial_link_setting = {
2268                 LANE_COUNT_ONE, LINK_RATE_LOW, LINK_SPREAD_DISABLED, false, 0};
2269         struct dc_link_settings current_link_setting =
2270                         initial_link_setting;
2271         uint32_t link_bw;
2272
2273         /* search for the minimum link setting that:
2274          * 1. is supported according to the link training result
2275          * 2. could support the b/w requested by the timing
2276          */
2277         while (current_link_setting.link_rate <=
2278                         link->verified_link_cap.link_rate) {
2279                 link_bw = dc_link_bandwidth_kbps(
2280                                 link,
2281                                 &current_link_setting);
2282                 if (req_bw <= link_bw) {
2283                         *link_setting = current_link_setting;
2284                         return true;
2285                 }
2286
2287                 if (current_link_setting.lane_count <
2288                                 link->verified_link_cap.lane_count) {
2289                         current_link_setting.lane_count =
2290                                         increase_lane_count(
2291                                                         current_link_setting.lane_count);
2292                 } else {
2293                         current_link_setting.link_rate =
2294                                         increase_link_rate(
2295                                                         current_link_setting.link_rate);
2296                         current_link_setting.lane_count =
2297                                         initial_link_setting.lane_count;
2298                 }
2299         }
2300
2301         return false;
2302 }
2303
2304 static bool decide_edp_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw)
2305 {
2306         struct dc_link_settings initial_link_setting;
2307         struct dc_link_settings current_link_setting;
2308         uint32_t link_bw;
2309
2310         if (link->dpcd_caps.dpcd_rev.raw < DPCD_REV_14 ||
2311                         link->dpcd_caps.edp_supported_link_rates_count == 0) {
2312                 *link_setting = link->verified_link_cap;
2313                 return true;
2314         }
2315
2316         memset(&initial_link_setting, 0, sizeof(initial_link_setting));
2317         initial_link_setting.lane_count = LANE_COUNT_ONE;
2318         initial_link_setting.link_rate = link->dpcd_caps.edp_supported_link_rates[0];
2319         initial_link_setting.link_spread = LINK_SPREAD_DISABLED;
2320         initial_link_setting.use_link_rate_set = true;
2321         initial_link_setting.link_rate_set = 0;
2322         current_link_setting = initial_link_setting;
2323
2324         /* search for the minimum link setting that:
2325          * 1. is supported according to the link training result
2326          * 2. could support the b/w requested by the timing
2327          */
2328         while (current_link_setting.link_rate <=
2329                         link->verified_link_cap.link_rate) {
2330                 link_bw = dc_link_bandwidth_kbps(
2331                                 link,
2332                                 &current_link_setting);
2333                 if (req_bw <= link_bw) {
2334                         *link_setting = current_link_setting;
2335                         return true;
2336                 }
2337
2338                 if (current_link_setting.lane_count <
2339                                 link->verified_link_cap.lane_count) {
2340                         current_link_setting.lane_count =
2341                                         increase_lane_count(
2342                                                         current_link_setting.lane_count);
2343                 } else {
2344                         if (current_link_setting.link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) {
2345                                 current_link_setting.link_rate_set++;
2346                                 current_link_setting.link_rate =
2347                                         link->dpcd_caps.edp_supported_link_rates[current_link_setting.link_rate_set];
2348                                 current_link_setting.lane_count =
2349                                                                         initial_link_setting.lane_count;
2350                         } else
2351                                 break;
2352                 }
2353         }
2354         return false;
2355 }
2356
2357 void decide_link_settings(struct dc_stream_state *stream,
2358         struct dc_link_settings *link_setting)
2359 {
2360         struct dc_link *link;
2361         uint32_t req_bw;
2362
2363         req_bw = dc_bandwidth_in_kbps_from_timing(&stream->timing);
2364
2365         link = stream->link;
2366
2367         /* if preferred is specified through AMDDP, use it, if it's enough
2368          * to drive the mode
2369          */
2370         if (link->preferred_link_setting.lane_count !=
2371                         LANE_COUNT_UNKNOWN &&
2372                         link->preferred_link_setting.link_rate !=
2373                                         LINK_RATE_UNKNOWN) {
2374                 *link_setting =  link->preferred_link_setting;
2375                 return;
2376         }
2377
2378         /* MST doesn't perform link training for now
2379          * TODO: add MST specific link training routine
2380          */
2381         if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
2382                 *link_setting = link->verified_link_cap;
2383                 return;
2384         }
2385
2386         if (link->connector_signal == SIGNAL_TYPE_EDP) {
2387                 if (decide_edp_link_settings(link, link_setting, req_bw))
2388                         return;
2389         } else if (decide_dp_link_settings(link, link_setting, req_bw))
2390                 return;
2391
2392         BREAK_TO_DEBUGGER();
2393         ASSERT(link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN);
2394
2395         *link_setting = link->verified_link_cap;
2396 }
2397
2398 /*************************Short Pulse IRQ***************************/
2399 static bool allow_hpd_rx_irq(const struct dc_link *link)
2400 {
2401         /*
2402          * Don't handle RX IRQ unless one of following is met:
2403          * 1) The link is established (cur_link_settings != unknown)
2404          * 2) We kicked off MST detection
2405          * 3) We know we're dealing with an active dongle
2406          */
2407
2408         if ((link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
2409                 (link->type == dc_connection_mst_branch) ||
2410                 is_dp_active_dongle(link))
2411                 return true;
2412
2413         return false;
2414 }
2415
2416 static bool handle_hpd_irq_psr_sink(struct dc_link *link)
2417 {
2418         union dpcd_psr_configuration psr_configuration;
2419
2420         if (!link->psr_settings.psr_feature_enabled)
2421                 return false;
2422
2423         dm_helpers_dp_read_dpcd(
2424                 link->ctx,
2425                 link,
2426                 368,/*DpcdAddress_PSR_Enable_Cfg*/
2427                 &psr_configuration.raw,
2428                 sizeof(psr_configuration.raw));
2429
2430
2431         if (psr_configuration.bits.ENABLE) {
2432                 unsigned char dpcdbuf[3] = {0};
2433                 union psr_error_status psr_error_status;
2434                 union psr_sink_psr_status psr_sink_psr_status;
2435
2436                 dm_helpers_dp_read_dpcd(
2437                         link->ctx,
2438                         link,
2439                         0x2006, /*DpcdAddress_PSR_Error_Status*/
2440                         (unsigned char *) dpcdbuf,
2441                         sizeof(dpcdbuf));
2442
2443                 /*DPCD 2006h   ERROR STATUS*/
2444                 psr_error_status.raw = dpcdbuf[0];
2445                 /*DPCD 2008h   SINK PANEL SELF REFRESH STATUS*/
2446                 psr_sink_psr_status.raw = dpcdbuf[2];
2447
2448                 if (psr_error_status.bits.LINK_CRC_ERROR ||
2449                                 psr_error_status.bits.RFB_STORAGE_ERROR) {
2450                         /* Acknowledge and clear error bits */
2451                         dm_helpers_dp_write_dpcd(
2452                                 link->ctx,
2453                                 link,
2454                                 8198,/*DpcdAddress_PSR_Error_Status*/
2455                                 &psr_error_status.raw,
2456                                 sizeof(psr_error_status.raw));
2457
2458                         /* PSR error, disable and re-enable PSR */
2459                         dc_link_set_psr_allow_active(link, false, true);
2460                         dc_link_set_psr_allow_active(link, true, true);
2461
2462                         return true;
2463                 } else if (psr_sink_psr_status.bits.SINK_SELF_REFRESH_STATUS ==
2464                                 PSR_SINK_STATE_ACTIVE_DISPLAY_FROM_SINK_RFB){
2465                         /* No error is detect, PSR is active.
2466                          * We should return with IRQ_HPD handled without
2467                          * checking for loss of sync since PSR would have
2468                          * powered down main link.
2469                          */
2470                         return true;
2471                 }
2472         }
2473         return false;
2474 }
2475
2476 static void dp_test_send_link_training(struct dc_link *link)
2477 {
2478         struct dc_link_settings link_settings = {0};
2479
2480         core_link_read_dpcd(
2481                         link,
2482                         DP_TEST_LANE_COUNT,
2483                         (unsigned char *)(&link_settings.lane_count),
2484                         1);
2485         core_link_read_dpcd(
2486                         link,
2487                         DP_TEST_LINK_RATE,
2488                         (unsigned char *)(&link_settings.link_rate),
2489                         1);
2490
2491         /* Set preferred link settings */
2492         link->verified_link_cap.lane_count = link_settings.lane_count;
2493         link->verified_link_cap.link_rate = link_settings.link_rate;
2494
2495         dp_retrain_link_dp_test(link, &link_settings, false);
2496 }
2497
2498 /* TODO Raven hbr2 compliance eye output is unstable
2499  * (toggling on and off) with debugger break
2500  * This caueses intermittent PHY automation failure
2501  * Need to look into the root cause */
2502 static void dp_test_send_phy_test_pattern(struct dc_link *link)
2503 {
2504         union phy_test_pattern dpcd_test_pattern;
2505         union lane_adjust dpcd_lane_adjustment[2];
2506         unsigned char dpcd_post_cursor_2_adjustment = 0;
2507         unsigned char test_80_bit_pattern[
2508                         (DP_TEST_80BIT_CUSTOM_PATTERN_79_72 -
2509                         DP_TEST_80BIT_CUSTOM_PATTERN_7_0)+1] = {0};
2510         enum dp_test_pattern test_pattern;
2511         struct dc_link_training_settings link_settings;
2512         union lane_adjust dpcd_lane_adjust;
2513         unsigned int lane;
2514         struct link_training_settings link_training_settings;
2515         int i = 0;
2516
2517         dpcd_test_pattern.raw = 0;
2518         memset(dpcd_lane_adjustment, 0, sizeof(dpcd_lane_adjustment));
2519         memset(&link_settings, 0, sizeof(link_settings));
2520
2521         /* get phy test pattern and pattern parameters from DP receiver */
2522         core_link_read_dpcd(
2523                         link,
2524                         DP_PHY_TEST_PATTERN,
2525                         &dpcd_test_pattern.raw,
2526                         sizeof(dpcd_test_pattern));
2527         core_link_read_dpcd(
2528                         link,
2529                         DP_ADJUST_REQUEST_LANE0_1,
2530                         &dpcd_lane_adjustment[0].raw,
2531                         sizeof(dpcd_lane_adjustment));
2532
2533         /*get post cursor 2 parameters
2534          * For DP 1.1a or eariler, this DPCD register's value is 0
2535          * For DP 1.2 or later:
2536          * Bits 1:0 = POST_CURSOR2_LANE0; Bits 3:2 = POST_CURSOR2_LANE1
2537          * Bits 5:4 = POST_CURSOR2_LANE2; Bits 7:6 = POST_CURSOR2_LANE3
2538          */
2539         core_link_read_dpcd(
2540                         link,
2541                         DP_ADJUST_REQUEST_POST_CURSOR2,
2542                         &dpcd_post_cursor_2_adjustment,
2543                         sizeof(dpcd_post_cursor_2_adjustment));
2544
2545         /* translate request */
2546         switch (dpcd_test_pattern.bits.PATTERN) {
2547         case PHY_TEST_PATTERN_D10_2:
2548                 test_pattern = DP_TEST_PATTERN_D102;
2549                 break;
2550         case PHY_TEST_PATTERN_SYMBOL_ERROR:
2551                 test_pattern = DP_TEST_PATTERN_SYMBOL_ERROR;
2552                 break;
2553         case PHY_TEST_PATTERN_PRBS7:
2554                 test_pattern = DP_TEST_PATTERN_PRBS7;
2555                 break;
2556         case PHY_TEST_PATTERN_80BIT_CUSTOM:
2557                 test_pattern = DP_TEST_PATTERN_80BIT_CUSTOM;
2558                 break;
2559         case PHY_TEST_PATTERN_CP2520_1:
2560                 /* CP2520 pattern is unstable, temporarily use TPS4 instead */
2561                 test_pattern = (link->dc->caps.force_dp_tps4_for_cp2520 == 1) ?
2562                                 DP_TEST_PATTERN_TRAINING_PATTERN4 :
2563                                 DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE;
2564                 break;
2565         case PHY_TEST_PATTERN_CP2520_2:
2566                 /* CP2520 pattern is unstable, temporarily use TPS4 instead */
2567                 test_pattern = (link->dc->caps.force_dp_tps4_for_cp2520 == 1) ?
2568                                 DP_TEST_PATTERN_TRAINING_PATTERN4 :
2569                                 DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE;
2570                 break;
2571         case PHY_TEST_PATTERN_CP2520_3:
2572                 test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN4;
2573                 break;
2574         default:
2575                 test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
2576         break;
2577         }
2578
2579         if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM)
2580                 core_link_read_dpcd(
2581                                 link,
2582                                 DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
2583                                 test_80_bit_pattern,
2584                                 sizeof(test_80_bit_pattern));
2585
2586         /* prepare link training settings */
2587         link_settings.link = link->cur_link_settings;
2588
2589         for (lane = 0; lane <
2590                 (unsigned int)(link->cur_link_settings.lane_count);
2591                 lane++) {
2592                 dpcd_lane_adjust.raw =
2593                         get_nibble_at_index(&dpcd_lane_adjustment[0].raw, lane);
2594                 link_settings.lane_settings[lane].VOLTAGE_SWING =
2595                         (enum dc_voltage_swing)
2596                         (dpcd_lane_adjust.bits.VOLTAGE_SWING_LANE);
2597                 link_settings.lane_settings[lane].PRE_EMPHASIS =
2598                         (enum dc_pre_emphasis)
2599                         (dpcd_lane_adjust.bits.PRE_EMPHASIS_LANE);
2600                 link_settings.lane_settings[lane].POST_CURSOR2 =
2601                         (enum dc_post_cursor2)
2602                         ((dpcd_post_cursor_2_adjustment >> (lane * 2)) & 0x03);
2603         }
2604
2605         for (i = 0; i < 4; i++)
2606                 link_training_settings.lane_settings[i] =
2607                                 link_settings.lane_settings[i];
2608         link_training_settings.link_settings = link_settings.link;
2609         link_training_settings.allow_invalid_msa_timing_param = false;
2610         /*Usage: Measure DP physical lane signal
2611          * by DP SI test equipment automatically.
2612          * PHY test pattern request is generated by equipment via HPD interrupt.
2613          * HPD needs to be active all the time. HPD should be active
2614          * all the time. Do not touch it.
2615          * forward request to DS
2616          */
2617         dc_link_dp_set_test_pattern(
2618                 link,
2619                 test_pattern,
2620                 DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED,
2621                 &link_training_settings,
2622                 test_80_bit_pattern,
2623                 (DP_TEST_80BIT_CUSTOM_PATTERN_79_72 -
2624                 DP_TEST_80BIT_CUSTOM_PATTERN_7_0)+1);
2625 }
2626
2627 static void dp_test_send_link_test_pattern(struct dc_link *link)
2628 {
2629         union link_test_pattern dpcd_test_pattern;
2630         union test_misc dpcd_test_params;
2631         enum dp_test_pattern test_pattern;
2632         enum dp_test_pattern_color_space test_pattern_color_space =
2633                         DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED;
2634
2635         memset(&dpcd_test_pattern, 0, sizeof(dpcd_test_pattern));
2636         memset(&dpcd_test_params, 0, sizeof(dpcd_test_params));
2637
2638         /* get link test pattern and pattern parameters */
2639         core_link_read_dpcd(
2640                         link,
2641                         DP_TEST_PATTERN,
2642                         &dpcd_test_pattern.raw,
2643                         sizeof(dpcd_test_pattern));
2644         core_link_read_dpcd(
2645                         link,
2646                         DP_TEST_MISC0,
2647                         &dpcd_test_params.raw,
2648                         sizeof(dpcd_test_params));
2649
2650         switch (dpcd_test_pattern.bits.PATTERN) {
2651         case LINK_TEST_PATTERN_COLOR_RAMP:
2652                 test_pattern = DP_TEST_PATTERN_COLOR_RAMP;
2653         break;
2654         case LINK_TEST_PATTERN_VERTICAL_BARS:
2655                 test_pattern = DP_TEST_PATTERN_VERTICAL_BARS;
2656         break; /* black and white */
2657         case LINK_TEST_PATTERN_COLOR_SQUARES:
2658                 test_pattern = (dpcd_test_params.bits.DYN_RANGE ==
2659                                 TEST_DYN_RANGE_VESA ?
2660                                 DP_TEST_PATTERN_COLOR_SQUARES :
2661                                 DP_TEST_PATTERN_COLOR_SQUARES_CEA);
2662         break;
2663         default:
2664                 test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
2665         break;
2666         }
2667
2668         if (dpcd_test_params.bits.CLR_FORMAT == 0)
2669                 test_pattern_color_space = DP_TEST_PATTERN_COLOR_SPACE_RGB;
2670         else
2671                 test_pattern_color_space = dpcd_test_params.bits.YCBCR_COEFS ?
2672                                 DP_TEST_PATTERN_COLOR_SPACE_YCBCR709 :
2673                                 DP_TEST_PATTERN_COLOR_SPACE_YCBCR601;
2674
2675         dc_link_dp_set_test_pattern(
2676                         link,
2677                         test_pattern,
2678                         test_pattern_color_space,
2679                         NULL,
2680                         NULL,
2681                         0);
2682 }
2683
2684 static void dp_test_get_audio_test_data(struct dc_link *link, bool disable_video)
2685 {
2686         union audio_test_mode            dpcd_test_mode = {0};
2687         struct audio_test_pattern_type   dpcd_pattern_type = {0};
2688         union audio_test_pattern_period  dpcd_pattern_period[AUDIO_CHANNELS_COUNT] = {0};
2689         enum dp_test_pattern test_pattern = DP_TEST_PATTERN_AUDIO_OPERATOR_DEFINED;
2690
2691         struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
2692         struct pipe_ctx *pipe_ctx = &pipes[0];
2693         unsigned int channel_count;
2694         unsigned int channel = 0;
2695         unsigned int modes = 0;
2696         unsigned int sampling_rate_in_hz = 0;
2697
2698         // get audio test mode and test pattern parameters
2699         core_link_read_dpcd(
2700                 link,
2701                 DP_TEST_AUDIO_MODE,
2702                 &dpcd_test_mode.raw,
2703                 sizeof(dpcd_test_mode));
2704
2705         core_link_read_dpcd(
2706                 link,
2707                 DP_TEST_AUDIO_PATTERN_TYPE,
2708                 &dpcd_pattern_type.value,
2709                 sizeof(dpcd_pattern_type));
2710
2711         channel_count = dpcd_test_mode.bits.channel_count + 1;
2712
2713         // read pattern periods for requested channels when sawTooth pattern is requested
2714         if (dpcd_pattern_type.value == AUDIO_TEST_PATTERN_SAWTOOTH ||
2715                         dpcd_pattern_type.value == AUDIO_TEST_PATTERN_OPERATOR_DEFINED) {
2716
2717                 test_pattern = (dpcd_pattern_type.value == AUDIO_TEST_PATTERN_SAWTOOTH) ?
2718                                 DP_TEST_PATTERN_AUDIO_SAWTOOTH : DP_TEST_PATTERN_AUDIO_OPERATOR_DEFINED;
2719                 // read period for each channel
2720                 for (channel = 0; channel < channel_count; channel++) {
2721                         core_link_read_dpcd(
2722                                                         link,
2723                                                         DP_TEST_AUDIO_PERIOD_CH1 + channel,
2724                                                         &dpcd_pattern_period[channel].raw,
2725                                                         sizeof(dpcd_pattern_period[channel]));
2726                 }
2727         }
2728
2729         // translate sampling rate
2730         switch (dpcd_test_mode.bits.sampling_rate) {
2731         case AUDIO_SAMPLING_RATE_32KHZ:
2732                 sampling_rate_in_hz = 32000;
2733                 break;
2734         case AUDIO_SAMPLING_RATE_44_1KHZ:
2735                 sampling_rate_in_hz = 44100;
2736                 break;
2737         case AUDIO_SAMPLING_RATE_48KHZ:
2738                 sampling_rate_in_hz = 48000;
2739                 break;
2740         case AUDIO_SAMPLING_RATE_88_2KHZ:
2741                 sampling_rate_in_hz = 88200;
2742                 break;
2743         case AUDIO_SAMPLING_RATE_96KHZ:
2744                 sampling_rate_in_hz = 96000;
2745                 break;
2746         case AUDIO_SAMPLING_RATE_176_4KHZ:
2747                 sampling_rate_in_hz = 176400;
2748                 break;
2749         case AUDIO_SAMPLING_RATE_192KHZ:
2750                 sampling_rate_in_hz = 192000;
2751                 break;
2752         default:
2753                 sampling_rate_in_hz = 0;
2754                 break;
2755         }
2756
2757         link->audio_test_data.flags.test_requested = 1;
2758         link->audio_test_data.flags.disable_video = disable_video;
2759         link->audio_test_data.sampling_rate = sampling_rate_in_hz;
2760         link->audio_test_data.channel_count = channel_count;
2761         link->audio_test_data.pattern_type = test_pattern;
2762
2763         if (test_pattern == DP_TEST_PATTERN_AUDIO_SAWTOOTH) {
2764                 for (modes = 0; modes < pipe_ctx->stream->audio_info.mode_count; modes++) {
2765                         link->audio_test_data.pattern_period[modes] = dpcd_pattern_period[modes].bits.pattern_period;
2766                 }
2767         }
2768 }
2769
2770 static void handle_automated_test(struct dc_link *link)
2771 {
2772         union test_request test_request;
2773         union test_response test_response;
2774
2775         memset(&test_request, 0, sizeof(test_request));
2776         memset(&test_response, 0, sizeof(test_response));
2777
2778         core_link_read_dpcd(
2779                 link,
2780                 DP_TEST_REQUEST,
2781                 &test_request.raw,
2782                 sizeof(union test_request));
2783         if (test_request.bits.LINK_TRAINING) {
2784                 /* ACK first to let DP RX test box monitor LT sequence */
2785                 test_response.bits.ACK = 1;
2786                 core_link_write_dpcd(
2787                         link,
2788                         DP_TEST_RESPONSE,
2789                         &test_response.raw,
2790                         sizeof(test_response));
2791                 dp_test_send_link_training(link);
2792                 /* no acknowledge request is needed again */
2793                 test_response.bits.ACK = 0;
2794         }
2795         if (test_request.bits.LINK_TEST_PATTRN) {
2796                 dp_test_send_link_test_pattern(link);
2797                 test_response.bits.ACK = 1;
2798         }
2799
2800         if (test_request.bits.AUDIO_TEST_PATTERN) {
2801                 dp_test_get_audio_test_data(link, test_request.bits.TEST_AUDIO_DISABLED_VIDEO);
2802                 test_response.bits.ACK = 1;
2803         }
2804
2805         if (test_request.bits.PHY_TEST_PATTERN) {
2806                 dp_test_send_phy_test_pattern(link);
2807                 test_response.bits.ACK = 1;
2808         }
2809
2810         /* send request acknowledgment */
2811         if (test_response.bits.ACK)
2812                 core_link_write_dpcd(
2813                         link,
2814                         DP_TEST_RESPONSE,
2815                         &test_response.raw,
2816                         sizeof(test_response));
2817 }
2818
2819 bool dc_link_handle_hpd_rx_irq(struct dc_link *link, union hpd_irq_data *out_hpd_irq_dpcd_data, bool *out_link_loss)
2820 {
2821         union hpd_irq_data hpd_irq_dpcd_data = { { { {0} } } };
2822         union device_service_irq device_service_clear = { { 0 } };
2823         enum dc_status result;
2824         bool status = false;
2825         struct pipe_ctx *pipe_ctx;
2826         struct dc_link_settings previous_link_settings;
2827         int i;
2828
2829         if (out_link_loss)
2830                 *out_link_loss = false;
2831         /* For use cases related to down stream connection status change,
2832          * PSR and device auto test, refer to function handle_sst_hpd_irq
2833          * in DAL2.1*/
2834
2835         DC_LOG_HW_HPD_IRQ("%s: Got short pulse HPD on link %d\n",
2836                 __func__, link->link_index);
2837
2838
2839          /* All the "handle_hpd_irq_xxx()" methods
2840                  * should be called only after
2841                  * dal_dpsst_ls_read_hpd_irq_data
2842                  * Order of calls is important too
2843                  */
2844         result = read_hpd_rx_irq_data(link, &hpd_irq_dpcd_data);
2845         if (out_hpd_irq_dpcd_data)
2846                 *out_hpd_irq_dpcd_data = hpd_irq_dpcd_data;
2847
2848         if (result != DC_OK) {
2849                 DC_LOG_HW_HPD_IRQ("%s: DPCD read failed to obtain irq data\n",
2850                         __func__);
2851                 return false;
2852         }
2853
2854         if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
2855                 device_service_clear.bits.AUTOMATED_TEST = 1;
2856                 core_link_write_dpcd(
2857                         link,
2858                         DP_DEVICE_SERVICE_IRQ_VECTOR,
2859                         &device_service_clear.raw,
2860                         sizeof(device_service_clear.raw));
2861                 device_service_clear.raw = 0;
2862                 handle_automated_test(link);
2863                 return false;
2864         }
2865
2866         if (!allow_hpd_rx_irq(link)) {
2867                 DC_LOG_HW_HPD_IRQ("%s: skipping HPD handling on %d\n",
2868                         __func__, link->link_index);
2869                 return false;
2870         }
2871
2872         if (handle_hpd_irq_psr_sink(link))
2873                 /* PSR-related error was detected and handled */
2874                 return true;
2875
2876         /* If PSR-related error handled, Main link may be off,
2877          * so do not handle as a normal sink status change interrupt.
2878          */
2879
2880         if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY)
2881                 return true;
2882
2883         /* check if we have MST msg and return since we poll for it */
2884         if (hpd_irq_dpcd_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY)
2885                 return false;
2886
2887         /* For now we only handle 'Downstream port status' case.
2888          * If we got sink count changed it means
2889          * Downstream port status changed,
2890          * then DM should call DC to do the detection.
2891          * NOTE: Do not handle link loss on eDP since it is internal link*/
2892         if ((link->connector_signal != SIGNAL_TYPE_EDP) &&
2893                 hpd_rx_irq_check_link_loss_status(
2894                         link,
2895                         &hpd_irq_dpcd_data)) {
2896                 /* Connectivity log: link loss */
2897                 CONN_DATA_LINK_LOSS(link,
2898                                         hpd_irq_dpcd_data.raw,
2899                                         sizeof(hpd_irq_dpcd_data),
2900                                         "Status: ");
2901
2902                 for (i = 0; i < MAX_PIPES; i++) {
2903                         pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
2904                         if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->link == link)
2905                                 link->dc->hwss.blank_stream(pipe_ctx);
2906                 }
2907
2908                 for (i = 0; i < MAX_PIPES; i++) {
2909                         pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
2910                         if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->link == link)
2911                                 break;
2912                 }
2913
2914                 if (pipe_ctx == NULL || pipe_ctx->stream == NULL)
2915                         return false;
2916
2917                 previous_link_settings = link->cur_link_settings;
2918
2919                 perform_link_training_with_retries(&previous_link_settings,
2920                         true, LINK_TRAINING_ATTEMPTS,
2921                         pipe_ctx,
2922                         pipe_ctx->stream->signal);
2923
2924                 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
2925                         dc_link_reallocate_mst_payload(link);
2926
2927                 for (i = 0; i < MAX_PIPES; i++) {
2928                         pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
2929                         if (pipe_ctx && pipe_ctx->stream && pipe_ctx->stream->link == link)
2930                                 link->dc->hwss.unblank_stream(pipe_ctx, &previous_link_settings);
2931                 }
2932
2933                 status = false;
2934                 if (out_link_loss)
2935                         *out_link_loss = true;
2936         }
2937
2938         if (link->type == dc_connection_active_dongle &&
2939                 hpd_irq_dpcd_data.bytes.sink_cnt.bits.SINK_COUNT
2940                         != link->dpcd_sink_count)
2941                 status = true;
2942
2943         /* reasons for HPD RX:
2944          * 1. Link Loss - ie Re-train the Link
2945          * 2. MST sideband message
2946          * 3. Automated Test - ie. Internal Commit
2947          * 4. CP (copy protection) - (not interesting for DM???)
2948          * 5. DRR
2949          * 6. Downstream Port status changed
2950          * -ie. Detect - this the only one
2951          * which is interesting for DM because
2952          * it must call dc_link_detect.
2953          */
2954         return status;
2955 }
2956
2957 /*query dpcd for version and mst cap addresses*/
2958 bool is_mst_supported(struct dc_link *link)
2959 {
2960         bool mst          = false;
2961         enum dc_status st = DC_OK;
2962         union dpcd_rev rev;
2963         union mstm_cap cap;
2964
2965         if (link->preferred_training_settings.mst_enable &&
2966                 *link->preferred_training_settings.mst_enable == false) {
2967                 return false;
2968         }
2969
2970         rev.raw  = 0;
2971         cap.raw  = 0;
2972
2973         st = core_link_read_dpcd(link, DP_DPCD_REV, &rev.raw,
2974                         sizeof(rev));
2975
2976         if (st == DC_OK && rev.raw >= DPCD_REV_12) {
2977
2978                 st = core_link_read_dpcd(link, DP_MSTM_CAP,
2979                                 &cap.raw, sizeof(cap));
2980                 if (st == DC_OK && cap.bits.MST_CAP == 1)
2981                         mst = true;
2982         }
2983         return mst;
2984
2985 }
2986
2987 bool is_dp_active_dongle(const struct dc_link *link)
2988 {
2989         return link->dpcd_caps.is_branch_dev;
2990 }
2991
2992 static int translate_dpcd_max_bpc(enum dpcd_downstream_port_max_bpc bpc)
2993 {
2994         switch (bpc) {
2995         case DOWN_STREAM_MAX_8BPC:
2996                 return 8;
2997         case DOWN_STREAM_MAX_10BPC:
2998                 return 10;
2999         case DOWN_STREAM_MAX_12BPC:
3000                 return 12;
3001         case DOWN_STREAM_MAX_16BPC:
3002                 return 16;
3003         default:
3004                 break;
3005         }
3006
3007         return -1;
3008 }
3009
3010 static void read_dp_device_vendor_id(struct dc_link *link)
3011 {
3012         struct dp_device_vendor_id dp_id;
3013
3014         /* read IEEE branch device id */
3015         core_link_read_dpcd(
3016                 link,
3017                 DP_BRANCH_OUI,
3018                 (uint8_t *)&dp_id,
3019                 sizeof(dp_id));
3020
3021         link->dpcd_caps.branch_dev_id =
3022                 (dp_id.ieee_oui[0] << 16) +
3023                 (dp_id.ieee_oui[1] << 8) +
3024                 dp_id.ieee_oui[2];
3025
3026         memmove(
3027                 link->dpcd_caps.branch_dev_name,
3028                 dp_id.ieee_device_id,
3029                 sizeof(dp_id.ieee_device_id));
3030 }
3031
3032
3033
3034 static void get_active_converter_info(
3035         uint8_t data, struct dc_link *link)
3036 {
3037         union dp_downstream_port_present ds_port = { .byte = data };
3038         memset(&link->dpcd_caps.dongle_caps, 0, sizeof(link->dpcd_caps.dongle_caps));
3039
3040         /* decode converter info*/
3041         if (!ds_port.fields.PORT_PRESENT) {
3042                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
3043                 ddc_service_set_dongle_type(link->ddc,
3044                                 link->dpcd_caps.dongle_type);
3045                 link->dpcd_caps.is_branch_dev = false;
3046                 return;
3047         }
3048
3049         /* DPCD 0x5 bit 0 = 1, it indicate it's branch device */
3050         if (ds_port.fields.PORT_TYPE == DOWNSTREAM_DP) {
3051                 link->dpcd_caps.is_branch_dev = false;
3052         }
3053
3054         else {
3055                 link->dpcd_caps.is_branch_dev = ds_port.fields.PORT_PRESENT;
3056         }
3057
3058         switch (ds_port.fields.PORT_TYPE) {
3059         case DOWNSTREAM_VGA:
3060                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_VGA_CONVERTER;
3061                 break;
3062         case DOWNSTREAM_DVI_HDMI_DP_PLUS_PLUS:
3063                 /* At this point we don't know is it DVI or HDMI or DP++,
3064                  * assume DVI.*/
3065                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_DVI_CONVERTER;
3066                 break;
3067         default:
3068                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
3069                 break;
3070         }
3071
3072         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_11) {
3073                 uint8_t det_caps[16]; /* CTS 4.2.2.7 expects source to read Detailed Capabilities Info : 00080h-0008F.*/
3074                 union dwnstream_port_caps_byte0 *port_caps =
3075                         (union dwnstream_port_caps_byte0 *)det_caps;
3076                 core_link_read_dpcd(link, DP_DOWNSTREAM_PORT_0,
3077                                 det_caps, sizeof(det_caps));
3078
3079                 switch (port_caps->bits.DWN_STRM_PORTX_TYPE) {
3080                 /*Handle DP case as DONGLE_NONE*/
3081                 case DOWN_STREAM_DETAILED_DP:
3082                         link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
3083                         break;
3084                 case DOWN_STREAM_DETAILED_VGA:
3085                         link->dpcd_caps.dongle_type =
3086                                 DISPLAY_DONGLE_DP_VGA_CONVERTER;
3087                         break;
3088                 case DOWN_STREAM_DETAILED_DVI:
3089                         link->dpcd_caps.dongle_type =
3090                                 DISPLAY_DONGLE_DP_DVI_CONVERTER;
3091                         break;
3092                 case DOWN_STREAM_DETAILED_HDMI:
3093                 case DOWN_STREAM_DETAILED_DP_PLUS_PLUS:
3094                         /*Handle DP++ active converter case, process DP++ case as HDMI case according DP1.4 spec*/
3095                         link->dpcd_caps.dongle_type =
3096                                 DISPLAY_DONGLE_DP_HDMI_CONVERTER;
3097
3098                         link->dpcd_caps.dongle_caps.dongle_type = link->dpcd_caps.dongle_type;
3099                         if (ds_port.fields.DETAILED_CAPS) {
3100
3101                                 union dwnstream_port_caps_byte3_hdmi
3102                                         hdmi_caps = {.raw = det_caps[3] };
3103                                 union dwnstream_port_caps_byte2
3104                                         hdmi_color_caps = {.raw = det_caps[2] };
3105                                 link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz =
3106                                         det_caps[1] * 2500;
3107
3108                                 link->dpcd_caps.dongle_caps.is_dp_hdmi_s3d_converter =
3109                                         hdmi_caps.bits.FRAME_SEQ_TO_FRAME_PACK;
3110                                 /*YCBCR capability only for HDMI case*/
3111                                 if (port_caps->bits.DWN_STRM_PORTX_TYPE
3112                                                 == DOWN_STREAM_DETAILED_HDMI) {
3113                                         link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_pass_through =
3114                                                         hdmi_caps.bits.YCrCr422_PASS_THROUGH;
3115                                         link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_pass_through =
3116                                                         hdmi_caps.bits.YCrCr420_PASS_THROUGH;
3117                                         link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_converter =
3118                                                         hdmi_caps.bits.YCrCr422_CONVERSION;
3119                                         link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_converter =
3120                                                         hdmi_caps.bits.YCrCr420_CONVERSION;
3121                                 }
3122
3123                                 link->dpcd_caps.dongle_caps.dp_hdmi_max_bpc =
3124                                         translate_dpcd_max_bpc(
3125                                                 hdmi_color_caps.bits.MAX_BITS_PER_COLOR_COMPONENT);
3126
3127                                 if (link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz != 0)
3128                                         link->dpcd_caps.dongle_caps.extendedCapValid = true;
3129                         }
3130
3131                         break;
3132                 }
3133         }
3134
3135         ddc_service_set_dongle_type(link->ddc, link->dpcd_caps.dongle_type);
3136
3137         {
3138                 struct dp_sink_hw_fw_revision dp_hw_fw_revision;
3139
3140                 core_link_read_dpcd(
3141                         link,
3142                         DP_BRANCH_REVISION_START,
3143                         (uint8_t *)&dp_hw_fw_revision,
3144                         sizeof(dp_hw_fw_revision));
3145
3146                 link->dpcd_caps.branch_hw_revision =
3147                         dp_hw_fw_revision.ieee_hw_rev;
3148
3149                 memmove(
3150                         link->dpcd_caps.branch_fw_revision,
3151                         dp_hw_fw_revision.ieee_fw_rev,
3152                         sizeof(dp_hw_fw_revision.ieee_fw_rev));
3153         }
3154 }
3155
3156 static void dp_wa_power_up_0010FA(struct dc_link *link, uint8_t *dpcd_data,
3157                 int length)
3158 {
3159         int retry = 0;
3160
3161         if (!link->dpcd_caps.dpcd_rev.raw) {
3162                 do {
3163                         dp_receiver_power_ctrl(link, true);
3164                         core_link_read_dpcd(link, DP_DPCD_REV,
3165                                                         dpcd_data, length);
3166                         link->dpcd_caps.dpcd_rev.raw = dpcd_data[
3167                                 DP_DPCD_REV -
3168                                 DP_DPCD_REV];
3169                 } while (retry++ < 4 && !link->dpcd_caps.dpcd_rev.raw);
3170         }
3171
3172         if (link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER) {
3173                 switch (link->dpcd_caps.branch_dev_id) {
3174                 /* 0010FA active dongles (DP-VGA, DP-DLDVI converters) power down
3175                  * all internal circuits including AUX communication preventing
3176                  * reading DPCD table and EDID (spec violation).
3177                  * Encoder will skip DP RX power down on disable_output to
3178                  * keep receiver powered all the time.*/
3179                 case DP_BRANCH_DEVICE_ID_0010FA:
3180                 case DP_BRANCH_DEVICE_ID_0080E1:
3181                 case DP_BRANCH_DEVICE_ID_00E04C:
3182                         link->wa_flags.dp_keep_receiver_powered = true;
3183                         break;
3184
3185                 /* TODO: May need work around for other dongles. */
3186                 default:
3187                         link->wa_flags.dp_keep_receiver_powered = false;
3188                         break;
3189                 }
3190         } else
3191                 link->wa_flags.dp_keep_receiver_powered = false;
3192 }
3193
3194 /* Read additional sink caps defined in source specific DPCD area
3195  * This function currently only reads from SinkCapability address (DP_SOURCE_SINK_CAP)
3196  */
3197 static bool dpcd_read_sink_ext_caps(struct dc_link *link)
3198 {
3199         uint8_t dpcd_data;
3200
3201         if (!link)
3202                 return false;
3203
3204         if (core_link_read_dpcd(link, DP_SOURCE_SINK_CAP, &dpcd_data, 1) != DC_OK)
3205                 return false;
3206
3207         link->dpcd_sink_ext_caps.raw = dpcd_data;
3208         return true;
3209 }
3210
3211 static bool retrieve_link_cap(struct dc_link *link)
3212 {
3213         /* DP_ADAPTER_CAP - DP_DPCD_REV + 1 == 16 and also DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT + 1 == 16,
3214          * which means size 16 will be good for both of those DPCD register block reads
3215          */
3216         uint8_t dpcd_data[16];
3217         uint8_t lttpr_dpcd_data[6];
3218
3219         /*Only need to read 1 byte starting from DP_DPRX_FEATURE_ENUMERATION_LIST.
3220          */
3221         uint8_t dpcd_dprx_data = '\0';
3222         uint8_t dpcd_power_state = '\0';
3223
3224         struct dp_device_vendor_id sink_id;
3225         union down_stream_port_count down_strm_port_count;
3226         union edp_configuration_cap edp_config_cap;
3227         union dp_downstream_port_present ds_port = { 0 };
3228         enum dc_status status = DC_ERROR_UNEXPECTED;
3229         uint32_t read_dpcd_retry_cnt = 3;
3230         int i;
3231         struct dp_sink_hw_fw_revision dp_hw_fw_revision;
3232
3233         /* Set default timeout to 3.2ms and read LTTPR capabilities */
3234         bool ext_timeout_support = link->dc->caps.extended_aux_timeout_support &&
3235                         !link->dc->config.disable_extended_timeout_support;
3236
3237         link->is_lttpr_mode_transparent = true;
3238
3239         if (ext_timeout_support) {
3240                 dc_link_aux_configure_timeout(link->ddc,
3241                                         LINK_AUX_DEFAULT_EXTENDED_TIMEOUT_PERIOD);
3242         }
3243
3244         memset(dpcd_data, '\0', sizeof(dpcd_data));
3245         memset(lttpr_dpcd_data, '\0', sizeof(lttpr_dpcd_data));
3246         memset(&down_strm_port_count,
3247                 '\0', sizeof(union down_stream_port_count));
3248         memset(&edp_config_cap, '\0',
3249                 sizeof(union edp_configuration_cap));
3250
3251         status = core_link_read_dpcd(link, DP_SET_POWER,
3252                                 &dpcd_power_state, sizeof(dpcd_power_state));
3253
3254         /* Delay 1 ms if AUX CH is in power down state. Based on spec
3255          * section 2.3.1.2, if AUX CH may be powered down due to
3256          * write to DPCD 600h = 2. Sink AUX CH is monitoring differential
3257          * signal and may need up to 1 ms before being able to reply.
3258          */
3259         if (status != DC_OK || dpcd_power_state == DP_SET_POWER_D3)
3260                 udelay(1000);
3261
3262         for (i = 0; i < read_dpcd_retry_cnt; i++) {
3263                 status = core_link_read_dpcd(
3264                                 link,
3265                                 DP_DPCD_REV,
3266                                 dpcd_data,
3267                                 sizeof(dpcd_data));
3268                 if (status == DC_OK)
3269                         break;
3270         }
3271
3272         if (status != DC_OK) {
3273                 dm_error("%s: Read dpcd data failed.\n", __func__);
3274                 return false;
3275         }
3276
3277         if (ext_timeout_support) {
3278
3279                 status = core_link_read_dpcd(
3280                                 link,
3281                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
3282                                 lttpr_dpcd_data,
3283                                 sizeof(lttpr_dpcd_data));
3284
3285                 link->dpcd_caps.lttpr_caps.revision.raw =
3286                                 lttpr_dpcd_data[DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV -
3287                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3288
3289                 link->dpcd_caps.lttpr_caps.max_link_rate =
3290                                 lttpr_dpcd_data[DP_MAX_LINK_RATE_PHY_REPEATER -
3291                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3292
3293                 link->dpcd_caps.lttpr_caps.phy_repeater_cnt =
3294                                 lttpr_dpcd_data[DP_PHY_REPEATER_CNT -
3295                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3296
3297                 link->dpcd_caps.lttpr_caps.max_lane_count =
3298                                 lttpr_dpcd_data[DP_MAX_LANE_COUNT_PHY_REPEATER -
3299                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3300
3301                 link->dpcd_caps.lttpr_caps.mode =
3302                                 lttpr_dpcd_data[DP_PHY_REPEATER_MODE -
3303                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3304
3305                 link->dpcd_caps.lttpr_caps.max_ext_timeout =
3306                                 lttpr_dpcd_data[DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT -
3307                                                                 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3308
3309                 if (link->dpcd_caps.lttpr_caps.phy_repeater_cnt > 0 &&
3310                                 link->dpcd_caps.lttpr_caps.max_lane_count > 0 &&
3311                                 link->dpcd_caps.lttpr_caps.max_lane_count <= 4 &&
3312                                 link->dpcd_caps.lttpr_caps.revision.raw >= 0x14) {
3313                         link->is_lttpr_mode_transparent = false;
3314                 } else {
3315                         /*No lttpr reset timeout to its default value*/
3316                         link->is_lttpr_mode_transparent = true;
3317                         dc_link_aux_configure_timeout(link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
3318                 }
3319
3320                 CONN_DATA_DETECT(link, lttpr_dpcd_data, sizeof(lttpr_dpcd_data), "LTTPR Caps: ");
3321         }
3322
3323         {
3324                 union training_aux_rd_interval aux_rd_interval;
3325
3326                 aux_rd_interval.raw =
3327                         dpcd_data[DP_TRAINING_AUX_RD_INTERVAL];
3328
3329                 link->dpcd_caps.ext_receiver_cap_field_present =
3330                                 aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1;
3331
3332                 if (aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1) {
3333                         uint8_t ext_cap_data[16];
3334
3335                         memset(ext_cap_data, '\0', sizeof(ext_cap_data));
3336                         for (i = 0; i < read_dpcd_retry_cnt; i++) {
3337                                 status = core_link_read_dpcd(
3338                                 link,
3339                                 DP_DP13_DPCD_REV,
3340                                 ext_cap_data,
3341                                 sizeof(ext_cap_data));
3342                                 if (status == DC_OK) {
3343                                         memcpy(dpcd_data, ext_cap_data, sizeof(dpcd_data));
3344                                         break;
3345                                 }
3346                         }
3347                         if (status != DC_OK)
3348                                 dm_error("%s: Read extend caps data failed, use cap from dpcd 0.\n", __func__);
3349                 }
3350         }
3351
3352         link->dpcd_caps.dpcd_rev.raw =
3353                         dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
3354
3355         if (link->dpcd_caps.dpcd_rev.raw >= 0x14) {
3356                 for (i = 0; i < read_dpcd_retry_cnt; i++) {
3357                         status = core_link_read_dpcd(
3358                                         link,
3359                                         DP_DPRX_FEATURE_ENUMERATION_LIST,
3360                                         &dpcd_dprx_data,
3361                                         sizeof(dpcd_dprx_data));
3362                         if (status == DC_OK)
3363                                 break;
3364                 }
3365
3366                 link->dpcd_caps.dprx_feature.raw = dpcd_dprx_data;
3367
3368                 if (status != DC_OK)
3369                         dm_error("%s: Read DPRX caps data failed.\n", __func__);
3370         }
3371
3372         else {
3373                 link->dpcd_caps.dprx_feature.raw = 0;
3374         }
3375
3376
3377         /* Error condition checking...
3378          * It is impossible for Sink to report Max Lane Count = 0.
3379          * It is possible for Sink to report Max Link Rate = 0, if it is
3380          * an eDP device that is reporting specialized link rates in the
3381          * SUPPORTED_LINK_RATE table.
3382          */
3383         if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0)
3384                 return false;
3385
3386         ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
3387                                  DP_DPCD_REV];
3388
3389         read_dp_device_vendor_id(link);
3390
3391         get_active_converter_info(ds_port.byte, link);
3392
3393         dp_wa_power_up_0010FA(link, dpcd_data, sizeof(dpcd_data));
3394
3395         down_strm_port_count.raw = dpcd_data[DP_DOWN_STREAM_PORT_COUNT -
3396                                  DP_DPCD_REV];
3397
3398         link->dpcd_caps.allow_invalid_MSA_timing_param =
3399                 down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;
3400
3401         link->dpcd_caps.max_ln_count.raw = dpcd_data[
3402                 DP_MAX_LANE_COUNT - DP_DPCD_REV];
3403
3404         link->dpcd_caps.max_down_spread.raw = dpcd_data[
3405                 DP_MAX_DOWNSPREAD - DP_DPCD_REV];
3406
3407         link->reported_link_cap.lane_count =
3408                 link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;
3409         link->reported_link_cap.link_rate = dpcd_data[
3410                 DP_MAX_LINK_RATE - DP_DPCD_REV];
3411         link->reported_link_cap.link_spread =
3412                 link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?
3413                 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
3414
3415         edp_config_cap.raw = dpcd_data[
3416                 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
3417         link->dpcd_caps.panel_mode_edp =
3418                 edp_config_cap.bits.ALT_SCRAMBLER_RESET;
3419         link->dpcd_caps.dpcd_display_control_capable =
3420                 edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE;
3421
3422         link->test_pattern_enabled = false;
3423         link->compliance_test_state.raw = 0;
3424
3425         /* read sink count */
3426         core_link_read_dpcd(link,
3427                         DP_SINK_COUNT,
3428                         &link->dpcd_caps.sink_count.raw,
3429                         sizeof(link->dpcd_caps.sink_count.raw));
3430
3431         /* read sink ieee oui */
3432         core_link_read_dpcd(link,
3433                         DP_SINK_OUI,
3434                         (uint8_t *)(&sink_id),
3435                         sizeof(sink_id));
3436
3437         link->dpcd_caps.sink_dev_id =
3438                         (sink_id.ieee_oui[0] << 16) +
3439                         (sink_id.ieee_oui[1] << 8) +
3440                         (sink_id.ieee_oui[2]);
3441
3442         memmove(
3443                 link->dpcd_caps.sink_dev_id_str,
3444                 sink_id.ieee_device_id,
3445                 sizeof(sink_id.ieee_device_id));
3446
3447         /* Quirk Apple MBP 2017 15" Retina panel: Wrong DP_MAX_LINK_RATE */
3448         {
3449                 uint8_t str_mbp_2017[] = { 101, 68, 21, 101, 98, 97 };
3450
3451                 if ((link->dpcd_caps.sink_dev_id == 0x0010fa) &&
3452                     !memcmp(link->dpcd_caps.sink_dev_id_str, str_mbp_2017,
3453                             sizeof(str_mbp_2017))) {
3454                         link->reported_link_cap.link_rate = 0x0c;
3455                 }
3456         }
3457
3458         core_link_read_dpcd(
3459                 link,
3460                 DP_SINK_HW_REVISION_START,
3461                 (uint8_t *)&dp_hw_fw_revision,
3462                 sizeof(dp_hw_fw_revision));
3463
3464         link->dpcd_caps.sink_hw_revision =
3465                 dp_hw_fw_revision.ieee_hw_rev;
3466
3467         memmove(
3468                 link->dpcd_caps.sink_fw_revision,
3469                 dp_hw_fw_revision.ieee_fw_rev,
3470                 sizeof(dp_hw_fw_revision.ieee_fw_rev));
3471
3472         memset(&link->dpcd_caps.dsc_caps, '\0',
3473                         sizeof(link->dpcd_caps.dsc_caps));
3474         memset(&link->dpcd_caps.fec_cap, '\0', sizeof(link->dpcd_caps.fec_cap));
3475         /* Read DSC and FEC sink capabilities if DP revision is 1.4 and up */
3476         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14) {
3477                 status = core_link_read_dpcd(
3478                                 link,
3479                                 DP_FEC_CAPABILITY,
3480                                 &link->dpcd_caps.fec_cap.raw,
3481                                 sizeof(link->dpcd_caps.fec_cap.raw));
3482                 status = core_link_read_dpcd(
3483                                 link,
3484                                 DP_DSC_SUPPORT,
3485                                 link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
3486                                 sizeof(link->dpcd_caps.dsc_caps.dsc_basic_caps.raw));
3487                 status = core_link_read_dpcd(
3488                                 link,
3489                                 DP_DSC_BRANCH_OVERALL_THROUGHPUT_0,
3490                                 link->dpcd_caps.dsc_caps.dsc_ext_caps.raw,
3491                                 sizeof(link->dpcd_caps.dsc_caps.dsc_ext_caps.raw));
3492         }
3493
3494         if (!dpcd_read_sink_ext_caps(link))
3495                 link->dpcd_sink_ext_caps.raw = 0;
3496
3497         /* Connectivity log: detection */
3498         CONN_DATA_DETECT(link, dpcd_data, sizeof(dpcd_data), "Rx Caps: ");
3499
3500         return true;
3501 }
3502
3503 bool dp_overwrite_extended_receiver_cap(struct dc_link *link)
3504 {
3505         uint8_t dpcd_data[16];
3506         uint32_t read_dpcd_retry_cnt = 3;
3507         enum dc_status status = DC_ERROR_UNEXPECTED;
3508         union dp_downstream_port_present ds_port = { 0 };
3509         union down_stream_port_count down_strm_port_count;
3510         union edp_configuration_cap edp_config_cap;
3511
3512         int i;
3513
3514         for (i = 0; i < read_dpcd_retry_cnt; i++) {
3515                 status = core_link_read_dpcd(
3516                                 link,
3517                                 DP_DPCD_REV,
3518                                 dpcd_data,
3519                                 sizeof(dpcd_data));
3520                 if (status == DC_OK)
3521                         break;
3522         }
3523
3524         link->dpcd_caps.dpcd_rev.raw =
3525                 dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
3526
3527         if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0)
3528                 return false;
3529
3530         ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
3531                         DP_DPCD_REV];
3532
3533         get_active_converter_info(ds_port.byte, link);
3534
3535         down_strm_port_count.raw = dpcd_data[DP_DOWN_STREAM_PORT_COUNT -
3536                         DP_DPCD_REV];
3537
3538         link->dpcd_caps.allow_invalid_MSA_timing_param =
3539                 down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;
3540
3541         link->dpcd_caps.max_ln_count.raw = dpcd_data[
3542                 DP_MAX_LANE_COUNT - DP_DPCD_REV];
3543
3544         link->dpcd_caps.max_down_spread.raw = dpcd_data[
3545                 DP_MAX_DOWNSPREAD - DP_DPCD_REV];
3546
3547         link->reported_link_cap.lane_count =
3548                 link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;
3549         link->reported_link_cap.link_rate = dpcd_data[
3550                 DP_MAX_LINK_RATE - DP_DPCD_REV];
3551         link->reported_link_cap.link_spread =
3552                 link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?
3553                 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
3554
3555         edp_config_cap.raw = dpcd_data[
3556                 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
3557         link->dpcd_caps.panel_mode_edp =
3558                 edp_config_cap.bits.ALT_SCRAMBLER_RESET;
3559         link->dpcd_caps.dpcd_display_control_capable =
3560                 edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE;
3561
3562         return true;
3563 }
3564
3565 bool detect_dp_sink_caps(struct dc_link *link)
3566 {
3567         return retrieve_link_cap(link);
3568
3569         /* dc init_hw has power encoder using default
3570          * signal for connector. For native DP, no
3571          * need to power up encoder again. If not native
3572          * DP, hw_init may need check signal or power up
3573          * encoder here.
3574          */
3575         /* TODO save sink caps in link->sink */
3576 }
3577
3578 enum dc_link_rate linkRateInKHzToLinkRateMultiplier(uint32_t link_rate_in_khz)
3579 {
3580         enum dc_link_rate link_rate;
3581         // LinkRate is normally stored as a multiplier of 0.27 Gbps per lane. Do the translation.
3582         switch (link_rate_in_khz) {
3583         case 1620000:
3584                 link_rate = LINK_RATE_LOW;              // Rate_1 (RBR)         - 1.62 Gbps/Lane
3585                 break;
3586         case 2160000:
3587                 link_rate = LINK_RATE_RATE_2;   // Rate_2                       - 2.16 Gbps/Lane
3588                 break;
3589         case 2430000:
3590                 link_rate = LINK_RATE_RATE_3;   // Rate_3                       - 2.43 Gbps/Lane
3591                 break;
3592         case 2700000:
3593                 link_rate = LINK_RATE_HIGH;             // Rate_4 (HBR)         - 2.70 Gbps/Lane
3594                 break;
3595         case 3240000:
3596                 link_rate = LINK_RATE_RBR2;             // Rate_5 (RBR2)        - 3.24 Gbps/Lane
3597                 break;
3598         case 4320000:
3599                 link_rate = LINK_RATE_RATE_6;   // Rate_6                       - 4.32 Gbps/Lane
3600                 break;
3601         case 5400000:
3602                 link_rate = LINK_RATE_HIGH2;    // Rate_7 (HBR2)        - 5.40 Gbps/Lane
3603                 break;
3604         case 8100000:
3605                 link_rate = LINK_RATE_HIGH3;    // Rate_8 (HBR3)        - 8.10 Gbps/Lane
3606                 break;
3607         default:
3608                 link_rate = LINK_RATE_UNKNOWN;
3609                 break;
3610         }
3611         return link_rate;
3612 }
3613
3614 void detect_edp_sink_caps(struct dc_link *link)
3615 {
3616         uint8_t supported_link_rates[16];
3617         uint32_t entry;
3618         uint32_t link_rate_in_khz;
3619         enum dc_link_rate link_rate = LINK_RATE_UNKNOWN;
3620
3621         retrieve_link_cap(link);
3622         link->dpcd_caps.edp_supported_link_rates_count = 0;
3623         memset(supported_link_rates, 0, sizeof(supported_link_rates));
3624
3625         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14 &&
3626                         (link->dc->config.optimize_edp_link_rate ||
3627                         link->reported_link_cap.link_rate == LINK_RATE_UNKNOWN)) {
3628                 // Read DPCD 00010h - 0001Fh 16 bytes at one shot
3629                 core_link_read_dpcd(link, DP_SUPPORTED_LINK_RATES,
3630                                                         supported_link_rates, sizeof(supported_link_rates));
3631
3632                 for (entry = 0; entry < 16; entry += 2) {
3633                         // DPCD register reports per-lane link rate = 16-bit link rate capability
3634                         // value X 200 kHz. Need multiplier to find link rate in kHz.
3635                         link_rate_in_khz = (supported_link_rates[entry+1] * 0x100 +
3636                                                                                 supported_link_rates[entry]) * 200;
3637
3638                         if (link_rate_in_khz != 0) {
3639                                 link_rate = linkRateInKHzToLinkRateMultiplier(link_rate_in_khz);
3640                                 link->dpcd_caps.edp_supported_link_rates[link->dpcd_caps.edp_supported_link_rates_count] = link_rate;
3641                                 link->dpcd_caps.edp_supported_link_rates_count++;
3642
3643                                 if (link->reported_link_cap.link_rate < link_rate)
3644                                         link->reported_link_cap.link_rate = link_rate;
3645                         }
3646                 }
3647         }
3648         link->verified_link_cap = link->reported_link_cap;
3649
3650         dc_link_set_default_brightness_aux(link);
3651 }
3652
3653 void dc_link_dp_enable_hpd(const struct dc_link *link)
3654 {
3655         struct link_encoder *encoder = link->link_enc;
3656
3657         if (encoder != NULL && encoder->funcs->enable_hpd != NULL)
3658                 encoder->funcs->enable_hpd(encoder);
3659 }
3660
3661 void dc_link_dp_disable_hpd(const struct dc_link *link)
3662 {
3663         struct link_encoder *encoder = link->link_enc;
3664
3665         if (encoder != NULL && encoder->funcs->enable_hpd != NULL)
3666                 encoder->funcs->disable_hpd(encoder);
3667 }
3668
3669 static bool is_dp_phy_pattern(enum dp_test_pattern test_pattern)
3670 {
3671         if ((DP_TEST_PATTERN_PHY_PATTERN_BEGIN <= test_pattern &&
3672                         test_pattern <= DP_TEST_PATTERN_PHY_PATTERN_END) ||
3673                         test_pattern == DP_TEST_PATTERN_VIDEO_MODE)
3674                 return true;
3675         else
3676                 return false;
3677 }
3678
3679 static void set_crtc_test_pattern(struct dc_link *link,
3680                                 struct pipe_ctx *pipe_ctx,
3681                                 enum dp_test_pattern test_pattern,
3682                                 enum dp_test_pattern_color_space test_pattern_color_space)
3683 {
3684         enum controller_dp_test_pattern controller_test_pattern;
3685         enum dc_color_depth color_depth = pipe_ctx->
3686                 stream->timing.display_color_depth;
3687         struct bit_depth_reduction_params params;
3688         struct output_pixel_processor *opp = pipe_ctx->stream_res.opp;
3689         int width = pipe_ctx->stream->timing.h_addressable +
3690                 pipe_ctx->stream->timing.h_border_left +
3691                 pipe_ctx->stream->timing.h_border_right;
3692         int height = pipe_ctx->stream->timing.v_addressable +
3693                 pipe_ctx->stream->timing.v_border_bottom +
3694                 pipe_ctx->stream->timing.v_border_top;
3695
3696         memset(&params, 0, sizeof(params));
3697
3698         switch (test_pattern) {
3699         case DP_TEST_PATTERN_COLOR_SQUARES:
3700                 controller_test_pattern =
3701                                 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES;
3702         break;
3703         case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
3704                 controller_test_pattern =
3705                                 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA;
3706         break;
3707         case DP_TEST_PATTERN_VERTICAL_BARS:
3708                 controller_test_pattern =
3709                                 CONTROLLER_DP_TEST_PATTERN_VERTICALBARS;
3710         break;
3711         case DP_TEST_PATTERN_HORIZONTAL_BARS:
3712                 controller_test_pattern =
3713                                 CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS;
3714         break;
3715         case DP_TEST_PATTERN_COLOR_RAMP:
3716                 controller_test_pattern =
3717                                 CONTROLLER_DP_TEST_PATTERN_COLORRAMP;
3718         break;
3719         default:
3720                 controller_test_pattern =
3721                                 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE;
3722         break;
3723         }
3724
3725         switch (test_pattern) {
3726         case DP_TEST_PATTERN_COLOR_SQUARES:
3727         case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
3728         case DP_TEST_PATTERN_VERTICAL_BARS:
3729         case DP_TEST_PATTERN_HORIZONTAL_BARS:
3730         case DP_TEST_PATTERN_COLOR_RAMP:
3731         {
3732                 /* disable bit depth reduction */
3733                 pipe_ctx->stream->bit_depth_params = params;
3734                 opp->funcs->opp_program_bit_depth_reduction(opp, &params);
3735                 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
3736                         pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
3737                                 controller_test_pattern, color_depth);
3738                 else if (opp->funcs->opp_set_disp_pattern_generator) {
3739                         struct pipe_ctx *odm_pipe;
3740                         enum controller_dp_color_space controller_color_space;
3741                         int opp_cnt = 1;
3742                         int offset = 0;
3743                         int dpg_width = width;
3744
3745                         switch (test_pattern_color_space) {
3746                         case DP_TEST_PATTERN_COLOR_SPACE_RGB:
3747                                 controller_color_space = CONTROLLER_DP_COLOR_SPACE_RGB;
3748                                 break;
3749                         case DP_TEST_PATTERN_COLOR_SPACE_YCBCR601:
3750                                 controller_color_space = CONTROLLER_DP_COLOR_SPACE_YCBCR601;
3751                                 break;
3752                         case DP_TEST_PATTERN_COLOR_SPACE_YCBCR709:
3753                                 controller_color_space = CONTROLLER_DP_COLOR_SPACE_YCBCR709;
3754                                 break;
3755                         case DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED:
3756                         default:
3757                                 controller_color_space = CONTROLLER_DP_COLOR_SPACE_UDEFINED;
3758                                 DC_LOG_ERROR("%s: Color space must be defined for test pattern", __func__);
3759                                 ASSERT(0);
3760                                 break;
3761                         }
3762
3763                         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
3764                                 opp_cnt++;
3765                         dpg_width = width / opp_cnt;
3766                         offset = dpg_width;
3767
3768                         opp->funcs->opp_set_disp_pattern_generator(opp,
3769                                 controller_test_pattern,
3770                                 controller_color_space,
3771                                 color_depth,
3772                                 NULL,
3773                                 dpg_width,
3774                                 height,
3775                                 0);
3776
3777                         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
3778                                 struct output_pixel_processor *odm_opp = odm_pipe->stream_res.opp;
3779                                 odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, &params);
3780                                 odm_opp->funcs->opp_set_disp_pattern_generator(odm_opp,
3781                                         controller_test_pattern,
3782                                         controller_color_space,
3783                                         color_depth,
3784                                         NULL,
3785                                         dpg_width,
3786                                         height,
3787                                         offset);
3788                                 offset += offset;
3789                         }
3790                 }
3791         }
3792         break;
3793         case DP_TEST_PATTERN_VIDEO_MODE:
3794         {
3795                 /* restore bitdepth reduction */
3796                 resource_build_bit_depth_reduction_params(pipe_ctx->stream, &params);
3797                 pipe_ctx->stream->bit_depth_params = params;
3798                 opp->funcs->opp_program_bit_depth_reduction(opp, &params);
3799                 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
3800                         pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
3801                                 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
3802                                 color_depth);
3803                 else if (opp->funcs->opp_set_disp_pattern_generator) {
3804                         struct pipe_ctx *odm_pipe;
3805                         int opp_cnt = 1;
3806                         int dpg_width = width;
3807
3808                         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
3809                                 opp_cnt++;
3810
3811                         dpg_width = width / opp_cnt;
3812                         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
3813                                 struct output_pixel_processor *odm_opp = odm_pipe->stream_res.opp;
3814
3815                                 odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, &params);
3816                                 odm_opp->funcs->opp_set_disp_pattern_generator(odm_opp,
3817                                         CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
3818                                         CONTROLLER_DP_COLOR_SPACE_UDEFINED,
3819                                         color_depth,
3820                                         NULL,
3821                                         dpg_width,
3822                                         height,
3823                                         0);
3824                         }
3825                         opp->funcs->opp_set_disp_pattern_generator(opp,
3826                                 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
3827                                 CONTROLLER_DP_COLOR_SPACE_UDEFINED,
3828                                 color_depth,
3829                                 NULL,
3830                                 dpg_width,
3831                                 height,
3832                                 0);
3833                 }
3834         }
3835         break;
3836
3837         default:
3838         break;
3839         }
3840 }
3841
3842 bool dc_link_dp_set_test_pattern(
3843         struct dc_link *link,
3844         enum dp_test_pattern test_pattern,
3845         enum dp_test_pattern_color_space test_pattern_color_space,
3846         const struct link_training_settings *p_link_settings,
3847         const unsigned char *p_custom_pattern,
3848         unsigned int cust_pattern_size)
3849 {
3850         struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx;
3851         struct pipe_ctx *pipe_ctx = &pipes[0];
3852         unsigned int lane;
3853         unsigned int i;
3854         unsigned char link_qual_pattern[LANE_COUNT_DP_MAX] = {0};
3855         union dpcd_training_pattern training_pattern;
3856         enum dpcd_phy_test_patterns pattern;
3857
3858         memset(&training_pattern, 0, sizeof(training_pattern));
3859
3860         for (i = 0; i < MAX_PIPES; i++) {
3861                 if (pipes[i].stream->link == link && !pipes[i].top_pipe && !pipes[i].prev_odm_pipe) {
3862                         pipe_ctx = &pipes[i];
3863                         break;
3864                 }
3865         }
3866
3867         /* Reset CRTC Test Pattern if it is currently running and request
3868          * is VideoMode Reset DP Phy Test Pattern if it is currently running
3869          * and request is VideoMode
3870          */
3871         if (link->test_pattern_enabled && test_pattern ==
3872                         DP_TEST_PATTERN_VIDEO_MODE) {
3873                 /* Set CRTC Test Pattern */
3874                 set_crtc_test_pattern(link, pipe_ctx, test_pattern, test_pattern_color_space);
3875                 dp_set_hw_test_pattern(link, test_pattern,
3876                                 (uint8_t *)p_custom_pattern,
3877                                 (uint32_t)cust_pattern_size);
3878
3879                 /* Unblank Stream */
3880                 link->dc->hwss.unblank_stream(
3881                         pipe_ctx,
3882                         &link->verified_link_cap);
3883                 /* TODO:m_pHwss->MuteAudioEndpoint
3884                  * (pPathMode->pDisplayPath, false);
3885                  */
3886
3887                 /* Reset Test Pattern state */
3888                 link->test_pattern_enabled = false;
3889
3890                 return true;
3891         }
3892
3893         /* Check for PHY Test Patterns */
3894         if (is_dp_phy_pattern(test_pattern)) {
3895                 /* Set DPCD Lane Settings before running test pattern */
3896                 if (p_link_settings != NULL) {
3897                         dp_set_hw_lane_settings(link, p_link_settings, DPRX);
3898                         dpcd_set_lane_settings(link, p_link_settings, DPRX);
3899                 }
3900
3901                 /* Blank stream if running test pattern */
3902                 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
3903                         /*TODO:
3904                          * m_pHwss->
3905                          * MuteAudioEndpoint(pPathMode->pDisplayPath, true);
3906                          */
3907                         /* Blank stream */
3908                         pipes->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc);
3909                 }
3910
3911                 dp_set_hw_test_pattern(link, test_pattern,
3912                                 (uint8_t *)p_custom_pattern,
3913                                 (uint32_t)cust_pattern_size);
3914
3915                 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
3916                         /* Set Test Pattern state */
3917                         link->test_pattern_enabled = true;
3918                         if (p_link_settings != NULL)
3919                                 dpcd_set_link_settings(link,
3920                                                 p_link_settings);
3921                 }
3922
3923                 switch (test_pattern) {
3924                 case DP_TEST_PATTERN_VIDEO_MODE:
3925                         pattern = PHY_TEST_PATTERN_NONE;
3926                         break;
3927                 case DP_TEST_PATTERN_D102:
3928                         pattern = PHY_TEST_PATTERN_D10_2;
3929                         break;
3930                 case DP_TEST_PATTERN_SYMBOL_ERROR:
3931                         pattern = PHY_TEST_PATTERN_SYMBOL_ERROR;
3932                         break;
3933                 case DP_TEST_PATTERN_PRBS7:
3934                         pattern = PHY_TEST_PATTERN_PRBS7;
3935                         break;
3936                 case DP_TEST_PATTERN_80BIT_CUSTOM:
3937                         pattern = PHY_TEST_PATTERN_80BIT_CUSTOM;
3938                         break;
3939                 case DP_TEST_PATTERN_CP2520_1:
3940                         pattern = PHY_TEST_PATTERN_CP2520_1;
3941                         break;
3942                 case DP_TEST_PATTERN_CP2520_2:
3943                         pattern = PHY_TEST_PATTERN_CP2520_2;
3944                         break;
3945                 case DP_TEST_PATTERN_CP2520_3:
3946                         pattern = PHY_TEST_PATTERN_CP2520_3;
3947                         break;
3948                 default:
3949                         return false;
3950                 }
3951
3952                 if (test_pattern == DP_TEST_PATTERN_VIDEO_MODE
3953                 /*TODO:&& !pPathMode->pDisplayPath->IsTargetPoweredOn()*/)
3954                         return false;
3955
3956                 if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
3957                         /* tell receiver that we are sending qualification
3958                          * pattern DP 1.2 or later - DP receiver's link quality
3959                          * pattern is set using DPCD LINK_QUAL_LANEx_SET
3960                          * register (0x10B~0x10E)\
3961                          */
3962                         for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++)
3963                                 link_qual_pattern[lane] =
3964                                                 (unsigned char)(pattern);
3965
3966                         core_link_write_dpcd(link,
3967                                         DP_LINK_QUAL_LANE0_SET,
3968                                         link_qual_pattern,
3969                                         sizeof(link_qual_pattern));
3970                 } else if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_10 ||
3971                            link->dpcd_caps.dpcd_rev.raw == 0) {
3972                         /* tell receiver that we are sending qualification
3973                          * pattern DP 1.1a or earlier - DP receiver's link
3974                          * quality pattern is set using
3975                          * DPCD TRAINING_PATTERN_SET -> LINK_QUAL_PATTERN_SET
3976                          * register (0x102). We will use v_1.3 when we are
3977                          * setting test pattern for DP 1.1.
3978                          */
3979                         core_link_read_dpcd(link, DP_TRAINING_PATTERN_SET,
3980                                             &training_pattern.raw,
3981                                             sizeof(training_pattern));
3982                         training_pattern.v1_3.LINK_QUAL_PATTERN_SET = pattern;
3983                         core_link_write_dpcd(link, DP_TRAINING_PATTERN_SET,
3984                                              &training_pattern.raw,
3985                                              sizeof(training_pattern));
3986                 }
3987         } else {
3988                 enum dc_color_space color_space = COLOR_SPACE_UNKNOWN;
3989
3990                 switch (test_pattern_color_space) {
3991                 case DP_TEST_PATTERN_COLOR_SPACE_RGB:
3992                         color_space = COLOR_SPACE_SRGB;
3993                         if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
3994                                 color_space = COLOR_SPACE_SRGB_LIMITED;
3995                         break;
3996
3997                 case DP_TEST_PATTERN_COLOR_SPACE_YCBCR601:
3998                         color_space = COLOR_SPACE_YCBCR601;
3999                         if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4000                                 color_space = COLOR_SPACE_YCBCR601_LIMITED;
4001                         break;
4002                 case DP_TEST_PATTERN_COLOR_SPACE_YCBCR709:
4003                         color_space = COLOR_SPACE_YCBCR709;
4004                         if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4005                                 color_space = COLOR_SPACE_YCBCR709_LIMITED;
4006                         break;
4007                 default:
4008                         break;
4009                 }
4010
4011                 if (pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_enable)
4012                         pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_enable(
4013                                         pipe_ctx->stream_res.tg);
4014                 pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg);
4015                 /* update MSA to requested color space */
4016                 pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute(pipe_ctx->stream_res.stream_enc,
4017                                 &pipe_ctx->stream->timing,
4018                                 color_space,
4019                                 pipe_ctx->stream->use_vsc_sdp_for_colorimetry,
4020                                 link->dpcd_caps.dprx_feature.bits.SST_SPLIT_SDP_CAP);
4021
4022                 if (pipe_ctx->stream->use_vsc_sdp_for_colorimetry) {
4023                         if (test_pattern == DP_TEST_PATTERN_COLOR_SQUARES_CEA)
4024                                 pipe_ctx->stream->vsc_infopacket.sb[17] |= (1 << 7); // sb17 bit 7 Dynamic Range: 0 = VESA range, 1 = CTA range
4025                         else
4026                                 pipe_ctx->stream->vsc_infopacket.sb[17] &= ~(1 << 7);
4027                         resource_build_info_frame(pipe_ctx);
4028                         link->dc->hwss.update_info_frame(pipe_ctx);
4029                 }
4030
4031                 /* CRTC Patterns */
4032                 set_crtc_test_pattern(link, pipe_ctx, test_pattern, test_pattern_color_space);
4033                 pipe_ctx->stream_res.tg->funcs->unlock(pipe_ctx->stream_res.tg);
4034                 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,
4035                                 CRTC_STATE_VACTIVE);
4036                 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,
4037                                 CRTC_STATE_VBLANK);
4038                 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg,
4039                                 CRTC_STATE_VACTIVE);
4040                 if (pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_disable)
4041                         pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_disable(
4042                                         pipe_ctx->stream_res.tg);
4043                 /* Set Test Pattern state */
4044                 link->test_pattern_enabled = true;
4045         }
4046
4047         return true;
4048 }
4049
4050 void dp_enable_mst_on_sink(struct dc_link *link, bool enable)
4051 {
4052         unsigned char mstmCntl;
4053
4054         core_link_read_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
4055         if (enable)
4056                 mstmCntl |= DP_MST_EN;
4057         else
4058                 mstmCntl &= (~DP_MST_EN);
4059
4060         core_link_write_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
4061 }
4062
4063 void dp_set_panel_mode(struct dc_link *link, enum dp_panel_mode panel_mode)
4064 {
4065         union dpcd_edp_config edp_config_set;
4066         bool panel_mode_edp = false;
4067
4068         memset(&edp_config_set, '\0', sizeof(union dpcd_edp_config));
4069
4070         if (panel_mode != DP_PANEL_MODE_DEFAULT) {
4071
4072                 switch (panel_mode) {
4073                 case DP_PANEL_MODE_EDP:
4074                 case DP_PANEL_MODE_SPECIAL:
4075                         panel_mode_edp = true;
4076                         break;
4077
4078                 default:
4079                                 break;
4080                 }
4081
4082                 /*set edp panel mode in receiver*/
4083                 core_link_read_dpcd(
4084                         link,
4085                         DP_EDP_CONFIGURATION_SET,
4086                         &edp_config_set.raw,
4087                         sizeof(edp_config_set.raw));
4088
4089                 if (edp_config_set.bits.PANEL_MODE_EDP
4090                         != panel_mode_edp) {
4091                         enum ddc_result result = DDC_RESULT_UNKNOWN;
4092
4093                         edp_config_set.bits.PANEL_MODE_EDP =
4094                         panel_mode_edp;
4095                         result = core_link_write_dpcd(
4096                                 link,
4097                                 DP_EDP_CONFIGURATION_SET,
4098                                 &edp_config_set.raw,
4099                                 sizeof(edp_config_set.raw));
4100
4101                         ASSERT(result == DDC_RESULT_SUCESSFULL);
4102                 }
4103         }
4104         DC_LOG_DETECTION_DP_CAPS("Link: %d eDP panel mode supported: %d "
4105                  "eDP panel mode enabled: %d \n",
4106                  link->link_index,
4107                  link->dpcd_caps.panel_mode_edp,
4108                  panel_mode_edp);
4109 }
4110
4111 enum dp_panel_mode dp_get_panel_mode(struct dc_link *link)
4112 {
4113         /* We need to explicitly check that connector
4114          * is not DP. Some Travis_VGA get reported
4115          * by video bios as DP.
4116          */
4117         if (link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) {
4118
4119                 switch (link->dpcd_caps.branch_dev_id) {
4120                 case DP_BRANCH_DEVICE_ID_0022B9:
4121                         /* alternate scrambler reset is required for Travis
4122                          * for the case when external chip does not
4123                          * provide sink device id, alternate scrambler
4124                          * scheme will  be overriden later by querying
4125                          * Encoder features
4126                          */
4127                         if (strncmp(
4128                                 link->dpcd_caps.branch_dev_name,
4129                                 DP_VGA_LVDS_CONVERTER_ID_2,
4130                                 sizeof(
4131                                 link->dpcd_caps.
4132                                 branch_dev_name)) == 0) {
4133                                         return DP_PANEL_MODE_SPECIAL;
4134                         }
4135                         break;
4136                 case DP_BRANCH_DEVICE_ID_00001A:
4137                         /* alternate scrambler reset is required for Travis
4138                          * for the case when external chip does not provide
4139                          * sink device id, alternate scrambler scheme will
4140                          * be overriden later by querying Encoder feature
4141                          */
4142                         if (strncmp(link->dpcd_caps.branch_dev_name,
4143                                 DP_VGA_LVDS_CONVERTER_ID_3,
4144                                 sizeof(
4145                                 link->dpcd_caps.
4146                                 branch_dev_name)) == 0) {
4147                                         return DP_PANEL_MODE_SPECIAL;
4148                         }
4149                         break;
4150                 default:
4151                         break;
4152                 }
4153         }
4154
4155         if (link->dpcd_caps.panel_mode_edp) {
4156                 return DP_PANEL_MODE_EDP;
4157         }
4158
4159         return DP_PANEL_MODE_DEFAULT;
4160 }
4161
4162 void dp_set_fec_ready(struct dc_link *link, bool ready)
4163 {
4164         /* FEC has to be "set ready" before the link training.
4165          * The policy is to always train with FEC
4166          * if the sink supports it and leave it enabled on link.
4167          * If FEC is not supported, disable it.
4168          */
4169         struct link_encoder *link_enc = link->link_enc;
4170         uint8_t fec_config = 0;
4171
4172         if (!dc_link_is_fec_supported(link) || link->dc->debug.disable_fec)
4173                 return;
4174
4175         if (link_enc->funcs->fec_set_ready &&
4176                         link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) {
4177                 if (ready) {
4178                         fec_config = 1;
4179                         if (core_link_write_dpcd(link,
4180                                         DP_FEC_CONFIGURATION,
4181                                         &fec_config,
4182                                         sizeof(fec_config)) == DC_OK) {
4183                                 link_enc->funcs->fec_set_ready(link_enc, true);
4184                                 link->fec_state = dc_link_fec_ready;
4185                         } else {
4186                                 link->link_enc->funcs->fec_set_ready(link->link_enc, false);
4187                                 link->fec_state = dc_link_fec_not_ready;
4188                                 dm_error("dpcd write failed to set fec_ready");
4189                         }
4190                 } else if (link->fec_state == dc_link_fec_ready) {
4191                         fec_config = 0;
4192                         core_link_write_dpcd(link,
4193                                         DP_FEC_CONFIGURATION,
4194                                         &fec_config,
4195                                         sizeof(fec_config));
4196                         link->link_enc->funcs->fec_set_ready(
4197                                         link->link_enc, false);
4198                         link->fec_state = dc_link_fec_not_ready;
4199                 }
4200         }
4201 }
4202
4203 void dp_set_fec_enable(struct dc_link *link, bool enable)
4204 {
4205         struct link_encoder *link_enc = link->link_enc;
4206
4207         if (!dc_link_is_fec_supported(link) || link->dc->debug.disable_fec)
4208                 return;
4209
4210         if (link_enc->funcs->fec_set_enable &&
4211                         link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) {
4212                 if (link->fec_state == dc_link_fec_ready && enable) {
4213                         /* Accord to DP spec, FEC enable sequence can first
4214                          * be transmitted anytime after 1000 LL codes have
4215                          * been transmitted on the link after link training
4216                          * completion. Using 1 lane RBR should have the maximum
4217                          * time for transmitting 1000 LL codes which is 6.173 us.
4218                          * So use 7 microseconds delay instead.
4219                          */
4220                         udelay(7);
4221                         link_enc->funcs->fec_set_enable(link_enc, true);
4222                         link->fec_state = dc_link_fec_enabled;
4223                 } else if (link->fec_state == dc_link_fec_enabled && !enable) {
4224                         link_enc->funcs->fec_set_enable(link_enc, false);
4225                         link->fec_state = dc_link_fec_ready;
4226                 }
4227         }
4228 }
4229
4230 void dpcd_set_source_specific_data(struct dc_link *link)
4231 {
4232         const uint32_t post_oui_delay = 30; // 30ms
4233         uint8_t dspc = 0;
4234         enum dc_status ret;
4235
4236         ret = core_link_read_dpcd(link, DP_DOWN_STREAM_PORT_COUNT, &dspc,
4237                                   sizeof(dspc));
4238
4239         if (ret != DC_OK) {
4240                 DC_LOG_ERROR("Error in DP aux read transaction,"
4241                              " not writing source specific data\n");
4242                 return;
4243         }
4244
4245         /* Return if OUI unsupported */
4246         if (!(dspc & DP_OUI_SUPPORT))
4247                 return;
4248
4249         if (!link->dc->vendor_signature.is_valid) {
4250                 struct dpcd_amd_signature amd_signature;
4251                 amd_signature.AMD_IEEE_TxSignature_byte1 = 0x0;
4252                 amd_signature.AMD_IEEE_TxSignature_byte2 = 0x0;
4253                 amd_signature.AMD_IEEE_TxSignature_byte3 = 0x1A;
4254                 amd_signature.device_id_byte1 =
4255                                 (uint8_t)(link->ctx->asic_id.chip_id);
4256                 amd_signature.device_id_byte2 =
4257                                 (uint8_t)(link->ctx->asic_id.chip_id >> 8);
4258                 memset(&amd_signature.zero, 0, 4);
4259                 amd_signature.dce_version =
4260                                 (uint8_t)(link->ctx->dce_version);
4261                 amd_signature.dal_version_byte1 = 0x0; // needed? where to get?
4262                 amd_signature.dal_version_byte2 = 0x0; // needed? where to get?
4263
4264                 core_link_write_dpcd(link, DP_SOURCE_OUI,
4265                                 (uint8_t *)(&amd_signature),
4266                                 sizeof(amd_signature));
4267
4268         } else {
4269                 core_link_write_dpcd(link, DP_SOURCE_OUI,
4270                                 link->dc->vendor_signature.data.raw,
4271                                 sizeof(link->dc->vendor_signature.data.raw));
4272         }
4273
4274         // Sink may need to configure internals based on vendor, so allow some
4275         // time before proceeding with possibly vendor specific transactions
4276         msleep(post_oui_delay);
4277 }
4278
4279 bool dc_link_set_backlight_level_nits(struct dc_link *link,
4280                 bool isHDR,
4281                 uint32_t backlight_millinits,
4282                 uint32_t transition_time_in_ms)
4283 {
4284         struct dpcd_source_backlight_set dpcd_backlight_set;
4285         uint8_t backlight_control = isHDR ? 1 : 0;
4286
4287         if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4288                         link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4289                 return false;
4290
4291         // OLEDs have no PWM, they can only use AUX
4292         if (link->dpcd_sink_ext_caps.bits.oled == 1)
4293                 backlight_control = 1;
4294
4295         *(uint32_t *)&dpcd_backlight_set.backlight_level_millinits = backlight_millinits;
4296         *(uint16_t *)&dpcd_backlight_set.backlight_transition_time_ms = (uint16_t)transition_time_in_ms;
4297
4298
4299         if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_LEVEL,
4300                         (uint8_t *)(&dpcd_backlight_set),
4301                         sizeof(dpcd_backlight_set)) != DC_OK)
4302                 return false;
4303
4304         if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_CONTROL,
4305                         &backlight_control, 1) != DC_OK)
4306                 return false;
4307
4308         return true;
4309 }
4310
4311 bool dc_link_get_backlight_level_nits(struct dc_link *link,
4312                 uint32_t *backlight_millinits_avg,
4313                 uint32_t *backlight_millinits_peak)
4314 {
4315         union dpcd_source_backlight_get dpcd_backlight_get;
4316
4317         memset(&dpcd_backlight_get, 0, sizeof(union dpcd_source_backlight_get));
4318
4319         if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4320                         link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4321                 return false;
4322
4323         if (!core_link_read_dpcd(link, DP_SOURCE_BACKLIGHT_CURRENT_PEAK,
4324                         dpcd_backlight_get.raw,
4325                         sizeof(union dpcd_source_backlight_get)))
4326                 return false;
4327
4328         *backlight_millinits_avg =
4329                 dpcd_backlight_get.bytes.backlight_millinits_avg;
4330         *backlight_millinits_peak =
4331                 dpcd_backlight_get.bytes.backlight_millinits_peak;
4332
4333         /* On non-supported panels dpcd_read usually succeeds with 0 returned */
4334         if (*backlight_millinits_avg == 0 ||
4335                         *backlight_millinits_avg > *backlight_millinits_peak)
4336                 return false;
4337
4338         return true;
4339 }
4340
4341 bool dc_link_backlight_enable_aux(struct dc_link *link, bool enable)
4342 {
4343         uint8_t backlight_enable = enable ? 1 : 0;
4344
4345         if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4346                 link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4347                 return false;
4348
4349         if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_ENABLE,
4350                 &backlight_enable, 1) != DC_OK)
4351                 return false;
4352
4353         return true;
4354 }
4355
4356 // we read default from 0x320 because we expect BIOS wrote it there
4357 // regular get_backlight_nit reads from panel set at 0x326
4358 bool dc_link_read_default_bl_aux(struct dc_link *link, uint32_t *backlight_millinits)
4359 {
4360         if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
4361                 link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
4362                 return false;
4363
4364         if (!core_link_read_dpcd(link, DP_SOURCE_BACKLIGHT_LEVEL,
4365                 (uint8_t *) backlight_millinits,
4366                 sizeof(uint32_t)))
4367                 return false;
4368
4369         return true;
4370 }
4371
4372 bool dc_link_set_default_brightness_aux(struct dc_link *link)
4373 {
4374         uint32_t default_backlight;
4375
4376         if (link &&
4377                 (link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1 ||
4378                 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1)) {
4379                 if (!dc_link_read_default_bl_aux(link, &default_backlight))
4380                         default_backlight = 150000;
4381                 // if < 5 nits or > 5000, it might be wrong readback
4382                 if (default_backlight < 5000 || default_backlight > 5000000)
4383                         default_backlight = 150000; //
4384
4385                 return dc_link_set_backlight_level_nits(link, true,
4386                                 default_backlight, 0);
4387         }
4388         return false;
4389 }