drivers/gpu/drm/amd/display/dc/core/dc_link.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <linux/slab.h>
  27
  28 #include "dm_services.h"
  29 #include "atomfirmware.h"
  30 #include "dm_helpers.h"
  31 #include "dc.h"
  32 #include "grph_object_id.h"
  33 #include "gpio_service_interface.h"
  34 #include "core_status.h"
  35 #include "dc_link_dp.h"
  36 #include "dc_link_ddc.h"
  37 #include "link_hwss.h"
  38 #include "opp.h"
  39
  40 #include "link_encoder.h"
  41 #include "hw_sequencer.h"
  42 #include "resource.h"
  43 #include "abm.h"
  44 #include "fixed31_32.h"
  45 #include "dpcd_defs.h"
  46 #include "dmcu.h"
  47 #include "hw/clk_mgr.h"
  48 #include "dce/dmub_psr.h"
  49 #include "dmub/dmub_srv.h"
  50 #include "inc/hw/panel_cntl.h"
  51 #include "inc/link_enc_cfg.h"
  52 #include "inc/link_dpcd.h"
  53
  54 #include "dc/dcn30/dcn30_vpg.h"
  55
  56 #define DC_LOGGER_INIT(logger)
  57
  58 #define LINK_INFO(...) \
  59         DC_LOG_HW_HOTPLUG(  \
  60                 __VA_ARGS__)
  61
  62 #define RETIMER_REDRIVER_INFO(...) \
  63         DC_LOG_RETIMER_REDRIVER(  \
  64                 __VA_ARGS__)
  65
  66 /*******************************************************************************
  67  * Private functions
  68  ******************************************************************************/
  69 #if defined(CONFIG_DRM_AMD_DC_DCN)
  70 static bool add_dp_hpo_link_encoder_to_link(struct dc_link *link)
  71 {
  72         struct hpo_dp_link_encoder *enc = resource_get_unused_hpo_dp_link_encoder(
  73                                         link->dc->res_pool);
  74
  75         if (!link->hpo_dp_link_enc && enc) {
  76                 link->hpo_dp_link_enc = enc;
  77                 link->hpo_dp_link_enc->transmitter = link->link_enc->transmitter;
  78                 link->hpo_dp_link_enc->hpd_source = link->link_enc->hpd_source;
  79         }
  80
  81         return (link->hpo_dp_link_enc != NULL);
  82 }
  83
  84 static void remove_dp_hpo_link_encoder_from_link(struct dc_link *link)
  85 {
  86         if (link->hpo_dp_link_enc) {
  87                 link->hpo_dp_link_enc->hpd_source = HPD_SOURCEID_UNKNOWN;
  88                 link->hpo_dp_link_enc->transmitter = TRANSMITTER_UNKNOWN;
  89                 link->hpo_dp_link_enc = NULL;
  90         }
  91 }
  92 #endif
  93
  94 static void dc_link_destruct(struct dc_link *link)
  95 {
  96         int i;
  97
  98         if (link->hpd_gpio) {
  99                 dal_gpio_destroy_irq(&link->hpd_gpio);
 100                 link->hpd_gpio = NULL;
 101         }
 102
 103         if (link->ddc)
 104                 dal_ddc_service_destroy(&link->ddc);
 105
 106         if (link->panel_cntl)
 107                 link->panel_cntl->funcs->destroy(&link->panel_cntl);
 108
 109         if (link->link_enc) {
 110                 /* Update link encoder resource tracking variables. These are used for
 111                  * the dynamic assignment of link encoders to streams. Virtual links
 112                  * are not assigned encoder resources on creation.
 113                  */
 114                 if (link->link_id.id != CONNECTOR_ID_VIRTUAL) {
 115                         link->dc->res_pool->link_encoders[link->eng_id - ENGINE_ID_DIGA] = NULL;
 116                         link->dc->res_pool->dig_link_enc_count--;
 117                 }
 118                 link->link_enc->funcs->destroy(&link->link_enc);
 119         }
 120
 121 #if defined(CONFIG_DRM_AMD_DC_DCN)
 122         if (link->hpo_dp_link_enc) {
 123                 remove_dp_hpo_link_encoder_from_link(link);
 124         }
 125 #endif
 126
 127         if (link->local_sink)
 128                 dc_sink_release(link->local_sink);
 129
 130         for (i = 0; i < link->sink_count; ++i)
 131                 dc_sink_release(link->remote_sinks[i]);
 132 }
 133
 134 struct gpio *get_hpd_gpio(struct dc_bios *dcb,
 135                           struct graphics_object_id link_id,
 136                           struct gpio_service *gpio_service)
 137 {
 138         enum bp_result bp_result;
 139         struct graphics_object_hpd_info hpd_info;
 140         struct gpio_pin_info pin_info;
 141
 142         if (dcb->funcs->get_hpd_info(dcb, link_id, &hpd_info) != BP_RESULT_OK)
 143                 return NULL;
 144
 145         bp_result = dcb->funcs->get_gpio_pin_info(dcb,
 146                 hpd_info.hpd_int_gpio_uid, &pin_info);
 147
 148         if (bp_result != BP_RESULT_OK) {
 149                 ASSERT(bp_result == BP_RESULT_NORECORD);
 150                 return NULL;
 151         }
 152
 153         return dal_gpio_service_create_irq(gpio_service,
 154                                            pin_info.offset,
 155                                            pin_info.mask);
 156 }
 157
 158 /*
 159  *  Function: program_hpd_filter
 160  *
 161  *  @brief
 162  *     Programs HPD filter on associated HPD line
 163  *
 164  *  @param [in] delay_on_connect_in_ms: Connect filter timeout
 165  *  @param [in] delay_on_disconnect_in_ms: Disconnect filter timeout
 166  *
 167  *  @return
 168  *     true on success, false otherwise
 169  */
 170 static bool program_hpd_filter(const struct dc_link *link)
 171 {
 172         bool result = false;
 173         struct gpio *hpd;
 174         int delay_on_connect_in_ms = 0;
 175         int delay_on_disconnect_in_ms = 0;
 176
 177         if (link->is_hpd_filter_disabled)
 178                 return false;
 179         /* Verify feature is supported */
 180         switch (link->connector_signal) {
 181         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 182         case SIGNAL_TYPE_DVI_DUAL_LINK:
 183         case SIGNAL_TYPE_HDMI_TYPE_A:
 184                 /* Program hpd filter */
 185                 delay_on_connect_in_ms = 500;
 186                 delay_on_disconnect_in_ms = 100;
 187                 break;
 188         case SIGNAL_TYPE_DISPLAY_PORT:
 189         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 190                 /* Program hpd filter to allow DP signal to settle */
 191                 /* 500: not able to detect MST <-> SST switch as HPD is low for
 192                  * only 100ms on DELL U2413
 193                  * 0: some passive dongle still show aux mode instead of i2c
 194                  * 20-50: not enough to hide bouncing HPD with passive dongle.
 195                  * also see intermittent i2c read issues.
 196                  */
 197                 delay_on_connect_in_ms = 80;
 198                 delay_on_disconnect_in_ms = 0;
 199                 break;
 200         case SIGNAL_TYPE_LVDS:
 201         case SIGNAL_TYPE_EDP:
 202         default:
 203                 /* Don't program hpd filter */
 204                 return false;
 205         }
 206
 207         /* Obtain HPD handle */
 208         hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
 209                            link->ctx->gpio_service);
 210
 211         if (!hpd)
 212                 return result;
 213
 214         /* Setup HPD filtering */
 215         if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) {
 216                 struct gpio_hpd_config config;
 217
 218                 config.delay_on_connect = delay_on_connect_in_ms;
 219                 config.delay_on_disconnect = delay_on_disconnect_in_ms;
 220
 221                 dal_irq_setup_hpd_filter(hpd, &config);
 222
 223                 dal_gpio_close(hpd);
 224
 225                 result = true;
 226         } else {
 227                 ASSERT_CRITICAL(false);
 228         }
 229
 230         /* Release HPD handle */
 231         dal_gpio_destroy_irq(&hpd);
 232
 233         return result;
 234 }
 235
 236 bool dc_link_wait_for_t12(struct dc_link *link)
 237 {
 238         if (link->connector_signal == SIGNAL_TYPE_EDP && link->dc->hwss.edp_wait_for_T12) {
 239                 link->dc->hwss.edp_wait_for_T12(link);
 240
 241                 return true;
 242         }
 243
 244         return false;
 245 }
 246
 247 /**
 248  * dc_link_detect_sink() - Determine if there is a sink connected
 249  *
 250  * @link: pointer to the dc link
 251  * @type: Returned connection type
 252  * Does not detect downstream devices, such as MST sinks
 253  * or display connected through active dongles
 254  */
 255 bool dc_link_detect_sink(struct dc_link *link, enum dc_connection_type *type)
 256 {
 257         uint32_t is_hpd_high = 0;
 258         struct gpio *hpd_pin;
 259
 260         if (link->connector_signal == SIGNAL_TYPE_LVDS) {
 261                 *type = dc_connection_single;
 262                 return true;
 263         }
 264
 265         if (link->connector_signal == SIGNAL_TYPE_EDP) {
 266                 /*in case it is not on*/
 267                 link->dc->hwss.edp_power_control(link, true);
 268                 link->dc->hwss.edp_wait_for_hpd_ready(link, true);
 269         }
 270
 271         /* Link may not have physical HPD pin. */
 272         if (link->ep_type != DISPLAY_ENDPOINT_PHY) {
 273                 if (link->hpd_status)
 274                         *type = dc_connection_single;
 275                 else
 276                         *type = dc_connection_none;
 277
 278                 return true;
 279         }
 280
 281         /* todo: may need to lock gpio access */
 282         hpd_pin = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
 283                                link->ctx->gpio_service);
 284         if (!hpd_pin)
 285                 goto hpd_gpio_failure;
 286
 287         dal_gpio_open(hpd_pin, GPIO_MODE_INTERRUPT);
 288         dal_gpio_get_value(hpd_pin, &is_hpd_high);
 289         dal_gpio_close(hpd_pin);
 290         dal_gpio_destroy_irq(&hpd_pin);
 291
 292         if (is_hpd_high) {
 293                 *type = dc_connection_single;
 294                 /* TODO: need to do the actual detection */
 295         } else {
 296                 *type = dc_connection_none;
 297         }
 298
 299         return true;
 300
 301 hpd_gpio_failure:
 302         return false;
 303 }
 304
 305 static enum ddc_transaction_type get_ddc_transaction_type(enum signal_type sink_signal)
 306 {
 307         enum ddc_transaction_type transaction_type = DDC_TRANSACTION_TYPE_NONE;
 308
 309         switch (sink_signal) {
 310         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 311         case SIGNAL_TYPE_DVI_DUAL_LINK:
 312         case SIGNAL_TYPE_HDMI_TYPE_A:
 313         case SIGNAL_TYPE_LVDS:
 314         case SIGNAL_TYPE_RGB:
 315                 transaction_type = DDC_TRANSACTION_TYPE_I2C;
 316                 break;
 317
 318         case SIGNAL_TYPE_DISPLAY_PORT:
 319         case SIGNAL_TYPE_EDP:
 320                 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 321                 break;
 322
 323         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 324                 /* MST does not use I2COverAux, but there is the
 325                  * SPECIAL use case for "immediate dwnstrm device
 326                  * access" (EPR#370830).
 327                  */
 328                 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 329                 break;
 330
 331         default:
 332                 break;
 333         }
 334
 335         return transaction_type;
 336 }
 337
 338 static enum signal_type get_basic_signal_type(struct graphics_object_id encoder,
 339                                               struct graphics_object_id downstream)
 340 {
 341         if (downstream.type == OBJECT_TYPE_CONNECTOR) {
 342                 switch (downstream.id) {
 343                 case CONNECTOR_ID_SINGLE_LINK_DVII:
 344                         switch (encoder.id) {
 345                         case ENCODER_ID_INTERNAL_DAC1:
 346                         case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
 347                         case ENCODER_ID_INTERNAL_DAC2:
 348                         case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
 349                                 return SIGNAL_TYPE_RGB;
 350                         default:
 351                                 return SIGNAL_TYPE_DVI_SINGLE_LINK;
 352                         }
 353                 break;
 354                 case CONNECTOR_ID_DUAL_LINK_DVII:
 355                 {
 356                         switch (encoder.id) {
 357                         case ENCODER_ID_INTERNAL_DAC1:
 358                         case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
 359                         case ENCODER_ID_INTERNAL_DAC2:
 360                         case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
 361                                 return SIGNAL_TYPE_RGB;
 362                         default:
 363                                 return SIGNAL_TYPE_DVI_DUAL_LINK;
 364                         }
 365                 }
 366                 break;
 367                 case CONNECTOR_ID_SINGLE_LINK_DVID:
 368                         return SIGNAL_TYPE_DVI_SINGLE_LINK;
 369                 case CONNECTOR_ID_DUAL_LINK_DVID:
 370                         return SIGNAL_TYPE_DVI_DUAL_LINK;
 371                 case CONNECTOR_ID_VGA:
 372                         return SIGNAL_TYPE_RGB;
 373                 case CONNECTOR_ID_HDMI_TYPE_A:
 374                         return SIGNAL_TYPE_HDMI_TYPE_A;
 375                 case CONNECTOR_ID_LVDS:
 376                         return SIGNAL_TYPE_LVDS;
 377                 case CONNECTOR_ID_DISPLAY_PORT:
 378                         return SIGNAL_TYPE_DISPLAY_PORT;
 379                 case CONNECTOR_ID_EDP:
 380                         return SIGNAL_TYPE_EDP;
 381                 default:
 382                         return SIGNAL_TYPE_NONE;
 383                 }
 384         } else if (downstream.type == OBJECT_TYPE_ENCODER) {
 385                 switch (downstream.id) {
 386                 case ENCODER_ID_EXTERNAL_NUTMEG:
 387                 case ENCODER_ID_EXTERNAL_TRAVIS:
 388                         return SIGNAL_TYPE_DISPLAY_PORT;
 389                 default:
 390                         return SIGNAL_TYPE_NONE;
 391                 }
 392         }
 393
 394         return SIGNAL_TYPE_NONE;
 395 }
 396
 397 /*
 398  * dc_link_is_dp_sink_present() - Check if there is a native DP
 399  * or passive DP-HDMI dongle connected
 400  */
 401 bool dc_link_is_dp_sink_present(struct dc_link *link)
 402 {
 403         enum gpio_result gpio_result;
 404         uint32_t clock_pin = 0;
 405         uint8_t retry = 0;
 406         struct ddc *ddc;
 407
 408         enum connector_id connector_id =
 409                 dal_graphics_object_id_get_connector_id(link->link_id);
 410
 411         bool present =
 412                 ((connector_id == CONNECTOR_ID_DISPLAY_PORT) ||
 413                 (connector_id == CONNECTOR_ID_EDP));
 414
 415         ddc = dal_ddc_service_get_ddc_pin(link->ddc);
 416
 417         if (!ddc) {
 418                 BREAK_TO_DEBUGGER();
 419                 return present;
 420         }
 421
 422         /* Open GPIO and set it to I2C mode */
 423         /* Note: this GpioMode_Input will be converted
 424          * to GpioConfigType_I2cAuxDualMode in GPIO component,
 425          * which indicates we need additional delay
 426          */
 427
 428         if (dal_ddc_open(ddc, GPIO_MODE_INPUT,
 429                          GPIO_DDC_CONFIG_TYPE_MODE_I2C) != GPIO_RESULT_OK) {
 430                 dal_ddc_close(ddc);
 431
 432                 return present;
 433         }
 434
 435         /*
 436          * Read GPIO: DP sink is present if both clock and data pins are zero
 437          *
 438          * [W/A] plug-unplug DP cable, sometimes customer board has
 439          * one short pulse on clk_pin(1V, < 1ms). DP will be config to HDMI/DVI
 440          * then monitor can't br light up. Add retry 3 times
 441          * But in real passive dongle, it need additional 3ms to detect
 442          */
 443         do {
 444                 gpio_result = dal_gpio_get_value(ddc->pin_clock, &clock_pin);
 445                 ASSERT(gpio_result == GPIO_RESULT_OK);
 446                 if (clock_pin)
 447                         udelay(1000);
 448                 else
 449                         break;
 450         } while (retry++ < 3);
 451
 452         present = (gpio_result == GPIO_RESULT_OK) && !clock_pin;
 453
 454         dal_ddc_close(ddc);
 455
 456         return present;
 457 }
 458
 459 /*
 460  * @brief
 461  * Detect output sink type
 462  */
 463 static enum signal_type link_detect_sink(struct dc_link *link,
 464                                          enum dc_detect_reason reason)
 465 {
 466         enum signal_type result;
 467         struct graphics_object_id enc_id;
 468
 469         if (link->is_dig_mapping_flexible)
 470                 enc_id = (struct graphics_object_id){.id = ENCODER_ID_UNKNOWN};
 471         else
 472                 enc_id = link->link_enc->id;
 473         result = get_basic_signal_type(enc_id, link->link_id);
 474
 475         /* Use basic signal type for link without physical connector. */
 476         if (link->ep_type != DISPLAY_ENDPOINT_PHY)
 477                 return result;
 478
 479         /* Internal digital encoder will detect only dongles
 480          * that require digital signal
 481          */
 482
 483         /* Detection mechanism is different
 484          * for different native connectors.
 485          * LVDS connector supports only LVDS signal;
 486          * PCIE is a bus slot, the actual connector needs to be detected first;
 487          * eDP connector supports only eDP signal;
 488          * HDMI should check straps for audio
 489          */
 490
 491         /* PCIE detects the actual connector on add-on board */
 492         if (link->link_id.id == CONNECTOR_ID_PCIE) {
 493                 /* ZAZTODO implement PCIE add-on card detection */
 494         }
 495
 496         switch (link->link_id.id) {
 497         case CONNECTOR_ID_HDMI_TYPE_A: {
 498                 /* check audio support:
 499                  * if native HDMI is not supported, switch to DVI
 500                  */
 501                 struct audio_support *aud_support =
 502                                         &link->dc->res_pool->audio_support;
 503
 504                 if (!aud_support->hdmi_audio_native)
 505                         if (link->link_id.id == CONNECTOR_ID_HDMI_TYPE_A)
 506                                 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
 507         }
 508         break;
 509         case CONNECTOR_ID_DISPLAY_PORT: {
 510                 /* DP HPD short pulse. Passive DP dongle will not
 511                  * have short pulse
 512                  */
 513                 if (reason != DETECT_REASON_HPDRX) {
 514                         /* Check whether DP signal detected: if not -
 515                          * we assume signal is DVI; it could be corrected
 516                          * to HDMI after dongle detection
 517                          */
 518                         if (!dm_helpers_is_dp_sink_present(link))
 519                                 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
 520                 }
 521         }
 522         break;
 523         default:
 524         break;
 525         }
 526
 527         return result;
 528 }
 529
 530 static enum signal_type decide_signal_from_strap_and_dongle_type(enum display_dongle_type dongle_type,
 531                                                                  struct audio_support *audio_support)
 532 {
 533         enum signal_type signal = SIGNAL_TYPE_NONE;
 534
 535         switch (dongle_type) {
 536         case DISPLAY_DONGLE_DP_HDMI_DONGLE:
 537                 if (audio_support->hdmi_audio_on_dongle)
 538                         signal = SIGNAL_TYPE_HDMI_TYPE_A;
 539                 else
 540                         signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 541                 break;
 542         case DISPLAY_DONGLE_DP_DVI_DONGLE:
 543                 signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 544                 break;
 545         case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
 546                 if (audio_support->hdmi_audio_native)
 547                         signal =  SIGNAL_TYPE_HDMI_TYPE_A;
 548                 else
 549                         signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 550                 break;
 551         default:
 552                 signal = SIGNAL_TYPE_NONE;
 553                 break;
 554         }
 555
 556         return signal;
 557 }
 558
 559 static enum signal_type dp_passive_dongle_detection(struct ddc_service *ddc,
 560                                                     struct display_sink_capability *sink_cap,
 561                                                     struct audio_support *audio_support)
 562 {
 563         dal_ddc_service_i2c_query_dp_dual_mode_adaptor(ddc, sink_cap);
 564
 565         return decide_signal_from_strap_and_dongle_type(sink_cap->dongle_type,
 566                                                         audio_support);
 567 }
 568
 569 static void link_disconnect_sink(struct dc_link *link)
 570 {
 571         if (link->local_sink) {
 572                 dc_sink_release(link->local_sink);
 573                 link->local_sink = NULL;
 574         }
 575
 576         link->dpcd_sink_count = 0;
 577         //link->dpcd_caps.dpcd_rev.raw = 0;
 578 }
 579
 580 static void link_disconnect_remap(struct dc_sink *prev_sink, struct dc_link *link)
 581 {
 582         dc_sink_release(link->local_sink);
 583         link->local_sink = prev_sink;
 584 }
 585
 586 #if defined(CONFIG_DRM_AMD_DC_HDCP)
 587 bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal)
 588 {
 589         bool ret = false;
 590
 591         switch (signal) {
 592         case SIGNAL_TYPE_DISPLAY_PORT:
 593         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 594                 ret = link->hdcp_caps.bcaps.bits.HDCP_CAPABLE;
 595                 break;
 596         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 597         case SIGNAL_TYPE_DVI_DUAL_LINK:
 598         case SIGNAL_TYPE_HDMI_TYPE_A:
 599         /* HDMI doesn't tell us its HDCP(1.4) capability, so assume to always be capable,
 600          * we can poll for bksv but some displays have an issue with this. Since its so rare
 601          * for a display to not be 1.4 capable, this assumtion is ok
 602          */
 603                 ret = true;
 604                 break;
 605         default:
 606                 break;
 607         }
 608         return ret;
 609 }
 610
 611 bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal)
 612 {
 613         bool ret = false;
 614
 615         switch (signal) {
 616         case SIGNAL_TYPE_DISPLAY_PORT:
 617         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 618                 ret = (link->hdcp_caps.bcaps.bits.HDCP_CAPABLE &&
 619                                 link->hdcp_caps.rx_caps.fields.byte0.hdcp_capable &&
 620                                 (link->hdcp_caps.rx_caps.fields.version == 0x2)) ? 1 : 0;
 621                 break;
 622         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 623         case SIGNAL_TYPE_DVI_DUAL_LINK:
 624         case SIGNAL_TYPE_HDMI_TYPE_A:
 625                 ret = (link->hdcp_caps.rx_caps.fields.version == 0x4) ? 1:0;
 626                 break;
 627         default:
 628                 break;
 629         }
 630
 631         return ret;
 632 }
 633
 634 static void query_hdcp_capability(enum signal_type signal, struct dc_link *link)
 635 {
 636         struct hdcp_protection_message msg22;
 637         struct hdcp_protection_message msg14;
 638
 639         memset(&msg22, 0, sizeof(struct hdcp_protection_message));
 640         memset(&msg14, 0, sizeof(struct hdcp_protection_message));
 641         memset(link->hdcp_caps.rx_caps.raw, 0,
 642                 sizeof(link->hdcp_caps.rx_caps.raw));
 643
 644         if ((link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
 645                         link->ddc->transaction_type ==
 646                         DDC_TRANSACTION_TYPE_I2C_OVER_AUX) ||
 647                         link->connector_signal == SIGNAL_TYPE_EDP) {
 648                 msg22.data = link->hdcp_caps.rx_caps.raw;
 649                 msg22.length = sizeof(link->hdcp_caps.rx_caps.raw);
 650                 msg22.msg_id = HDCP_MESSAGE_ID_RX_CAPS;
 651         } else {
 652                 msg22.data = &link->hdcp_caps.rx_caps.fields.version;
 653                 msg22.length = sizeof(link->hdcp_caps.rx_caps.fields.version);
 654                 msg22.msg_id = HDCP_MESSAGE_ID_HDCP2VERSION;
 655         }
 656         msg22.version = HDCP_VERSION_22;
 657         msg22.link = HDCP_LINK_PRIMARY;
 658         msg22.max_retries = 5;
 659         dc_process_hdcp_msg(signal, link, &msg22);
 660
 661         if (signal == SIGNAL_TYPE_DISPLAY_PORT || signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
 662                 msg14.data = &link->hdcp_caps.bcaps.raw;
 663                 msg14.length = sizeof(link->hdcp_caps.bcaps.raw);
 664                 msg14.msg_id = HDCP_MESSAGE_ID_READ_BCAPS;
 665                 msg14.version = HDCP_VERSION_14;
 666                 msg14.link = HDCP_LINK_PRIMARY;
 667                 msg14.max_retries = 5;
 668
 669                 dc_process_hdcp_msg(signal, link, &msg14);
 670         }
 671
 672 }
 673 #endif
 674
 675 static void read_current_link_settings_on_detect(struct dc_link *link)
 676 {
 677         union lane_count_set lane_count_set = {0};
 678         uint8_t link_bw_set;
 679         uint8_t link_rate_set;
 680         uint32_t read_dpcd_retry_cnt = 10;
 681         enum dc_status status = DC_ERROR_UNEXPECTED;
 682         int i;
 683         union max_down_spread max_down_spread = {0};
 684
 685         // Read DPCD 00101h to find out the number of lanes currently set
 686         for (i = 0; i < read_dpcd_retry_cnt; i++) {
 687                 status = core_link_read_dpcd(link,
 688                                              DP_LANE_COUNT_SET,
 689                                              &lane_count_set.raw,
 690                                              sizeof(lane_count_set));
 691                 /* First DPCD read after VDD ON can fail if the particular board
 692                  * does not have HPD pin wired correctly. So if DPCD read fails,
 693                  * which it should never happen, retry a few times. Target worst
 694                  * case scenario of 80 ms.
 695                  */
 696                 if (status == DC_OK) {
 697                         link->cur_link_settings.lane_count =
 698                                         lane_count_set.bits.LANE_COUNT_SET;
 699                         break;
 700                 }
 701
 702                 msleep(8);
 703         }
 704
 705         // Read DPCD 00100h to find if standard link rates are set
 706         core_link_read_dpcd(link, DP_LINK_BW_SET,
 707                             &link_bw_set, sizeof(link_bw_set));
 708
 709         if (link_bw_set == 0) {
 710                 if (link->connector_signal == SIGNAL_TYPE_EDP) {
 711                         /* If standard link rates are not being used,
 712                          * Read DPCD 00115h to find the edp link rate set used
 713                          */
 714                         core_link_read_dpcd(link, DP_LINK_RATE_SET,
 715                                             &link_rate_set, sizeof(link_rate_set));
 716
 717                         // edp_supported_link_rates_count = 0 for DP
 718                         if (link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) {
 719                                 link->cur_link_settings.link_rate =
 720                                         link->dpcd_caps.edp_supported_link_rates[link_rate_set];
 721                                 link->cur_link_settings.link_rate_set = link_rate_set;
 722                                 link->cur_link_settings.use_link_rate_set = true;
 723                         }
 724                 } else {
 725                         // Link Rate not found. Seamless boot may not work.
 726                         ASSERT(false);
 727                 }
 728         } else {
 729                 link->cur_link_settings.link_rate = link_bw_set;
 730                 link->cur_link_settings.use_link_rate_set = false;
 731         }
 732         // Read DPCD 00003h to find the max down spread.
 733         core_link_read_dpcd(link, DP_MAX_DOWNSPREAD,
 734                             &max_down_spread.raw, sizeof(max_down_spread));
 735         link->cur_link_settings.link_spread =
 736                 max_down_spread.bits.MAX_DOWN_SPREAD ?
 737                 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
 738 }
 739
 740 static bool detect_dp(struct dc_link *link,
 741                       struct display_sink_capability *sink_caps,
 742                       enum dc_detect_reason reason)
 743 {
 744         struct audio_support *audio_support = &link->dc->res_pool->audio_support;
 745
 746         sink_caps->signal = link_detect_sink(link, reason);
 747         sink_caps->transaction_type =
 748                 get_ddc_transaction_type(sink_caps->signal);
 749
 750         if (sink_caps->transaction_type == DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
 751                 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
 752                 if (!detect_dp_sink_caps(link))
 753                         return false;
 754                 if (is_mst_supported(link)) {
 755                         sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
 756                         link->type = dc_connection_mst_branch;
 757
 758                         dal_ddc_service_set_transaction_type(link->ddc,
 759                                                              sink_caps->transaction_type);
 760
 761 #if defined(CONFIG_DRM_AMD_DC_HDCP)
 762                         /* In case of fallback to SST when topology discovery below fails
 763                          * HDCP caps will be querried again later by the upper layer (caller
 764                          * of this function). */
 765                         query_hdcp_capability(SIGNAL_TYPE_DISPLAY_PORT_MST, link);
 766 #endif
 767                 }
 768
 769                 if (link->type != dc_connection_mst_branch &&
 770                                 is_dp_branch_device(link))
 771                         /* DP SST branch */
 772                         link->type = dc_connection_sst_branch;
 773         } else {
 774                 /* DP passive dongles */
 775                 sink_caps->signal = dp_passive_dongle_detection(link->ddc,
 776                                                                 sink_caps,
 777                                                                 audio_support);
 778                 link->dpcd_caps.dongle_type = sink_caps->dongle_type;
 779                 link->dpcd_caps.dpcd_rev.raw = 0;
 780         }
 781
 782         return true;
 783 }
 784
 785 static bool is_same_edid(struct dc_edid *old_edid, struct dc_edid *new_edid)
 786 {
 787         if (old_edid->length != new_edid->length)
 788                 return false;
 789
 790         if (new_edid->length == 0)
 791                 return false;
 792
 793         return (memcmp(old_edid->raw_edid,
 794                        new_edid->raw_edid, new_edid->length) == 0);
 795 }
 796
 797 static bool wait_for_entering_dp_alt_mode(struct dc_link *link)
 798 {
 799         /**
 800          * something is terribly wrong if time out is > 200ms. (5Hz)
 801          * 500 microseconds * 400 tries us 200 ms
 802          **/
 803         unsigned int sleep_time_in_microseconds = 500;
 804         unsigned int tries_allowed = 400;
 805         bool is_in_alt_mode;
 806         unsigned long long enter_timestamp;
 807         unsigned long long finish_timestamp;
 808         unsigned long long time_taken_in_ns;
 809         int tries_taken;
 810
 811         DC_LOGGER_INIT(link->ctx->logger);
 812
 813         if (!link->link_enc->funcs->is_in_alt_mode)
 814                 return true;
 815
 816         is_in_alt_mode = link->link_enc->funcs->is_in_alt_mode(link->link_enc);
 817         DC_LOG_WARNING("DP Alt mode state on HPD: %d\n", is_in_alt_mode);
 818
 819         if (is_in_alt_mode)
 820                 return true;
 821
 822         enter_timestamp = dm_get_timestamp(link->ctx);
 823
 824         for (tries_taken = 0; tries_taken < tries_allowed; tries_taken++) {
 825                 udelay(sleep_time_in_microseconds);
 826                 /* ask the link if alt mode is enabled, if so return ok */
 827                 if (link->link_enc->funcs->is_in_alt_mode(link->link_enc)) {
 828                         finish_timestamp = dm_get_timestamp(link->ctx);
 829                         time_taken_in_ns =
 830                                 dm_get_elapse_time_in_ns(link->ctx,
 831                                                          finish_timestamp,
 832                                                          enter_timestamp);
 833                         DC_LOG_WARNING("Alt mode entered finished after %llu ms\n",
 834                                        div_u64(time_taken_in_ns, 1000000));
 835                         return true;
 836                 }
 837         }
 838         finish_timestamp = dm_get_timestamp(link->ctx);
 839         time_taken_in_ns = dm_get_elapse_time_in_ns(link->ctx, finish_timestamp,
 840                                                     enter_timestamp);
 841         DC_LOG_WARNING("Alt mode has timed out after %llu ms\n",
 842                        div_u64(time_taken_in_ns, 1000000));
 843         return false;
 844 }
 845
 846 /*
 847  * dc_link_detect() - Detect if a sink is attached to a given link
 848  *
 849  * link->local_sink is created or destroyed as needed.
 850  *
 851  * This does not create remote sinks but will trigger DM
 852  * to start MST detection if a branch is detected.
 853  */
 854 static bool dc_link_detect_helper(struct dc_link *link,
 855                                   enum dc_detect_reason reason)
 856 {
 857         struct dc_sink_init_data sink_init_data = { 0 };
 858         struct display_sink_capability sink_caps = { 0 };
 859         uint32_t i;
 860         bool converter_disable_audio = false;
 861         struct audio_support *aud_support = &link->dc->res_pool->audio_support;
 862         bool same_edid = false;
 863         enum dc_edid_status edid_status;
 864         struct dc_context *dc_ctx = link->ctx;
 865         struct dc_sink *sink = NULL;
 866         struct dc_sink *prev_sink = NULL;
 867         struct dpcd_caps prev_dpcd_caps;
 868         enum dc_connection_type new_connection_type = dc_connection_none;
 869         enum dc_connection_type pre_connection_type = dc_connection_none;
 870         bool perform_dp_seamless_boot = false;
 871         const uint32_t post_oui_delay = 30; // 30ms
 872
 873         DC_LOGGER_INIT(link->ctx->logger);
 874
 875         if (dc_is_virtual_signal(link->connector_signal))
 876                 return false;
 877
 878         if (((link->connector_signal == SIGNAL_TYPE_LVDS ||
 879                 link->connector_signal == SIGNAL_TYPE_EDP) &&
 880                 (!link->dc->config.allow_edp_hotplug_detection)) &&
 881                 link->local_sink) {
 882                 // need to re-write OUI and brightness in resume case
 883                 if (link->connector_signal == SIGNAL_TYPE_EDP) {
 884                         dpcd_set_source_specific_data(link);
 885                         msleep(post_oui_delay);
 886                         dc_link_set_default_brightness_aux(link);
 887                         //TODO: use cached
 888                 }
 889
 890                 return true;
 891         }
 892
 893         if (!dc_link_detect_sink(link, &new_connection_type)) {
 894                 BREAK_TO_DEBUGGER();
 895                 return false;
 896         }
 897
 898         prev_sink = link->local_sink;
 899         if (prev_sink) {
 900                 dc_sink_retain(prev_sink);
 901                 memcpy(&prev_dpcd_caps, &link->dpcd_caps, sizeof(struct dpcd_caps));
 902         }
 903
 904         link_disconnect_sink(link);
 905         if (new_connection_type != dc_connection_none) {
 906                 pre_connection_type = link->type;
 907                 link->type = new_connection_type;
 908                 link->link_state_valid = false;
 909
 910                 /* From Disconnected-to-Connected. */
 911                 switch (link->connector_signal) {
 912                 case SIGNAL_TYPE_HDMI_TYPE_A: {
 913                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 914                         if (aud_support->hdmi_audio_native)
 915                                 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
 916                         else
 917                                 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 918                         break;
 919                 }
 920
 921                 case SIGNAL_TYPE_DVI_SINGLE_LINK: {
 922                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 923                         sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 924                         break;
 925                 }
 926
 927                 case SIGNAL_TYPE_DVI_DUAL_LINK: {
 928                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 929                         sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
 930                         break;
 931                 }
 932
 933                 case SIGNAL_TYPE_LVDS: {
 934                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 935                         sink_caps.signal = SIGNAL_TYPE_LVDS;
 936                         break;
 937                 }
 938
 939                 case SIGNAL_TYPE_EDP: {
 940                         read_current_link_settings_on_detect(link);
 941
 942                         detect_edp_sink_caps(link);
 943                         read_current_link_settings_on_detect(link);
 944                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 945                         sink_caps.signal = SIGNAL_TYPE_EDP;
 946                         break;
 947                 }
 948
 949                 case SIGNAL_TYPE_DISPLAY_PORT: {
 950                         /* wa HPD high coming too early*/
 951                         if (link->ep_type == DISPLAY_ENDPOINT_PHY &&
 952                             link->link_enc->features.flags.bits.DP_IS_USB_C == 1) {
 953                                 /* if alt mode times out, return false */
 954                                 if (!wait_for_entering_dp_alt_mode(link))
 955                                         return false;
 956                         }
 957
 958                         if (!detect_dp(link, &sink_caps, reason)) {
 959                                 if (prev_sink)
 960                                         dc_sink_release(prev_sink);
 961                                 return false;
 962                         }
 963
 964 #if defined(CONFIG_DRM_AMD_DC_DCN)
 965                         if (dp_get_link_encoding_format(&link->reported_link_cap) == DP_128b_132b_ENCODING)
 966                                 add_dp_hpo_link_encoder_to_link(link);
 967 #endif
 968
 969                         if (link->type == dc_connection_mst_branch) {
 970                                 LINK_INFO("link=%d, mst branch is now Connected\n",
 971                                           link->link_index);
 972                                 /* Need to setup mst link_cap struct here
 973                                  * otherwise dc_link_detect() will leave mst link_cap
 974                                  * empty which leads to allocate_mst_payload() has "0"
 975                                  * pbn_per_slot value leading to exception on dc_fixpt_div()
 976                                  */
 977                                 dp_verify_mst_link_cap(link);
 978
 979                                 /*
 980                                  * This call will initiate MST topology discovery. Which
 981                                  * will detect MST ports and add new DRM connector DRM
 982                                  * framework. Then read EDID via remote i2c over aux. In
 983                                  * the end, will notify DRM detect result and save EDID
 984                                  * into DRM framework.
 985                                  *
 986                                  * .detect is called by .fill_modes.
 987                                  * .fill_modes is called by user mode ioctl
 988                                  * DRM_IOCTL_MODE_GETCONNECTOR.
 989                                  *
 990                                  * .get_modes is called by .fill_modes.
 991                                  *
 992                                  * call .get_modes, AMDGPU DM implementation will create
 993                                  * new dc_sink and add to dc_link. For long HPD plug
 994                                  * in/out, MST has its own handle.
 995                                  *
 996                                  * Therefore, just after dc_create, link->sink is not
 997                                  * created for MST until user mode app calls
 998                                  * DRM_IOCTL_MODE_GETCONNECTOR.
 999                                  *
1000                                  * Need check ->sink usages in case ->sink = NULL
1001                                  * TODO: s3 resume check
1002                                  */
1003
1004                                 dm_helpers_dp_update_branch_info(link->ctx, link);
1005                                 if (dm_helpers_dp_mst_start_top_mgr(link->ctx,
1006                                                 link, reason == DETECT_REASON_BOOT)) {
1007                                         if (prev_sink)
1008                                                 dc_sink_release(prev_sink);
1009                                         return false;
1010                                 } else {
1011                                         link->type = dc_connection_sst_branch;
1012                                         sink_caps.signal = SIGNAL_TYPE_DISPLAY_PORT;
1013                                 }
1014                         }
1015
1016                         /* Active SST downstream branch device unplug*/
1017                         if (link->type == dc_connection_sst_branch &&
1018                             link->dpcd_caps.sink_count.bits.SINK_COUNT == 0) {
1019                                 if (prev_sink)
1020                                         /* Downstream unplug */
1021                                         dc_sink_release(prev_sink);
1022                                 return true;
1023                         }
1024
1025                         /* disable audio for non DP to HDMI active sst converter */
1026                         if (link->type == dc_connection_sst_branch &&
1027                                         is_dp_active_dongle(link) &&
1028                                         (link->dpcd_caps.dongle_type !=
1029                                                         DISPLAY_DONGLE_DP_HDMI_CONVERTER))
1030                                 converter_disable_audio = true;
1031
1032                         // link switch from MST to non-MST stop topology manager
1033                         if (pre_connection_type == dc_connection_mst_branch &&
1034                                         link->type != dc_connection_mst_branch)
1035                                 dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
1036
1037
1038                         // For seamless boot, to skip verify link cap, we read UEFI settings and set them as verified.
1039                         if (reason == DETECT_REASON_BOOT &&
1040                                         !dc_ctx->dc->config.power_down_display_on_boot &&
1041                                         link->link_status.link_active)
1042                                 perform_dp_seamless_boot = true;
1043
1044                         if (perform_dp_seamless_boot) {
1045                                 read_current_link_settings_on_detect(link);
1046                                 link->verified_link_cap = link->reported_link_cap;
1047                         }
1048
1049                         break;
1050                 }
1051
1052                 default:
1053                         DC_ERROR("Invalid connector type! signal:%d\n",
1054                                  link->connector_signal);
1055                         if (prev_sink)
1056                                 dc_sink_release(prev_sink);
1057                         return false;
1058                 } /* switch() */
1059
1060                 if (link->dpcd_caps.sink_count.bits.SINK_COUNT)
1061                         link->dpcd_sink_count =
1062                                 link->dpcd_caps.sink_count.bits.SINK_COUNT;
1063                 else
1064                         link->dpcd_sink_count = 1;
1065
1066                 dal_ddc_service_set_transaction_type(link->ddc,
1067                                                      sink_caps.transaction_type);
1068
1069                 link->aux_mode =
1070                         dal_ddc_service_is_in_aux_transaction_mode(link->ddc);
1071
1072                 sink_init_data.link = link;
1073                 sink_init_data.sink_signal = sink_caps.signal;
1074
1075                 sink = dc_sink_create(&sink_init_data);
1076                 if (!sink) {
1077                         DC_ERROR("Failed to create sink!\n");
1078                         if (prev_sink)
1079                                 dc_sink_release(prev_sink);
1080                         return false;
1081                 }
1082
1083                 sink->link->dongle_max_pix_clk = sink_caps.max_hdmi_pixel_clock;
1084                 sink->converter_disable_audio = converter_disable_audio;
1085
1086                 /* dc_sink_create returns a new reference */
1087                 link->local_sink = sink;
1088
1089                 edid_status = dm_helpers_read_local_edid(link->ctx,
1090                                                          link, sink);
1091
1092                 switch (edid_status) {
1093                 case EDID_BAD_CHECKSUM:
1094                         DC_LOG_ERROR("EDID checksum invalid.\n");
1095                         break;
1096                 case EDID_NO_RESPONSE:
1097                         DC_LOG_ERROR("No EDID read.\n");
1098                         /*
1099                          * Abort detection for non-DP connectors if we have
1100                          * no EDID
1101                          *
1102                          * DP needs to report as connected if HDP is high
1103                          * even if we have no EDID in order to go to
1104                          * fail-safe mode
1105                          */
1106                         if (dc_is_hdmi_signal(link->connector_signal) ||
1107                             dc_is_dvi_signal(link->connector_signal)) {
1108                                 if (prev_sink)
1109                                         dc_sink_release(prev_sink);
1110
1111                                 return false;
1112                         }
1113                         break;
1114                 default:
1115                         break;
1116                 }
1117
1118                 // Check if edid is the same
1119                 if ((prev_sink) &&
1120                     (edid_status == EDID_THE_SAME || edid_status == EDID_OK))
1121                         same_edid = is_same_edid(&prev_sink->dc_edid,
1122                                                  &sink->dc_edid);
1123
1124                 if (sink->edid_caps.panel_patch.skip_scdc_overwrite)
1125                         link->ctx->dc->debug.hdmi20_disable = true;
1126
1127                 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
1128                     sink_caps.transaction_type ==
1129                     DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
1130                         /*
1131                          * TODO debug why Dell 2413 doesn't like
1132                          *  two link trainings
1133                          */
1134 #if defined(CONFIG_DRM_AMD_DC_HDCP)
1135                         query_hdcp_capability(sink->sink_signal, link);
1136 #endif
1137
1138                         // verify link cap for SST non-seamless boot
1139                         if (!perform_dp_seamless_boot)
1140                                 dp_verify_link_cap_with_retries(link,
1141                                                                 &link->reported_link_cap,
1142                                                                 LINK_TRAINING_MAX_VERIFY_RETRY);
1143                 } else {
1144                         // If edid is the same, then discard new sink and revert back to original sink
1145                         if (same_edid) {
1146                                 link_disconnect_remap(prev_sink, link);
1147                                 sink = prev_sink;
1148                                 prev_sink = NULL;
1149                         }
1150 #if defined(CONFIG_DRM_AMD_DC_HDCP)
1151                         query_hdcp_capability(sink->sink_signal, link);
1152 #endif
1153                 }
1154
1155                 /* HDMI-DVI Dongle */
1156                 if (sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A &&
1157                     !sink->edid_caps.edid_hdmi)
1158                         sink->sink_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1159
1160                 /* Connectivity log: detection */
1161                 for (i = 0; i < sink->dc_edid.length / DC_EDID_BLOCK_SIZE; i++) {
1162                         CONN_DATA_DETECT(link,
1163                                          &sink->dc_edid.raw_edid[i * DC_EDID_BLOCK_SIZE],
1164                                          DC_EDID_BLOCK_SIZE,
1165                                          "%s: [Block %d] ", sink->edid_caps.display_name, i);
1166                 }
1167
1168                 DC_LOG_DETECTION_EDID_PARSER("%s: "
1169                         "manufacturer_id = %X, "
1170                         "product_id = %X, "
1171                         "serial_number = %X, "
1172                         "manufacture_week = %d, "
1173                         "manufacture_year = %d, "
1174                         "display_name = %s, "
1175                         "speaker_flag = %d, "
1176                         "audio_mode_count = %d\n",
1177                         __func__,
1178                         sink->edid_caps.manufacturer_id,
1179                         sink->edid_caps.product_id,
1180                         sink->edid_caps.serial_number,
1181                         sink->edid_caps.manufacture_week,
1182                         sink->edid_caps.manufacture_year,
1183                         sink->edid_caps.display_name,
1184                         sink->edid_caps.speaker_flags,
1185                         sink->edid_caps.audio_mode_count);
1186
1187                 for (i = 0; i < sink->edid_caps.audio_mode_count; i++) {
1188                         DC_LOG_DETECTION_EDID_PARSER("%s: mode number = %d, "
1189                                 "format_code = %d, "
1190                                 "channel_count = %d, "
1191                                 "sample_rate = %d, "
1192                                 "sample_size = %d\n",
1193                                 __func__,
1194                                 i,
1195                                 sink->edid_caps.audio_modes[i].format_code,
1196                                 sink->edid_caps.audio_modes[i].channel_count,
1197                                 sink->edid_caps.audio_modes[i].sample_rate,
1198                                 sink->edid_caps.audio_modes[i].sample_size);
1199                 }
1200         } else {
1201                 /* From Connected-to-Disconnected. */
1202                 if (link->type == dc_connection_mst_branch) {
1203                         LINK_INFO("link=%d, mst branch is now Disconnected\n",
1204                                   link->link_index);
1205
1206                         dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
1207
1208                         link->mst_stream_alloc_table.stream_count = 0;
1209                         memset(link->mst_stream_alloc_table.stream_allocations,
1210                                0,
1211                                sizeof(link->mst_stream_alloc_table.stream_allocations));
1212                 }
1213
1214 #if defined(CONFIG_DRM_AMD_DC_DCN)
1215                 if (dp_get_link_encoding_format(&link->cur_link_settings) == DP_128b_132b_ENCODING)
1216                         reset_dp_hpo_stream_encoders_for_link(link);
1217 #endif
1218
1219                 link->type = dc_connection_none;
1220                 sink_caps.signal = SIGNAL_TYPE_NONE;
1221                 /* When we unplug a passive DP-HDMI dongle connection, dongle_max_pix_clk
1222                  *  is not cleared. If we emulate a DP signal on this connection, it thinks
1223                  *  the dongle is still there and limits the number of modes we can emulate.
1224                  *  Clear dongle_max_pix_clk on disconnect to fix this
1225                  */
1226                 link->dongle_max_pix_clk = 0;
1227         }
1228
1229         LINK_INFO("link=%d, dc_sink_in=%p is now %s prev_sink=%p edid same=%d\n",
1230                   link->link_index, sink,
1231                   (sink_caps.signal ==
1232                    SIGNAL_TYPE_NONE ? "Disconnected" : "Connected"),
1233                   prev_sink, same_edid);
1234
1235         if (prev_sink)
1236                 dc_sink_release(prev_sink);
1237
1238         return true;
1239 }
1240
1241 bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
1242 {
1243         const struct dc *dc = link->dc;
1244         bool ret;
1245         bool can_apply_seamless_boot = false;
1246         int i;
1247
1248         for (i = 0; i < dc->current_state->stream_count; i++) {
1249                 if (dc->current_state->streams[i]->apply_seamless_boot_optimization) {
1250                         can_apply_seamless_boot = true;
1251                         break;
1252                 }
1253         }
1254
1255 #if defined(CONFIG_DRM_AMD_DC_DCN)
1256         dc_z10_restore(dc);
1257 #endif
1258
1259         /* get out of low power state */
1260         if (!can_apply_seamless_boot && reason != DETECT_REASON_BOOT)
1261                 clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr);
1262
1263         ret = dc_link_detect_helper(link, reason);
1264
1265         /* Go back to power optimized state */
1266         if (!can_apply_seamless_boot && reason != DETECT_REASON_BOOT)
1267                 clk_mgr_optimize_pwr_state(dc, dc->clk_mgr);
1268
1269         return ret;
1270 }
1271
1272 bool dc_link_get_hpd_state(struct dc_link *dc_link)
1273 {
1274         uint32_t state;
1275
1276         dal_gpio_lock_pin(dc_link->hpd_gpio);
1277         dal_gpio_get_value(dc_link->hpd_gpio, &state);
1278         dal_gpio_unlock_pin(dc_link->hpd_gpio);
1279
1280         return state;
1281 }
1282
1283 static enum hpd_source_id get_hpd_line(struct dc_link *link)
1284 {
1285         struct gpio *hpd;
1286         enum hpd_source_id hpd_id = HPD_SOURCEID_UNKNOWN;
1287
1288         hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
1289                            link->ctx->gpio_service);
1290
1291         if (hpd) {
1292                 switch (dal_irq_get_source(hpd)) {
1293                 case DC_IRQ_SOURCE_HPD1:
1294                         hpd_id = HPD_SOURCEID1;
1295                 break;
1296                 case DC_IRQ_SOURCE_HPD2:
1297                         hpd_id = HPD_SOURCEID2;
1298                 break;
1299                 case DC_IRQ_SOURCE_HPD3:
1300                         hpd_id = HPD_SOURCEID3;
1301                 break;
1302                 case DC_IRQ_SOURCE_HPD4:
1303                         hpd_id = HPD_SOURCEID4;
1304                 break;
1305                 case DC_IRQ_SOURCE_HPD5:
1306                         hpd_id = HPD_SOURCEID5;
1307                 break;
1308                 case DC_IRQ_SOURCE_HPD6:
1309                         hpd_id = HPD_SOURCEID6;
1310                 break;
1311                 default:
1312                         BREAK_TO_DEBUGGER();
1313                 break;
1314                 }
1315
1316                 dal_gpio_destroy_irq(&hpd);
1317         }
1318
1319         return hpd_id;
1320 }
1321
1322 static enum channel_id get_ddc_line(struct dc_link *link)
1323 {
1324         struct ddc *ddc;
1325         enum channel_id channel = CHANNEL_ID_UNKNOWN;
1326
1327         ddc = dal_ddc_service_get_ddc_pin(link->ddc);
1328
1329         if (ddc) {
1330                 switch (dal_ddc_get_line(ddc)) {
1331                 case GPIO_DDC_LINE_DDC1:
1332                         channel = CHANNEL_ID_DDC1;
1333                         break;
1334                 case GPIO_DDC_LINE_DDC2:
1335                         channel = CHANNEL_ID_DDC2;
1336                         break;
1337                 case GPIO_DDC_LINE_DDC3:
1338                         channel = CHANNEL_ID_DDC3;
1339                         break;
1340                 case GPIO_DDC_LINE_DDC4:
1341                         channel = CHANNEL_ID_DDC4;
1342                         break;
1343                 case GPIO_DDC_LINE_DDC5:
1344                         channel = CHANNEL_ID_DDC5;
1345                         break;
1346                 case GPIO_DDC_LINE_DDC6:
1347                         channel = CHANNEL_ID_DDC6;
1348                         break;
1349                 case GPIO_DDC_LINE_DDC_VGA:
1350                         channel = CHANNEL_ID_DDC_VGA;
1351                         break;
1352                 case GPIO_DDC_LINE_I2C_PAD:
1353                         channel = CHANNEL_ID_I2C_PAD;
1354                         break;
1355                 default:
1356                         BREAK_TO_DEBUGGER();
1357                         break;
1358                 }
1359         }
1360
1361         return channel;
1362 }
1363
1364 static enum transmitter translate_encoder_to_transmitter(struct graphics_object_id encoder)
1365 {
1366         switch (encoder.id) {
1367         case ENCODER_ID_INTERNAL_UNIPHY:
1368                 switch (encoder.enum_id) {
1369                 case ENUM_ID_1:
1370                         return TRANSMITTER_UNIPHY_A;
1371                 case ENUM_ID_2:
1372                         return TRANSMITTER_UNIPHY_B;
1373                 default:
1374                         return TRANSMITTER_UNKNOWN;
1375                 }
1376         break;
1377         case ENCODER_ID_INTERNAL_UNIPHY1:
1378                 switch (encoder.enum_id) {
1379                 case ENUM_ID_1:
1380                         return TRANSMITTER_UNIPHY_C;
1381                 case ENUM_ID_2:
1382                         return TRANSMITTER_UNIPHY_D;
1383                 default:
1384                         return TRANSMITTER_UNKNOWN;
1385                 }
1386         break;
1387         case ENCODER_ID_INTERNAL_UNIPHY2:
1388                 switch (encoder.enum_id) {
1389                 case ENUM_ID_1:
1390                         return TRANSMITTER_UNIPHY_E;
1391                 case ENUM_ID_2:
1392                         return TRANSMITTER_UNIPHY_F;
1393                 default:
1394                         return TRANSMITTER_UNKNOWN;
1395                 }
1396         break;
1397         case ENCODER_ID_INTERNAL_UNIPHY3:
1398                 switch (encoder.enum_id) {
1399                 case ENUM_ID_1:
1400                         return TRANSMITTER_UNIPHY_G;
1401                 default:
1402                         return TRANSMITTER_UNKNOWN;
1403                 }
1404         break;
1405         case ENCODER_ID_EXTERNAL_NUTMEG:
1406                 switch (encoder.enum_id) {
1407                 case ENUM_ID_1:
1408                         return TRANSMITTER_NUTMEG_CRT;
1409                 default:
1410                         return TRANSMITTER_UNKNOWN;
1411                 }
1412         break;
1413         case ENCODER_ID_EXTERNAL_TRAVIS:
1414                 switch (encoder.enum_id) {
1415                 case ENUM_ID_1:
1416                         return TRANSMITTER_TRAVIS_CRT;
1417                 case ENUM_ID_2:
1418                         return TRANSMITTER_TRAVIS_LCD;
1419                 default:
1420                         return TRANSMITTER_UNKNOWN;
1421                 }
1422         break;
1423         default:
1424                 return TRANSMITTER_UNKNOWN;
1425         }
1426 }
1427
1428 static bool dc_link_construct_legacy(struct dc_link *link,
1429                                      const struct link_init_data *init_params)
1430 {
1431         uint8_t i;
1432         struct ddc_service_init_data ddc_service_init_data = { { 0 } };
1433         struct dc_context *dc_ctx = init_params->ctx;
1434         struct encoder_init_data enc_init_data = { 0 };
1435         struct panel_cntl_init_data panel_cntl_init_data = { 0 };
1436         struct integrated_info *info;
1437         struct dc_bios *bios = init_params->dc->ctx->dc_bios;
1438         const struct dc_vbios_funcs *bp_funcs = bios->funcs;
1439         struct bp_disp_connector_caps_info disp_connect_caps_info = { 0 };
1440
1441         DC_LOGGER_INIT(dc_ctx->logger);
1442
1443         info = kzalloc(sizeof(*info), GFP_KERNEL);
1444         if (!info)
1445                 goto create_fail;
1446
1447         link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1448         link->irq_source_hpd_rx = DC_IRQ_SOURCE_INVALID;
1449
1450         link->link_status.dpcd_caps = &link->dpcd_caps;
1451
1452         link->dc = init_params->dc;
1453         link->ctx = dc_ctx;
1454         link->link_index = init_params->link_index;
1455
1456         memset(&link->preferred_training_settings, 0,
1457                sizeof(struct dc_link_training_overrides));
1458         memset(&link->preferred_link_setting, 0,
1459                sizeof(struct dc_link_settings));
1460
1461         link->link_id =
1462                 bios->funcs->get_connector_id(bios, init_params->connector_index);
1463
1464         link->ep_type = DISPLAY_ENDPOINT_PHY;
1465
1466         DC_LOG_DC("BIOS object table - link_id: %d", link->link_id.id);
1467
1468         if (bios->funcs->get_disp_connector_caps_info) {
1469                 bios->funcs->get_disp_connector_caps_info(bios, link->link_id, &disp_connect_caps_info);
1470                 link->is_internal_display = disp_connect_caps_info.INTERNAL_DISPLAY;
1471                 DC_LOG_DC("BIOS object table - is_internal_display: %d", link->is_internal_display);
1472         }
1473
1474         if (link->link_id.type != OBJECT_TYPE_CONNECTOR) {
1475                 dm_output_to_console("%s: Invalid Connector ObjectID from Adapter Service for connector index:%d! type %d expected %d\n",
1476                                      __func__, init_params->connector_index,
1477                                      link->link_id.type, OBJECT_TYPE_CONNECTOR);
1478                 goto create_fail;
1479         }
1480
1481         if (link->dc->res_pool->funcs->link_init)
1482                 link->dc->res_pool->funcs->link_init(link);
1483
1484         link->hpd_gpio = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
1485                                       link->ctx->gpio_service);
1486
1487         if (link->hpd_gpio) {
1488                 dal_gpio_open(link->hpd_gpio, GPIO_MODE_INTERRUPT);
1489                 dal_gpio_unlock_pin(link->hpd_gpio);
1490                 link->irq_source_hpd = dal_irq_get_source(link->hpd_gpio);
1491
1492                 DC_LOG_DC("BIOS object table - hpd_gpio id: %d", link->hpd_gpio->id);
1493                 DC_LOG_DC("BIOS object table - hpd_gpio en: %d", link->hpd_gpio->en);
1494         }
1495
1496         switch (link->link_id.id) {
1497         case CONNECTOR_ID_HDMI_TYPE_A:
1498                 link->connector_signal = SIGNAL_TYPE_HDMI_TYPE_A;
1499
1500                 break;
1501         case CONNECTOR_ID_SINGLE_LINK_DVID:
1502         case CONNECTOR_ID_SINGLE_LINK_DVII:
1503                 link->connector_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1504                 break;
1505         case CONNECTOR_ID_DUAL_LINK_DVID:
1506         case CONNECTOR_ID_DUAL_LINK_DVII:
1507                 link->connector_signal = SIGNAL_TYPE_DVI_DUAL_LINK;
1508                 break;
1509         case CONNECTOR_ID_DISPLAY_PORT:
1510                 link->connector_signal = SIGNAL_TYPE_DISPLAY_PORT;
1511
1512                 if (link->hpd_gpio)
1513                         link->irq_source_hpd_rx =
1514                                         dal_irq_get_rx_source(link->hpd_gpio);
1515
1516                 break;
1517         case CONNECTOR_ID_EDP:
1518                 link->connector_signal = SIGNAL_TYPE_EDP;
1519
1520                 if (link->hpd_gpio) {
1521                         if (!link->dc->config.allow_edp_hotplug_detection)
1522                                 link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1523                         link->irq_source_hpd_rx =
1524                                         dal_irq_get_rx_source(link->hpd_gpio);
1525                 }
1526
1527                 break;
1528         case CONNECTOR_ID_LVDS:
1529                 link->connector_signal = SIGNAL_TYPE_LVDS;
1530                 break;
1531         default:
1532                 DC_LOG_WARNING("Unsupported Connector type:%d!\n",
1533                                link->link_id.id);
1534                 goto create_fail;
1535         }
1536
1537         /* TODO: #DAL3 Implement id to str function.*/
1538         LINK_INFO("Connector[%d] description:"
1539                   "signal %d\n",
1540                   init_params->connector_index,
1541                   link->connector_signal);
1542
1543         ddc_service_init_data.ctx = link->ctx;
1544         ddc_service_init_data.id = link->link_id;
1545         ddc_service_init_data.link = link;
1546         link->ddc = dal_ddc_service_create(&ddc_service_init_data);
1547
1548         if (!link->ddc) {
1549                 DC_ERROR("Failed to create ddc_service!\n");
1550                 goto ddc_create_fail;
1551         }
1552
1553         if (!link->ddc->ddc_pin) {
1554                 DC_ERROR("Failed to get I2C info for connector!\n");
1555                 goto ddc_create_fail;
1556         }
1557
1558         link->ddc_hw_inst =
1559                 dal_ddc_get_line(dal_ddc_service_get_ddc_pin(link->ddc));
1560
1561
1562         if (link->dc->res_pool->funcs->panel_cntl_create &&
1563                 (link->link_id.id == CONNECTOR_ID_EDP ||
1564                         link->link_id.id == CONNECTOR_ID_LVDS)) {
1565                 panel_cntl_init_data.ctx = dc_ctx;
1566                 panel_cntl_init_data.inst =
1567                         panel_cntl_init_data.ctx->dc_edp_id_count;
1568                 link->panel_cntl =
1569                         link->dc->res_pool->funcs->panel_cntl_create(
1570                                                                 &panel_cntl_init_data);
1571                 panel_cntl_init_data.ctx->dc_edp_id_count++;
1572
1573                 if (link->panel_cntl == NULL) {
1574                         DC_ERROR("Failed to create link panel_cntl!\n");
1575                         goto panel_cntl_create_fail;
1576                 }
1577         }
1578
1579         enc_init_data.ctx = dc_ctx;
1580         bp_funcs->get_src_obj(dc_ctx->dc_bios, link->link_id, 0,
1581                               &enc_init_data.encoder);
1582         enc_init_data.connector = link->link_id;
1583         enc_init_data.channel = get_ddc_line(link);
1584         enc_init_data.hpd_source = get_hpd_line(link);
1585
1586         link->hpd_src = enc_init_data.hpd_source;
1587
1588         enc_init_data.transmitter =
1589                 translate_encoder_to_transmitter(enc_init_data.encoder);
1590         link->link_enc =
1591                 link->dc->res_pool->funcs->link_enc_create(&enc_init_data);
1592
1593         if (!link->link_enc) {
1594                 DC_ERROR("Failed to create link encoder!\n");
1595                 goto link_enc_create_fail;
1596         }
1597
1598         DC_LOG_DC("BIOS object table - DP_IS_USB_C: %d", link->link_enc->features.flags.bits.DP_IS_USB_C);
1599 #if defined(CONFIG_DRM_AMD_DC_DCN)
1600         DC_LOG_DC("BIOS object table - IS_DP2_CAPABLE: %d", link->link_enc->features.flags.bits.IS_DP2_CAPABLE);
1601 #endif
1602
1603         /* Update link encoder tracking variables. These are used for the dynamic
1604          * assignment of link encoders to streams.
1605          */
1606         link->eng_id = link->link_enc->preferred_engine;
1607         link->dc->res_pool->link_encoders[link->eng_id - ENGINE_ID_DIGA] = link->link_enc;
1608         link->dc->res_pool->dig_link_enc_count++;
1609
1610         link->link_enc_hw_inst = link->link_enc->transmitter;
1611
1612         for (i = 0; i < 4; i++) {
1613                 if (bp_funcs->get_device_tag(dc_ctx->dc_bios,
1614                                              link->link_id, i,
1615                                              &link->device_tag) != BP_RESULT_OK) {
1616                         DC_ERROR("Failed to find device tag!\n");
1617                         goto device_tag_fail;
1618                 }
1619
1620                 /* Look for device tag that matches connector signal,
1621                  * CRT for rgb, LCD for other supported signal tyes
1622                  */
1623                 if (!bp_funcs->is_device_id_supported(dc_ctx->dc_bios,
1624                                                       link->device_tag.dev_id))
1625                         continue;
1626                 if (link->device_tag.dev_id.device_type == DEVICE_TYPE_CRT &&
1627                     link->connector_signal != SIGNAL_TYPE_RGB)
1628                         continue;
1629                 if (link->device_tag.dev_id.device_type == DEVICE_TYPE_LCD &&
1630                     link->connector_signal == SIGNAL_TYPE_RGB)
1631                         continue;
1632
1633                 DC_LOG_DC("BIOS object table - device_tag.acpi_device: %d", link->device_tag.acpi_device);
1634                 DC_LOG_DC("BIOS object table - device_tag.dev_id.device_type: %d", link->device_tag.dev_id.device_type);
1635                 DC_LOG_DC("BIOS object table - device_tag.dev_id.enum_id: %d", link->device_tag.dev_id.enum_id);
1636                 break;
1637         }
1638
1639         if (bios->integrated_info)
1640                 memcpy(info, bios->integrated_info, sizeof(*info));
1641
1642         /* Look for channel mapping corresponding to connector and device tag */
1643         for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; i++) {
1644                 struct external_display_path *path =
1645                         &info->ext_disp_conn_info.path[i];
1646
1647                 if (path->device_connector_id.enum_id == link->link_id.enum_id &&
1648                     path->device_connector_id.id == link->link_id.id &&
1649                     path->device_connector_id.type == link->link_id.type) {
1650                         if (link->device_tag.acpi_device != 0 &&
1651                             path->device_acpi_enum == link->device_tag.acpi_device) {
1652                                 link->ddi_channel_mapping = path->channel_mapping;
1653                                 link->chip_caps = path->caps;
1654                                 DC_LOG_DC("BIOS object table - ddi_channel_mapping: 0x%04X", link->ddi_channel_mapping.raw);
1655                                 DC_LOG_DC("BIOS object table - chip_caps: %d", link->chip_caps);
1656                         } else if (path->device_tag ==
1657                                    link->device_tag.dev_id.raw_device_tag) {
1658                                 link->ddi_channel_mapping = path->channel_mapping;
1659                                 link->chip_caps = path->caps;
1660                                 DC_LOG_DC("BIOS object table - ddi_channel_mapping: 0x%04X", link->ddi_channel_mapping.raw);
1661                                 DC_LOG_DC("BIOS object table - chip_caps: %d", link->chip_caps);
1662                         }
1663
1664                         if (link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) {
1665                                 link->bios_forced_drive_settings.VOLTAGE_SWING =
1666                                                 (info->ext_disp_conn_info.fixdpvoltageswing & 0x3);
1667                                 link->bios_forced_drive_settings.PRE_EMPHASIS =
1668                                                 ((info->ext_disp_conn_info.fixdpvoltageswing >> 2) & 0x3);
1669                         }
1670
1671                         break;
1672                 }
1673         }
1674
1675         if (bios->funcs->get_atom_dc_golden_table)
1676                 bios->funcs->get_atom_dc_golden_table(bios);
1677
1678         /*
1679          * TODO check if GPIO programmed correctly
1680          *
1681          * If GPIO isn't programmed correctly HPD might not rise or drain
1682          * fast enough, leading to bounces.
1683          */
1684         program_hpd_filter(link);
1685
1686         link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
1687
1688         DC_LOG_DC("BIOS object table - %s finished successfully.\n", __func__);
1689         kfree(info);
1690         return true;
1691 device_tag_fail:
1692         link->link_enc->funcs->destroy(&link->link_enc);
1693 link_enc_create_fail:
1694         if (link->panel_cntl != NULL)
1695                 link->panel_cntl->funcs->destroy(&link->panel_cntl);
1696 panel_cntl_create_fail:
1697         dal_ddc_service_destroy(&link->ddc);
1698 ddc_create_fail:
1699 create_fail:
1700
1701         if (link->hpd_gpio) {
1702                 dal_gpio_destroy_irq(&link->hpd_gpio);
1703                 link->hpd_gpio = NULL;
1704         }
1705
1706         DC_LOG_DC("BIOS object table - %s failed.\n", __func__);
1707         kfree(info);
1708
1709         return false;
1710 }
1711
1712 static bool dc_link_construct_dpia(struct dc_link *link,
1713                                    const struct link_init_data *init_params)
1714 {
1715         struct ddc_service_init_data ddc_service_init_data = { { 0 } };
1716         struct dc_context *dc_ctx = init_params->ctx;
1717
1718         DC_LOGGER_INIT(dc_ctx->logger);
1719
1720         /* Initialized irq source for hpd and hpd rx */
1721         link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1722         link->irq_source_hpd_rx = DC_IRQ_SOURCE_INVALID;
1723         link->link_status.dpcd_caps = &link->dpcd_caps;
1724
1725         link->dc = init_params->dc;
1726         link->ctx = dc_ctx;
1727         link->link_index = init_params->link_index;
1728
1729         memset(&link->preferred_training_settings, 0,
1730                sizeof(struct dc_link_training_overrides));
1731         memset(&link->preferred_link_setting, 0,
1732                sizeof(struct dc_link_settings));
1733
1734         /* Dummy Init for linkid */
1735         link->link_id.type = OBJECT_TYPE_CONNECTOR;
1736         link->link_id.id = CONNECTOR_ID_DISPLAY_PORT;
1737         link->link_id.enum_id = ENUM_ID_1 + init_params->connector_index;
1738         link->is_internal_display = false;
1739         link->connector_signal = SIGNAL_TYPE_DISPLAY_PORT;
1740         LINK_INFO("Connector[%d] description:signal %d\n",
1741                   init_params->connector_index,
1742                   link->connector_signal);
1743
1744         link->ep_type = DISPLAY_ENDPOINT_USB4_DPIA;
1745         link->is_dig_mapping_flexible = true;
1746
1747         /* TODO: Initialize link : funcs->link_init */
1748
1749         ddc_service_init_data.ctx = link->ctx;
1750         ddc_service_init_data.id = link->link_id;
1751         ddc_service_init_data.link = link;
1752         /* Set indicator for dpia link so that ddc won't be created */
1753         ddc_service_init_data.is_dpia_link = true;
1754
1755         link->ddc = dal_ddc_service_create(&ddc_service_init_data);
1756         if (!link->ddc) {
1757                 DC_ERROR("Failed to create ddc_service!\n");
1758                 goto ddc_create_fail;
1759         }
1760
1761         /* Set dpia port index : 0 to number of dpia ports */
1762         link->ddc_hw_inst = init_params->connector_index;
1763
1764         /* TODO: Create link encoder */
1765
1766         link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
1767
1768         /* Some docks seem to NAK I2C writes to segment pointer with mot=0. */
1769         link->wa_flags.dp_mot_reset_segment = true;
1770
1771         return true;
1772
1773 ddc_create_fail:
1774         return false;
1775 }
1776
1777 static bool dc_link_construct(struct dc_link *link,
1778                               const struct link_init_data *init_params)
1779 {
1780         /* Handle dpia case */
1781         if (init_params->is_dpia_link)
1782                 return dc_link_construct_dpia(link, init_params);
1783         else
1784                 return dc_link_construct_legacy(link, init_params);
1785 }
1786 /*******************************************************************************
1787  * Public functions
1788  ******************************************************************************/
1789 struct dc_link *link_create(const struct link_init_data *init_params)
1790 {
1791         struct dc_link *link =
1792                         kzalloc(sizeof(*link), GFP_KERNEL);
1793
1794         if (NULL == link)
1795                 goto alloc_fail;
1796
1797         if (false == dc_link_construct(link, init_params))
1798                 goto construct_fail;
1799
1800         /*
1801          * Must use preferred_link_setting, not reported_link_cap or verified_link_cap,
1802          * since struct preferred_link_setting won't be reset after S3.
1803          */
1804         link->preferred_link_setting.dpcd_source_device_specific_field_support = true;
1805
1806         return link;
1807
1808 construct_fail:
1809         kfree(link);
1810
1811 alloc_fail:
1812         return NULL;
1813 }
1814
1815 void link_destroy(struct dc_link **link)
1816 {
1817         dc_link_destruct(*link);
1818         kfree(*link);
1819         *link = NULL;
1820 }
1821
1822 static void enable_stream_features(struct pipe_ctx *pipe_ctx)
1823 {
1824         struct dc_stream_state *stream = pipe_ctx->stream;
1825
1826         if (pipe_ctx->stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST) {
1827                 struct dc_link *link = stream->link;
1828                 union down_spread_ctrl old_downspread;
1829                 union down_spread_ctrl new_downspread;
1830
1831                 core_link_read_dpcd(link, DP_DOWNSPREAD_CTRL,
1832                                 &old_downspread.raw, sizeof(old_downspread));
1833
1834                 new_downspread.raw = old_downspread.raw;
1835
1836                 new_downspread.bits.IGNORE_MSA_TIMING_PARAM =
1837                                 (stream->ignore_msa_timing_param) ? 1 : 0;
1838
1839                 if (new_downspread.raw != old_downspread.raw) {
1840                         core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
1841                                 &new_downspread.raw, sizeof(new_downspread));
1842                 }
1843
1844         } else {
1845                 dm_helpers_mst_enable_stream_features(stream);
1846         }
1847 }
1848
1849 static enum dc_status enable_link_dp(struct dc_state *state,
1850                                      struct pipe_ctx *pipe_ctx)
1851 {
1852         struct dc_stream_state *stream = pipe_ctx->stream;
1853         enum dc_status status;
1854         bool skip_video_pattern;
1855         struct dc_link *link = stream->link;
1856         struct dc_link_settings link_settings = {0};
1857         bool fec_enable;
1858         int i;
1859         bool apply_seamless_boot_optimization = false;
1860         uint32_t bl_oled_enable_delay = 50; // in ms
1861         const uint32_t post_oui_delay = 30; // 30ms
1862         /* Reduce link bandwidth between failed link training attempts. */
1863         bool do_fallback = false;
1864
1865         // check for seamless boot
1866         for (i = 0; i < state->stream_count; i++) {
1867                 if (state->streams[i]->apply_seamless_boot_optimization) {
1868                         apply_seamless_boot_optimization = true;
1869                         break;
1870                 }
1871         }
1872
1873         /* get link settings for video mode timing */
1874         decide_link_settings(stream, &link_settings);
1875
1876         /* Train with fallback when enabling DPIA link. Conventional links are
1877          * trained with fallback during sink detection.
1878          */
1879         if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
1880                 do_fallback = true;
1881
1882 #if defined(CONFIG_DRM_AMD_DC_DCN)
1883         /*
1884          * Temporary w/a to get DP2.0 link rates to work with SST.
1885          * TODO DP2.0 - Workaround: Remove w/a if and when the issue is resolved.
1886          */
1887         if (dp_get_link_encoding_format(&link_settings) == DP_128b_132b_ENCODING &&
1888                         pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT &&
1889                         link->dc->debug.set_mst_en_for_sst) {
1890                 dp_enable_mst_on_sink(link, true);
1891         }
1892 #endif
1893
1894         if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) {
1895                 /*in case it is not on*/
1896                 link->dc->hwss.edp_power_control(link, true);
1897                 link->dc->hwss.edp_wait_for_hpd_ready(link, true);
1898         }
1899
1900 #if defined(CONFIG_DRM_AMD_DC_DCN)
1901         if (dp_get_link_encoding_format(&link_settings) == DP_128b_132b_ENCODING) {
1902                 /* TODO - DP2.0 HW: calculate 32 symbol clock for HPO encoder */
1903         } else {
1904                 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk =
1905                                 link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
1906                 if (state->clk_mgr && !apply_seamless_boot_optimization)
1907                         state->clk_mgr->funcs->update_clocks(state->clk_mgr,
1908                                         state, false);
1909         }
1910 #else
1911         pipe_ctx->stream_res.pix_clk_params.requested_sym_clk =
1912                 link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
1913         if (state->clk_mgr && !apply_seamless_boot_optimization)
1914                 state->clk_mgr->funcs->update_clocks(state->clk_mgr,
1915                                                                                         state, false);
1916 #endif
1917
1918         // during mode switch we do DP_SET_POWER off then on, and OUI is lost
1919         dpcd_set_source_specific_data(link);
1920         if (link->dpcd_sink_ext_caps.raw != 0)
1921                 msleep(post_oui_delay);
1922
1923         skip_video_pattern = true;
1924
1925         if (link_settings.link_rate == LINK_RATE_LOW)
1926                 skip_video_pattern = false;
1927
1928         if (perform_link_training_with_retries(&link_settings,
1929                                                skip_video_pattern,
1930                                                LINK_TRAINING_ATTEMPTS,
1931                                                pipe_ctx,
1932                                                pipe_ctx->stream->signal,
1933                                                do_fallback)) {
1934                 link->cur_link_settings = link_settings;
1935                 status = DC_OK;
1936         } else {
1937                 status = DC_FAIL_DP_LINK_TRAINING;
1938         }
1939
1940         if (link->preferred_training_settings.fec_enable)
1941                 fec_enable = *link->preferred_training_settings.fec_enable;
1942         else
1943                 fec_enable = true;
1944
1945 #if defined(CONFIG_DRM_AMD_DC_DCN)
1946         if (dp_get_link_encoding_format(&link_settings) == DP_8b_10b_ENCODING)
1947                 dp_set_fec_enable(link, fec_enable);
1948 #else
1949         dp_set_fec_enable(link, fec_enable);
1950 #endif
1951
1952         // during mode set we do DP_SET_POWER off then on, aux writes are lost
1953         if (link->dpcd_sink_ext_caps.bits.oled == 1 ||
1954                 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1 ||
1955                 link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1) {
1956                 dc_link_set_default_brightness_aux(link); // TODO: use cached if known
1957                 if (link->dpcd_sink_ext_caps.bits.oled == 1)
1958                         msleep(bl_oled_enable_delay);
1959                 dc_link_backlight_enable_aux(link, true);
1960         }
1961
1962         return status;
1963 }
1964
1965 static enum dc_status enable_link_edp(
1966                 struct dc_state *state,
1967                 struct pipe_ctx *pipe_ctx)
1968 {
1969         enum dc_status status;
1970
1971         status = enable_link_dp(state, pipe_ctx);
1972
1973         return status;
1974 }
1975
1976 static enum dc_status enable_link_dp_mst(
1977                 struct dc_state *state,
1978                 struct pipe_ctx *pipe_ctx)
1979 {
1980         struct dc_link *link = pipe_ctx->stream->link;
1981
1982         /* sink signal type after MST branch is MST. Multiple MST sinks
1983          * share one link. Link DP PHY is enable or training only once.
1984          */
1985         if (link->link_status.link_active)
1986                 return DC_OK;
1987
1988         /* clear payload table */
1989         dm_helpers_dp_mst_clear_payload_allocation_table(link->ctx, link);
1990
1991         /* to make sure the pending down rep can be processed
1992          * before enabling the link
1993          */
1994         dm_helpers_dp_mst_poll_pending_down_reply(link->ctx, link);
1995
1996         /* set the sink to MST mode before enabling the link */
1997         dp_enable_mst_on_sink(link, true);
1998
1999         return enable_link_dp(state, pipe_ctx);
2000 }
2001
2002 static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx,
2003                 enum engine_id eng_id,
2004                 struct ext_hdmi_settings *settings)
2005 {
2006         bool result = false;
2007         int i = 0;
2008         struct integrated_info *integrated_info =
2009                         pipe_ctx->stream->ctx->dc_bios->integrated_info;
2010
2011         if (integrated_info == NULL)
2012                 return false;
2013
2014         /*
2015          * Get retimer settings from sbios for passing SI eye test for DCE11
2016          * The setting values are varied based on board revision and port id
2017          * Therefore the setting values of each ports is passed by sbios.
2018          */
2019
2020         // Check if current bios contains ext Hdmi settings
2021         if (integrated_info->gpu_cap_info & 0x20) {
2022                 switch (eng_id) {
2023                 case ENGINE_ID_DIGA:
2024                         settings->slv_addr = integrated_info->dp0_ext_hdmi_slv_addr;
2025                         settings->reg_num = integrated_info->dp0_ext_hdmi_6g_reg_num;
2026                         settings->reg_num_6g = integrated_info->dp0_ext_hdmi_6g_reg_num;
2027                         memmove(settings->reg_settings,
2028                                         integrated_info->dp0_ext_hdmi_reg_settings,
2029                                         sizeof(integrated_info->dp0_ext_hdmi_reg_settings));
2030                         memmove(settings->reg_settings_6g,
2031                                         integrated_info->dp0_ext_hdmi_6g_reg_settings,
2032                                         sizeof(integrated_info->dp0_ext_hdmi_6g_reg_settings));
2033                         result = true;
2034                         break;
2035                 case ENGINE_ID_DIGB:
2036                         settings->slv_addr = integrated_info->dp1_ext_hdmi_slv_addr;
2037                         settings->reg_num = integrated_info->dp1_ext_hdmi_6g_reg_num;
2038                         settings->reg_num_6g = integrated_info->dp1_ext_hdmi_6g_reg_num;
2039                         memmove(settings->reg_settings,
2040                                         integrated_info->dp1_ext_hdmi_reg_settings,
2041                                         sizeof(integrated_info->dp1_ext_hdmi_reg_settings));
2042                         memmove(settings->reg_settings_6g,
2043                                         integrated_info->dp1_ext_hdmi_6g_reg_settings,
2044                                         sizeof(integrated_info->dp1_ext_hdmi_6g_reg_settings));
2045                         result = true;
2046                         break;
2047                 case ENGINE_ID_DIGC:
2048                         settings->slv_addr = integrated_info->dp2_ext_hdmi_slv_addr;
2049                         settings->reg_num = integrated_info->dp2_ext_hdmi_6g_reg_num;
2050                         settings->reg_num_6g = integrated_info->dp2_ext_hdmi_6g_reg_num;
2051                         memmove(settings->reg_settings,
2052                                         integrated_info->dp2_ext_hdmi_reg_settings,
2053                                         sizeof(integrated_info->dp2_ext_hdmi_reg_settings));
2054                         memmove(settings->reg_settings_6g,
2055                                         integrated_info->dp2_ext_hdmi_6g_reg_settings,
2056                                         sizeof(integrated_info->dp2_ext_hdmi_6g_reg_settings));
2057                         result = true;
2058                         break;
2059                 case ENGINE_ID_DIGD:
2060                         settings->slv_addr = integrated_info->dp3_ext_hdmi_slv_addr;
2061                         settings->reg_num = integrated_info->dp3_ext_hdmi_6g_reg_num;
2062                         settings->reg_num_6g = integrated_info->dp3_ext_hdmi_6g_reg_num;
2063                         memmove(settings->reg_settings,
2064                                         integrated_info->dp3_ext_hdmi_reg_settings,
2065                                         sizeof(integrated_info->dp3_ext_hdmi_reg_settings));
2066                         memmove(settings->reg_settings_6g,
2067                                         integrated_info->dp3_ext_hdmi_6g_reg_settings,
2068                                         sizeof(integrated_info->dp3_ext_hdmi_6g_reg_settings));
2069                         result = true;
2070                         break;
2071                 default:
2072                         break;
2073                 }
2074
2075                 if (result == true) {
2076                         // Validate settings from bios integrated info table
2077                         if (settings->slv_addr == 0)
2078                                 return false;
2079                         if (settings->reg_num > 9)
2080                                 return false;
2081                         if (settings->reg_num_6g > 3)
2082                                 return false;
2083
2084                         for (i = 0; i < settings->reg_num; i++) {
2085                                 if (settings->reg_settings[i].i2c_reg_index > 0x20)
2086                                         return false;
2087                         }
2088
2089                         for (i = 0; i < settings->reg_num_6g; i++) {
2090                                 if (settings->reg_settings_6g[i].i2c_reg_index > 0x20)
2091                                         return false;
2092                         }
2093                 }
2094         }
2095
2096         return result;
2097 }
2098
2099 static bool i2c_write(struct pipe_ctx *pipe_ctx,
2100                 uint8_t address, uint8_t *buffer, uint32_t length)
2101 {
2102         struct i2c_command cmd = {0};
2103         struct i2c_payload payload = {0};
2104
2105         memset(&payload, 0, sizeof(payload));
2106         memset(&cmd, 0, sizeof(cmd));
2107
2108         cmd.number_of_payloads = 1;
2109         cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
2110         cmd.speed = pipe_ctx->stream->ctx->dc->caps.i2c_speed_in_khz;
2111
2112         payload.address = address;
2113         payload.data = buffer;
2114         payload.length = length;
2115         payload.write = true;
2116         cmd.payloads = &payload;
2117
2118         if (dm_helpers_submit_i2c(pipe_ctx->stream->ctx,
2119                         pipe_ctx->stream->link, &cmd))
2120                 return true;
2121
2122         return false;
2123 }
2124
2125 static void write_i2c_retimer_setting(
2126                 struct pipe_ctx *pipe_ctx,
2127                 bool is_vga_mode,
2128                 bool is_over_340mhz,
2129                 struct ext_hdmi_settings *settings)
2130 {
2131         uint8_t slave_address = (settings->slv_addr >> 1);
2132         uint8_t buffer[2];
2133         const uint8_t apply_rx_tx_change = 0x4;
2134         uint8_t offset = 0xA;
2135         uint8_t value = 0;
2136         int i = 0;
2137         bool i2c_success = false;
2138         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
2139
2140         memset(&buffer, 0, sizeof(buffer));
2141
2142         /* Start Ext-Hdmi programming*/
2143
2144         for (i = 0; i < settings->reg_num; i++) {
2145                 /* Apply 3G settings */
2146                 if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
2147
2148                         buffer[0] = settings->reg_settings[i].i2c_reg_index;
2149                         buffer[1] = settings->reg_settings[i].i2c_reg_val;
2150                         i2c_success = i2c_write(pipe_ctx, slave_address,
2151                                                 buffer, sizeof(buffer));
2152                         RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2153                                 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
2154                                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2155
2156                         if (!i2c_success)
2157                                 goto i2c_write_fail;
2158
2159                         /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
2160                          * needs to be set to 1 on every 0xA-0xC write.
2161                          */
2162                         if (settings->reg_settings[i].i2c_reg_index == 0xA ||
2163                                 settings->reg_settings[i].i2c_reg_index == 0xB ||
2164                                 settings->reg_settings[i].i2c_reg_index == 0xC) {
2165
2166                                 /* Query current value from offset 0xA */
2167                                 if (settings->reg_settings[i].i2c_reg_index == 0xA)
2168                                         value = settings->reg_settings[i].i2c_reg_val;
2169                                 else {
2170                                         i2c_success =
2171                                                 dal_ddc_service_query_ddc_data(
2172                                                 pipe_ctx->stream->link->ddc,
2173                                                 slave_address, &offset, 1, &value, 1);
2174                                         if (!i2c_success)
2175                                                 goto i2c_write_fail;
2176                                 }
2177
2178                                 buffer[0] = offset;
2179                                 /* Set APPLY_RX_TX_CHANGE bit to 1 */
2180                                 buffer[1] = value | apply_rx_tx_change;
2181                                 i2c_success = i2c_write(pipe_ctx, slave_address,
2182                                                 buffer, sizeof(buffer));
2183                                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2184                                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2185                                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2186                                 if (!i2c_success)
2187                                         goto i2c_write_fail;
2188                         }
2189                 }
2190         }
2191
2192         /* Apply 3G settings */
2193         if (is_over_340mhz) {
2194                 for (i = 0; i < settings->reg_num_6g; i++) {
2195                         /* Apply 3G settings */
2196                         if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
2197
2198                                 buffer[0] = settings->reg_settings_6g[i].i2c_reg_index;
2199                                 buffer[1] = settings->reg_settings_6g[i].i2c_reg_val;
2200                                 i2c_success = i2c_write(pipe_ctx, slave_address,
2201                                                         buffer, sizeof(buffer));
2202                                 RETIMER_REDRIVER_INFO("above 340Mhz: retimer write to slave_address = 0x%x,\
2203                                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2204                                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2205
2206                                 if (!i2c_success)
2207                                         goto i2c_write_fail;
2208
2209                                 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
2210                                  * needs to be set to 1 on every 0xA-0xC write.
2211                                  */
2212                                 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA ||
2213                                         settings->reg_settings_6g[i].i2c_reg_index == 0xB ||
2214                                         settings->reg_settings_6g[i].i2c_reg_index == 0xC) {
2215
2216                                         /* Query current value from offset 0xA */
2217                                         if (settings->reg_settings_6g[i].i2c_reg_index == 0xA)
2218                                                 value = settings->reg_settings_6g[i].i2c_reg_val;
2219                                         else {
2220                                                 i2c_success =
2221                                                                 dal_ddc_service_query_ddc_data(
2222                                                                 pipe_ctx->stream->link->ddc,
2223                                                                 slave_address, &offset, 1, &value, 1);
2224                                                 if (!i2c_success)
2225                                                         goto i2c_write_fail;
2226                                         }
2227
2228                                         buffer[0] = offset;
2229                                         /* Set APPLY_RX_TX_CHANGE bit to 1 */
2230                                         buffer[1] = value | apply_rx_tx_change;
2231                                         i2c_success = i2c_write(pipe_ctx, slave_address,
2232                                                         buffer, sizeof(buffer));
2233                                         RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2234                                                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2235                                                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2236                                         if (!i2c_success)
2237                                                 goto i2c_write_fail;
2238                                 }
2239                         }
2240                 }
2241         }
2242
2243         if (is_vga_mode) {
2244                 /* Program additional settings if using 640x480 resolution */
2245
2246                 /* Write offset 0xFF to 0x01 */
2247                 buffer[0] = 0xff;
2248                 buffer[1] = 0x01;
2249                 i2c_success = i2c_write(pipe_ctx, slave_address,
2250                                 buffer, sizeof(buffer));
2251                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2252                                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2253                                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2254                 if (!i2c_success)
2255                         goto i2c_write_fail;
2256
2257                 /* Write offset 0x00 to 0x23 */
2258                 buffer[0] = 0x00;
2259                 buffer[1] = 0x23;
2260                 i2c_success = i2c_write(pipe_ctx, slave_address,
2261                                 buffer, sizeof(buffer));
2262                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2263                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2264                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2265                 if (!i2c_success)
2266                         goto i2c_write_fail;
2267
2268                 /* Write offset 0xff to 0x00 */
2269                 buffer[0] = 0xff;
2270                 buffer[1] = 0x00;
2271                 i2c_success = i2c_write(pipe_ctx, slave_address,
2272                                 buffer, sizeof(buffer));
2273                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2274                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2275                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2276                 if (!i2c_success)
2277                         goto i2c_write_fail;
2278
2279         }
2280
2281         return;
2282
2283 i2c_write_fail:
2284         DC_LOG_DEBUG("Set retimer failed");
2285 }
2286
2287 static void write_i2c_default_retimer_setting(
2288                 struct pipe_ctx *pipe_ctx,
2289                 bool is_vga_mode,
2290                 bool is_over_340mhz)
2291 {
2292         uint8_t slave_address = (0xBA >> 1);
2293         uint8_t buffer[2];
2294         bool i2c_success = false;
2295         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
2296
2297         memset(&buffer, 0, sizeof(buffer));
2298
2299         /* Program Slave Address for tuning single integrity */
2300         /* Write offset 0x0A to 0x13 */
2301         buffer[0] = 0x0A;
2302         buffer[1] = 0x13;
2303         i2c_success = i2c_write(pipe_ctx, slave_address,
2304                         buffer, sizeof(buffer));
2305         RETIMER_REDRIVER_INFO("retimer writes default setting to slave_address = 0x%x,\
2306                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2307                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2308         if (!i2c_success)
2309                 goto i2c_write_fail;
2310
2311         /* Write offset 0x0A to 0x17 */
2312         buffer[0] = 0x0A;
2313         buffer[1] = 0x17;
2314         i2c_success = i2c_write(pipe_ctx, slave_address,
2315                         buffer, sizeof(buffer));
2316         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2317                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2318                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2319         if (!i2c_success)
2320                 goto i2c_write_fail;
2321
2322         /* Write offset 0x0B to 0xDA or 0xD8 */
2323         buffer[0] = 0x0B;
2324         buffer[1] = is_over_340mhz ? 0xDA : 0xD8;
2325         i2c_success = i2c_write(pipe_ctx, slave_address,
2326                         buffer, sizeof(buffer));
2327         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2328                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2329                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2330         if (!i2c_success)
2331                 goto i2c_write_fail;
2332
2333         /* Write offset 0x0A to 0x17 */
2334         buffer[0] = 0x0A;
2335         buffer[1] = 0x17;
2336         i2c_success = i2c_write(pipe_ctx, slave_address,
2337                         buffer, sizeof(buffer));
2338         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2339                 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
2340                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2341         if (!i2c_success)
2342                 goto i2c_write_fail;
2343
2344         /* Write offset 0x0C to 0x1D or 0x91 */
2345         buffer[0] = 0x0C;
2346         buffer[1] = is_over_340mhz ? 0x1D : 0x91;
2347         i2c_success = i2c_write(pipe_ctx, slave_address,
2348                         buffer, sizeof(buffer));
2349         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2350                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2351                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2352         if (!i2c_success)
2353                 goto i2c_write_fail;
2354
2355         /* Write offset 0x0A to 0x17 */
2356         buffer[0] = 0x0A;
2357         buffer[1] = 0x17;
2358         i2c_success = i2c_write(pipe_ctx, slave_address,
2359                         buffer, sizeof(buffer));
2360         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2361                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2362                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2363         if (!i2c_success)
2364                 goto i2c_write_fail;
2365
2366
2367         if (is_vga_mode) {
2368                 /* Program additional settings if using 640x480 resolution */
2369
2370                 /* Write offset 0xFF to 0x01 */
2371                 buffer[0] = 0xff;
2372                 buffer[1] = 0x01;
2373                 i2c_success = i2c_write(pipe_ctx, slave_address,
2374                                 buffer, sizeof(buffer));
2375                 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2376                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2377                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2378                 if (!i2c_success)
2379                         goto i2c_write_fail;
2380
2381                 /* Write offset 0x00 to 0x23 */
2382                 buffer[0] = 0x00;
2383                 buffer[1] = 0x23;
2384                 i2c_success = i2c_write(pipe_ctx, slave_address,
2385                                 buffer, sizeof(buffer));
2386                 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2387                         offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
2388                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2389                 if (!i2c_success)
2390                         goto i2c_write_fail;
2391
2392                 /* Write offset 0xff to 0x00 */
2393                 buffer[0] = 0xff;
2394                 buffer[1] = 0x00;
2395                 i2c_success = i2c_write(pipe_ctx, slave_address,
2396                                 buffer, sizeof(buffer));
2397                 RETIMER_REDRIVER_INFO("retimer write default setting to slave_addr = 0x%x,\
2398                         offset = 0x%x, reg_val= 0x%x, i2c_success = %d end here\n",
2399                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2400                 if (!i2c_success)
2401                         goto i2c_write_fail;
2402         }
2403
2404         return;
2405
2406 i2c_write_fail:
2407         DC_LOG_DEBUG("Set default retimer failed");
2408 }
2409
2410 static void write_i2c_redriver_setting(
2411                 struct pipe_ctx *pipe_ctx,
2412                 bool is_over_340mhz)
2413 {
2414         uint8_t slave_address = (0xF0 >> 1);
2415         uint8_t buffer[16];
2416         bool i2c_success = false;
2417         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
2418
2419         memset(&buffer, 0, sizeof(buffer));
2420
2421         // Program Slave Address for tuning single integrity
2422         buffer[3] = 0x4E;
2423         buffer[4] = 0x4E;
2424         buffer[5] = 0x4E;
2425         buffer[6] = is_over_340mhz ? 0x4E : 0x4A;
2426
2427         i2c_success = i2c_write(pipe_ctx, slave_address,
2428                                         buffer, sizeof(buffer));
2429         RETIMER_REDRIVER_INFO("redriver write 0 to all 16 reg offset expect following:\n\
2430                 \t slave_addr = 0x%x, offset[3] = 0x%x, offset[4] = 0x%x,\
2431                 offset[5] = 0x%x,offset[6] is_over_340mhz = 0x%x,\
2432                 i2c_success = %d\n",
2433                 slave_address, buffer[3], buffer[4], buffer[5], buffer[6], i2c_success?1:0);
2434
2435         if (!i2c_success)
2436                 DC_LOG_DEBUG("Set redriver failed");
2437 }
2438
2439 static void disable_link(struct dc_link *link, enum signal_type signal)
2440 {
2441         /*
2442          * TODO: implement call for dp_set_hw_test_pattern
2443          * it is needed for compliance testing
2444          */
2445
2446         /* Here we need to specify that encoder output settings
2447          * need to be calculated as for the set mode,
2448          * it will lead to querying dynamic link capabilities
2449          * which should be done before enable output
2450          */
2451
2452         if (dc_is_dp_signal(signal)) {
2453                 /* SST DP, eDP */
2454 #if defined(CONFIG_DRM_AMD_DC_DCN)
2455                 struct dc_link_settings link_settings = link->cur_link_settings;
2456 #endif
2457                 if (dc_is_dp_sst_signal(signal))
2458                         dp_disable_link_phy(link, signal);
2459                 else
2460                         dp_disable_link_phy_mst(link, signal);
2461
2462                 if (dc_is_dp_sst_signal(signal) ||
2463                                 link->mst_stream_alloc_table.stream_count == 0) {
2464 #if defined(CONFIG_DRM_AMD_DC_DCN)
2465                         if (dp_get_link_encoding_format(&link_settings) == DP_8b_10b_ENCODING) {
2466                                 dp_set_fec_enable(link, false);
2467                                 dp_set_fec_ready(link, false);
2468                         }
2469 #else
2470                         dp_set_fec_enable(link, false);
2471                         dp_set_fec_ready(link, false);
2472 #endif
2473                 }
2474         } else {
2475                 if (signal != SIGNAL_TYPE_VIRTUAL)
2476                         link->link_enc->funcs->disable_output(link->link_enc, signal);
2477         }
2478
2479         if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
2480                 /* MST disable link only when no stream use the link */
2481                 if (link->mst_stream_alloc_table.stream_count <= 0)
2482                         link->link_status.link_active = false;
2483         } else {
2484                 link->link_status.link_active = false;
2485         }
2486 }
2487
2488 static void enable_link_hdmi(struct pipe_ctx *pipe_ctx)
2489 {
2490         struct dc_stream_state *stream = pipe_ctx->stream;
2491         struct dc_link *link = stream->link;
2492         enum dc_color_depth display_color_depth;
2493         enum engine_id eng_id;
2494         struct ext_hdmi_settings settings = {0};
2495         bool is_over_340mhz = false;
2496         bool is_vga_mode = (stream->timing.h_addressable == 640)
2497                         && (stream->timing.v_addressable == 480);
2498
2499         if (stream->phy_pix_clk == 0)
2500                 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10;
2501         if (stream->phy_pix_clk > 340000)
2502                 is_over_340mhz = true;
2503
2504         if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
2505                 unsigned short masked_chip_caps = pipe_ctx->stream->link->chip_caps &
2506                                 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
2507                 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {
2508                         /* DP159, Retimer settings */
2509                         eng_id = pipe_ctx->stream_res.stream_enc->id;
2510
2511                         if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) {
2512                                 write_i2c_retimer_setting(pipe_ctx,
2513                                                 is_vga_mode, is_over_340mhz, &settings);
2514                         } else {
2515                                 write_i2c_default_retimer_setting(pipe_ctx,
2516                                                 is_vga_mode, is_over_340mhz);
2517                         }
2518                 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {
2519                         /* PI3EQX1204, Redriver settings */
2520                         write_i2c_redriver_setting(pipe_ctx, is_over_340mhz);
2521                 }
2522         }
2523
2524         if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
2525                 dal_ddc_service_write_scdc_data(
2526                         stream->link->ddc,
2527                         stream->phy_pix_clk,
2528                         stream->timing.flags.LTE_340MCSC_SCRAMBLE);
2529
2530         memset(&stream->link->cur_link_settings, 0,
2531                         sizeof(struct dc_link_settings));
2532
2533         display_color_depth = stream->timing.display_color_depth;
2534         if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
2535                 display_color_depth = COLOR_DEPTH_888;
2536
2537         link->link_enc->funcs->enable_tmds_output(
2538                         link->link_enc,
2539                         pipe_ctx->clock_source->id,
2540                         display_color_depth,
2541                         pipe_ctx->stream->signal,
2542                         stream->phy_pix_clk);
2543
2544         if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
2545                 dal_ddc_service_read_scdc_data(link->ddc);
2546 }
2547
2548 static void enable_link_lvds(struct pipe_ctx *pipe_ctx)
2549 {
2550         struct dc_stream_state *stream = pipe_ctx->stream;
2551         struct dc_link *link = stream->link;
2552
2553         if (stream->phy_pix_clk == 0)
2554                 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10;
2555
2556         memset(&stream->link->cur_link_settings, 0,
2557                         sizeof(struct dc_link_settings));
2558
2559         link->link_enc->funcs->enable_lvds_output(
2560                         link->link_enc,
2561                         pipe_ctx->clock_source->id,
2562                         stream->phy_pix_clk);
2563
2564 }
2565
2566 /****************************enable_link***********************************/
2567 static enum dc_status enable_link(
2568                 struct dc_state *state,
2569                 struct pipe_ctx *pipe_ctx)
2570 {
2571         enum dc_status status = DC_ERROR_UNEXPECTED;
2572         struct dc_stream_state *stream = pipe_ctx->stream;
2573         struct dc_link *link = stream->link;
2574
2575         /* There's some scenarios where driver is unloaded with display
2576          * still enabled. When driver is reloaded, it may cause a display
2577          * to not light up if there is a mismatch between old and new
2578          * link settings. Need to call disable first before enabling at
2579          * new link settings.
2580          */
2581         if (link->link_status.link_active) {
2582                 disable_link(link, pipe_ctx->stream->signal);
2583         }
2584
2585         switch (pipe_ctx->stream->signal) {
2586         case SIGNAL_TYPE_DISPLAY_PORT:
2587                 status = enable_link_dp(state, pipe_ctx);
2588                 break;
2589         case SIGNAL_TYPE_EDP:
2590                 status = enable_link_edp(state, pipe_ctx);
2591                 break;
2592         case SIGNAL_TYPE_DISPLAY_PORT_MST:
2593                 status = enable_link_dp_mst(state, pipe_ctx);
2594                 msleep(200);
2595                 break;
2596         case SIGNAL_TYPE_DVI_SINGLE_LINK:
2597         case SIGNAL_TYPE_DVI_DUAL_LINK:
2598         case SIGNAL_TYPE_HDMI_TYPE_A:
2599                 enable_link_hdmi(pipe_ctx);
2600                 status = DC_OK;
2601                 break;
2602         case SIGNAL_TYPE_LVDS:
2603                 enable_link_lvds(pipe_ctx);
2604                 status = DC_OK;
2605                 break;
2606         case SIGNAL_TYPE_VIRTUAL:
2607                 status = DC_OK;
2608                 break;
2609         default:
2610                 break;
2611         }
2612
2613         if (status == DC_OK)
2614                 pipe_ctx->stream->link->link_status.link_active = true;
2615
2616         return status;
2617 }
2618
2619 static uint32_t get_timing_pixel_clock_100hz(const struct dc_crtc_timing *timing)
2620 {
2621
2622         uint32_t pxl_clk = timing->pix_clk_100hz;
2623
2624         if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
2625                 pxl_clk /= 2;
2626         else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
2627                 pxl_clk = pxl_clk * 2 / 3;
2628
2629         if (timing->display_color_depth == COLOR_DEPTH_101010)
2630                 pxl_clk = pxl_clk * 10 / 8;
2631         else if (timing->display_color_depth == COLOR_DEPTH_121212)
2632                 pxl_clk = pxl_clk * 12 / 8;
2633
2634         return pxl_clk;
2635 }
2636
2637 static bool dp_active_dongle_validate_timing(
2638                 const struct dc_crtc_timing *timing,
2639                 const struct dpcd_caps *dpcd_caps)
2640 {
2641         const struct dc_dongle_caps *dongle_caps = &dpcd_caps->dongle_caps;
2642
2643         switch (dpcd_caps->dongle_type) {
2644         case DISPLAY_DONGLE_DP_VGA_CONVERTER:
2645         case DISPLAY_DONGLE_DP_DVI_CONVERTER:
2646         case DISPLAY_DONGLE_DP_DVI_DONGLE:
2647                 if (timing->pixel_encoding == PIXEL_ENCODING_RGB)
2648                         return true;
2649                 else
2650                         return false;
2651         default:
2652                 break;
2653         }
2654
2655 #if defined(CONFIG_DRM_AMD_DC_DCN)
2656         if (dpcd_caps->dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER &&
2657                         dongle_caps->extendedCapValid == true) {
2658 #else
2659         if (dpcd_caps->dongle_type != DISPLAY_DONGLE_DP_HDMI_CONVERTER ||
2660                 dongle_caps->extendedCapValid == false)
2661                 return true;
2662 #endif
2663
2664         /* Check Pixel Encoding */
2665         switch (timing->pixel_encoding) {
2666         case PIXEL_ENCODING_RGB:
2667         case PIXEL_ENCODING_YCBCR444:
2668                 break;
2669         case PIXEL_ENCODING_YCBCR422:
2670                 if (!dongle_caps->is_dp_hdmi_ycbcr422_pass_through)
2671                         return false;
2672                 break;
2673         case PIXEL_ENCODING_YCBCR420:
2674                 if (!dongle_caps->is_dp_hdmi_ycbcr420_pass_through)
2675                         return false;
2676                 break;
2677         default:
2678                 /* Invalid Pixel Encoding*/
2679                 return false;
2680         }
2681
2682         switch (timing->display_color_depth) {
2683         case COLOR_DEPTH_666:
2684         case COLOR_DEPTH_888:
2685                 /*888 and 666 should always be supported*/
2686                 break;
2687         case COLOR_DEPTH_101010:
2688                 if (dongle_caps->dp_hdmi_max_bpc < 10)
2689                         return false;
2690                 break;
2691         case COLOR_DEPTH_121212:
2692                 if (dongle_caps->dp_hdmi_max_bpc < 12)
2693                         return false;
2694                 break;
2695         case COLOR_DEPTH_141414:
2696         case COLOR_DEPTH_161616:
2697         default:
2698                 /* These color depths are currently not supported */
2699                 return false;
2700         }
2701
2702         if (get_timing_pixel_clock_100hz(timing) > (dongle_caps->dp_hdmi_max_pixel_clk_in_khz * 10))
2703                 return false;
2704
2705 #if defined(CONFIG_DRM_AMD_DC_DCN)
2706         }
2707
2708         if (dpcd_caps->channel_coding_cap.bits.DP_128b_132b_SUPPORTED == 0 &&
2709                         dpcd_caps->dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_PASSTHROUGH_SUPPORT == 0 &&
2710                         dongle_caps->dfp_cap_ext.supported) {
2711
2712                 if (dongle_caps->dfp_cap_ext.max_pixel_rate_in_mps < (timing->pix_clk_100hz / 10000))
2713                         return false;
2714
2715                 if (dongle_caps->dfp_cap_ext.max_video_h_active_width < timing->h_addressable)
2716                         return false;
2717
2718                 if (dongle_caps->dfp_cap_ext.max_video_v_active_height < timing->v_addressable)
2719                         return false;
2720
2721                 if (timing->pixel_encoding == PIXEL_ENCODING_RGB) {
2722                         if (!dongle_caps->dfp_cap_ext.encoding_format_caps.support_rgb)
2723                                 return false;
2724                         if (timing->display_color_depth == COLOR_DEPTH_666 &&
2725                                         !dongle_caps->dfp_cap_ext.rgb_color_depth_caps.support_6bpc)
2726                                 return false;
2727                         else if (timing->display_color_depth == COLOR_DEPTH_888 &&
2728                                         !dongle_caps->dfp_cap_ext.rgb_color_depth_caps.support_8bpc)
2729                                 return false;
2730                         else if (timing->display_color_depth == COLOR_DEPTH_101010 &&
2731                                         !dongle_caps->dfp_cap_ext.rgb_color_depth_caps.support_10bpc)
2732                                 return false;
2733                         else if (timing->display_color_depth == COLOR_DEPTH_121212 &&
2734                                         !dongle_caps->dfp_cap_ext.rgb_color_depth_caps.support_12bpc)
2735                                 return false;
2736                         else if (timing->display_color_depth == COLOR_DEPTH_161616 &&
2737                                         !dongle_caps->dfp_cap_ext.rgb_color_depth_caps.support_16bpc)
2738                                 return false;
2739                 } else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR444) {
2740                         if (!dongle_caps->dfp_cap_ext.encoding_format_caps.support_rgb)
2741                                 return false;
2742                         if (timing->display_color_depth == COLOR_DEPTH_888 &&
2743                                         !dongle_caps->dfp_cap_ext.ycbcr444_color_depth_caps.support_8bpc)
2744                                 return false;
2745                         else if (timing->display_color_depth == COLOR_DEPTH_101010 &&
2746                                         !dongle_caps->dfp_cap_ext.ycbcr444_color_depth_caps.support_10bpc)
2747                                 return false;
2748                         else if (timing->display_color_depth == COLOR_DEPTH_121212 &&
2749                                         !dongle_caps->dfp_cap_ext.ycbcr444_color_depth_caps.support_12bpc)
2750                                 return false;
2751                         else if (timing->display_color_depth == COLOR_DEPTH_161616 &&
2752                                         !dongle_caps->dfp_cap_ext.ycbcr444_color_depth_caps.support_16bpc)
2753                                 return false;
2754                 } else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
2755                         if (!dongle_caps->dfp_cap_ext.encoding_format_caps.support_rgb)
2756                                 return false;
2757                         if (timing->display_color_depth == COLOR_DEPTH_888 &&
2758                                         !dongle_caps->dfp_cap_ext.ycbcr422_color_depth_caps.support_8bpc)
2759                                 return false;
2760                         else if (timing->display_color_depth == COLOR_DEPTH_101010 &&
2761                                         !dongle_caps->dfp_cap_ext.ycbcr422_color_depth_caps.support_10bpc)
2762                                 return false;
2763                         else if (timing->display_color_depth == COLOR_DEPTH_121212 &&
2764                                         !dongle_caps->dfp_cap_ext.ycbcr422_color_depth_caps.support_12bpc)
2765                                 return false;
2766                         else if (timing->display_color_depth == COLOR_DEPTH_161616 &&
2767                                         !dongle_caps->dfp_cap_ext.ycbcr422_color_depth_caps.support_16bpc)
2768                                 return false;
2769                 } else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) {
2770                         if (!dongle_caps->dfp_cap_ext.encoding_format_caps.support_rgb)
2771                                 return false;
2772                         if (timing->display_color_depth == COLOR_DEPTH_888 &&
2773                                         !dongle_caps->dfp_cap_ext.ycbcr420_color_depth_caps.support_8bpc)
2774                                 return false;
2775                         else if (timing->display_color_depth == COLOR_DEPTH_101010 &&
2776                                         !dongle_caps->dfp_cap_ext.ycbcr420_color_depth_caps.support_10bpc)
2777                                 return false;
2778                         else if (timing->display_color_depth == COLOR_DEPTH_121212 &&
2779                                         !dongle_caps->dfp_cap_ext.ycbcr420_color_depth_caps.support_12bpc)
2780                                 return false;
2781                         else if (timing->display_color_depth == COLOR_DEPTH_161616 &&
2782                                         !dongle_caps->dfp_cap_ext.ycbcr420_color_depth_caps.support_16bpc)
2783                                 return false;
2784                 }
2785         }
2786 #endif
2787
2788         return true;
2789 }
2790
2791 enum dc_status dc_link_validate_mode_timing(
2792                 const struct dc_stream_state *stream,
2793                 struct dc_link *link,
2794                 const struct dc_crtc_timing *timing)
2795 {
2796         uint32_t max_pix_clk = stream->link->dongle_max_pix_clk * 10;
2797         struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
2798
2799         /* A hack to avoid failing any modes for EDID override feature on
2800          * topology change such as lower quality cable for DP or different dongle
2801          */
2802         if (link->remote_sinks[0] && link->remote_sinks[0]->sink_signal == SIGNAL_TYPE_VIRTUAL)
2803                 return DC_OK;
2804
2805         /* Passive Dongle */
2806         if (max_pix_clk != 0 && get_timing_pixel_clock_100hz(timing) > max_pix_clk)
2807                 return DC_EXCEED_DONGLE_CAP;
2808
2809         /* Active Dongle*/
2810         if (!dp_active_dongle_validate_timing(timing, dpcd_caps))
2811                 return DC_EXCEED_DONGLE_CAP;
2812
2813         switch (stream->signal) {
2814         case SIGNAL_TYPE_EDP:
2815         case SIGNAL_TYPE_DISPLAY_PORT:
2816                 if (!dp_validate_mode_timing(
2817                                 link,
2818                                 timing))
2819                         return DC_NO_DP_LINK_BANDWIDTH;
2820                 break;
2821
2822         default:
2823                 break;
2824         }
2825
2826         return DC_OK;
2827 }
2828
2829 static struct abm *get_abm_from_stream_res(const struct dc_link *link)
2830 {
2831         int i;
2832         struct dc *dc = NULL;
2833         struct abm *abm = NULL;
2834
2835         if (!link || !link->ctx)
2836                 return NULL;
2837
2838         dc = link->ctx->dc;
2839
2840         for (i = 0; i < MAX_PIPES; i++) {
2841                 struct pipe_ctx pipe_ctx = dc->current_state->res_ctx.pipe_ctx[i];
2842                 struct dc_stream_state *stream = pipe_ctx.stream;
2843
2844                 if (stream && stream->link == link) {
2845                         abm = pipe_ctx.stream_res.abm;
2846                         break;
2847                 }
2848         }
2849         return abm;
2850 }
2851
2852 int dc_link_get_backlight_level(const struct dc_link *link)
2853 {
2854         struct abm *abm = get_abm_from_stream_res(link);
2855         struct panel_cntl *panel_cntl = link->panel_cntl;
2856         struct dc  *dc = link->ctx->dc;
2857         struct dmcu *dmcu = dc->res_pool->dmcu;
2858         bool fw_set_brightness = true;
2859
2860         if (dmcu)
2861                 fw_set_brightness = dmcu->funcs->is_dmcu_initialized(dmcu);
2862
2863         if (!fw_set_brightness && panel_cntl->funcs->get_current_backlight)
2864                 return panel_cntl->funcs->get_current_backlight(panel_cntl);
2865         else if (abm != NULL && abm->funcs->get_current_backlight != NULL)
2866                 return (int) abm->funcs->get_current_backlight(abm);
2867         else
2868                 return DC_ERROR_UNEXPECTED;
2869 }
2870
2871 int dc_link_get_target_backlight_pwm(const struct dc_link *link)
2872 {
2873         struct abm *abm = get_abm_from_stream_res(link);
2874
2875         if (abm == NULL || abm->funcs->get_target_backlight == NULL)
2876                 return DC_ERROR_UNEXPECTED;
2877
2878         return (int) abm->funcs->get_target_backlight(abm);
2879 }
2880
2881 static struct pipe_ctx *get_pipe_from_link(const struct dc_link *link)
2882 {
2883         int i;
2884         struct dc *dc = link->ctx->dc;
2885         struct pipe_ctx *pipe_ctx = NULL;
2886
2887         for (i = 0; i < MAX_PIPES; i++) {
2888                 if (dc->current_state->res_ctx.pipe_ctx[i].stream) {
2889                         if (dc->current_state->res_ctx.pipe_ctx[i].stream->link == link) {
2890                                 pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
2891                                 break;
2892                         }
2893                 }
2894         }
2895
2896         return pipe_ctx;
2897 }
2898
2899 bool dc_link_set_backlight_level(const struct dc_link *link,
2900                 uint32_t backlight_pwm_u16_16,
2901                 uint32_t frame_ramp)
2902 {
2903         struct dc  *dc = link->ctx->dc;
2904
2905         DC_LOGGER_INIT(link->ctx->logger);
2906         DC_LOG_BACKLIGHT("New Backlight level: %d (0x%X)\n",
2907                         backlight_pwm_u16_16, backlight_pwm_u16_16);
2908
2909         if (dc_is_embedded_signal(link->connector_signal)) {
2910                 struct pipe_ctx *pipe_ctx = get_pipe_from_link(link);
2911
2912                 if (pipe_ctx) {
2913                         /* Disable brightness ramping when the display is blanked
2914                          * as it can hang the DMCU
2915                          */
2916                         if (pipe_ctx->plane_state == NULL)
2917                                 frame_ramp = 0;
2918                 } else {
2919                         return false;
2920                 }
2921
2922                 dc->hwss.set_backlight_level(
2923                                 pipe_ctx,
2924                                 backlight_pwm_u16_16,
2925                                 frame_ramp);
2926         }
2927         return true;
2928 }
2929
2930 bool dc_link_set_psr_allow_active(struct dc_link *link, const bool *allow_active,
2931                 bool wait, bool force_static, const unsigned int *power_opts)
2932 {
2933         struct dc  *dc = link->ctx->dc;
2934         struct dmcu *dmcu = dc->res_pool->dmcu;
2935         struct dmub_psr *psr = dc->res_pool->psr;
2936         unsigned int panel_inst;
2937
2938         if (psr == NULL && force_static)
2939                 return false;
2940
2941         if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
2942                 return false;
2943
2944         /* Set power optimization flag */
2945         if (power_opts && link->psr_settings.psr_power_opt != *power_opts) {
2946                 link->psr_settings.psr_power_opt = *power_opts;
2947
2948                 if (psr != NULL && link->psr_settings.psr_feature_enabled && psr->funcs->psr_set_power_opt)
2949                         psr->funcs->psr_set_power_opt(psr, link->psr_settings.psr_power_opt);
2950         }
2951
2952         /* Enable or Disable PSR */
2953         if (allow_active && link->psr_settings.psr_allow_active != *allow_active) {
2954                 link->psr_settings.psr_allow_active = *allow_active;
2955
2956 #if defined(CONFIG_DRM_AMD_DC_DCN)
2957                 if (!link->psr_settings.psr_allow_active)
2958                         dc_z10_restore(dc);
2959 #endif
2960
2961                 if (psr != NULL && link->psr_settings.psr_feature_enabled) {
2962                         if (force_static && psr->funcs->psr_force_static)
2963                                 psr->funcs->psr_force_static(psr, panel_inst);
2964                         psr->funcs->psr_enable(psr, link->psr_settings.psr_allow_active, wait, panel_inst);
2965                 } else if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu)) &&
2966                         link->psr_settings.psr_feature_enabled)
2967                         dmcu->funcs->set_psr_enable(dmcu, link->psr_settings.psr_allow_active, wait);
2968                 else
2969                         return false;
2970         }
2971
2972         return true;
2973 }
2974
2975 bool dc_link_get_psr_state(const struct dc_link *link, enum dc_psr_state *state)
2976 {
2977         struct dc  *dc = link->ctx->dc;
2978         struct dmcu *dmcu = dc->res_pool->dmcu;
2979         struct dmub_psr *psr = dc->res_pool->psr;
2980         unsigned int panel_inst;
2981
2982         if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
2983                 return false;
2984
2985         if (psr != NULL && link->psr_settings.psr_feature_enabled)
2986                 psr->funcs->psr_get_state(psr, state, panel_inst);
2987         else if (dmcu != NULL && link->psr_settings.psr_feature_enabled)
2988                 dmcu->funcs->get_psr_state(dmcu, state);
2989
2990         return true;
2991 }
2992
2993 static inline enum physical_phy_id
2994 transmitter_to_phy_id(enum transmitter transmitter_value)
2995 {
2996         switch (transmitter_value) {
2997         case TRANSMITTER_UNIPHY_A:
2998                 return PHYLD_0;
2999         case TRANSMITTER_UNIPHY_B:
3000                 return PHYLD_1;
3001         case TRANSMITTER_UNIPHY_C:
3002                 return PHYLD_2;
3003         case TRANSMITTER_UNIPHY_D:
3004                 return PHYLD_3;
3005         case TRANSMITTER_UNIPHY_E:
3006                 return PHYLD_4;
3007         case TRANSMITTER_UNIPHY_F:
3008                 return PHYLD_5;
3009         case TRANSMITTER_NUTMEG_CRT:
3010                 return PHYLD_6;
3011         case TRANSMITTER_TRAVIS_CRT:
3012                 return PHYLD_7;
3013         case TRANSMITTER_TRAVIS_LCD:
3014                 return PHYLD_8;
3015         case TRANSMITTER_UNIPHY_G:
3016                 return PHYLD_9;
3017         case TRANSMITTER_COUNT:
3018                 return PHYLD_COUNT;
3019         case TRANSMITTER_UNKNOWN:
3020                 return PHYLD_UNKNOWN;
3021         default:
3022                 WARN_ONCE(1, "Unknown transmitter value %d\n",
3023                           transmitter_value);
3024                 return PHYLD_UNKNOWN;
3025         }
3026 }
3027
3028 bool dc_link_setup_psr(struct dc_link *link,
3029                 const struct dc_stream_state *stream, struct psr_config *psr_config,
3030                 struct psr_context *psr_context)
3031 {
3032         struct dc *dc;
3033         struct dmcu *dmcu;
3034         struct dmub_psr *psr;
3035         int i;
3036         unsigned int panel_inst;
3037         /* updateSinkPsrDpcdConfig*/
3038         union dpcd_psr_configuration psr_configuration;
3039
3040         psr_context->controllerId = CONTROLLER_ID_UNDEFINED;
3041
3042         if (!link)
3043                 return false;
3044
3045         dc = link->ctx->dc;
3046         dmcu = dc->res_pool->dmcu;
3047         psr = dc->res_pool->psr;
3048
3049         if (!dmcu && !psr)
3050                 return false;
3051
3052         if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
3053                 return false;
3054
3055
3056         memset(&psr_configuration, 0, sizeof(psr_configuration));
3057
3058         psr_configuration.bits.ENABLE                    = 1;
3059         psr_configuration.bits.CRC_VERIFICATION          = 1;
3060         psr_configuration.bits.FRAME_CAPTURE_INDICATION  =
3061                         psr_config->psr_frame_capture_indication_req;
3062
3063         /* Check for PSR v2*/
3064         if (psr_config->psr_version == 0x2) {
3065                 /* For PSR v2 selective update.
3066                  * Indicates whether sink should start capturing
3067                  * immediately following active scan line,
3068                  * or starting with the 2nd active scan line.
3069                  */
3070                 psr_configuration.bits.LINE_CAPTURE_INDICATION = 0;
3071                 /*For PSR v2, determines whether Sink should generate
3072                  * IRQ_HPD when CRC mismatch is detected.
3073                  */
3074                 psr_configuration.bits.IRQ_HPD_WITH_CRC_ERROR    = 1;
3075         }
3076
3077         dm_helpers_dp_write_dpcd(
3078                 link->ctx,
3079                 link,
3080                 368,
3081                 &psr_configuration.raw,
3082                 sizeof(psr_configuration.raw));
3083
3084         psr_context->channel = link->ddc->ddc_pin->hw_info.ddc_channel;
3085         psr_context->transmitterId = link->link_enc->transmitter;
3086         psr_context->engineId = link->link_enc->preferred_engine;
3087
3088         for (i = 0; i < MAX_PIPES; i++) {
3089                 if (dc->current_state->res_ctx.pipe_ctx[i].stream
3090                                 == stream) {
3091                         /* dmcu -1 for all controller id values,
3092                          * therefore +1 here
3093                          */
3094                         psr_context->controllerId =
3095                                 dc->current_state->res_ctx.
3096                                 pipe_ctx[i].stream_res.tg->inst + 1;
3097                         break;
3098                 }
3099         }
3100
3101         /* Hardcoded for now.  Can be Pcie or Uniphy (or Unknown)*/
3102         psr_context->phyType = PHY_TYPE_UNIPHY;
3103         /*PhyId is associated with the transmitter id*/
3104         psr_context->smuPhyId =
3105                 transmitter_to_phy_id(link->link_enc->transmitter);
3106
3107         psr_context->crtcTimingVerticalTotal = stream->timing.v_total;
3108         psr_context->vsync_rate_hz = div64_u64(div64_u64((stream->
3109                                         timing.pix_clk_100hz * 100),
3110                                         stream->timing.v_total),
3111                                         stream->timing.h_total);
3112
3113         psr_context->psrSupportedDisplayConfig = true;
3114         psr_context->psrExitLinkTrainingRequired =
3115                 psr_config->psr_exit_link_training_required;
3116         psr_context->sdpTransmitLineNumDeadline =
3117                 psr_config->psr_sdp_transmit_line_num_deadline;
3118         psr_context->psrFrameCaptureIndicationReq =
3119                 psr_config->psr_frame_capture_indication_req;
3120
3121         psr_context->skipPsrWaitForPllLock = 0; /* only = 1 in KV */
3122
3123         psr_context->numberOfControllers =
3124                         link->dc->res_pool->timing_generator_count;
3125
3126         psr_context->rfb_update_auto_en = true;
3127
3128         /* 2 frames before enter PSR. */
3129         psr_context->timehyst_frames = 2;
3130         /* half a frame
3131          * (units in 100 lines, i.e. a value of 1 represents 100 lines)
3132          */
3133         psr_context->hyst_lines = stream->timing.v_total / 2 / 100;
3134         psr_context->aux_repeats = 10;
3135
3136         psr_context->psr_level.u32all = 0;
3137
3138         /*skip power down the single pipe since it blocks the cstate*/
3139 #if defined(CONFIG_DRM_AMD_DC_DCN)
3140         if (link->ctx->asic_id.chip_family >= FAMILY_RV) {
3141                 psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true;
3142                 if (link->ctx->asic_id.chip_family == FAMILY_YELLOW_CARP && !dc->debug.disable_z10)
3143                         psr_context->psr_level.bits.SKIP_CRTC_DISABLE = false;
3144         }
3145 #else
3146         if (link->ctx->asic_id.chip_family >= FAMILY_RV)
3147                 psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true;
3148 #endif
3149
3150         /* SMU will perform additional powerdown sequence.
3151          * For unsupported ASICs, set psr_level flag to skip PSR
3152          *  static screen notification to SMU.
3153          *  (Always set for DAL2, did not check ASIC)
3154          */
3155         psr_context->allow_smu_optimizations = psr_config->allow_smu_optimizations;
3156         psr_context->allow_multi_disp_optimizations = psr_config->allow_multi_disp_optimizations;
3157
3158         /* Complete PSR entry before aborting to prevent intermittent
3159          * freezes on certain eDPs
3160          */
3161         psr_context->psr_level.bits.DISABLE_PSR_ENTRY_ABORT = 1;
3162
3163         /* Controls additional delay after remote frame capture before
3164          * continuing power down, default = 0
3165          */
3166         psr_context->frame_delay = 0;
3167
3168         if (psr)
3169                 link->psr_settings.psr_feature_enabled = psr->funcs->psr_copy_settings(psr,
3170                         link, psr_context, panel_inst);
3171         else
3172                 link->psr_settings.psr_feature_enabled = dmcu->funcs->setup_psr(dmcu, link, psr_context);
3173
3174         /* psr_enabled == 0 indicates setup_psr did not succeed, but this
3175          * should not happen since firmware should be running at this point
3176          */
3177         if (link->psr_settings.psr_feature_enabled == 0)
3178                 ASSERT(0);
3179
3180         return true;
3181
3182 }
3183
3184 void dc_link_get_psr_residency(const struct dc_link *link, uint32_t *residency)
3185 {
3186         struct dc  *dc = link->ctx->dc;
3187         struct dmub_psr *psr = dc->res_pool->psr;
3188         unsigned int panel_inst;
3189
3190         if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
3191                 return;
3192
3193         /* PSR residency measurements only supported on DMCUB */
3194         if (psr != NULL && link->psr_settings.psr_feature_enabled)
3195                 psr->funcs->psr_get_residency(psr, residency, panel_inst);
3196         else
3197                 *residency = 0;
3198 }
3199
3200 const struct dc_link_status *dc_link_get_status(const struct dc_link *link)
3201 {
3202         return &link->link_status;
3203 }
3204
3205 void core_link_resume(struct dc_link *link)
3206 {
3207         if (link->connector_signal != SIGNAL_TYPE_VIRTUAL)
3208                 program_hpd_filter(link);
3209 }
3210
3211 static struct fixed31_32 get_pbn_per_slot(struct dc_stream_state *stream)
3212 {
3213         struct fixed31_32 mbytes_per_sec;
3214         uint32_t link_rate_in_mbytes_per_sec = dc_link_bandwidth_kbps(stream->link,
3215                         &stream->link->cur_link_settings);
3216         link_rate_in_mbytes_per_sec /= 8000; /* Kbits to MBytes */
3217
3218         mbytes_per_sec = dc_fixpt_from_int(link_rate_in_mbytes_per_sec);
3219
3220         return dc_fixpt_div_int(mbytes_per_sec, 54);
3221 }
3222
3223 static struct fixed31_32 get_pbn_from_bw_in_kbps(uint64_t kbps)
3224 {
3225         struct fixed31_32 peak_kbps;
3226         uint32_t numerator = 0;
3227         uint32_t denominator = 1;
3228
3229         /*
3230          * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
3231          * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on
3232          * common multiplier to render an integer PBN for all link rate/lane
3233          * counts combinations
3234          * calculate
3235          * peak_kbps *= (1006/1000)
3236          * peak_kbps *= (64/54)
3237          * peak_kbps *= 8    convert to bytes
3238          */
3239
3240         numerator = 64 * PEAK_FACTOR_X1000;
3241         denominator = 54 * 8 * 1000 * 1000;
3242         kbps *= numerator;
3243         peak_kbps = dc_fixpt_from_fraction(kbps, denominator);
3244
3245         return peak_kbps;
3246 }
3247
3248 static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx)
3249 {
3250         uint64_t kbps;
3251
3252         kbps = dc_bandwidth_in_kbps_from_timing(&pipe_ctx->stream->timing);
3253         return get_pbn_from_bw_in_kbps(kbps);
3254 }
3255
3256 static void update_mst_stream_alloc_table(
3257         struct dc_link *link,
3258         struct stream_encoder *stream_enc,
3259 #if defined(CONFIG_DRM_AMD_DC_DCN)
3260         struct hpo_dp_stream_encoder *hpo_dp_stream_enc, // TODO: Rename stream_enc to dio_stream_enc?
3261 #endif
3262         const struct dp_mst_stream_allocation_table *proposed_table)
3263 {
3264         struct link_mst_stream_allocation work_table[MAX_CONTROLLER_NUM] = { 0 };
3265         struct link_mst_stream_allocation *dc_alloc;
3266
3267         int i;
3268         int j;
3269
3270         /* if DRM proposed_table has more than one new payload */
3271         ASSERT(proposed_table->stream_count -
3272                         link->mst_stream_alloc_table.stream_count < 2);
3273
3274         /* copy proposed_table to link, add stream encoder */
3275         for (i = 0; i < proposed_table->stream_count; i++) {
3276
3277                 for (j = 0; j < link->mst_stream_alloc_table.stream_count; j++) {
3278                         dc_alloc =
3279                         &link->mst_stream_alloc_table.stream_allocations[j];
3280
3281                         if (dc_alloc->vcp_id ==
3282                                 proposed_table->stream_allocations[i].vcp_id) {
3283
3284                                 work_table[i] = *dc_alloc;
3285                                 work_table[i].slot_count = proposed_table->stream_allocations[i].slot_count;
3286                                 break; /* exit j loop */
3287                         }
3288                 }
3289
3290                 /* new vcp_id */
3291                 if (j == link->mst_stream_alloc_table.stream_count) {
3292                         work_table[i].vcp_id =
3293                                 proposed_table->stream_allocations[i].vcp_id;
3294                         work_table[i].slot_count =
3295                                 proposed_table->stream_allocations[i].slot_count;
3296                         work_table[i].stream_enc = stream_enc;
3297 #if defined(CONFIG_DRM_AMD_DC_DCN)
3298                         work_table[i].hpo_dp_stream_enc = hpo_dp_stream_enc;
3299 #endif
3300                 }
3301         }
3302
3303         /* update link->mst_stream_alloc_table with work_table */
3304         link->mst_stream_alloc_table.stream_count =
3305                         proposed_table->stream_count;
3306         for (i = 0; i < MAX_CONTROLLER_NUM; i++)
3307                 link->mst_stream_alloc_table.stream_allocations[i] =
3308                                 work_table[i];
3309 }
3310 #if defined(CONFIG_DRM_AMD_DC_DCN)
3311 static void dc_log_vcp_x_y(const struct dc_link *link, struct fixed31_32 avg_time_slots_per_mtp)
3312 {
3313         const uint32_t VCP_Y_PRECISION = 1000;
3314         uint64_t vcp_x, vcp_y;
3315
3316         // Add 0.5*(1/VCP_Y_PRECISION) to round up to decimal precision
3317         avg_time_slots_per_mtp = dc_fixpt_add(
3318                         avg_time_slots_per_mtp, dc_fixpt_from_fraction(1, 2 * VCP_Y_PRECISION));
3319
3320         vcp_x = dc_fixpt_floor(avg_time_slots_per_mtp);
3321         vcp_y = dc_fixpt_floor(
3322                         dc_fixpt_mul_int(
3323                                 dc_fixpt_sub_int(avg_time_slots_per_mtp, dc_fixpt_floor(avg_time_slots_per_mtp)),
3324                                 VCP_Y_PRECISION));
3325
3326         if (link->type == dc_connection_mst_branch)
3327                 DC_LOG_DP2("MST Update Payload: set_throttled_vcp_size slot X.Y for MST stream "
3328                                 "X: %lld Y: %lld/%d", vcp_x, vcp_y, VCP_Y_PRECISION);
3329         else
3330                 DC_LOG_DP2("SST Update Payload: set_throttled_vcp_size slot X.Y for SST stream "
3331                                 "X: %lld Y: %lld/%d", vcp_x, vcp_y, VCP_Y_PRECISION);
3332 }
3333
3334 /*
3335  * Payload allocation/deallocation for SST introduced in DP2.0
3336  */
3337 enum dc_status dc_link_update_sst_payload(struct pipe_ctx *pipe_ctx, bool allocate)
3338 {
3339         struct dc_stream_state *stream = pipe_ctx->stream;
3340         struct dc_link *link = stream->link;
3341         struct hpo_dp_link_encoder *hpo_dp_link_encoder = link->hpo_dp_link_enc;
3342         struct hpo_dp_stream_encoder *hpo_dp_stream_encoder = pipe_ctx->stream_res.hpo_dp_stream_enc;
3343         struct link_mst_stream_allocation_table proposed_table = {0};
3344         struct fixed31_32 avg_time_slots_per_mtp;
3345         DC_LOGGER_INIT(link->ctx->logger);
3346
3347         /* slot X.Y for SST payload deallocate */
3348         if (!allocate) {
3349                 avg_time_slots_per_mtp = dc_fixpt_from_int(0);
3350
3351                 dc_log_vcp_x_y(link, avg_time_slots_per_mtp);
3352
3353                 hpo_dp_link_encoder->funcs->set_throttled_vcp_size(
3354                                 hpo_dp_link_encoder,
3355                                 hpo_dp_stream_encoder->inst,
3356                                 avg_time_slots_per_mtp);
3357         }
3358
3359         /* calculate VC payload and update branch with new payload allocation table*/
3360         if (!dpcd_write_128b_132b_sst_payload_allocation_table(
3361                         stream,
3362                         link,
3363                         &proposed_table,
3364                         allocate)) {
3365                 DC_LOG_ERROR("SST Update Payload: Failed to update "
3366                                                 "allocation table for "
3367                                                 "pipe idx: %d\n",
3368                                                 pipe_ctx->pipe_idx);
3369         }
3370
3371         proposed_table.stream_allocations[0].hpo_dp_stream_enc = hpo_dp_stream_encoder;
3372
3373         ASSERT(proposed_table.stream_count == 1);
3374
3375         //TODO - DP2.0 Logging: Instead of hpo_dp_stream_enc pointer, log instance id
3376         DC_LOG_DP2("SST Update Payload: hpo_dp_stream_enc: %p      "
3377                 "vcp_id: %d      "
3378                 "slot_count: %d\n",
3379                 (void *) proposed_table.stream_allocations[0].hpo_dp_stream_enc,
3380                 proposed_table.stream_allocations[0].vcp_id,
3381                 proposed_table.stream_allocations[0].slot_count);
3382
3383         /* program DP source TX for payload */
3384         hpo_dp_link_encoder->funcs->update_stream_allocation_table(
3385                         hpo_dp_link_encoder,
3386                         &proposed_table);
3387
3388         /* poll for ACT handled */
3389         if (!dpcd_poll_for_allocation_change_trigger(link)) {
3390                 // Failures will result in blackscreen and errors logged
3391                 BREAK_TO_DEBUGGER();
3392         }
3393
3394         /* slot X.Y for SST payload allocate */
3395         if (allocate) {
3396                 avg_time_slots_per_mtp = calculate_sst_avg_time_slots_per_mtp(stream, link);
3397
3398                 dc_log_vcp_x_y(link, avg_time_slots_per_mtp);
3399
3400                 hpo_dp_link_encoder->funcs->set_throttled_vcp_size(
3401                                 hpo_dp_link_encoder,
3402                                 hpo_dp_stream_encoder->inst,
3403                                 avg_time_slots_per_mtp);
3404         }
3405
3406         /* Always return DC_OK.
3407          * If part of sequence fails, log failure(s) and show blackscreen
3408          */
3409         return DC_OK;
3410 }
3411 #endif
3412
3413 /* convert link_mst_stream_alloc_table to dm dp_mst_stream_alloc_table
3414  * because stream_encoder is not exposed to dm
3415  */
3416 enum dc_status dc_link_allocate_mst_payload(struct pipe_ctx *pipe_ctx)
3417 {
3418         struct dc_stream_state *stream = pipe_ctx->stream;
3419         struct dc_link *link = stream->link;
3420         struct link_encoder *link_encoder = NULL;
3421         struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
3422 #if defined(CONFIG_DRM_AMD_DC_DCN)
3423         struct hpo_dp_link_encoder *hpo_dp_link_encoder = link->hpo_dp_link_enc;
3424         struct hpo_dp_stream_encoder *hpo_dp_stream_encoder = pipe_ctx->stream_res.hpo_dp_stream_enc;
3425 #endif
3426         struct dp_mst_stream_allocation_table proposed_table = {0};
3427         struct fixed31_32 avg_time_slots_per_mtp;
3428         struct fixed31_32 pbn;
3429         struct fixed31_32 pbn_per_slot;
3430         int i;
3431         enum act_return_status ret;
3432         DC_LOGGER_INIT(link->ctx->logger);
3433
3434         /* Link encoder may have been dynamically assigned to non-physical display endpoint. */
3435         if (link->ep_type == DISPLAY_ENDPOINT_PHY)
3436                 link_encoder = link->link_enc;
3437         else if (link->dc->res_pool->funcs->link_encs_assign)
3438                 link_encoder = link_enc_cfg_get_link_enc_used_by_stream(pipe_ctx->stream->ctx->dc, stream);
3439         ASSERT(link_encoder);
3440
3441         /* enable_link_dp_mst already check link->enabled_stream_count
3442          * and stream is in link->stream[]. This is called during set mode,
3443          * stream_enc is available.
3444          */
3445
3446         /* get calculate VC payload for stream: stream_alloc */
3447         if (dm_helpers_dp_mst_write_payload_allocation_table(
3448                 stream->ctx,
3449                 stream,
3450                 &proposed_table,
3451                 true)) {
3452                 update_mst_stream_alloc_table(
3453 #if defined(CONFIG_DRM_AMD_DC_DCN)
3454                                         link,
3455                                         pipe_ctx->stream_res.stream_enc,
3456                                         pipe_ctx->stream_res.hpo_dp_stream_enc,
3457                                         &proposed_table);
3458 #else
3459                                         link, pipe_ctx->stream_res.stream_enc, &proposed_table);
3460 #endif
3461         }
3462         else
3463                 DC_LOG_WARNING("Failed to update"
3464                                 "MST allocation table for"
3465                                 "pipe idx:%d\n",
3466                                 pipe_ctx->pipe_idx);
3467
3468         DC_LOG_MST("%s  "
3469                         "stream_count: %d: \n ",
3470                         __func__,
3471                         link->mst_stream_alloc_table.stream_count);
3472
3473         for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
3474 #if defined(CONFIG_DRM_AMD_DC_DCN)
3475                 DC_LOG_MST("stream_enc[%d]: %p      "
3476                 "stream[%d].hpo_dp_stream_enc: %p      "
3477                 "stream[%d].vcp_id: %d      "
3478                 "stream[%d].slot_count: %d\n",
3479                 i,
3480                 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
3481                 i,
3482                 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc,
3483                 i,
3484                 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
3485                 i,
3486                 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
3487 #else
3488                 DC_LOG_MST("stream_enc[%d]: %p      "
3489                 "stream[%d].vcp_id: %d      "
3490                 "stream[%d].slot_count: %d\n",
3491                 i,
3492                 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
3493                 i,
3494                 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
3495                 i,
3496                 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
3497 #endif
3498         }
3499
3500         ASSERT(proposed_table.stream_count > 0);
3501
3502         if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) {
3503                 static enum dc_status status;
3504                 uint8_t mst_alloc_slots = 0, prev_mst_slots_in_use = 0xFF;
3505
3506                 for (i = 0; i < link->mst_stream_alloc_table.stream_count; i++)
3507                         mst_alloc_slots += link->mst_stream_alloc_table.stream_allocations[i].slot_count;
3508
3509                 status = dc_process_dmub_set_mst_slots(link->dc, link->link_index,
3510                         mst_alloc_slots, &prev_mst_slots_in_use);
3511                 ASSERT(status == DC_OK);
3512                 DC_LOG_MST("dpia : status[%d]: alloc_slots[%d]: used_slots[%d]\n",
3513                                 status, mst_alloc_slots, prev_mst_slots_in_use);
3514         }
3515
3516         /* program DP source TX for payload */
3517 #if defined(CONFIG_DRM_AMD_DC_DCN)
3518         switch (dp_get_link_encoding_format(&link->cur_link_settings)) {
3519         case DP_8b_10b_ENCODING:
3520                 link_encoder->funcs->update_mst_stream_allocation_table(
3521                         link_encoder,
3522                         &link->mst_stream_alloc_table);
3523                 break;
3524         case DP_128b_132b_ENCODING:
3525                 hpo_dp_link_encoder->funcs->update_stream_allocation_table(
3526                                 hpo_dp_link_encoder,
3527                                 &link->mst_stream_alloc_table);
3528                 break;
3529         case DP_UNKNOWN_ENCODING:
3530                 DC_LOG_ERROR("Failure: unknown encoding format\n");
3531                 return DC_ERROR_UNEXPECTED;
3532         }
3533 #else
3534         link_encoder->funcs->update_mst_stream_allocation_table(
3535                 link_encoder,
3536                 &link->mst_stream_alloc_table);
3537 #endif
3538
3539         /* send down message */
3540         ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger(
3541                         stream->ctx,
3542                         stream);
3543
3544         if (ret != ACT_LINK_LOST) {
3545                 dm_helpers_dp_mst_send_payload_allocation(
3546                                 stream->ctx,
3547                                 stream,
3548                                 true);
3549         }
3550
3551         /* slot X.Y for only current stream */
3552         pbn_per_slot = get_pbn_per_slot(stream);
3553         if (pbn_per_slot.value == 0) {
3554                 DC_LOG_ERROR("Failure: pbn_per_slot==0 not allowed. Cannot continue, returning DC_UNSUPPORTED_VALUE.\n");
3555                 return DC_UNSUPPORTED_VALUE;
3556         }
3557         pbn = get_pbn_from_timing(pipe_ctx);
3558         avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot);
3559
3560 #if defined(CONFIG_DRM_AMD_DC_DCN)
3561         switch (dp_get_link_encoding_format(&link->cur_link_settings)) {
3562         case DP_8b_10b_ENCODING:
3563                 stream_encoder->funcs->set_throttled_vcp_size(
3564                         stream_encoder,
3565                         avg_time_slots_per_mtp);
3566                 break;
3567         case DP_128b_132b_ENCODING:
3568                 hpo_dp_link_encoder->funcs->set_throttled_vcp_size(
3569                                 hpo_dp_link_encoder,
3570                                 hpo_dp_stream_encoder->inst,
3571                                 avg_time_slots_per_mtp);
3572                 break;
3573         case DP_UNKNOWN_ENCODING:
3574                 DC_LOG_ERROR("Failure: unknown encoding format\n");
3575                 return DC_ERROR_UNEXPECTED;
3576         }
3577 #else
3578         stream_encoder->funcs->set_throttled_vcp_size(
3579                 stream_encoder,
3580                 avg_time_slots_per_mtp);
3581 #endif
3582
3583         return DC_OK;
3584
3585 }
3586
3587 #if defined(CONFIG_DRM_AMD_DC_DCN)
3588 enum dc_status dc_link_reduce_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps)
3589 {
3590         struct dc_stream_state *stream = pipe_ctx->stream;
3591         struct dc_link *link = stream->link;
3592         struct fixed31_32 avg_time_slots_per_mtp;
3593         struct fixed31_32 pbn;
3594         struct fixed31_32 pbn_per_slot;
3595         struct link_encoder *link_encoder = link->link_enc;
3596         struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
3597         struct dp_mst_stream_allocation_table proposed_table = {0};
3598         uint8_t i;
3599         enum act_return_status ret;
3600         DC_LOGGER_INIT(link->ctx->logger);
3601
3602         /* decrease throttled vcp size */
3603         pbn_per_slot = get_pbn_per_slot(stream);
3604         pbn = get_pbn_from_bw_in_kbps(bw_in_kbps);
3605         avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot);
3606
3607         stream_encoder->funcs->set_throttled_vcp_size(
3608                                 stream_encoder,
3609                                 avg_time_slots_per_mtp);
3610
3611         /* send ALLOCATE_PAYLOAD sideband message with updated pbn */
3612         dm_helpers_dp_mst_send_payload_allocation(
3613                         stream->ctx,
3614                         stream,
3615                         true);
3616
3617         /* notify immediate branch device table update */
3618         if (dm_helpers_dp_mst_write_payload_allocation_table(
3619                         stream->ctx,
3620                         stream,
3621                         &proposed_table,
3622                         true)) {
3623                 /* update mst stream allocation table software state */
3624                 update_mst_stream_alloc_table(
3625                                 link,
3626                                 pipe_ctx->stream_res.stream_enc,
3627                                 pipe_ctx->stream_res.hpo_dp_stream_enc,
3628                                 &proposed_table);
3629         } else {
3630                 DC_LOG_WARNING("Failed to update"
3631                                 "MST allocation table for"
3632                                 "pipe idx:%d\n",
3633                                 pipe_ctx->pipe_idx);
3634         }
3635
3636         DC_LOG_MST("%s  "
3637                         "stream_count: %d: \n ",
3638                         __func__,
3639                         link->mst_stream_alloc_table.stream_count);
3640
3641         for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
3642                 DC_LOG_MST("stream_enc[%d]: %p      "
3643                                 "stream[%d].vcp_id: %d      "
3644                                 "stream[%d].slot_count: %d\n",
3645                                 i,
3646                                 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
3647                                 i,
3648                                 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
3649                                 i,
3650                                 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
3651         }
3652
3653         ASSERT(proposed_table.stream_count > 0);
3654
3655         /* update mst stream allocation table hardware state */
3656         link_encoder->funcs->update_mst_stream_allocation_table(
3657                         link_encoder,
3658                         &link->mst_stream_alloc_table);
3659
3660         /* poll for immediate branch device ACT handled */
3661         ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger(
3662                         stream->ctx,
3663                         stream);
3664
3665         return DC_OK;
3666 }
3667
3668 enum dc_status dc_link_increase_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps)
3669 {
3670         struct dc_stream_state *stream = pipe_ctx->stream;
3671         struct dc_link *link = stream->link;
3672         struct fixed31_32 avg_time_slots_per_mtp;
3673         struct fixed31_32 pbn;
3674         struct fixed31_32 pbn_per_slot;
3675         struct link_encoder *link_encoder = link->link_enc;
3676         struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
3677         struct dp_mst_stream_allocation_table proposed_table = {0};
3678         uint8_t i;
3679         enum act_return_status ret;
3680         DC_LOGGER_INIT(link->ctx->logger);
3681
3682         /* notify immediate branch device table update */
3683         if (dm_helpers_dp_mst_write_payload_allocation_table(
3684                                 stream->ctx,
3685                                 stream,
3686                                 &proposed_table,
3687                                 true)) {
3688                 /* update mst stream allocation table software state */
3689                 update_mst_stream_alloc_table(
3690                                 link,
3691                                 pipe_ctx->stream_res.stream_enc,
3692                                 pipe_ctx->stream_res.hpo_dp_stream_enc,
3693                                 &proposed_table);
3694         }
3695
3696         DC_LOG_MST("%s  "
3697                         "stream_count: %d: \n ",
3698                         __func__,
3699                         link->mst_stream_alloc_table.stream_count);
3700
3701         for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
3702                 DC_LOG_MST("stream_enc[%d]: %p      "
3703                                 "stream[%d].vcp_id: %d      "
3704                                 "stream[%d].slot_count: %d\n",
3705                                 i,
3706                                 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
3707                                 i,
3708                                 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
3709                                 i,
3710                                 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
3711         }
3712
3713         ASSERT(proposed_table.stream_count > 0);
3714
3715         /* update mst stream allocation table hardware state */
3716         link_encoder->funcs->update_mst_stream_allocation_table(
3717                         link_encoder,
3718                         &link->mst_stream_alloc_table);
3719
3720         /* poll for immediate branch device ACT handled */
3721         ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger(
3722                         stream->ctx,
3723                         stream);
3724
3725         if (ret != ACT_LINK_LOST) {
3726                 /* send ALLOCATE_PAYLOAD sideband message with updated pbn */
3727                 dm_helpers_dp_mst_send_payload_allocation(
3728                                 stream->ctx,
3729                                 stream,
3730                                 true);
3731         }
3732
3733         /* increase throttled vcp size */
3734         pbn = get_pbn_from_bw_in_kbps(bw_in_kbps);
3735         pbn_per_slot = get_pbn_per_slot(stream);
3736         avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot);
3737
3738         stream_encoder->funcs->set_throttled_vcp_size(
3739                                 stream_encoder,
3740                                 avg_time_slots_per_mtp);
3741
3742         return DC_OK;
3743 }
3744 #endif
3745
3746 static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx)
3747 {
3748         struct dc_stream_state *stream = pipe_ctx->stream;
3749         struct dc_link *link = stream->link;
3750         struct link_encoder *link_encoder = NULL;
3751         struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
3752 #if defined(CONFIG_DRM_AMD_DC_DCN)
3753         struct hpo_dp_link_encoder *hpo_dp_link_encoder = link->hpo_dp_link_enc;
3754         struct hpo_dp_stream_encoder *hpo_dp_stream_encoder = pipe_ctx->stream_res.hpo_dp_stream_enc;
3755 #endif
3756         struct dp_mst_stream_allocation_table proposed_table = {0};
3757         struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0);
3758         int i;
3759         bool mst_mode = (link->type == dc_connection_mst_branch);
3760         DC_LOGGER_INIT(link->ctx->logger);
3761
3762         /* Link encoder may have been dynamically assigned to non-physical display endpoint. */
3763         if (link->ep_type == DISPLAY_ENDPOINT_PHY)
3764                 link_encoder = link->link_enc;
3765         else if (link->dc->res_pool->funcs->link_encs_assign)
3766                 link_encoder = link_enc_cfg_get_link_enc_used_by_stream(pipe_ctx->stream->ctx->dc, stream);
3767         ASSERT(link_encoder);
3768
3769         /* deallocate_mst_payload is called before disable link. When mode or
3770          * disable/enable monitor, new stream is created which is not in link
3771          * stream[] yet. For this, payload is not allocated yet, so de-alloc
3772          * should not done. For new mode set, map_resources will get engine
3773          * for new stream, so stream_enc->id should be validated until here.
3774          */
3775
3776         /* slot X.Y */
3777 #if defined(CONFIG_DRM_AMD_DC_DCN)
3778         switch (dp_get_link_encoding_format(&link->cur_link_settings)) {
3779         case DP_8b_10b_ENCODING:
3780                 stream_encoder->funcs->set_throttled_vcp_size(
3781                         stream_encoder,
3782                         avg_time_slots_per_mtp);
3783                 break;
3784         case DP_128b_132b_ENCODING:
3785                 hpo_dp_link_encoder->funcs->set_throttled_vcp_size(
3786                                 hpo_dp_link_encoder,
3787                                 hpo_dp_stream_encoder->inst,
3788                                 avg_time_slots_per_mtp);
3789                 break;
3790         case DP_UNKNOWN_ENCODING:
3791                 DC_LOG_ERROR("Failure: unknown encoding format\n");
3792                 return DC_ERROR_UNEXPECTED;
3793         }
3794 #else
3795         stream_encoder->funcs->set_throttled_vcp_size(
3796                 stream_encoder,
3797                 avg_time_slots_per_mtp);
3798 #endif
3799
3800         /* TODO: which component is responsible for remove payload table? */
3801         if (mst_mode) {
3802                 if (dm_helpers_dp_mst_write_payload_allocation_table(
3803                                 stream->ctx,
3804                                 stream,
3805                                 &proposed_table,
3806                                 false)) {
3807
3808 #if defined(CONFIG_DRM_AMD_DC_DCN)
3809                         update_mst_stream_alloc_table(
3810                                                 link,
3811                                                 pipe_ctx->stream_res.stream_enc,
3812                                                 pipe_ctx->stream_res.hpo_dp_stream_enc,
3813                                                 &proposed_table);
3814 #else
3815                         update_mst_stream_alloc_table(
3816                                 link, pipe_ctx->stream_res.stream_enc, &proposed_table);
3817 #endif
3818                 }
3819                 else {
3820                                 DC_LOG_WARNING("Failed to update"
3821                                                 "MST allocation table for"
3822                                                 "pipe idx:%d\n",
3823                                                 pipe_ctx->pipe_idx);
3824                 }
3825         }
3826
3827         DC_LOG_MST("%s"
3828                         "stream_count: %d: ",
3829                         __func__,
3830                         link->mst_stream_alloc_table.stream_count);
3831
3832         for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
3833 #if defined(CONFIG_DRM_AMD_DC_DCN)
3834                 DC_LOG_MST("stream_enc[%d]: %p      "
3835                 "stream[%d].hpo_dp_stream_enc: %p      "
3836                 "stream[%d].vcp_id: %d      "
3837                 "stream[%d].slot_count: %d\n",
3838                 i,
3839                 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
3840                 i,
3841                 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc,
3842                 i,
3843                 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
3844                 i,
3845                 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
3846 #else
3847                 DC_LOG_MST("stream_enc[%d]: %p      "
3848                 "stream[%d].vcp_id: %d      "
3849                 "stream[%d].slot_count: %d\n",
3850                 i,
3851                 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
3852                 i,
3853                 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
3854                 i,
3855                 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
3856 #endif
3857         }
3858
3859         if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) {
3860                 enum dc_status status;
3861                 uint8_t mst_alloc_slots = 0, prev_mst_slots_in_use = 0xFF;
3862
3863                 for (i = 0; i < link->mst_stream_alloc_table.stream_count; i++)
3864                         mst_alloc_slots += link->mst_stream_alloc_table.stream_allocations[i].slot_count;
3865
3866                 status = dc_process_dmub_set_mst_slots(link->dc, link->link_index,
3867                         mst_alloc_slots, &prev_mst_slots_in_use);
3868                 ASSERT(status != DC_NOT_SUPPORTED);
3869                 DC_LOG_MST("dpia : status[%d]: alloc_slots[%d]: used_slots[%d]\n",
3870                                 status, mst_alloc_slots, prev_mst_slots_in_use);
3871         }
3872
3873 #if defined(CONFIG_DRM_AMD_DC_DCN)
3874         switch (dp_get_link_encoding_format(&link->cur_link_settings)) {
3875         case DP_8b_10b_ENCODING:
3876                 link_encoder->funcs->update_mst_stream_allocation_table(
3877                         link_encoder,
3878                         &link->mst_stream_alloc_table);
3879                 break;
3880         case DP_128b_132b_ENCODING:
3881                 hpo_dp_link_encoder->funcs->update_stream_allocation_table(
3882                                 hpo_dp_link_encoder,
3883                                 &link->mst_stream_alloc_table);
3884                 break;
3885         case DP_UNKNOWN_ENCODING:
3886                 DC_LOG_ERROR("Failure: unknown encoding format\n");
3887                 return DC_ERROR_UNEXPECTED;
3888         }
3889 #else
3890         link_encoder->funcs->update_mst_stream_allocation_table(
3891                 link_encoder,
3892                 &link->mst_stream_alloc_table);
3893 #endif
3894
3895         if (mst_mode) {
3896                 dm_helpers_dp_mst_poll_for_allocation_change_trigger(
3897                         stream->ctx,
3898                         stream);
3899
3900                 dm_helpers_dp_mst_send_payload_allocation(
3901                         stream->ctx,
3902                         stream,
3903                         false);
3904         }
3905
3906         return DC_OK;
3907 }
3908
3909
3910 #if defined(CONFIG_DRM_AMD_DC_HDCP)
3911 static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off)
3912 {
3913         struct cp_psp *cp_psp = &pipe_ctx->stream->ctx->cp_psp;
3914 #if defined(CONFIG_DRM_AMD_DC_DCN)
3915         struct link_encoder *link_enc = NULL;
3916         struct dc_state *state = pipe_ctx->stream->ctx->dc->current_state;
3917         struct link_enc_assignment link_enc_assign;
3918         int i;
3919 #endif
3920
3921         if (cp_psp && cp_psp->funcs.update_stream_config) {
3922                 struct cp_psp_stream_config config = {0};
3923                 enum dp_panel_mode panel_mode =
3924                                 dp_get_panel_mode(pipe_ctx->stream->link);
3925
3926                 config.otg_inst = (uint8_t) pipe_ctx->stream_res.tg->inst;
3927                 /*stream_enc_inst*/
3928                 config.dig_fe = (uint8_t) pipe_ctx->stream_res.stream_enc->stream_enc_inst;
3929                 config.dig_be = pipe_ctx->stream->link->link_enc_hw_inst;
3930 #if defined(CONFIG_DRM_AMD_DC_DCN)
3931                 config.stream_enc_idx = pipe_ctx->stream_res.stream_enc->id - ENGINE_ID_DIGA;
3932
3933                 if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_PHY ||
3934                                 pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) {
3935                         link_enc = pipe_ctx->stream->link->link_enc;
3936                         config.dio_output_type = pipe_ctx->stream->link->ep_type;
3937                         config.dio_output_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A;
3938                         if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_PHY)
3939                                 link_enc = pipe_ctx->stream->link->link_enc;
3940                         else if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
3941                                 if (pipe_ctx->stream->link->dc->res_pool->funcs->link_encs_assign) {
3942                                         link_enc = link_enc_cfg_get_link_enc_used_by_stream(
3943                                                         pipe_ctx->stream->ctx->dc,
3944                                                         pipe_ctx->stream);
3945                         }
3946                         // Initialize PHY ID with ABCDE - 01234 mapping except when it is B0
3947                         config.phy_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A;
3948
3949                         //look up the link_enc_assignment for the current pipe_ctx
3950                         for (i = 0; i < state->stream_count; i++) {
3951                                 if (pipe_ctx->stream == state->streams[i]) {
3952                                         link_enc_assign = state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[i];
3953                                 }
3954                         }
3955                         // Add flag to guard new A0 DIG mapping
3956                         if (pipe_ctx->stream->ctx->dc->enable_c20_dtm_b0 == true) {
3957                                 config.dig_be = link_enc_assign.eng_id;
3958                                 config.dio_output_type = pipe_ctx->stream->link->ep_type;
3959                                 config.dio_output_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A;
3960                         } else {
3961                                 config.dio_output_type = 0;
3962                                 config.dio_output_idx = 0;
3963                         }
3964
3965                         // Add flag to guard B0 implementation
3966                         if (pipe_ctx->stream->ctx->dc->enable_c20_dtm_b0 == true &&
3967                                         link_enc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0) {
3968                                 if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) {
3969                                         link_enc = link_enc_assign.stream->link_enc;
3970
3971                                         // enum ID 1-4 maps to DPIA PHY ID 0-3
3972                                         config.phy_idx = link_enc_assign.ep_id.link_id.enum_id - ENUM_ID_1;
3973                                 } else {  // for non DPIA mode over B0, ABCDE maps to 01564
3974
3975                                         switch (link_enc->transmitter) {
3976                                         case TRANSMITTER_UNIPHY_A:
3977                                                 config.phy_idx = 0;
3978                                                 break;
3979                                         case TRANSMITTER_UNIPHY_B:
3980                                                 config.phy_idx = 1;
3981                                                 break;
3982                                         case TRANSMITTER_UNIPHY_C:
3983                                                 config.phy_idx = 5;
3984                                                 break;
3985                                         case TRANSMITTER_UNIPHY_D:
3986                                                 config.phy_idx = 6;
3987                                                 break;
3988                                         case TRANSMITTER_UNIPHY_E:
3989                                                 config.phy_idx = 4;
3990                                                 break;
3991                                         default:
3992                                                 config.phy_idx = 0;
3993                                                 break;
3994                                         }
3995
3996                                 }
3997                         }
3998                 } else if (pipe_ctx->stream->link->dc->res_pool->funcs->link_encs_assign) {
3999                         link_enc = link_enc_cfg_get_link_enc_used_by_stream(
4000                                         pipe_ctx->stream->ctx->dc,
4001                                         pipe_ctx->stream);
4002                         config.phy_idx = 0; /* Clear phy_idx for non-physical display endpoints. */
4003                 }
4004                 ASSERT(link_enc);
4005                 if (link_enc)
4006                         config.link_enc_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A;
4007                 if (is_dp_128b_132b_signal(pipe_ctx)) {
4008                         config.stream_enc_idx = pipe_ctx->stream_res.hpo_dp_stream_enc->id - ENGINE_ID_HPO_DP_0;
4009                         config.link_enc_idx = pipe_ctx->stream->link->hpo_dp_link_enc->inst;
4010                         config.dp2_enabled = 1;
4011                 }
4012 #endif
4013                 config.dpms_off = dpms_off;
4014                 config.dm_stream_ctx = pipe_ctx->stream->dm_stream_context;
4015                 config.assr_enabled = (panel_mode == DP_PANEL_MODE_EDP);
4016                 config.mst_enabled = (pipe_ctx->stream->signal ==
4017                                 SIGNAL_TYPE_DISPLAY_PORT_MST);
4018                 cp_psp->funcs.update_stream_config(cp_psp->handle, &config);
4019         }
4020 }
4021 #endif
4022
4023 #if defined(CONFIG_DRM_AMD_DC_DCN)
4024 static void fpga_dp_hpo_enable_link_and_stream(struct dc_state *state, struct pipe_ctx *pipe_ctx)
4025 {
4026         struct dc *dc = pipe_ctx->stream->ctx->dc;
4027         struct dc_stream_state *stream = pipe_ctx->stream;
4028         struct link_mst_stream_allocation_table proposed_table = {0};
4029         struct fixed31_32 avg_time_slots_per_mtp;
4030         uint8_t req_slot_count = 0;
4031         uint8_t vc_id = 1; /// VC ID always 1 for SST
4032
4033         struct dc_link_settings link_settings = {0};
4034         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
4035
4036         decide_link_settings(stream, &link_settings);
4037         stream->link->cur_link_settings = link_settings;
4038
4039         /*  Enable clock, Configure lane count, and Enable Link Encoder*/
4040         enable_dp_hpo_output(stream->link, &stream->link->cur_link_settings);
4041
4042 #ifdef DIAGS_BUILD
4043         /* Workaround for FPGA HPO capture DP link data:
4044          * HPO capture will set link to active mode
4045          * This workaround is required to get a capture from start of frame
4046          */
4047         if (!dc->debug.fpga_hpo_capture_en) {
4048                 struct encoder_set_dp_phy_pattern_param params = {0};
4049                 params.dp_phy_pattern = DP_TEST_PATTERN_VIDEO_MODE;
4050
4051                 /* Set link active */
4052                 stream->link->hpo_dp_link_enc->funcs->set_link_test_pattern(
4053                                 stream->link->hpo_dp_link_enc,
4054                                 &params);
4055         }
4056 #endif
4057
4058         /* Enable DP_STREAM_ENC */
4059         dc->hwss.enable_stream(pipe_ctx);
4060
4061         /* Set DPS PPS SDP (AKA "info frames") */
4062         if (pipe_ctx->stream->timing.flags.DSC) {
4063                 dp_set_dsc_pps_sdp(pipe_ctx, true, true);
4064         }
4065
4066         /* Allocate Payload */
4067         if ((stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) && (state->stream_count > 1)) {
4068                 // MST case
4069                 uint8_t i;
4070
4071                 proposed_table.stream_count = state->stream_count;
4072                 for (i = 0; i < state->stream_count; i++) {
4073                         avg_time_slots_per_mtp = calculate_sst_avg_time_slots_per_mtp(state->streams[i], state->streams[i]->link);
4074                         req_slot_count = dc_fixpt_ceil(avg_time_slots_per_mtp);
4075                         proposed_table.stream_allocations[i].slot_count = req_slot_count;
4076                         proposed_table.stream_allocations[i].vcp_id = i+1;
4077                         /* NOTE: This makes assumption that pipe_ctx index is same as stream index */
4078                         proposed_table.stream_allocations[i].hpo_dp_stream_enc = state->res_ctx.pipe_ctx[i].stream_res.hpo_dp_stream_enc;
4079                 }
4080         } else {
4081                 // SST case
4082                 avg_time_slots_per_mtp = calculate_sst_avg_time_slots_per_mtp(stream, stream->link);
4083                 req_slot_count = dc_fixpt_ceil(avg_time_slots_per_mtp);
4084                 proposed_table.stream_count = 1; /// Always 1 stream for SST
4085                 proposed_table.stream_allocations[0].slot_count = req_slot_count;
4086                 proposed_table.stream_allocations[0].vcp_id = vc_id;
4087                 proposed_table.stream_allocations[0].hpo_dp_stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc;
4088         }
4089
4090         stream->link->hpo_dp_link_enc->funcs->update_stream_allocation_table(
4091                         stream->link->hpo_dp_link_enc,
4092                         &proposed_table);
4093
4094         stream->link->hpo_dp_link_enc->funcs->set_throttled_vcp_size(
4095                         stream->link->hpo_dp_link_enc,
4096                         pipe_ctx->stream_res.hpo_dp_stream_enc->inst,
4097                         avg_time_slots_per_mtp);
4098
4099
4100
4101         dc->hwss.unblank_stream(pipe_ctx, &stream->link->cur_link_settings);
4102 }
4103 #endif
4104
4105 void core_link_enable_stream(
4106                 struct dc_state *state,
4107                 struct pipe_ctx *pipe_ctx)
4108 {
4109         struct dc *dc = pipe_ctx->stream->ctx->dc;
4110         struct dc_stream_state *stream = pipe_ctx->stream;
4111         struct dc_link *link = stream->sink->link;
4112         enum dc_status status;
4113         struct link_encoder *link_enc;
4114 #if defined(CONFIG_DRM_AMD_DC_DCN)
4115         enum otg_out_mux_dest otg_out_dest = OUT_MUX_DIO;
4116         struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg;
4117
4118         if (is_dp_128b_132b_signal(pipe_ctx))
4119                 vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg;
4120 #endif
4121         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
4122
4123         if (!IS_DIAG_DC(dc->ctx->dce_environment) &&
4124                         dc_is_virtual_signal(pipe_ctx->stream->signal))
4125                 return;
4126
4127         if (dc->res_pool->funcs->link_encs_assign && stream->link->ep_type != DISPLAY_ENDPOINT_PHY)
4128                 link_enc = link_enc_cfg_get_link_enc_used_by_stream(dc, stream);
4129         else
4130                 link_enc = stream->link->link_enc;
4131         ASSERT(link_enc);
4132
4133 #if defined(CONFIG_DRM_AMD_DC_DCN)
4134         if (!dc_is_virtual_signal(pipe_ctx->stream->signal)
4135                         && !is_dp_128b_132b_signal(pipe_ctx)) {
4136 #else
4137         if (!dc_is_virtual_signal(pipe_ctx->stream->signal)) {
4138 #endif
4139                 if (link_enc)
4140                         link_enc->funcs->setup(
4141                                 link_enc,
4142                                 pipe_ctx->stream->signal);
4143                 pipe_ctx->stream_res.stream_enc->funcs->setup_stereo_sync(
4144                         pipe_ctx->stream_res.stream_enc,
4145                         pipe_ctx->stream_res.tg->inst,
4146                         stream->timing.timing_3d_format != TIMING_3D_FORMAT_NONE);
4147         }
4148
4149 #if defined(CONFIG_DRM_AMD_DC_DCN)
4150         if (is_dp_128b_132b_signal(pipe_ctx)) {
4151                 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->set_stream_attribute(
4152                                 pipe_ctx->stream_res.hpo_dp_stream_enc,
4153                                 &stream->timing,
4154                                 stream->output_color_space,
4155                                 stream->use_vsc_sdp_for_colorimetry,
4156                                 stream->timing.flags.DSC,
4157                                 false);
4158                 otg_out_dest = OUT_MUX_HPO_DP;
4159         } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
4160                 pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute(
4161                                 pipe_ctx->stream_res.stream_enc,
4162                                 &stream->timing,
4163                                 stream->output_color_space,
4164                                 stream->use_vsc_sdp_for_colorimetry,
4165                                 stream->link->dpcd_caps.dprx_feature.bits.SST_SPLIT_SDP_CAP);
4166         }
4167 #else
4168         pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute(
4169                         pipe_ctx->stream_res.stream_enc,
4170                         &stream->timing,
4171                         stream->output_color_space,
4172                         stream->use_vsc_sdp_for_colorimetry,
4173                         stream->link->dpcd_caps.dprx_feature.bits.SST_SPLIT_SDP_CAP);
4174 #endif
4175
4176         if (dc_is_dp_signal(pipe_ctx->stream->signal))
4177                 dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_DP_STREAM_ATTR);
4178
4179         if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal))
4180                 pipe_ctx->stream_res.stream_enc->funcs->hdmi_set_stream_attribute(
4181                         pipe_ctx->stream_res.stream_enc,
4182                         &stream->timing,
4183                         stream->phy_pix_clk,
4184                         pipe_ctx->stream_res.audio != NULL);
4185
4186         pipe_ctx->stream->link->link_state_valid = true;
4187
4188 #if defined(CONFIG_DRM_AMD_DC_DCN)
4189         if (pipe_ctx->stream_res.tg->funcs->set_out_mux)
4190                 pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, otg_out_dest);
4191 #endif
4192
4193         if (dc_is_dvi_signal(pipe_ctx->stream->signal))
4194                 pipe_ctx->stream_res.stream_enc->funcs->dvi_set_stream_attribute(
4195                         pipe_ctx->stream_res.stream_enc,
4196                         &stream->timing,
4197                         (pipe_ctx->stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) ?
4198                         true : false);
4199
4200         if (dc_is_lvds_signal(pipe_ctx->stream->signal))
4201                 pipe_ctx->stream_res.stream_enc->funcs->lvds_set_stream_attribute(
4202                         pipe_ctx->stream_res.stream_enc,
4203                         &stream->timing);
4204
4205         if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
4206                 bool apply_edp_fast_boot_optimization =
4207                         pipe_ctx->stream->apply_edp_fast_boot_optimization;
4208
4209                 pipe_ctx->stream->apply_edp_fast_boot_optimization = false;
4210
4211 #if defined(CONFIG_DRM_AMD_DC_DCN)
4212                 // Enable VPG before building infoframe
4213                 if (vpg && vpg->funcs->vpg_poweron)
4214                         vpg->funcs->vpg_poweron(vpg);
4215 #endif
4216
4217                 resource_build_info_frame(pipe_ctx);
4218                 dc->hwss.update_info_frame(pipe_ctx);
4219
4220                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
4221                         dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME);
4222
4223                 /* Do not touch link on seamless boot optimization. */
4224                 if (pipe_ctx->stream->apply_seamless_boot_optimization) {
4225                         pipe_ctx->stream->dpms_off = false;
4226
4227                         /* Still enable stream features & audio on seamless boot for DP external displays */
4228                         if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT) {
4229                                 enable_stream_features(pipe_ctx);
4230                                 if (pipe_ctx->stream_res.audio != NULL) {
4231                                         pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc);
4232                                         dc->hwss.enable_audio_stream(pipe_ctx);
4233                                 }
4234                         }
4235
4236 #if defined(CONFIG_DRM_AMD_DC_HDCP)
4237                         update_psp_stream_config(pipe_ctx, false);
4238 #endif
4239                         return;
4240                 }
4241
4242                 /* eDP lit up by bios already, no need to enable again. */
4243                 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&
4244                                         apply_edp_fast_boot_optimization &&
4245                                         !pipe_ctx->stream->timing.flags.DSC) {
4246                         pipe_ctx->stream->dpms_off = false;
4247 #if defined(CONFIG_DRM_AMD_DC_HDCP)
4248                         update_psp_stream_config(pipe_ctx, false);
4249 #endif
4250                         return;
4251                 }
4252
4253                 if (pipe_ctx->stream->dpms_off)
4254                         return;
4255
4256                 /* Have to setup DSC before DIG FE and BE are connected (which happens before the
4257                  * link training). This is to make sure the bandwidth sent to DIG BE won't be
4258                  * bigger than what the link and/or DIG BE can handle. VBID[6]/CompressedStream_flag
4259                  * will be automatically set at a later time when the video is enabled
4260                  * (DP_VID_STREAM_EN = 1).
4261                  */
4262                 if (pipe_ctx->stream->timing.flags.DSC) {
4263                         if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
4264                                         dc_is_virtual_signal(pipe_ctx->stream->signal))
4265                                 dp_set_dsc_enable(pipe_ctx, true);
4266                 }
4267
4268                 status = enable_link(state, pipe_ctx);
4269
4270                 if (status != DC_OK) {
4271                         DC_LOG_WARNING("enabling link %u failed: %d\n",
4272                         pipe_ctx->stream->link->link_index,
4273                         status);
4274
4275                         /* Abort stream enable *unless* the failure was due to
4276                          * DP link training - some DP monitors will recover and
4277                          * show the stream anyway. But MST displays can't proceed
4278                          * without link training.
4279                          */
4280                         if (status != DC_FAIL_DP_LINK_TRAINING ||
4281                                         pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
4282                                 BREAK_TO_DEBUGGER();
4283                                 return;
4284                         }
4285                 }
4286
4287                 /* turn off otg test pattern if enable */
4288                 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
4289                         pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
4290                                         CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
4291                                         COLOR_DEPTH_UNDEFINED);
4292
4293                 /* This second call is needed to reconfigure the DIG
4294                  * as a workaround for the incorrect value being applied
4295                  * from transmitter control.
4296                  */
4297 #if defined(CONFIG_DRM_AMD_DC_DCN)
4298                 if (!(dc_is_virtual_signal(pipe_ctx->stream->signal) ||
4299                                 is_dp_128b_132b_signal(pipe_ctx)))
4300 #else
4301                 if (!dc_is_virtual_signal(pipe_ctx->stream->signal))
4302 #endif
4303                         if (link_enc)
4304                                 link_enc->funcs->setup(
4305                                         link_enc,
4306                                         pipe_ctx->stream->signal);
4307
4308                 dc->hwss.enable_stream(pipe_ctx);
4309
4310                 /* Set DPS PPS SDP (AKA "info frames") */
4311                 if (pipe_ctx->stream->timing.flags.DSC) {
4312                         if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
4313                                         dc_is_virtual_signal(pipe_ctx->stream->signal)) {
4314                                 dp_set_dsc_on_rx(pipe_ctx, true);
4315                                 dp_set_dsc_pps_sdp(pipe_ctx, true, true);
4316                         }
4317                 }
4318
4319                 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
4320                         dc_link_allocate_mst_payload(pipe_ctx);
4321 #if defined(CONFIG_DRM_AMD_DC_DCN)
4322                 else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT &&
4323                                 is_dp_128b_132b_signal(pipe_ctx))
4324                         dc_link_update_sst_payload(pipe_ctx, true);
4325 #endif
4326
4327                 dc->hwss.unblank_stream(pipe_ctx,
4328                         &pipe_ctx->stream->link->cur_link_settings);
4329
4330                 if (stream->sink_patches.delay_ignore_msa > 0)
4331                         msleep(stream->sink_patches.delay_ignore_msa);
4332
4333                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
4334                         enable_stream_features(pipe_ctx);
4335 #if defined(CONFIG_DRM_AMD_DC_HDCP)
4336                 update_psp_stream_config(pipe_ctx, false);
4337 #endif
4338
4339                 dc->hwss.enable_audio_stream(pipe_ctx);
4340
4341         } else { // if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
4342 #if defined(CONFIG_DRM_AMD_DC_DCN)
4343                 if (is_dp_128b_132b_signal(pipe_ctx)) {
4344                         fpga_dp_hpo_enable_link_and_stream(state, pipe_ctx);
4345                 }
4346 #endif
4347                 if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
4348                                 dc_is_virtual_signal(pipe_ctx->stream->signal))
4349                         dp_set_dsc_enable(pipe_ctx, true);
4350
4351         }
4352
4353         if (pipe_ctx->stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
4354                 core_link_set_avmute(pipe_ctx, false);
4355         }
4356 }
4357
4358 void core_link_disable_stream(struct pipe_ctx *pipe_ctx)
4359 {
4360         struct dc  *dc = pipe_ctx->stream->ctx->dc;
4361         struct dc_stream_state *stream = pipe_ctx->stream;
4362         struct dc_link *link = stream->sink->link;
4363 #if defined(CONFIG_DRM_AMD_DC_DCN)
4364         struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg;
4365
4366         if (is_dp_128b_132b_signal(pipe_ctx))
4367                 vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg;
4368 #endif
4369
4370         if (!IS_DIAG_DC(dc->ctx->dce_environment) &&
4371                         dc_is_virtual_signal(pipe_ctx->stream->signal))
4372                 return;
4373
4374         if (!pipe_ctx->stream->sink->edid_caps.panel_patch.skip_avmute) {
4375                 if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
4376                         core_link_set_avmute(pipe_ctx, true);
4377         }
4378
4379         dc->hwss.disable_audio_stream(pipe_ctx);
4380
4381 #if defined(CONFIG_DRM_AMD_DC_HDCP)
4382         update_psp_stream_config(pipe_ctx, true);
4383 #endif
4384         dc->hwss.blank_stream(pipe_ctx);
4385
4386         if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
4387                 deallocate_mst_payload(pipe_ctx);
4388 #if defined(CONFIG_DRM_AMD_DC_DCN)
4389         else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT &&
4390                         is_dp_128b_132b_signal(pipe_ctx))
4391                 dc_link_update_sst_payload(pipe_ctx, false);
4392 #endif
4393
4394         if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
4395                 struct ext_hdmi_settings settings = {0};
4396                 enum engine_id eng_id = pipe_ctx->stream_res.stream_enc->id;
4397
4398                 unsigned short masked_chip_caps = link->chip_caps &
4399                                 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
4400                 //Need to inform that sink is going to use legacy HDMI mode.
4401                 dal_ddc_service_write_scdc_data(
4402                         link->ddc,
4403                         165000,//vbios only handles 165Mhz.
4404                         false);
4405                 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {
4406                         /* DP159, Retimer settings */
4407                         if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings))
4408                                 write_i2c_retimer_setting(pipe_ctx,
4409                                                 false, false, &settings);
4410                         else
4411                                 write_i2c_default_retimer_setting(pipe_ctx,
4412                                                 false, false);
4413                 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {
4414                         /* PI3EQX1204, Redriver settings */
4415                         write_i2c_redriver_setting(pipe_ctx, false);
4416                 }
4417         }
4418
4419 #if defined(CONFIG_DRM_AMD_DC_DCN)
4420         if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT &&
4421                         !is_dp_128b_132b_signal(pipe_ctx)) {
4422
4423                 /* In DP1.x SST mode, our encoder will go to TPS1
4424                  * when link is on but stream is off.
4425                  * Disabling link before stream will avoid exposing TPS1 pattern
4426                  * during the disable sequence as it will confuse some receivers
4427                  * state machine.
4428                  * In DP2 or MST mode, our encoder will stay video active
4429                  */
4430                 disable_link(pipe_ctx->stream->link, pipe_ctx->stream->signal);
4431                 dc->hwss.disable_stream(pipe_ctx);
4432         } else {
4433                 dc->hwss.disable_stream(pipe_ctx);
4434                 disable_link(pipe_ctx->stream->link, pipe_ctx->stream->signal);
4435         }
4436 #else
4437         disable_link(pipe_ctx->stream->link, pipe_ctx->stream->signal);
4438
4439         dc->hwss.disable_stream(pipe_ctx);
4440 #endif
4441
4442         if (pipe_ctx->stream->timing.flags.DSC) {
4443                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
4444                         dp_set_dsc_enable(pipe_ctx, false);
4445         }
4446 #if defined(CONFIG_DRM_AMD_DC_DCN)
4447         if (is_dp_128b_132b_signal(pipe_ctx)) {
4448                 if (pipe_ctx->stream_res.tg->funcs->set_out_mux)
4449                         pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, OUT_MUX_DIO);
4450         }
4451 #endif
4452
4453 #if defined(CONFIG_DRM_AMD_DC_DCN)
4454         if (vpg && vpg->funcs->vpg_powerdown)
4455                 vpg->funcs->vpg_powerdown(vpg);
4456 #endif
4457 }
4458
4459 void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
4460 {
4461         struct dc  *dc = pipe_ctx->stream->ctx->dc;
4462
4463         if (!dc_is_hdmi_signal(pipe_ctx->stream->signal))
4464                 return;
4465
4466         dc->hwss.set_avmute(pipe_ctx, enable);
4467 }
4468
4469 /**
4470  *  dc_link_enable_hpd_filter:
4471  *     If enable is true, programs HPD filter on associated HPD line using
4472  *     delay_on_disconnect/delay_on_connect values dependent on
4473  *     link->connector_signal
4474  *
4475  *     If enable is false, programs HPD filter on associated HPD line with no
4476  *     delays on connect or disconnect
4477  *
4478  *  @link:   pointer to the dc link
4479  *  @enable: boolean specifying whether to enable hbd
4480  */
4481 void dc_link_enable_hpd_filter(struct dc_link *link, bool enable)
4482 {
4483         struct gpio *hpd;
4484
4485         if (enable) {
4486                 link->is_hpd_filter_disabled = false;
4487                 program_hpd_filter(link);
4488         } else {
4489                 link->is_hpd_filter_disabled = true;
4490                 /* Obtain HPD handle */
4491                 hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
4492
4493                 if (!hpd)
4494                         return;
4495
4496                 /* Setup HPD filtering */
4497                 if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) {
4498                         struct gpio_hpd_config config;
4499
4500                         config.delay_on_connect = 0;
4501                         config.delay_on_disconnect = 0;
4502
4503                         dal_irq_setup_hpd_filter(hpd, &config);
4504
4505                         dal_gpio_close(hpd);
4506                 } else {
4507                         ASSERT_CRITICAL(false);
4508                 }
4509                 /* Release HPD handle */
4510                 dal_gpio_destroy_irq(&hpd);
4511         }
4512 }
4513
4514 void dc_link_set_drive_settings(struct dc *dc,
4515                                 struct link_training_settings *lt_settings,
4516                                 const struct dc_link *link)
4517 {
4518
4519         int i;
4520
4521         for (i = 0; i < dc->link_count; i++) {
4522                 if (dc->links[i] == link)
4523                         break;
4524         }
4525
4526         if (i >= dc->link_count)
4527                 ASSERT_CRITICAL(false);
4528
4529         dc_link_dp_set_drive_settings(dc->links[i], lt_settings);
4530 }
4531
4532 void dc_link_set_preferred_link_settings(struct dc *dc,
4533                                          struct dc_link_settings *link_setting,
4534                                          struct dc_link *link)
4535 {
4536         int i;
4537         struct pipe_ctx *pipe;
4538         struct dc_stream_state *link_stream;
4539         struct dc_link_settings store_settings = *link_setting;
4540
4541         link->preferred_link_setting = store_settings;
4542
4543         /* Retrain with preferred link settings only relevant for
4544          * DP signal type
4545          * Check for non-DP signal or if passive dongle present
4546          */
4547         if (!dc_is_dp_signal(link->connector_signal) ||
4548                 link->dongle_max_pix_clk > 0)
4549                 return;
4550
4551         for (i = 0; i < MAX_PIPES; i++) {
4552                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
4553                 if (pipe->stream && pipe->stream->link) {
4554                         if (pipe->stream->link == link) {
4555                                 link_stream = pipe->stream;
4556                                 break;
4557                         }
4558                 }
4559         }
4560
4561         /* Stream not found */
4562         if (i == MAX_PIPES)
4563                 return;
4564
4565         /* Cannot retrain link if backend is off */
4566         if (link_stream->dpms_off)
4567                 return;
4568
4569         decide_link_settings(link_stream, &store_settings);
4570
4571         if ((store_settings.lane_count != LANE_COUNT_UNKNOWN) &&
4572                 (store_settings.link_rate != LINK_RATE_UNKNOWN))
4573                 dp_retrain_link_dp_test(link, &store_settings, false);
4574 }
4575
4576 void dc_link_set_preferred_training_settings(struct dc *dc,
4577                                                  struct dc_link_settings *link_setting,
4578                                                  struct dc_link_training_overrides *lt_overrides,
4579                                                  struct dc_link *link,
4580                                                  bool skip_immediate_retrain)
4581 {
4582         if (lt_overrides != NULL)
4583                 link->preferred_training_settings = *lt_overrides;
4584         else
4585                 memset(&link->preferred_training_settings, 0, sizeof(link->preferred_training_settings));
4586
4587         if (link_setting != NULL) {
4588                 link->preferred_link_setting = *link_setting;
4589 #if defined(CONFIG_DRM_AMD_DC_DCN)
4590                 if (dp_get_link_encoding_format(link_setting) ==
4591                                 DP_128b_132b_ENCODING && !link->hpo_dp_link_enc) {
4592                         if (!add_dp_hpo_link_encoder_to_link(link))
4593                                 memset(&link->preferred_link_setting, 0, sizeof(link->preferred_link_setting));
4594                 }
4595 #endif
4596         } else {
4597                 link->preferred_link_setting.lane_count = LANE_COUNT_UNKNOWN;
4598                 link->preferred_link_setting.link_rate = LINK_RATE_UNKNOWN;
4599         }
4600
4601         /* Retrain now, or wait until next stream update to apply */
4602         if (skip_immediate_retrain == false)
4603                 dc_link_set_preferred_link_settings(dc, &link->preferred_link_setting, link);
4604 }
4605
4606 void dc_link_enable_hpd(const struct dc_link *link)
4607 {
4608         dc_link_dp_enable_hpd(link);
4609 }
4610
4611 void dc_link_disable_hpd(const struct dc_link *link)
4612 {
4613         dc_link_dp_disable_hpd(link);
4614 }
4615
4616 void dc_link_set_test_pattern(struct dc_link *link,
4617                               enum dp_test_pattern test_pattern,
4618                               enum dp_test_pattern_color_space test_pattern_color_space,
4619                               const struct link_training_settings *p_link_settings,
4620                               const unsigned char *p_custom_pattern,
4621                               unsigned int cust_pattern_size)
4622 {
4623         if (link != NULL)
4624                 dc_link_dp_set_test_pattern(
4625                         link,
4626                         test_pattern,
4627                         test_pattern_color_space,
4628                         p_link_settings,
4629                         p_custom_pattern,
4630                         cust_pattern_size);
4631 }
4632
4633 uint32_t dc_link_bandwidth_kbps(
4634         const struct dc_link *link,
4635         const struct dc_link_settings *link_setting)
4636 {
4637 #if defined(CONFIG_DRM_AMD_DC_DCN)
4638         uint32_t total_data_bw_efficiency_x10000 = 0;
4639         uint32_t link_rate_per_lane_kbps = 0;
4640
4641         switch (dp_get_link_encoding_format(link_setting)) {
4642         case DP_8b_10b_ENCODING:
4643                 /* For 8b/10b encoding:
4644                  * link rate is defined in the unit of LINK_RATE_REF_FREQ_IN_KHZ per DP byte per lane.
4645                  * data bandwidth efficiency is 80% with additional 3% overhead if FEC is supported.
4646                  */
4647                 link_rate_per_lane_kbps = link_setting->link_rate * LINK_RATE_REF_FREQ_IN_KHZ * BITS_PER_DP_BYTE;
4648                 total_data_bw_efficiency_x10000 = DATA_EFFICIENCY_8b_10b_x10000;
4649                 if (dc_link_should_enable_fec(link)) {
4650                         total_data_bw_efficiency_x10000 /= 100;
4651                         total_data_bw_efficiency_x10000 *= DATA_EFFICIENCY_8b_10b_FEC_EFFICIENCY_x100;
4652                 }
4653                 break;
4654         case DP_128b_132b_ENCODING:
4655                 /* For 128b/132b encoding:
4656                  * link rate is defined in the unit of 10mbps per lane.
4657                  * total data bandwidth efficiency is always 96.71%.
4658                  */
4659                 link_rate_per_lane_kbps = link_setting->link_rate * 10000;
4660                 total_data_bw_efficiency_x10000 = DATA_EFFICIENCY_128b_132b_x10000;
4661                 break;
4662         default:
4663                 break;
4664         }
4665
4666         /* overall effective link bandwidth = link rate per lane * lane count * total data bandwidth efficiency */
4667         return link_rate_per_lane_kbps * link_setting->lane_count / 10000 * total_data_bw_efficiency_x10000;
4668 #else
4669         uint32_t link_bw_kbps =
4670                 link_setting->link_rate * LINK_RATE_REF_FREQ_IN_KHZ; /* bytes per sec */
4671
4672         link_bw_kbps *= 8;   /* 8 bits per byte*/
4673         link_bw_kbps *= link_setting->lane_count;
4674
4675         if (dc_link_should_enable_fec(link)) {
4676                 /* Account for FEC overhead.
4677                  * We have to do it based on caps,
4678                  * and not based on FEC being set ready,
4679                  * because FEC is set ready too late in
4680                  * the process to correctly be picked up
4681                  * by mode enumeration.
4682                  *
4683                  * There's enough zeros at the end of 'kbps'
4684                  * that make the below operation 100% precise
4685                  * for our purposes.
4686                  * 'long long' makes it work even for HDMI 2.1
4687                  * max bandwidth (and much, much bigger bandwidths
4688                  * than that, actually).
4689                  *
4690                  * NOTE: Reducing link BW by 3% may not be precise
4691                  * because it may be a stream BT that increases by 3%, and so
4692                  * 1/1.03 = 0.970873 factor should have been used instead,
4693                  * but the difference is minimal and is in a safe direction,
4694                  * which all works well around potential ambiguity of DP 1.4a spec.
4695                  */
4696                 long long fec_link_bw_kbps = link_bw_kbps * 970LL;
4697                 link_bw_kbps = (uint32_t)(div64_s64(fec_link_bw_kbps, 1000LL));
4698         }
4699         return link_bw_kbps;
4700
4701 #endif
4702 }
4703
4704 const struct dc_link_settings *dc_link_get_link_cap(
4705                 const struct dc_link *link)
4706 {
4707         if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN &&
4708                         link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN)
4709                 return &link->preferred_link_setting;
4710         return &link->verified_link_cap;
4711 }
4712
4713 void dc_link_overwrite_extended_receiver_cap(
4714                 struct dc_link *link)
4715 {
4716         dp_overwrite_extended_receiver_cap(link);
4717 }
4718
4719 bool dc_link_is_fec_supported(const struct dc_link *link)
4720 {
4721         struct link_encoder *link_enc = NULL;
4722
4723         /* Links supporting dynamically assigned link encoder will be assigned next
4724          * available encoder if one not already assigned.
4725          */
4726         if (link->is_dig_mapping_flexible &&
4727                         link->dc->res_pool->funcs->link_encs_assign) {
4728                 link_enc = link_enc_cfg_get_link_enc_used_by_link(link->ctx->dc, link);
4729                 if (link_enc == NULL)
4730                         link_enc = link_enc_cfg_get_next_avail_link_enc(link->ctx->dc);
4731         } else
4732                 link_enc = link->link_enc;
4733         ASSERT(link_enc);
4734
4735         return (dc_is_dp_signal(link->connector_signal) && link_enc &&
4736                         link_enc->features.fec_supported &&
4737                         link->dpcd_caps.fec_cap.bits.FEC_CAPABLE &&
4738                         !IS_FPGA_MAXIMUS_DC(link->ctx->dce_environment));
4739 }
4740
4741 bool dc_link_should_enable_fec(const struct dc_link *link)
4742 {
4743         bool is_fec_disable = false;
4744         bool ret = false;
4745
4746         if ((link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT_MST &&
4747                         link->local_sink &&
4748                         link->local_sink->edid_caps.panel_patch.disable_fec) ||
4749                         (link->connector_signal == SIGNAL_TYPE_EDP
4750                                 ))
4751                 is_fec_disable = true;
4752
4753         if (dc_link_is_fec_supported(link) && !link->dc->debug.disable_fec && !is_fec_disable)
4754                 ret = true;
4755
4756         return ret;
4757 }
4758
4759 uint32_t dc_bandwidth_in_kbps_from_timing(
4760                 const struct dc_crtc_timing *timing)
4761 {
4762         uint32_t bits_per_channel = 0;
4763         uint32_t kbps;
4764
4765 #if defined(CONFIG_DRM_AMD_DC_DCN)
4766         if (timing->flags.DSC)
4767                 return dc_dsc_stream_bandwidth_in_kbps(timing,
4768                                 timing->dsc_cfg.bits_per_pixel,
4769                                 timing->dsc_cfg.num_slices_h,
4770                                 timing->dsc_cfg.is_dp);
4771 #endif
4772
4773         switch (timing->display_color_depth) {
4774         case COLOR_DEPTH_666:
4775                 bits_per_channel = 6;
4776                 break;
4777         case COLOR_DEPTH_888:
4778                 bits_per_channel = 8;
4779                 break;
4780         case COLOR_DEPTH_101010:
4781                 bits_per_channel = 10;
4782                 break;
4783         case COLOR_DEPTH_121212:
4784                 bits_per_channel = 12;
4785                 break;
4786         case COLOR_DEPTH_141414:
4787                 bits_per_channel = 14;
4788                 break;
4789         case COLOR_DEPTH_161616:
4790                 bits_per_channel = 16;
4791                 break;
4792         default:
4793                 ASSERT(bits_per_channel != 0);
4794                 bits_per_channel = 8;
4795                 break;
4796         }
4797
4798         kbps = timing->pix_clk_100hz / 10;
4799         kbps *= bits_per_channel;
4800
4801         if (timing->flags.Y_ONLY != 1) {
4802                 /*Only YOnly make reduce bandwidth by 1/3 compares to RGB*/
4803                 kbps *= 3;
4804                 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
4805                         kbps /= 2;
4806                 else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
4807                         kbps = kbps * 2 / 3;
4808         }
4809
4810         return kbps;
4811
4812 }