drivers/gpu/drm/amd/display/dc/core/dc_link.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <linux/slab.h>
  27
  28 #include "dm_services.h"
  29 #include "atom.h"
  30 #include "dm_helpers.h"
  31 #include "dc.h"
  32 #include "grph_object_id.h"
  33 #include "gpio_service_interface.h"
  34 #include "core_status.h"
  35 #include "dc_link_dp.h"
  36 #include "dc_link_ddc.h"
  37 #include "link_hwss.h"
  38 #include "opp.h"
  39
  40 #include "link_encoder.h"
  41 #include "hw_sequencer.h"
  42 #include "resource.h"
  43 #include "abm.h"
  44 #include "fixed31_32.h"
  45 #include "dpcd_defs.h"
  46 #include "dmcu.h"
  47 #include "hw/clk_mgr.h"
  48 #include "dce/dmub_psr.h"
  49
  50 #define DC_LOGGER_INIT(logger)
  51
  52
  53 #define LINK_INFO(...) \
  54         DC_LOG_HW_HOTPLUG(  \
  55                 __VA_ARGS__)
  56
  57 #define RETIMER_REDRIVER_INFO(...) \
  58         DC_LOG_RETIMER_REDRIVER(  \
  59                 __VA_ARGS__)
  60 /*******************************************************************************
  61  * Private structures
  62  ******************************************************************************/
  63
  64 enum {
  65         PEAK_FACTOR_X1000 = 1006,
  66         /*
  67         * Some receivers fail to train on first try and are good
  68         * on subsequent tries. 2 retries should be plenty. If we
  69         * don't have a successful training then we don't expect to
  70         * ever get one.
  71         */
  72         LINK_TRAINING_MAX_VERIFY_RETRY = 2
  73 };
  74
  75 /*******************************************************************************
  76  * Private functions
  77  ******************************************************************************/
  78 static void dc_link_destruct(struct dc_link *link)
  79 {
  80         int i;
  81
  82         if (link->hpd_gpio != NULL) {
  83                 dal_gpio_destroy_irq(&link->hpd_gpio);
  84                 link->hpd_gpio = NULL;
  85         }
  86
  87         if (link->ddc)
  88                 dal_ddc_service_destroy(&link->ddc);
  89
  90         if(link->link_enc)
  91                 link->link_enc->funcs->destroy(&link->link_enc);
  92
  93         if (link->local_sink)
  94                 dc_sink_release(link->local_sink);
  95
  96         for (i = 0; i < link->sink_count; ++i)
  97                 dc_sink_release(link->remote_sinks[i]);
  98 }
  99
 100 struct gpio *get_hpd_gpio(struct dc_bios *dcb,
 101                 struct graphics_object_id link_id,
 102                 struct gpio_service *gpio_service)
 103 {
 104         enum bp_result bp_result;
 105         struct graphics_object_hpd_info hpd_info;
 106         struct gpio_pin_info pin_info;
 107
 108         if (dcb->funcs->get_hpd_info(dcb, link_id, &hpd_info) != BP_RESULT_OK)
 109                 return NULL;
 110
 111         bp_result = dcb->funcs->get_gpio_pin_info(dcb,
 112                 hpd_info.hpd_int_gpio_uid, &pin_info);
 113
 114         if (bp_result != BP_RESULT_OK) {
 115                 ASSERT(bp_result == BP_RESULT_NORECORD);
 116                 return NULL;
 117         }
 118
 119         return dal_gpio_service_create_irq(
 120                 gpio_service,
 121                 pin_info.offset,
 122                 pin_info.mask);
 123 }
 124
 125 /*
 126  *  Function: program_hpd_filter
 127  *
 128  *  @brief
 129  *     Programs HPD filter on associated HPD line
 130  *
 131  *  @param [in] delay_on_connect_in_ms: Connect filter timeout
 132  *  @param [in] delay_on_disconnect_in_ms: Disconnect filter timeout
 133  *
 134  *  @return
 135  *     true on success, false otherwise
 136  */
 137 static bool program_hpd_filter(
 138         const struct dc_link *link)
 139 {
 140         bool result = false;
 141
 142         struct gpio *hpd;
 143
 144         int delay_on_connect_in_ms = 0;
 145         int delay_on_disconnect_in_ms = 0;
 146
 147         if (link->is_hpd_filter_disabled)
 148                 return false;
 149         /* Verify feature is supported */
 150         switch (link->connector_signal) {
 151         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 152         case SIGNAL_TYPE_DVI_DUAL_LINK:
 153         case SIGNAL_TYPE_HDMI_TYPE_A:
 154                 /* Program hpd filter */
 155                 delay_on_connect_in_ms = 500;
 156                 delay_on_disconnect_in_ms = 100;
 157                 break;
 158         case SIGNAL_TYPE_DISPLAY_PORT:
 159         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 160                 /* Program hpd filter to allow DP signal to settle */
 161                 /* 500: not able to detect MST <-> SST switch as HPD is low for
 162                  *      only 100ms on DELL U2413
 163                  * 0:   some passive dongle still show aux mode instead of i2c
 164                  * 20-50:not enough to hide bouncing HPD with passive dongle.
 165                  *      also see intermittent i2c read issues.
 166                  */
 167                 delay_on_connect_in_ms = 80;
 168                 delay_on_disconnect_in_ms = 0;
 169                 break;
 170         case SIGNAL_TYPE_LVDS:
 171         case SIGNAL_TYPE_EDP:
 172         default:
 173                 /* Don't program hpd filter */
 174                 return false;
 175         }
 176
 177         /* Obtain HPD handle */
 178         hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
 179
 180         if (!hpd)
 181                 return result;
 182
 183         /* Setup HPD filtering */
 184         if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) {
 185                 struct gpio_hpd_config config;
 186
 187                 config.delay_on_connect = delay_on_connect_in_ms;
 188                 config.delay_on_disconnect = delay_on_disconnect_in_ms;
 189
 190                 dal_irq_setup_hpd_filter(hpd, &config);
 191
 192                 dal_gpio_close(hpd);
 193
 194                 result = true;
 195         } else {
 196                 ASSERT_CRITICAL(false);
 197         }
 198
 199         /* Release HPD handle */
 200         dal_gpio_destroy_irq(&hpd);
 201
 202         return result;
 203 }
 204
 205 /**
 206  * dc_link_detect_sink() - Determine if there is a sink connected
 207  *
 208  * @type: Returned connection type
 209  * Does not detect downstream devices, such as MST sinks
 210  * or display connected through active dongles
 211  */
 212 bool dc_link_detect_sink(struct dc_link *link, enum dc_connection_type *type)
 213 {
 214         uint32_t is_hpd_high = 0;
 215         struct gpio *hpd_pin;
 216
 217         if (link->connector_signal == SIGNAL_TYPE_LVDS) {
 218                 *type = dc_connection_single;
 219                 return true;
 220         }
 221
 222         if (link->connector_signal == SIGNAL_TYPE_EDP) {
 223                 /*in case it is not on*/
 224                 link->dc->hwss.edp_power_control(link, true);
 225                 link->dc->hwss.edp_wait_for_hpd_ready(link, true);
 226         }
 227
 228         /* todo: may need to lock gpio access */
 229         hpd_pin = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
 230         if (hpd_pin == NULL)
 231                 goto hpd_gpio_failure;
 232
 233         dal_gpio_open(hpd_pin, GPIO_MODE_INTERRUPT);
 234         dal_gpio_get_value(hpd_pin, &is_hpd_high);
 235         dal_gpio_close(hpd_pin);
 236         dal_gpio_destroy_irq(&hpd_pin);
 237
 238         if (is_hpd_high) {
 239                 *type = dc_connection_single;
 240                 /* TODO: need to do the actual detection */
 241         } else {
 242                 *type = dc_connection_none;
 243         }
 244
 245         return true;
 246
 247 hpd_gpio_failure:
 248         return false;
 249 }
 250
 251 static enum ddc_transaction_type get_ddc_transaction_type(
 252                 enum signal_type sink_signal)
 253 {
 254         enum ddc_transaction_type transaction_type = DDC_TRANSACTION_TYPE_NONE;
 255
 256         switch (sink_signal) {
 257         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 258         case SIGNAL_TYPE_DVI_DUAL_LINK:
 259         case SIGNAL_TYPE_HDMI_TYPE_A:
 260         case SIGNAL_TYPE_LVDS:
 261         case SIGNAL_TYPE_RGB:
 262                 transaction_type = DDC_TRANSACTION_TYPE_I2C;
 263                 break;
 264
 265         case SIGNAL_TYPE_DISPLAY_PORT:
 266         case SIGNAL_TYPE_EDP:
 267                 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 268                 break;
 269
 270         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 271                 /* MST does not use I2COverAux, but there is the
 272                  * SPECIAL use case for "immediate dwnstrm device
 273                  * access" (EPR#370830). */
 274                 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 275                 break;
 276
 277         default:
 278                 break;
 279         }
 280
 281         return transaction_type;
 282 }
 283
 284 static enum signal_type get_basic_signal_type(
 285         struct graphics_object_id encoder,
 286         struct graphics_object_id downstream)
 287 {
 288         if (downstream.type == OBJECT_TYPE_CONNECTOR) {
 289                 switch (downstream.id) {
 290                 case CONNECTOR_ID_SINGLE_LINK_DVII:
 291                         switch (encoder.id) {
 292                         case ENCODER_ID_INTERNAL_DAC1:
 293                         case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
 294                         case ENCODER_ID_INTERNAL_DAC2:
 295                         case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
 296                                 return SIGNAL_TYPE_RGB;
 297                         default:
 298                                 return SIGNAL_TYPE_DVI_SINGLE_LINK;
 299                         }
 300                 break;
 301                 case CONNECTOR_ID_DUAL_LINK_DVII:
 302                 {
 303                         switch (encoder.id) {
 304                         case ENCODER_ID_INTERNAL_DAC1:
 305                         case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
 306                         case ENCODER_ID_INTERNAL_DAC2:
 307                         case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
 308                                 return SIGNAL_TYPE_RGB;
 309                         default:
 310                                 return SIGNAL_TYPE_DVI_DUAL_LINK;
 311                         }
 312                 }
 313                 break;
 314                 case CONNECTOR_ID_SINGLE_LINK_DVID:
 315                         return SIGNAL_TYPE_DVI_SINGLE_LINK;
 316                 case CONNECTOR_ID_DUAL_LINK_DVID:
 317                         return SIGNAL_TYPE_DVI_DUAL_LINK;
 318                 case CONNECTOR_ID_VGA:
 319                         return SIGNAL_TYPE_RGB;
 320                 case CONNECTOR_ID_HDMI_TYPE_A:
 321                         return SIGNAL_TYPE_HDMI_TYPE_A;
 322                 case CONNECTOR_ID_LVDS:
 323                         return SIGNAL_TYPE_LVDS;
 324                 case CONNECTOR_ID_DISPLAY_PORT:
 325                         return SIGNAL_TYPE_DISPLAY_PORT;
 326                 case CONNECTOR_ID_EDP:
 327                         return SIGNAL_TYPE_EDP;
 328                 default:
 329                         return SIGNAL_TYPE_NONE;
 330                 }
 331         } else if (downstream.type == OBJECT_TYPE_ENCODER) {
 332                 switch (downstream.id) {
 333                 case ENCODER_ID_EXTERNAL_NUTMEG:
 334                 case ENCODER_ID_EXTERNAL_TRAVIS:
 335                         return SIGNAL_TYPE_DISPLAY_PORT;
 336                 default:
 337                         return SIGNAL_TYPE_NONE;
 338                 }
 339         }
 340
 341         return SIGNAL_TYPE_NONE;
 342 }
 343
 344 /**
 345  * dc_link_is_dp_sink_present() - Check if there is a native DP
 346  * or passive DP-HDMI dongle connected
 347  */
 348 bool dc_link_is_dp_sink_present(struct dc_link *link)
 349 {
 350         enum gpio_result gpio_result;
 351         uint32_t clock_pin = 0;
 352         uint8_t retry = 0;
 353         struct ddc *ddc;
 354
 355         enum connector_id connector_id =
 356                 dal_graphics_object_id_get_connector_id(link->link_id);
 357
 358         bool present =
 359                 ((connector_id == CONNECTOR_ID_DISPLAY_PORT) ||
 360                 (connector_id == CONNECTOR_ID_EDP));
 361
 362         ddc = dal_ddc_service_get_ddc_pin(link->ddc);
 363
 364         if (!ddc) {
 365                 BREAK_TO_DEBUGGER();
 366                 return present;
 367         }
 368
 369         /* Open GPIO and set it to I2C mode */
 370         /* Note: this GpioMode_Input will be converted
 371          * to GpioConfigType_I2cAuxDualMode in GPIO component,
 372          * which indicates we need additional delay */
 373
 374         if (GPIO_RESULT_OK != dal_ddc_open(
 375                 ddc, GPIO_MODE_INPUT, GPIO_DDC_CONFIG_TYPE_MODE_I2C)) {
 376                 dal_ddc_close(ddc);
 377
 378                 return present;
 379         }
 380
 381         /*
 382          * Read GPIO: DP sink is present if both clock and data pins are zero
 383          *
 384          * [W/A] plug-unplug DP cable, sometimes customer board has
 385          * one short pulse on clk_pin(1V, < 1ms). DP will be config to HDMI/DVI
 386          * then monitor can't br light up. Add retry 3 times
 387          * But in real passive dongle, it need additional 3ms to detect
 388          */
 389         do {
 390                 gpio_result = dal_gpio_get_value(ddc->pin_clock, &clock_pin);
 391                 ASSERT(gpio_result == GPIO_RESULT_OK);
 392                 if (clock_pin)
 393                         udelay(1000);
 394                 else
 395                         break;
 396         } while (retry++ < 3);
 397
 398         present = (gpio_result == GPIO_RESULT_OK) && !clock_pin;
 399
 400         dal_ddc_close(ddc);
 401
 402         return present;
 403 }
 404
 405 /*
 406  * @brief
 407  * Detect output sink type
 408  */
 409 static enum signal_type link_detect_sink(
 410         struct dc_link *link,
 411         enum dc_detect_reason reason)
 412 {
 413         enum signal_type result = get_basic_signal_type(
 414                 link->link_enc->id, link->link_id);
 415
 416         /* Internal digital encoder will detect only dongles
 417          * that require digital signal */
 418
 419         /* Detection mechanism is different
 420          * for different native connectors.
 421          * LVDS connector supports only LVDS signal;
 422          * PCIE is a bus slot, the actual connector needs to be detected first;
 423          * eDP connector supports only eDP signal;
 424          * HDMI should check straps for audio */
 425
 426         /* PCIE detects the actual connector on add-on board */
 427
 428         if (link->link_id.id == CONNECTOR_ID_PCIE) {
 429                 /* ZAZTODO implement PCIE add-on card detection */
 430         }
 431
 432         switch (link->link_id.id) {
 433         case CONNECTOR_ID_HDMI_TYPE_A: {
 434                 /* check audio support:
 435                  * if native HDMI is not supported, switch to DVI */
 436                 struct audio_support *aud_support = &link->dc->res_pool->audio_support;
 437
 438                 if (!aud_support->hdmi_audio_native)
 439                         if (link->link_id.id == CONNECTOR_ID_HDMI_TYPE_A)
 440                                 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
 441         }
 442         break;
 443         case CONNECTOR_ID_DISPLAY_PORT: {
 444                 /* DP HPD short pulse. Passive DP dongle will not
 445                  * have short pulse
 446                  */
 447                 if (reason != DETECT_REASON_HPDRX) {
 448                         /* Check whether DP signal detected: if not -
 449                          * we assume signal is DVI; it could be corrected
 450                          * to HDMI after dongle detection
 451                          */
 452                         if (!dm_helpers_is_dp_sink_present(link))
 453                                 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
 454                 }
 455         }
 456         break;
 457         default:
 458         break;
 459         }
 460
 461         return result;
 462 }
 463
 464 static enum signal_type decide_signal_from_strap_and_dongle_type(
 465                 enum display_dongle_type dongle_type,
 466                 struct audio_support *audio_support)
 467 {
 468         enum signal_type signal = SIGNAL_TYPE_NONE;
 469
 470         switch (dongle_type) {
 471         case DISPLAY_DONGLE_DP_HDMI_DONGLE:
 472                 if (audio_support->hdmi_audio_on_dongle)
 473                         signal =  SIGNAL_TYPE_HDMI_TYPE_A;
 474                 else
 475                         signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 476                 break;
 477         case DISPLAY_DONGLE_DP_DVI_DONGLE:
 478                 signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 479                 break;
 480         case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
 481                 if (audio_support->hdmi_audio_native)
 482                         signal =  SIGNAL_TYPE_HDMI_TYPE_A;
 483                 else
 484                         signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 485                 break;
 486         default:
 487                 signal = SIGNAL_TYPE_NONE;
 488                 break;
 489         }
 490
 491         return signal;
 492 }
 493
 494 static enum signal_type dp_passive_dongle_detection(
 495                 struct ddc_service *ddc,
 496                 struct display_sink_capability *sink_cap,
 497                 struct audio_support *audio_support)
 498 {
 499         dal_ddc_service_i2c_query_dp_dual_mode_adaptor(
 500                                                 ddc, sink_cap);
 501         return decide_signal_from_strap_and_dongle_type(
 502                         sink_cap->dongle_type,
 503                         audio_support);
 504 }
 505
 506 static void link_disconnect_sink(struct dc_link *link)
 507 {
 508         if (link->local_sink) {
 509                 dc_sink_release(link->local_sink);
 510                 link->local_sink = NULL;
 511         }
 512
 513         link->dpcd_sink_count = 0;
 514 }
 515
 516 static void link_disconnect_remap(struct dc_sink *prev_sink, struct dc_link *link)
 517 {
 518         dc_sink_release(link->local_sink);
 519         link->local_sink = prev_sink;
 520 }
 521
 522
 523 static void read_current_link_settings_on_detect(struct dc_link *link)
 524 {
 525         union lane_count_set lane_count_set = { {0} };
 526         uint8_t link_bw_set;
 527         uint8_t link_rate_set;
 528         uint32_t read_dpcd_retry_cnt = 10;
 529         enum dc_status status = DC_ERROR_UNEXPECTED;
 530         int i;
 531         union max_down_spread max_down_spread = { {0} };
 532
 533         // Read DPCD 00101h to find out the number of lanes currently set
 534         for (i = 0; i < read_dpcd_retry_cnt; i++) {
 535                 status = core_link_read_dpcd(
 536                                 link,
 537                                 DP_LANE_COUNT_SET,
 538                                 &lane_count_set.raw,
 539                                 sizeof(lane_count_set));
 540                 /* First DPCD read after VDD ON can fail if the particular board
 541                  * does not have HPD pin wired correctly. So if DPCD read fails,
 542                  * which it should never happen, retry a few times. Target worst
 543                  * case scenario of 80 ms.
 544                  */
 545                 if (status == DC_OK) {
 546                         link->cur_link_settings.lane_count = lane_count_set.bits.LANE_COUNT_SET;
 547                         break;
 548                 }
 549
 550                 msleep(8);
 551         }
 552
 553         // Read DPCD 00100h to find if standard link rates are set
 554         core_link_read_dpcd(link, DP_LINK_BW_SET,
 555                         &link_bw_set, sizeof(link_bw_set));
 556
 557         if (link_bw_set == 0) {
 558                 if (link->connector_signal == SIGNAL_TYPE_EDP) {
 559                         /* If standard link rates are not being used,
 560                          * Read DPCD 00115h to find the edp link rate set used
 561                          */
 562                         core_link_read_dpcd(link, DP_LINK_RATE_SET,
 563                                         &link_rate_set, sizeof(link_rate_set));
 564
 565                         // edp_supported_link_rates_count = 0 for DP
 566                         if (link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) {
 567                                 link->cur_link_settings.link_rate =
 568                                                 link->dpcd_caps.edp_supported_link_rates[link_rate_set];
 569                                 link->cur_link_settings.link_rate_set = link_rate_set;
 570                                 link->cur_link_settings.use_link_rate_set = true;
 571                         }
 572                 } else {
 573                         // Link Rate not found. Seamless boot may not work.
 574                         ASSERT(false);
 575                 }
 576         } else {
 577                 link->cur_link_settings.link_rate = link_bw_set;
 578                 link->cur_link_settings.use_link_rate_set = false;
 579         }
 580         // Read DPCD 00003h to find the max down spread.
 581         core_link_read_dpcd(link, DP_MAX_DOWNSPREAD,
 582                         &max_down_spread.raw, sizeof(max_down_spread));
 583         link->cur_link_settings.link_spread =
 584                 max_down_spread.bits.MAX_DOWN_SPREAD ?
 585                 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
 586 }
 587
 588 static bool detect_dp(struct dc_link *link,
 589                       struct display_sink_capability *sink_caps,
 590                       bool *converter_disable_audio,
 591                       struct audio_support *audio_support,
 592                       enum dc_detect_reason reason)
 593 {
 594         bool boot = false;
 595
 596         sink_caps->signal = link_detect_sink(link, reason);
 597         sink_caps->transaction_type =
 598                 get_ddc_transaction_type(sink_caps->signal);
 599
 600         if (sink_caps->transaction_type == DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
 601                 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
 602
 603                 dpcd_set_source_specific_data(link);
 604
 605                 if (!detect_dp_sink_caps(link))
 606                         return false;
 607
 608                 if (is_mst_supported(link)) {
 609                         sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
 610                         link->type = dc_connection_mst_branch;
 611
 612                         dal_ddc_service_set_transaction_type(link->ddc,
 613                                                              sink_caps->transaction_type);
 614
 615                         /*
 616                          * This call will initiate MST topology discovery. Which
 617                          * will detect MST ports and add new DRM connector DRM
 618                          * framework. Then read EDID via remote i2c over aux. In
 619                          * the end, will notify DRM detect result and save EDID
 620                          * into DRM framework.
 621                          *
 622                          * .detect is called by .fill_modes.
 623                          * .fill_modes is called by user mode ioctl
 624                          * DRM_IOCTL_MODE_GETCONNECTOR.
 625                          *
 626                          * .get_modes is called by .fill_modes.
 627                          *
 628                          * call .get_modes, AMDGPU DM implementation will create
 629                          * new dc_sink and add to dc_link. For long HPD plug
 630                          * in/out, MST has its own handle.
 631                          *
 632                          * Therefore, just after dc_create, link->sink is not
 633                          * created for MST until user mode app calls
 634                          * DRM_IOCTL_MODE_GETCONNECTOR.
 635                          *
 636                          * Need check ->sink usages in case ->sink = NULL
 637                          * TODO: s3 resume check
 638                          */
 639                         if (reason == DETECT_REASON_BOOT)
 640                                 boot = true;
 641
 642                         dm_helpers_dp_update_branch_info(link->ctx, link);
 643
 644                         if (!dm_helpers_dp_mst_start_top_mgr(link->ctx,
 645                                                              link, boot)) {
 646                                 /* MST not supported */
 647                                 link->type = dc_connection_single;
 648                                 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
 649                         }
 650                 }
 651
 652                 if (link->type != dc_connection_mst_branch &&
 653                     is_dp_active_dongle(link)) {
 654                         /* DP active dongles */
 655                         link->type = dc_connection_active_dongle;
 656                         if (!link->dpcd_caps.sink_count.bits.SINK_COUNT) {
 657                                 /*
 658                                  * active dongle unplug processing for short irq
 659                                  */
 660                                 link_disconnect_sink(link);
 661                                 return true;
 662                         }
 663
 664                         if (link->dpcd_caps.dongle_type !=
 665                             DISPLAY_DONGLE_DP_HDMI_CONVERTER)
 666                                 *converter_disable_audio = true;
 667                 }
 668         } else {
 669                 /* DP passive dongles */
 670                 sink_caps->signal = dp_passive_dongle_detection(link->ddc,
 671                                                                 sink_caps,
 672                                                                 audio_support);
 673         }
 674
 675         return true;
 676 }
 677
 678 static bool is_same_edid(struct dc_edid *old_edid, struct dc_edid *new_edid)
 679 {
 680         if (old_edid->length != new_edid->length)
 681                 return false;
 682
 683         if (new_edid->length == 0)
 684                 return false;
 685
 686         return (memcmp(old_edid->raw_edid, new_edid->raw_edid, new_edid->length) == 0);
 687 }
 688
 689 static bool wait_for_alt_mode(struct dc_link *link)
 690 {
 691
 692         /**
 693          * something is terribly wrong if time out is > 200ms. (5Hz)
 694          * 500 microseconds * 400 tries us 200 ms
 695          **/
 696         unsigned int sleep_time_in_microseconds = 500;
 697         unsigned int tries_allowed = 400;
 698         bool is_in_alt_mode;
 699         unsigned long long enter_timestamp;
 700         unsigned long long finish_timestamp;
 701         unsigned long long time_taken_in_ns;
 702         int tries_taken;
 703
 704         DC_LOGGER_INIT(link->ctx->logger);
 705
 706         if (link->link_enc->funcs->is_in_alt_mode == NULL)
 707                 return true;
 708
 709         is_in_alt_mode = link->link_enc->funcs->is_in_alt_mode(link->link_enc);
 710         DC_LOG_WARNING("DP Alt mode state on HPD: %d\n", is_in_alt_mode);
 711
 712         if (is_in_alt_mode)
 713                 return true;
 714
 715         enter_timestamp = dm_get_timestamp(link->ctx);
 716
 717         for (tries_taken = 0; tries_taken < tries_allowed; tries_taken++) {
 718                 udelay(sleep_time_in_microseconds);
 719                 /* ask the link if alt mode is enabled, if so return ok */
 720                 if (link->link_enc->funcs->is_in_alt_mode(link->link_enc)) {
 721
 722                         finish_timestamp = dm_get_timestamp(link->ctx);
 723                         time_taken_in_ns = dm_get_elapse_time_in_ns(
 724                                 link->ctx, finish_timestamp, enter_timestamp);
 725                         DC_LOG_WARNING("Alt mode entered finished after %llu ms\n",
 726                                        div_u64(time_taken_in_ns, 1000000));
 727                         return true;
 728                 }
 729
 730         }
 731         finish_timestamp = dm_get_timestamp(link->ctx);
 732         time_taken_in_ns = dm_get_elapse_time_in_ns(link->ctx, finish_timestamp,
 733                                                     enter_timestamp);
 734         DC_LOG_WARNING("Alt mode has timed out after %llu ms\n",
 735                         div_u64(time_taken_in_ns, 1000000));
 736         return false;
 737 }
 738
 739 /**
 740  * dc_link_detect() - Detect if a sink is attached to a given link
 741  *
 742  * link->local_sink is created or destroyed as needed.
 743  *
 744  * This does not create remote sinks but will trigger DM
 745  * to start MST detection if a branch is detected.
 746  */
 747 static bool dc_link_detect_helper(struct dc_link *link,
 748                                   enum dc_detect_reason reason)
 749 {
 750         struct dc_sink_init_data sink_init_data = { 0 };
 751         struct display_sink_capability sink_caps = { 0 };
 752         uint8_t i;
 753         bool converter_disable_audio = false;
 754         struct audio_support *aud_support = &link->dc->res_pool->audio_support;
 755         bool same_edid = false;
 756         enum dc_edid_status edid_status;
 757         struct dc_context *dc_ctx = link->ctx;
 758         struct dc_sink *sink = NULL;
 759         struct dc_sink *prev_sink = NULL;
 760         struct dpcd_caps prev_dpcd_caps;
 761         bool same_dpcd = true;
 762         enum dc_connection_type new_connection_type = dc_connection_none;
 763         bool perform_dp_seamless_boot = false;
 764
 765         DC_LOGGER_INIT(link->ctx->logger);
 766
 767         if (dc_is_virtual_signal(link->connector_signal))
 768                 return false;
 769
 770         if ((link->connector_signal == SIGNAL_TYPE_LVDS ||
 771                         link->connector_signal == SIGNAL_TYPE_EDP) &&
 772                         link->local_sink) {
 773
 774                 // need to re-write OUI and brightness in resume case
 775                 if (link->connector_signal == SIGNAL_TYPE_EDP) {
 776                         dpcd_set_source_specific_data(link);
 777                         dc_link_set_default_brightness_aux(link); //TODO: use cached
 778                 }
 779
 780                 return true;
 781         }
 782
 783         if (false == dc_link_detect_sink(link, &new_connection_type)) {
 784                 BREAK_TO_DEBUGGER();
 785                 return false;
 786         }
 787
 788         prev_sink = link->local_sink;
 789         if (prev_sink != NULL) {
 790                 dc_sink_retain(prev_sink);
 791                 memcpy(&prev_dpcd_caps, &link->dpcd_caps, sizeof(struct dpcd_caps));
 792         }
 793         link_disconnect_sink(link);
 794
 795         if (new_connection_type != dc_connection_none) {
 796                 link->type = new_connection_type;
 797                 link->link_state_valid = false;
 798
 799                 /* From Disconnected-to-Connected. */
 800                 switch (link->connector_signal) {
 801                 case SIGNAL_TYPE_HDMI_TYPE_A: {
 802                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 803                         if (aud_support->hdmi_audio_native)
 804                                 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
 805                         else
 806                                 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 807                         break;
 808                 }
 809
 810                 case SIGNAL_TYPE_DVI_SINGLE_LINK: {
 811                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 812                         sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 813                         break;
 814                 }
 815
 816                 case SIGNAL_TYPE_DVI_DUAL_LINK: {
 817                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 818                         sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
 819                         break;
 820                 }
 821
 822                 case SIGNAL_TYPE_LVDS: {
 823                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 824                         sink_caps.signal = SIGNAL_TYPE_LVDS;
 825                         break;
 826                 }
 827
 828                 case SIGNAL_TYPE_EDP: {
 829                         read_current_link_settings_on_detect(link);
 830
 831                         dpcd_set_source_specific_data(link);
 832
 833                         detect_edp_sink_caps(link);
 834                         read_current_link_settings_on_detect(link);
 835                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 836                         sink_caps.signal = SIGNAL_TYPE_EDP;
 837                         break;
 838                 }
 839
 840                 case SIGNAL_TYPE_DISPLAY_PORT: {
 841
 842                         /* wa HPD high coming too early*/
 843                         if (link->link_enc->features.flags.bits.DP_IS_USB_C == 1) {
 844
 845                                 /* if alt mode times out, return false */
 846                                 if (wait_for_alt_mode(link) == false) {
 847                                         return false;
 848                                 }
 849                         }
 850
 851                         if (!detect_dp(
 852                                 link,
 853                                 &sink_caps,
 854                                 &converter_disable_audio,
 855                                 aud_support, reason)) {
 856                                 if (prev_sink != NULL)
 857                                         dc_sink_release(prev_sink);
 858                                 return false;
 859                         }
 860
 861                         // Check if dpcp block is the same
 862                         if (prev_sink != NULL) {
 863                                 if (memcmp(&link->dpcd_caps, &prev_dpcd_caps, sizeof(struct dpcd_caps)))
 864                                         same_dpcd = false;
 865                         }
 866                         /* Active dongle downstream unplug*/
 867                         if (link->type == dc_connection_active_dongle &&
 868                                 link->dpcd_caps.sink_count.bits.SINK_COUNT == 0) {
 869                                 if (prev_sink != NULL)
 870                                         /* Downstream unplug */
 871                                         dc_sink_release(prev_sink);
 872                                 return true;
 873                         }
 874
 875                         if (link->type == dc_connection_mst_branch) {
 876                                 LINK_INFO("link=%d, mst branch is now Connected\n",
 877                                         link->link_index);
 878                                 /* Need to setup mst link_cap struct here
 879                                  * otherwise dc_link_detect() will leave mst link_cap
 880                                  * empty which leads to allocate_mst_payload() has "0"
 881                                  * pbn_per_slot value leading to exception on dc_fixpt_div()
 882                                  */
 883                                 dp_verify_mst_link_cap(link);
 884
 885                                 if (prev_sink != NULL)
 886                                         dc_sink_release(prev_sink);
 887                                 return false;
 888                         }
 889
 890                         // For seamless boot, to skip verify link cap, we read UEFI settings and set them as verified.
 891                         if (reason == DETECT_REASON_BOOT &&
 892                                         dc_ctx->dc->config.power_down_display_on_boot == false &&
 893                                         link->link_status.link_active == true)
 894                                 perform_dp_seamless_boot = true;
 895
 896                         if (perform_dp_seamless_boot) {
 897                                 read_current_link_settings_on_detect(link);
 898                                 link->verified_link_cap = link->reported_link_cap;
 899                         }
 900
 901                         break;
 902                 }
 903
 904                 default:
 905                         DC_ERROR("Invalid connector type! signal:%d\n",
 906                                 link->connector_signal);
 907                         if (prev_sink != NULL)
 908                                 dc_sink_release(prev_sink);
 909                         return false;
 910                 } /* switch() */
 911
 912                 if (link->dpcd_caps.sink_count.bits.SINK_COUNT)
 913                         link->dpcd_sink_count = link->dpcd_caps.sink_count.
 914                                         bits.SINK_COUNT;
 915                 else
 916                         link->dpcd_sink_count = 1;
 917
 918                 dal_ddc_service_set_transaction_type(
 919                                                 link->ddc,
 920                                                 sink_caps.transaction_type);
 921
 922                 link->aux_mode = dal_ddc_service_is_in_aux_transaction_mode(
 923                                 link->ddc);
 924
 925                 sink_init_data.link = link;
 926                 sink_init_data.sink_signal = sink_caps.signal;
 927
 928                 sink = dc_sink_create(&sink_init_data);
 929                 if (!sink) {
 930                         DC_ERROR("Failed to create sink!\n");
 931                         if (prev_sink != NULL)
 932                                 dc_sink_release(prev_sink);
 933                         return false;
 934                 }
 935
 936                 sink->link->dongle_max_pix_clk = sink_caps.max_hdmi_pixel_clock;
 937                 sink->converter_disable_audio = converter_disable_audio;
 938
 939                 /* dc_sink_create returns a new reference */
 940                 link->local_sink = sink;
 941
 942                 edid_status = dm_helpers_read_local_edid(
 943                                 link->ctx,
 944                                 link,
 945                                 sink);
 946
 947                 switch (edid_status) {
 948                 case EDID_BAD_CHECKSUM:
 949                         DC_LOG_ERROR("EDID checksum invalid.\n");
 950                         break;
 951                 case EDID_NO_RESPONSE:
 952                         DC_LOG_ERROR("No EDID read.\n");
 953
 954                         /*
 955                          * Abort detection for non-DP connectors if we have
 956                          * no EDID
 957                          *
 958                          * DP needs to report as connected if HDP is high
 959                          * even if we have no EDID in order to go to
 960                          * fail-safe mode
 961                          */
 962                         if (dc_is_hdmi_signal(link->connector_signal) ||
 963                             dc_is_dvi_signal(link->connector_signal)) {
 964                                 if (prev_sink != NULL)
 965                                         dc_sink_release(prev_sink);
 966
 967                                 return false;
 968                         }
 969                 default:
 970                         break;
 971                 }
 972
 973                 if (link->local_sink->edid_caps.panel_patch.disable_fec)
 974                         link->ctx->dc->debug.disable_fec = true;
 975
 976                 // Check if edid is the same
 977                 if ((prev_sink != NULL) && ((edid_status == EDID_THE_SAME) || (edid_status == EDID_OK)))
 978                         same_edid = is_same_edid(&prev_sink->dc_edid, &sink->dc_edid);
 979
 980                 if (sink->edid_caps.panel_patch.skip_scdc_overwrite)
 981                         link->ctx->dc->debug.hdmi20_disable = true;
 982
 983                 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
 984                         sink_caps.transaction_type == DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
 985                         /*
 986                          * TODO debug why Dell 2413 doesn't like
 987                          *  two link trainings
 988                          */
 989
 990                         // verify link cap for SST non-seamless boot
 991                         if (!perform_dp_seamless_boot)
 992                                 dp_verify_link_cap_with_retries(link,
 993                                                 &link->reported_link_cap,
 994                                                 LINK_TRAINING_MAX_VERIFY_RETRY);
 995                 } else {
 996                         // If edid is the same, then discard new sink and revert back to original sink
 997                         if (same_edid) {
 998                                 link_disconnect_remap(prev_sink, link);
 999                                 sink = prev_sink;
1000                                 prev_sink = NULL;
1001
1002                         }
1003                 }
1004
1005                 /* HDMI-DVI Dongle */
1006                 if (sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A &&
1007                                 !sink->edid_caps.edid_hdmi)
1008                         sink->sink_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1009
1010                 /* Connectivity log: detection */
1011                 for (i = 0; i < sink->dc_edid.length / DC_EDID_BLOCK_SIZE; i++) {
1012                         CONN_DATA_DETECT(link,
1013                                         &sink->dc_edid.raw_edid[i * DC_EDID_BLOCK_SIZE],
1014                                         DC_EDID_BLOCK_SIZE,
1015                                         "%s: [Block %d] ", sink->edid_caps.display_name, i);
1016                 }
1017
1018                 DC_LOG_DETECTION_EDID_PARSER("%s: "
1019                         "manufacturer_id = %X, "
1020                         "product_id = %X, "
1021                         "serial_number = %X, "
1022                         "manufacture_week = %d, "
1023                         "manufacture_year = %d, "
1024                         "display_name = %s, "
1025                         "speaker_flag = %d, "
1026                         "audio_mode_count = %d\n",
1027                         __func__,
1028                         sink->edid_caps.manufacturer_id,
1029                         sink->edid_caps.product_id,
1030                         sink->edid_caps.serial_number,
1031                         sink->edid_caps.manufacture_week,
1032                         sink->edid_caps.manufacture_year,
1033                         sink->edid_caps.display_name,
1034                         sink->edid_caps.speaker_flags,
1035                         sink->edid_caps.audio_mode_count);
1036
1037                 for (i = 0; i < sink->edid_caps.audio_mode_count; i++) {
1038                         DC_LOG_DETECTION_EDID_PARSER("%s: mode number = %d, "
1039                                 "format_code = %d, "
1040                                 "channel_count = %d, "
1041                                 "sample_rate = %d, "
1042                                 "sample_size = %d\n",
1043                                 __func__,
1044                                 i,
1045                                 sink->edid_caps.audio_modes[i].format_code,
1046                                 sink->edid_caps.audio_modes[i].channel_count,
1047                                 sink->edid_caps.audio_modes[i].sample_rate,
1048                                 sink->edid_caps.audio_modes[i].sample_size);
1049                 }
1050
1051         } else {
1052                 /* From Connected-to-Disconnected. */
1053                 if (link->type == dc_connection_mst_branch) {
1054                         LINK_INFO("link=%d, mst branch is now Disconnected\n",
1055                                 link->link_index);
1056
1057                         dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
1058
1059                         link->mst_stream_alloc_table.stream_count = 0;
1060                         memset(link->mst_stream_alloc_table.stream_allocations, 0, sizeof(link->mst_stream_alloc_table.stream_allocations));
1061                 }
1062
1063                 link->type = dc_connection_none;
1064                 sink_caps.signal = SIGNAL_TYPE_NONE;
1065                 /* When we unplug a passive DP-HDMI dongle connection, dongle_max_pix_clk
1066                  *  is not cleared. If we emulate a DP signal on this connection, it thinks
1067                  *  the dongle is still there and limits the number of modes we can emulate.
1068                  *  Clear dongle_max_pix_clk on disconnect to fix this
1069                  */
1070                 link->dongle_max_pix_clk = 0;
1071         }
1072
1073         LINK_INFO("link=%d, dc_sink_in=%p is now %s prev_sink=%p dpcd same=%d edid same=%d\n",
1074                 link->link_index, sink,
1075                 (sink_caps.signal == SIGNAL_TYPE_NONE ?
1076                         "Disconnected":"Connected"), prev_sink,
1077                         same_dpcd, same_edid);
1078
1079         if (prev_sink != NULL)
1080                 dc_sink_release(prev_sink);
1081
1082         return true;
1083
1084 }
1085
1086 bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
1087 {
1088         const struct dc *dc = link->dc;
1089         bool ret;
1090
1091         /* get out of low power state */
1092         clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr);
1093
1094         ret = dc_link_detect_helper(link, reason);
1095
1096         /* Go back to power optimized state */
1097         clk_mgr_optimize_pwr_state(dc, dc->clk_mgr);
1098
1099         return ret;
1100 }
1101
1102 bool dc_link_get_hpd_state(struct dc_link *dc_link)
1103 {
1104         uint32_t state;
1105
1106         dal_gpio_lock_pin(dc_link->hpd_gpio);
1107         dal_gpio_get_value(dc_link->hpd_gpio, &state);
1108         dal_gpio_unlock_pin(dc_link->hpd_gpio);
1109
1110         return state;
1111 }
1112
1113 static enum hpd_source_id get_hpd_line(
1114                 struct dc_link *link)
1115 {
1116         struct gpio *hpd;
1117         enum hpd_source_id hpd_id = HPD_SOURCEID_UNKNOWN;
1118
1119         hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
1120
1121         if (hpd) {
1122                 switch (dal_irq_get_source(hpd)) {
1123                 case DC_IRQ_SOURCE_HPD1:
1124                         hpd_id = HPD_SOURCEID1;
1125                 break;
1126                 case DC_IRQ_SOURCE_HPD2:
1127                         hpd_id = HPD_SOURCEID2;
1128                 break;
1129                 case DC_IRQ_SOURCE_HPD3:
1130                         hpd_id = HPD_SOURCEID3;
1131                 break;
1132                 case DC_IRQ_SOURCE_HPD4:
1133                         hpd_id = HPD_SOURCEID4;
1134                 break;
1135                 case DC_IRQ_SOURCE_HPD5:
1136                         hpd_id = HPD_SOURCEID5;
1137                 break;
1138                 case DC_IRQ_SOURCE_HPD6:
1139                         hpd_id = HPD_SOURCEID6;
1140                 break;
1141                 default:
1142                         BREAK_TO_DEBUGGER();
1143                 break;
1144                 }
1145
1146                 dal_gpio_destroy_irq(&hpd);
1147         }
1148
1149         return hpd_id;
1150 }
1151
1152 static enum channel_id get_ddc_line(struct dc_link *link)
1153 {
1154         struct ddc *ddc;
1155         enum channel_id channel = CHANNEL_ID_UNKNOWN;
1156
1157         ddc = dal_ddc_service_get_ddc_pin(link->ddc);
1158
1159         if (ddc) {
1160                 switch (dal_ddc_get_line(ddc)) {
1161                 case GPIO_DDC_LINE_DDC1:
1162                         channel = CHANNEL_ID_DDC1;
1163                         break;
1164                 case GPIO_DDC_LINE_DDC2:
1165                         channel = CHANNEL_ID_DDC2;
1166                         break;
1167                 case GPIO_DDC_LINE_DDC3:
1168                         channel = CHANNEL_ID_DDC3;
1169                         break;
1170                 case GPIO_DDC_LINE_DDC4:
1171                         channel = CHANNEL_ID_DDC4;
1172                         break;
1173                 case GPIO_DDC_LINE_DDC5:
1174                         channel = CHANNEL_ID_DDC5;
1175                         break;
1176                 case GPIO_DDC_LINE_DDC6:
1177                         channel = CHANNEL_ID_DDC6;
1178                         break;
1179                 case GPIO_DDC_LINE_DDC_VGA:
1180                         channel = CHANNEL_ID_DDC_VGA;
1181                         break;
1182                 case GPIO_DDC_LINE_I2C_PAD:
1183                         channel = CHANNEL_ID_I2C_PAD;
1184                         break;
1185                 default:
1186                         BREAK_TO_DEBUGGER();
1187                         break;
1188                 }
1189         }
1190
1191         return channel;
1192 }
1193
1194 static enum transmitter translate_encoder_to_transmitter(
1195         struct graphics_object_id encoder)
1196 {
1197         switch (encoder.id) {
1198         case ENCODER_ID_INTERNAL_UNIPHY:
1199                 switch (encoder.enum_id) {
1200                 case ENUM_ID_1:
1201                         return TRANSMITTER_UNIPHY_A;
1202                 case ENUM_ID_2:
1203                         return TRANSMITTER_UNIPHY_B;
1204                 default:
1205                         return TRANSMITTER_UNKNOWN;
1206                 }
1207         break;
1208         case ENCODER_ID_INTERNAL_UNIPHY1:
1209                 switch (encoder.enum_id) {
1210                 case ENUM_ID_1:
1211                         return TRANSMITTER_UNIPHY_C;
1212                 case ENUM_ID_2:
1213                         return TRANSMITTER_UNIPHY_D;
1214                 default:
1215                         return TRANSMITTER_UNKNOWN;
1216                 }
1217         break;
1218         case ENCODER_ID_INTERNAL_UNIPHY2:
1219                 switch (encoder.enum_id) {
1220                 case ENUM_ID_1:
1221                         return TRANSMITTER_UNIPHY_E;
1222                 case ENUM_ID_2:
1223                         return TRANSMITTER_UNIPHY_F;
1224                 default:
1225                         return TRANSMITTER_UNKNOWN;
1226                 }
1227         break;
1228         case ENCODER_ID_INTERNAL_UNIPHY3:
1229                 switch (encoder.enum_id) {
1230                 case ENUM_ID_1:
1231                         return TRANSMITTER_UNIPHY_G;
1232                 default:
1233                         return TRANSMITTER_UNKNOWN;
1234                 }
1235         break;
1236         case ENCODER_ID_EXTERNAL_NUTMEG:
1237                 switch (encoder.enum_id) {
1238                 case ENUM_ID_1:
1239                         return TRANSMITTER_NUTMEG_CRT;
1240                 default:
1241                         return TRANSMITTER_UNKNOWN;
1242                 }
1243         break;
1244         case ENCODER_ID_EXTERNAL_TRAVIS:
1245                 switch (encoder.enum_id) {
1246                 case ENUM_ID_1:
1247                         return TRANSMITTER_TRAVIS_CRT;
1248                 case ENUM_ID_2:
1249                         return TRANSMITTER_TRAVIS_LCD;
1250                 default:
1251                         return TRANSMITTER_UNKNOWN;
1252                 }
1253         break;
1254         default:
1255                 return TRANSMITTER_UNKNOWN;
1256         }
1257 }
1258
1259 static bool dc_link_construct(
1260         struct dc_link *link,
1261         const struct link_init_data *init_params)
1262 {
1263         uint8_t i;
1264         struct ddc_service_init_data ddc_service_init_data = { { 0 } };
1265         struct dc_context *dc_ctx = init_params->ctx;
1266         struct encoder_init_data enc_init_data = { 0 };
1267         struct integrated_info info = {{{ 0 }}};
1268         struct dc_bios *bios = init_params->dc->ctx->dc_bios;
1269         const struct dc_vbios_funcs *bp_funcs = bios->funcs;
1270         DC_LOGGER_INIT(dc_ctx->logger);
1271
1272         link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1273         link->irq_source_hpd_rx = DC_IRQ_SOURCE_INVALID;
1274
1275         link->link_status.dpcd_caps = &link->dpcd_caps;
1276
1277         link->dc = init_params->dc;
1278         link->ctx = dc_ctx;
1279         link->link_index = init_params->link_index;
1280
1281         memset(&link->preferred_training_settings, 0, sizeof(struct dc_link_training_overrides));
1282         memset(&link->preferred_link_setting, 0, sizeof(struct dc_link_settings));
1283
1284         link->link_id = bios->funcs->get_connector_id(bios, init_params->connector_index);
1285
1286         if (link->link_id.type != OBJECT_TYPE_CONNECTOR) {
1287                 dm_output_to_console("%s: Invalid Connector ObjectID from Adapter Service for connector index:%d! type %d expected %d\n",
1288                          __func__, init_params->connector_index,
1289                          link->link_id.type, OBJECT_TYPE_CONNECTOR);
1290                 goto create_fail;
1291         }
1292
1293         if (link->dc->res_pool->funcs->link_init)
1294                 link->dc->res_pool->funcs->link_init(link);
1295
1296         link->hpd_gpio = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
1297         if (link->hpd_gpio != NULL) {
1298                 dal_gpio_open(link->hpd_gpio, GPIO_MODE_INTERRUPT);
1299                 dal_gpio_unlock_pin(link->hpd_gpio);
1300                 link->irq_source_hpd = dal_irq_get_source(link->hpd_gpio);
1301         }
1302
1303         switch (link->link_id.id) {
1304         case CONNECTOR_ID_HDMI_TYPE_A:
1305                 link->connector_signal = SIGNAL_TYPE_HDMI_TYPE_A;
1306
1307                 break;
1308         case CONNECTOR_ID_SINGLE_LINK_DVID:
1309         case CONNECTOR_ID_SINGLE_LINK_DVII:
1310                 link->connector_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1311                 break;
1312         case CONNECTOR_ID_DUAL_LINK_DVID:
1313         case CONNECTOR_ID_DUAL_LINK_DVII:
1314                 link->connector_signal = SIGNAL_TYPE_DVI_DUAL_LINK;
1315                 break;
1316         case CONNECTOR_ID_DISPLAY_PORT:
1317                 link->connector_signal =        SIGNAL_TYPE_DISPLAY_PORT;
1318
1319                 if (link->hpd_gpio != NULL)
1320                         link->irq_source_hpd_rx =
1321                                         dal_irq_get_rx_source(link->hpd_gpio);
1322
1323                 break;
1324         case CONNECTOR_ID_EDP:
1325                 link->connector_signal = SIGNAL_TYPE_EDP;
1326
1327                 if (link->hpd_gpio != NULL) {
1328                         link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1329                         link->irq_source_hpd_rx =
1330                                         dal_irq_get_rx_source(link->hpd_gpio);
1331                 }
1332                 break;
1333         case CONNECTOR_ID_LVDS:
1334                 link->connector_signal = SIGNAL_TYPE_LVDS;
1335                 break;
1336         default:
1337                 DC_LOG_WARNING("Unsupported Connector type:%d!\n", link->link_id.id);
1338                 goto create_fail;
1339         }
1340
1341         /* TODO: #DAL3 Implement id to str function.*/
1342         LINK_INFO("Connector[%d] description:"
1343                         "signal %d\n",
1344                         init_params->connector_index,
1345                         link->connector_signal);
1346
1347         ddc_service_init_data.ctx = link->ctx;
1348         ddc_service_init_data.id = link->link_id;
1349         ddc_service_init_data.link = link;
1350         link->ddc = dal_ddc_service_create(&ddc_service_init_data);
1351
1352         if (link->ddc == NULL) {
1353                 DC_ERROR("Failed to create ddc_service!\n");
1354                 goto ddc_create_fail;
1355         }
1356
1357         link->ddc_hw_inst =
1358                 dal_ddc_get_line(
1359                         dal_ddc_service_get_ddc_pin(link->ddc));
1360
1361         enc_init_data.ctx = dc_ctx;
1362         bp_funcs->get_src_obj(dc_ctx->dc_bios, link->link_id, 0, &enc_init_data.encoder);
1363         enc_init_data.connector = link->link_id;
1364         enc_init_data.channel = get_ddc_line(link);
1365         enc_init_data.hpd_source = get_hpd_line(link);
1366
1367         link->hpd_src = enc_init_data.hpd_source;
1368
1369         enc_init_data.transmitter =
1370                         translate_encoder_to_transmitter(enc_init_data.encoder);
1371         link->link_enc = link->dc->res_pool->funcs->link_enc_create(
1372                                                                 &enc_init_data);
1373
1374         if (link->link_enc == NULL) {
1375                 DC_ERROR("Failed to create link encoder!\n");
1376                 goto link_enc_create_fail;
1377         }
1378
1379         link->link_enc_hw_inst = link->link_enc->transmitter;
1380
1381         for (i = 0; i < 4; i++) {
1382                 if (BP_RESULT_OK !=
1383                                 bp_funcs->get_device_tag(dc_ctx->dc_bios, link->link_id, i, &link->device_tag)) {
1384                         DC_ERROR("Failed to find device tag!\n");
1385                         goto device_tag_fail;
1386                 }
1387
1388                 /* Look for device tag that matches connector signal,
1389                  * CRT for rgb, LCD for other supported signal tyes
1390                  */
1391                 if (!bp_funcs->is_device_id_supported(dc_ctx->dc_bios, link->device_tag.dev_id))
1392                         continue;
1393                 if (link->device_tag.dev_id.device_type == DEVICE_TYPE_CRT
1394                         && link->connector_signal != SIGNAL_TYPE_RGB)
1395                         continue;
1396                 if (link->device_tag.dev_id.device_type == DEVICE_TYPE_LCD
1397                         && link->connector_signal == SIGNAL_TYPE_RGB)
1398                         continue;
1399                 break;
1400         }
1401
1402         if (bios->integrated_info)
1403                 info = *bios->integrated_info;
1404
1405         /* Look for channel mapping corresponding to connector and device tag */
1406         for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; i++) {
1407                 struct external_display_path *path =
1408                         &info.ext_disp_conn_info.path[i];
1409                 if (path->device_connector_id.enum_id == link->link_id.enum_id
1410                         && path->device_connector_id.id == link->link_id.id
1411                         && path->device_connector_id.type == link->link_id.type) {
1412
1413                         if (link->device_tag.acpi_device != 0
1414                                 && path->device_acpi_enum == link->device_tag.acpi_device) {
1415                                 link->ddi_channel_mapping = path->channel_mapping;
1416                                 link->chip_caps = path->caps;
1417                         } else if (path->device_tag ==
1418                                         link->device_tag.dev_id.raw_device_tag) {
1419                                 link->ddi_channel_mapping = path->channel_mapping;
1420                                 link->chip_caps = path->caps;
1421                         }
1422                         break;
1423                 }
1424         }
1425
1426         /*
1427          * TODO check if GPIO programmed correctly
1428          *
1429          * If GPIO isn't programmed correctly HPD might not rise or drain
1430          * fast enough, leading to bounces.
1431          */
1432         program_hpd_filter(link);
1433
1434         return true;
1435 device_tag_fail:
1436         link->link_enc->funcs->destroy(&link->link_enc);
1437 link_enc_create_fail:
1438         dal_ddc_service_destroy(&link->ddc);
1439 ddc_create_fail:
1440 create_fail:
1441
1442         if (link->hpd_gpio != NULL) {
1443                 dal_gpio_destroy_irq(&link->hpd_gpio);
1444                 link->hpd_gpio = NULL;
1445         }
1446
1447         return false;
1448 }
1449
1450 /*******************************************************************************
1451  * Public functions
1452  ******************************************************************************/
1453 struct dc_link *link_create(const struct link_init_data *init_params)
1454 {
1455         struct dc_link *link =
1456                         kzalloc(sizeof(*link), GFP_KERNEL);
1457
1458         if (NULL == link)
1459                 goto alloc_fail;
1460
1461         if (false == dc_link_construct(link, init_params))
1462                 goto construct_fail;
1463
1464         return link;
1465
1466 construct_fail:
1467         kfree(link);
1468
1469 alloc_fail:
1470         return NULL;
1471 }
1472
1473 void link_destroy(struct dc_link **link)
1474 {
1475         dc_link_destruct(*link);
1476         kfree(*link);
1477         *link = NULL;
1478 }
1479
1480 static void enable_stream_features(struct pipe_ctx *pipe_ctx)
1481 {
1482         struct dc_stream_state *stream = pipe_ctx->stream;
1483         struct dc_link *link = stream->link;
1484         union down_spread_ctrl old_downspread;
1485         union down_spread_ctrl new_downspread;
1486
1487         core_link_read_dpcd(link, DP_DOWNSPREAD_CTRL,
1488                         &old_downspread.raw, sizeof(old_downspread));
1489
1490         new_downspread.raw = old_downspread.raw;
1491
1492         new_downspread.bits.IGNORE_MSA_TIMING_PARAM =
1493                         (stream->ignore_msa_timing_param) ? 1 : 0;
1494
1495         if (new_downspread.raw != old_downspread.raw) {
1496                 core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
1497                         &new_downspread.raw, sizeof(new_downspread));
1498         }
1499 }
1500
1501 static enum dc_status enable_link_dp(struct dc_state *state,
1502                                      struct pipe_ctx *pipe_ctx)
1503 {
1504         struct dc_stream_state *stream = pipe_ctx->stream;
1505         enum dc_status status;
1506         bool skip_video_pattern;
1507         struct dc_link *link = stream->link;
1508         struct dc_link_settings link_settings = {0};
1509         bool fec_enable;
1510         int i;
1511         bool apply_seamless_boot_optimization = false;
1512         uint32_t bl_oled_enable_delay = 50; // in ms
1513
1514         // check for seamless boot
1515         for (i = 0; i < state->stream_count; i++) {
1516                 if (state->streams[i]->apply_seamless_boot_optimization) {
1517                         apply_seamless_boot_optimization = true;
1518                         break;
1519                 }
1520         }
1521
1522         /* get link settings for video mode timing */
1523         decide_link_settings(stream, &link_settings);
1524
1525         if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) {
1526                 /*in case it is not on*/
1527                 link->dc->hwss.edp_power_control(link, true);
1528                 link->dc->hwss.edp_wait_for_hpd_ready(link, true);
1529         }
1530
1531         pipe_ctx->stream_res.pix_clk_params.requested_sym_clk =
1532                         link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
1533         if (state->clk_mgr && !apply_seamless_boot_optimization)
1534                 state->clk_mgr->funcs->update_clocks(state->clk_mgr,
1535                                                      state, false);
1536
1537         // during mode switch we do DP_SET_POWER off then on, and OUI is lost
1538         dpcd_set_source_specific_data(link);
1539
1540         skip_video_pattern = true;
1541
1542         if (link_settings.link_rate == LINK_RATE_LOW)
1543                 skip_video_pattern = false;
1544
1545         if (perform_link_training_with_retries(&link_settings,
1546                                                skip_video_pattern,
1547                                                LINK_TRAINING_ATTEMPTS,
1548                                                pipe_ctx,
1549                                                pipe_ctx->stream->signal)) {
1550                 link->cur_link_settings = link_settings;
1551                 status = DC_OK;
1552         } else {
1553                 status = DC_FAIL_DP_LINK_TRAINING;
1554         }
1555
1556         if (link->preferred_training_settings.fec_enable)
1557                 fec_enable = *link->preferred_training_settings.fec_enable;
1558         else
1559                 fec_enable = true;
1560
1561         dp_set_fec_enable(link, fec_enable);
1562
1563         // during mode set we do DP_SET_POWER off then on, aux writes are lost
1564         if (link->dpcd_sink_ext_caps.bits.oled == 1 ||
1565                 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1 ||
1566                 link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1) {
1567                 dc_link_set_default_brightness_aux(link); // TODO: use cached if known
1568                 if (link->dpcd_sink_ext_caps.bits.oled == 1)
1569                         msleep(bl_oled_enable_delay);
1570                 dc_link_backlight_enable_aux(link, true);
1571         }
1572
1573         return status;
1574 }
1575
1576 static enum dc_status enable_link_edp(
1577                 struct dc_state *state,
1578                 struct pipe_ctx *pipe_ctx)
1579 {
1580         enum dc_status status;
1581
1582         status = enable_link_dp(state, pipe_ctx);
1583
1584         return status;
1585 }
1586
1587 static enum dc_status enable_link_dp_mst(
1588                 struct dc_state *state,
1589                 struct pipe_ctx *pipe_ctx)
1590 {
1591         struct dc_link *link = pipe_ctx->stream->link;
1592
1593         /* sink signal type after MST branch is MST. Multiple MST sinks
1594          * share one link. Link DP PHY is enable or training only once.
1595          */
1596         if (link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN)
1597                 return DC_OK;
1598
1599         /* clear payload table */
1600         dm_helpers_dp_mst_clear_payload_allocation_table(link->ctx, link);
1601
1602         /* to make sure the pending down rep can be processed
1603          * before enabling the link
1604          */
1605         dm_helpers_dp_mst_poll_pending_down_reply(link->ctx, link);
1606
1607         /* set the sink to MST mode before enabling the link */
1608         dp_enable_mst_on_sink(link, true);
1609
1610         return enable_link_dp(state, pipe_ctx);
1611 }
1612
1613 static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx,
1614                 enum engine_id eng_id,
1615                 struct ext_hdmi_settings *settings)
1616 {
1617         bool result = false;
1618         int i = 0;
1619         struct integrated_info *integrated_info =
1620                         pipe_ctx->stream->ctx->dc_bios->integrated_info;
1621
1622         if (integrated_info == NULL)
1623                 return false;
1624
1625         /*
1626          * Get retimer settings from sbios for passing SI eye test for DCE11
1627          * The setting values are varied based on board revision and port id
1628          * Therefore the setting values of each ports is passed by sbios.
1629          */
1630
1631         // Check if current bios contains ext Hdmi settings
1632         if (integrated_info->gpu_cap_info & 0x20) {
1633                 switch (eng_id) {
1634                 case ENGINE_ID_DIGA:
1635                         settings->slv_addr = integrated_info->dp0_ext_hdmi_slv_addr;
1636                         settings->reg_num = integrated_info->dp0_ext_hdmi_6g_reg_num;
1637                         settings->reg_num_6g = integrated_info->dp0_ext_hdmi_6g_reg_num;
1638                         memmove(settings->reg_settings,
1639                                         integrated_info->dp0_ext_hdmi_reg_settings,
1640                                         sizeof(integrated_info->dp0_ext_hdmi_reg_settings));
1641                         memmove(settings->reg_settings_6g,
1642                                         integrated_info->dp0_ext_hdmi_6g_reg_settings,
1643                                         sizeof(integrated_info->dp0_ext_hdmi_6g_reg_settings));
1644                         result = true;
1645                         break;
1646                 case ENGINE_ID_DIGB:
1647                         settings->slv_addr = integrated_info->dp1_ext_hdmi_slv_addr;
1648                         settings->reg_num = integrated_info->dp1_ext_hdmi_6g_reg_num;
1649                         settings->reg_num_6g = integrated_info->dp1_ext_hdmi_6g_reg_num;
1650                         memmove(settings->reg_settings,
1651                                         integrated_info->dp1_ext_hdmi_reg_settings,
1652                                         sizeof(integrated_info->dp1_ext_hdmi_reg_settings));
1653                         memmove(settings->reg_settings_6g,
1654                                         integrated_info->dp1_ext_hdmi_6g_reg_settings,
1655                                         sizeof(integrated_info->dp1_ext_hdmi_6g_reg_settings));
1656                         result = true;
1657                         break;
1658                 case ENGINE_ID_DIGC:
1659                         settings->slv_addr = integrated_info->dp2_ext_hdmi_slv_addr;
1660                         settings->reg_num = integrated_info->dp2_ext_hdmi_6g_reg_num;
1661                         settings->reg_num_6g = integrated_info->dp2_ext_hdmi_6g_reg_num;
1662                         memmove(settings->reg_settings,
1663                                         integrated_info->dp2_ext_hdmi_reg_settings,
1664                                         sizeof(integrated_info->dp2_ext_hdmi_reg_settings));
1665                         memmove(settings->reg_settings_6g,
1666                                         integrated_info->dp2_ext_hdmi_6g_reg_settings,
1667                                         sizeof(integrated_info->dp2_ext_hdmi_6g_reg_settings));
1668                         result = true;
1669                         break;
1670                 case ENGINE_ID_DIGD:
1671                         settings->slv_addr = integrated_info->dp3_ext_hdmi_slv_addr;
1672                         settings->reg_num = integrated_info->dp3_ext_hdmi_6g_reg_num;
1673                         settings->reg_num_6g = integrated_info->dp3_ext_hdmi_6g_reg_num;
1674                         memmove(settings->reg_settings,
1675                                         integrated_info->dp3_ext_hdmi_reg_settings,
1676                                         sizeof(integrated_info->dp3_ext_hdmi_reg_settings));
1677                         memmove(settings->reg_settings_6g,
1678                                         integrated_info->dp3_ext_hdmi_6g_reg_settings,
1679                                         sizeof(integrated_info->dp3_ext_hdmi_6g_reg_settings));
1680                         result = true;
1681                         break;
1682                 default:
1683                         break;
1684                 }
1685
1686                 if (result == true) {
1687                         // Validate settings from bios integrated info table
1688                         if (settings->slv_addr == 0)
1689                                 return false;
1690                         if (settings->reg_num > 9)
1691                                 return false;
1692                         if (settings->reg_num_6g > 3)
1693                                 return false;
1694
1695                         for (i = 0; i < settings->reg_num; i++) {
1696                                 if (settings->reg_settings[i].i2c_reg_index > 0x20)
1697                                         return false;
1698                         }
1699
1700                         for (i = 0; i < settings->reg_num_6g; i++) {
1701                                 if (settings->reg_settings_6g[i].i2c_reg_index > 0x20)
1702                                         return false;
1703                         }
1704                 }
1705         }
1706
1707         return result;
1708 }
1709
1710 static bool i2c_write(struct pipe_ctx *pipe_ctx,
1711                 uint8_t address, uint8_t *buffer, uint32_t length)
1712 {
1713         struct i2c_command cmd = {0};
1714         struct i2c_payload payload = {0};
1715
1716         memset(&payload, 0, sizeof(payload));
1717         memset(&cmd, 0, sizeof(cmd));
1718
1719         cmd.number_of_payloads = 1;
1720         cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
1721         cmd.speed = pipe_ctx->stream->ctx->dc->caps.i2c_speed_in_khz;
1722
1723         payload.address = address;
1724         payload.data = buffer;
1725         payload.length = length;
1726         payload.write = true;
1727         cmd.payloads = &payload;
1728
1729         if (dm_helpers_submit_i2c(pipe_ctx->stream->ctx,
1730                         pipe_ctx->stream->link, &cmd))
1731                 return true;
1732
1733         return false;
1734 }
1735
1736 static void write_i2c_retimer_setting(
1737                 struct pipe_ctx *pipe_ctx,
1738                 bool is_vga_mode,
1739                 bool is_over_340mhz,
1740                 struct ext_hdmi_settings *settings)
1741 {
1742         uint8_t slave_address = (settings->slv_addr >> 1);
1743         uint8_t buffer[2];
1744         const uint8_t apply_rx_tx_change = 0x4;
1745         uint8_t offset = 0xA;
1746         uint8_t value = 0;
1747         int i = 0;
1748         bool i2c_success = false;
1749         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
1750
1751         memset(&buffer, 0, sizeof(buffer));
1752
1753         /* Start Ext-Hdmi programming*/
1754
1755         for (i = 0; i < settings->reg_num; i++) {
1756                 /* Apply 3G settings */
1757                 if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
1758
1759                         buffer[0] = settings->reg_settings[i].i2c_reg_index;
1760                         buffer[1] = settings->reg_settings[i].i2c_reg_val;
1761                         i2c_success = i2c_write(pipe_ctx, slave_address,
1762                                                 buffer, sizeof(buffer));
1763                         RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1764                                 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
1765                                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1766
1767                         if (!i2c_success)
1768                                 goto i2c_write_fail;
1769
1770                         /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
1771                          * needs to be set to 1 on every 0xA-0xC write.
1772                          */
1773                         if (settings->reg_settings[i].i2c_reg_index == 0xA ||
1774                                 settings->reg_settings[i].i2c_reg_index == 0xB ||
1775                                 settings->reg_settings[i].i2c_reg_index == 0xC) {
1776
1777                                 /* Query current value from offset 0xA */
1778                                 if (settings->reg_settings[i].i2c_reg_index == 0xA)
1779                                         value = settings->reg_settings[i].i2c_reg_val;
1780                                 else {
1781                                         i2c_success =
1782                                                 dal_ddc_service_query_ddc_data(
1783                                                 pipe_ctx->stream->link->ddc,
1784                                                 slave_address, &offset, 1, &value, 1);
1785                                         if (!i2c_success)
1786                                                 goto i2c_write_fail;
1787                                 }
1788
1789                                 buffer[0] = offset;
1790                                 /* Set APPLY_RX_TX_CHANGE bit to 1 */
1791                                 buffer[1] = value | apply_rx_tx_change;
1792                                 i2c_success = i2c_write(pipe_ctx, slave_address,
1793                                                 buffer, sizeof(buffer));
1794                                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1795                                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1796                                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
1797                                 if (!i2c_success)
1798                                         goto i2c_write_fail;
1799                         }
1800                 }
1801         }
1802
1803         /* Apply 3G settings */
1804         if (is_over_340mhz) {
1805                 for (i = 0; i < settings->reg_num_6g; i++) {
1806                         /* Apply 3G settings */
1807                         if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
1808
1809                                 buffer[0] = settings->reg_settings_6g[i].i2c_reg_index;
1810                                 buffer[1] = settings->reg_settings_6g[i].i2c_reg_val;
1811                                 i2c_success = i2c_write(pipe_ctx, slave_address,
1812                                                         buffer, sizeof(buffer));
1813                                 RETIMER_REDRIVER_INFO("above 340Mhz: retimer write to slave_address = 0x%x,\
1814                                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1815                                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
1816
1817                                 if (!i2c_success)
1818                                         goto i2c_write_fail;
1819
1820                                 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
1821                                  * needs to be set to 1 on every 0xA-0xC write.
1822                                  */
1823                                 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA ||
1824                                         settings->reg_settings_6g[i].i2c_reg_index == 0xB ||
1825                                         settings->reg_settings_6g[i].i2c_reg_index == 0xC) {
1826
1827                                         /* Query current value from offset 0xA */
1828                                         if (settings->reg_settings_6g[i].i2c_reg_index == 0xA)
1829                                                 value = settings->reg_settings_6g[i].i2c_reg_val;
1830                                         else {
1831                                                 i2c_success =
1832                                                                 dal_ddc_service_query_ddc_data(
1833                                                                 pipe_ctx->stream->link->ddc,
1834                                                                 slave_address, &offset, 1, &value, 1);
1835                                                 if (!i2c_success)
1836                                                         goto i2c_write_fail;
1837                                         }
1838
1839                                         buffer[0] = offset;
1840                                         /* Set APPLY_RX_TX_CHANGE bit to 1 */
1841                                         buffer[1] = value | apply_rx_tx_change;
1842                                         i2c_success = i2c_write(pipe_ctx, slave_address,
1843                                                         buffer, sizeof(buffer));
1844                                         RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1845                                                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1846                                                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1847                                         if (!i2c_success)
1848                                                 goto i2c_write_fail;
1849                                 }
1850                         }
1851                 }
1852         }
1853
1854         if (is_vga_mode) {
1855                 /* Program additional settings if using 640x480 resolution */
1856
1857                 /* Write offset 0xFF to 0x01 */
1858                 buffer[0] = 0xff;
1859                 buffer[1] = 0x01;
1860                 i2c_success = i2c_write(pipe_ctx, slave_address,
1861                                 buffer, sizeof(buffer));
1862                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1863                                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1864                                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1865                 if (!i2c_success)
1866                         goto i2c_write_fail;
1867
1868                 /* Write offset 0x00 to 0x23 */
1869                 buffer[0] = 0x00;
1870                 buffer[1] = 0x23;
1871                 i2c_success = i2c_write(pipe_ctx, slave_address,
1872                                 buffer, sizeof(buffer));
1873                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1874                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1875                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
1876                 if (!i2c_success)
1877                         goto i2c_write_fail;
1878
1879                 /* Write offset 0xff to 0x00 */
1880                 buffer[0] = 0xff;
1881                 buffer[1] = 0x00;
1882                 i2c_success = i2c_write(pipe_ctx, slave_address,
1883                                 buffer, sizeof(buffer));
1884                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1885                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1886                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
1887                 if (!i2c_success)
1888                         goto i2c_write_fail;
1889
1890         }
1891
1892         return;
1893
1894 i2c_write_fail:
1895         DC_LOG_DEBUG("Set retimer failed");
1896 }
1897
1898 static void write_i2c_default_retimer_setting(
1899                 struct pipe_ctx *pipe_ctx,
1900                 bool is_vga_mode,
1901                 bool is_over_340mhz)
1902 {
1903         uint8_t slave_address = (0xBA >> 1);
1904         uint8_t buffer[2];
1905         bool i2c_success = false;
1906         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
1907
1908         memset(&buffer, 0, sizeof(buffer));
1909
1910         /* Program Slave Address for tuning single integrity */
1911         /* Write offset 0x0A to 0x13 */
1912         buffer[0] = 0x0A;
1913         buffer[1] = 0x13;
1914         i2c_success = i2c_write(pipe_ctx, slave_address,
1915                         buffer, sizeof(buffer));
1916         RETIMER_REDRIVER_INFO("retimer writes default setting to slave_address = 0x%x,\
1917                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1918                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1919         if (!i2c_success)
1920                 goto i2c_write_fail;
1921
1922         /* Write offset 0x0A to 0x17 */
1923         buffer[0] = 0x0A;
1924         buffer[1] = 0x17;
1925         i2c_success = i2c_write(pipe_ctx, slave_address,
1926                         buffer, sizeof(buffer));
1927         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
1928                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1929                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1930         if (!i2c_success)
1931                 goto i2c_write_fail;
1932
1933         /* Write offset 0x0B to 0xDA or 0xD8 */
1934         buffer[0] = 0x0B;
1935         buffer[1] = is_over_340mhz ? 0xDA : 0xD8;
1936         i2c_success = i2c_write(pipe_ctx, slave_address,
1937                         buffer, sizeof(buffer));
1938         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
1939                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1940                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1941         if (!i2c_success)
1942                 goto i2c_write_fail;
1943
1944         /* Write offset 0x0A to 0x17 */
1945         buffer[0] = 0x0A;
1946         buffer[1] = 0x17;
1947         i2c_success = i2c_write(pipe_ctx, slave_address,
1948                         buffer, sizeof(buffer));
1949         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
1950                 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
1951                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1952         if (!i2c_success)
1953                 goto i2c_write_fail;
1954
1955         /* Write offset 0x0C to 0x1D or 0x91 */
1956         buffer[0] = 0x0C;
1957         buffer[1] = is_over_340mhz ? 0x1D : 0x91;
1958         i2c_success = i2c_write(pipe_ctx, slave_address,
1959                         buffer, sizeof(buffer));
1960         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
1961                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1962                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1963         if (!i2c_success)
1964                 goto i2c_write_fail;
1965
1966         /* Write offset 0x0A to 0x17 */
1967         buffer[0] = 0x0A;
1968         buffer[1] = 0x17;
1969         i2c_success = i2c_write(pipe_ctx, slave_address,
1970                         buffer, sizeof(buffer));
1971         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
1972                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1973                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1974         if (!i2c_success)
1975                 goto i2c_write_fail;
1976
1977
1978         if (is_vga_mode) {
1979                 /* Program additional settings if using 640x480 resolution */
1980
1981                 /* Write offset 0xFF to 0x01 */
1982                 buffer[0] = 0xff;
1983                 buffer[1] = 0x01;
1984                 i2c_success = i2c_write(pipe_ctx, slave_address,
1985                                 buffer, sizeof(buffer));
1986                 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
1987                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
1988                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
1989                 if (!i2c_success)
1990                         goto i2c_write_fail;
1991
1992                 /* Write offset 0x00 to 0x23 */
1993                 buffer[0] = 0x00;
1994                 buffer[1] = 0x23;
1995                 i2c_success = i2c_write(pipe_ctx, slave_address,
1996                                 buffer, sizeof(buffer));
1997                 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
1998                         offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
1999                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2000                 if (!i2c_success)
2001                         goto i2c_write_fail;
2002
2003                 /* Write offset 0xff to 0x00 */
2004                 buffer[0] = 0xff;
2005                 buffer[1] = 0x00;
2006                 i2c_success = i2c_write(pipe_ctx, slave_address,
2007                                 buffer, sizeof(buffer));
2008                 RETIMER_REDRIVER_INFO("retimer write default setting to slave_addr = 0x%x,\
2009                         offset = 0x%x, reg_val= 0x%x, i2c_success = %d end here\n",
2010                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2011                 if (!i2c_success)
2012                         goto i2c_write_fail;
2013         }
2014
2015         return;
2016
2017 i2c_write_fail:
2018         DC_LOG_DEBUG("Set default retimer failed");
2019 }
2020
2021 static void write_i2c_redriver_setting(
2022                 struct pipe_ctx *pipe_ctx,
2023                 bool is_over_340mhz)
2024 {
2025         uint8_t slave_address = (0xF0 >> 1);
2026         uint8_t buffer[16];
2027         bool i2c_success = false;
2028         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
2029
2030         memset(&buffer, 0, sizeof(buffer));
2031
2032         // Program Slave Address for tuning single integrity
2033         buffer[3] = 0x4E;
2034         buffer[4] = 0x4E;
2035         buffer[5] = 0x4E;
2036         buffer[6] = is_over_340mhz ? 0x4E : 0x4A;
2037
2038         i2c_success = i2c_write(pipe_ctx, slave_address,
2039                                         buffer, sizeof(buffer));
2040         RETIMER_REDRIVER_INFO("redriver write 0 to all 16 reg offset expect following:\n\
2041                 \t slave_addr = 0x%x, offset[3] = 0x%x, offset[4] = 0x%x,\
2042                 offset[5] = 0x%x,offset[6] is_over_340mhz = 0x%x,\
2043                 i2c_success = %d\n",
2044                 slave_address, buffer[3], buffer[4], buffer[5], buffer[6], i2c_success?1:0);
2045
2046         if (!i2c_success)
2047                 DC_LOG_DEBUG("Set redriver failed");
2048 }
2049
2050 static void disable_link(struct dc_link *link, enum signal_type signal)
2051 {
2052         /*
2053          * TODO: implement call for dp_set_hw_test_pattern
2054          * it is needed for compliance testing
2055          */
2056
2057         /* Here we need to specify that encoder output settings
2058          * need to be calculated as for the set mode,
2059          * it will lead to querying dynamic link capabilities
2060          * which should be done before enable output
2061          */
2062
2063         if (dc_is_dp_signal(signal)) {
2064                 /* SST DP, eDP */
2065                 if (dc_is_dp_sst_signal(signal))
2066                         dp_disable_link_phy(link, signal);
2067                 else
2068                         dp_disable_link_phy_mst(link, signal);
2069
2070                 if (dc_is_dp_sst_signal(signal) ||
2071                                 link->mst_stream_alloc_table.stream_count == 0) {
2072                         dp_set_fec_enable(link, false);
2073                         dp_set_fec_ready(link, false);
2074                 }
2075         } else {
2076                 if (signal != SIGNAL_TYPE_VIRTUAL)
2077                         link->link_enc->funcs->disable_output(link->link_enc, signal);
2078         }
2079
2080         if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
2081                 /* MST disable link only when no stream use the link */
2082                 if (link->mst_stream_alloc_table.stream_count <= 0)
2083                         link->link_status.link_active = false;
2084         } else {
2085                 link->link_status.link_active = false;
2086         }
2087 }
2088
2089 static void enable_link_hdmi(struct pipe_ctx *pipe_ctx)
2090 {
2091         struct dc_stream_state *stream = pipe_ctx->stream;
2092         struct dc_link *link = stream->link;
2093         enum dc_color_depth display_color_depth;
2094         enum engine_id eng_id;
2095         struct ext_hdmi_settings settings = {0};
2096         bool is_over_340mhz = false;
2097         bool is_vga_mode = (stream->timing.h_addressable == 640)
2098                         && (stream->timing.v_addressable == 480);
2099
2100         if (stream->phy_pix_clk == 0)
2101                 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10;
2102         if (stream->phy_pix_clk > 340000)
2103                 is_over_340mhz = true;
2104
2105         if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
2106                 unsigned short masked_chip_caps = pipe_ctx->stream->link->chip_caps &
2107                                 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
2108                 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {
2109                         /* DP159, Retimer settings */
2110                         eng_id = pipe_ctx->stream_res.stream_enc->id;
2111
2112                         if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) {
2113                                 write_i2c_retimer_setting(pipe_ctx,
2114                                                 is_vga_mode, is_over_340mhz, &settings);
2115                         } else {
2116                                 write_i2c_default_retimer_setting(pipe_ctx,
2117                                                 is_vga_mode, is_over_340mhz);
2118                         }
2119                 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {
2120                         /* PI3EQX1204, Redriver settings */
2121                         write_i2c_redriver_setting(pipe_ctx, is_over_340mhz);
2122                 }
2123         }
2124
2125         if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
2126                 dal_ddc_service_write_scdc_data(
2127                         stream->link->ddc,
2128                         stream->phy_pix_clk,
2129                         stream->timing.flags.LTE_340MCSC_SCRAMBLE);
2130
2131         memset(&stream->link->cur_link_settings, 0,
2132                         sizeof(struct dc_link_settings));
2133
2134         display_color_depth = stream->timing.display_color_depth;
2135         if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
2136                 display_color_depth = COLOR_DEPTH_888;
2137
2138         link->link_enc->funcs->enable_tmds_output(
2139                         link->link_enc,
2140                         pipe_ctx->clock_source->id,
2141                         display_color_depth,
2142                         pipe_ctx->stream->signal,
2143                         stream->phy_pix_clk);
2144
2145         if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
2146                 dal_ddc_service_read_scdc_data(link->ddc);
2147 }
2148
2149 static void enable_link_lvds(struct pipe_ctx *pipe_ctx)
2150 {
2151         struct dc_stream_state *stream = pipe_ctx->stream;
2152         struct dc_link *link = stream->link;
2153
2154         if (stream->phy_pix_clk == 0)
2155                 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10;
2156
2157         memset(&stream->link->cur_link_settings, 0,
2158                         sizeof(struct dc_link_settings));
2159
2160         link->link_enc->funcs->enable_lvds_output(
2161                         link->link_enc,
2162                         pipe_ctx->clock_source->id,
2163                         stream->phy_pix_clk);
2164
2165 }
2166
2167 /****************************enable_link***********************************/
2168 static enum dc_status enable_link(
2169                 struct dc_state *state,
2170                 struct pipe_ctx *pipe_ctx)
2171 {
2172         enum dc_status status = DC_ERROR_UNEXPECTED;
2173         struct dc_stream_state *stream = pipe_ctx->stream;
2174         struct dc_link *link = stream->link;
2175
2176         /* There's some scenarios where driver is unloaded with display
2177          * still enabled. When driver is reloaded, it may cause a display
2178          * to not light up if there is a mismatch between old and new
2179          * link settings. Need to call disable first before enabling at
2180          * new link settings.
2181          */
2182         if (link->link_status.link_active) {
2183                 disable_link(link, pipe_ctx->stream->signal);
2184         }
2185
2186         switch (pipe_ctx->stream->signal) {
2187         case SIGNAL_TYPE_DISPLAY_PORT:
2188                 status = enable_link_dp(state, pipe_ctx);
2189                 break;
2190         case SIGNAL_TYPE_EDP:
2191                 status = enable_link_edp(state, pipe_ctx);
2192                 break;
2193         case SIGNAL_TYPE_DISPLAY_PORT_MST:
2194                 status = enable_link_dp_mst(state, pipe_ctx);
2195                 msleep(200);
2196                 break;
2197         case SIGNAL_TYPE_DVI_SINGLE_LINK:
2198         case SIGNAL_TYPE_DVI_DUAL_LINK:
2199         case SIGNAL_TYPE_HDMI_TYPE_A:
2200                 enable_link_hdmi(pipe_ctx);
2201                 status = DC_OK;
2202                 break;
2203         case SIGNAL_TYPE_LVDS:
2204                 enable_link_lvds(pipe_ctx);
2205                 status = DC_OK;
2206                 break;
2207         case SIGNAL_TYPE_VIRTUAL:
2208                 status = DC_OK;
2209                 break;
2210         default:
2211                 break;
2212         }
2213
2214         if (status == DC_OK)
2215                 pipe_ctx->stream->link->link_status.link_active = true;
2216
2217         return status;
2218 }
2219
2220 static uint32_t get_timing_pixel_clock_100hz(const struct dc_crtc_timing *timing)
2221 {
2222
2223         uint32_t pxl_clk = timing->pix_clk_100hz;
2224
2225         if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
2226                 pxl_clk /= 2;
2227         else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
2228                 pxl_clk = pxl_clk * 2 / 3;
2229
2230         if (timing->display_color_depth == COLOR_DEPTH_101010)
2231                 pxl_clk = pxl_clk * 10 / 8;
2232         else if (timing->display_color_depth == COLOR_DEPTH_121212)
2233                 pxl_clk = pxl_clk * 12 / 8;
2234
2235         return pxl_clk;
2236 }
2237
2238 static bool dp_active_dongle_validate_timing(
2239                 const struct dc_crtc_timing *timing,
2240                 const struct dpcd_caps *dpcd_caps)
2241 {
2242         const struct dc_dongle_caps *dongle_caps = &dpcd_caps->dongle_caps;
2243
2244         switch (dpcd_caps->dongle_type) {
2245         case DISPLAY_DONGLE_DP_VGA_CONVERTER:
2246         case DISPLAY_DONGLE_DP_DVI_CONVERTER:
2247         case DISPLAY_DONGLE_DP_DVI_DONGLE:
2248                 if (timing->pixel_encoding == PIXEL_ENCODING_RGB)
2249                         return true;
2250                 else
2251                         return false;
2252         default:
2253                 break;
2254         }
2255
2256         if (dpcd_caps->dongle_type != DISPLAY_DONGLE_DP_HDMI_CONVERTER ||
2257                 dongle_caps->extendedCapValid == false)
2258                 return true;
2259
2260         /* Check Pixel Encoding */
2261         switch (timing->pixel_encoding) {
2262         case PIXEL_ENCODING_RGB:
2263         case PIXEL_ENCODING_YCBCR444:
2264                 break;
2265         case PIXEL_ENCODING_YCBCR422:
2266                 if (!dongle_caps->is_dp_hdmi_ycbcr422_pass_through)
2267                         return false;
2268                 break;
2269         case PIXEL_ENCODING_YCBCR420:
2270                 if (!dongle_caps->is_dp_hdmi_ycbcr420_pass_through)
2271                         return false;
2272                 break;
2273         default:
2274                 /* Invalid Pixel Encoding*/
2275                 return false;
2276         }
2277
2278         switch (timing->display_color_depth) {
2279         case COLOR_DEPTH_666:
2280         case COLOR_DEPTH_888:
2281                 /*888 and 666 should always be supported*/
2282                 break;
2283         case COLOR_DEPTH_101010:
2284                 if (dongle_caps->dp_hdmi_max_bpc < 10)
2285                         return false;
2286                 break;
2287         case COLOR_DEPTH_121212:
2288                 if (dongle_caps->dp_hdmi_max_bpc < 12)
2289                         return false;
2290                 break;
2291         case COLOR_DEPTH_141414:
2292         case COLOR_DEPTH_161616:
2293         default:
2294                 /* These color depths are currently not supported */
2295                 return false;
2296         }
2297
2298         if (get_timing_pixel_clock_100hz(timing) > (dongle_caps->dp_hdmi_max_pixel_clk_in_khz * 10))
2299                 return false;
2300
2301         return true;
2302 }
2303
2304 enum dc_status dc_link_validate_mode_timing(
2305                 const struct dc_stream_state *stream,
2306                 struct dc_link *link,
2307                 const struct dc_crtc_timing *timing)
2308 {
2309         uint32_t max_pix_clk = stream->link->dongle_max_pix_clk * 10;
2310         struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
2311
2312         /* A hack to avoid failing any modes for EDID override feature on
2313          * topology change such as lower quality cable for DP or different dongle
2314          */
2315         if (link->remote_sinks[0])
2316                 return DC_OK;
2317
2318         /* Passive Dongle */
2319         if (max_pix_clk != 0 && get_timing_pixel_clock_100hz(timing) > max_pix_clk)
2320                 return DC_EXCEED_DONGLE_CAP;
2321
2322         /* Active Dongle*/
2323         if (!dp_active_dongle_validate_timing(timing, dpcd_caps))
2324                 return DC_EXCEED_DONGLE_CAP;
2325
2326         switch (stream->signal) {
2327         case SIGNAL_TYPE_EDP:
2328         case SIGNAL_TYPE_DISPLAY_PORT:
2329                 if (!dp_validate_mode_timing(
2330                                 link,
2331                                 timing))
2332                         return DC_NO_DP_LINK_BANDWIDTH;
2333                 break;
2334
2335         default:
2336                 break;
2337         }
2338
2339         return DC_OK;
2340 }
2341
2342 int dc_link_get_backlight_level(const struct dc_link *link)
2343 {
2344         struct abm *abm = link->ctx->dc->res_pool->abm;
2345
2346         if (abm == NULL || abm->funcs->get_current_backlight == NULL)
2347                 return DC_ERROR_UNEXPECTED;
2348
2349         return (int) abm->funcs->get_current_backlight(abm);
2350 }
2351
2352 bool dc_link_set_backlight_level(const struct dc_link *link,
2353                 uint32_t backlight_pwm_u16_16,
2354                 uint32_t frame_ramp)
2355 {
2356         struct dc  *dc = link->ctx->dc;
2357         struct abm *abm = dc->res_pool->abm;
2358         struct dmcu *dmcu = dc->res_pool->dmcu;
2359         unsigned int controller_id = 0;
2360         bool use_smooth_brightness = true;
2361         int i;
2362         DC_LOGGER_INIT(link->ctx->logger);
2363
2364         if ((dmcu == NULL) ||
2365                 (abm == NULL) ||
2366                 (abm->funcs->set_backlight_level_pwm == NULL))
2367                 return false;
2368
2369         use_smooth_brightness = dmcu->funcs->is_dmcu_initialized(dmcu);
2370
2371         DC_LOG_BACKLIGHT("New Backlight level: %d (0x%X)\n",
2372                         backlight_pwm_u16_16, backlight_pwm_u16_16);
2373
2374         if (dc_is_embedded_signal(link->connector_signal)) {
2375                 for (i = 0; i < MAX_PIPES; i++) {
2376                         if (dc->current_state->res_ctx.pipe_ctx[i].stream) {
2377                                 if (dc->current_state->res_ctx.
2378                                                 pipe_ctx[i].stream->link
2379                                                 == link) {
2380                                         /* DMCU -1 for all controller id values,
2381                                          * therefore +1 here
2382                                          */
2383                                         controller_id =
2384                                                 dc->current_state->
2385                                                 res_ctx.pipe_ctx[i].stream_res.tg->inst +
2386                                                 1;
2387
2388                                         /* Disable brightness ramping when the display is blanked
2389                                          * as it can hang the DMCU
2390                                          */
2391                                         if (dc->current_state->res_ctx.pipe_ctx[i].plane_state == NULL)
2392                                                 frame_ramp = 0;
2393                                 }
2394                         }
2395                 }
2396                 abm->funcs->set_backlight_level_pwm(
2397                                 abm,
2398                                 backlight_pwm_u16_16,
2399                                 frame_ramp,
2400                                 controller_id,
2401                                 use_smooth_brightness);
2402         }
2403
2404         return true;
2405 }
2406
2407 bool dc_link_set_abm_disable(const struct dc_link *link)
2408 {
2409         struct dc  *dc = link->ctx->dc;
2410         struct abm *abm = dc->res_pool->abm;
2411
2412         if ((abm == NULL) || (abm->funcs->set_backlight_level_pwm == NULL))
2413                 return false;
2414
2415         abm->funcs->set_abm_immediate_disable(abm);
2416
2417         return true;
2418 }
2419
2420 bool dc_link_set_psr_allow_active(struct dc_link *link, bool allow_active, bool wait)
2421 {
2422         struct dc  *dc = link->ctx->dc;
2423         struct dmcu *dmcu = dc->res_pool->dmcu;
2424         struct dmub_psr *psr = dc->res_pool->psr;
2425
2426         if (psr != NULL && link->psr_feature_enabled)
2427                 psr->funcs->psr_enable(psr, allow_active);
2428         else if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu)) && link->psr_feature_enabled)
2429                 dmcu->funcs->set_psr_enable(dmcu, allow_active, wait);
2430
2431         link->psr_allow_active = allow_active;
2432
2433         return true;
2434 }
2435
2436 bool dc_link_get_psr_state(const struct dc_link *link, uint32_t *psr_state)
2437 {
2438         struct dc  *dc = link->ctx->dc;
2439         struct dmcu *dmcu = dc->res_pool->dmcu;
2440         struct dmub_psr *psr = dc->res_pool->psr;
2441
2442         if (psr != NULL && link->psr_feature_enabled)
2443                 psr->funcs->psr_get_state(psr, psr_state);
2444         else if (dmcu != NULL && link->psr_feature_enabled)
2445                 dmcu->funcs->get_psr_state(dmcu, psr_state);
2446
2447         return true;
2448 }
2449
2450 static inline enum physical_phy_id
2451 transmitter_to_phy_id(enum transmitter transmitter_value)
2452 {
2453         switch (transmitter_value) {
2454         case TRANSMITTER_UNIPHY_A:
2455                 return PHYLD_0;
2456         case TRANSMITTER_UNIPHY_B:
2457                 return PHYLD_1;
2458         case TRANSMITTER_UNIPHY_C:
2459                 return PHYLD_2;
2460         case TRANSMITTER_UNIPHY_D:
2461                 return PHYLD_3;
2462         case TRANSMITTER_UNIPHY_E:
2463                 return PHYLD_4;
2464         case TRANSMITTER_UNIPHY_F:
2465                 return PHYLD_5;
2466         case TRANSMITTER_NUTMEG_CRT:
2467                 return PHYLD_6;
2468         case TRANSMITTER_TRAVIS_CRT:
2469                 return PHYLD_7;
2470         case TRANSMITTER_TRAVIS_LCD:
2471                 return PHYLD_8;
2472         case TRANSMITTER_UNIPHY_G:
2473                 return PHYLD_9;
2474         case TRANSMITTER_COUNT:
2475                 return PHYLD_COUNT;
2476         case TRANSMITTER_UNKNOWN:
2477                 return PHYLD_UNKNOWN;
2478         default:
2479                 WARN_ONCE(1, "Unknown transmitter value %d\n",
2480                           transmitter_value);
2481                 return PHYLD_UNKNOWN;
2482         }
2483 }
2484
2485 bool dc_link_setup_psr(struct dc_link *link,
2486                 const struct dc_stream_state *stream, struct psr_config *psr_config,
2487                 struct psr_context *psr_context)
2488 {
2489         struct dc *dc;
2490         struct dmcu *dmcu;
2491         struct dmub_psr *psr;
2492         int i;
2493         /* updateSinkPsrDpcdConfig*/
2494         union dpcd_psr_configuration psr_configuration;
2495
2496         psr_context->controllerId = CONTROLLER_ID_UNDEFINED;
2497
2498         if (!link)
2499                 return false;
2500
2501         dc = link->ctx->dc;
2502         dmcu = dc->res_pool->dmcu;
2503         psr = dc->res_pool->psr;
2504
2505         if (!dmcu && !psr)
2506                 return false;
2507
2508
2509         memset(&psr_configuration, 0, sizeof(psr_configuration));
2510
2511         psr_configuration.bits.ENABLE                    = 1;
2512         psr_configuration.bits.CRC_VERIFICATION          = 1;
2513         psr_configuration.bits.FRAME_CAPTURE_INDICATION  =
2514                         psr_config->psr_frame_capture_indication_req;
2515
2516         /* Check for PSR v2*/
2517         if (psr_config->psr_version == 0x2) {
2518                 /* For PSR v2 selective update.
2519                  * Indicates whether sink should start capturing
2520                  * immediately following active scan line,
2521                  * or starting with the 2nd active scan line.
2522                  */
2523                 psr_configuration.bits.LINE_CAPTURE_INDICATION = 0;
2524                 /*For PSR v2, determines whether Sink should generate
2525                  * IRQ_HPD when CRC mismatch is detected.
2526                  */
2527                 psr_configuration.bits.IRQ_HPD_WITH_CRC_ERROR    = 1;
2528         }
2529
2530         dm_helpers_dp_write_dpcd(
2531                 link->ctx,
2532                 link,
2533                 368,
2534                 &psr_configuration.raw,
2535                 sizeof(psr_configuration.raw));
2536
2537         psr_context->channel = link->ddc->ddc_pin->hw_info.ddc_channel;
2538         psr_context->transmitterId = link->link_enc->transmitter;
2539         psr_context->engineId = link->link_enc->preferred_engine;
2540
2541         for (i = 0; i < MAX_PIPES; i++) {
2542                 if (dc->current_state->res_ctx.pipe_ctx[i].stream
2543                                 == stream) {
2544                         /* dmcu -1 for all controller id values,
2545                          * therefore +1 here
2546                          */
2547                         psr_context->controllerId =
2548                                 dc->current_state->res_ctx.
2549                                 pipe_ctx[i].stream_res.tg->inst + 1;
2550                         break;
2551                 }
2552         }
2553
2554         /* Hardcoded for now.  Can be Pcie or Uniphy (or Unknown)*/
2555         psr_context->phyType = PHY_TYPE_UNIPHY;
2556         /*PhyId is associated with the transmitter id*/
2557         psr_context->smuPhyId =
2558                 transmitter_to_phy_id(link->link_enc->transmitter);
2559
2560         psr_context->crtcTimingVerticalTotal = stream->timing.v_total;
2561         psr_context->vsync_rate_hz = div64_u64(div64_u64((stream->
2562                                         timing.pix_clk_100hz * 100),
2563                                         stream->timing.v_total),
2564                                         stream->timing.h_total);
2565
2566         psr_context->psrSupportedDisplayConfig = true;
2567         psr_context->psrExitLinkTrainingRequired =
2568                 psr_config->psr_exit_link_training_required;
2569         psr_context->sdpTransmitLineNumDeadline =
2570                 psr_config->psr_sdp_transmit_line_num_deadline;
2571         psr_context->psrFrameCaptureIndicationReq =
2572                 psr_config->psr_frame_capture_indication_req;
2573
2574         psr_context->skipPsrWaitForPllLock = 0; /* only = 1 in KV */
2575
2576         psr_context->numberOfControllers =
2577                         link->dc->res_pool->timing_generator_count;
2578
2579         psr_context->rfb_update_auto_en = true;
2580
2581         /* 2 frames before enter PSR. */
2582         psr_context->timehyst_frames = 2;
2583         /* half a frame
2584          * (units in 100 lines, i.e. a value of 1 represents 100 lines)
2585          */
2586         psr_context->hyst_lines = stream->timing.v_total / 2 / 100;
2587         psr_context->aux_repeats = 10;
2588
2589         psr_context->psr_level.u32all = 0;
2590
2591 #if defined(CONFIG_DRM_AMD_DC_DCN)
2592         /*skip power down the single pipe since it blocks the cstate*/
2593         if (ASICREV_IS_RAVEN(link->ctx->asic_id.hw_internal_rev))
2594                 psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true;
2595 #endif
2596
2597         /* SMU will perform additional powerdown sequence.
2598          * For unsupported ASICs, set psr_level flag to skip PSR
2599          *  static screen notification to SMU.
2600          *  (Always set for DAL2, did not check ASIC)
2601          */
2602         psr_context->allow_smu_optimizations = psr_config->allow_smu_optimizations;
2603
2604         /* Complete PSR entry before aborting to prevent intermittent
2605          * freezes on certain eDPs
2606          */
2607         psr_context->psr_level.bits.DISABLE_PSR_ENTRY_ABORT = 1;
2608
2609         /* Controls additional delay after remote frame capture before
2610          * continuing power down, default = 0
2611          */
2612         psr_context->frame_delay = 0;
2613
2614         if (psr)
2615                 link->psr_feature_enabled = psr->funcs->psr_copy_settings(psr, link, psr_context);
2616         else
2617                 link->psr_feature_enabled = dmcu->funcs->setup_psr(dmcu, link, psr_context);
2618
2619         /* psr_enabled == 0 indicates setup_psr did not succeed, but this
2620          * should not happen since firmware should be running at this point
2621          */
2622         if (link->psr_feature_enabled == 0)
2623                 ASSERT(0);
2624
2625         return true;
2626
2627 }
2628
2629 const struct dc_link_status *dc_link_get_status(const struct dc_link *link)
2630 {
2631         return &link->link_status;
2632 }
2633
2634 void core_link_resume(struct dc_link *link)
2635 {
2636         if (link->connector_signal != SIGNAL_TYPE_VIRTUAL)
2637                 program_hpd_filter(link);
2638 }
2639
2640 static struct fixed31_32 get_pbn_per_slot(struct dc_stream_state *stream)
2641 {
2642         struct fixed31_32 mbytes_per_sec;
2643         uint32_t link_rate_in_mbytes_per_sec = dc_link_bandwidth_kbps(stream->link,
2644                         &stream->link->cur_link_settings);
2645         link_rate_in_mbytes_per_sec /= 8000; /* Kbits to MBytes */
2646
2647         mbytes_per_sec = dc_fixpt_from_int(link_rate_in_mbytes_per_sec);
2648
2649         return dc_fixpt_div_int(mbytes_per_sec, 54);
2650 }
2651
2652 static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx)
2653 {
2654         uint64_t kbps;
2655         struct fixed31_32 peak_kbps;
2656         uint32_t numerator;
2657         uint32_t denominator;
2658
2659         kbps = dc_bandwidth_in_kbps_from_timing(&pipe_ctx->stream->timing);
2660
2661         /*
2662          * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
2663          * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on
2664          * common multiplier to render an integer PBN for all link rate/lane
2665          * counts combinations
2666          * calculate
2667          * peak_kbps *= (1006/1000)
2668          * peak_kbps *= (64/54)
2669          * peak_kbps *= 8    convert to bytes
2670          */
2671
2672         numerator = 64 * PEAK_FACTOR_X1000;
2673         denominator = 54 * 8 * 1000 * 1000;
2674         kbps *= numerator;
2675         peak_kbps = dc_fixpt_from_fraction(kbps, denominator);
2676
2677         return peak_kbps;
2678 }
2679
2680 static void update_mst_stream_alloc_table(
2681         struct dc_link *link,
2682         struct stream_encoder *stream_enc,
2683         const struct dp_mst_stream_allocation_table *proposed_table)
2684 {
2685         struct link_mst_stream_allocation work_table[MAX_CONTROLLER_NUM] = {
2686                         { 0 } };
2687         struct link_mst_stream_allocation *dc_alloc;
2688
2689         int i;
2690         int j;
2691
2692         /* if DRM proposed_table has more than one new payload */
2693         ASSERT(proposed_table->stream_count -
2694                         link->mst_stream_alloc_table.stream_count < 2);
2695
2696         /* copy proposed_table to link, add stream encoder */
2697         for (i = 0; i < proposed_table->stream_count; i++) {
2698
2699                 for (j = 0; j < link->mst_stream_alloc_table.stream_count; j++) {
2700                         dc_alloc =
2701                         &link->mst_stream_alloc_table.stream_allocations[j];
2702
2703                         if (dc_alloc->vcp_id ==
2704                                 proposed_table->stream_allocations[i].vcp_id) {
2705
2706                                 work_table[i] = *dc_alloc;
2707                                 break; /* exit j loop */
2708                         }
2709                 }
2710
2711                 /* new vcp_id */
2712                 if (j == link->mst_stream_alloc_table.stream_count) {
2713                         work_table[i].vcp_id =
2714                                 proposed_table->stream_allocations[i].vcp_id;
2715                         work_table[i].slot_count =
2716                                 proposed_table->stream_allocations[i].slot_count;
2717                         work_table[i].stream_enc = stream_enc;
2718                 }
2719         }
2720
2721         /* update link->mst_stream_alloc_table with work_table */
2722         link->mst_stream_alloc_table.stream_count =
2723                         proposed_table->stream_count;
2724         for (i = 0; i < MAX_CONTROLLER_NUM; i++)
2725                 link->mst_stream_alloc_table.stream_allocations[i] =
2726                                 work_table[i];
2727 }
2728
2729 /* convert link_mst_stream_alloc_table to dm dp_mst_stream_alloc_table
2730  * because stream_encoder is not exposed to dm
2731  */
2732 enum dc_status dc_link_allocate_mst_payload(struct pipe_ctx *pipe_ctx)
2733 {
2734         struct dc_stream_state *stream = pipe_ctx->stream;
2735         struct dc_link *link = stream->link;
2736         struct link_encoder *link_encoder = link->link_enc;
2737         struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
2738         struct dp_mst_stream_allocation_table proposed_table = {0};
2739         struct fixed31_32 avg_time_slots_per_mtp;
2740         struct fixed31_32 pbn;
2741         struct fixed31_32 pbn_per_slot;
2742         uint8_t i;
2743         enum act_return_status ret;
2744         DC_LOGGER_INIT(link->ctx->logger);
2745
2746         /* enable_link_dp_mst already check link->enabled_stream_count
2747          * and stream is in link->stream[]. This is called during set mode,
2748          * stream_enc is available.
2749          */
2750
2751         /* get calculate VC payload for stream: stream_alloc */
2752         if (dm_helpers_dp_mst_write_payload_allocation_table(
2753                 stream->ctx,
2754                 stream,
2755                 &proposed_table,
2756                 true)) {
2757                 update_mst_stream_alloc_table(
2758                                         link, pipe_ctx->stream_res.stream_enc, &proposed_table);
2759         }
2760         else
2761                 DC_LOG_WARNING("Failed to update"
2762                                 "MST allocation table for"
2763                                 "pipe idx:%d\n",
2764                                 pipe_ctx->pipe_idx);
2765
2766         DC_LOG_MST("%s  "
2767                         "stream_count: %d: \n ",
2768                         __func__,
2769                         link->mst_stream_alloc_table.stream_count);
2770
2771         for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
2772                 DC_LOG_MST("stream_enc[%d]: %p      "
2773                 "stream[%d].vcp_id: %d      "
2774                 "stream[%d].slot_count: %d\n",
2775                 i,
2776                 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
2777                 i,
2778                 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
2779                 i,
2780                 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
2781         }
2782
2783         ASSERT(proposed_table.stream_count > 0);
2784
2785         /* program DP source TX for payload */
2786         link_encoder->funcs->update_mst_stream_allocation_table(
2787                 link_encoder,
2788                 &link->mst_stream_alloc_table);
2789
2790         /* send down message */
2791         ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger(
2792                         stream->ctx,
2793                         stream);
2794
2795         if (ret != ACT_LINK_LOST) {
2796                 dm_helpers_dp_mst_send_payload_allocation(
2797                                 stream->ctx,
2798                                 stream,
2799                                 true);
2800         }
2801
2802         /* slot X.Y for only current stream */
2803         pbn_per_slot = get_pbn_per_slot(stream);
2804         pbn = get_pbn_from_timing(pipe_ctx);
2805         avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot);
2806
2807         stream_encoder->funcs->set_mst_bandwidth(
2808                 stream_encoder,
2809                 avg_time_slots_per_mtp);
2810
2811         return DC_OK;
2812
2813 }
2814
2815 static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx)
2816 {
2817         struct dc_stream_state *stream = pipe_ctx->stream;
2818         struct dc_link *link = stream->link;
2819         struct link_encoder *link_encoder = link->link_enc;
2820         struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
2821         struct dp_mst_stream_allocation_table proposed_table = {0};
2822         struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0);
2823         uint8_t i;
2824         bool mst_mode = (link->type == dc_connection_mst_branch);
2825         DC_LOGGER_INIT(link->ctx->logger);
2826
2827         /* deallocate_mst_payload is called before disable link. When mode or
2828          * disable/enable monitor, new stream is created which is not in link
2829          * stream[] yet. For this, payload is not allocated yet, so de-alloc
2830          * should not done. For new mode set, map_resources will get engine
2831          * for new stream, so stream_enc->id should be validated until here.
2832          */
2833
2834         /* slot X.Y */
2835         stream_encoder->funcs->set_mst_bandwidth(
2836                 stream_encoder,
2837                 avg_time_slots_per_mtp);
2838
2839         /* TODO: which component is responsible for remove payload table? */
2840         if (mst_mode) {
2841                 if (dm_helpers_dp_mst_write_payload_allocation_table(
2842                                 stream->ctx,
2843                                 stream,
2844                                 &proposed_table,
2845                                 false)) {
2846
2847                         update_mst_stream_alloc_table(
2848                                 link, pipe_ctx->stream_res.stream_enc, &proposed_table);
2849                 }
2850                 else {
2851                                 DC_LOG_WARNING("Failed to update"
2852                                                 "MST allocation table for"
2853                                                 "pipe idx:%d\n",
2854                                                 pipe_ctx->pipe_idx);
2855                 }
2856         }
2857
2858         DC_LOG_MST("%s"
2859                         "stream_count: %d: ",
2860                         __func__,
2861                         link->mst_stream_alloc_table.stream_count);
2862
2863         for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
2864                 DC_LOG_MST("stream_enc[%d]: %p      "
2865                 "stream[%d].vcp_id: %d      "
2866                 "stream[%d].slot_count: %d\n",
2867                 i,
2868                 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
2869                 i,
2870                 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
2871                 i,
2872                 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
2873         }
2874
2875         link_encoder->funcs->update_mst_stream_allocation_table(
2876                 link_encoder,
2877                 &link->mst_stream_alloc_table);
2878
2879         if (mst_mode) {
2880                 dm_helpers_dp_mst_poll_for_allocation_change_trigger(
2881                         stream->ctx,
2882                         stream);
2883
2884                 dm_helpers_dp_mst_send_payload_allocation(
2885                         stream->ctx,
2886                         stream,
2887                         false);
2888         }
2889
2890         return DC_OK;
2891 }
2892
2893 enum dc_status dc_link_reallocate_mst_payload(struct dc_link *link)
2894 {
2895         int i;
2896         struct pipe_ctx *pipe_ctx;
2897
2898         // Clear all of MST payload then reallocate
2899         for (i = 0; i < MAX_PIPES; i++) {
2900                 pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
2901
2902                 /* driver enable split pipe for external monitors
2903                  * we have to check pipe_ctx is split pipe or not
2904                  * If it's split pipe, driver using top pipe to
2905                  * reaallocate.
2906                  */
2907                 if (!pipe_ctx || pipe_ctx->top_pipe)
2908                         continue;
2909
2910                 if (pipe_ctx->stream && pipe_ctx->stream->link == link &&
2911                                 pipe_ctx->stream->dpms_off == false &&
2912                                 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
2913                         deallocate_mst_payload(pipe_ctx);
2914                 }
2915         }
2916
2917         for (i = 0; i < MAX_PIPES; i++) {
2918                 pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
2919
2920                 if (!pipe_ctx || pipe_ctx->top_pipe)
2921                         continue;
2922
2923                 if (pipe_ctx->stream && pipe_ctx->stream->link == link &&
2924                                 pipe_ctx->stream->dpms_off == false &&
2925                                 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
2926                         /* enable/disable PHY will clear connection between BE and FE
2927                          * need to restore it.
2928                          */
2929                         link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
2930                                                                         pipe_ctx->stream_res.stream_enc->id, true);
2931                         dc_link_allocate_mst_payload(pipe_ctx);
2932                 }
2933         }
2934
2935         return DC_OK;
2936 }
2937
2938 #if defined(CONFIG_DRM_AMD_DC_HDCP)
2939 static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off)
2940 {
2941         struct cp_psp *cp_psp = &pipe_ctx->stream->ctx->cp_psp;
2942         if (cp_psp && cp_psp->funcs.update_stream_config) {
2943                 struct cp_psp_stream_config config;
2944
2945                 memset(&config, 0, sizeof(config));
2946
2947                 config.otg_inst = (uint8_t) pipe_ctx->stream_res.tg->inst;
2948                 /*stream_enc_inst*/
2949                 config.stream_enc_inst = (uint8_t) pipe_ctx->stream_res.stream_enc->stream_enc_inst;
2950                 config.link_enc_inst = pipe_ctx->stream->link->link_enc_hw_inst;
2951                 config.dpms_off = dpms_off;
2952                 config.dm_stream_ctx = pipe_ctx->stream->dm_stream_context;
2953                 config.mst_supported = (pipe_ctx->stream->signal ==
2954                                 SIGNAL_TYPE_DISPLAY_PORT_MST);
2955                 cp_psp->funcs.update_stream_config(cp_psp->handle, &config);
2956         }
2957 }
2958 #endif
2959
2960 void core_link_enable_stream(
2961                 struct dc_state *state,
2962                 struct pipe_ctx *pipe_ctx)
2963 {
2964         struct dc *dc = pipe_ctx->stream->ctx->dc;
2965         struct dc_stream_state *stream = pipe_ctx->stream;
2966         enum dc_status status;
2967         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
2968
2969         if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) &&
2970                         dc_is_virtual_signal(pipe_ctx->stream->signal))
2971                 return;
2972
2973         if (!dc_is_virtual_signal(pipe_ctx->stream->signal)) {
2974                 stream->link->link_enc->funcs->setup(
2975                         stream->link->link_enc,
2976                         pipe_ctx->stream->signal);
2977                 pipe_ctx->stream_res.stream_enc->funcs->setup_stereo_sync(
2978                         pipe_ctx->stream_res.stream_enc,
2979                         pipe_ctx->stream_res.tg->inst,
2980                         stream->timing.timing_3d_format != TIMING_3D_FORMAT_NONE);
2981         }
2982
2983         if (dc_is_dp_signal(pipe_ctx->stream->signal))
2984                 pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute(
2985                         pipe_ctx->stream_res.stream_enc,
2986                         &stream->timing,
2987                         stream->output_color_space,
2988                         stream->use_vsc_sdp_for_colorimetry,
2989                         stream->link->dpcd_caps.dprx_feature.bits.SST_SPLIT_SDP_CAP);
2990
2991         if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal))
2992                 pipe_ctx->stream_res.stream_enc->funcs->hdmi_set_stream_attribute(
2993                         pipe_ctx->stream_res.stream_enc,
2994                         &stream->timing,
2995                         stream->phy_pix_clk,
2996                         pipe_ctx->stream_res.audio != NULL);
2997
2998         pipe_ctx->stream->link->link_state_valid = true;
2999
3000         if (dc_is_dvi_signal(pipe_ctx->stream->signal))
3001                 pipe_ctx->stream_res.stream_enc->funcs->dvi_set_stream_attribute(
3002                         pipe_ctx->stream_res.stream_enc,
3003                         &stream->timing,
3004                         (pipe_ctx->stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) ?
3005                         true : false);
3006
3007         if (dc_is_lvds_signal(pipe_ctx->stream->signal))
3008                 pipe_ctx->stream_res.stream_enc->funcs->lvds_set_stream_attribute(
3009                         pipe_ctx->stream_res.stream_enc,
3010                         &stream->timing);
3011
3012         if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
3013                 bool apply_edp_fast_boot_optimization =
3014                         pipe_ctx->stream->apply_edp_fast_boot_optimization;
3015
3016                 pipe_ctx->stream->apply_edp_fast_boot_optimization = false;
3017
3018                 resource_build_info_frame(pipe_ctx);
3019                 dc->hwss.update_info_frame(pipe_ctx);
3020
3021                 /* Do not touch link on seamless boot optimization. */
3022                 if (pipe_ctx->stream->apply_seamless_boot_optimization) {
3023                         pipe_ctx->stream->dpms_off = false;
3024 #if defined(CONFIG_DRM_AMD_DC_HDCP)
3025                         update_psp_stream_config(pipe_ctx, false);
3026 #endif
3027                         return;
3028                 }
3029
3030                 /* eDP lit up by bios already, no need to enable again. */
3031                 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&
3032                                         apply_edp_fast_boot_optimization) {
3033                         pipe_ctx->stream->dpms_off = false;
3034 #if defined(CONFIG_DRM_AMD_DC_HDCP)
3035                         update_psp_stream_config(pipe_ctx, false);
3036 #endif
3037                         return;
3038                 }
3039
3040                 if (pipe_ctx->stream->dpms_off)
3041                         return;
3042
3043                 status = enable_link(state, pipe_ctx);
3044
3045                 if (status != DC_OK) {
3046                         DC_LOG_WARNING("enabling link %u failed: %d\n",
3047                         pipe_ctx->stream->link->link_index,
3048                         status);
3049
3050                         /* Abort stream enable *unless* the failure was due to
3051                          * DP link training - some DP monitors will recover and
3052                          * show the stream anyway. But MST displays can't proceed
3053                          * without link training.
3054                          */
3055                         if (status != DC_FAIL_DP_LINK_TRAINING ||
3056                                         pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
3057                                 BREAK_TO_DEBUGGER();
3058                                 return;
3059                         }
3060                 }
3061
3062                 dc->hwss.enable_audio_stream(pipe_ctx);
3063
3064                 /* turn off otg test pattern if enable */
3065                 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
3066                         pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
3067                                         CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
3068                                         COLOR_DEPTH_UNDEFINED);
3069
3070                 if (pipe_ctx->stream->timing.flags.DSC) {
3071                         if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
3072                                         dc_is_virtual_signal(pipe_ctx->stream->signal))
3073                                 dp_set_dsc_enable(pipe_ctx, true);
3074                 }
3075                 dc->hwss.enable_stream(pipe_ctx);
3076
3077                 /* Set DPS PPS SDP (AKA "info frames") */
3078                 if (pipe_ctx->stream->timing.flags.DSC) {
3079                         if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
3080                                         dc_is_virtual_signal(pipe_ctx->stream->signal))
3081                                 dp_set_dsc_pps_sdp(pipe_ctx, true);
3082                 }
3083
3084                 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
3085                         dc_link_allocate_mst_payload(pipe_ctx);
3086
3087                 dc->hwss.unblank_stream(pipe_ctx,
3088                         &pipe_ctx->stream->link->cur_link_settings);
3089
3090                 if (stream->sink_patches.delay_ignore_msa > 0)
3091                         msleep(stream->sink_patches.delay_ignore_msa);
3092
3093                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
3094                         enable_stream_features(pipe_ctx);
3095 #if defined(CONFIG_DRM_AMD_DC_HDCP)
3096                 update_psp_stream_config(pipe_ctx, false);
3097 #endif
3098         } else { // if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
3099                 if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
3100                                 dc_is_virtual_signal(pipe_ctx->stream->signal))
3101                         dp_set_dsc_enable(pipe_ctx, true);
3102
3103         }
3104 }
3105
3106 void core_link_disable_stream(struct pipe_ctx *pipe_ctx)
3107 {
3108         struct dc  *dc = pipe_ctx->stream->ctx->dc;
3109         struct dc_stream_state *stream = pipe_ctx->stream;
3110         struct dc_link *link = stream->sink->link;
3111
3112         if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) &&
3113                         dc_is_virtual_signal(pipe_ctx->stream->signal))
3114                 return;
3115
3116 #if defined(CONFIG_DRM_AMD_DC_HDCP)
3117         update_psp_stream_config(pipe_ctx, true);
3118 #endif
3119
3120         dc->hwss.blank_stream(pipe_ctx);
3121
3122         if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
3123                 deallocate_mst_payload(pipe_ctx);
3124
3125         if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
3126                 struct ext_hdmi_settings settings = {0};
3127                 enum engine_id eng_id = pipe_ctx->stream_res.stream_enc->id;
3128
3129                 unsigned short masked_chip_caps = link->chip_caps &
3130                                 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
3131                 //Need to inform that sink is going to use legacy HDMI mode.
3132                 dal_ddc_service_write_scdc_data(
3133                         link->ddc,
3134                         165000,//vbios only handles 165Mhz.
3135                         false);
3136                 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {
3137                         /* DP159, Retimer settings */
3138                         if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings))
3139                                 write_i2c_retimer_setting(pipe_ctx,
3140                                                 false, false, &settings);
3141                         else
3142                                 write_i2c_default_retimer_setting(pipe_ctx,
3143                                                 false, false);
3144                 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {
3145                         /* PI3EQX1204, Redriver settings */
3146                         write_i2c_redriver_setting(pipe_ctx, false);
3147                 }
3148         }
3149         dc->hwss.disable_stream(pipe_ctx);
3150
3151         disable_link(pipe_ctx->stream->link, pipe_ctx->stream->signal);
3152         if (pipe_ctx->stream->timing.flags.DSC) {
3153                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
3154                         dp_set_dsc_enable(pipe_ctx, false);
3155         }
3156 }
3157
3158 void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
3159 {
3160         struct dc  *dc = pipe_ctx->stream->ctx->dc;
3161
3162         if (!dc_is_hdmi_signal(pipe_ctx->stream->signal))
3163                 return;
3164
3165         dc->hwss.set_avmute(pipe_ctx, enable);
3166 }
3167
3168 /**
3169  *****************************************************************************
3170  *  Function: dc_link_enable_hpd_filter
3171  *
3172  *  @brief
3173  *     If enable is true, programs HPD filter on associated HPD line using
3174  *     delay_on_disconnect/delay_on_connect values dependent on
3175  *     link->connector_signal
3176  *
3177  *     If enable is false, programs HPD filter on associated HPD line with no
3178  *     delays on connect or disconnect
3179  *
3180  *  @param [in] link: pointer to the dc link
3181  *  @param [in] enable: boolean specifying whether to enable hbd
3182  *****************************************************************************
3183  */
3184 void dc_link_enable_hpd_filter(struct dc_link *link, bool enable)
3185 {
3186         struct gpio *hpd;
3187
3188         if (enable) {
3189                 link->is_hpd_filter_disabled = false;
3190                 program_hpd_filter(link);
3191         } else {
3192                 link->is_hpd_filter_disabled = true;
3193                 /* Obtain HPD handle */
3194                 hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
3195
3196                 if (!hpd)
3197                         return;
3198
3199                 /* Setup HPD filtering */
3200                 if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) {
3201                         struct gpio_hpd_config config;
3202
3203                         config.delay_on_connect = 0;
3204                         config.delay_on_disconnect = 0;
3205
3206                         dal_irq_setup_hpd_filter(hpd, &config);
3207
3208                         dal_gpio_close(hpd);
3209                 } else {
3210                         ASSERT_CRITICAL(false);
3211                 }
3212                 /* Release HPD handle */
3213                 dal_gpio_destroy_irq(&hpd);
3214         }
3215 }
3216
3217 uint32_t dc_bandwidth_in_kbps_from_timing(
3218         const struct dc_crtc_timing *timing)
3219 {
3220         uint32_t bits_per_channel = 0;
3221         uint32_t kbps;
3222
3223         if (timing->flags.DSC) {
3224                 kbps = (timing->pix_clk_100hz * timing->dsc_cfg.bits_per_pixel);
3225                 kbps = kbps / 160 + ((kbps % 160) ? 1 : 0);
3226                 return kbps;
3227         }
3228
3229         switch (timing->display_color_depth) {
3230         case COLOR_DEPTH_666:
3231                 bits_per_channel = 6;
3232                 break;
3233         case COLOR_DEPTH_888:
3234                 bits_per_channel = 8;
3235                 break;
3236         case COLOR_DEPTH_101010:
3237                 bits_per_channel = 10;
3238                 break;
3239         case COLOR_DEPTH_121212:
3240                 bits_per_channel = 12;
3241                 break;
3242         case COLOR_DEPTH_141414:
3243                 bits_per_channel = 14;
3244                 break;
3245         case COLOR_DEPTH_161616:
3246                 bits_per_channel = 16;
3247                 break;
3248         default:
3249                 break;
3250         }
3251
3252         ASSERT(bits_per_channel != 0);
3253
3254         kbps = timing->pix_clk_100hz / 10;
3255         kbps *= bits_per_channel;
3256
3257         if (timing->flags.Y_ONLY != 1) {
3258                 /*Only YOnly make reduce bandwidth by 1/3 compares to RGB*/
3259                 kbps *= 3;
3260                 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
3261                         kbps /= 2;
3262                 else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
3263                         kbps = kbps * 2 / 3;
3264         }
3265
3266         return kbps;
3267
3268 }
3269
3270 void dc_link_set_drive_settings(struct dc *dc,
3271                                 struct link_training_settings *lt_settings,
3272                                 const struct dc_link *link)
3273 {
3274
3275         int i;
3276
3277         for (i = 0; i < dc->link_count; i++) {
3278                 if (dc->links[i] == link)
3279                         break;
3280         }
3281
3282         if (i >= dc->link_count)
3283                 ASSERT_CRITICAL(false);
3284
3285         dc_link_dp_set_drive_settings(dc->links[i], lt_settings);
3286 }
3287
3288 void dc_link_perform_link_training(struct dc *dc,
3289                                    struct dc_link_settings *link_setting,
3290                                    bool skip_video_pattern)
3291 {
3292         int i;
3293
3294         for (i = 0; i < dc->link_count; i++)
3295                 dc_link_dp_perform_link_training(
3296                         dc->links[i],
3297                         link_setting,
3298                         skip_video_pattern);
3299 }
3300
3301 void dc_link_set_preferred_link_settings(struct dc *dc,
3302                                          struct dc_link_settings *link_setting,
3303                                          struct dc_link *link)
3304 {
3305         int i;
3306         struct pipe_ctx *pipe;
3307         struct dc_stream_state *link_stream;
3308         struct dc_link_settings store_settings = *link_setting;
3309
3310         link->preferred_link_setting = store_settings;
3311
3312         /* Retrain with preferred link settings only relevant for
3313          * DP signal type
3314          * Check for non-DP signal or if passive dongle present
3315          */
3316         if (!dc_is_dp_signal(link->connector_signal) ||
3317                 link->dongle_max_pix_clk > 0)
3318                 return;
3319
3320         for (i = 0; i < MAX_PIPES; i++) {
3321                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
3322                 if (pipe->stream && pipe->stream->link) {
3323                         if (pipe->stream->link == link) {
3324                                 link_stream = pipe->stream;
3325                                 break;
3326                         }
3327                 }
3328         }
3329
3330         /* Stream not found */
3331         if (i == MAX_PIPES)
3332                 return;
3333
3334         /* Cannot retrain link if backend is off */
3335         if (link_stream->dpms_off)
3336                 return;
3337
3338         decide_link_settings(link_stream, &store_settings);
3339
3340         if ((store_settings.lane_count != LANE_COUNT_UNKNOWN) &&
3341                 (store_settings.link_rate != LINK_RATE_UNKNOWN))
3342                 dp_retrain_link_dp_test(link, &store_settings, false);
3343 }
3344
3345 void dc_link_set_preferred_training_settings(struct dc *dc,
3346                                                  struct dc_link_settings *link_setting,
3347                                                  struct dc_link_training_overrides *lt_overrides,
3348                                                  struct dc_link *link,
3349                                                  bool skip_immediate_retrain)
3350 {
3351         if (lt_overrides != NULL)
3352                 link->preferred_training_settings = *lt_overrides;
3353         else
3354                 memset(&link->preferred_training_settings, 0, sizeof(link->preferred_training_settings));
3355
3356         if (link_setting != NULL) {
3357                 link->preferred_link_setting = *link_setting;
3358         } else {
3359                 link->preferred_link_setting.lane_count = LANE_COUNT_UNKNOWN;
3360                 link->preferred_link_setting.link_rate = LINK_RATE_UNKNOWN;
3361         }
3362
3363         /* Retrain now, or wait until next stream update to apply */
3364         if (skip_immediate_retrain == false)
3365                 dc_link_set_preferred_link_settings(dc, &link->preferred_link_setting, link);
3366 }
3367
3368 void dc_link_enable_hpd(const struct dc_link *link)
3369 {
3370         dc_link_dp_enable_hpd(link);
3371 }
3372
3373 void dc_link_disable_hpd(const struct dc_link *link)
3374 {
3375         dc_link_dp_disable_hpd(link);
3376 }
3377
3378 void dc_link_set_test_pattern(struct dc_link *link,
3379                               enum dp_test_pattern test_pattern,
3380                               enum dp_test_pattern_color_space test_pattern_color_space,
3381                               const struct link_training_settings *p_link_settings,
3382                               const unsigned char *p_custom_pattern,
3383                               unsigned int cust_pattern_size)
3384 {
3385         if (link != NULL)
3386                 dc_link_dp_set_test_pattern(
3387                         link,
3388                         test_pattern,
3389                         test_pattern_color_space,
3390                         p_link_settings,
3391                         p_custom_pattern,
3392                         cust_pattern_size);
3393 }
3394
3395 uint32_t dc_link_bandwidth_kbps(
3396         const struct dc_link *link,
3397         const struct dc_link_settings *link_setting)
3398 {
3399         uint32_t link_bw_kbps =
3400                 link_setting->link_rate * LINK_RATE_REF_FREQ_IN_KHZ; /* bytes per sec */
3401
3402         link_bw_kbps *= 8;   /* 8 bits per byte*/
3403         link_bw_kbps *= link_setting->lane_count;
3404
3405         if (dc_link_is_fec_supported(link) && !link->dc->debug.disable_fec) {
3406                 /* Account for FEC overhead.
3407                  * We have to do it based on caps,
3408                  * and not based on FEC being set ready,
3409                  * because FEC is set ready too late in
3410                  * the process to correctly be picked up
3411                  * by mode enumeration.
3412                  *
3413                  * There's enough zeros at the end of 'kbps'
3414                  * that make the below operation 100% precise
3415                  * for our purposes.
3416                  * 'long long' makes it work even for HDMI 2.1
3417                  * max bandwidth (and much, much bigger bandwidths
3418                  * than that, actually).
3419                  *
3420                  * NOTE: Reducing link BW by 3% may not be precise
3421                  * because it may be a stream BT that increases by 3%, and so
3422                  * 1/1.03 = 0.970873 factor should have been used instead,
3423                  * but the difference is minimal and is in a safe direction,
3424                  * which all works well around potential ambiguity of DP 1.4a spec.
3425                  */
3426                 link_bw_kbps = mul_u64_u32_shr(BIT_ULL(32) * 970LL / 1000,
3427                                                link_bw_kbps, 32);
3428         }
3429
3430         return link_bw_kbps;
3431
3432 }
3433
3434 const struct dc_link_settings *dc_link_get_link_cap(
3435                 const struct dc_link *link)
3436 {
3437         if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN &&
3438                         link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN)
3439                 return &link->preferred_link_setting;
3440         return &link->verified_link_cap;
3441 }
3442
3443 void dc_link_overwrite_extended_receiver_cap(
3444                 struct dc_link *link)
3445 {
3446         dp_overwrite_extended_receiver_cap(link);
3447 }
3448
3449 bool dc_link_is_fec_supported(const struct dc_link *link)
3450 {
3451         return (dc_is_dp_signal(link->connector_signal) &&
3452                         link->link_enc->features.fec_supported &&
3453                         link->dpcd_caps.fec_cap.bits.FEC_CAPABLE &&
3454                         !IS_FPGA_MAXIMUS_DC(link->ctx->dce_environment));
3455 }
3456