2 * Copyright 2012-15 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include <linux/slab.h>
28 #include "dm_services.h"
29 #include "atomfirmware.h"
30 #include "dm_helpers.h"
32 #include "grph_object_id.h"
33 #include "gpio_service_interface.h"
34 #include "core_status.h"
35 #include "dc_link_dp.h"
36 #include "dc_link_ddc.h"
37 #include "link_hwss.h"
40 #include "link_encoder.h"
41 #include "hw_sequencer.h"
44 #include "fixed31_32.h"
45 #include "dpcd_defs.h"
47 #include "hw/clk_mgr.h"
48 #include "dce/dmub_psr.h"
49 #include "dmub/dmub_srv.h"
50 #include "inc/hw/panel_cntl.h"
51 #include "inc/link_enc_cfg.h"
52 #include "inc/link_dpcd.h"
54 #include "dc/dcn30/dcn30_vpg.h"
56 #define DC_LOGGER_INIT(logger)
58 #define LINK_INFO(...) \
62 #define RETIMER_REDRIVER_INFO(...) \
63 DC_LOG_RETIMER_REDRIVER( \
66 /*******************************************************************************
68 ******************************************************************************/
69 #if defined(CONFIG_DRM_AMD_DC_DCN)
70 static bool add_dp_hpo_link_encoder_to_link(struct dc_link *link)
72 struct hpo_dp_link_encoder *enc = resource_get_unused_hpo_dp_link_encoder(
75 if (!link->hpo_dp_link_enc && enc) {
76 link->hpo_dp_link_enc = enc;
77 link->hpo_dp_link_enc->transmitter = link->link_enc->transmitter;
78 link->hpo_dp_link_enc->hpd_source = link->link_enc->hpd_source;
81 return (link->hpo_dp_link_enc != NULL);
84 static void remove_dp_hpo_link_encoder_from_link(struct dc_link *link)
86 if (link->hpo_dp_link_enc) {
87 link->hpo_dp_link_enc->hpd_source = HPD_SOURCEID_UNKNOWN;
88 link->hpo_dp_link_enc->transmitter = TRANSMITTER_UNKNOWN;
89 link->hpo_dp_link_enc = NULL;
94 static void dc_link_destruct(struct dc_link *link)
99 dal_gpio_destroy_irq(&link->hpd_gpio);
100 link->hpd_gpio = NULL;
104 dal_ddc_service_destroy(&link->ddc);
106 if (link->panel_cntl)
107 link->panel_cntl->funcs->destroy(&link->panel_cntl);
109 if (link->link_enc) {
110 /* Update link encoder resource tracking variables. These are used for
111 * the dynamic assignment of link encoders to streams. Virtual links
112 * are not assigned encoder resources on creation.
114 if (link->link_id.id != CONNECTOR_ID_VIRTUAL) {
115 link->dc->res_pool->link_encoders[link->eng_id - ENGINE_ID_DIGA] = NULL;
116 link->dc->res_pool->dig_link_enc_count--;
118 link->link_enc->funcs->destroy(&link->link_enc);
121 #if defined(CONFIG_DRM_AMD_DC_DCN)
122 if (link->hpo_dp_link_enc) {
123 remove_dp_hpo_link_encoder_from_link(link);
127 if (link->local_sink)
128 dc_sink_release(link->local_sink);
130 for (i = 0; i < link->sink_count; ++i)
131 dc_sink_release(link->remote_sinks[i]);
134 struct gpio *get_hpd_gpio(struct dc_bios *dcb,
135 struct graphics_object_id link_id,
136 struct gpio_service *gpio_service)
138 enum bp_result bp_result;
139 struct graphics_object_hpd_info hpd_info;
140 struct gpio_pin_info pin_info;
142 if (dcb->funcs->get_hpd_info(dcb, link_id, &hpd_info) != BP_RESULT_OK)
145 bp_result = dcb->funcs->get_gpio_pin_info(dcb,
146 hpd_info.hpd_int_gpio_uid, &pin_info);
148 if (bp_result != BP_RESULT_OK) {
149 ASSERT(bp_result == BP_RESULT_NORECORD);
153 return dal_gpio_service_create_irq(gpio_service,
159 * Function: program_hpd_filter
162 * Programs HPD filter on associated HPD line
164 * @param [in] delay_on_connect_in_ms: Connect filter timeout
165 * @param [in] delay_on_disconnect_in_ms: Disconnect filter timeout
168 * true on success, false otherwise
170 static bool program_hpd_filter(const struct dc_link *link)
174 int delay_on_connect_in_ms = 0;
175 int delay_on_disconnect_in_ms = 0;
177 if (link->is_hpd_filter_disabled)
179 /* Verify feature is supported */
180 switch (link->connector_signal) {
181 case SIGNAL_TYPE_DVI_SINGLE_LINK:
182 case SIGNAL_TYPE_DVI_DUAL_LINK:
183 case SIGNAL_TYPE_HDMI_TYPE_A:
184 /* Program hpd filter */
185 delay_on_connect_in_ms = 500;
186 delay_on_disconnect_in_ms = 100;
188 case SIGNAL_TYPE_DISPLAY_PORT:
189 case SIGNAL_TYPE_DISPLAY_PORT_MST:
190 /* Program hpd filter to allow DP signal to settle */
191 /* 500: not able to detect MST <-> SST switch as HPD is low for
192 * only 100ms on DELL U2413
193 * 0: some passive dongle still show aux mode instead of i2c
194 * 20-50: not enough to hide bouncing HPD with passive dongle.
195 * also see intermittent i2c read issues.
197 delay_on_connect_in_ms = 80;
198 delay_on_disconnect_in_ms = 0;
200 case SIGNAL_TYPE_LVDS:
201 case SIGNAL_TYPE_EDP:
203 /* Don't program hpd filter */
207 /* Obtain HPD handle */
208 hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
209 link->ctx->gpio_service);
214 /* Setup HPD filtering */
215 if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) {
216 struct gpio_hpd_config config;
218 config.delay_on_connect = delay_on_connect_in_ms;
219 config.delay_on_disconnect = delay_on_disconnect_in_ms;
221 dal_irq_setup_hpd_filter(hpd, &config);
227 ASSERT_CRITICAL(false);
230 /* Release HPD handle */
231 dal_gpio_destroy_irq(&hpd);
236 bool dc_link_wait_for_t12(struct dc_link *link)
238 if (link->connector_signal == SIGNAL_TYPE_EDP && link->dc->hwss.edp_wait_for_T12) {
239 link->dc->hwss.edp_wait_for_T12(link);
248 * dc_link_detect_sink() - Determine if there is a sink connected
250 * @link: pointer to the dc link
251 * @type: Returned connection type
252 * Does not detect downstream devices, such as MST sinks
253 * or display connected through active dongles
255 bool dc_link_detect_sink(struct dc_link *link, enum dc_connection_type *type)
257 uint32_t is_hpd_high = 0;
258 struct gpio *hpd_pin;
260 if (link->connector_signal == SIGNAL_TYPE_LVDS) {
261 *type = dc_connection_single;
265 if (link->connector_signal == SIGNAL_TYPE_EDP) {
266 /*in case it is not on*/
267 link->dc->hwss.edp_power_control(link, true);
268 link->dc->hwss.edp_wait_for_hpd_ready(link, true);
271 /* Link may not have physical HPD pin. */
272 if (link->ep_type != DISPLAY_ENDPOINT_PHY) {
273 if (link->hpd_status)
274 *type = dc_connection_single;
276 *type = dc_connection_none;
281 /* todo: may need to lock gpio access */
282 hpd_pin = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
283 link->ctx->gpio_service);
285 goto hpd_gpio_failure;
287 dal_gpio_open(hpd_pin, GPIO_MODE_INTERRUPT);
288 dal_gpio_get_value(hpd_pin, &is_hpd_high);
289 dal_gpio_close(hpd_pin);
290 dal_gpio_destroy_irq(&hpd_pin);
293 *type = dc_connection_single;
294 /* TODO: need to do the actual detection */
296 *type = dc_connection_none;
305 static enum ddc_transaction_type get_ddc_transaction_type(enum signal_type sink_signal)
307 enum ddc_transaction_type transaction_type = DDC_TRANSACTION_TYPE_NONE;
309 switch (sink_signal) {
310 case SIGNAL_TYPE_DVI_SINGLE_LINK:
311 case SIGNAL_TYPE_DVI_DUAL_LINK:
312 case SIGNAL_TYPE_HDMI_TYPE_A:
313 case SIGNAL_TYPE_LVDS:
314 case SIGNAL_TYPE_RGB:
315 transaction_type = DDC_TRANSACTION_TYPE_I2C;
318 case SIGNAL_TYPE_DISPLAY_PORT:
319 case SIGNAL_TYPE_EDP:
320 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
323 case SIGNAL_TYPE_DISPLAY_PORT_MST:
324 /* MST does not use I2COverAux, but there is the
325 * SPECIAL use case for "immediate dwnstrm device
326 * access" (EPR#370830).
328 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
335 return transaction_type;
338 static enum signal_type get_basic_signal_type(struct graphics_object_id encoder,
339 struct graphics_object_id downstream)
341 if (downstream.type == OBJECT_TYPE_CONNECTOR) {
342 switch (downstream.id) {
343 case CONNECTOR_ID_SINGLE_LINK_DVII:
344 switch (encoder.id) {
345 case ENCODER_ID_INTERNAL_DAC1:
346 case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
347 case ENCODER_ID_INTERNAL_DAC2:
348 case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
349 return SIGNAL_TYPE_RGB;
351 return SIGNAL_TYPE_DVI_SINGLE_LINK;
354 case CONNECTOR_ID_DUAL_LINK_DVII:
356 switch (encoder.id) {
357 case ENCODER_ID_INTERNAL_DAC1:
358 case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
359 case ENCODER_ID_INTERNAL_DAC2:
360 case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
361 return SIGNAL_TYPE_RGB;
363 return SIGNAL_TYPE_DVI_DUAL_LINK;
367 case CONNECTOR_ID_SINGLE_LINK_DVID:
368 return SIGNAL_TYPE_DVI_SINGLE_LINK;
369 case CONNECTOR_ID_DUAL_LINK_DVID:
370 return SIGNAL_TYPE_DVI_DUAL_LINK;
371 case CONNECTOR_ID_VGA:
372 return SIGNAL_TYPE_RGB;
373 case CONNECTOR_ID_HDMI_TYPE_A:
374 return SIGNAL_TYPE_HDMI_TYPE_A;
375 case CONNECTOR_ID_LVDS:
376 return SIGNAL_TYPE_LVDS;
377 case CONNECTOR_ID_DISPLAY_PORT:
378 return SIGNAL_TYPE_DISPLAY_PORT;
379 case CONNECTOR_ID_EDP:
380 return SIGNAL_TYPE_EDP;
382 return SIGNAL_TYPE_NONE;
384 } else if (downstream.type == OBJECT_TYPE_ENCODER) {
385 switch (downstream.id) {
386 case ENCODER_ID_EXTERNAL_NUTMEG:
387 case ENCODER_ID_EXTERNAL_TRAVIS:
388 return SIGNAL_TYPE_DISPLAY_PORT;
390 return SIGNAL_TYPE_NONE;
394 return SIGNAL_TYPE_NONE;
398 * dc_link_is_dp_sink_present() - Check if there is a native DP
399 * or passive DP-HDMI dongle connected
401 bool dc_link_is_dp_sink_present(struct dc_link *link)
403 enum gpio_result gpio_result;
404 uint32_t clock_pin = 0;
408 enum connector_id connector_id =
409 dal_graphics_object_id_get_connector_id(link->link_id);
412 ((connector_id == CONNECTOR_ID_DISPLAY_PORT) ||
413 (connector_id == CONNECTOR_ID_EDP));
415 ddc = dal_ddc_service_get_ddc_pin(link->ddc);
422 /* Open GPIO and set it to I2C mode */
423 /* Note: this GpioMode_Input will be converted
424 * to GpioConfigType_I2cAuxDualMode in GPIO component,
425 * which indicates we need additional delay
428 if (dal_ddc_open(ddc, GPIO_MODE_INPUT,
429 GPIO_DDC_CONFIG_TYPE_MODE_I2C) != GPIO_RESULT_OK) {
436 * Read GPIO: DP sink is present if both clock and data pins are zero
438 * [W/A] plug-unplug DP cable, sometimes customer board has
439 * one short pulse on clk_pin(1V, < 1ms). DP will be config to HDMI/DVI
440 * then monitor can't br light up. Add retry 3 times
441 * But in real passive dongle, it need additional 3ms to detect
444 gpio_result = dal_gpio_get_value(ddc->pin_clock, &clock_pin);
445 ASSERT(gpio_result == GPIO_RESULT_OK);
450 } while (retry++ < 3);
452 present = (gpio_result == GPIO_RESULT_OK) && !clock_pin;
461 * Detect output sink type
463 static enum signal_type link_detect_sink(struct dc_link *link,
464 enum dc_detect_reason reason)
466 enum signal_type result;
467 struct graphics_object_id enc_id;
469 if (link->is_dig_mapping_flexible)
470 enc_id = (struct graphics_object_id){.id = ENCODER_ID_UNKNOWN};
472 enc_id = link->link_enc->id;
473 result = get_basic_signal_type(enc_id, link->link_id);
475 /* Use basic signal type for link without physical connector. */
476 if (link->ep_type != DISPLAY_ENDPOINT_PHY)
479 /* Internal digital encoder will detect only dongles
480 * that require digital signal
483 /* Detection mechanism is different
484 * for different native connectors.
485 * LVDS connector supports only LVDS signal;
486 * PCIE is a bus slot, the actual connector needs to be detected first;
487 * eDP connector supports only eDP signal;
488 * HDMI should check straps for audio
491 /* PCIE detects the actual connector on add-on board */
492 if (link->link_id.id == CONNECTOR_ID_PCIE) {
493 /* ZAZTODO implement PCIE add-on card detection */
496 switch (link->link_id.id) {
497 case CONNECTOR_ID_HDMI_TYPE_A: {
498 /* check audio support:
499 * if native HDMI is not supported, switch to DVI
501 struct audio_support *aud_support =
502 &link->dc->res_pool->audio_support;
504 if (!aud_support->hdmi_audio_native)
505 if (link->link_id.id == CONNECTOR_ID_HDMI_TYPE_A)
506 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
509 case CONNECTOR_ID_DISPLAY_PORT: {
510 /* DP HPD short pulse. Passive DP dongle will not
513 if (reason != DETECT_REASON_HPDRX) {
514 /* Check whether DP signal detected: if not -
515 * we assume signal is DVI; it could be corrected
516 * to HDMI after dongle detection
518 if (!dm_helpers_is_dp_sink_present(link))
519 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
530 static enum signal_type decide_signal_from_strap_and_dongle_type(enum display_dongle_type dongle_type,
531 struct audio_support *audio_support)
533 enum signal_type signal = SIGNAL_TYPE_NONE;
535 switch (dongle_type) {
536 case DISPLAY_DONGLE_DP_HDMI_DONGLE:
537 if (audio_support->hdmi_audio_on_dongle)
538 signal = SIGNAL_TYPE_HDMI_TYPE_A;
540 signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
542 case DISPLAY_DONGLE_DP_DVI_DONGLE:
543 signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
545 case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
546 if (audio_support->hdmi_audio_native)
547 signal = SIGNAL_TYPE_HDMI_TYPE_A;
549 signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
552 signal = SIGNAL_TYPE_NONE;
559 static enum signal_type dp_passive_dongle_detection(struct ddc_service *ddc,
560 struct display_sink_capability *sink_cap,
561 struct audio_support *audio_support)
563 dal_ddc_service_i2c_query_dp_dual_mode_adaptor(ddc, sink_cap);
565 return decide_signal_from_strap_and_dongle_type(sink_cap->dongle_type,
569 static void link_disconnect_sink(struct dc_link *link)
571 if (link->local_sink) {
572 dc_sink_release(link->local_sink);
573 link->local_sink = NULL;
576 link->dpcd_sink_count = 0;
577 //link->dpcd_caps.dpcd_rev.raw = 0;
580 static void link_disconnect_remap(struct dc_sink *prev_sink, struct dc_link *link)
582 dc_sink_release(link->local_sink);
583 link->local_sink = prev_sink;
586 #if defined(CONFIG_DRM_AMD_DC_HDCP)
587 bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal)
592 case SIGNAL_TYPE_DISPLAY_PORT:
593 case SIGNAL_TYPE_DISPLAY_PORT_MST:
594 ret = link->hdcp_caps.bcaps.bits.HDCP_CAPABLE;
596 case SIGNAL_TYPE_DVI_SINGLE_LINK:
597 case SIGNAL_TYPE_DVI_DUAL_LINK:
598 case SIGNAL_TYPE_HDMI_TYPE_A:
599 /* HDMI doesn't tell us its HDCP(1.4) capability, so assume to always be capable,
600 * we can poll for bksv but some displays have an issue with this. Since its so rare
601 * for a display to not be 1.4 capable, this assumtion is ok
611 bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal)
616 case SIGNAL_TYPE_DISPLAY_PORT:
617 case SIGNAL_TYPE_DISPLAY_PORT_MST:
618 ret = (link->hdcp_caps.bcaps.bits.HDCP_CAPABLE &&
619 link->hdcp_caps.rx_caps.fields.byte0.hdcp_capable &&
620 (link->hdcp_caps.rx_caps.fields.version == 0x2)) ? 1 : 0;
622 case SIGNAL_TYPE_DVI_SINGLE_LINK:
623 case SIGNAL_TYPE_DVI_DUAL_LINK:
624 case SIGNAL_TYPE_HDMI_TYPE_A:
625 ret = (link->hdcp_caps.rx_caps.fields.version == 0x4) ? 1:0;
634 static void query_hdcp_capability(enum signal_type signal, struct dc_link *link)
636 struct hdcp_protection_message msg22;
637 struct hdcp_protection_message msg14;
639 memset(&msg22, 0, sizeof(struct hdcp_protection_message));
640 memset(&msg14, 0, sizeof(struct hdcp_protection_message));
641 memset(link->hdcp_caps.rx_caps.raw, 0,
642 sizeof(link->hdcp_caps.rx_caps.raw));
644 if ((link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
645 link->ddc->transaction_type ==
646 DDC_TRANSACTION_TYPE_I2C_OVER_AUX) ||
647 link->connector_signal == SIGNAL_TYPE_EDP) {
648 msg22.data = link->hdcp_caps.rx_caps.raw;
649 msg22.length = sizeof(link->hdcp_caps.rx_caps.raw);
650 msg22.msg_id = HDCP_MESSAGE_ID_RX_CAPS;
652 msg22.data = &link->hdcp_caps.rx_caps.fields.version;
653 msg22.length = sizeof(link->hdcp_caps.rx_caps.fields.version);
654 msg22.msg_id = HDCP_MESSAGE_ID_HDCP2VERSION;
656 msg22.version = HDCP_VERSION_22;
657 msg22.link = HDCP_LINK_PRIMARY;
658 msg22.max_retries = 5;
659 dc_process_hdcp_msg(signal, link, &msg22);
661 if (signal == SIGNAL_TYPE_DISPLAY_PORT || signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
662 msg14.data = &link->hdcp_caps.bcaps.raw;
663 msg14.length = sizeof(link->hdcp_caps.bcaps.raw);
664 msg14.msg_id = HDCP_MESSAGE_ID_READ_BCAPS;
665 msg14.version = HDCP_VERSION_14;
666 msg14.link = HDCP_LINK_PRIMARY;
667 msg14.max_retries = 5;
669 dc_process_hdcp_msg(signal, link, &msg14);
675 static void read_current_link_settings_on_detect(struct dc_link *link)
677 union lane_count_set lane_count_set = {0};
679 uint8_t link_rate_set;
680 uint32_t read_dpcd_retry_cnt = 10;
681 enum dc_status status = DC_ERROR_UNEXPECTED;
683 union max_down_spread max_down_spread = {0};
685 // Read DPCD 00101h to find out the number of lanes currently set
686 for (i = 0; i < read_dpcd_retry_cnt; i++) {
687 status = core_link_read_dpcd(link,
690 sizeof(lane_count_set));
691 /* First DPCD read after VDD ON can fail if the particular board
692 * does not have HPD pin wired correctly. So if DPCD read fails,
693 * which it should never happen, retry a few times. Target worst
694 * case scenario of 80 ms.
696 if (status == DC_OK) {
697 link->cur_link_settings.lane_count =
698 lane_count_set.bits.LANE_COUNT_SET;
705 // Read DPCD 00100h to find if standard link rates are set
706 core_link_read_dpcd(link, DP_LINK_BW_SET,
707 &link_bw_set, sizeof(link_bw_set));
709 if (link_bw_set == 0) {
710 if (link->connector_signal == SIGNAL_TYPE_EDP) {
711 /* If standard link rates are not being used,
712 * Read DPCD 00115h to find the edp link rate set used
714 core_link_read_dpcd(link, DP_LINK_RATE_SET,
715 &link_rate_set, sizeof(link_rate_set));
717 // edp_supported_link_rates_count = 0 for DP
718 if (link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) {
719 link->cur_link_settings.link_rate =
720 link->dpcd_caps.edp_supported_link_rates[link_rate_set];
721 link->cur_link_settings.link_rate_set = link_rate_set;
722 link->cur_link_settings.use_link_rate_set = true;
725 // Link Rate not found. Seamless boot may not work.
729 link->cur_link_settings.link_rate = link_bw_set;
730 link->cur_link_settings.use_link_rate_set = false;
732 // Read DPCD 00003h to find the max down spread.
733 core_link_read_dpcd(link, DP_MAX_DOWNSPREAD,
734 &max_down_spread.raw, sizeof(max_down_spread));
735 link->cur_link_settings.link_spread =
736 max_down_spread.bits.MAX_DOWN_SPREAD ?
737 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
740 static bool detect_dp(struct dc_link *link,
741 struct display_sink_capability *sink_caps,
742 enum dc_detect_reason reason)
744 struct audio_support *audio_support = &link->dc->res_pool->audio_support;
746 sink_caps->signal = link_detect_sink(link, reason);
747 sink_caps->transaction_type =
748 get_ddc_transaction_type(sink_caps->signal);
750 if (sink_caps->transaction_type == DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
751 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
752 if (!detect_dp_sink_caps(link))
754 if (is_mst_supported(link)) {
755 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
756 link->type = dc_connection_mst_branch;
758 dal_ddc_service_set_transaction_type(link->ddc,
759 sink_caps->transaction_type);
761 #if defined(CONFIG_DRM_AMD_DC_HDCP)
762 /* In case of fallback to SST when topology discovery below fails
763 * HDCP caps will be querried again later by the upper layer (caller
764 * of this function). */
765 query_hdcp_capability(SIGNAL_TYPE_DISPLAY_PORT_MST, link);
769 if (link->type != dc_connection_mst_branch &&
770 is_dp_branch_device(link))
772 link->type = dc_connection_sst_branch;
774 /* DP passive dongles */
775 sink_caps->signal = dp_passive_dongle_detection(link->ddc,
778 link->dpcd_caps.dongle_type = sink_caps->dongle_type;
779 link->dpcd_caps.dpcd_rev.raw = 0;
785 static bool is_same_edid(struct dc_edid *old_edid, struct dc_edid *new_edid)
787 if (old_edid->length != new_edid->length)
790 if (new_edid->length == 0)
793 return (memcmp(old_edid->raw_edid,
794 new_edid->raw_edid, new_edid->length) == 0);
797 static bool wait_for_entering_dp_alt_mode(struct dc_link *link)
800 * something is terribly wrong if time out is > 200ms. (5Hz)
801 * 500 microseconds * 400 tries us 200 ms
803 unsigned int sleep_time_in_microseconds = 500;
804 unsigned int tries_allowed = 400;
806 unsigned long long enter_timestamp;
807 unsigned long long finish_timestamp;
808 unsigned long long time_taken_in_ns;
811 DC_LOGGER_INIT(link->ctx->logger);
813 if (!link->link_enc->funcs->is_in_alt_mode)
816 is_in_alt_mode = link->link_enc->funcs->is_in_alt_mode(link->link_enc);
817 DC_LOG_WARNING("DP Alt mode state on HPD: %d\n", is_in_alt_mode);
822 enter_timestamp = dm_get_timestamp(link->ctx);
824 for (tries_taken = 0; tries_taken < tries_allowed; tries_taken++) {
825 udelay(sleep_time_in_microseconds);
826 /* ask the link if alt mode is enabled, if so return ok */
827 if (link->link_enc->funcs->is_in_alt_mode(link->link_enc)) {
828 finish_timestamp = dm_get_timestamp(link->ctx);
830 dm_get_elapse_time_in_ns(link->ctx,
833 DC_LOG_WARNING("Alt mode entered finished after %llu ms\n",
834 div_u64(time_taken_in_ns, 1000000));
838 finish_timestamp = dm_get_timestamp(link->ctx);
839 time_taken_in_ns = dm_get_elapse_time_in_ns(link->ctx, finish_timestamp,
841 DC_LOG_WARNING("Alt mode has timed out after %llu ms\n",
842 div_u64(time_taken_in_ns, 1000000));
847 * dc_link_detect() - Detect if a sink is attached to a given link
849 * link->local_sink is created or destroyed as needed.
851 * This does not create remote sinks but will trigger DM
852 * to start MST detection if a branch is detected.
854 static bool dc_link_detect_helper(struct dc_link *link,
855 enum dc_detect_reason reason)
857 struct dc_sink_init_data sink_init_data = { 0 };
858 struct display_sink_capability sink_caps = { 0 };
860 bool converter_disable_audio = false;
861 struct audio_support *aud_support = &link->dc->res_pool->audio_support;
862 bool same_edid = false;
863 enum dc_edid_status edid_status;
864 struct dc_context *dc_ctx = link->ctx;
865 struct dc_sink *sink = NULL;
866 struct dc_sink *prev_sink = NULL;
867 struct dpcd_caps prev_dpcd_caps;
868 enum dc_connection_type new_connection_type = dc_connection_none;
869 enum dc_connection_type pre_connection_type = dc_connection_none;
870 bool perform_dp_seamless_boot = false;
871 const uint32_t post_oui_delay = 30; // 30ms
873 DC_LOGGER_INIT(link->ctx->logger);
875 if (dc_is_virtual_signal(link->connector_signal))
878 if (((link->connector_signal == SIGNAL_TYPE_LVDS ||
879 link->connector_signal == SIGNAL_TYPE_EDP) &&
880 (!link->dc->config.allow_edp_hotplug_detection)) &&
882 // need to re-write OUI and brightness in resume case
883 if (link->connector_signal == SIGNAL_TYPE_EDP) {
884 dpcd_set_source_specific_data(link);
885 msleep(post_oui_delay);
886 dc_link_set_default_brightness_aux(link);
893 if (!dc_link_detect_sink(link, &new_connection_type)) {
898 prev_sink = link->local_sink;
900 dc_sink_retain(prev_sink);
901 memcpy(&prev_dpcd_caps, &link->dpcd_caps, sizeof(struct dpcd_caps));
904 link_disconnect_sink(link);
905 if (new_connection_type != dc_connection_none) {
906 pre_connection_type = link->type;
907 link->type = new_connection_type;
908 link->link_state_valid = false;
910 /* From Disconnected-to-Connected. */
911 switch (link->connector_signal) {
912 case SIGNAL_TYPE_HDMI_TYPE_A: {
913 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
914 if (aud_support->hdmi_audio_native)
915 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
917 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
921 case SIGNAL_TYPE_DVI_SINGLE_LINK: {
922 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
923 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
927 case SIGNAL_TYPE_DVI_DUAL_LINK: {
928 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
929 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
933 case SIGNAL_TYPE_LVDS: {
934 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
935 sink_caps.signal = SIGNAL_TYPE_LVDS;
939 case SIGNAL_TYPE_EDP: {
940 read_current_link_settings_on_detect(link);
942 detect_edp_sink_caps(link);
943 read_current_link_settings_on_detect(link);
944 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
945 sink_caps.signal = SIGNAL_TYPE_EDP;
949 case SIGNAL_TYPE_DISPLAY_PORT: {
950 /* wa HPD high coming too early*/
951 if (link->ep_type == DISPLAY_ENDPOINT_PHY &&
952 link->link_enc->features.flags.bits.DP_IS_USB_C == 1) {
953 /* if alt mode times out, return false */
954 if (!wait_for_entering_dp_alt_mode(link))
958 if (!detect_dp(link, &sink_caps, reason)) {
960 dc_sink_release(prev_sink);
964 #if defined(CONFIG_DRM_AMD_DC_DCN)
965 if (dp_get_link_encoding_format(&link->reported_link_cap) == DP_128b_132b_ENCODING)
966 add_dp_hpo_link_encoder_to_link(link);
969 if (link->type == dc_connection_mst_branch) {
970 LINK_INFO("link=%d, mst branch is now Connected\n",
972 /* Need to setup mst link_cap struct here
973 * otherwise dc_link_detect() will leave mst link_cap
974 * empty which leads to allocate_mst_payload() has "0"
975 * pbn_per_slot value leading to exception on dc_fixpt_div()
977 dp_verify_mst_link_cap(link);
980 * This call will initiate MST topology discovery. Which
981 * will detect MST ports and add new DRM connector DRM
982 * framework. Then read EDID via remote i2c over aux. In
983 * the end, will notify DRM detect result and save EDID
984 * into DRM framework.
986 * .detect is called by .fill_modes.
987 * .fill_modes is called by user mode ioctl
988 * DRM_IOCTL_MODE_GETCONNECTOR.
990 * .get_modes is called by .fill_modes.
992 * call .get_modes, AMDGPU DM implementation will create
993 * new dc_sink and add to dc_link. For long HPD plug
994 * in/out, MST has its own handle.
996 * Therefore, just after dc_create, link->sink is not
997 * created for MST until user mode app calls
998 * DRM_IOCTL_MODE_GETCONNECTOR.
1000 * Need check ->sink usages in case ->sink = NULL
1001 * TODO: s3 resume check
1004 dm_helpers_dp_update_branch_info(link->ctx, link);
1005 if (dm_helpers_dp_mst_start_top_mgr(link->ctx,
1006 link, reason == DETECT_REASON_BOOT)) {
1008 dc_sink_release(prev_sink);
1011 link->type = dc_connection_sst_branch;
1012 sink_caps.signal = SIGNAL_TYPE_DISPLAY_PORT;
1016 /* Active SST downstream branch device unplug*/
1017 if (link->type == dc_connection_sst_branch &&
1018 link->dpcd_caps.sink_count.bits.SINK_COUNT == 0) {
1020 /* Downstream unplug */
1021 dc_sink_release(prev_sink);
1025 /* disable audio for non DP to HDMI active sst converter */
1026 if (link->type == dc_connection_sst_branch &&
1027 is_dp_active_dongle(link) &&
1028 (link->dpcd_caps.dongle_type !=
1029 DISPLAY_DONGLE_DP_HDMI_CONVERTER))
1030 converter_disable_audio = true;
1032 // link switch from MST to non-MST stop topology manager
1033 if (pre_connection_type == dc_connection_mst_branch &&
1034 link->type != dc_connection_mst_branch)
1035 dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
1038 // For seamless boot, to skip verify link cap, we read UEFI settings and set them as verified.
1039 if (reason == DETECT_REASON_BOOT &&
1040 !dc_ctx->dc->config.power_down_display_on_boot &&
1041 link->link_status.link_active)
1042 perform_dp_seamless_boot = true;
1044 if (perform_dp_seamless_boot) {
1045 read_current_link_settings_on_detect(link);
1046 link->verified_link_cap = link->reported_link_cap;
1053 DC_ERROR("Invalid connector type! signal:%d\n",
1054 link->connector_signal);
1056 dc_sink_release(prev_sink);
1060 if (link->dpcd_caps.sink_count.bits.SINK_COUNT)
1061 link->dpcd_sink_count =
1062 link->dpcd_caps.sink_count.bits.SINK_COUNT;
1064 link->dpcd_sink_count = 1;
1066 dal_ddc_service_set_transaction_type(link->ddc,
1067 sink_caps.transaction_type);
1070 dal_ddc_service_is_in_aux_transaction_mode(link->ddc);
1072 sink_init_data.link = link;
1073 sink_init_data.sink_signal = sink_caps.signal;
1075 sink = dc_sink_create(&sink_init_data);
1077 DC_ERROR("Failed to create sink!\n");
1079 dc_sink_release(prev_sink);
1083 sink->link->dongle_max_pix_clk = sink_caps.max_hdmi_pixel_clock;
1084 sink->converter_disable_audio = converter_disable_audio;
1086 /* dc_sink_create returns a new reference */
1087 link->local_sink = sink;
1089 edid_status = dm_helpers_read_local_edid(link->ctx,
1092 switch (edid_status) {
1093 case EDID_BAD_CHECKSUM:
1094 DC_LOG_ERROR("EDID checksum invalid.\n");
1096 case EDID_NO_RESPONSE:
1097 DC_LOG_ERROR("No EDID read.\n");
1099 * Abort detection for non-DP connectors if we have
1102 * DP needs to report as connected if HDP is high
1103 * even if we have no EDID in order to go to
1106 if (dc_is_hdmi_signal(link->connector_signal) ||
1107 dc_is_dvi_signal(link->connector_signal)) {
1109 dc_sink_release(prev_sink);
1118 // Check if edid is the same
1120 (edid_status == EDID_THE_SAME || edid_status == EDID_OK))
1121 same_edid = is_same_edid(&prev_sink->dc_edid,
1124 if (sink->edid_caps.panel_patch.skip_scdc_overwrite)
1125 link->ctx->dc->debug.hdmi20_disable = true;
1127 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
1128 sink_caps.transaction_type ==
1129 DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
1131 * TODO debug why Dell 2413 doesn't like
1132 * two link trainings
1134 #if defined(CONFIG_DRM_AMD_DC_HDCP)
1135 query_hdcp_capability(sink->sink_signal, link);
1138 // verify link cap for SST non-seamless boot
1139 if (!perform_dp_seamless_boot)
1140 dp_verify_link_cap_with_retries(link,
1141 &link->reported_link_cap,
1142 LINK_TRAINING_MAX_VERIFY_RETRY);
1144 // If edid is the same, then discard new sink and revert back to original sink
1146 link_disconnect_remap(prev_sink, link);
1150 #if defined(CONFIG_DRM_AMD_DC_HDCP)
1151 query_hdcp_capability(sink->sink_signal, link);
1155 /* HDMI-DVI Dongle */
1156 if (sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A &&
1157 !sink->edid_caps.edid_hdmi)
1158 sink->sink_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1160 /* Connectivity log: detection */
1161 for (i = 0; i < sink->dc_edid.length / DC_EDID_BLOCK_SIZE; i++) {
1162 CONN_DATA_DETECT(link,
1163 &sink->dc_edid.raw_edid[i * DC_EDID_BLOCK_SIZE],
1165 "%s: [Block %d] ", sink->edid_caps.display_name, i);
1168 DC_LOG_DETECTION_EDID_PARSER("%s: "
1169 "manufacturer_id = %X, "
1171 "serial_number = %X, "
1172 "manufacture_week = %d, "
1173 "manufacture_year = %d, "
1174 "display_name = %s, "
1175 "speaker_flag = %d, "
1176 "audio_mode_count = %d\n",
1178 sink->edid_caps.manufacturer_id,
1179 sink->edid_caps.product_id,
1180 sink->edid_caps.serial_number,
1181 sink->edid_caps.manufacture_week,
1182 sink->edid_caps.manufacture_year,
1183 sink->edid_caps.display_name,
1184 sink->edid_caps.speaker_flags,
1185 sink->edid_caps.audio_mode_count);
1187 for (i = 0; i < sink->edid_caps.audio_mode_count; i++) {
1188 DC_LOG_DETECTION_EDID_PARSER("%s: mode number = %d, "
1189 "format_code = %d, "
1190 "channel_count = %d, "
1191 "sample_rate = %d, "
1192 "sample_size = %d\n",
1195 sink->edid_caps.audio_modes[i].format_code,
1196 sink->edid_caps.audio_modes[i].channel_count,
1197 sink->edid_caps.audio_modes[i].sample_rate,
1198 sink->edid_caps.audio_modes[i].sample_size);
1201 /* From Connected-to-Disconnected. */
1202 if (link->type == dc_connection_mst_branch) {
1203 LINK_INFO("link=%d, mst branch is now Disconnected\n",
1206 dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
1208 link->mst_stream_alloc_table.stream_count = 0;
1209 memset(link->mst_stream_alloc_table.stream_allocations,
1211 sizeof(link->mst_stream_alloc_table.stream_allocations));
1214 #if defined(CONFIG_DRM_AMD_DC_DCN)
1215 if (dp_get_link_encoding_format(&link->cur_link_settings) == DP_128b_132b_ENCODING)
1216 reset_dp_hpo_stream_encoders_for_link(link);
1219 link->type = dc_connection_none;
1220 sink_caps.signal = SIGNAL_TYPE_NONE;
1221 /* When we unplug a passive DP-HDMI dongle connection, dongle_max_pix_clk
1222 * is not cleared. If we emulate a DP signal on this connection, it thinks
1223 * the dongle is still there and limits the number of modes we can emulate.
1224 * Clear dongle_max_pix_clk on disconnect to fix this
1226 link->dongle_max_pix_clk = 0;
1229 LINK_INFO("link=%d, dc_sink_in=%p is now %s prev_sink=%p edid same=%d\n",
1230 link->link_index, sink,
1231 (sink_caps.signal ==
1232 SIGNAL_TYPE_NONE ? "Disconnected" : "Connected"),
1233 prev_sink, same_edid);
1236 dc_sink_release(prev_sink);
1241 bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
1243 const struct dc *dc = link->dc;
1245 bool can_apply_seamless_boot = false;
1248 for (i = 0; i < dc->current_state->stream_count; i++) {
1249 if (dc->current_state->streams[i]->apply_seamless_boot_optimization) {
1250 can_apply_seamless_boot = true;
1255 #if defined(CONFIG_DRM_AMD_DC_DCN)
1259 /* get out of low power state */
1260 if (!can_apply_seamless_boot && reason != DETECT_REASON_BOOT)
1261 clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr);
1263 ret = dc_link_detect_helper(link, reason);
1265 /* Go back to power optimized state */
1266 if (!can_apply_seamless_boot && reason != DETECT_REASON_BOOT)
1267 clk_mgr_optimize_pwr_state(dc, dc->clk_mgr);
1272 bool dc_link_get_hpd_state(struct dc_link *dc_link)
1276 dal_gpio_lock_pin(dc_link->hpd_gpio);
1277 dal_gpio_get_value(dc_link->hpd_gpio, &state);
1278 dal_gpio_unlock_pin(dc_link->hpd_gpio);
1283 static enum hpd_source_id get_hpd_line(struct dc_link *link)
1286 enum hpd_source_id hpd_id = HPD_SOURCEID_UNKNOWN;
1288 hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
1289 link->ctx->gpio_service);
1292 switch (dal_irq_get_source(hpd)) {
1293 case DC_IRQ_SOURCE_HPD1:
1294 hpd_id = HPD_SOURCEID1;
1296 case DC_IRQ_SOURCE_HPD2:
1297 hpd_id = HPD_SOURCEID2;
1299 case DC_IRQ_SOURCE_HPD3:
1300 hpd_id = HPD_SOURCEID3;
1302 case DC_IRQ_SOURCE_HPD4:
1303 hpd_id = HPD_SOURCEID4;
1305 case DC_IRQ_SOURCE_HPD5:
1306 hpd_id = HPD_SOURCEID5;
1308 case DC_IRQ_SOURCE_HPD6:
1309 hpd_id = HPD_SOURCEID6;
1312 BREAK_TO_DEBUGGER();
1316 dal_gpio_destroy_irq(&hpd);
1322 static enum channel_id get_ddc_line(struct dc_link *link)
1325 enum channel_id channel = CHANNEL_ID_UNKNOWN;
1327 ddc = dal_ddc_service_get_ddc_pin(link->ddc);
1330 switch (dal_ddc_get_line(ddc)) {
1331 case GPIO_DDC_LINE_DDC1:
1332 channel = CHANNEL_ID_DDC1;
1334 case GPIO_DDC_LINE_DDC2:
1335 channel = CHANNEL_ID_DDC2;
1337 case GPIO_DDC_LINE_DDC3:
1338 channel = CHANNEL_ID_DDC3;
1340 case GPIO_DDC_LINE_DDC4:
1341 channel = CHANNEL_ID_DDC4;
1343 case GPIO_DDC_LINE_DDC5:
1344 channel = CHANNEL_ID_DDC5;
1346 case GPIO_DDC_LINE_DDC6:
1347 channel = CHANNEL_ID_DDC6;
1349 case GPIO_DDC_LINE_DDC_VGA:
1350 channel = CHANNEL_ID_DDC_VGA;
1352 case GPIO_DDC_LINE_I2C_PAD:
1353 channel = CHANNEL_ID_I2C_PAD;
1356 BREAK_TO_DEBUGGER();
1364 static enum transmitter translate_encoder_to_transmitter(struct graphics_object_id encoder)
1366 switch (encoder.id) {
1367 case ENCODER_ID_INTERNAL_UNIPHY:
1368 switch (encoder.enum_id) {
1370 return TRANSMITTER_UNIPHY_A;
1372 return TRANSMITTER_UNIPHY_B;
1374 return TRANSMITTER_UNKNOWN;
1377 case ENCODER_ID_INTERNAL_UNIPHY1:
1378 switch (encoder.enum_id) {
1380 return TRANSMITTER_UNIPHY_C;
1382 return TRANSMITTER_UNIPHY_D;
1384 return TRANSMITTER_UNKNOWN;
1387 case ENCODER_ID_INTERNAL_UNIPHY2:
1388 switch (encoder.enum_id) {
1390 return TRANSMITTER_UNIPHY_E;
1392 return TRANSMITTER_UNIPHY_F;
1394 return TRANSMITTER_UNKNOWN;
1397 case ENCODER_ID_INTERNAL_UNIPHY3:
1398 switch (encoder.enum_id) {
1400 return TRANSMITTER_UNIPHY_G;
1402 return TRANSMITTER_UNKNOWN;
1405 case ENCODER_ID_EXTERNAL_NUTMEG:
1406 switch (encoder.enum_id) {
1408 return TRANSMITTER_NUTMEG_CRT;
1410 return TRANSMITTER_UNKNOWN;
1413 case ENCODER_ID_EXTERNAL_TRAVIS:
1414 switch (encoder.enum_id) {
1416 return TRANSMITTER_TRAVIS_CRT;
1418 return TRANSMITTER_TRAVIS_LCD;
1420 return TRANSMITTER_UNKNOWN;
1424 return TRANSMITTER_UNKNOWN;
1428 static bool dc_link_construct_legacy(struct dc_link *link,
1429 const struct link_init_data *init_params)
1432 struct ddc_service_init_data ddc_service_init_data = { { 0 } };
1433 struct dc_context *dc_ctx = init_params->ctx;
1434 struct encoder_init_data enc_init_data = { 0 };
1435 struct panel_cntl_init_data panel_cntl_init_data = { 0 };
1436 struct integrated_info *info;
1437 struct dc_bios *bios = init_params->dc->ctx->dc_bios;
1438 const struct dc_vbios_funcs *bp_funcs = bios->funcs;
1439 struct bp_disp_connector_caps_info disp_connect_caps_info = { 0 };
1441 DC_LOGGER_INIT(dc_ctx->logger);
1443 info = kzalloc(sizeof(*info), GFP_KERNEL);
1447 link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1448 link->irq_source_hpd_rx = DC_IRQ_SOURCE_INVALID;
1450 link->link_status.dpcd_caps = &link->dpcd_caps;
1452 link->dc = init_params->dc;
1454 link->link_index = init_params->link_index;
1456 memset(&link->preferred_training_settings, 0,
1457 sizeof(struct dc_link_training_overrides));
1458 memset(&link->preferred_link_setting, 0,
1459 sizeof(struct dc_link_settings));
1462 bios->funcs->get_connector_id(bios, init_params->connector_index);
1464 link->ep_type = DISPLAY_ENDPOINT_PHY;
1466 DC_LOG_DC("BIOS object table - link_id: %d", link->link_id.id);
1468 if (bios->funcs->get_disp_connector_caps_info) {
1469 bios->funcs->get_disp_connector_caps_info(bios, link->link_id, &disp_connect_caps_info);
1470 link->is_internal_display = disp_connect_caps_info.INTERNAL_DISPLAY;
1471 DC_LOG_DC("BIOS object table - is_internal_display: %d", link->is_internal_display);
1474 if (link->link_id.type != OBJECT_TYPE_CONNECTOR) {
1475 dm_output_to_console("%s: Invalid Connector ObjectID from Adapter Service for connector index:%d! type %d expected %d\n",
1476 __func__, init_params->connector_index,
1477 link->link_id.type, OBJECT_TYPE_CONNECTOR);
1481 if (link->dc->res_pool->funcs->link_init)
1482 link->dc->res_pool->funcs->link_init(link);
1484 link->hpd_gpio = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
1485 link->ctx->gpio_service);
1487 if (link->hpd_gpio) {
1488 dal_gpio_open(link->hpd_gpio, GPIO_MODE_INTERRUPT);
1489 dal_gpio_unlock_pin(link->hpd_gpio);
1490 link->irq_source_hpd = dal_irq_get_source(link->hpd_gpio);
1492 DC_LOG_DC("BIOS object table - hpd_gpio id: %d", link->hpd_gpio->id);
1493 DC_LOG_DC("BIOS object table - hpd_gpio en: %d", link->hpd_gpio->en);
1496 switch (link->link_id.id) {
1497 case CONNECTOR_ID_HDMI_TYPE_A:
1498 link->connector_signal = SIGNAL_TYPE_HDMI_TYPE_A;
1501 case CONNECTOR_ID_SINGLE_LINK_DVID:
1502 case CONNECTOR_ID_SINGLE_LINK_DVII:
1503 link->connector_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1505 case CONNECTOR_ID_DUAL_LINK_DVID:
1506 case CONNECTOR_ID_DUAL_LINK_DVII:
1507 link->connector_signal = SIGNAL_TYPE_DVI_DUAL_LINK;
1509 case CONNECTOR_ID_DISPLAY_PORT:
1510 link->connector_signal = SIGNAL_TYPE_DISPLAY_PORT;
1513 link->irq_source_hpd_rx =
1514 dal_irq_get_rx_source(link->hpd_gpio);
1517 case CONNECTOR_ID_EDP:
1518 link->connector_signal = SIGNAL_TYPE_EDP;
1520 if (link->hpd_gpio) {
1521 if (!link->dc->config.allow_edp_hotplug_detection)
1522 link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1523 link->irq_source_hpd_rx =
1524 dal_irq_get_rx_source(link->hpd_gpio);
1528 case CONNECTOR_ID_LVDS:
1529 link->connector_signal = SIGNAL_TYPE_LVDS;
1532 DC_LOG_WARNING("Unsupported Connector type:%d!\n",
1537 /* TODO: #DAL3 Implement id to str function.*/
1538 LINK_INFO("Connector[%d] description:"
1540 init_params->connector_index,
1541 link->connector_signal);
1543 ddc_service_init_data.ctx = link->ctx;
1544 ddc_service_init_data.id = link->link_id;
1545 ddc_service_init_data.link = link;
1546 link->ddc = dal_ddc_service_create(&ddc_service_init_data);
1549 DC_ERROR("Failed to create ddc_service!\n");
1550 goto ddc_create_fail;
1553 if (!link->ddc->ddc_pin) {
1554 DC_ERROR("Failed to get I2C info for connector!\n");
1555 goto ddc_create_fail;
1559 dal_ddc_get_line(dal_ddc_service_get_ddc_pin(link->ddc));
1562 if (link->dc->res_pool->funcs->panel_cntl_create &&
1563 (link->link_id.id == CONNECTOR_ID_EDP ||
1564 link->link_id.id == CONNECTOR_ID_LVDS)) {
1565 panel_cntl_init_data.ctx = dc_ctx;
1566 panel_cntl_init_data.inst =
1567 panel_cntl_init_data.ctx->dc_edp_id_count;
1569 link->dc->res_pool->funcs->panel_cntl_create(
1570 &panel_cntl_init_data);
1571 panel_cntl_init_data.ctx->dc_edp_id_count++;
1573 if (link->panel_cntl == NULL) {
1574 DC_ERROR("Failed to create link panel_cntl!\n");
1575 goto panel_cntl_create_fail;
1579 enc_init_data.ctx = dc_ctx;
1580 bp_funcs->get_src_obj(dc_ctx->dc_bios, link->link_id, 0,
1581 &enc_init_data.encoder);
1582 enc_init_data.connector = link->link_id;
1583 enc_init_data.channel = get_ddc_line(link);
1584 enc_init_data.hpd_source = get_hpd_line(link);
1586 link->hpd_src = enc_init_data.hpd_source;
1588 enc_init_data.transmitter =
1589 translate_encoder_to_transmitter(enc_init_data.encoder);
1591 link->dc->res_pool->funcs->link_enc_create(&enc_init_data);
1593 if (!link->link_enc) {
1594 DC_ERROR("Failed to create link encoder!\n");
1595 goto link_enc_create_fail;
1598 DC_LOG_DC("BIOS object table - DP_IS_USB_C: %d", link->link_enc->features.flags.bits.DP_IS_USB_C);
1599 #if defined(CONFIG_DRM_AMD_DC_DCN)
1600 DC_LOG_DC("BIOS object table - IS_DP2_CAPABLE: %d", link->link_enc->features.flags.bits.IS_DP2_CAPABLE);
1603 /* Update link encoder tracking variables. These are used for the dynamic
1604 * assignment of link encoders to streams.
1606 link->eng_id = link->link_enc->preferred_engine;
1607 link->dc->res_pool->link_encoders[link->eng_id - ENGINE_ID_DIGA] = link->link_enc;
1608 link->dc->res_pool->dig_link_enc_count++;
1610 link->link_enc_hw_inst = link->link_enc->transmitter;
1612 for (i = 0; i < 4; i++) {
1613 if (bp_funcs->get_device_tag(dc_ctx->dc_bios,
1615 &link->device_tag) != BP_RESULT_OK) {
1616 DC_ERROR("Failed to find device tag!\n");
1617 goto device_tag_fail;
1620 /* Look for device tag that matches connector signal,
1621 * CRT for rgb, LCD for other supported signal tyes
1623 if (!bp_funcs->is_device_id_supported(dc_ctx->dc_bios,
1624 link->device_tag.dev_id))
1626 if (link->device_tag.dev_id.device_type == DEVICE_TYPE_CRT &&
1627 link->connector_signal != SIGNAL_TYPE_RGB)
1629 if (link->device_tag.dev_id.device_type == DEVICE_TYPE_LCD &&
1630 link->connector_signal == SIGNAL_TYPE_RGB)
1633 DC_LOG_DC("BIOS object table - device_tag.acpi_device: %d", link->device_tag.acpi_device);
1634 DC_LOG_DC("BIOS object table - device_tag.dev_id.device_type: %d", link->device_tag.dev_id.device_type);
1635 DC_LOG_DC("BIOS object table - device_tag.dev_id.enum_id: %d", link->device_tag.dev_id.enum_id);
1639 if (bios->integrated_info)
1640 memcpy(info, bios->integrated_info, sizeof(*info));
1642 /* Look for channel mapping corresponding to connector and device tag */
1643 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; i++) {
1644 struct external_display_path *path =
1645 &info->ext_disp_conn_info.path[i];
1647 if (path->device_connector_id.enum_id == link->link_id.enum_id &&
1648 path->device_connector_id.id == link->link_id.id &&
1649 path->device_connector_id.type == link->link_id.type) {
1650 if (link->device_tag.acpi_device != 0 &&
1651 path->device_acpi_enum == link->device_tag.acpi_device) {
1652 link->ddi_channel_mapping = path->channel_mapping;
1653 link->chip_caps = path->caps;
1654 DC_LOG_DC("BIOS object table - ddi_channel_mapping: 0x%04X", link->ddi_channel_mapping.raw);
1655 DC_LOG_DC("BIOS object table - chip_caps: %d", link->chip_caps);
1656 } else if (path->device_tag ==
1657 link->device_tag.dev_id.raw_device_tag) {
1658 link->ddi_channel_mapping = path->channel_mapping;
1659 link->chip_caps = path->caps;
1660 DC_LOG_DC("BIOS object table - ddi_channel_mapping: 0x%04X", link->ddi_channel_mapping.raw);
1661 DC_LOG_DC("BIOS object table - chip_caps: %d", link->chip_caps);
1664 if (link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) {
1665 link->bios_forced_drive_settings.VOLTAGE_SWING =
1666 (info->ext_disp_conn_info.fixdpvoltageswing & 0x3);
1667 link->bios_forced_drive_settings.PRE_EMPHASIS =
1668 ((info->ext_disp_conn_info.fixdpvoltageswing >> 2) & 0x3);
1675 if (bios->funcs->get_atom_dc_golden_table)
1676 bios->funcs->get_atom_dc_golden_table(bios);
1679 * TODO check if GPIO programmed correctly
1681 * If GPIO isn't programmed correctly HPD might not rise or drain
1682 * fast enough, leading to bounces.
1684 program_hpd_filter(link);
1686 link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
1688 DC_LOG_DC("BIOS object table - %s finished successfully.\n", __func__);
1692 link->link_enc->funcs->destroy(&link->link_enc);
1693 link_enc_create_fail:
1694 if (link->panel_cntl != NULL)
1695 link->panel_cntl->funcs->destroy(&link->panel_cntl);
1696 panel_cntl_create_fail:
1697 dal_ddc_service_destroy(&link->ddc);
1701 if (link->hpd_gpio) {
1702 dal_gpio_destroy_irq(&link->hpd_gpio);
1703 link->hpd_gpio = NULL;
1706 DC_LOG_DC("BIOS object table - %s failed.\n", __func__);
1712 static bool dc_link_construct_dpia(struct dc_link *link,
1713 const struct link_init_data *init_params)
1715 struct ddc_service_init_data ddc_service_init_data = { { 0 } };
1716 struct dc_context *dc_ctx = init_params->ctx;
1718 DC_LOGGER_INIT(dc_ctx->logger);
1720 /* Initialized irq source for hpd and hpd rx */
1721 link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1722 link->irq_source_hpd_rx = DC_IRQ_SOURCE_INVALID;
1723 link->link_status.dpcd_caps = &link->dpcd_caps;
1725 link->dc = init_params->dc;
1727 link->link_index = init_params->link_index;
1729 memset(&link->preferred_training_settings, 0,
1730 sizeof(struct dc_link_training_overrides));
1731 memset(&link->preferred_link_setting, 0,
1732 sizeof(struct dc_link_settings));
1734 /* Dummy Init for linkid */
1735 link->link_id.type = OBJECT_TYPE_CONNECTOR;
1736 link->link_id.id = CONNECTOR_ID_DISPLAY_PORT;
1737 link->link_id.enum_id = ENUM_ID_1 + init_params->connector_index;
1738 link->is_internal_display = false;
1739 link->connector_signal = SIGNAL_TYPE_DISPLAY_PORT;
1740 LINK_INFO("Connector[%d] description:signal %d\n",
1741 init_params->connector_index,
1742 link->connector_signal);
1744 link->ep_type = DISPLAY_ENDPOINT_USB4_DPIA;
1745 link->is_dig_mapping_flexible = true;
1747 /* TODO: Initialize link : funcs->link_init */
1749 ddc_service_init_data.ctx = link->ctx;
1750 ddc_service_init_data.id = link->link_id;
1751 ddc_service_init_data.link = link;
1752 /* Set indicator for dpia link so that ddc won't be created */
1753 ddc_service_init_data.is_dpia_link = true;
1755 link->ddc = dal_ddc_service_create(&ddc_service_init_data);
1757 DC_ERROR("Failed to create ddc_service!\n");
1758 goto ddc_create_fail;
1761 /* Set dpia port index : 0 to number of dpia ports */
1762 link->ddc_hw_inst = init_params->connector_index;
1764 /* TODO: Create link encoder */
1766 link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
1768 /* Some docks seem to NAK I2C writes to segment pointer with mot=0. */
1769 link->wa_flags.dp_mot_reset_segment = true;
1777 static bool dc_link_construct(struct dc_link *link,
1778 const struct link_init_data *init_params)
1780 /* Handle dpia case */
1781 if (init_params->is_dpia_link)
1782 return dc_link_construct_dpia(link, init_params);
1784 return dc_link_construct_legacy(link, init_params);
1786 /*******************************************************************************
1788 ******************************************************************************/
1789 struct dc_link *link_create(const struct link_init_data *init_params)
1791 struct dc_link *link =
1792 kzalloc(sizeof(*link), GFP_KERNEL);
1797 if (false == dc_link_construct(link, init_params))
1798 goto construct_fail;
1801 * Must use preferred_link_setting, not reported_link_cap or verified_link_cap,
1802 * since struct preferred_link_setting won't be reset after S3.
1804 link->preferred_link_setting.dpcd_source_device_specific_field_support = true;
1815 void link_destroy(struct dc_link **link)
1817 dc_link_destruct(*link);
1822 static void enable_stream_features(struct pipe_ctx *pipe_ctx)
1824 struct dc_stream_state *stream = pipe_ctx->stream;
1826 if (pipe_ctx->stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST) {
1827 struct dc_link *link = stream->link;
1828 union down_spread_ctrl old_downspread;
1829 union down_spread_ctrl new_downspread;
1831 core_link_read_dpcd(link, DP_DOWNSPREAD_CTRL,
1832 &old_downspread.raw, sizeof(old_downspread));
1834 new_downspread.raw = old_downspread.raw;
1836 new_downspread.bits.IGNORE_MSA_TIMING_PARAM =
1837 (stream->ignore_msa_timing_param) ? 1 : 0;
1839 if (new_downspread.raw != old_downspread.raw) {
1840 core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
1841 &new_downspread.raw, sizeof(new_downspread));
1845 dm_helpers_mst_enable_stream_features(stream);
1849 static enum dc_status enable_link_dp(struct dc_state *state,
1850 struct pipe_ctx *pipe_ctx)
1852 struct dc_stream_state *stream = pipe_ctx->stream;
1853 enum dc_status status;
1854 bool skip_video_pattern;
1855 struct dc_link *link = stream->link;
1856 struct dc_link_settings link_settings = {0};
1859 bool apply_seamless_boot_optimization = false;
1860 uint32_t bl_oled_enable_delay = 50; // in ms
1861 const uint32_t post_oui_delay = 30; // 30ms
1862 /* Reduce link bandwidth between failed link training attempts. */
1863 bool do_fallback = false;
1865 // check for seamless boot
1866 for (i = 0; i < state->stream_count; i++) {
1867 if (state->streams[i]->apply_seamless_boot_optimization) {
1868 apply_seamless_boot_optimization = true;
1873 /* get link settings for video mode timing */
1874 decide_link_settings(stream, &link_settings);
1876 /* Train with fallback when enabling DPIA link. Conventional links are
1877 * trained with fallback during sink detection.
1879 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
1882 #if defined(CONFIG_DRM_AMD_DC_DCN)
1884 * Temporary w/a to get DP2.0 link rates to work with SST.
1885 * TODO DP2.0 - Workaround: Remove w/a if and when the issue is resolved.
1887 if (dp_get_link_encoding_format(&link_settings) == DP_128b_132b_ENCODING &&
1888 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT &&
1889 link->dc->debug.set_mst_en_for_sst) {
1890 dp_enable_mst_on_sink(link, true);
1894 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) {
1895 /*in case it is not on*/
1896 link->dc->hwss.edp_power_control(link, true);
1897 link->dc->hwss.edp_wait_for_hpd_ready(link, true);
1900 #if defined(CONFIG_DRM_AMD_DC_DCN)
1901 if (dp_get_link_encoding_format(&link_settings) == DP_128b_132b_ENCODING) {
1902 /* TODO - DP2.0 HW: calculate 32 symbol clock for HPO encoder */
1904 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk =
1905 link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
1906 if (state->clk_mgr && !apply_seamless_boot_optimization)
1907 state->clk_mgr->funcs->update_clocks(state->clk_mgr,
1911 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk =
1912 link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
1913 if (state->clk_mgr && !apply_seamless_boot_optimization)
1914 state->clk_mgr->funcs->update_clocks(state->clk_mgr,
1918 // during mode switch we do DP_SET_POWER off then on, and OUI is lost
1919 dpcd_set_source_specific_data(link);
1920 if (link->dpcd_sink_ext_caps.raw != 0)
1921 msleep(post_oui_delay);
1923 skip_video_pattern = true;
1925 if (link_settings.link_rate == LINK_RATE_LOW)
1926 skip_video_pattern = false;
1928 if (perform_link_training_with_retries(&link_settings,
1930 LINK_TRAINING_ATTEMPTS,
1932 pipe_ctx->stream->signal,
1934 link->cur_link_settings = link_settings;
1937 status = DC_FAIL_DP_LINK_TRAINING;
1940 if (link->preferred_training_settings.fec_enable)
1941 fec_enable = *link->preferred_training_settings.fec_enable;
1945 #if defined(CONFIG_DRM_AMD_DC_DCN)
1946 if (dp_get_link_encoding_format(&link_settings) == DP_8b_10b_ENCODING)
1947 dp_set_fec_enable(link, fec_enable);
1949 dp_set_fec_enable(link, fec_enable);
1952 // during mode set we do DP_SET_POWER off then on, aux writes are lost
1953 if (link->dpcd_sink_ext_caps.bits.oled == 1 ||
1954 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1 ||
1955 link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1) {
1956 dc_link_set_default_brightness_aux(link); // TODO: use cached if known
1957 if (link->dpcd_sink_ext_caps.bits.oled == 1)
1958 msleep(bl_oled_enable_delay);
1959 dc_link_backlight_enable_aux(link, true);
1965 static enum dc_status enable_link_edp(
1966 struct dc_state *state,
1967 struct pipe_ctx *pipe_ctx)
1969 enum dc_status status;
1971 status = enable_link_dp(state, pipe_ctx);
1976 static enum dc_status enable_link_dp_mst(
1977 struct dc_state *state,
1978 struct pipe_ctx *pipe_ctx)
1980 struct dc_link *link = pipe_ctx->stream->link;
1982 /* sink signal type after MST branch is MST. Multiple MST sinks
1983 * share one link. Link DP PHY is enable or training only once.
1985 if (link->link_status.link_active)
1988 /* clear payload table */
1989 dm_helpers_dp_mst_clear_payload_allocation_table(link->ctx, link);
1991 /* to make sure the pending down rep can be processed
1992 * before enabling the link
1994 dm_helpers_dp_mst_poll_pending_down_reply(link->ctx, link);
1996 /* set the sink to MST mode before enabling the link */
1997 dp_enable_mst_on_sink(link, true);
1999 return enable_link_dp(state, pipe_ctx);
2002 static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx,
2003 enum engine_id eng_id,
2004 struct ext_hdmi_settings *settings)
2006 bool result = false;
2008 struct integrated_info *integrated_info =
2009 pipe_ctx->stream->ctx->dc_bios->integrated_info;
2011 if (integrated_info == NULL)
2015 * Get retimer settings from sbios for passing SI eye test for DCE11
2016 * The setting values are varied based on board revision and port id
2017 * Therefore the setting values of each ports is passed by sbios.
2020 // Check if current bios contains ext Hdmi settings
2021 if (integrated_info->gpu_cap_info & 0x20) {
2023 case ENGINE_ID_DIGA:
2024 settings->slv_addr = integrated_info->dp0_ext_hdmi_slv_addr;
2025 settings->reg_num = integrated_info->dp0_ext_hdmi_6g_reg_num;
2026 settings->reg_num_6g = integrated_info->dp0_ext_hdmi_6g_reg_num;
2027 memmove(settings->reg_settings,
2028 integrated_info->dp0_ext_hdmi_reg_settings,
2029 sizeof(integrated_info->dp0_ext_hdmi_reg_settings));
2030 memmove(settings->reg_settings_6g,
2031 integrated_info->dp0_ext_hdmi_6g_reg_settings,
2032 sizeof(integrated_info->dp0_ext_hdmi_6g_reg_settings));
2035 case ENGINE_ID_DIGB:
2036 settings->slv_addr = integrated_info->dp1_ext_hdmi_slv_addr;
2037 settings->reg_num = integrated_info->dp1_ext_hdmi_6g_reg_num;
2038 settings->reg_num_6g = integrated_info->dp1_ext_hdmi_6g_reg_num;
2039 memmove(settings->reg_settings,
2040 integrated_info->dp1_ext_hdmi_reg_settings,
2041 sizeof(integrated_info->dp1_ext_hdmi_reg_settings));
2042 memmove(settings->reg_settings_6g,
2043 integrated_info->dp1_ext_hdmi_6g_reg_settings,
2044 sizeof(integrated_info->dp1_ext_hdmi_6g_reg_settings));
2047 case ENGINE_ID_DIGC:
2048 settings->slv_addr = integrated_info->dp2_ext_hdmi_slv_addr;
2049 settings->reg_num = integrated_info->dp2_ext_hdmi_6g_reg_num;
2050 settings->reg_num_6g = integrated_info->dp2_ext_hdmi_6g_reg_num;
2051 memmove(settings->reg_settings,
2052 integrated_info->dp2_ext_hdmi_reg_settings,
2053 sizeof(integrated_info->dp2_ext_hdmi_reg_settings));
2054 memmove(settings->reg_settings_6g,
2055 integrated_info->dp2_ext_hdmi_6g_reg_settings,
2056 sizeof(integrated_info->dp2_ext_hdmi_6g_reg_settings));
2059 case ENGINE_ID_DIGD:
2060 settings->slv_addr = integrated_info->dp3_ext_hdmi_slv_addr;
2061 settings->reg_num = integrated_info->dp3_ext_hdmi_6g_reg_num;
2062 settings->reg_num_6g = integrated_info->dp3_ext_hdmi_6g_reg_num;
2063 memmove(settings->reg_settings,
2064 integrated_info->dp3_ext_hdmi_reg_settings,
2065 sizeof(integrated_info->dp3_ext_hdmi_reg_settings));
2066 memmove(settings->reg_settings_6g,
2067 integrated_info->dp3_ext_hdmi_6g_reg_settings,
2068 sizeof(integrated_info->dp3_ext_hdmi_6g_reg_settings));
2075 if (result == true) {
2076 // Validate settings from bios integrated info table
2077 if (settings->slv_addr == 0)
2079 if (settings->reg_num > 9)
2081 if (settings->reg_num_6g > 3)
2084 for (i = 0; i < settings->reg_num; i++) {
2085 if (settings->reg_settings[i].i2c_reg_index > 0x20)
2089 for (i = 0; i < settings->reg_num_6g; i++) {
2090 if (settings->reg_settings_6g[i].i2c_reg_index > 0x20)
2099 static bool i2c_write(struct pipe_ctx *pipe_ctx,
2100 uint8_t address, uint8_t *buffer, uint32_t length)
2102 struct i2c_command cmd = {0};
2103 struct i2c_payload payload = {0};
2105 memset(&payload, 0, sizeof(payload));
2106 memset(&cmd, 0, sizeof(cmd));
2108 cmd.number_of_payloads = 1;
2109 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
2110 cmd.speed = pipe_ctx->stream->ctx->dc->caps.i2c_speed_in_khz;
2112 payload.address = address;
2113 payload.data = buffer;
2114 payload.length = length;
2115 payload.write = true;
2116 cmd.payloads = &payload;
2118 if (dm_helpers_submit_i2c(pipe_ctx->stream->ctx,
2119 pipe_ctx->stream->link, &cmd))
2125 static void write_i2c_retimer_setting(
2126 struct pipe_ctx *pipe_ctx,
2128 bool is_over_340mhz,
2129 struct ext_hdmi_settings *settings)
2131 uint8_t slave_address = (settings->slv_addr >> 1);
2133 const uint8_t apply_rx_tx_change = 0x4;
2134 uint8_t offset = 0xA;
2137 bool i2c_success = false;
2138 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
2140 memset(&buffer, 0, sizeof(buffer));
2142 /* Start Ext-Hdmi programming*/
2144 for (i = 0; i < settings->reg_num; i++) {
2145 /* Apply 3G settings */
2146 if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
2148 buffer[0] = settings->reg_settings[i].i2c_reg_index;
2149 buffer[1] = settings->reg_settings[i].i2c_reg_val;
2150 i2c_success = i2c_write(pipe_ctx, slave_address,
2151 buffer, sizeof(buffer));
2152 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2153 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
2154 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2157 goto i2c_write_fail;
2159 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
2160 * needs to be set to 1 on every 0xA-0xC write.
2162 if (settings->reg_settings[i].i2c_reg_index == 0xA ||
2163 settings->reg_settings[i].i2c_reg_index == 0xB ||
2164 settings->reg_settings[i].i2c_reg_index == 0xC) {
2166 /* Query current value from offset 0xA */
2167 if (settings->reg_settings[i].i2c_reg_index == 0xA)
2168 value = settings->reg_settings[i].i2c_reg_val;
2171 dal_ddc_service_query_ddc_data(
2172 pipe_ctx->stream->link->ddc,
2173 slave_address, &offset, 1, &value, 1);
2175 goto i2c_write_fail;
2179 /* Set APPLY_RX_TX_CHANGE bit to 1 */
2180 buffer[1] = value | apply_rx_tx_change;
2181 i2c_success = i2c_write(pipe_ctx, slave_address,
2182 buffer, sizeof(buffer));
2183 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2184 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2185 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2187 goto i2c_write_fail;
2192 /* Apply 3G settings */
2193 if (is_over_340mhz) {
2194 for (i = 0; i < settings->reg_num_6g; i++) {
2195 /* Apply 3G settings */
2196 if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
2198 buffer[0] = settings->reg_settings_6g[i].i2c_reg_index;
2199 buffer[1] = settings->reg_settings_6g[i].i2c_reg_val;
2200 i2c_success = i2c_write(pipe_ctx, slave_address,
2201 buffer, sizeof(buffer));
2202 RETIMER_REDRIVER_INFO("above 340Mhz: retimer write to slave_address = 0x%x,\
2203 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2204 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2207 goto i2c_write_fail;
2209 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
2210 * needs to be set to 1 on every 0xA-0xC write.
2212 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA ||
2213 settings->reg_settings_6g[i].i2c_reg_index == 0xB ||
2214 settings->reg_settings_6g[i].i2c_reg_index == 0xC) {
2216 /* Query current value from offset 0xA */
2217 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA)
2218 value = settings->reg_settings_6g[i].i2c_reg_val;
2221 dal_ddc_service_query_ddc_data(
2222 pipe_ctx->stream->link->ddc,
2223 slave_address, &offset, 1, &value, 1);
2225 goto i2c_write_fail;
2229 /* Set APPLY_RX_TX_CHANGE bit to 1 */
2230 buffer[1] = value | apply_rx_tx_change;
2231 i2c_success = i2c_write(pipe_ctx, slave_address,
2232 buffer, sizeof(buffer));
2233 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2234 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2235 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2237 goto i2c_write_fail;
2244 /* Program additional settings if using 640x480 resolution */
2246 /* Write offset 0xFF to 0x01 */
2249 i2c_success = i2c_write(pipe_ctx, slave_address,
2250 buffer, sizeof(buffer));
2251 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2252 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2253 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2255 goto i2c_write_fail;
2257 /* Write offset 0x00 to 0x23 */
2260 i2c_success = i2c_write(pipe_ctx, slave_address,
2261 buffer, sizeof(buffer));
2262 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2263 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2264 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2266 goto i2c_write_fail;
2268 /* Write offset 0xff to 0x00 */
2271 i2c_success = i2c_write(pipe_ctx, slave_address,
2272 buffer, sizeof(buffer));
2273 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2274 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2275 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2277 goto i2c_write_fail;
2284 DC_LOG_DEBUG("Set retimer failed");
2287 static void write_i2c_default_retimer_setting(
2288 struct pipe_ctx *pipe_ctx,
2290 bool is_over_340mhz)
2292 uint8_t slave_address = (0xBA >> 1);
2294 bool i2c_success = false;
2295 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
2297 memset(&buffer, 0, sizeof(buffer));
2299 /* Program Slave Address for tuning single integrity */
2300 /* Write offset 0x0A to 0x13 */
2303 i2c_success = i2c_write(pipe_ctx, slave_address,
2304 buffer, sizeof(buffer));
2305 RETIMER_REDRIVER_INFO("retimer writes default setting to slave_address = 0x%x,\
2306 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2307 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2309 goto i2c_write_fail;
2311 /* Write offset 0x0A to 0x17 */
2314 i2c_success = i2c_write(pipe_ctx, slave_address,
2315 buffer, sizeof(buffer));
2316 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2317 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2318 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2320 goto i2c_write_fail;
2322 /* Write offset 0x0B to 0xDA or 0xD8 */
2324 buffer[1] = is_over_340mhz ? 0xDA : 0xD8;
2325 i2c_success = i2c_write(pipe_ctx, slave_address,
2326 buffer, sizeof(buffer));
2327 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2328 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2329 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2331 goto i2c_write_fail;
2333 /* Write offset 0x0A to 0x17 */
2336 i2c_success = i2c_write(pipe_ctx, slave_address,
2337 buffer, sizeof(buffer));
2338 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2339 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
2340 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2342 goto i2c_write_fail;
2344 /* Write offset 0x0C to 0x1D or 0x91 */
2346 buffer[1] = is_over_340mhz ? 0x1D : 0x91;
2347 i2c_success = i2c_write(pipe_ctx, slave_address,
2348 buffer, sizeof(buffer));
2349 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2350 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2351 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2353 goto i2c_write_fail;
2355 /* Write offset 0x0A to 0x17 */
2358 i2c_success = i2c_write(pipe_ctx, slave_address,
2359 buffer, sizeof(buffer));
2360 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2361 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2362 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2364 goto i2c_write_fail;
2368 /* Program additional settings if using 640x480 resolution */
2370 /* Write offset 0xFF to 0x01 */
2373 i2c_success = i2c_write(pipe_ctx, slave_address,
2374 buffer, sizeof(buffer));
2375 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2376 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2377 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2379 goto i2c_write_fail;
2381 /* Write offset 0x00 to 0x23 */
2384 i2c_success = i2c_write(pipe_ctx, slave_address,
2385 buffer, sizeof(buffer));
2386 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2387 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
2388 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2390 goto i2c_write_fail;
2392 /* Write offset 0xff to 0x00 */
2395 i2c_success = i2c_write(pipe_ctx, slave_address,
2396 buffer, sizeof(buffer));
2397 RETIMER_REDRIVER_INFO("retimer write default setting to slave_addr = 0x%x,\
2398 offset = 0x%x, reg_val= 0x%x, i2c_success = %d end here\n",
2399 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2401 goto i2c_write_fail;
2407 DC_LOG_DEBUG("Set default retimer failed");
2410 static void write_i2c_redriver_setting(
2411 struct pipe_ctx *pipe_ctx,
2412 bool is_over_340mhz)
2414 uint8_t slave_address = (0xF0 >> 1);
2416 bool i2c_success = false;
2417 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
2419 memset(&buffer, 0, sizeof(buffer));
2421 // Program Slave Address for tuning single integrity
2425 buffer[6] = is_over_340mhz ? 0x4E : 0x4A;
2427 i2c_success = i2c_write(pipe_ctx, slave_address,
2428 buffer, sizeof(buffer));
2429 RETIMER_REDRIVER_INFO("redriver write 0 to all 16 reg offset expect following:\n\
2430 \t slave_addr = 0x%x, offset[3] = 0x%x, offset[4] = 0x%x,\
2431 offset[5] = 0x%x,offset[6] is_over_340mhz = 0x%x,\
2432 i2c_success = %d\n",
2433 slave_address, buffer[3], buffer[4], buffer[5], buffer[6], i2c_success?1:0);
2436 DC_LOG_DEBUG("Set redriver failed");
2439 static void disable_link(struct dc_link *link, enum signal_type signal)
2442 * TODO: implement call for dp_set_hw_test_pattern
2443 * it is needed for compliance testing
2446 /* Here we need to specify that encoder output settings
2447 * need to be calculated as for the set mode,
2448 * it will lead to querying dynamic link capabilities
2449 * which should be done before enable output
2452 if (dc_is_dp_signal(signal)) {
2454 #if defined(CONFIG_DRM_AMD_DC_DCN)
2455 struct dc_link_settings link_settings = link->cur_link_settings;
2457 if (dc_is_dp_sst_signal(signal))
2458 dp_disable_link_phy(link, signal);
2460 dp_disable_link_phy_mst(link, signal);
2462 if (dc_is_dp_sst_signal(signal) ||
2463 link->mst_stream_alloc_table.stream_count == 0) {
2464 #if defined(CONFIG_DRM_AMD_DC_DCN)
2465 if (dp_get_link_encoding_format(&link_settings) == DP_8b_10b_ENCODING) {
2466 dp_set_fec_enable(link, false);
2467 dp_set_fec_ready(link, false);
2470 dp_set_fec_enable(link, false);
2471 dp_set_fec_ready(link, false);
2475 if (signal != SIGNAL_TYPE_VIRTUAL)
2476 link->link_enc->funcs->disable_output(link->link_enc, signal);
2479 if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
2480 /* MST disable link only when no stream use the link */
2481 if (link->mst_stream_alloc_table.stream_count <= 0)
2482 link->link_status.link_active = false;
2484 link->link_status.link_active = false;
2488 static void enable_link_hdmi(struct pipe_ctx *pipe_ctx)
2490 struct dc_stream_state *stream = pipe_ctx->stream;
2491 struct dc_link *link = stream->link;
2492 enum dc_color_depth display_color_depth;
2493 enum engine_id eng_id;
2494 struct ext_hdmi_settings settings = {0};
2495 bool is_over_340mhz = false;
2496 bool is_vga_mode = (stream->timing.h_addressable == 640)
2497 && (stream->timing.v_addressable == 480);
2499 if (stream->phy_pix_clk == 0)
2500 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10;
2501 if (stream->phy_pix_clk > 340000)
2502 is_over_340mhz = true;
2504 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
2505 unsigned short masked_chip_caps = pipe_ctx->stream->link->chip_caps &
2506 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
2507 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {
2508 /* DP159, Retimer settings */
2509 eng_id = pipe_ctx->stream_res.stream_enc->id;
2511 if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) {
2512 write_i2c_retimer_setting(pipe_ctx,
2513 is_vga_mode, is_over_340mhz, &settings);
2515 write_i2c_default_retimer_setting(pipe_ctx,
2516 is_vga_mode, is_over_340mhz);
2518 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {
2519 /* PI3EQX1204, Redriver settings */
2520 write_i2c_redriver_setting(pipe_ctx, is_over_340mhz);
2524 if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
2525 dal_ddc_service_write_scdc_data(
2527 stream->phy_pix_clk,
2528 stream->timing.flags.LTE_340MCSC_SCRAMBLE);
2530 memset(&stream->link->cur_link_settings, 0,
2531 sizeof(struct dc_link_settings));
2533 display_color_depth = stream->timing.display_color_depth;
2534 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
2535 display_color_depth = COLOR_DEPTH_888;
2537 link->link_enc->funcs->enable_tmds_output(
2539 pipe_ctx->clock_source->id,
2540 display_color_depth,
2541 pipe_ctx->stream->signal,
2542 stream->phy_pix_clk);
2544 if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
2545 dal_ddc_service_read_scdc_data(link->ddc);
2548 static void enable_link_lvds(struct pipe_ctx *pipe_ctx)
2550 struct dc_stream_state *stream = pipe_ctx->stream;
2551 struct dc_link *link = stream->link;
2553 if (stream->phy_pix_clk == 0)
2554 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10;
2556 memset(&stream->link->cur_link_settings, 0,
2557 sizeof(struct dc_link_settings));
2559 link->link_enc->funcs->enable_lvds_output(
2561 pipe_ctx->clock_source->id,
2562 stream->phy_pix_clk);
2566 /****************************enable_link***********************************/
2567 static enum dc_status enable_link(
2568 struct dc_state *state,
2569 struct pipe_ctx *pipe_ctx)
2571 enum dc_status status = DC_ERROR_UNEXPECTED;
2572 struct dc_stream_state *stream = pipe_ctx->stream;
2573 struct dc_link *link = stream->link;
2575 /* There's some scenarios where driver is unloaded with display
2576 * still enabled. When driver is reloaded, it may cause a display
2577 * to not light up if there is a mismatch between old and new
2578 * link settings. Need to call disable first before enabling at
2579 * new link settings.
2581 if (link->link_status.link_active) {
2582 disable_link(link, pipe_ctx->stream->signal);
2585 switch (pipe_ctx->stream->signal) {
2586 case SIGNAL_TYPE_DISPLAY_PORT:
2587 status = enable_link_dp(state, pipe_ctx);
2589 case SIGNAL_TYPE_EDP:
2590 status = enable_link_edp(state, pipe_ctx);
2592 case SIGNAL_TYPE_DISPLAY_PORT_MST:
2593 status = enable_link_dp_mst(state, pipe_ctx);
2596 case SIGNAL_TYPE_DVI_SINGLE_LINK:
2597 case SIGNAL_TYPE_DVI_DUAL_LINK:
2598 case SIGNAL_TYPE_HDMI_TYPE_A:
2599 enable_link_hdmi(pipe_ctx);
2602 case SIGNAL_TYPE_LVDS:
2603 enable_link_lvds(pipe_ctx);
2606 case SIGNAL_TYPE_VIRTUAL:
2613 if (status == DC_OK)
2614 pipe_ctx->stream->link->link_status.link_active = true;
2619 static uint32_t get_timing_pixel_clock_100hz(const struct dc_crtc_timing *timing)
2622 uint32_t pxl_clk = timing->pix_clk_100hz;
2624 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
2626 else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
2627 pxl_clk = pxl_clk * 2 / 3;
2629 if (timing->display_color_depth == COLOR_DEPTH_101010)
2630 pxl_clk = pxl_clk * 10 / 8;
2631 else if (timing->display_color_depth == COLOR_DEPTH_121212)
2632 pxl_clk = pxl_clk * 12 / 8;
2637 static bool dp_active_dongle_validate_timing(
2638 const struct dc_crtc_timing *timing,
2639 const struct dpcd_caps *dpcd_caps)
2641 const struct dc_dongle_caps *dongle_caps = &dpcd_caps->dongle_caps;
2643 switch (dpcd_caps->dongle_type) {
2644 case DISPLAY_DONGLE_DP_VGA_CONVERTER:
2645 case DISPLAY_DONGLE_DP_DVI_CONVERTER:
2646 case DISPLAY_DONGLE_DP_DVI_DONGLE:
2647 if (timing->pixel_encoding == PIXEL_ENCODING_RGB)
2655 #if defined(CONFIG_DRM_AMD_DC_DCN)
2656 if (dpcd_caps->dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER &&
2657 dongle_caps->extendedCapValid == true) {
2659 if (dpcd_caps->dongle_type != DISPLAY_DONGLE_DP_HDMI_CONVERTER ||
2660 dongle_caps->extendedCapValid == false)
2664 /* Check Pixel Encoding */
2665 switch (timing->pixel_encoding) {
2666 case PIXEL_ENCODING_RGB:
2667 case PIXEL_ENCODING_YCBCR444:
2669 case PIXEL_ENCODING_YCBCR422:
2670 if (!dongle_caps->is_dp_hdmi_ycbcr422_pass_through)
2673 case PIXEL_ENCODING_YCBCR420:
2674 if (!dongle_caps->is_dp_hdmi_ycbcr420_pass_through)
2678 /* Invalid Pixel Encoding*/
2682 switch (timing->display_color_depth) {
2683 case COLOR_DEPTH_666:
2684 case COLOR_DEPTH_888:
2685 /*888 and 666 should always be supported*/
2687 case COLOR_DEPTH_101010:
2688 if (dongle_caps->dp_hdmi_max_bpc < 10)
2691 case COLOR_DEPTH_121212:
2692 if (dongle_caps->dp_hdmi_max_bpc < 12)
2695 case COLOR_DEPTH_141414:
2696 case COLOR_DEPTH_161616:
2698 /* These color depths are currently not supported */
2702 if (get_timing_pixel_clock_100hz(timing) > (dongle_caps->dp_hdmi_max_pixel_clk_in_khz * 10))
2705 #if defined(CONFIG_DRM_AMD_DC_DCN)
2708 if (dpcd_caps->channel_coding_cap.bits.DP_128b_132b_SUPPORTED == 0 &&
2709 dpcd_caps->dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_PASSTHROUGH_SUPPORT == 0 &&
2710 dongle_caps->dfp_cap_ext.supported) {
2712 if (dongle_caps->dfp_cap_ext.max_pixel_rate_in_mps < (timing->pix_clk_100hz / 10000))
2715 if (dongle_caps->dfp_cap_ext.max_video_h_active_width < timing->h_addressable)
2718 if (dongle_caps->dfp_cap_ext.max_video_v_active_height < timing->v_addressable)
2721 if (timing->pixel_encoding == PIXEL_ENCODING_RGB) {
2722 if (!dongle_caps->dfp_cap_ext.encoding_format_caps.support_rgb)
2724 if (timing->display_color_depth == COLOR_DEPTH_666 &&
2725 !dongle_caps->dfp_cap_ext.rgb_color_depth_caps.support_6bpc)
2727 else if (timing->display_color_depth == COLOR_DEPTH_888 &&
2728 !dongle_caps->dfp_cap_ext.rgb_color_depth_caps.support_8bpc)
2730 else if (timing->display_color_depth == COLOR_DEPTH_101010 &&
2731 !dongle_caps->dfp_cap_ext.rgb_color_depth_caps.support_10bpc)
2733 else if (timing->display_color_depth == COLOR_DEPTH_121212 &&
2734 !dongle_caps->dfp_cap_ext.rgb_color_depth_caps.support_12bpc)
2736 else if (timing->display_color_depth == COLOR_DEPTH_161616 &&
2737 !dongle_caps->dfp_cap_ext.rgb_color_depth_caps.support_16bpc)
2739 } else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR444) {
2740 if (!dongle_caps->dfp_cap_ext.encoding_format_caps.support_rgb)
2742 if (timing->display_color_depth == COLOR_DEPTH_888 &&
2743 !dongle_caps->dfp_cap_ext.ycbcr444_color_depth_caps.support_8bpc)
2745 else if (timing->display_color_depth == COLOR_DEPTH_101010 &&
2746 !dongle_caps->dfp_cap_ext.ycbcr444_color_depth_caps.support_10bpc)
2748 else if (timing->display_color_depth == COLOR_DEPTH_121212 &&
2749 !dongle_caps->dfp_cap_ext.ycbcr444_color_depth_caps.support_12bpc)
2751 else if (timing->display_color_depth == COLOR_DEPTH_161616 &&
2752 !dongle_caps->dfp_cap_ext.ycbcr444_color_depth_caps.support_16bpc)
2754 } else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
2755 if (!dongle_caps->dfp_cap_ext.encoding_format_caps.support_rgb)
2757 if (timing->display_color_depth == COLOR_DEPTH_888 &&
2758 !dongle_caps->dfp_cap_ext.ycbcr422_color_depth_caps.support_8bpc)
2760 else if (timing->display_color_depth == COLOR_DEPTH_101010 &&
2761 !dongle_caps->dfp_cap_ext.ycbcr422_color_depth_caps.support_10bpc)
2763 else if (timing->display_color_depth == COLOR_DEPTH_121212 &&
2764 !dongle_caps->dfp_cap_ext.ycbcr422_color_depth_caps.support_12bpc)
2766 else if (timing->display_color_depth == COLOR_DEPTH_161616 &&
2767 !dongle_caps->dfp_cap_ext.ycbcr422_color_depth_caps.support_16bpc)
2769 } else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) {
2770 if (!dongle_caps->dfp_cap_ext.encoding_format_caps.support_rgb)
2772 if (timing->display_color_depth == COLOR_DEPTH_888 &&
2773 !dongle_caps->dfp_cap_ext.ycbcr420_color_depth_caps.support_8bpc)
2775 else if (timing->display_color_depth == COLOR_DEPTH_101010 &&
2776 !dongle_caps->dfp_cap_ext.ycbcr420_color_depth_caps.support_10bpc)
2778 else if (timing->display_color_depth == COLOR_DEPTH_121212 &&
2779 !dongle_caps->dfp_cap_ext.ycbcr420_color_depth_caps.support_12bpc)
2781 else if (timing->display_color_depth == COLOR_DEPTH_161616 &&
2782 !dongle_caps->dfp_cap_ext.ycbcr420_color_depth_caps.support_16bpc)
2791 enum dc_status dc_link_validate_mode_timing(
2792 const struct dc_stream_state *stream,
2793 struct dc_link *link,
2794 const struct dc_crtc_timing *timing)
2796 uint32_t max_pix_clk = stream->link->dongle_max_pix_clk * 10;
2797 struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
2799 /* A hack to avoid failing any modes for EDID override feature on
2800 * topology change such as lower quality cable for DP or different dongle
2802 if (link->remote_sinks[0] && link->remote_sinks[0]->sink_signal == SIGNAL_TYPE_VIRTUAL)
2805 /* Passive Dongle */
2806 if (max_pix_clk != 0 && get_timing_pixel_clock_100hz(timing) > max_pix_clk)
2807 return DC_EXCEED_DONGLE_CAP;
2810 if (!dp_active_dongle_validate_timing(timing, dpcd_caps))
2811 return DC_EXCEED_DONGLE_CAP;
2813 switch (stream->signal) {
2814 case SIGNAL_TYPE_EDP:
2815 case SIGNAL_TYPE_DISPLAY_PORT:
2816 if (!dp_validate_mode_timing(
2819 return DC_NO_DP_LINK_BANDWIDTH;
2829 static struct abm *get_abm_from_stream_res(const struct dc_link *link)
2832 struct dc *dc = NULL;
2833 struct abm *abm = NULL;
2835 if (!link || !link->ctx)
2840 for (i = 0; i < MAX_PIPES; i++) {
2841 struct pipe_ctx pipe_ctx = dc->current_state->res_ctx.pipe_ctx[i];
2842 struct dc_stream_state *stream = pipe_ctx.stream;
2844 if (stream && stream->link == link) {
2845 abm = pipe_ctx.stream_res.abm;
2852 int dc_link_get_backlight_level(const struct dc_link *link)
2854 struct abm *abm = get_abm_from_stream_res(link);
2855 struct panel_cntl *panel_cntl = link->panel_cntl;
2856 struct dc *dc = link->ctx->dc;
2857 struct dmcu *dmcu = dc->res_pool->dmcu;
2858 bool fw_set_brightness = true;
2861 fw_set_brightness = dmcu->funcs->is_dmcu_initialized(dmcu);
2863 if (!fw_set_brightness && panel_cntl->funcs->get_current_backlight)
2864 return panel_cntl->funcs->get_current_backlight(panel_cntl);
2865 else if (abm != NULL && abm->funcs->get_current_backlight != NULL)
2866 return (int) abm->funcs->get_current_backlight(abm);
2868 return DC_ERROR_UNEXPECTED;
2871 int dc_link_get_target_backlight_pwm(const struct dc_link *link)
2873 struct abm *abm = get_abm_from_stream_res(link);
2875 if (abm == NULL || abm->funcs->get_target_backlight == NULL)
2876 return DC_ERROR_UNEXPECTED;
2878 return (int) abm->funcs->get_target_backlight(abm);
2881 static struct pipe_ctx *get_pipe_from_link(const struct dc_link *link)
2884 struct dc *dc = link->ctx->dc;
2885 struct pipe_ctx *pipe_ctx = NULL;
2887 for (i = 0; i < MAX_PIPES; i++) {
2888 if (dc->current_state->res_ctx.pipe_ctx[i].stream) {
2889 if (dc->current_state->res_ctx.pipe_ctx[i].stream->link == link) {
2890 pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
2899 bool dc_link_set_backlight_level(const struct dc_link *link,
2900 uint32_t backlight_pwm_u16_16,
2901 uint32_t frame_ramp)
2903 struct dc *dc = link->ctx->dc;
2905 DC_LOGGER_INIT(link->ctx->logger);
2906 DC_LOG_BACKLIGHT("New Backlight level: %d (0x%X)\n",
2907 backlight_pwm_u16_16, backlight_pwm_u16_16);
2909 if (dc_is_embedded_signal(link->connector_signal)) {
2910 struct pipe_ctx *pipe_ctx = get_pipe_from_link(link);
2913 /* Disable brightness ramping when the display is blanked
2914 * as it can hang the DMCU
2916 if (pipe_ctx->plane_state == NULL)
2922 dc->hwss.set_backlight_level(
2924 backlight_pwm_u16_16,
2930 bool dc_link_set_psr_allow_active(struct dc_link *link, const bool *allow_active,
2931 bool wait, bool force_static, const unsigned int *power_opts)
2933 struct dc *dc = link->ctx->dc;
2934 struct dmcu *dmcu = dc->res_pool->dmcu;
2935 struct dmub_psr *psr = dc->res_pool->psr;
2936 unsigned int panel_inst;
2938 if (psr == NULL && force_static)
2941 if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
2944 /* Set power optimization flag */
2945 if (power_opts && link->psr_settings.psr_power_opt != *power_opts) {
2946 link->psr_settings.psr_power_opt = *power_opts;
2948 if (psr != NULL && link->psr_settings.psr_feature_enabled && psr->funcs->psr_set_power_opt)
2949 psr->funcs->psr_set_power_opt(psr, link->psr_settings.psr_power_opt);
2952 /* Enable or Disable PSR */
2953 if (allow_active && link->psr_settings.psr_allow_active != *allow_active) {
2954 link->psr_settings.psr_allow_active = *allow_active;
2956 #if defined(CONFIG_DRM_AMD_DC_DCN)
2957 if (!link->psr_settings.psr_allow_active)
2961 if (psr != NULL && link->psr_settings.psr_feature_enabled) {
2962 if (force_static && psr->funcs->psr_force_static)
2963 psr->funcs->psr_force_static(psr, panel_inst);
2964 psr->funcs->psr_enable(psr, link->psr_settings.psr_allow_active, wait, panel_inst);
2965 } else if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu)) &&
2966 link->psr_settings.psr_feature_enabled)
2967 dmcu->funcs->set_psr_enable(dmcu, link->psr_settings.psr_allow_active, wait);
2975 bool dc_link_get_psr_state(const struct dc_link *link, enum dc_psr_state *state)
2977 struct dc *dc = link->ctx->dc;
2978 struct dmcu *dmcu = dc->res_pool->dmcu;
2979 struct dmub_psr *psr = dc->res_pool->psr;
2980 unsigned int panel_inst;
2982 if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
2985 if (psr != NULL && link->psr_settings.psr_feature_enabled)
2986 psr->funcs->psr_get_state(psr, state, panel_inst);
2987 else if (dmcu != NULL && link->psr_settings.psr_feature_enabled)
2988 dmcu->funcs->get_psr_state(dmcu, state);
2993 static inline enum physical_phy_id
2994 transmitter_to_phy_id(enum transmitter transmitter_value)
2996 switch (transmitter_value) {
2997 case TRANSMITTER_UNIPHY_A:
2999 case TRANSMITTER_UNIPHY_B:
3001 case TRANSMITTER_UNIPHY_C:
3003 case TRANSMITTER_UNIPHY_D:
3005 case TRANSMITTER_UNIPHY_E:
3007 case TRANSMITTER_UNIPHY_F:
3009 case TRANSMITTER_NUTMEG_CRT:
3011 case TRANSMITTER_TRAVIS_CRT:
3013 case TRANSMITTER_TRAVIS_LCD:
3015 case TRANSMITTER_UNIPHY_G:
3017 case TRANSMITTER_COUNT:
3019 case TRANSMITTER_UNKNOWN:
3020 return PHYLD_UNKNOWN;
3022 WARN_ONCE(1, "Unknown transmitter value %d\n",
3024 return PHYLD_UNKNOWN;
3028 bool dc_link_setup_psr(struct dc_link *link,
3029 const struct dc_stream_state *stream, struct psr_config *psr_config,
3030 struct psr_context *psr_context)
3034 struct dmub_psr *psr;
3036 unsigned int panel_inst;
3037 /* updateSinkPsrDpcdConfig*/
3038 union dpcd_psr_configuration psr_configuration;
3040 psr_context->controllerId = CONTROLLER_ID_UNDEFINED;
3046 dmcu = dc->res_pool->dmcu;
3047 psr = dc->res_pool->psr;
3052 if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
3056 memset(&psr_configuration, 0, sizeof(psr_configuration));
3058 psr_configuration.bits.ENABLE = 1;
3059 psr_configuration.bits.CRC_VERIFICATION = 1;
3060 psr_configuration.bits.FRAME_CAPTURE_INDICATION =
3061 psr_config->psr_frame_capture_indication_req;
3063 /* Check for PSR v2*/
3064 if (psr_config->psr_version == 0x2) {
3065 /* For PSR v2 selective update.
3066 * Indicates whether sink should start capturing
3067 * immediately following active scan line,
3068 * or starting with the 2nd active scan line.
3070 psr_configuration.bits.LINE_CAPTURE_INDICATION = 0;
3071 /*For PSR v2, determines whether Sink should generate
3072 * IRQ_HPD when CRC mismatch is detected.
3074 psr_configuration.bits.IRQ_HPD_WITH_CRC_ERROR = 1;
3077 dm_helpers_dp_write_dpcd(
3081 &psr_configuration.raw,
3082 sizeof(psr_configuration.raw));
3084 psr_context->channel = link->ddc->ddc_pin->hw_info.ddc_channel;
3085 psr_context->transmitterId = link->link_enc->transmitter;
3086 psr_context->engineId = link->link_enc->preferred_engine;
3088 for (i = 0; i < MAX_PIPES; i++) {
3089 if (dc->current_state->res_ctx.pipe_ctx[i].stream
3091 /* dmcu -1 for all controller id values,
3094 psr_context->controllerId =
3095 dc->current_state->res_ctx.
3096 pipe_ctx[i].stream_res.tg->inst + 1;
3101 /* Hardcoded for now. Can be Pcie or Uniphy (or Unknown)*/
3102 psr_context->phyType = PHY_TYPE_UNIPHY;
3103 /*PhyId is associated with the transmitter id*/
3104 psr_context->smuPhyId =
3105 transmitter_to_phy_id(link->link_enc->transmitter);
3107 psr_context->crtcTimingVerticalTotal = stream->timing.v_total;
3108 psr_context->vsync_rate_hz = div64_u64(div64_u64((stream->
3109 timing.pix_clk_100hz * 100),
3110 stream->timing.v_total),
3111 stream->timing.h_total);
3113 psr_context->psrSupportedDisplayConfig = true;
3114 psr_context->psrExitLinkTrainingRequired =
3115 psr_config->psr_exit_link_training_required;
3116 psr_context->sdpTransmitLineNumDeadline =
3117 psr_config->psr_sdp_transmit_line_num_deadline;
3118 psr_context->psrFrameCaptureIndicationReq =
3119 psr_config->psr_frame_capture_indication_req;
3121 psr_context->skipPsrWaitForPllLock = 0; /* only = 1 in KV */
3123 psr_context->numberOfControllers =
3124 link->dc->res_pool->timing_generator_count;
3126 psr_context->rfb_update_auto_en = true;
3128 /* 2 frames before enter PSR. */
3129 psr_context->timehyst_frames = 2;
3131 * (units in 100 lines, i.e. a value of 1 represents 100 lines)
3133 psr_context->hyst_lines = stream->timing.v_total / 2 / 100;
3134 psr_context->aux_repeats = 10;
3136 psr_context->psr_level.u32all = 0;
3138 /*skip power down the single pipe since it blocks the cstate*/
3139 #if defined(CONFIG_DRM_AMD_DC_DCN)
3140 if (link->ctx->asic_id.chip_family >= FAMILY_RV) {
3141 psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true;
3142 if (link->ctx->asic_id.chip_family == FAMILY_YELLOW_CARP && !dc->debug.disable_z10)
3143 psr_context->psr_level.bits.SKIP_CRTC_DISABLE = false;
3146 if (link->ctx->asic_id.chip_family >= FAMILY_RV)
3147 psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true;
3150 /* SMU will perform additional powerdown sequence.
3151 * For unsupported ASICs, set psr_level flag to skip PSR
3152 * static screen notification to SMU.
3153 * (Always set for DAL2, did not check ASIC)
3155 psr_context->allow_smu_optimizations = psr_config->allow_smu_optimizations;
3156 psr_context->allow_multi_disp_optimizations = psr_config->allow_multi_disp_optimizations;
3158 /* Complete PSR entry before aborting to prevent intermittent
3159 * freezes on certain eDPs
3161 psr_context->psr_level.bits.DISABLE_PSR_ENTRY_ABORT = 1;
3163 /* Controls additional delay after remote frame capture before
3164 * continuing power down, default = 0
3166 psr_context->frame_delay = 0;
3169 link->psr_settings.psr_feature_enabled = psr->funcs->psr_copy_settings(psr,
3170 link, psr_context, panel_inst);
3172 link->psr_settings.psr_feature_enabled = dmcu->funcs->setup_psr(dmcu, link, psr_context);
3174 /* psr_enabled == 0 indicates setup_psr did not succeed, but this
3175 * should not happen since firmware should be running at this point
3177 if (link->psr_settings.psr_feature_enabled == 0)
3184 void dc_link_get_psr_residency(const struct dc_link *link, uint32_t *residency)
3186 struct dc *dc = link->ctx->dc;
3187 struct dmub_psr *psr = dc->res_pool->psr;
3188 unsigned int panel_inst;
3190 if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
3193 /* PSR residency measurements only supported on DMCUB */
3194 if (psr != NULL && link->psr_settings.psr_feature_enabled)
3195 psr->funcs->psr_get_residency(psr, residency, panel_inst);
3200 const struct dc_link_status *dc_link_get_status(const struct dc_link *link)
3202 return &link->link_status;
3205 void core_link_resume(struct dc_link *link)
3207 if (link->connector_signal != SIGNAL_TYPE_VIRTUAL)
3208 program_hpd_filter(link);
3211 static struct fixed31_32 get_pbn_per_slot(struct dc_stream_state *stream)
3213 struct fixed31_32 mbytes_per_sec;
3214 uint32_t link_rate_in_mbytes_per_sec = dc_link_bandwidth_kbps(stream->link,
3215 &stream->link->cur_link_settings);
3216 link_rate_in_mbytes_per_sec /= 8000; /* Kbits to MBytes */
3218 mbytes_per_sec = dc_fixpt_from_int(link_rate_in_mbytes_per_sec);
3220 return dc_fixpt_div_int(mbytes_per_sec, 54);
3223 static struct fixed31_32 get_pbn_from_bw_in_kbps(uint64_t kbps)
3225 struct fixed31_32 peak_kbps;
3226 uint32_t numerator = 0;
3227 uint32_t denominator = 1;
3230 * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
3231 * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on
3232 * common multiplier to render an integer PBN for all link rate/lane
3233 * counts combinations
3235 * peak_kbps *= (1006/1000)
3236 * peak_kbps *= (64/54)
3237 * peak_kbps *= 8 convert to bytes
3240 numerator = 64 * PEAK_FACTOR_X1000;
3241 denominator = 54 * 8 * 1000 * 1000;
3243 peak_kbps = dc_fixpt_from_fraction(kbps, denominator);
3248 static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx)
3252 kbps = dc_bandwidth_in_kbps_from_timing(&pipe_ctx->stream->timing);
3253 return get_pbn_from_bw_in_kbps(kbps);
3256 static void update_mst_stream_alloc_table(
3257 struct dc_link *link,
3258 struct stream_encoder *stream_enc,
3259 #if defined(CONFIG_DRM_AMD_DC_DCN)
3260 struct hpo_dp_stream_encoder *hpo_dp_stream_enc, // TODO: Rename stream_enc to dio_stream_enc?
3262 const struct dp_mst_stream_allocation_table *proposed_table)
3264 struct link_mst_stream_allocation work_table[MAX_CONTROLLER_NUM] = { 0 };
3265 struct link_mst_stream_allocation *dc_alloc;
3270 /* if DRM proposed_table has more than one new payload */
3271 ASSERT(proposed_table->stream_count -
3272 link->mst_stream_alloc_table.stream_count < 2);
3274 /* copy proposed_table to link, add stream encoder */
3275 for (i = 0; i < proposed_table->stream_count; i++) {
3277 for (j = 0; j < link->mst_stream_alloc_table.stream_count; j++) {
3279 &link->mst_stream_alloc_table.stream_allocations[j];
3281 if (dc_alloc->vcp_id ==
3282 proposed_table->stream_allocations[i].vcp_id) {
3284 work_table[i] = *dc_alloc;
3285 work_table[i].slot_count = proposed_table->stream_allocations[i].slot_count;
3286 break; /* exit j loop */
3291 if (j == link->mst_stream_alloc_table.stream_count) {
3292 work_table[i].vcp_id =
3293 proposed_table->stream_allocations[i].vcp_id;
3294 work_table[i].slot_count =
3295 proposed_table->stream_allocations[i].slot_count;
3296 work_table[i].stream_enc = stream_enc;
3297 #if defined(CONFIG_DRM_AMD_DC_DCN)
3298 work_table[i].hpo_dp_stream_enc = hpo_dp_stream_enc;
3303 /* update link->mst_stream_alloc_table with work_table */
3304 link->mst_stream_alloc_table.stream_count =
3305 proposed_table->stream_count;
3306 for (i = 0; i < MAX_CONTROLLER_NUM; i++)
3307 link->mst_stream_alloc_table.stream_allocations[i] =
3310 #if defined(CONFIG_DRM_AMD_DC_DCN)
3311 static void dc_log_vcp_x_y(const struct dc_link *link, struct fixed31_32 avg_time_slots_per_mtp)
3313 const uint32_t VCP_Y_PRECISION = 1000;
3314 uint64_t vcp_x, vcp_y;
3316 // Add 0.5*(1/VCP_Y_PRECISION) to round up to decimal precision
3317 avg_time_slots_per_mtp = dc_fixpt_add(
3318 avg_time_slots_per_mtp, dc_fixpt_from_fraction(1, 2 * VCP_Y_PRECISION));
3320 vcp_x = dc_fixpt_floor(avg_time_slots_per_mtp);
3321 vcp_y = dc_fixpt_floor(
3323 dc_fixpt_sub_int(avg_time_slots_per_mtp, dc_fixpt_floor(avg_time_slots_per_mtp)),
3326 if (link->type == dc_connection_mst_branch)
3327 DC_LOG_DP2("MST Update Payload: set_throttled_vcp_size slot X.Y for MST stream "
3328 "X: %lld Y: %lld/%d", vcp_x, vcp_y, VCP_Y_PRECISION);
3330 DC_LOG_DP2("SST Update Payload: set_throttled_vcp_size slot X.Y for SST stream "
3331 "X: %lld Y: %lld/%d", vcp_x, vcp_y, VCP_Y_PRECISION);
3335 * Payload allocation/deallocation for SST introduced in DP2.0
3337 enum dc_status dc_link_update_sst_payload(struct pipe_ctx *pipe_ctx, bool allocate)
3339 struct dc_stream_state *stream = pipe_ctx->stream;
3340 struct dc_link *link = stream->link;
3341 struct hpo_dp_link_encoder *hpo_dp_link_encoder = link->hpo_dp_link_enc;
3342 struct hpo_dp_stream_encoder *hpo_dp_stream_encoder = pipe_ctx->stream_res.hpo_dp_stream_enc;
3343 struct link_mst_stream_allocation_table proposed_table = {0};
3344 struct fixed31_32 avg_time_slots_per_mtp;
3345 DC_LOGGER_INIT(link->ctx->logger);
3347 /* slot X.Y for SST payload deallocate */
3349 avg_time_slots_per_mtp = dc_fixpt_from_int(0);
3351 dc_log_vcp_x_y(link, avg_time_slots_per_mtp);
3353 hpo_dp_link_encoder->funcs->set_throttled_vcp_size(
3354 hpo_dp_link_encoder,
3355 hpo_dp_stream_encoder->inst,
3356 avg_time_slots_per_mtp);
3359 /* calculate VC payload and update branch with new payload allocation table*/
3360 if (!dpcd_write_128b_132b_sst_payload_allocation_table(
3365 DC_LOG_ERROR("SST Update Payload: Failed to update "
3366 "allocation table for "
3368 pipe_ctx->pipe_idx);
3371 proposed_table.stream_allocations[0].hpo_dp_stream_enc = hpo_dp_stream_encoder;
3373 ASSERT(proposed_table.stream_count == 1);
3375 //TODO - DP2.0 Logging: Instead of hpo_dp_stream_enc pointer, log instance id
3376 DC_LOG_DP2("SST Update Payload: hpo_dp_stream_enc: %p "
3379 (void *) proposed_table.stream_allocations[0].hpo_dp_stream_enc,
3380 proposed_table.stream_allocations[0].vcp_id,
3381 proposed_table.stream_allocations[0].slot_count);
3383 /* program DP source TX for payload */
3384 hpo_dp_link_encoder->funcs->update_stream_allocation_table(
3385 hpo_dp_link_encoder,
3388 /* poll for ACT handled */
3389 if (!dpcd_poll_for_allocation_change_trigger(link)) {
3390 // Failures will result in blackscreen and errors logged
3391 BREAK_TO_DEBUGGER();
3394 /* slot X.Y for SST payload allocate */
3396 avg_time_slots_per_mtp = calculate_sst_avg_time_slots_per_mtp(stream, link);
3398 dc_log_vcp_x_y(link, avg_time_slots_per_mtp);
3400 hpo_dp_link_encoder->funcs->set_throttled_vcp_size(
3401 hpo_dp_link_encoder,
3402 hpo_dp_stream_encoder->inst,
3403 avg_time_slots_per_mtp);
3406 /* Always return DC_OK.
3407 * If part of sequence fails, log failure(s) and show blackscreen
3413 /* convert link_mst_stream_alloc_table to dm dp_mst_stream_alloc_table
3414 * because stream_encoder is not exposed to dm
3416 enum dc_status dc_link_allocate_mst_payload(struct pipe_ctx *pipe_ctx)
3418 struct dc_stream_state *stream = pipe_ctx->stream;
3419 struct dc_link *link = stream->link;
3420 struct link_encoder *link_encoder = NULL;
3421 struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
3422 #if defined(CONFIG_DRM_AMD_DC_DCN)
3423 struct hpo_dp_link_encoder *hpo_dp_link_encoder = link->hpo_dp_link_enc;
3424 struct hpo_dp_stream_encoder *hpo_dp_stream_encoder = pipe_ctx->stream_res.hpo_dp_stream_enc;
3426 struct dp_mst_stream_allocation_table proposed_table = {0};
3427 struct fixed31_32 avg_time_slots_per_mtp;
3428 struct fixed31_32 pbn;
3429 struct fixed31_32 pbn_per_slot;
3431 enum act_return_status ret;
3432 DC_LOGGER_INIT(link->ctx->logger);
3434 /* Link encoder may have been dynamically assigned to non-physical display endpoint. */
3435 if (link->ep_type == DISPLAY_ENDPOINT_PHY)
3436 link_encoder = link->link_enc;
3437 else if (link->dc->res_pool->funcs->link_encs_assign)
3438 link_encoder = link_enc_cfg_get_link_enc_used_by_stream(pipe_ctx->stream->ctx->dc, stream);
3439 ASSERT(link_encoder);
3441 /* enable_link_dp_mst already check link->enabled_stream_count
3442 * and stream is in link->stream[]. This is called during set mode,
3443 * stream_enc is available.
3446 /* get calculate VC payload for stream: stream_alloc */
3447 if (dm_helpers_dp_mst_write_payload_allocation_table(
3452 update_mst_stream_alloc_table(
3453 #if defined(CONFIG_DRM_AMD_DC_DCN)
3455 pipe_ctx->stream_res.stream_enc,
3456 pipe_ctx->stream_res.hpo_dp_stream_enc,
3459 link, pipe_ctx->stream_res.stream_enc, &proposed_table);
3463 DC_LOG_WARNING("Failed to update"
3464 "MST allocation table for"
3466 pipe_ctx->pipe_idx);
3469 "stream_count: %d: \n ",
3471 link->mst_stream_alloc_table.stream_count);
3473 for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
3474 #if defined(CONFIG_DRM_AMD_DC_DCN)
3475 DC_LOG_MST("stream_enc[%d]: %p "
3476 "stream[%d].hpo_dp_stream_enc: %p "
3477 "stream[%d].vcp_id: %d "
3478 "stream[%d].slot_count: %d\n",
3480 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
3482 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc,
3484 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
3486 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
3488 DC_LOG_MST("stream_enc[%d]: %p "
3489 "stream[%d].vcp_id: %d "
3490 "stream[%d].slot_count: %d\n",
3492 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
3494 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
3496 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
3500 ASSERT(proposed_table.stream_count > 0);
3502 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) {
3503 static enum dc_status status;
3504 uint8_t mst_alloc_slots = 0, prev_mst_slots_in_use = 0xFF;
3506 for (i = 0; i < link->mst_stream_alloc_table.stream_count; i++)
3507 mst_alloc_slots += link->mst_stream_alloc_table.stream_allocations[i].slot_count;
3509 status = dc_process_dmub_set_mst_slots(link->dc, link->link_index,
3510 mst_alloc_slots, &prev_mst_slots_in_use);
3511 ASSERT(status == DC_OK);
3512 DC_LOG_MST("dpia : status[%d]: alloc_slots[%d]: used_slots[%d]\n",
3513 status, mst_alloc_slots, prev_mst_slots_in_use);
3516 /* program DP source TX for payload */
3517 #if defined(CONFIG_DRM_AMD_DC_DCN)
3518 switch (dp_get_link_encoding_format(&link->cur_link_settings)) {
3519 case DP_8b_10b_ENCODING:
3520 link_encoder->funcs->update_mst_stream_allocation_table(
3522 &link->mst_stream_alloc_table);
3524 case DP_128b_132b_ENCODING:
3525 hpo_dp_link_encoder->funcs->update_stream_allocation_table(
3526 hpo_dp_link_encoder,
3527 &link->mst_stream_alloc_table);
3529 case DP_UNKNOWN_ENCODING:
3530 DC_LOG_ERROR("Failure: unknown encoding format\n");
3531 return DC_ERROR_UNEXPECTED;
3534 link_encoder->funcs->update_mst_stream_allocation_table(
3536 &link->mst_stream_alloc_table);
3539 /* send down message */
3540 ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger(
3544 if (ret != ACT_LINK_LOST) {
3545 dm_helpers_dp_mst_send_payload_allocation(
3551 /* slot X.Y for only current stream */
3552 pbn_per_slot = get_pbn_per_slot(stream);
3553 if (pbn_per_slot.value == 0) {
3554 DC_LOG_ERROR("Failure: pbn_per_slot==0 not allowed. Cannot continue, returning DC_UNSUPPORTED_VALUE.\n");
3555 return DC_UNSUPPORTED_VALUE;
3557 pbn = get_pbn_from_timing(pipe_ctx);
3558 avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot);
3560 #if defined(CONFIG_DRM_AMD_DC_DCN)
3561 switch (dp_get_link_encoding_format(&link->cur_link_settings)) {
3562 case DP_8b_10b_ENCODING:
3563 stream_encoder->funcs->set_throttled_vcp_size(
3565 avg_time_slots_per_mtp);
3567 case DP_128b_132b_ENCODING:
3568 hpo_dp_link_encoder->funcs->set_throttled_vcp_size(
3569 hpo_dp_link_encoder,
3570 hpo_dp_stream_encoder->inst,
3571 avg_time_slots_per_mtp);
3573 case DP_UNKNOWN_ENCODING:
3574 DC_LOG_ERROR("Failure: unknown encoding format\n");
3575 return DC_ERROR_UNEXPECTED;
3578 stream_encoder->funcs->set_throttled_vcp_size(
3580 avg_time_slots_per_mtp);
3587 #if defined(CONFIG_DRM_AMD_DC_DCN)
3588 enum dc_status dc_link_reduce_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps)
3590 struct dc_stream_state *stream = pipe_ctx->stream;
3591 struct dc_link *link = stream->link;
3592 struct fixed31_32 avg_time_slots_per_mtp;
3593 struct fixed31_32 pbn;
3594 struct fixed31_32 pbn_per_slot;
3595 struct link_encoder *link_encoder = link->link_enc;
3596 struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
3597 struct dp_mst_stream_allocation_table proposed_table = {0};
3599 enum act_return_status ret;
3600 DC_LOGGER_INIT(link->ctx->logger);
3602 /* decrease throttled vcp size */
3603 pbn_per_slot = get_pbn_per_slot(stream);
3604 pbn = get_pbn_from_bw_in_kbps(bw_in_kbps);
3605 avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot);
3607 stream_encoder->funcs->set_throttled_vcp_size(
3609 avg_time_slots_per_mtp);
3611 /* send ALLOCATE_PAYLOAD sideband message with updated pbn */
3612 dm_helpers_dp_mst_send_payload_allocation(
3617 /* notify immediate branch device table update */
3618 if (dm_helpers_dp_mst_write_payload_allocation_table(
3623 /* update mst stream allocation table software state */
3624 update_mst_stream_alloc_table(
3626 pipe_ctx->stream_res.stream_enc,
3627 pipe_ctx->stream_res.hpo_dp_stream_enc,
3630 DC_LOG_WARNING("Failed to update"
3631 "MST allocation table for"
3633 pipe_ctx->pipe_idx);
3637 "stream_count: %d: \n ",
3639 link->mst_stream_alloc_table.stream_count);
3641 for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
3642 DC_LOG_MST("stream_enc[%d]: %p "
3643 "stream[%d].vcp_id: %d "
3644 "stream[%d].slot_count: %d\n",
3646 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
3648 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
3650 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
3653 ASSERT(proposed_table.stream_count > 0);
3655 /* update mst stream allocation table hardware state */
3656 link_encoder->funcs->update_mst_stream_allocation_table(
3658 &link->mst_stream_alloc_table);
3660 /* poll for immediate branch device ACT handled */
3661 ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger(
3668 enum dc_status dc_link_increase_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps)
3670 struct dc_stream_state *stream = pipe_ctx->stream;
3671 struct dc_link *link = stream->link;
3672 struct fixed31_32 avg_time_slots_per_mtp;
3673 struct fixed31_32 pbn;
3674 struct fixed31_32 pbn_per_slot;
3675 struct link_encoder *link_encoder = link->link_enc;
3676 struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
3677 struct dp_mst_stream_allocation_table proposed_table = {0};
3679 enum act_return_status ret;
3680 DC_LOGGER_INIT(link->ctx->logger);
3682 /* notify immediate branch device table update */
3683 if (dm_helpers_dp_mst_write_payload_allocation_table(
3688 /* update mst stream allocation table software state */
3689 update_mst_stream_alloc_table(
3691 pipe_ctx->stream_res.stream_enc,
3692 pipe_ctx->stream_res.hpo_dp_stream_enc,
3697 "stream_count: %d: \n ",
3699 link->mst_stream_alloc_table.stream_count);
3701 for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
3702 DC_LOG_MST("stream_enc[%d]: %p "
3703 "stream[%d].vcp_id: %d "
3704 "stream[%d].slot_count: %d\n",
3706 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
3708 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
3710 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
3713 ASSERT(proposed_table.stream_count > 0);
3715 /* update mst stream allocation table hardware state */
3716 link_encoder->funcs->update_mst_stream_allocation_table(
3718 &link->mst_stream_alloc_table);
3720 /* poll for immediate branch device ACT handled */
3721 ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger(
3725 if (ret != ACT_LINK_LOST) {
3726 /* send ALLOCATE_PAYLOAD sideband message with updated pbn */
3727 dm_helpers_dp_mst_send_payload_allocation(
3733 /* increase throttled vcp size */
3734 pbn = get_pbn_from_bw_in_kbps(bw_in_kbps);
3735 pbn_per_slot = get_pbn_per_slot(stream);
3736 avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot);
3738 stream_encoder->funcs->set_throttled_vcp_size(
3740 avg_time_slots_per_mtp);
3746 static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx)
3748 struct dc_stream_state *stream = pipe_ctx->stream;
3749 struct dc_link *link = stream->link;
3750 struct link_encoder *link_encoder = NULL;
3751 struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
3752 #if defined(CONFIG_DRM_AMD_DC_DCN)
3753 struct hpo_dp_link_encoder *hpo_dp_link_encoder = link->hpo_dp_link_enc;
3754 struct hpo_dp_stream_encoder *hpo_dp_stream_encoder = pipe_ctx->stream_res.hpo_dp_stream_enc;
3756 struct dp_mst_stream_allocation_table proposed_table = {0};
3757 struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0);
3759 bool mst_mode = (link->type == dc_connection_mst_branch);
3760 DC_LOGGER_INIT(link->ctx->logger);
3762 /* Link encoder may have been dynamically assigned to non-physical display endpoint. */
3763 if (link->ep_type == DISPLAY_ENDPOINT_PHY)
3764 link_encoder = link->link_enc;
3765 else if (link->dc->res_pool->funcs->link_encs_assign)
3766 link_encoder = link_enc_cfg_get_link_enc_used_by_stream(pipe_ctx->stream->ctx->dc, stream);
3767 ASSERT(link_encoder);
3769 /* deallocate_mst_payload is called before disable link. When mode or
3770 * disable/enable monitor, new stream is created which is not in link
3771 * stream[] yet. For this, payload is not allocated yet, so de-alloc
3772 * should not done. For new mode set, map_resources will get engine
3773 * for new stream, so stream_enc->id should be validated until here.
3777 #if defined(CONFIG_DRM_AMD_DC_DCN)
3778 switch (dp_get_link_encoding_format(&link->cur_link_settings)) {
3779 case DP_8b_10b_ENCODING:
3780 stream_encoder->funcs->set_throttled_vcp_size(
3782 avg_time_slots_per_mtp);
3784 case DP_128b_132b_ENCODING:
3785 hpo_dp_link_encoder->funcs->set_throttled_vcp_size(
3786 hpo_dp_link_encoder,
3787 hpo_dp_stream_encoder->inst,
3788 avg_time_slots_per_mtp);
3790 case DP_UNKNOWN_ENCODING:
3791 DC_LOG_ERROR("Failure: unknown encoding format\n");
3792 return DC_ERROR_UNEXPECTED;
3795 stream_encoder->funcs->set_throttled_vcp_size(
3797 avg_time_slots_per_mtp);
3800 /* TODO: which component is responsible for remove payload table? */
3802 if (dm_helpers_dp_mst_write_payload_allocation_table(
3808 #if defined(CONFIG_DRM_AMD_DC_DCN)
3809 update_mst_stream_alloc_table(
3811 pipe_ctx->stream_res.stream_enc,
3812 pipe_ctx->stream_res.hpo_dp_stream_enc,
3815 update_mst_stream_alloc_table(
3816 link, pipe_ctx->stream_res.stream_enc, &proposed_table);
3820 DC_LOG_WARNING("Failed to update"
3821 "MST allocation table for"
3823 pipe_ctx->pipe_idx);
3828 "stream_count: %d: ",
3830 link->mst_stream_alloc_table.stream_count);
3832 for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
3833 #if defined(CONFIG_DRM_AMD_DC_DCN)
3834 DC_LOG_MST("stream_enc[%d]: %p "
3835 "stream[%d].hpo_dp_stream_enc: %p "
3836 "stream[%d].vcp_id: %d "
3837 "stream[%d].slot_count: %d\n",
3839 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
3841 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc,
3843 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
3845 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
3847 DC_LOG_MST("stream_enc[%d]: %p "
3848 "stream[%d].vcp_id: %d "
3849 "stream[%d].slot_count: %d\n",
3851 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
3853 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
3855 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
3859 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) {
3860 enum dc_status status;
3861 uint8_t mst_alloc_slots = 0, prev_mst_slots_in_use = 0xFF;
3863 for (i = 0; i < link->mst_stream_alloc_table.stream_count; i++)
3864 mst_alloc_slots += link->mst_stream_alloc_table.stream_allocations[i].slot_count;
3866 status = dc_process_dmub_set_mst_slots(link->dc, link->link_index,
3867 mst_alloc_slots, &prev_mst_slots_in_use);
3868 ASSERT(status != DC_NOT_SUPPORTED);
3869 DC_LOG_MST("dpia : status[%d]: alloc_slots[%d]: used_slots[%d]\n",
3870 status, mst_alloc_slots, prev_mst_slots_in_use);
3873 #if defined(CONFIG_DRM_AMD_DC_DCN)
3874 switch (dp_get_link_encoding_format(&link->cur_link_settings)) {
3875 case DP_8b_10b_ENCODING:
3876 link_encoder->funcs->update_mst_stream_allocation_table(
3878 &link->mst_stream_alloc_table);
3880 case DP_128b_132b_ENCODING:
3881 hpo_dp_link_encoder->funcs->update_stream_allocation_table(
3882 hpo_dp_link_encoder,
3883 &link->mst_stream_alloc_table);
3885 case DP_UNKNOWN_ENCODING:
3886 DC_LOG_ERROR("Failure: unknown encoding format\n");
3887 return DC_ERROR_UNEXPECTED;
3890 link_encoder->funcs->update_mst_stream_allocation_table(
3892 &link->mst_stream_alloc_table);
3896 dm_helpers_dp_mst_poll_for_allocation_change_trigger(
3900 dm_helpers_dp_mst_send_payload_allocation(
3910 #if defined(CONFIG_DRM_AMD_DC_HDCP)
3911 static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off)
3913 struct cp_psp *cp_psp = &pipe_ctx->stream->ctx->cp_psp;
3914 #if defined(CONFIG_DRM_AMD_DC_DCN)
3915 struct link_encoder *link_enc = NULL;
3916 struct dc_state *state = pipe_ctx->stream->ctx->dc->current_state;
3917 struct link_enc_assignment link_enc_assign;
3921 if (cp_psp && cp_psp->funcs.update_stream_config) {
3922 struct cp_psp_stream_config config = {0};
3923 enum dp_panel_mode panel_mode =
3924 dp_get_panel_mode(pipe_ctx->stream->link);
3926 config.otg_inst = (uint8_t) pipe_ctx->stream_res.tg->inst;
3928 config.dig_fe = (uint8_t) pipe_ctx->stream_res.stream_enc->stream_enc_inst;
3929 config.dig_be = pipe_ctx->stream->link->link_enc_hw_inst;
3930 #if defined(CONFIG_DRM_AMD_DC_DCN)
3931 config.stream_enc_idx = pipe_ctx->stream_res.stream_enc->id - ENGINE_ID_DIGA;
3933 if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_PHY ||
3934 pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) {
3935 link_enc = pipe_ctx->stream->link->link_enc;
3936 config.dio_output_type = pipe_ctx->stream->link->ep_type;
3937 config.dio_output_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A;
3938 if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_PHY)
3939 link_enc = pipe_ctx->stream->link->link_enc;
3940 else if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
3941 if (pipe_ctx->stream->link->dc->res_pool->funcs->link_encs_assign) {
3942 link_enc = link_enc_cfg_get_link_enc_used_by_stream(
3943 pipe_ctx->stream->ctx->dc,
3946 // Initialize PHY ID with ABCDE - 01234 mapping except when it is B0
3947 config.phy_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A;
3949 //look up the link_enc_assignment for the current pipe_ctx
3950 for (i = 0; i < state->stream_count; i++) {
3951 if (pipe_ctx->stream == state->streams[i]) {
3952 link_enc_assign = state->res_ctx.link_enc_cfg_ctx.link_enc_assignments[i];
3955 // Add flag to guard new A0 DIG mapping
3956 if (pipe_ctx->stream->ctx->dc->enable_c20_dtm_b0 == true) {
3957 config.dig_be = link_enc_assign.eng_id;
3958 config.dio_output_type = pipe_ctx->stream->link->ep_type;
3959 config.dio_output_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A;
3961 config.dio_output_type = 0;
3962 config.dio_output_idx = 0;
3965 // Add flag to guard B0 implementation
3966 if (pipe_ctx->stream->ctx->dc->enable_c20_dtm_b0 == true &&
3967 link_enc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0) {
3968 if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) {
3969 link_enc = link_enc_assign.stream->link_enc;
3971 // enum ID 1-4 maps to DPIA PHY ID 0-3
3972 config.phy_idx = link_enc_assign.ep_id.link_id.enum_id - ENUM_ID_1;
3973 } else { // for non DPIA mode over B0, ABCDE maps to 01564
3975 switch (link_enc->transmitter) {
3976 case TRANSMITTER_UNIPHY_A:
3979 case TRANSMITTER_UNIPHY_B:
3982 case TRANSMITTER_UNIPHY_C:
3985 case TRANSMITTER_UNIPHY_D:
3988 case TRANSMITTER_UNIPHY_E:
3998 } else if (pipe_ctx->stream->link->dc->res_pool->funcs->link_encs_assign) {
3999 link_enc = link_enc_cfg_get_link_enc_used_by_stream(
4000 pipe_ctx->stream->ctx->dc,
4002 config.phy_idx = 0; /* Clear phy_idx for non-physical display endpoints. */
4006 config.link_enc_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A;
4007 if (is_dp_128b_132b_signal(pipe_ctx)) {
4008 config.stream_enc_idx = pipe_ctx->stream_res.hpo_dp_stream_enc->id - ENGINE_ID_HPO_DP_0;
4009 config.link_enc_idx = pipe_ctx->stream->link->hpo_dp_link_enc->inst;
4010 config.dp2_enabled = 1;
4013 config.dpms_off = dpms_off;
4014 config.dm_stream_ctx = pipe_ctx->stream->dm_stream_context;
4015 config.assr_enabled = (panel_mode == DP_PANEL_MODE_EDP);
4016 config.mst_enabled = (pipe_ctx->stream->signal ==
4017 SIGNAL_TYPE_DISPLAY_PORT_MST);
4018 cp_psp->funcs.update_stream_config(cp_psp->handle, &config);
4023 #if defined(CONFIG_DRM_AMD_DC_DCN)
4024 static void fpga_dp_hpo_enable_link_and_stream(struct dc_state *state, struct pipe_ctx *pipe_ctx)
4026 struct dc *dc = pipe_ctx->stream->ctx->dc;
4027 struct dc_stream_state *stream = pipe_ctx->stream;
4028 struct link_mst_stream_allocation_table proposed_table = {0};
4029 struct fixed31_32 avg_time_slots_per_mtp;
4030 uint8_t req_slot_count = 0;
4031 uint8_t vc_id = 1; /// VC ID always 1 for SST
4033 struct dc_link_settings link_settings = {0};
4034 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
4036 decide_link_settings(stream, &link_settings);
4037 stream->link->cur_link_settings = link_settings;
4039 /* Enable clock, Configure lane count, and Enable Link Encoder*/
4040 enable_dp_hpo_output(stream->link, &stream->link->cur_link_settings);
4043 /* Workaround for FPGA HPO capture DP link data:
4044 * HPO capture will set link to active mode
4045 * This workaround is required to get a capture from start of frame
4047 if (!dc->debug.fpga_hpo_capture_en) {
4048 struct encoder_set_dp_phy_pattern_param params = {0};
4049 params.dp_phy_pattern = DP_TEST_PATTERN_VIDEO_MODE;
4051 /* Set link active */
4052 stream->link->hpo_dp_link_enc->funcs->set_link_test_pattern(
4053 stream->link->hpo_dp_link_enc,
4058 /* Enable DP_STREAM_ENC */
4059 dc->hwss.enable_stream(pipe_ctx);
4061 /* Set DPS PPS SDP (AKA "info frames") */
4062 if (pipe_ctx->stream->timing.flags.DSC) {
4063 dp_set_dsc_pps_sdp(pipe_ctx, true, true);
4066 /* Allocate Payload */
4067 if ((stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) && (state->stream_count > 1)) {
4071 proposed_table.stream_count = state->stream_count;
4072 for (i = 0; i < state->stream_count; i++) {
4073 avg_time_slots_per_mtp = calculate_sst_avg_time_slots_per_mtp(state->streams[i], state->streams[i]->link);
4074 req_slot_count = dc_fixpt_ceil(avg_time_slots_per_mtp);
4075 proposed_table.stream_allocations[i].slot_count = req_slot_count;
4076 proposed_table.stream_allocations[i].vcp_id = i+1;
4077 /* NOTE: This makes assumption that pipe_ctx index is same as stream index */
4078 proposed_table.stream_allocations[i].hpo_dp_stream_enc = state->res_ctx.pipe_ctx[i].stream_res.hpo_dp_stream_enc;
4082 avg_time_slots_per_mtp = calculate_sst_avg_time_slots_per_mtp(stream, stream->link);
4083 req_slot_count = dc_fixpt_ceil(avg_time_slots_per_mtp);
4084 proposed_table.stream_count = 1; /// Always 1 stream for SST
4085 proposed_table.stream_allocations[0].slot_count = req_slot_count;
4086 proposed_table.stream_allocations[0].vcp_id = vc_id;
4087 proposed_table.stream_allocations[0].hpo_dp_stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc;
4090 stream->link->hpo_dp_link_enc->funcs->update_stream_allocation_table(
4091 stream->link->hpo_dp_link_enc,
4094 stream->link->hpo_dp_link_enc->funcs->set_throttled_vcp_size(
4095 stream->link->hpo_dp_link_enc,
4096 pipe_ctx->stream_res.hpo_dp_stream_enc->inst,
4097 avg_time_slots_per_mtp);
4101 dc->hwss.unblank_stream(pipe_ctx, &stream->link->cur_link_settings);
4105 void core_link_enable_stream(
4106 struct dc_state *state,
4107 struct pipe_ctx *pipe_ctx)
4109 struct dc *dc = pipe_ctx->stream->ctx->dc;
4110 struct dc_stream_state *stream = pipe_ctx->stream;
4111 struct dc_link *link = stream->sink->link;
4112 enum dc_status status;
4113 struct link_encoder *link_enc;
4114 #if defined(CONFIG_DRM_AMD_DC_DCN)
4115 enum otg_out_mux_dest otg_out_dest = OUT_MUX_DIO;
4116 struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg;
4118 if (is_dp_128b_132b_signal(pipe_ctx))
4119 vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg;
4121 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
4123 if (!IS_DIAG_DC(dc->ctx->dce_environment) &&
4124 dc_is_virtual_signal(pipe_ctx->stream->signal))
4127 if (dc->res_pool->funcs->link_encs_assign && stream->link->ep_type != DISPLAY_ENDPOINT_PHY)
4128 link_enc = link_enc_cfg_get_link_enc_used_by_stream(dc, stream);
4130 link_enc = stream->link->link_enc;
4133 #if defined(CONFIG_DRM_AMD_DC_DCN)
4134 if (!dc_is_virtual_signal(pipe_ctx->stream->signal)
4135 && !is_dp_128b_132b_signal(pipe_ctx)) {
4137 if (!dc_is_virtual_signal(pipe_ctx->stream->signal)) {
4140 link_enc->funcs->setup(
4142 pipe_ctx->stream->signal);
4143 pipe_ctx->stream_res.stream_enc->funcs->setup_stereo_sync(
4144 pipe_ctx->stream_res.stream_enc,
4145 pipe_ctx->stream_res.tg->inst,
4146 stream->timing.timing_3d_format != TIMING_3D_FORMAT_NONE);
4149 #if defined(CONFIG_DRM_AMD_DC_DCN)
4150 if (is_dp_128b_132b_signal(pipe_ctx)) {
4151 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->set_stream_attribute(
4152 pipe_ctx->stream_res.hpo_dp_stream_enc,
4154 stream->output_color_space,
4155 stream->use_vsc_sdp_for_colorimetry,
4156 stream->timing.flags.DSC,
4158 otg_out_dest = OUT_MUX_HPO_DP;
4159 } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
4160 pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute(
4161 pipe_ctx->stream_res.stream_enc,
4163 stream->output_color_space,
4164 stream->use_vsc_sdp_for_colorimetry,
4165 stream->link->dpcd_caps.dprx_feature.bits.SST_SPLIT_SDP_CAP);
4168 pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute(
4169 pipe_ctx->stream_res.stream_enc,
4171 stream->output_color_space,
4172 stream->use_vsc_sdp_for_colorimetry,
4173 stream->link->dpcd_caps.dprx_feature.bits.SST_SPLIT_SDP_CAP);
4176 if (dc_is_dp_signal(pipe_ctx->stream->signal))
4177 dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_DP_STREAM_ATTR);
4179 if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal))
4180 pipe_ctx->stream_res.stream_enc->funcs->hdmi_set_stream_attribute(
4181 pipe_ctx->stream_res.stream_enc,
4183 stream->phy_pix_clk,
4184 pipe_ctx->stream_res.audio != NULL);
4186 pipe_ctx->stream->link->link_state_valid = true;
4188 #if defined(CONFIG_DRM_AMD_DC_DCN)
4189 if (pipe_ctx->stream_res.tg->funcs->set_out_mux)
4190 pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, otg_out_dest);
4193 if (dc_is_dvi_signal(pipe_ctx->stream->signal))
4194 pipe_ctx->stream_res.stream_enc->funcs->dvi_set_stream_attribute(
4195 pipe_ctx->stream_res.stream_enc,
4197 (pipe_ctx->stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) ?
4200 if (dc_is_lvds_signal(pipe_ctx->stream->signal))
4201 pipe_ctx->stream_res.stream_enc->funcs->lvds_set_stream_attribute(
4202 pipe_ctx->stream_res.stream_enc,
4205 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
4206 bool apply_edp_fast_boot_optimization =
4207 pipe_ctx->stream->apply_edp_fast_boot_optimization;
4209 pipe_ctx->stream->apply_edp_fast_boot_optimization = false;
4211 #if defined(CONFIG_DRM_AMD_DC_DCN)
4212 // Enable VPG before building infoframe
4213 if (vpg && vpg->funcs->vpg_poweron)
4214 vpg->funcs->vpg_poweron(vpg);
4217 resource_build_info_frame(pipe_ctx);
4218 dc->hwss.update_info_frame(pipe_ctx);
4220 if (dc_is_dp_signal(pipe_ctx->stream->signal))
4221 dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME);
4223 /* Do not touch link on seamless boot optimization. */
4224 if (pipe_ctx->stream->apply_seamless_boot_optimization) {
4225 pipe_ctx->stream->dpms_off = false;
4227 /* Still enable stream features & audio on seamless boot for DP external displays */
4228 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT) {
4229 enable_stream_features(pipe_ctx);
4230 if (pipe_ctx->stream_res.audio != NULL) {
4231 pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc);
4232 dc->hwss.enable_audio_stream(pipe_ctx);
4236 #if defined(CONFIG_DRM_AMD_DC_HDCP)
4237 update_psp_stream_config(pipe_ctx, false);
4242 /* eDP lit up by bios already, no need to enable again. */
4243 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&
4244 apply_edp_fast_boot_optimization &&
4245 !pipe_ctx->stream->timing.flags.DSC) {
4246 pipe_ctx->stream->dpms_off = false;
4247 #if defined(CONFIG_DRM_AMD_DC_HDCP)
4248 update_psp_stream_config(pipe_ctx, false);
4253 if (pipe_ctx->stream->dpms_off)
4256 /* Have to setup DSC before DIG FE and BE are connected (which happens before the
4257 * link training). This is to make sure the bandwidth sent to DIG BE won't be
4258 * bigger than what the link and/or DIG BE can handle. VBID[6]/CompressedStream_flag
4259 * will be automatically set at a later time when the video is enabled
4260 * (DP_VID_STREAM_EN = 1).
4262 if (pipe_ctx->stream->timing.flags.DSC) {
4263 if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
4264 dc_is_virtual_signal(pipe_ctx->stream->signal))
4265 dp_set_dsc_enable(pipe_ctx, true);
4268 status = enable_link(state, pipe_ctx);
4270 if (status != DC_OK) {
4271 DC_LOG_WARNING("enabling link %u failed: %d\n",
4272 pipe_ctx->stream->link->link_index,
4275 /* Abort stream enable *unless* the failure was due to
4276 * DP link training - some DP monitors will recover and
4277 * show the stream anyway. But MST displays can't proceed
4278 * without link training.
4280 if (status != DC_FAIL_DP_LINK_TRAINING ||
4281 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
4282 BREAK_TO_DEBUGGER();
4287 /* turn off otg test pattern if enable */
4288 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
4289 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
4290 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
4291 COLOR_DEPTH_UNDEFINED);
4293 /* This second call is needed to reconfigure the DIG
4294 * as a workaround for the incorrect value being applied
4295 * from transmitter control.
4297 #if defined(CONFIG_DRM_AMD_DC_DCN)
4298 if (!(dc_is_virtual_signal(pipe_ctx->stream->signal) ||
4299 is_dp_128b_132b_signal(pipe_ctx)))
4301 if (!dc_is_virtual_signal(pipe_ctx->stream->signal))
4304 link_enc->funcs->setup(
4306 pipe_ctx->stream->signal);
4308 dc->hwss.enable_stream(pipe_ctx);
4310 /* Set DPS PPS SDP (AKA "info frames") */
4311 if (pipe_ctx->stream->timing.flags.DSC) {
4312 if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
4313 dc_is_virtual_signal(pipe_ctx->stream->signal)) {
4314 dp_set_dsc_on_rx(pipe_ctx, true);
4315 dp_set_dsc_pps_sdp(pipe_ctx, true, true);
4319 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
4320 dc_link_allocate_mst_payload(pipe_ctx);
4321 #if defined(CONFIG_DRM_AMD_DC_DCN)
4322 else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT &&
4323 is_dp_128b_132b_signal(pipe_ctx))
4324 dc_link_update_sst_payload(pipe_ctx, true);
4327 dc->hwss.unblank_stream(pipe_ctx,
4328 &pipe_ctx->stream->link->cur_link_settings);
4330 if (stream->sink_patches.delay_ignore_msa > 0)
4331 msleep(stream->sink_patches.delay_ignore_msa);
4333 if (dc_is_dp_signal(pipe_ctx->stream->signal))
4334 enable_stream_features(pipe_ctx);
4335 #if defined(CONFIG_DRM_AMD_DC_HDCP)
4336 update_psp_stream_config(pipe_ctx, false);
4339 dc->hwss.enable_audio_stream(pipe_ctx);
4341 } else { // if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
4342 #if defined(CONFIG_DRM_AMD_DC_DCN)
4343 if (is_dp_128b_132b_signal(pipe_ctx)) {
4344 fpga_dp_hpo_enable_link_and_stream(state, pipe_ctx);
4347 if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
4348 dc_is_virtual_signal(pipe_ctx->stream->signal))
4349 dp_set_dsc_enable(pipe_ctx, true);
4353 if (pipe_ctx->stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
4354 core_link_set_avmute(pipe_ctx, false);
4358 void core_link_disable_stream(struct pipe_ctx *pipe_ctx)
4360 struct dc *dc = pipe_ctx->stream->ctx->dc;
4361 struct dc_stream_state *stream = pipe_ctx->stream;
4362 struct dc_link *link = stream->sink->link;
4363 #if defined(CONFIG_DRM_AMD_DC_DCN)
4364 struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg;
4366 if (is_dp_128b_132b_signal(pipe_ctx))
4367 vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg;
4370 if (!IS_DIAG_DC(dc->ctx->dce_environment) &&
4371 dc_is_virtual_signal(pipe_ctx->stream->signal))
4374 if (!pipe_ctx->stream->sink->edid_caps.panel_patch.skip_avmute) {
4375 if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
4376 core_link_set_avmute(pipe_ctx, true);
4379 dc->hwss.disable_audio_stream(pipe_ctx);
4381 #if defined(CONFIG_DRM_AMD_DC_HDCP)
4382 update_psp_stream_config(pipe_ctx, true);
4384 dc->hwss.blank_stream(pipe_ctx);
4386 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
4387 deallocate_mst_payload(pipe_ctx);
4388 #if defined(CONFIG_DRM_AMD_DC_DCN)
4389 else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT &&
4390 is_dp_128b_132b_signal(pipe_ctx))
4391 dc_link_update_sst_payload(pipe_ctx, false);
4394 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
4395 struct ext_hdmi_settings settings = {0};
4396 enum engine_id eng_id = pipe_ctx->stream_res.stream_enc->id;
4398 unsigned short masked_chip_caps = link->chip_caps &
4399 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
4400 //Need to inform that sink is going to use legacy HDMI mode.
4401 dal_ddc_service_write_scdc_data(
4403 165000,//vbios only handles 165Mhz.
4405 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {
4406 /* DP159, Retimer settings */
4407 if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings))
4408 write_i2c_retimer_setting(pipe_ctx,
4409 false, false, &settings);
4411 write_i2c_default_retimer_setting(pipe_ctx,
4413 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {
4414 /* PI3EQX1204, Redriver settings */
4415 write_i2c_redriver_setting(pipe_ctx, false);
4419 #if defined(CONFIG_DRM_AMD_DC_DCN)
4420 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT &&
4421 !is_dp_128b_132b_signal(pipe_ctx)) {
4423 /* In DP1.x SST mode, our encoder will go to TPS1
4424 * when link is on but stream is off.
4425 * Disabling link before stream will avoid exposing TPS1 pattern
4426 * during the disable sequence as it will confuse some receivers
4428 * In DP2 or MST mode, our encoder will stay video active
4430 disable_link(pipe_ctx->stream->link, pipe_ctx->stream->signal);
4431 dc->hwss.disable_stream(pipe_ctx);
4433 dc->hwss.disable_stream(pipe_ctx);
4434 disable_link(pipe_ctx->stream->link, pipe_ctx->stream->signal);
4437 disable_link(pipe_ctx->stream->link, pipe_ctx->stream->signal);
4439 dc->hwss.disable_stream(pipe_ctx);
4442 if (pipe_ctx->stream->timing.flags.DSC) {
4443 if (dc_is_dp_signal(pipe_ctx->stream->signal))
4444 dp_set_dsc_enable(pipe_ctx, false);
4446 #if defined(CONFIG_DRM_AMD_DC_DCN)
4447 if (is_dp_128b_132b_signal(pipe_ctx)) {
4448 if (pipe_ctx->stream_res.tg->funcs->set_out_mux)
4449 pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, OUT_MUX_DIO);
4453 #if defined(CONFIG_DRM_AMD_DC_DCN)
4454 if (vpg && vpg->funcs->vpg_powerdown)
4455 vpg->funcs->vpg_powerdown(vpg);
4459 void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
4461 struct dc *dc = pipe_ctx->stream->ctx->dc;
4463 if (!dc_is_hdmi_signal(pipe_ctx->stream->signal))
4466 dc->hwss.set_avmute(pipe_ctx, enable);
4470 * dc_link_enable_hpd_filter:
4471 * If enable is true, programs HPD filter on associated HPD line using
4472 * delay_on_disconnect/delay_on_connect values dependent on
4473 * link->connector_signal
4475 * If enable is false, programs HPD filter on associated HPD line with no
4476 * delays on connect or disconnect
4478 * @link: pointer to the dc link
4479 * @enable: boolean specifying whether to enable hbd
4481 void dc_link_enable_hpd_filter(struct dc_link *link, bool enable)
4486 link->is_hpd_filter_disabled = false;
4487 program_hpd_filter(link);
4489 link->is_hpd_filter_disabled = true;
4490 /* Obtain HPD handle */
4491 hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
4496 /* Setup HPD filtering */
4497 if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) {
4498 struct gpio_hpd_config config;
4500 config.delay_on_connect = 0;
4501 config.delay_on_disconnect = 0;
4503 dal_irq_setup_hpd_filter(hpd, &config);
4505 dal_gpio_close(hpd);
4507 ASSERT_CRITICAL(false);
4509 /* Release HPD handle */
4510 dal_gpio_destroy_irq(&hpd);
4514 void dc_link_set_drive_settings(struct dc *dc,
4515 struct link_training_settings *lt_settings,
4516 const struct dc_link *link)
4521 for (i = 0; i < dc->link_count; i++) {
4522 if (dc->links[i] == link)
4526 if (i >= dc->link_count)
4527 ASSERT_CRITICAL(false);
4529 dc_link_dp_set_drive_settings(dc->links[i], lt_settings);
4532 void dc_link_set_preferred_link_settings(struct dc *dc,
4533 struct dc_link_settings *link_setting,
4534 struct dc_link *link)
4537 struct pipe_ctx *pipe;
4538 struct dc_stream_state *link_stream;
4539 struct dc_link_settings store_settings = *link_setting;
4541 link->preferred_link_setting = store_settings;
4543 /* Retrain with preferred link settings only relevant for
4545 * Check for non-DP signal or if passive dongle present
4547 if (!dc_is_dp_signal(link->connector_signal) ||
4548 link->dongle_max_pix_clk > 0)
4551 for (i = 0; i < MAX_PIPES; i++) {
4552 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
4553 if (pipe->stream && pipe->stream->link) {
4554 if (pipe->stream->link == link) {
4555 link_stream = pipe->stream;
4561 /* Stream not found */
4565 /* Cannot retrain link if backend is off */
4566 if (link_stream->dpms_off)
4569 decide_link_settings(link_stream, &store_settings);
4571 if ((store_settings.lane_count != LANE_COUNT_UNKNOWN) &&
4572 (store_settings.link_rate != LINK_RATE_UNKNOWN))
4573 dp_retrain_link_dp_test(link, &store_settings, false);
4576 void dc_link_set_preferred_training_settings(struct dc *dc,
4577 struct dc_link_settings *link_setting,
4578 struct dc_link_training_overrides *lt_overrides,
4579 struct dc_link *link,
4580 bool skip_immediate_retrain)
4582 if (lt_overrides != NULL)
4583 link->preferred_training_settings = *lt_overrides;
4585 memset(&link->preferred_training_settings, 0, sizeof(link->preferred_training_settings));
4587 if (link_setting != NULL) {
4588 link->preferred_link_setting = *link_setting;
4589 #if defined(CONFIG_DRM_AMD_DC_DCN)
4590 if (dp_get_link_encoding_format(link_setting) ==
4591 DP_128b_132b_ENCODING && !link->hpo_dp_link_enc) {
4592 if (!add_dp_hpo_link_encoder_to_link(link))
4593 memset(&link->preferred_link_setting, 0, sizeof(link->preferred_link_setting));
4597 link->preferred_link_setting.lane_count = LANE_COUNT_UNKNOWN;
4598 link->preferred_link_setting.link_rate = LINK_RATE_UNKNOWN;
4601 /* Retrain now, or wait until next stream update to apply */
4602 if (skip_immediate_retrain == false)
4603 dc_link_set_preferred_link_settings(dc, &link->preferred_link_setting, link);
4606 void dc_link_enable_hpd(const struct dc_link *link)
4608 dc_link_dp_enable_hpd(link);
4611 void dc_link_disable_hpd(const struct dc_link *link)
4613 dc_link_dp_disable_hpd(link);
4616 void dc_link_set_test_pattern(struct dc_link *link,
4617 enum dp_test_pattern test_pattern,
4618 enum dp_test_pattern_color_space test_pattern_color_space,
4619 const struct link_training_settings *p_link_settings,
4620 const unsigned char *p_custom_pattern,
4621 unsigned int cust_pattern_size)
4624 dc_link_dp_set_test_pattern(
4627 test_pattern_color_space,
4633 uint32_t dc_link_bandwidth_kbps(
4634 const struct dc_link *link,
4635 const struct dc_link_settings *link_setting)
4637 #if defined(CONFIG_DRM_AMD_DC_DCN)
4638 uint32_t total_data_bw_efficiency_x10000 = 0;
4639 uint32_t link_rate_per_lane_kbps = 0;
4641 switch (dp_get_link_encoding_format(link_setting)) {
4642 case DP_8b_10b_ENCODING:
4643 /* For 8b/10b encoding:
4644 * link rate is defined in the unit of LINK_RATE_REF_FREQ_IN_KHZ per DP byte per lane.
4645 * data bandwidth efficiency is 80% with additional 3% overhead if FEC is supported.
4647 link_rate_per_lane_kbps = link_setting->link_rate * LINK_RATE_REF_FREQ_IN_KHZ * BITS_PER_DP_BYTE;
4648 total_data_bw_efficiency_x10000 = DATA_EFFICIENCY_8b_10b_x10000;
4649 if (dc_link_should_enable_fec(link)) {
4650 total_data_bw_efficiency_x10000 /= 100;
4651 total_data_bw_efficiency_x10000 *= DATA_EFFICIENCY_8b_10b_FEC_EFFICIENCY_x100;
4654 case DP_128b_132b_ENCODING:
4655 /* For 128b/132b encoding:
4656 * link rate is defined in the unit of 10mbps per lane.
4657 * total data bandwidth efficiency is always 96.71%.
4659 link_rate_per_lane_kbps = link_setting->link_rate * 10000;
4660 total_data_bw_efficiency_x10000 = DATA_EFFICIENCY_128b_132b_x10000;
4666 /* overall effective link bandwidth = link rate per lane * lane count * total data bandwidth efficiency */
4667 return link_rate_per_lane_kbps * link_setting->lane_count / 10000 * total_data_bw_efficiency_x10000;
4669 uint32_t link_bw_kbps =
4670 link_setting->link_rate * LINK_RATE_REF_FREQ_IN_KHZ; /* bytes per sec */
4672 link_bw_kbps *= 8; /* 8 bits per byte*/
4673 link_bw_kbps *= link_setting->lane_count;
4675 if (dc_link_should_enable_fec(link)) {
4676 /* Account for FEC overhead.
4677 * We have to do it based on caps,
4678 * and not based on FEC being set ready,
4679 * because FEC is set ready too late in
4680 * the process to correctly be picked up
4681 * by mode enumeration.
4683 * There's enough zeros at the end of 'kbps'
4684 * that make the below operation 100% precise
4686 * 'long long' makes it work even for HDMI 2.1
4687 * max bandwidth (and much, much bigger bandwidths
4688 * than that, actually).
4690 * NOTE: Reducing link BW by 3% may not be precise
4691 * because it may be a stream BT that increases by 3%, and so
4692 * 1/1.03 = 0.970873 factor should have been used instead,
4693 * but the difference is minimal and is in a safe direction,
4694 * which all works well around potential ambiguity of DP 1.4a spec.
4696 long long fec_link_bw_kbps = link_bw_kbps * 970LL;
4697 link_bw_kbps = (uint32_t)(div64_s64(fec_link_bw_kbps, 1000LL));
4699 return link_bw_kbps;
4704 const struct dc_link_settings *dc_link_get_link_cap(
4705 const struct dc_link *link)
4707 if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN &&
4708 link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN)
4709 return &link->preferred_link_setting;
4710 return &link->verified_link_cap;
4713 void dc_link_overwrite_extended_receiver_cap(
4714 struct dc_link *link)
4716 dp_overwrite_extended_receiver_cap(link);
4719 bool dc_link_is_fec_supported(const struct dc_link *link)
4721 struct link_encoder *link_enc = NULL;
4723 /* Links supporting dynamically assigned link encoder will be assigned next
4724 * available encoder if one not already assigned.
4726 if (link->is_dig_mapping_flexible &&
4727 link->dc->res_pool->funcs->link_encs_assign) {
4728 link_enc = link_enc_cfg_get_link_enc_used_by_link(link->ctx->dc, link);
4729 if (link_enc == NULL)
4730 link_enc = link_enc_cfg_get_next_avail_link_enc(link->ctx->dc);
4732 link_enc = link->link_enc;
4735 return (dc_is_dp_signal(link->connector_signal) && link_enc &&
4736 link_enc->features.fec_supported &&
4737 link->dpcd_caps.fec_cap.bits.FEC_CAPABLE &&
4738 !IS_FPGA_MAXIMUS_DC(link->ctx->dce_environment));
4741 bool dc_link_should_enable_fec(const struct dc_link *link)
4743 bool is_fec_disable = false;
4746 if ((link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT_MST &&
4748 link->local_sink->edid_caps.panel_patch.disable_fec) ||
4749 (link->connector_signal == SIGNAL_TYPE_EDP
4751 is_fec_disable = true;
4753 if (dc_link_is_fec_supported(link) && !link->dc->debug.disable_fec && !is_fec_disable)
4759 uint32_t dc_bandwidth_in_kbps_from_timing(
4760 const struct dc_crtc_timing *timing)
4762 uint32_t bits_per_channel = 0;
4765 #if defined(CONFIG_DRM_AMD_DC_DCN)
4766 if (timing->flags.DSC)
4767 return dc_dsc_stream_bandwidth_in_kbps(timing,
4768 timing->dsc_cfg.bits_per_pixel,
4769 timing->dsc_cfg.num_slices_h,
4770 timing->dsc_cfg.is_dp);
4773 switch (timing->display_color_depth) {
4774 case COLOR_DEPTH_666:
4775 bits_per_channel = 6;
4777 case COLOR_DEPTH_888:
4778 bits_per_channel = 8;
4780 case COLOR_DEPTH_101010:
4781 bits_per_channel = 10;
4783 case COLOR_DEPTH_121212:
4784 bits_per_channel = 12;
4786 case COLOR_DEPTH_141414:
4787 bits_per_channel = 14;
4789 case COLOR_DEPTH_161616:
4790 bits_per_channel = 16;
4793 ASSERT(bits_per_channel != 0);
4794 bits_per_channel = 8;
4798 kbps = timing->pix_clk_100hz / 10;
4799 kbps *= bits_per_channel;
4801 if (timing->flags.Y_ONLY != 1) {
4802 /*Only YOnly make reduce bandwidth by 1/3 compares to RGB*/
4804 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
4806 else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
4807 kbps = kbps * 2 / 3;