drivers/gpu/drm/amd/display/dc/core/dc_link.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <linux/slab.h>
  27
  28 #include "dm_services.h"
  29 #include "atomfirmware.h"
  30 #include "dm_helpers.h"
  31 #include "dc.h"
  32 #include "grph_object_id.h"
  33 #include "gpio_service_interface.h"
  34 #include "core_status.h"
  35 #include "dc_link_dp.h"
  36 #include "dc_link_dpia.h"
  37 #include "dc_link_ddc.h"
  38 #include "link_hwss.h"
  39 #include "opp.h"
  40
  41 #include "link_encoder.h"
  42 #include "hw_sequencer.h"
  43 #include "resource.h"
  44 #include "abm.h"
  45 #include "fixed31_32.h"
  46 #include "dpcd_defs.h"
  47 #include "dmcu.h"
  48 #include "hw/clk_mgr.h"
  49 #include "dce/dmub_psr.h"
  50 #include "dmub/dmub_srv.h"
  51 #include "inc/hw/panel_cntl.h"
  52 #include "inc/link_enc_cfg.h"
  53 #include "inc/link_dpcd.h"
  54 #include "link/link_dp_trace.h"
  55
  56 #include "dc/dcn30/dcn30_vpg.h"
  57
  58 #define DC_LOGGER_INIT(logger)
  59
  60 #define LINK_INFO(...) \
  61         DC_LOG_HW_HOTPLUG(  \
  62                 __VA_ARGS__)
  63
  64 #define RETIMER_REDRIVER_INFO(...) \
  65         DC_LOG_RETIMER_REDRIVER(  \
  66                 __VA_ARGS__)
  67
  68 /*******************************************************************************
  69  * Private functions
  70  ******************************************************************************/
  71 static void dc_link_destruct(struct dc_link *link)
  72 {
  73         int i;
  74
  75         if (link->hpd_gpio) {
  76                 dal_gpio_destroy_irq(&link->hpd_gpio);
  77                 link->hpd_gpio = NULL;
  78         }
  79
  80         if (link->ddc)
  81                 dal_ddc_service_destroy(&link->ddc);
  82
  83         if (link->panel_cntl)
  84                 link->panel_cntl->funcs->destroy(&link->panel_cntl);
  85
  86         if (link->link_enc) {
  87                 /* Update link encoder resource tracking variables. These are used for
  88                  * the dynamic assignment of link encoders to streams. Virtual links
  89                  * are not assigned encoder resources on creation.
  90                  */
  91                 if (link->link_id.id != CONNECTOR_ID_VIRTUAL) {
  92                         link->dc->res_pool->link_encoders[link->eng_id - ENGINE_ID_DIGA] = NULL;
  93                         link->dc->res_pool->dig_link_enc_count--;
  94                 }
  95                 link->link_enc->funcs->destroy(&link->link_enc);
  96         }
  97
  98         if (link->local_sink)
  99                 dc_sink_release(link->local_sink);
 100
 101         for (i = 0; i < link->sink_count; ++i)
 102                 dc_sink_release(link->remote_sinks[i]);
 103 }
 104
 105 struct gpio *get_hpd_gpio(struct dc_bios *dcb,
 106                           struct graphics_object_id link_id,
 107                           struct gpio_service *gpio_service)
 108 {
 109         enum bp_result bp_result;
 110         struct graphics_object_hpd_info hpd_info;
 111         struct gpio_pin_info pin_info;
 112
 113         if (dcb->funcs->get_hpd_info(dcb, link_id, &hpd_info) != BP_RESULT_OK)
 114                 return NULL;
 115
 116         bp_result = dcb->funcs->get_gpio_pin_info(dcb,
 117                 hpd_info.hpd_int_gpio_uid, &pin_info);
 118
 119         if (bp_result != BP_RESULT_OK) {
 120                 ASSERT(bp_result == BP_RESULT_NORECORD);
 121                 return NULL;
 122         }
 123
 124         return dal_gpio_service_create_irq(gpio_service,
 125                                            pin_info.offset,
 126                                            pin_info.mask);
 127 }
 128
 129 /*
 130  *  Function: program_hpd_filter
 131  *
 132  *  @brief
 133  *     Programs HPD filter on associated HPD line
 134  *
 135  *  @param [in] delay_on_connect_in_ms: Connect filter timeout
 136  *  @param [in] delay_on_disconnect_in_ms: Disconnect filter timeout
 137  *
 138  *  @return
 139  *     true on success, false otherwise
 140  */
 141 static bool program_hpd_filter(const struct dc_link *link)
 142 {
 143         bool result = false;
 144         struct gpio *hpd;
 145         int delay_on_connect_in_ms = 0;
 146         int delay_on_disconnect_in_ms = 0;
 147
 148         if (link->is_hpd_filter_disabled)
 149                 return false;
 150         /* Verify feature is supported */
 151         switch (link->connector_signal) {
 152         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 153         case SIGNAL_TYPE_DVI_DUAL_LINK:
 154         case SIGNAL_TYPE_HDMI_TYPE_A:
 155                 /* Program hpd filter */
 156                 delay_on_connect_in_ms = 500;
 157                 delay_on_disconnect_in_ms = 100;
 158                 break;
 159         case SIGNAL_TYPE_DISPLAY_PORT:
 160         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 161                 /* Program hpd filter to allow DP signal to settle */
 162                 /* 500: not able to detect MST <-> SST switch as HPD is low for
 163                  * only 100ms on DELL U2413
 164                  * 0: some passive dongle still show aux mode instead of i2c
 165                  * 20-50: not enough to hide bouncing HPD with passive dongle.
 166                  * also see intermittent i2c read issues.
 167                  */
 168                 delay_on_connect_in_ms = 80;
 169                 delay_on_disconnect_in_ms = 0;
 170                 break;
 171         case SIGNAL_TYPE_LVDS:
 172         case SIGNAL_TYPE_EDP:
 173         default:
 174                 /* Don't program hpd filter */
 175                 return false;
 176         }
 177
 178         /* Obtain HPD handle */
 179         hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
 180                            link->ctx->gpio_service);
 181
 182         if (!hpd)
 183                 return result;
 184
 185         /* Setup HPD filtering */
 186         if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) {
 187                 struct gpio_hpd_config config;
 188
 189                 config.delay_on_connect = delay_on_connect_in_ms;
 190                 config.delay_on_disconnect = delay_on_disconnect_in_ms;
 191
 192                 dal_irq_setup_hpd_filter(hpd, &config);
 193
 194                 dal_gpio_close(hpd);
 195
 196                 result = true;
 197         } else {
 198                 ASSERT_CRITICAL(false);
 199         }
 200
 201         /* Release HPD handle */
 202         dal_gpio_destroy_irq(&hpd);
 203
 204         return result;
 205 }
 206
 207 bool dc_link_wait_for_t12(struct dc_link *link)
 208 {
 209         if (link->connector_signal == SIGNAL_TYPE_EDP && link->dc->hwss.edp_wait_for_T12) {
 210                 link->dc->hwss.edp_wait_for_T12(link);
 211
 212                 return true;
 213         }
 214
 215         return false;
 216 }
 217
 218 /**
 219  * dc_link_detect_sink() - Determine if there is a sink connected
 220  *
 221  * @link: pointer to the dc link
 222  * @type: Returned connection type
 223  * Does not detect downstream devices, such as MST sinks
 224  * or display connected through active dongles
 225  */
 226 bool dc_link_detect_sink(struct dc_link *link, enum dc_connection_type *type)
 227 {
 228         uint32_t is_hpd_high = 0;
 229         struct gpio *hpd_pin;
 230
 231         if (link->connector_signal == SIGNAL_TYPE_LVDS) {
 232                 *type = dc_connection_single;
 233                 return true;
 234         }
 235
 236         if (link->connector_signal == SIGNAL_TYPE_EDP) {
 237                 /*in case it is not on*/
 238                 if (!link->dc->config.edp_no_power_sequencing)
 239                         link->dc->hwss.edp_power_control(link, true);
 240                 link->dc->hwss.edp_wait_for_hpd_ready(link, true);
 241         }
 242
 243         /* Link may not have physical HPD pin. */
 244         if (link->ep_type != DISPLAY_ENDPOINT_PHY) {
 245                 if (link->is_hpd_pending || !dc_link_dpia_query_hpd_status(link))
 246                         *type = dc_connection_none;
 247                 else
 248                         *type = dc_connection_single;
 249
 250                 return true;
 251         }
 252
 253         /* todo: may need to lock gpio access */
 254         hpd_pin = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
 255                                link->ctx->gpio_service);
 256         if (!hpd_pin)
 257                 goto hpd_gpio_failure;
 258
 259         dal_gpio_open(hpd_pin, GPIO_MODE_INTERRUPT);
 260         dal_gpio_get_value(hpd_pin, &is_hpd_high);
 261         dal_gpio_close(hpd_pin);
 262         dal_gpio_destroy_irq(&hpd_pin);
 263
 264         if (is_hpd_high) {
 265                 *type = dc_connection_single;
 266                 /* TODO: need to do the actual detection */
 267         } else {
 268                 *type = dc_connection_none;
 269         }
 270
 271         return true;
 272
 273 hpd_gpio_failure:
 274         return false;
 275 }
 276
 277 static enum ddc_transaction_type get_ddc_transaction_type(enum signal_type sink_signal)
 278 {
 279         enum ddc_transaction_type transaction_type = DDC_TRANSACTION_TYPE_NONE;
 280
 281         switch (sink_signal) {
 282         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 283         case SIGNAL_TYPE_DVI_DUAL_LINK:
 284         case SIGNAL_TYPE_HDMI_TYPE_A:
 285         case SIGNAL_TYPE_LVDS:
 286         case SIGNAL_TYPE_RGB:
 287                 transaction_type = DDC_TRANSACTION_TYPE_I2C;
 288                 break;
 289
 290         case SIGNAL_TYPE_DISPLAY_PORT:
 291         case SIGNAL_TYPE_EDP:
 292                 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 293                 break;
 294
 295         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 296                 /* MST does not use I2COverAux, but there is the
 297                  * SPECIAL use case for "immediate dwnstrm device
 298                  * access" (EPR#370830).
 299                  */
 300                 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 301                 break;
 302
 303         default:
 304                 break;
 305         }
 306
 307         return transaction_type;
 308 }
 309
 310 static enum signal_type get_basic_signal_type(struct graphics_object_id encoder,
 311                                               struct graphics_object_id downstream)
 312 {
 313         if (downstream.type == OBJECT_TYPE_CONNECTOR) {
 314                 switch (downstream.id) {
 315                 case CONNECTOR_ID_SINGLE_LINK_DVII:
 316                         switch (encoder.id) {
 317                         case ENCODER_ID_INTERNAL_DAC1:
 318                         case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
 319                         case ENCODER_ID_INTERNAL_DAC2:
 320                         case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
 321                                 return SIGNAL_TYPE_RGB;
 322                         default:
 323                                 return SIGNAL_TYPE_DVI_SINGLE_LINK;
 324                         }
 325                 break;
 326                 case CONNECTOR_ID_DUAL_LINK_DVII:
 327                 {
 328                         switch (encoder.id) {
 329                         case ENCODER_ID_INTERNAL_DAC1:
 330                         case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
 331                         case ENCODER_ID_INTERNAL_DAC2:
 332                         case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
 333                                 return SIGNAL_TYPE_RGB;
 334                         default:
 335                                 return SIGNAL_TYPE_DVI_DUAL_LINK;
 336                         }
 337                 }
 338                 break;
 339                 case CONNECTOR_ID_SINGLE_LINK_DVID:
 340                         return SIGNAL_TYPE_DVI_SINGLE_LINK;
 341                 case CONNECTOR_ID_DUAL_LINK_DVID:
 342                         return SIGNAL_TYPE_DVI_DUAL_LINK;
 343                 case CONNECTOR_ID_VGA:
 344                         return SIGNAL_TYPE_RGB;
 345                 case CONNECTOR_ID_HDMI_TYPE_A:
 346                         return SIGNAL_TYPE_HDMI_TYPE_A;
 347                 case CONNECTOR_ID_LVDS:
 348                         return SIGNAL_TYPE_LVDS;
 349                 case CONNECTOR_ID_DISPLAY_PORT:
 350                 case CONNECTOR_ID_USBC:
 351                         return SIGNAL_TYPE_DISPLAY_PORT;
 352                 case CONNECTOR_ID_EDP:
 353                         return SIGNAL_TYPE_EDP;
 354                 default:
 355                         return SIGNAL_TYPE_NONE;
 356                 }
 357         } else if (downstream.type == OBJECT_TYPE_ENCODER) {
 358                 switch (downstream.id) {
 359                 case ENCODER_ID_EXTERNAL_NUTMEG:
 360                 case ENCODER_ID_EXTERNAL_TRAVIS:
 361                         return SIGNAL_TYPE_DISPLAY_PORT;
 362                 default:
 363                         return SIGNAL_TYPE_NONE;
 364                 }
 365         }
 366
 367         return SIGNAL_TYPE_NONE;
 368 }
 369
 370 /*
 371  * dc_link_is_dp_sink_present() - Check if there is a native DP
 372  * or passive DP-HDMI dongle connected
 373  */
 374 bool dc_link_is_dp_sink_present(struct dc_link *link)
 375 {
 376         enum gpio_result gpio_result;
 377         uint32_t clock_pin = 0;
 378         uint8_t retry = 0;
 379         struct ddc *ddc;
 380
 381         enum connector_id connector_id =
 382                 dal_graphics_object_id_get_connector_id(link->link_id);
 383
 384         bool present =
 385                 ((connector_id == CONNECTOR_ID_DISPLAY_PORT) ||
 386                 (connector_id == CONNECTOR_ID_EDP) ||
 387                 (connector_id == CONNECTOR_ID_USBC));
 388
 389         ddc = dal_ddc_service_get_ddc_pin(link->ddc);
 390
 391         if (!ddc) {
 392                 BREAK_TO_DEBUGGER();
 393                 return present;
 394         }
 395
 396         /* Open GPIO and set it to I2C mode */
 397         /* Note: this GpioMode_Input will be converted
 398          * to GpioConfigType_I2cAuxDualMode in GPIO component,
 399          * which indicates we need additional delay
 400          */
 401
 402         if (dal_ddc_open(ddc, GPIO_MODE_INPUT,
 403                          GPIO_DDC_CONFIG_TYPE_MODE_I2C) != GPIO_RESULT_OK) {
 404                 dal_ddc_close(ddc);
 405
 406                 return present;
 407         }
 408
 409         /*
 410          * Read GPIO: DP sink is present if both clock and data pins are zero
 411          *
 412          * [W/A] plug-unplug DP cable, sometimes customer board has
 413          * one short pulse on clk_pin(1V, < 1ms). DP will be config to HDMI/DVI
 414          * then monitor can't br light up. Add retry 3 times
 415          * But in real passive dongle, it need additional 3ms to detect
 416          */
 417         do {
 418                 gpio_result = dal_gpio_get_value(ddc->pin_clock, &clock_pin);
 419                 ASSERT(gpio_result == GPIO_RESULT_OK);
 420                 if (clock_pin)
 421                         udelay(1000);
 422                 else
 423                         break;
 424         } while (retry++ < 3);
 425
 426         present = (gpio_result == GPIO_RESULT_OK) && !clock_pin;
 427
 428         dal_ddc_close(ddc);
 429
 430         return present;
 431 }
 432
 433 /*
 434  * @brief
 435  * Detect output sink type
 436  */
 437 static enum signal_type link_detect_sink(struct dc_link *link,
 438                                          enum dc_detect_reason reason)
 439 {
 440         enum signal_type result;
 441         struct graphics_object_id enc_id;
 442
 443         if (link->is_dig_mapping_flexible)
 444                 enc_id = (struct graphics_object_id){.id = ENCODER_ID_UNKNOWN};
 445         else
 446                 enc_id = link->link_enc->id;
 447         result = get_basic_signal_type(enc_id, link->link_id);
 448
 449         /* Use basic signal type for link without physical connector. */
 450         if (link->ep_type != DISPLAY_ENDPOINT_PHY)
 451                 return result;
 452
 453         /* Internal digital encoder will detect only dongles
 454          * that require digital signal
 455          */
 456
 457         /* Detection mechanism is different
 458          * for different native connectors.
 459          * LVDS connector supports only LVDS signal;
 460          * PCIE is a bus slot, the actual connector needs to be detected first;
 461          * eDP connector supports only eDP signal;
 462          * HDMI should check straps for audio
 463          */
 464
 465         /* PCIE detects the actual connector on add-on board */
 466         if (link->link_id.id == CONNECTOR_ID_PCIE) {
 467                 /* ZAZTODO implement PCIE add-on card detection */
 468         }
 469
 470         switch (link->link_id.id) {
 471         case CONNECTOR_ID_HDMI_TYPE_A: {
 472                 /* check audio support:
 473                  * if native HDMI is not supported, switch to DVI
 474                  */
 475                 struct audio_support *aud_support =
 476                                         &link->dc->res_pool->audio_support;
 477
 478                 if (!aud_support->hdmi_audio_native)
 479                         if (link->link_id.id == CONNECTOR_ID_HDMI_TYPE_A)
 480                                 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
 481         }
 482         break;
 483         case CONNECTOR_ID_DISPLAY_PORT:
 484         case CONNECTOR_ID_USBC: {
 485                 /* DP HPD short pulse. Passive DP dongle will not
 486                  * have short pulse
 487                  */
 488                 if (reason != DETECT_REASON_HPDRX) {
 489                         /* Check whether DP signal detected: if not -
 490                          * we assume signal is DVI; it could be corrected
 491                          * to HDMI after dongle detection
 492                          */
 493                         if (!dm_helpers_is_dp_sink_present(link))
 494                                 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
 495                 }
 496         }
 497         break;
 498         default:
 499         break;
 500         }
 501
 502         return result;
 503 }
 504
 505 static enum signal_type decide_signal_from_strap_and_dongle_type(enum display_dongle_type dongle_type,
 506                                                                  struct audio_support *audio_support)
 507 {
 508         enum signal_type signal = SIGNAL_TYPE_NONE;
 509
 510         switch (dongle_type) {
 511         case DISPLAY_DONGLE_DP_HDMI_DONGLE:
 512                 if (audio_support->hdmi_audio_on_dongle)
 513                         signal = SIGNAL_TYPE_HDMI_TYPE_A;
 514                 else
 515                         signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 516                 break;
 517         case DISPLAY_DONGLE_DP_DVI_DONGLE:
 518                 signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 519                 break;
 520         case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
 521                 if (audio_support->hdmi_audio_native)
 522                         signal =  SIGNAL_TYPE_HDMI_TYPE_A;
 523                 else
 524                         signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 525                 break;
 526         default:
 527                 signal = SIGNAL_TYPE_NONE;
 528                 break;
 529         }
 530
 531         return signal;
 532 }
 533
 534 static enum signal_type dp_passive_dongle_detection(struct ddc_service *ddc,
 535                                                     struct display_sink_capability *sink_cap,
 536                                                     struct audio_support *audio_support)
 537 {
 538         dal_ddc_service_i2c_query_dp_dual_mode_adaptor(ddc, sink_cap);
 539
 540         return decide_signal_from_strap_and_dongle_type(sink_cap->dongle_type,
 541                                                         audio_support);
 542 }
 543
 544 static void link_disconnect_sink(struct dc_link *link)
 545 {
 546         if (link->local_sink) {
 547                 dc_sink_release(link->local_sink);
 548                 link->local_sink = NULL;
 549         }
 550
 551         link->dpcd_sink_count = 0;
 552         //link->dpcd_caps.dpcd_rev.raw = 0;
 553 }
 554
 555 static void link_disconnect_remap(struct dc_sink *prev_sink, struct dc_link *link)
 556 {
 557         dc_sink_release(link->local_sink);
 558         link->local_sink = prev_sink;
 559 }
 560
 561 #if defined(CONFIG_DRM_AMD_DC_HDCP)
 562 bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal)
 563 {
 564         bool ret = false;
 565
 566         switch (signal) {
 567         case SIGNAL_TYPE_DISPLAY_PORT:
 568         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 569                 ret = link->hdcp_caps.bcaps.bits.HDCP_CAPABLE;
 570                 break;
 571         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 572         case SIGNAL_TYPE_DVI_DUAL_LINK:
 573         case SIGNAL_TYPE_HDMI_TYPE_A:
 574         /* HDMI doesn't tell us its HDCP(1.4) capability, so assume to always be capable,
 575          * we can poll for bksv but some displays have an issue with this. Since its so rare
 576          * for a display to not be 1.4 capable, this assumtion is ok
 577          */
 578                 ret = true;
 579                 break;
 580         default:
 581                 break;
 582         }
 583         return ret;
 584 }
 585
 586 bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal)
 587 {
 588         bool ret = false;
 589
 590         switch (signal) {
 591         case SIGNAL_TYPE_DISPLAY_PORT:
 592         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 593                 ret = (link->hdcp_caps.bcaps.bits.HDCP_CAPABLE &&
 594                                 link->hdcp_caps.rx_caps.fields.byte0.hdcp_capable &&
 595                                 (link->hdcp_caps.rx_caps.fields.version == 0x2)) ? 1 : 0;
 596                 break;
 597         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 598         case SIGNAL_TYPE_DVI_DUAL_LINK:
 599         case SIGNAL_TYPE_HDMI_TYPE_A:
 600                 ret = (link->hdcp_caps.rx_caps.fields.version == 0x4) ? 1:0;
 601                 break;
 602         default:
 603                 break;
 604         }
 605
 606         return ret;
 607 }
 608
 609 static void query_hdcp_capability(enum signal_type signal, struct dc_link *link)
 610 {
 611         struct hdcp_protection_message msg22;
 612         struct hdcp_protection_message msg14;
 613
 614         memset(&msg22, 0, sizeof(struct hdcp_protection_message));
 615         memset(&msg14, 0, sizeof(struct hdcp_protection_message));
 616         memset(link->hdcp_caps.rx_caps.raw, 0,
 617                 sizeof(link->hdcp_caps.rx_caps.raw));
 618
 619         if ((link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
 620                         link->ddc->transaction_type ==
 621                         DDC_TRANSACTION_TYPE_I2C_OVER_AUX) ||
 622                         link->connector_signal == SIGNAL_TYPE_EDP) {
 623                 msg22.data = link->hdcp_caps.rx_caps.raw;
 624                 msg22.length = sizeof(link->hdcp_caps.rx_caps.raw);
 625                 msg22.msg_id = HDCP_MESSAGE_ID_RX_CAPS;
 626         } else {
 627                 msg22.data = &link->hdcp_caps.rx_caps.fields.version;
 628                 msg22.length = sizeof(link->hdcp_caps.rx_caps.fields.version);
 629                 msg22.msg_id = HDCP_MESSAGE_ID_HDCP2VERSION;
 630         }
 631         msg22.version = HDCP_VERSION_22;
 632         msg22.link = HDCP_LINK_PRIMARY;
 633         msg22.max_retries = 5;
 634         dc_process_hdcp_msg(signal, link, &msg22);
 635
 636         if (signal == SIGNAL_TYPE_DISPLAY_PORT || signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
 637                 msg14.data = &link->hdcp_caps.bcaps.raw;
 638                 msg14.length = sizeof(link->hdcp_caps.bcaps.raw);
 639                 msg14.msg_id = HDCP_MESSAGE_ID_READ_BCAPS;
 640                 msg14.version = HDCP_VERSION_14;
 641                 msg14.link = HDCP_LINK_PRIMARY;
 642                 msg14.max_retries = 5;
 643
 644                 dc_process_hdcp_msg(signal, link, &msg14);
 645         }
 646
 647 }
 648 #endif
 649
 650 static void read_current_link_settings_on_detect(struct dc_link *link)
 651 {
 652         union lane_count_set lane_count_set = {0};
 653         uint8_t link_bw_set;
 654         uint8_t link_rate_set;
 655         uint32_t read_dpcd_retry_cnt = 10;
 656         enum dc_status status = DC_ERROR_UNEXPECTED;
 657         int i;
 658         union max_down_spread max_down_spread = {0};
 659
 660         // Read DPCD 00101h to find out the number of lanes currently set
 661         for (i = 0; i < read_dpcd_retry_cnt; i++) {
 662                 status = core_link_read_dpcd(link,
 663                                              DP_LANE_COUNT_SET,
 664                                              &lane_count_set.raw,
 665                                              sizeof(lane_count_set));
 666                 /* First DPCD read after VDD ON can fail if the particular board
 667                  * does not have HPD pin wired correctly. So if DPCD read fails,
 668                  * which it should never happen, retry a few times. Target worst
 669                  * case scenario of 80 ms.
 670                  */
 671                 if (status == DC_OK) {
 672                         link->cur_link_settings.lane_count =
 673                                         lane_count_set.bits.LANE_COUNT_SET;
 674                         break;
 675                 }
 676
 677                 msleep(8);
 678         }
 679
 680         // Read DPCD 00100h to find if standard link rates are set
 681         core_link_read_dpcd(link, DP_LINK_BW_SET,
 682                             &link_bw_set, sizeof(link_bw_set));
 683
 684         if (link_bw_set == 0) {
 685                 if (link->connector_signal == SIGNAL_TYPE_EDP) {
 686                         /* If standard link rates are not being used,
 687                          * Read DPCD 00115h to find the edp link rate set used
 688                          */
 689                         core_link_read_dpcd(link, DP_LINK_RATE_SET,
 690                                             &link_rate_set, sizeof(link_rate_set));
 691
 692                         // edp_supported_link_rates_count = 0 for DP
 693                         if (link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) {
 694                                 link->cur_link_settings.link_rate =
 695                                         link->dpcd_caps.edp_supported_link_rates[link_rate_set];
 696                                 link->cur_link_settings.link_rate_set = link_rate_set;
 697                                 link->cur_link_settings.use_link_rate_set = true;
 698                         }
 699                 } else {
 700                         // Link Rate not found. Seamless boot may not work.
 701                         ASSERT(false);
 702                 }
 703         } else {
 704                 link->cur_link_settings.link_rate = link_bw_set;
 705                 link->cur_link_settings.use_link_rate_set = false;
 706         }
 707         // Read DPCD 00003h to find the max down spread.
 708         core_link_read_dpcd(link, DP_MAX_DOWNSPREAD,
 709                             &max_down_spread.raw, sizeof(max_down_spread));
 710         link->cur_link_settings.link_spread =
 711                 max_down_spread.bits.MAX_DOWN_SPREAD ?
 712                 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
 713 }
 714
 715 static bool detect_dp(struct dc_link *link,
 716                       struct display_sink_capability *sink_caps,
 717                       enum dc_detect_reason reason)
 718 {
 719         struct audio_support *audio_support = &link->dc->res_pool->audio_support;
 720
 721         sink_caps->signal = link_detect_sink(link, reason);
 722         sink_caps->transaction_type =
 723                 get_ddc_transaction_type(sink_caps->signal);
 724
 725         if (sink_caps->transaction_type == DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
 726                 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
 727                 if (!detect_dp_sink_caps(link))
 728                         return false;
 729
 730                 if (is_dp_branch_device(link))
 731                         /* DP SST branch */
 732                         link->type = dc_connection_sst_branch;
 733         } else {
 734                 /* DP passive dongles */
 735                 sink_caps->signal = dp_passive_dongle_detection(link->ddc,
 736                                                                 sink_caps,
 737                                                                 audio_support);
 738                 link->dpcd_caps.dongle_type = sink_caps->dongle_type;
 739                 link->dpcd_caps.is_dongle_type_one = sink_caps->is_dongle_type_one;
 740                 link->dpcd_caps.dpcd_rev.raw = 0;
 741         }
 742
 743         return true;
 744 }
 745
 746 static bool is_same_edid(struct dc_edid *old_edid, struct dc_edid *new_edid)
 747 {
 748         if (old_edid->length != new_edid->length)
 749                 return false;
 750
 751         if (new_edid->length == 0)
 752                 return false;
 753
 754         return (memcmp(old_edid->raw_edid,
 755                        new_edid->raw_edid, new_edid->length) == 0);
 756 }
 757
 758 static bool wait_for_entering_dp_alt_mode(struct dc_link *link)
 759 {
 760         /**
 761          * something is terribly wrong if time out is > 200ms. (5Hz)
 762          * 500 microseconds * 400 tries us 200 ms
 763          **/
 764         unsigned int sleep_time_in_microseconds = 500;
 765         unsigned int tries_allowed = 400;
 766         bool is_in_alt_mode;
 767         unsigned long long enter_timestamp;
 768         unsigned long long finish_timestamp;
 769         unsigned long long time_taken_in_ns;
 770         int tries_taken;
 771
 772         DC_LOGGER_INIT(link->ctx->logger);
 773
 774         if (!link->link_enc->funcs->is_in_alt_mode)
 775                 return true;
 776
 777         is_in_alt_mode = link->link_enc->funcs->is_in_alt_mode(link->link_enc);
 778         DC_LOG_WARNING("DP Alt mode state on HPD: %d\n", is_in_alt_mode);
 779
 780         if (is_in_alt_mode)
 781                 return true;
 782
 783         enter_timestamp = dm_get_timestamp(link->ctx);
 784
 785         for (tries_taken = 0; tries_taken < tries_allowed; tries_taken++) {
 786                 udelay(sleep_time_in_microseconds);
 787                 /* ask the link if alt mode is enabled, if so return ok */
 788                 if (link->link_enc->funcs->is_in_alt_mode(link->link_enc)) {
 789                         finish_timestamp = dm_get_timestamp(link->ctx);
 790                         time_taken_in_ns =
 791                                 dm_get_elapse_time_in_ns(link->ctx,
 792                                                          finish_timestamp,
 793                                                          enter_timestamp);
 794                         DC_LOG_WARNING("Alt mode entered finished after %llu ms\n",
 795                                        div_u64(time_taken_in_ns, 1000000));
 796                         return true;
 797                 }
 798         }
 799         finish_timestamp = dm_get_timestamp(link->ctx);
 800         time_taken_in_ns = dm_get_elapse_time_in_ns(link->ctx, finish_timestamp,
 801                                                     enter_timestamp);
 802         DC_LOG_WARNING("Alt mode has timed out after %llu ms\n",
 803                        div_u64(time_taken_in_ns, 1000000));
 804         return false;
 805 }
 806
 807 static void apply_dpia_mst_dsc_always_on_wa(struct dc_link *link)
 808 {
 809         /* Apply work around for tunneled MST on certain USB4 docks. Always use DSC if dock
 810          * reports DSC support.
 811          */
 812         if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA &&
 813                         link->type == dc_connection_mst_branch &&
 814                         link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 &&
 815                         link->dpcd_caps.branch_hw_revision == DP_BRANCH_HW_REV_20 &&
 816                         link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT &&
 817                         !link->dc->debug.dpia_debug.bits.disable_mst_dsc_work_around)
 818                 link->wa_flags.dpia_mst_dsc_always_on = true;
 819 }
 820
 821 static void revert_dpia_mst_dsc_always_on_wa(struct dc_link *link)
 822 {
 823         /* Disable work around which keeps DSC on for tunneled MST on certain USB4 docks. */
 824         if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
 825                 link->wa_flags.dpia_mst_dsc_always_on = false;
 826 }
 827
 828 static bool discover_dp_mst_topology(struct dc_link *link, enum dc_detect_reason reason)
 829 {
 830         DC_LOGGER_INIT(link->ctx->logger);
 831
 832         LINK_INFO("link=%d, mst branch is now Connected\n",
 833                   link->link_index);
 834
 835         apply_dpia_mst_dsc_always_on_wa(link);
 836         link->type = dc_connection_mst_branch;
 837         dm_helpers_dp_update_branch_info(link->ctx, link);
 838         if (dm_helpers_dp_mst_start_top_mgr(link->ctx,
 839                         link, (reason == DETECT_REASON_BOOT || reason == DETECT_REASON_RESUMEFROMS3S4))) {
 840                 link_disconnect_sink(link);
 841         } else {
 842                 link->type = dc_connection_sst_branch;
 843         }
 844
 845         return link->type == dc_connection_mst_branch;
 846 }
 847
 848 bool reset_cur_dp_mst_topology(struct dc_link *link)
 849 {
 850         bool result = false;
 851         DC_LOGGER_INIT(link->ctx->logger);
 852
 853         LINK_INFO("link=%d, mst branch is now Disconnected\n",
 854                   link->link_index);
 855
 856         revert_dpia_mst_dsc_always_on_wa(link);
 857         result = dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
 858
 859         link->mst_stream_alloc_table.stream_count = 0;
 860         memset(link->mst_stream_alloc_table.stream_allocations,
 861                         0,
 862                         sizeof(link->mst_stream_alloc_table.stream_allocations));
 863         return result;
 864 }
 865
 866 static bool should_prepare_phy_clocks_for_link_verification(const struct dc *dc,
 867                 enum dc_detect_reason reason)
 868 {
 869         int i;
 870         bool can_apply_seamless_boot = false;
 871
 872         for (i = 0; i < dc->current_state->stream_count; i++) {
 873                 if (dc->current_state->streams[i]->apply_seamless_boot_optimization) {
 874                         can_apply_seamless_boot = true;
 875                         break;
 876                 }
 877         }
 878
 879         return !can_apply_seamless_boot && reason != DETECT_REASON_BOOT;
 880 }
 881
 882 static void prepare_phy_clocks_for_destructive_link_verification(const struct dc *dc)
 883 {
 884         dc_z10_restore(dc);
 885         clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr);
 886 }
 887
 888 static void restore_phy_clocks_for_destructive_link_verification(const struct dc *dc)
 889 {
 890         clk_mgr_optimize_pwr_state(dc, dc->clk_mgr);
 891 }
 892
 893 static void set_all_streams_dpms_off_for_link(struct dc_link *link)
 894 {
 895         int i;
 896         struct pipe_ctx *pipe_ctx;
 897         struct dc_stream_update stream_update;
 898         bool dpms_off = true;
 899         struct link_resource link_res = {0};
 900
 901         memset(&stream_update, 0, sizeof(stream_update));
 902         stream_update.dpms_off = &dpms_off;
 903
 904         for (i = 0; i < MAX_PIPES; i++) {
 905                 pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
 906                 if (pipe_ctx && pipe_ctx->stream && !pipe_ctx->stream->dpms_off &&
 907                                 pipe_ctx->stream->link == link && !pipe_ctx->prev_odm_pipe) {
 908                         stream_update.stream = pipe_ctx->stream;
 909                         dc_commit_updates_for_stream(link->ctx->dc, NULL, 0,
 910                                         pipe_ctx->stream, &stream_update,
 911                                         link->ctx->dc->current_state);
 912                 }
 913         }
 914
 915         /* link can be also enabled by vbios. In this case it is not recorded
 916          * in pipe_ctx. Disable link phy here to make sure it is completely off
 917          */
 918         dp_disable_link_phy(link, &link_res, link->connector_signal);
 919 }
 920
 921 static void verify_link_capability_destructive(struct dc_link *link,
 922                 struct dc_sink *sink,
 923                 enum dc_detect_reason reason)
 924 {
 925         bool should_prepare_phy_clocks =
 926                         should_prepare_phy_clocks_for_link_verification(link->dc, reason);
 927
 928         if (should_prepare_phy_clocks)
 929                 prepare_phy_clocks_for_destructive_link_verification(link->dc);
 930
 931         if (dc_is_dp_signal(link->local_sink->sink_signal)) {
 932                 struct dc_link_settings known_limit_link_setting =
 933                                 dp_get_max_link_cap(link);
 934                 set_all_streams_dpms_off_for_link(link);
 935                 dp_verify_link_cap_with_retries(
 936                                 link, &known_limit_link_setting,
 937                                 LINK_TRAINING_MAX_VERIFY_RETRY);
 938         } else {
 939                 ASSERT(0);
 940         }
 941
 942         if (should_prepare_phy_clocks)
 943                 restore_phy_clocks_for_destructive_link_verification(link->dc);
 944 }
 945
 946 static void verify_link_capability_non_destructive(struct dc_link *link)
 947 {
 948         if (dc_is_dp_signal(link->local_sink->sink_signal)) {
 949                 if (dc_is_embedded_signal(link->local_sink->sink_signal) ||
 950                                 link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
 951                         /* TODO - should we check link encoder's max link caps here?
 952                          * How do we know which link encoder to check from?
 953                          */
 954                         link->verified_link_cap = link->reported_link_cap;
 955                 else
 956                         link->verified_link_cap = dp_get_max_link_cap(link);
 957         }
 958 }
 959
 960 static bool should_verify_link_capability_destructively(struct dc_link *link,
 961                 enum dc_detect_reason reason)
 962 {
 963         bool destrictive = false;
 964         struct dc_link_settings max_link_cap;
 965         bool is_link_enc_unavailable = link->link_enc &&
 966                         link->dc->res_pool->funcs->link_encs_assign &&
 967                         !link_enc_cfg_is_link_enc_avail(
 968                                         link->ctx->dc,
 969                                         link->link_enc->preferred_engine,
 970                                         link);
 971
 972         if (dc_is_dp_signal(link->local_sink->sink_signal)) {
 973                 max_link_cap = dp_get_max_link_cap(link);
 974                 destrictive = true;
 975
 976                 if (link->dc->debug.skip_detection_link_training ||
 977                                 dc_is_embedded_signal(link->local_sink->sink_signal) ||
 978                                 link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) {
 979                         destrictive = false;
 980                 } else if (dp_get_link_encoding_format(&max_link_cap) ==
 981                                 DP_8b_10b_ENCODING) {
 982                         if (link->dpcd_caps.is_mst_capable ||
 983                                         is_link_enc_unavailable) {
 984                                 destrictive = false;
 985                         }
 986                 }
 987         }
 988
 989         return destrictive;
 990 }
 991
 992 static void verify_link_capability(struct dc_link *link, struct dc_sink *sink,
 993                 enum dc_detect_reason reason)
 994 {
 995         if (should_verify_link_capability_destructively(link, reason))
 996                 verify_link_capability_destructive(link, sink, reason);
 997         else
 998                 verify_link_capability_non_destructive(link);
 999 }
1000
1001
1002 /**
1003  * detect_link_and_local_sink() - Detect if a sink is attached to a given link
1004  *
1005  * link->local_sink is created or destroyed as needed.
1006  *
1007  * This does not create remote sinks.
1008  */
1009 static bool detect_link_and_local_sink(struct dc_link *link,
1010                                   enum dc_detect_reason reason)
1011 {
1012         struct dc_sink_init_data sink_init_data = { 0 };
1013         struct display_sink_capability sink_caps = { 0 };
1014         uint32_t i;
1015         bool converter_disable_audio = false;
1016         struct audio_support *aud_support = &link->dc->res_pool->audio_support;
1017         bool same_edid = false;
1018         enum dc_edid_status edid_status;
1019         struct dc_context *dc_ctx = link->ctx;
1020         struct dc *dc = dc_ctx->dc;
1021         struct dc_sink *sink = NULL;
1022         struct dc_sink *prev_sink = NULL;
1023         struct dpcd_caps prev_dpcd_caps;
1024         enum dc_connection_type new_connection_type = dc_connection_none;
1025         const uint32_t post_oui_delay = 30; // 30ms
1026
1027         DC_LOGGER_INIT(link->ctx->logger);
1028
1029         if (dc_is_virtual_signal(link->connector_signal))
1030                 return false;
1031
1032         if (((link->connector_signal == SIGNAL_TYPE_LVDS ||
1033                 link->connector_signal == SIGNAL_TYPE_EDP) &&
1034                 (!link->dc->config.allow_edp_hotplug_detection)) &&
1035                 link->local_sink) {
1036                 // need to re-write OUI and brightness in resume case
1037                 if (link->connector_signal == SIGNAL_TYPE_EDP &&
1038                         (link->dpcd_sink_ext_caps.bits.oled == 1)) {
1039                         dpcd_set_source_specific_data(link);
1040                         msleep(post_oui_delay);
1041                         dc_link_set_default_brightness_aux(link);
1042                         //TODO: use cached
1043                 }
1044
1045                 return true;
1046         }
1047
1048         if (!dc_link_detect_sink(link, &new_connection_type)) {
1049                 BREAK_TO_DEBUGGER();
1050                 return false;
1051         }
1052
1053         prev_sink = link->local_sink;
1054         if (prev_sink) {
1055                 dc_sink_retain(prev_sink);
1056                 memcpy(&prev_dpcd_caps, &link->dpcd_caps, sizeof(struct dpcd_caps));
1057         }
1058
1059         link_disconnect_sink(link);
1060         if (new_connection_type != dc_connection_none) {
1061                 link->type = new_connection_type;
1062                 link->link_state_valid = false;
1063
1064                 /* From Disconnected-to-Connected. */
1065                 switch (link->connector_signal) {
1066                 case SIGNAL_TYPE_HDMI_TYPE_A: {
1067                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1068                         if (aud_support->hdmi_audio_native)
1069                                 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
1070                         else
1071                                 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1072                         break;
1073                 }
1074
1075                 case SIGNAL_TYPE_DVI_SINGLE_LINK: {
1076                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1077                         sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1078                         break;
1079                 }
1080
1081                 case SIGNAL_TYPE_DVI_DUAL_LINK: {
1082                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1083                         sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
1084                         break;
1085                 }
1086
1087                 case SIGNAL_TYPE_LVDS: {
1088                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1089                         sink_caps.signal = SIGNAL_TYPE_LVDS;
1090                         break;
1091                 }
1092
1093                 case SIGNAL_TYPE_EDP: {
1094                         read_current_link_settings_on_detect(link);
1095
1096                         detect_edp_sink_caps(link);
1097                         read_current_link_settings_on_detect(link);
1098
1099                         /* Disable power sequence on MIPI panel + converter
1100                          */
1101                         if (dc->config.enable_mipi_converter_optimization &&
1102                                 dc_ctx->dce_version == DCN_VERSION_3_01 &&
1103                                 link->dpcd_caps.sink_dev_id == DP_BRANCH_DEVICE_ID_0022B9 &&
1104                                 memcmp(&link->dpcd_caps.branch_dev_name, DP_SINK_BRANCH_DEV_NAME_7580,
1105                                         sizeof(link->dpcd_caps.branch_dev_name)) == 0) {
1106                                 dc->config.edp_no_power_sequencing = true;
1107
1108                                 if (!link->dpcd_caps.set_power_state_capable_edp)
1109                                         link->wa_flags.dp_keep_receiver_powered = true;
1110                         }
1111
1112                         sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
1113                         sink_caps.signal = SIGNAL_TYPE_EDP;
1114                         break;
1115                 }
1116
1117                 case SIGNAL_TYPE_DISPLAY_PORT: {
1118                         /* wa HPD high coming too early*/
1119                         if (link->ep_type == DISPLAY_ENDPOINT_PHY &&
1120                             link->link_enc->features.flags.bits.DP_IS_USB_C == 1) {
1121                                 /* if alt mode times out, return false */
1122                                 if (!wait_for_entering_dp_alt_mode(link))
1123                                         return false;
1124                         }
1125
1126                         if (!detect_dp(link, &sink_caps, reason)) {
1127                                 if (prev_sink)
1128                                         dc_sink_release(prev_sink);
1129                                 return false;
1130                         }
1131
1132                         /* Active SST downstream branch device unplug*/
1133                         if (link->type == dc_connection_sst_branch &&
1134                             link->dpcd_caps.sink_count.bits.SINK_COUNT == 0) {
1135                                 if (prev_sink)
1136                                         /* Downstream unplug */
1137                                         dc_sink_release(prev_sink);
1138                                 return true;
1139                         }
1140
1141                         /* disable audio for non DP to HDMI active sst converter */
1142                         if (link->type == dc_connection_sst_branch &&
1143                                         is_dp_active_dongle(link) &&
1144                                         (link->dpcd_caps.dongle_type !=
1145                                                         DISPLAY_DONGLE_DP_HDMI_CONVERTER))
1146                                 converter_disable_audio = true;
1147                         break;
1148                 }
1149
1150                 default:
1151                         DC_ERROR("Invalid connector type! signal:%d\n",
1152                                  link->connector_signal);
1153                         if (prev_sink)
1154                                 dc_sink_release(prev_sink);
1155                         return false;
1156                 } /* switch() */
1157
1158                 if (link->dpcd_caps.sink_count.bits.SINK_COUNT)
1159                         link->dpcd_sink_count =
1160                                 link->dpcd_caps.sink_count.bits.SINK_COUNT;
1161                 else
1162                         link->dpcd_sink_count = 1;
1163
1164                 dal_ddc_service_set_transaction_type(link->ddc,
1165                                                      sink_caps.transaction_type);
1166
1167                 link->aux_mode =
1168                         dal_ddc_service_is_in_aux_transaction_mode(link->ddc);
1169
1170                 sink_init_data.link = link;
1171                 sink_init_data.sink_signal = sink_caps.signal;
1172
1173                 sink = dc_sink_create(&sink_init_data);
1174                 if (!sink) {
1175                         DC_ERROR("Failed to create sink!\n");
1176                         if (prev_sink)
1177                                 dc_sink_release(prev_sink);
1178                         return false;
1179                 }
1180
1181                 sink->link->dongle_max_pix_clk = sink_caps.max_hdmi_pixel_clock;
1182                 sink->converter_disable_audio = converter_disable_audio;
1183
1184                 /* dc_sink_create returns a new reference */
1185                 link->local_sink = sink;
1186
1187                 edid_status = dm_helpers_read_local_edid(link->ctx,
1188                                                          link, sink);
1189
1190                 switch (edid_status) {
1191                 case EDID_BAD_CHECKSUM:
1192                         DC_LOG_ERROR("EDID checksum invalid.\n");
1193                         break;
1194                 case EDID_PARTIAL_VALID:
1195                         DC_LOG_ERROR("Partial EDID valid, abandon invalid blocks.\n");
1196                         break;
1197                 case EDID_NO_RESPONSE:
1198                         DC_LOG_ERROR("No EDID read.\n");
1199                         /*
1200                          * Abort detection for non-DP connectors if we have
1201                          * no EDID
1202                          *
1203                          * DP needs to report as connected if HDP is high
1204                          * even if we have no EDID in order to go to
1205                          * fail-safe mode
1206                          */
1207                         if (dc_is_hdmi_signal(link->connector_signal) ||
1208                             dc_is_dvi_signal(link->connector_signal)) {
1209                                 if (prev_sink)
1210                                         dc_sink_release(prev_sink);
1211
1212                                 return false;
1213                         }
1214
1215                         if (link->type == dc_connection_sst_branch &&
1216                                         link->dpcd_caps.dongle_type ==
1217                                                 DISPLAY_DONGLE_DP_VGA_CONVERTER &&
1218                                         reason == DETECT_REASON_HPDRX) {
1219                                 /* Abort detection for DP-VGA adapters when EDID
1220                                  * can't be read and detection reason is VGA-side
1221                                  * hotplug
1222                                  */
1223                                 if (prev_sink)
1224                                         dc_sink_release(prev_sink);
1225                                 link_disconnect_sink(link);
1226
1227                                 return true;
1228                         }
1229
1230                         break;
1231                 default:
1232                         break;
1233                 }
1234
1235                 // Check if edid is the same
1236                 if ((prev_sink) &&
1237                     (edid_status == EDID_THE_SAME || edid_status == EDID_OK))
1238                         same_edid = is_same_edid(&prev_sink->dc_edid,
1239                                                  &sink->dc_edid);
1240
1241                 if (sink->edid_caps.panel_patch.skip_scdc_overwrite)
1242                         link->ctx->dc->debug.hdmi20_disable = true;
1243
1244                 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
1245                     sink_caps.transaction_type ==
1246                     DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
1247                         /*
1248                          * TODO debug why Dell 2413 doesn't like
1249                          *  two link trainings
1250                          */
1251 #if defined(CONFIG_DRM_AMD_DC_HDCP)
1252                         query_hdcp_capability(sink->sink_signal, link);
1253 #endif
1254                 } else {
1255                         // If edid is the same, then discard new sink and revert back to original sink
1256                         if (same_edid) {
1257                                 link_disconnect_remap(prev_sink, link);
1258                                 sink = prev_sink;
1259                                 prev_sink = NULL;
1260                         }
1261 #if defined(CONFIG_DRM_AMD_DC_HDCP)
1262                         query_hdcp_capability(sink->sink_signal, link);
1263 #endif
1264                 }
1265
1266                 /* HDMI-DVI Dongle */
1267                 if (sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A &&
1268                     !sink->edid_caps.edid_hdmi)
1269                         sink->sink_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1270
1271                 if (link->local_sink && dc_is_dp_signal(sink_caps.signal))
1272                         dp_trace_init(link);
1273
1274                 /* Connectivity log: detection */
1275                 for (i = 0; i < sink->dc_edid.length / DC_EDID_BLOCK_SIZE; i++) {
1276                         CONN_DATA_DETECT(link,
1277                                          &sink->dc_edid.raw_edid[i * DC_EDID_BLOCK_SIZE],
1278                                          DC_EDID_BLOCK_SIZE,
1279                                          "%s: [Block %d] ", sink->edid_caps.display_name, i);
1280                 }
1281
1282                 DC_LOG_DETECTION_EDID_PARSER("%s: "
1283                         "manufacturer_id = %X, "
1284                         "product_id = %X, "
1285                         "serial_number = %X, "
1286                         "manufacture_week = %d, "
1287                         "manufacture_year = %d, "
1288                         "display_name = %s, "
1289                         "speaker_flag = %d, "
1290                         "audio_mode_count = %d\n",
1291                         __func__,
1292                         sink->edid_caps.manufacturer_id,
1293                         sink->edid_caps.product_id,
1294                         sink->edid_caps.serial_number,
1295                         sink->edid_caps.manufacture_week,
1296                         sink->edid_caps.manufacture_year,
1297                         sink->edid_caps.display_name,
1298                         sink->edid_caps.speaker_flags,
1299                         sink->edid_caps.audio_mode_count);
1300
1301                 for (i = 0; i < sink->edid_caps.audio_mode_count; i++) {
1302                         DC_LOG_DETECTION_EDID_PARSER("%s: mode number = %d, "
1303                                 "format_code = %d, "
1304                                 "channel_count = %d, "
1305                                 "sample_rate = %d, "
1306                                 "sample_size = %d\n",
1307                                 __func__,
1308                                 i,
1309                                 sink->edid_caps.audio_modes[i].format_code,
1310                                 sink->edid_caps.audio_modes[i].channel_count,
1311                                 sink->edid_caps.audio_modes[i].sample_rate,
1312                                 sink->edid_caps.audio_modes[i].sample_size);
1313                 }
1314
1315                 if (link->connector_signal == SIGNAL_TYPE_EDP) {
1316                         // Init dc_panel_config
1317                         dm_helpers_init_panel_settings(dc_ctx, &link->panel_config);
1318                         // Override dc_panel_config if system has specific settings
1319                         dm_helpers_override_panel_settings(dc_ctx, &link->panel_config);
1320                 }
1321
1322         } else {
1323                 /* From Connected-to-Disconnected. */
1324                 link->type = dc_connection_none;
1325                 sink_caps.signal = SIGNAL_TYPE_NONE;
1326                 /* When we unplug a passive DP-HDMI dongle connection, dongle_max_pix_clk
1327                  *  is not cleared. If we emulate a DP signal on this connection, it thinks
1328                  *  the dongle is still there and limits the number of modes we can emulate.
1329                  *  Clear dongle_max_pix_clk on disconnect to fix this
1330                  */
1331                 link->dongle_max_pix_clk = 0;
1332
1333                 dc_link_clear_dprx_states(link);
1334                 dp_trace_reset(link);
1335         }
1336
1337         LINK_INFO("link=%d, dc_sink_in=%p is now %s prev_sink=%p edid same=%d\n",
1338                   link->link_index, sink,
1339                   (sink_caps.signal ==
1340                    SIGNAL_TYPE_NONE ? "Disconnected" : "Connected"),
1341                   prev_sink, same_edid);
1342
1343         if (prev_sink)
1344                 dc_sink_release(prev_sink);
1345
1346         return true;
1347 }
1348
1349 bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
1350 {
1351         bool is_local_sink_detect_success;
1352         bool is_delegated_to_mst_top_mgr = false;
1353         enum dc_connection_type pre_link_type = link->type;
1354
1355         is_local_sink_detect_success = detect_link_and_local_sink(link, reason);
1356
1357         if (is_local_sink_detect_success && link->local_sink)
1358                 verify_link_capability(link, link->local_sink, reason);
1359
1360         if (is_local_sink_detect_success && link->local_sink &&
1361                         dc_is_dp_signal(link->local_sink->sink_signal) &&
1362                         link->dpcd_caps.is_mst_capable)
1363                 is_delegated_to_mst_top_mgr = discover_dp_mst_topology(link, reason);
1364
1365         if (is_local_sink_detect_success &&
1366                         pre_link_type == dc_connection_mst_branch &&
1367                         link->type != dc_connection_mst_branch)
1368                 is_delegated_to_mst_top_mgr = reset_cur_dp_mst_topology(link);
1369
1370         return is_local_sink_detect_success && !is_delegated_to_mst_top_mgr;
1371 }
1372
1373 bool dc_link_get_hpd_state(struct dc_link *dc_link)
1374 {
1375         uint32_t state;
1376
1377         dal_gpio_lock_pin(dc_link->hpd_gpio);
1378         dal_gpio_get_value(dc_link->hpd_gpio, &state);
1379         dal_gpio_unlock_pin(dc_link->hpd_gpio);
1380
1381         return state;
1382 }
1383
1384 static enum hpd_source_id get_hpd_line(struct dc_link *link)
1385 {
1386         struct gpio *hpd;
1387         enum hpd_source_id hpd_id;
1388
1389         hpd_id = HPD_SOURCEID_UNKNOWN;
1390
1391         hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
1392                            link->ctx->gpio_service);
1393
1394         if (hpd) {
1395                 switch (dal_irq_get_source(hpd)) {
1396                 case DC_IRQ_SOURCE_HPD1:
1397                         hpd_id = HPD_SOURCEID1;
1398                 break;
1399                 case DC_IRQ_SOURCE_HPD2:
1400                         hpd_id = HPD_SOURCEID2;
1401                 break;
1402                 case DC_IRQ_SOURCE_HPD3:
1403                         hpd_id = HPD_SOURCEID3;
1404                 break;
1405                 case DC_IRQ_SOURCE_HPD4:
1406                         hpd_id = HPD_SOURCEID4;
1407                 break;
1408                 case DC_IRQ_SOURCE_HPD5:
1409                         hpd_id = HPD_SOURCEID5;
1410                 break;
1411                 case DC_IRQ_SOURCE_HPD6:
1412                         hpd_id = HPD_SOURCEID6;
1413                 break;
1414                 default:
1415                         BREAK_TO_DEBUGGER();
1416                 break;
1417                 }
1418
1419                 dal_gpio_destroy_irq(&hpd);
1420         }
1421
1422         return hpd_id;
1423 }
1424
1425 static enum channel_id get_ddc_line(struct dc_link *link)
1426 {
1427         struct ddc *ddc;
1428         enum channel_id channel;
1429
1430         channel = CHANNEL_ID_UNKNOWN;
1431
1432         ddc = dal_ddc_service_get_ddc_pin(link->ddc);
1433
1434         if (ddc) {
1435                 switch (dal_ddc_get_line(ddc)) {
1436                 case GPIO_DDC_LINE_DDC1:
1437                         channel = CHANNEL_ID_DDC1;
1438                         break;
1439                 case GPIO_DDC_LINE_DDC2:
1440                         channel = CHANNEL_ID_DDC2;
1441                         break;
1442                 case GPIO_DDC_LINE_DDC3:
1443                         channel = CHANNEL_ID_DDC3;
1444                         break;
1445                 case GPIO_DDC_LINE_DDC4:
1446                         channel = CHANNEL_ID_DDC4;
1447                         break;
1448                 case GPIO_DDC_LINE_DDC5:
1449                         channel = CHANNEL_ID_DDC5;
1450                         break;
1451                 case GPIO_DDC_LINE_DDC6:
1452                         channel = CHANNEL_ID_DDC6;
1453                         break;
1454                 case GPIO_DDC_LINE_DDC_VGA:
1455                         channel = CHANNEL_ID_DDC_VGA;
1456                         break;
1457                 case GPIO_DDC_LINE_I2C_PAD:
1458                         channel = CHANNEL_ID_I2C_PAD;
1459                         break;
1460                 default:
1461                         BREAK_TO_DEBUGGER();
1462                         break;
1463                 }
1464         }
1465
1466         return channel;
1467 }
1468
1469 static enum transmitter translate_encoder_to_transmitter(struct graphics_object_id encoder)
1470 {
1471         switch (encoder.id) {
1472         case ENCODER_ID_INTERNAL_UNIPHY:
1473                 switch (encoder.enum_id) {
1474                 case ENUM_ID_1:
1475                         return TRANSMITTER_UNIPHY_A;
1476                 case ENUM_ID_2:
1477                         return TRANSMITTER_UNIPHY_B;
1478                 default:
1479                         return TRANSMITTER_UNKNOWN;
1480                 }
1481         break;
1482         case ENCODER_ID_INTERNAL_UNIPHY1:
1483                 switch (encoder.enum_id) {
1484                 case ENUM_ID_1:
1485                         return TRANSMITTER_UNIPHY_C;
1486                 case ENUM_ID_2:
1487                         return TRANSMITTER_UNIPHY_D;
1488                 default:
1489                         return TRANSMITTER_UNKNOWN;
1490                 }
1491         break;
1492         case ENCODER_ID_INTERNAL_UNIPHY2:
1493                 switch (encoder.enum_id) {
1494                 case ENUM_ID_1:
1495                         return TRANSMITTER_UNIPHY_E;
1496                 case ENUM_ID_2:
1497                         return TRANSMITTER_UNIPHY_F;
1498                 default:
1499                         return TRANSMITTER_UNKNOWN;
1500                 }
1501         break;
1502         case ENCODER_ID_INTERNAL_UNIPHY3:
1503                 switch (encoder.enum_id) {
1504                 case ENUM_ID_1:
1505                         return TRANSMITTER_UNIPHY_G;
1506                 default:
1507                         return TRANSMITTER_UNKNOWN;
1508                 }
1509         break;
1510         case ENCODER_ID_EXTERNAL_NUTMEG:
1511                 switch (encoder.enum_id) {
1512                 case ENUM_ID_1:
1513                         return TRANSMITTER_NUTMEG_CRT;
1514                 default:
1515                         return TRANSMITTER_UNKNOWN;
1516                 }
1517         break;
1518         case ENCODER_ID_EXTERNAL_TRAVIS:
1519                 switch (encoder.enum_id) {
1520                 case ENUM_ID_1:
1521                         return TRANSMITTER_TRAVIS_CRT;
1522                 case ENUM_ID_2:
1523                         return TRANSMITTER_TRAVIS_LCD;
1524                 default:
1525                         return TRANSMITTER_UNKNOWN;
1526                 }
1527         break;
1528         default:
1529                 return TRANSMITTER_UNKNOWN;
1530         }
1531 }
1532
1533 static bool dc_link_construct_legacy(struct dc_link *link,
1534                                      const struct link_init_data *init_params)
1535 {
1536         uint8_t i;
1537         struct ddc_service_init_data ddc_service_init_data = { 0 };
1538         struct dc_context *dc_ctx = init_params->ctx;
1539         struct encoder_init_data enc_init_data = { 0 };
1540         struct panel_cntl_init_data panel_cntl_init_data = { 0 };
1541         struct integrated_info *info;
1542         struct dc_bios *bios = init_params->dc->ctx->dc_bios;
1543         const struct dc_vbios_funcs *bp_funcs = bios->funcs;
1544         struct bp_disp_connector_caps_info disp_connect_caps_info = { 0 };
1545
1546         DC_LOGGER_INIT(dc_ctx->logger);
1547
1548         info = kzalloc(sizeof(*info), GFP_KERNEL);
1549         if (!info)
1550                 goto create_fail;
1551
1552         link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1553         link->irq_source_hpd_rx = DC_IRQ_SOURCE_INVALID;
1554
1555         link->link_status.dpcd_caps = &link->dpcd_caps;
1556
1557         link->dc = init_params->dc;
1558         link->ctx = dc_ctx;
1559         link->link_index = init_params->link_index;
1560
1561         memset(&link->preferred_training_settings, 0,
1562                sizeof(struct dc_link_training_overrides));
1563         memset(&link->preferred_link_setting, 0,
1564                sizeof(struct dc_link_settings));
1565
1566         link->link_id =
1567                 bios->funcs->get_connector_id(bios, init_params->connector_index);
1568
1569         link->ep_type = DISPLAY_ENDPOINT_PHY;
1570
1571         DC_LOG_DC("BIOS object table - link_id: %d", link->link_id.id);
1572
1573         if (bios->funcs->get_disp_connector_caps_info) {
1574                 bios->funcs->get_disp_connector_caps_info(bios, link->link_id, &disp_connect_caps_info);
1575                 link->is_internal_display = disp_connect_caps_info.INTERNAL_DISPLAY;
1576                 DC_LOG_DC("BIOS object table - is_internal_display: %d", link->is_internal_display);
1577         }
1578
1579         if (link->link_id.type != OBJECT_TYPE_CONNECTOR) {
1580                 dm_output_to_console("%s: Invalid Connector ObjectID from Adapter Service for connector index:%d! type %d expected %d\n",
1581                                      __func__, init_params->connector_index,
1582                                      link->link_id.type, OBJECT_TYPE_CONNECTOR);
1583                 goto create_fail;
1584         }
1585
1586         if (link->dc->res_pool->funcs->link_init)
1587                 link->dc->res_pool->funcs->link_init(link);
1588
1589         link->hpd_gpio = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
1590                                       link->ctx->gpio_service);
1591
1592         if (link->hpd_gpio) {
1593                 dal_gpio_open(link->hpd_gpio, GPIO_MODE_INTERRUPT);
1594                 dal_gpio_unlock_pin(link->hpd_gpio);
1595                 link->irq_source_hpd = dal_irq_get_source(link->hpd_gpio);
1596
1597                 DC_LOG_DC("BIOS object table - hpd_gpio id: %d", link->hpd_gpio->id);
1598                 DC_LOG_DC("BIOS object table - hpd_gpio en: %d", link->hpd_gpio->en);
1599         }
1600
1601         switch (link->link_id.id) {
1602         case CONNECTOR_ID_HDMI_TYPE_A:
1603                 link->connector_signal = SIGNAL_TYPE_HDMI_TYPE_A;
1604
1605                 break;
1606         case CONNECTOR_ID_SINGLE_LINK_DVID:
1607         case CONNECTOR_ID_SINGLE_LINK_DVII:
1608                 link->connector_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1609                 break;
1610         case CONNECTOR_ID_DUAL_LINK_DVID:
1611         case CONNECTOR_ID_DUAL_LINK_DVII:
1612                 link->connector_signal = SIGNAL_TYPE_DVI_DUAL_LINK;
1613                 break;
1614         case CONNECTOR_ID_DISPLAY_PORT:
1615         case CONNECTOR_ID_USBC:
1616                 link->connector_signal = SIGNAL_TYPE_DISPLAY_PORT;
1617
1618                 if (link->hpd_gpio)
1619                         link->irq_source_hpd_rx =
1620                                         dal_irq_get_rx_source(link->hpd_gpio);
1621
1622                 break;
1623         case CONNECTOR_ID_EDP:
1624                 link->connector_signal = SIGNAL_TYPE_EDP;
1625
1626                 if (link->hpd_gpio) {
1627                         if (!link->dc->config.allow_edp_hotplug_detection)
1628                                 link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1629
1630                         switch (link->dc->config.allow_edp_hotplug_detection) {
1631                         case 1: // only the 1st eDP handles hotplug
1632                                 if (link->link_index == 0)
1633                                         link->irq_source_hpd_rx =
1634                                                 dal_irq_get_rx_source(link->hpd_gpio);
1635                                 else
1636                                         link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1637                                 break;
1638                         case 2: // only the 2nd eDP handles hotplug
1639                                 if (link->link_index == 1)
1640                                         link->irq_source_hpd_rx =
1641                                                 dal_irq_get_rx_source(link->hpd_gpio);
1642                                 else
1643                                         link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1644                                 break;
1645                         default:
1646                                 break;
1647                         }
1648                 }
1649
1650                 break;
1651         case CONNECTOR_ID_LVDS:
1652                 link->connector_signal = SIGNAL_TYPE_LVDS;
1653                 break;
1654         default:
1655                 DC_LOG_WARNING("Unsupported Connector type:%d!\n",
1656                                link->link_id.id);
1657                 goto create_fail;
1658         }
1659
1660         /* TODO: #DAL3 Implement id to str function.*/
1661         LINK_INFO("Connector[%d] description:"
1662                   "signal %d\n",
1663                   init_params->connector_index,
1664                   link->connector_signal);
1665
1666         ddc_service_init_data.ctx = link->ctx;
1667         ddc_service_init_data.id = link->link_id;
1668         ddc_service_init_data.link = link;
1669         link->ddc = dal_ddc_service_create(&ddc_service_init_data);
1670
1671         if (!link->ddc) {
1672                 DC_ERROR("Failed to create ddc_service!\n");
1673                 goto ddc_create_fail;
1674         }
1675
1676         if (!link->ddc->ddc_pin) {
1677                 DC_ERROR("Failed to get I2C info for connector!\n");
1678                 goto ddc_create_fail;
1679         }
1680
1681         link->ddc_hw_inst =
1682                 dal_ddc_get_line(dal_ddc_service_get_ddc_pin(link->ddc));
1683
1684
1685         if (link->dc->res_pool->funcs->panel_cntl_create &&
1686                 (link->link_id.id == CONNECTOR_ID_EDP ||
1687                         link->link_id.id == CONNECTOR_ID_LVDS)) {
1688                 panel_cntl_init_data.ctx = dc_ctx;
1689                 panel_cntl_init_data.inst =
1690                         panel_cntl_init_data.ctx->dc_edp_id_count;
1691                 link->panel_cntl =
1692                         link->dc->res_pool->funcs->panel_cntl_create(
1693                                                                 &panel_cntl_init_data);
1694                 panel_cntl_init_data.ctx->dc_edp_id_count++;
1695
1696                 if (link->panel_cntl == NULL) {
1697                         DC_ERROR("Failed to create link panel_cntl!\n");
1698                         goto panel_cntl_create_fail;
1699                 }
1700         }
1701
1702         enc_init_data.ctx = dc_ctx;
1703         bp_funcs->get_src_obj(dc_ctx->dc_bios, link->link_id, 0,
1704                               &enc_init_data.encoder);
1705         enc_init_data.connector = link->link_id;
1706         enc_init_data.channel = get_ddc_line(link);
1707         enc_init_data.hpd_source = get_hpd_line(link);
1708
1709         link->hpd_src = enc_init_data.hpd_source;
1710
1711         enc_init_data.transmitter =
1712                 translate_encoder_to_transmitter(enc_init_data.encoder);
1713         link->link_enc =
1714                 link->dc->res_pool->funcs->link_enc_create(dc_ctx, &enc_init_data);
1715
1716         if (!link->link_enc) {
1717                 DC_ERROR("Failed to create link encoder!\n");
1718                 goto link_enc_create_fail;
1719         }
1720
1721         DC_LOG_DC("BIOS object table - DP_IS_USB_C: %d", link->link_enc->features.flags.bits.DP_IS_USB_C);
1722         DC_LOG_DC("BIOS object table - IS_DP2_CAPABLE: %d", link->link_enc->features.flags.bits.IS_DP2_CAPABLE);
1723
1724         /* Update link encoder tracking variables. These are used for the dynamic
1725          * assignment of link encoders to streams.
1726          */
1727         link->eng_id = link->link_enc->preferred_engine;
1728         link->dc->res_pool->link_encoders[link->eng_id - ENGINE_ID_DIGA] = link->link_enc;
1729         link->dc->res_pool->dig_link_enc_count++;
1730
1731         link->link_enc_hw_inst = link->link_enc->transmitter;
1732
1733         for (i = 0; i < 4; i++) {
1734                 if (bp_funcs->get_device_tag(dc_ctx->dc_bios,
1735                                              link->link_id, i,
1736                                              &link->device_tag) != BP_RESULT_OK) {
1737                         DC_ERROR("Failed to find device tag!\n");
1738                         goto device_tag_fail;
1739                 }
1740
1741                 /* Look for device tag that matches connector signal,
1742                  * CRT for rgb, LCD for other supported signal tyes
1743                  */
1744                 if (!bp_funcs->is_device_id_supported(dc_ctx->dc_bios,
1745                                                       link->device_tag.dev_id))
1746                         continue;
1747                 if (link->device_tag.dev_id.device_type == DEVICE_TYPE_CRT &&
1748                     link->connector_signal != SIGNAL_TYPE_RGB)
1749                         continue;
1750                 if (link->device_tag.dev_id.device_type == DEVICE_TYPE_LCD &&
1751                     link->connector_signal == SIGNAL_TYPE_RGB)
1752                         continue;
1753
1754                 DC_LOG_DC("BIOS object table - device_tag.acpi_device: %d", link->device_tag.acpi_device);
1755                 DC_LOG_DC("BIOS object table - device_tag.dev_id.device_type: %d", link->device_tag.dev_id.device_type);
1756                 DC_LOG_DC("BIOS object table - device_tag.dev_id.enum_id: %d", link->device_tag.dev_id.enum_id);
1757                 break;
1758         }
1759
1760         if (bios->integrated_info)
1761                 memcpy(info, bios->integrated_info, sizeof(*info));
1762
1763         /* Look for channel mapping corresponding to connector and device tag */
1764         for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; i++) {
1765                 struct external_display_path *path =
1766                         &info->ext_disp_conn_info.path[i];
1767
1768                 if (path->device_connector_id.enum_id == link->link_id.enum_id &&
1769                     path->device_connector_id.id == link->link_id.id &&
1770                     path->device_connector_id.type == link->link_id.type) {
1771                         if (link->device_tag.acpi_device != 0 &&
1772                             path->device_acpi_enum == link->device_tag.acpi_device) {
1773                                 link->ddi_channel_mapping = path->channel_mapping;
1774                                 link->chip_caps = path->caps;
1775                                 DC_LOG_DC("BIOS object table - ddi_channel_mapping: 0x%04X", link->ddi_channel_mapping.raw);
1776                                 DC_LOG_DC("BIOS object table - chip_caps: %d", link->chip_caps);
1777                         } else if (path->device_tag ==
1778                                    link->device_tag.dev_id.raw_device_tag) {
1779                                 link->ddi_channel_mapping = path->channel_mapping;
1780                                 link->chip_caps = path->caps;
1781                                 DC_LOG_DC("BIOS object table - ddi_channel_mapping: 0x%04X", link->ddi_channel_mapping.raw);
1782                                 DC_LOG_DC("BIOS object table - chip_caps: %d", link->chip_caps);
1783                         }
1784
1785                         if (link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) {
1786                                 link->bios_forced_drive_settings.VOLTAGE_SWING =
1787                                                 (info->ext_disp_conn_info.fixdpvoltageswing & 0x3);
1788                                 link->bios_forced_drive_settings.PRE_EMPHASIS =
1789                                                 ((info->ext_disp_conn_info.fixdpvoltageswing >> 2) & 0x3);
1790                         }
1791
1792                         break;
1793                 }
1794         }
1795
1796         if (bios->funcs->get_atom_dc_golden_table)
1797                 bios->funcs->get_atom_dc_golden_table(bios);
1798
1799         /*
1800          * TODO check if GPIO programmed correctly
1801          *
1802          * If GPIO isn't programmed correctly HPD might not rise or drain
1803          * fast enough, leading to bounces.
1804          */
1805         program_hpd_filter(link);
1806
1807         link->psr_settings.psr_vtotal_control_support = false;
1808         link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
1809
1810         DC_LOG_DC("BIOS object table - %s finished successfully.\n", __func__);
1811         kfree(info);
1812         return true;
1813 device_tag_fail:
1814         link->link_enc->funcs->destroy(&link->link_enc);
1815 link_enc_create_fail:
1816         if (link->panel_cntl != NULL)
1817                 link->panel_cntl->funcs->destroy(&link->panel_cntl);
1818 panel_cntl_create_fail:
1819         dal_ddc_service_destroy(&link->ddc);
1820 ddc_create_fail:
1821 create_fail:
1822
1823         if (link->hpd_gpio) {
1824                 dal_gpio_destroy_irq(&link->hpd_gpio);
1825                 link->hpd_gpio = NULL;
1826         }
1827
1828         DC_LOG_DC("BIOS object table - %s failed.\n", __func__);
1829         kfree(info);
1830
1831         return false;
1832 }
1833
1834 static bool dc_link_construct_dpia(struct dc_link *link,
1835                                    const struct link_init_data *init_params)
1836 {
1837         struct ddc_service_init_data ddc_service_init_data = { 0 };
1838         struct dc_context *dc_ctx = init_params->ctx;
1839
1840         DC_LOGGER_INIT(dc_ctx->logger);
1841
1842         /* Initialized irq source for hpd and hpd rx */
1843         link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1844         link->irq_source_hpd_rx = DC_IRQ_SOURCE_INVALID;
1845         link->link_status.dpcd_caps = &link->dpcd_caps;
1846
1847         link->dc = init_params->dc;
1848         link->ctx = dc_ctx;
1849         link->link_index = init_params->link_index;
1850
1851         memset(&link->preferred_training_settings, 0,
1852                sizeof(struct dc_link_training_overrides));
1853         memset(&link->preferred_link_setting, 0,
1854                sizeof(struct dc_link_settings));
1855
1856         /* Dummy Init for linkid */
1857         link->link_id.type = OBJECT_TYPE_CONNECTOR;
1858         link->link_id.id = CONNECTOR_ID_DISPLAY_PORT;
1859         link->link_id.enum_id = ENUM_ID_1 + init_params->connector_index;
1860         link->is_internal_display = false;
1861         link->connector_signal = SIGNAL_TYPE_DISPLAY_PORT;
1862         LINK_INFO("Connector[%d] description:signal %d\n",
1863                   init_params->connector_index,
1864                   link->connector_signal);
1865
1866         link->ep_type = DISPLAY_ENDPOINT_USB4_DPIA;
1867         link->is_dig_mapping_flexible = true;
1868
1869         /* TODO: Initialize link : funcs->link_init */
1870
1871         ddc_service_init_data.ctx = link->ctx;
1872         ddc_service_init_data.id = link->link_id;
1873         ddc_service_init_data.link = link;
1874         /* Set indicator for dpia link so that ddc won't be created */
1875         ddc_service_init_data.is_dpia_link = true;
1876
1877         link->ddc = dal_ddc_service_create(&ddc_service_init_data);
1878         if (!link->ddc) {
1879                 DC_ERROR("Failed to create ddc_service!\n");
1880                 goto ddc_create_fail;
1881         }
1882
1883         /* Set dpia port index : 0 to number of dpia ports */
1884         link->ddc_hw_inst = init_params->connector_index;
1885
1886         /* TODO: Create link encoder */
1887
1888         link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
1889
1890         /* Some docks seem to NAK I2C writes to segment pointer with mot=0. */
1891         link->wa_flags.dp_mot_reset_segment = true;
1892
1893         return true;
1894
1895 ddc_create_fail:
1896         return false;
1897 }
1898
1899 static bool dc_link_construct(struct dc_link *link,
1900                               const struct link_init_data *init_params)
1901 {
1902         /* Handle dpia case */
1903         if (init_params->is_dpia_link)
1904                 return dc_link_construct_dpia(link, init_params);
1905         else
1906                 return dc_link_construct_legacy(link, init_params);
1907 }
1908 /*******************************************************************************
1909  * Public functions
1910  ******************************************************************************/
1911 struct dc_link *link_create(const struct link_init_data *init_params)
1912 {
1913         struct dc_link *link =
1914                         kzalloc(sizeof(*link), GFP_KERNEL);
1915
1916         if (NULL == link)
1917                 goto alloc_fail;
1918
1919         if (false == dc_link_construct(link, init_params))
1920                 goto construct_fail;
1921
1922         /*
1923          * Must use preferred_link_setting, not reported_link_cap or verified_link_cap,
1924          * since struct preferred_link_setting won't be reset after S3.
1925          */
1926         link->preferred_link_setting.dpcd_source_device_specific_field_support = true;
1927
1928         return link;
1929
1930 construct_fail:
1931         kfree(link);
1932
1933 alloc_fail:
1934         return NULL;
1935 }
1936
1937 void link_destroy(struct dc_link **link)
1938 {
1939         dc_link_destruct(*link);
1940         kfree(*link);
1941         *link = NULL;
1942 }
1943
1944 static void enable_stream_features(struct pipe_ctx *pipe_ctx)
1945 {
1946         struct dc_stream_state *stream = pipe_ctx->stream;
1947
1948         if (pipe_ctx->stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST) {
1949                 struct dc_link *link = stream->link;
1950                 union down_spread_ctrl old_downspread;
1951                 union down_spread_ctrl new_downspread;
1952
1953                 memset(&old_downspread, 0, sizeof(old_downspread));
1954
1955                 core_link_read_dpcd(link, DP_DOWNSPREAD_CTRL,
1956                                 &old_downspread.raw, sizeof(old_downspread));
1957
1958                 new_downspread.raw = old_downspread.raw;
1959
1960                 new_downspread.bits.IGNORE_MSA_TIMING_PARAM =
1961                                 (stream->ignore_msa_timing_param) ? 1 : 0;
1962
1963                 if (new_downspread.raw != old_downspread.raw) {
1964                         core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
1965                                 &new_downspread.raw, sizeof(new_downspread));
1966                 }
1967
1968         } else {
1969                 dm_helpers_mst_enable_stream_features(stream);
1970         }
1971 }
1972
1973 static enum dc_status enable_link_dp(struct dc_state *state,
1974                                      struct pipe_ctx *pipe_ctx)
1975 {
1976         struct dc_stream_state *stream = pipe_ctx->stream;
1977         enum dc_status status;
1978         bool skip_video_pattern;
1979         struct dc_link *link = stream->link;
1980         const struct dc_link_settings *link_settings =
1981                         &pipe_ctx->link_config.dp_link_settings;
1982         bool fec_enable;
1983         int i;
1984         bool apply_seamless_boot_optimization = false;
1985         uint32_t bl_oled_enable_delay = 50; // in ms
1986         const uint32_t post_oui_delay = 30; // 30ms
1987         /* Reduce link bandwidth between failed link training attempts. */
1988         bool do_fallback = false;
1989
1990         // check for seamless boot
1991         for (i = 0; i < state->stream_count; i++) {
1992                 if (state->streams[i]->apply_seamless_boot_optimization) {
1993                         apply_seamless_boot_optimization = true;
1994                         break;
1995                 }
1996         }
1997
1998         /* Train with fallback when enabling DPIA link. Conventional links are
1999          * trained with fallback during sink detection.
2000          */
2001         if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
2002                 do_fallback = true;
2003
2004         /*
2005          * Temporary w/a to get DP2.0 link rates to work with SST.
2006          * TODO DP2.0 - Workaround: Remove w/a if and when the issue is resolved.
2007          */
2008         if (dp_get_link_encoding_format(link_settings) == DP_128b_132b_ENCODING &&
2009                         pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT &&
2010                         link->dc->debug.set_mst_en_for_sst) {
2011                 dp_enable_mst_on_sink(link, true);
2012         }
2013
2014         if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) {
2015                 /*in case it is not on*/
2016                 if (!link->dc->config.edp_no_power_sequencing)
2017                         link->dc->hwss.edp_power_control(link, true);
2018                 link->dc->hwss.edp_wait_for_hpd_ready(link, true);
2019         }
2020
2021         if (dp_get_link_encoding_format(link_settings) == DP_128b_132b_ENCODING) {
2022                 /* TODO - DP2.0 HW: calculate 32 symbol clock for HPO encoder */
2023         } else {
2024                 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk =
2025                                 link_settings->link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
2026                 if (state->clk_mgr && !apply_seamless_boot_optimization)
2027                         state->clk_mgr->funcs->update_clocks(state->clk_mgr,
2028                                         state, false);
2029         }
2030
2031         // during mode switch we do DP_SET_POWER off then on, and OUI is lost
2032         dpcd_set_source_specific_data(link);
2033         if (link->dpcd_sink_ext_caps.raw != 0)
2034                 msleep(post_oui_delay);
2035
2036         // similarly, mode switch can cause loss of cable ID
2037         dpcd_write_cable_id_to_dprx(link);
2038
2039         skip_video_pattern = true;
2040
2041         if (link_settings->link_rate == LINK_RATE_LOW)
2042                 skip_video_pattern = false;
2043
2044         if (perform_link_training_with_retries(link_settings,
2045                                                skip_video_pattern,
2046                                                LINK_TRAINING_ATTEMPTS,
2047                                                pipe_ctx,
2048                                                pipe_ctx->stream->signal,
2049                                                do_fallback)) {
2050                 status = DC_OK;
2051         } else {
2052                 status = DC_FAIL_DP_LINK_TRAINING;
2053         }
2054
2055         if (link->preferred_training_settings.fec_enable)
2056                 fec_enable = *link->preferred_training_settings.fec_enable;
2057         else
2058                 fec_enable = true;
2059
2060         if (dp_get_link_encoding_format(link_settings) == DP_8b_10b_ENCODING)
2061                 dp_set_fec_enable(link, fec_enable);
2062
2063         // during mode set we do DP_SET_POWER off then on, aux writes are lost
2064         if (link->dpcd_sink_ext_caps.bits.oled == 1 ||
2065                 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1 ||
2066                 link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1) {
2067                 dc_link_set_default_brightness_aux(link); // TODO: use cached if known
2068                 if (link->dpcd_sink_ext_caps.bits.oled == 1)
2069                         msleep(bl_oled_enable_delay);
2070                 dc_link_backlight_enable_aux(link, true);
2071         }
2072
2073         return status;
2074 }
2075
2076 static enum dc_status enable_link_edp(
2077                 struct dc_state *state,
2078                 struct pipe_ctx *pipe_ctx)
2079 {
2080         return enable_link_dp(state, pipe_ctx);
2081 }
2082
2083 static enum dc_status enable_link_dp_mst(
2084                 struct dc_state *state,
2085                 struct pipe_ctx *pipe_ctx)
2086 {
2087         struct dc_link *link = pipe_ctx->stream->link;
2088
2089         /* sink signal type after MST branch is MST. Multiple MST sinks
2090          * share one link. Link DP PHY is enable or training only once.
2091          */
2092         if (link->link_status.link_active)
2093                 return DC_OK;
2094
2095         /* clear payload table */
2096         dm_helpers_dp_mst_clear_payload_allocation_table(link->ctx, link);
2097
2098         /* to make sure the pending down rep can be processed
2099          * before enabling the link
2100          */
2101         dm_helpers_dp_mst_poll_pending_down_reply(link->ctx, link);
2102
2103         /* set the sink to MST mode before enabling the link */
2104         dp_enable_mst_on_sink(link, true);
2105
2106         return enable_link_dp(state, pipe_ctx);
2107 }
2108
2109 void dc_link_blank_all_dp_displays(struct dc *dc)
2110 {
2111         unsigned int i;
2112         uint8_t dpcd_power_state = '\0';
2113         enum dc_status status = DC_ERROR_UNEXPECTED;
2114
2115         for (i = 0; i < dc->link_count; i++) {
2116                 if ((dc->links[i]->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) ||
2117                         (dc->links[i]->priv == NULL) || (dc->links[i]->local_sink == NULL))
2118                         continue;
2119
2120                 /* DP 2.0 spec requires that we read LTTPR caps first */
2121                 dp_retrieve_lttpr_cap(dc->links[i]);
2122                 /* if any of the displays are lit up turn them off */
2123                 status = core_link_read_dpcd(dc->links[i], DP_SET_POWER,
2124                                                         &dpcd_power_state, sizeof(dpcd_power_state));
2125
2126                 if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0)
2127                         dc_link_blank_dp_stream(dc->links[i], true);
2128         }
2129
2130 }
2131
2132 void dc_link_blank_all_edp_displays(struct dc *dc)
2133 {
2134         unsigned int i;
2135         uint8_t dpcd_power_state = '\0';
2136         enum dc_status status = DC_ERROR_UNEXPECTED;
2137
2138         for (i = 0; i < dc->link_count; i++) {
2139                 if ((dc->links[i]->connector_signal != SIGNAL_TYPE_EDP) ||
2140                         (!dc->links[i]->edp_sink_present))
2141                         continue;
2142
2143                 /* if any of the displays are lit up turn them off */
2144                 status = core_link_read_dpcd(dc->links[i], DP_SET_POWER,
2145                                                         &dpcd_power_state, sizeof(dpcd_power_state));
2146
2147                 if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0)
2148                         dc_link_blank_dp_stream(dc->links[i], true);
2149         }
2150 }
2151
2152 void dc_link_blank_dp_stream(struct dc_link *link, bool hw_init)
2153 {
2154         unsigned int j;
2155         struct dc  *dc = link->ctx->dc;
2156         enum signal_type signal = link->connector_signal;
2157
2158         if ((signal == SIGNAL_TYPE_EDP) ||
2159                 (signal == SIGNAL_TYPE_DISPLAY_PORT)) {
2160                 if (link->ep_type == DISPLAY_ENDPOINT_PHY &&
2161                         link->link_enc->funcs->get_dig_frontend &&
2162                         link->link_enc->funcs->is_dig_enabled(link->link_enc)) {
2163                         unsigned int fe = link->link_enc->funcs->get_dig_frontend(link->link_enc);
2164
2165                         if (fe != ENGINE_ID_UNKNOWN)
2166                                 for (j = 0; j < dc->res_pool->stream_enc_count; j++) {
2167                                         if (fe == dc->res_pool->stream_enc[j]->id) {
2168                                                 dc->res_pool->stream_enc[j]->funcs->dp_blank(link,
2169                                                                         dc->res_pool->stream_enc[j]);
2170                                                 break;
2171                                         }
2172                                 }
2173                 }
2174
2175                 if ((!link->wa_flags.dp_keep_receiver_powered) || hw_init)
2176                         dp_receiver_power_ctrl(link, false);
2177         }
2178 }
2179
2180 static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx,
2181                 enum engine_id eng_id,
2182                 struct ext_hdmi_settings *settings)
2183 {
2184         bool result = false;
2185         int i = 0;
2186         struct integrated_info *integrated_info =
2187                         pipe_ctx->stream->ctx->dc_bios->integrated_info;
2188
2189         if (integrated_info == NULL)
2190                 return false;
2191
2192         /*
2193          * Get retimer settings from sbios for passing SI eye test for DCE11
2194          * The setting values are varied based on board revision and port id
2195          * Therefore the setting values of each ports is passed by sbios.
2196          */
2197
2198         // Check if current bios contains ext Hdmi settings
2199         if (integrated_info->gpu_cap_info & 0x20) {
2200                 switch (eng_id) {
2201                 case ENGINE_ID_DIGA:
2202                         settings->slv_addr = integrated_info->dp0_ext_hdmi_slv_addr;
2203                         settings->reg_num = integrated_info->dp0_ext_hdmi_6g_reg_num;
2204                         settings->reg_num_6g = integrated_info->dp0_ext_hdmi_6g_reg_num;
2205                         memmove(settings->reg_settings,
2206                                         integrated_info->dp0_ext_hdmi_reg_settings,
2207                                         sizeof(integrated_info->dp0_ext_hdmi_reg_settings));
2208                         memmove(settings->reg_settings_6g,
2209                                         integrated_info->dp0_ext_hdmi_6g_reg_settings,
2210                                         sizeof(integrated_info->dp0_ext_hdmi_6g_reg_settings));
2211                         result = true;
2212                         break;
2213                 case ENGINE_ID_DIGB:
2214                         settings->slv_addr = integrated_info->dp1_ext_hdmi_slv_addr;
2215                         settings->reg_num = integrated_info->dp1_ext_hdmi_6g_reg_num;
2216                         settings->reg_num_6g = integrated_info->dp1_ext_hdmi_6g_reg_num;
2217                         memmove(settings->reg_settings,
2218                                         integrated_info->dp1_ext_hdmi_reg_settings,
2219                                         sizeof(integrated_info->dp1_ext_hdmi_reg_settings));
2220                         memmove(settings->reg_settings_6g,
2221                                         integrated_info->dp1_ext_hdmi_6g_reg_settings,
2222                                         sizeof(integrated_info->dp1_ext_hdmi_6g_reg_settings));
2223                         result = true;
2224                         break;
2225                 case ENGINE_ID_DIGC:
2226                         settings->slv_addr = integrated_info->dp2_ext_hdmi_slv_addr;
2227                         settings->reg_num = integrated_info->dp2_ext_hdmi_6g_reg_num;
2228                         settings->reg_num_6g = integrated_info->dp2_ext_hdmi_6g_reg_num;
2229                         memmove(settings->reg_settings,
2230                                         integrated_info->dp2_ext_hdmi_reg_settings,
2231                                         sizeof(integrated_info->dp2_ext_hdmi_reg_settings));
2232                         memmove(settings->reg_settings_6g,
2233                                         integrated_info->dp2_ext_hdmi_6g_reg_settings,
2234                                         sizeof(integrated_info->dp2_ext_hdmi_6g_reg_settings));
2235                         result = true;
2236                         break;
2237                 case ENGINE_ID_DIGD:
2238                         settings->slv_addr = integrated_info->dp3_ext_hdmi_slv_addr;
2239                         settings->reg_num = integrated_info->dp3_ext_hdmi_6g_reg_num;
2240                         settings->reg_num_6g = integrated_info->dp3_ext_hdmi_6g_reg_num;
2241                         memmove(settings->reg_settings,
2242                                         integrated_info->dp3_ext_hdmi_reg_settings,
2243                                         sizeof(integrated_info->dp3_ext_hdmi_reg_settings));
2244                         memmove(settings->reg_settings_6g,
2245                                         integrated_info->dp3_ext_hdmi_6g_reg_settings,
2246                                         sizeof(integrated_info->dp3_ext_hdmi_6g_reg_settings));
2247                         result = true;
2248                         break;
2249                 default:
2250                         break;
2251                 }
2252
2253                 if (result == true) {
2254                         // Validate settings from bios integrated info table
2255                         if (settings->slv_addr == 0)
2256                                 return false;
2257                         if (settings->reg_num > 9)
2258                                 return false;
2259                         if (settings->reg_num_6g > 3)
2260                                 return false;
2261
2262                         for (i = 0; i < settings->reg_num; i++) {
2263                                 if (settings->reg_settings[i].i2c_reg_index > 0x20)
2264                                         return false;
2265                         }
2266
2267                         for (i = 0; i < settings->reg_num_6g; i++) {
2268                                 if (settings->reg_settings_6g[i].i2c_reg_index > 0x20)
2269                                         return false;
2270                         }
2271                 }
2272         }
2273
2274         return result;
2275 }
2276
2277 static bool i2c_write(struct pipe_ctx *pipe_ctx,
2278                 uint8_t address, uint8_t *buffer, uint32_t length)
2279 {
2280         struct i2c_command cmd = {0};
2281         struct i2c_payload payload = {0};
2282
2283         memset(&payload, 0, sizeof(payload));
2284         memset(&cmd, 0, sizeof(cmd));
2285
2286         cmd.number_of_payloads = 1;
2287         cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
2288         cmd.speed = pipe_ctx->stream->ctx->dc->caps.i2c_speed_in_khz;
2289
2290         payload.address = address;
2291         payload.data = buffer;
2292         payload.length = length;
2293         payload.write = true;
2294         cmd.payloads = &payload;
2295
2296         if (dm_helpers_submit_i2c(pipe_ctx->stream->ctx,
2297                         pipe_ctx->stream->link, &cmd))
2298                 return true;
2299
2300         return false;
2301 }
2302
2303 static void write_i2c_retimer_setting(
2304                 struct pipe_ctx *pipe_ctx,
2305                 bool is_vga_mode,
2306                 bool is_over_340mhz,
2307                 struct ext_hdmi_settings *settings)
2308 {
2309         uint8_t slave_address = (settings->slv_addr >> 1);
2310         uint8_t buffer[2];
2311         const uint8_t apply_rx_tx_change = 0x4;
2312         uint8_t offset = 0xA;
2313         uint8_t value = 0;
2314         int i = 0;
2315         bool i2c_success = false;
2316         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
2317
2318         memset(&buffer, 0, sizeof(buffer));
2319
2320         /* Start Ext-Hdmi programming*/
2321
2322         for (i = 0; i < settings->reg_num; i++) {
2323                 /* Apply 3G settings */
2324                 if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
2325
2326                         buffer[0] = settings->reg_settings[i].i2c_reg_index;
2327                         buffer[1] = settings->reg_settings[i].i2c_reg_val;
2328                         i2c_success = i2c_write(pipe_ctx, slave_address,
2329                                                 buffer, sizeof(buffer));
2330                         RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2331                                 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
2332                                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2333
2334                         if (!i2c_success)
2335                                 goto i2c_write_fail;
2336
2337                         /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
2338                          * needs to be set to 1 on every 0xA-0xC write.
2339                          */
2340                         if (settings->reg_settings[i].i2c_reg_index == 0xA ||
2341                                 settings->reg_settings[i].i2c_reg_index == 0xB ||
2342                                 settings->reg_settings[i].i2c_reg_index == 0xC) {
2343
2344                                 /* Query current value from offset 0xA */
2345                                 if (settings->reg_settings[i].i2c_reg_index == 0xA)
2346                                         value = settings->reg_settings[i].i2c_reg_val;
2347                                 else {
2348                                         i2c_success =
2349                                                 dal_ddc_service_query_ddc_data(
2350                                                 pipe_ctx->stream->link->ddc,
2351                                                 slave_address, &offset, 1, &value, 1);
2352                                         if (!i2c_success)
2353                                                 goto i2c_write_fail;
2354                                 }
2355
2356                                 buffer[0] = offset;
2357                                 /* Set APPLY_RX_TX_CHANGE bit to 1 */
2358                                 buffer[1] = value | apply_rx_tx_change;
2359                                 i2c_success = i2c_write(pipe_ctx, slave_address,
2360                                                 buffer, sizeof(buffer));
2361                                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2362                                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2363                                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2364                                 if (!i2c_success)
2365                                         goto i2c_write_fail;
2366                         }
2367                 }
2368         }
2369
2370         /* Apply 3G settings */
2371         if (is_over_340mhz) {
2372                 for (i = 0; i < settings->reg_num_6g; i++) {
2373                         /* Apply 3G settings */
2374                         if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
2375
2376                                 buffer[0] = settings->reg_settings_6g[i].i2c_reg_index;
2377                                 buffer[1] = settings->reg_settings_6g[i].i2c_reg_val;
2378                                 i2c_success = i2c_write(pipe_ctx, slave_address,
2379                                                         buffer, sizeof(buffer));
2380                                 RETIMER_REDRIVER_INFO("above 340Mhz: retimer write to slave_address = 0x%x,\
2381                                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2382                                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2383
2384                                 if (!i2c_success)
2385                                         goto i2c_write_fail;
2386
2387                                 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
2388                                  * needs to be set to 1 on every 0xA-0xC write.
2389                                  */
2390                                 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA ||
2391                                         settings->reg_settings_6g[i].i2c_reg_index == 0xB ||
2392                                         settings->reg_settings_6g[i].i2c_reg_index == 0xC) {
2393
2394                                         /* Query current value from offset 0xA */
2395                                         if (settings->reg_settings_6g[i].i2c_reg_index == 0xA)
2396                                                 value = settings->reg_settings_6g[i].i2c_reg_val;
2397                                         else {
2398                                                 i2c_success =
2399                                                                 dal_ddc_service_query_ddc_data(
2400                                                                 pipe_ctx->stream->link->ddc,
2401                                                                 slave_address, &offset, 1, &value, 1);
2402                                                 if (!i2c_success)
2403                                                         goto i2c_write_fail;
2404                                         }
2405
2406                                         buffer[0] = offset;
2407                                         /* Set APPLY_RX_TX_CHANGE bit to 1 */
2408                                         buffer[1] = value | apply_rx_tx_change;
2409                                         i2c_success = i2c_write(pipe_ctx, slave_address,
2410                                                         buffer, sizeof(buffer));
2411                                         RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2412                                                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2413                                                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2414                                         if (!i2c_success)
2415                                                 goto i2c_write_fail;
2416                                 }
2417                         }
2418                 }
2419         }
2420
2421         if (is_vga_mode) {
2422                 /* Program additional settings if using 640x480 resolution */
2423
2424                 /* Write offset 0xFF to 0x01 */
2425                 buffer[0] = 0xff;
2426                 buffer[1] = 0x01;
2427                 i2c_success = i2c_write(pipe_ctx, slave_address,
2428                                 buffer, sizeof(buffer));
2429                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2430                                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2431                                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2432                 if (!i2c_success)
2433                         goto i2c_write_fail;
2434
2435                 /* Write offset 0x00 to 0x23 */
2436                 buffer[0] = 0x00;
2437                 buffer[1] = 0x23;
2438                 i2c_success = i2c_write(pipe_ctx, slave_address,
2439                                 buffer, sizeof(buffer));
2440                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2441                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2442                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2443                 if (!i2c_success)
2444                         goto i2c_write_fail;
2445
2446                 /* Write offset 0xff to 0x00 */
2447                 buffer[0] = 0xff;
2448                 buffer[1] = 0x00;
2449                 i2c_success = i2c_write(pipe_ctx, slave_address,
2450                                 buffer, sizeof(buffer));
2451                 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2452                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2453                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2454                 if (!i2c_success)
2455                         goto i2c_write_fail;
2456
2457         }
2458
2459         return;
2460
2461 i2c_write_fail:
2462         DC_LOG_DEBUG("Set retimer failed");
2463 }
2464
2465 static void write_i2c_default_retimer_setting(
2466                 struct pipe_ctx *pipe_ctx,
2467                 bool is_vga_mode,
2468                 bool is_over_340mhz)
2469 {
2470         uint8_t slave_address = (0xBA >> 1);
2471         uint8_t buffer[2];
2472         bool i2c_success = false;
2473         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
2474
2475         memset(&buffer, 0, sizeof(buffer));
2476
2477         /* Program Slave Address for tuning single integrity */
2478         /* Write offset 0x0A to 0x13 */
2479         buffer[0] = 0x0A;
2480         buffer[1] = 0x13;
2481         i2c_success = i2c_write(pipe_ctx, slave_address,
2482                         buffer, sizeof(buffer));
2483         RETIMER_REDRIVER_INFO("retimer writes default setting to slave_address = 0x%x,\
2484                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2485                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2486         if (!i2c_success)
2487                 goto i2c_write_fail;
2488
2489         /* Write offset 0x0A to 0x17 */
2490         buffer[0] = 0x0A;
2491         buffer[1] = 0x17;
2492         i2c_success = i2c_write(pipe_ctx, slave_address,
2493                         buffer, sizeof(buffer));
2494         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2495                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2496                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2497         if (!i2c_success)
2498                 goto i2c_write_fail;
2499
2500         /* Write offset 0x0B to 0xDA or 0xD8 */
2501         buffer[0] = 0x0B;
2502         buffer[1] = is_over_340mhz ? 0xDA : 0xD8;
2503         i2c_success = i2c_write(pipe_ctx, slave_address,
2504                         buffer, sizeof(buffer));
2505         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2506                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2507                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2508         if (!i2c_success)
2509                 goto i2c_write_fail;
2510
2511         /* Write offset 0x0A to 0x17 */
2512         buffer[0] = 0x0A;
2513         buffer[1] = 0x17;
2514         i2c_success = i2c_write(pipe_ctx, slave_address,
2515                         buffer, sizeof(buffer));
2516         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2517                 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
2518                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2519         if (!i2c_success)
2520                 goto i2c_write_fail;
2521
2522         /* Write offset 0x0C to 0x1D or 0x91 */
2523         buffer[0] = 0x0C;
2524         buffer[1] = is_over_340mhz ? 0x1D : 0x91;
2525         i2c_success = i2c_write(pipe_ctx, slave_address,
2526                         buffer, sizeof(buffer));
2527         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2528                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2529                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2530         if (!i2c_success)
2531                 goto i2c_write_fail;
2532
2533         /* Write offset 0x0A to 0x17 */
2534         buffer[0] = 0x0A;
2535         buffer[1] = 0x17;
2536         i2c_success = i2c_write(pipe_ctx, slave_address,
2537                         buffer, sizeof(buffer));
2538         RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2539                 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2540                 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2541         if (!i2c_success)
2542                 goto i2c_write_fail;
2543
2544
2545         if (is_vga_mode) {
2546                 /* Program additional settings if using 640x480 resolution */
2547
2548                 /* Write offset 0xFF to 0x01 */
2549                 buffer[0] = 0xff;
2550                 buffer[1] = 0x01;
2551                 i2c_success = i2c_write(pipe_ctx, slave_address,
2552                                 buffer, sizeof(buffer));
2553                 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2554                         offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2555                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2556                 if (!i2c_success)
2557                         goto i2c_write_fail;
2558
2559                 /* Write offset 0x00 to 0x23 */
2560                 buffer[0] = 0x00;
2561                 buffer[1] = 0x23;
2562                 i2c_success = i2c_write(pipe_ctx, slave_address,
2563                                 buffer, sizeof(buffer));
2564                 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2565                         offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
2566                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2567                 if (!i2c_success)
2568                         goto i2c_write_fail;
2569
2570                 /* Write offset 0xff to 0x00 */
2571                 buffer[0] = 0xff;
2572                 buffer[1] = 0x00;
2573                 i2c_success = i2c_write(pipe_ctx, slave_address,
2574                                 buffer, sizeof(buffer));
2575                 RETIMER_REDRIVER_INFO("retimer write default setting to slave_addr = 0x%x,\
2576                         offset = 0x%x, reg_val= 0x%x, i2c_success = %d end here\n",
2577                         slave_address, buffer[0], buffer[1], i2c_success?1:0);
2578                 if (!i2c_success)
2579                         goto i2c_write_fail;
2580         }
2581
2582         return;
2583
2584 i2c_write_fail:
2585         DC_LOG_DEBUG("Set default retimer failed");
2586 }
2587
2588 static void write_i2c_redriver_setting(
2589                 struct pipe_ctx *pipe_ctx,
2590                 bool is_over_340mhz)
2591 {
2592         uint8_t slave_address = (0xF0 >> 1);
2593         uint8_t buffer[16];
2594         bool i2c_success = false;
2595         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
2596
2597         memset(&buffer, 0, sizeof(buffer));
2598
2599         // Program Slave Address for tuning single integrity
2600         buffer[3] = 0x4E;
2601         buffer[4] = 0x4E;
2602         buffer[5] = 0x4E;
2603         buffer[6] = is_over_340mhz ? 0x4E : 0x4A;
2604
2605         i2c_success = i2c_write(pipe_ctx, slave_address,
2606                                         buffer, sizeof(buffer));
2607         RETIMER_REDRIVER_INFO("redriver write 0 to all 16 reg offset expect following:\n\
2608                 \t slave_addr = 0x%x, offset[3] = 0x%x, offset[4] = 0x%x,\
2609                 offset[5] = 0x%x,offset[6] is_over_340mhz = 0x%x,\
2610                 i2c_success = %d\n",
2611                 slave_address, buffer[3], buffer[4], buffer[5], buffer[6], i2c_success?1:0);
2612
2613         if (!i2c_success)
2614                 DC_LOG_DEBUG("Set redriver failed");
2615 }
2616
2617 static void disable_link(struct dc_link *link, const struct link_resource *link_res,
2618                 enum signal_type signal)
2619 {
2620         /*
2621          * TODO: implement call for dp_set_hw_test_pattern
2622          * it is needed for compliance testing
2623          */
2624
2625         /* Here we need to specify that encoder output settings
2626          * need to be calculated as for the set mode,
2627          * it will lead to querying dynamic link capabilities
2628          * which should be done before enable output
2629          */
2630
2631         if (dc_is_dp_signal(signal)) {
2632                 /* SST DP, eDP */
2633                 struct dc_link_settings link_settings = link->cur_link_settings;
2634                 if (dc_is_dp_sst_signal(signal))
2635                         dp_disable_link_phy(link, link_res, signal);
2636                 else
2637                         dp_disable_link_phy_mst(link, link_res, signal);
2638
2639                 if (dc_is_dp_sst_signal(signal) ||
2640                                 link->mst_stream_alloc_table.stream_count == 0) {
2641                         if (dp_get_link_encoding_format(&link_settings) == DP_8b_10b_ENCODING) {
2642                                 dp_set_fec_enable(link, false);
2643                                 dp_set_fec_ready(link, link_res, false);
2644                         }
2645                 }
2646         } else {
2647                 if (signal != SIGNAL_TYPE_VIRTUAL)
2648                         link->link_enc->funcs->disable_output(link->link_enc, signal);
2649         }
2650
2651         if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
2652                 /* MST disable link only when no stream use the link */
2653                 if (link->mst_stream_alloc_table.stream_count <= 0)
2654                         link->link_status.link_active = false;
2655         } else {
2656                 link->link_status.link_active = false;
2657         }
2658 }
2659
2660 static void enable_link_hdmi(struct pipe_ctx *pipe_ctx)
2661 {
2662         struct dc_stream_state *stream = pipe_ctx->stream;
2663         struct dc_link *link = stream->link;
2664         enum dc_color_depth display_color_depth;
2665         enum engine_id eng_id;
2666         struct ext_hdmi_settings settings = {0};
2667         bool is_over_340mhz = false;
2668         bool is_vga_mode = (stream->timing.h_addressable == 640)
2669                         && (stream->timing.v_addressable == 480);
2670
2671         if (stream->phy_pix_clk == 0)
2672                 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10;
2673         if (stream->phy_pix_clk > 340000)
2674                 is_over_340mhz = true;
2675
2676         if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
2677                 unsigned short masked_chip_caps = pipe_ctx->stream->link->chip_caps &
2678                                 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
2679                 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {
2680                         /* DP159, Retimer settings */
2681                         eng_id = pipe_ctx->stream_res.stream_enc->id;
2682
2683                         if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) {
2684                                 write_i2c_retimer_setting(pipe_ctx,
2685                                                 is_vga_mode, is_over_340mhz, &settings);
2686                         } else {
2687                                 write_i2c_default_retimer_setting(pipe_ctx,
2688                                                 is_vga_mode, is_over_340mhz);
2689                         }
2690                 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {
2691                         /* PI3EQX1204, Redriver settings */
2692                         write_i2c_redriver_setting(pipe_ctx, is_over_340mhz);
2693                 }
2694         }
2695
2696         if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
2697                 dal_ddc_service_write_scdc_data(
2698                         stream->link->ddc,
2699                         stream->phy_pix_clk,
2700                         stream->timing.flags.LTE_340MCSC_SCRAMBLE);
2701
2702         memset(&stream->link->cur_link_settings, 0,
2703                         sizeof(struct dc_link_settings));
2704
2705         display_color_depth = stream->timing.display_color_depth;
2706         if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
2707                 display_color_depth = COLOR_DEPTH_888;
2708
2709         link->link_enc->funcs->enable_tmds_output(
2710                         link->link_enc,
2711                         pipe_ctx->clock_source->id,
2712                         display_color_depth,
2713                         pipe_ctx->stream->signal,
2714                         stream->phy_pix_clk);
2715
2716         if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
2717                 dal_ddc_service_read_scdc_data(link->ddc);
2718 }
2719
2720 static void enable_link_lvds(struct pipe_ctx *pipe_ctx)
2721 {
2722         struct dc_stream_state *stream = pipe_ctx->stream;
2723         struct dc_link *link = stream->link;
2724
2725         if (stream->phy_pix_clk == 0)
2726                 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10;
2727
2728         memset(&stream->link->cur_link_settings, 0,
2729                         sizeof(struct dc_link_settings));
2730
2731         link->link_enc->funcs->enable_lvds_output(
2732                         link->link_enc,
2733                         pipe_ctx->clock_source->id,
2734                         stream->phy_pix_clk);
2735
2736 }
2737
2738 bool dc_power_alpm_dpcd_enable(struct dc_link *link, bool enable)
2739 {
2740         bool ret = false;
2741         union dpcd_alpm_configuration alpm_config;
2742
2743         if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) {
2744                 memset(&alpm_config, 0, sizeof(alpm_config));
2745
2746                 alpm_config.bits.ENABLE = (enable ? true : false);
2747                 ret = dm_helpers_dp_write_dpcd(link->ctx, link,
2748                                 DP_RECEIVER_ALPM_CONFIG, &alpm_config.raw,
2749                                 sizeof(alpm_config.raw));
2750         }
2751         return ret;
2752 }
2753
2754 /****************************enable_link***********************************/
2755 static enum dc_status enable_link(
2756                 struct dc_state *state,
2757                 struct pipe_ctx *pipe_ctx)
2758 {
2759         enum dc_status status = DC_ERROR_UNEXPECTED;
2760         struct dc_stream_state *stream = pipe_ctx->stream;
2761         struct dc_link *link = stream->link;
2762
2763         /* There's some scenarios where driver is unloaded with display
2764          * still enabled. When driver is reloaded, it may cause a display
2765          * to not light up if there is a mismatch between old and new
2766          * link settings. Need to call disable first before enabling at
2767          * new link settings.
2768          */
2769         if (link->link_status.link_active) {
2770                 disable_link(link, &pipe_ctx->link_res, pipe_ctx->stream->signal);
2771         }
2772
2773         switch (pipe_ctx->stream->signal) {
2774         case SIGNAL_TYPE_DISPLAY_PORT:
2775                 status = enable_link_dp(state, pipe_ctx);
2776                 break;
2777         case SIGNAL_TYPE_EDP:
2778                 status = enable_link_edp(state, pipe_ctx);
2779                 break;
2780         case SIGNAL_TYPE_DISPLAY_PORT_MST:
2781                 status = enable_link_dp_mst(state, pipe_ctx);
2782                 msleep(200);
2783                 break;
2784         case SIGNAL_TYPE_DVI_SINGLE_LINK:
2785         case SIGNAL_TYPE_DVI_DUAL_LINK:
2786         case SIGNAL_TYPE_HDMI_TYPE_A:
2787                 enable_link_hdmi(pipe_ctx);
2788                 status = DC_OK;
2789                 break;
2790         case SIGNAL_TYPE_LVDS:
2791                 enable_link_lvds(pipe_ctx);
2792                 status = DC_OK;
2793                 break;
2794         case SIGNAL_TYPE_VIRTUAL:
2795                 status = DC_OK;
2796                 break;
2797         default:
2798                 break;
2799         }
2800
2801         if (status == DC_OK)
2802                 pipe_ctx->stream->link->link_status.link_active = true;
2803
2804         return status;
2805 }
2806
2807 static uint32_t get_timing_pixel_clock_100hz(const struct dc_crtc_timing *timing)
2808 {
2809
2810         uint32_t pxl_clk = timing->pix_clk_100hz;
2811
2812         if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
2813                 pxl_clk /= 2;
2814         else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
2815                 pxl_clk = pxl_clk * 2 / 3;
2816
2817         if (timing->display_color_depth == COLOR_DEPTH_101010)
2818                 pxl_clk = pxl_clk * 10 / 8;
2819         else if (timing->display_color_depth == COLOR_DEPTH_121212)
2820                 pxl_clk = pxl_clk * 12 / 8;
2821
2822         return pxl_clk;
2823 }
2824
2825 static bool dp_active_dongle_validate_timing(
2826                 const struct dc_crtc_timing *timing,
2827                 const struct dpcd_caps *dpcd_caps)
2828 {
2829         const struct dc_dongle_caps *dongle_caps = &dpcd_caps->dongle_caps;
2830
2831         switch (dpcd_caps->dongle_type) {
2832         case DISPLAY_DONGLE_DP_VGA_CONVERTER:
2833         case DISPLAY_DONGLE_DP_DVI_CONVERTER:
2834         case DISPLAY_DONGLE_DP_DVI_DONGLE:
2835                 if (timing->pixel_encoding == PIXEL_ENCODING_RGB)
2836                         return true;
2837                 else
2838                         return false;
2839         default:
2840                 break;
2841         }
2842
2843         if (dpcd_caps->dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER &&
2844                         dongle_caps->extendedCapValid == true) {
2845                 /* Check Pixel Encoding */
2846                 switch (timing->pixel_encoding) {
2847                 case PIXEL_ENCODING_RGB:
2848                 case PIXEL_ENCODING_YCBCR444:
2849                         break;
2850                 case PIXEL_ENCODING_YCBCR422:
2851                         if (!dongle_caps->is_dp_hdmi_ycbcr422_pass_through)
2852                                 return false;
2853                         break;
2854                 case PIXEL_ENCODING_YCBCR420:
2855                         if (!dongle_caps->is_dp_hdmi_ycbcr420_pass_through)
2856                                 return false;
2857                         break;
2858                 default:
2859                         /* Invalid Pixel Encoding*/
2860                         return false;
2861                 }
2862
2863                 switch (timing->display_color_depth) {
2864                 case COLOR_DEPTH_666:
2865                 case COLOR_DEPTH_888:
2866                         /*888 and 666 should always be supported*/
2867                         break;
2868                 case COLOR_DEPTH_101010:
2869                         if (dongle_caps->dp_hdmi_max_bpc < 10)
2870                                 return false;
2871                         break;
2872                 case COLOR_DEPTH_121212:
2873                         if (dongle_caps->dp_hdmi_max_bpc < 12)
2874                                 return false;
2875                         break;
2876                 case COLOR_DEPTH_141414:
2877                 case COLOR_DEPTH_161616:
2878                 default:
2879                         /* These color depths are currently not supported */
2880                         return false;
2881                 }
2882
2883                 /* Check 3D format */
2884                 switch (timing->timing_3d_format) {
2885                 case TIMING_3D_FORMAT_NONE:
2886                 case TIMING_3D_FORMAT_FRAME_ALTERNATE:
2887                         /*Only frame alternate 3D is supported on active dongle*/
2888                         break;
2889                 default:
2890                         /*other 3D formats are not supported due to bad infoframe translation */
2891                         return false;
2892                 }
2893
2894 #if defined(CONFIG_DRM_AMD_DC_DCN)
2895                 if (dongle_caps->dp_hdmi_frl_max_link_bw_in_kbps > 0) { // DP to HDMI FRL converter
2896                         struct dc_crtc_timing outputTiming = *timing;
2897
2898                         if (timing->flags.DSC && !timing->dsc_cfg.is_frl)
2899                                 /* DP input has DSC, HDMI FRL output doesn't have DSC, remove DSC from output timing */
2900                                 outputTiming.flags.DSC = 0;
2901                         if (dc_bandwidth_in_kbps_from_timing(&outputTiming) > dongle_caps->dp_hdmi_frl_max_link_bw_in_kbps)
2902                                 return false;
2903                 } else { // DP to HDMI TMDS converter
2904                         if (get_timing_pixel_clock_100hz(timing) > (dongle_caps->dp_hdmi_max_pixel_clk_in_khz * 10))
2905                                 return false;
2906                 }
2907 #else
2908                 if (get_timing_pixel_clock_100hz(timing) > (dongle_caps->dp_hdmi_max_pixel_clk_in_khz * 10))
2909                         return false;
2910 #endif
2911         }
2912
2913         if (dpcd_caps->channel_coding_cap.bits.DP_128b_132b_SUPPORTED == 0 &&
2914                         dpcd_caps->dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_PASSTHROUGH_SUPPORT == 0 &&
2915                         dongle_caps->dfp_cap_ext.supported) {
2916
2917                 if (dongle_caps->dfp_cap_ext.max_pixel_rate_in_mps < (timing->pix_clk_100hz / 10000))
2918                         return false;
2919
2920                 if (dongle_caps->dfp_cap_ext.max_video_h_active_width < timing->h_addressable)
2921                         return false;
2922
2923                 if (dongle_caps->dfp_cap_ext.max_video_v_active_height < timing->v_addressable)
2924                         return false;
2925
2926                 if (timing->pixel_encoding == PIXEL_ENCODING_RGB) {
2927                         if (!dongle_caps->dfp_cap_ext.encoding_format_caps.support_rgb)
2928                                 return false;
2929                         if (timing->display_color_depth == COLOR_DEPTH_666 &&
2930                                         !dongle_caps->dfp_cap_ext.rgb_color_depth_caps.support_6bpc)
2931                                 return false;
2932                         else if (timing->display_color_depth == COLOR_DEPTH_888 &&
2933                                         !dongle_caps->dfp_cap_ext.rgb_color_depth_caps.support_8bpc)
2934                                 return false;
2935                         else if (timing->display_color_depth == COLOR_DEPTH_101010 &&
2936                                         !dongle_caps->dfp_cap_ext.rgb_color_depth_caps.support_10bpc)
2937                                 return false;
2938                         else if (timing->display_color_depth == COLOR_DEPTH_121212 &&
2939                                         !dongle_caps->dfp_cap_ext.rgb_color_depth_caps.support_12bpc)
2940                                 return false;
2941                         else if (timing->display_color_depth == COLOR_DEPTH_161616 &&
2942                                         !dongle_caps->dfp_cap_ext.rgb_color_depth_caps.support_16bpc)
2943                                 return false;
2944                 } else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR444) {
2945                         if (!dongle_caps->dfp_cap_ext.encoding_format_caps.support_rgb)
2946                                 return false;
2947                         if (timing->display_color_depth == COLOR_DEPTH_888 &&
2948                                         !dongle_caps->dfp_cap_ext.ycbcr444_color_depth_caps.support_8bpc)
2949                                 return false;
2950                         else if (timing->display_color_depth == COLOR_DEPTH_101010 &&
2951                                         !dongle_caps->dfp_cap_ext.ycbcr444_color_depth_caps.support_10bpc)
2952                                 return false;
2953                         else if (timing->display_color_depth == COLOR_DEPTH_121212 &&
2954                                         !dongle_caps->dfp_cap_ext.ycbcr444_color_depth_caps.support_12bpc)
2955                                 return false;
2956                         else if (timing->display_color_depth == COLOR_DEPTH_161616 &&
2957                                         !dongle_caps->dfp_cap_ext.ycbcr444_color_depth_caps.support_16bpc)
2958                                 return false;
2959                 } else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
2960                         if (!dongle_caps->dfp_cap_ext.encoding_format_caps.support_rgb)
2961                                 return false;
2962                         if (timing->display_color_depth == COLOR_DEPTH_888 &&
2963                                         !dongle_caps->dfp_cap_ext.ycbcr422_color_depth_caps.support_8bpc)
2964                                 return false;
2965                         else if (timing->display_color_depth == COLOR_DEPTH_101010 &&
2966                                         !dongle_caps->dfp_cap_ext.ycbcr422_color_depth_caps.support_10bpc)
2967                                 return false;
2968                         else if (timing->display_color_depth == COLOR_DEPTH_121212 &&
2969                                         !dongle_caps->dfp_cap_ext.ycbcr422_color_depth_caps.support_12bpc)
2970                                 return false;
2971                         else if (timing->display_color_depth == COLOR_DEPTH_161616 &&
2972                                         !dongle_caps->dfp_cap_ext.ycbcr422_color_depth_caps.support_16bpc)
2973                                 return false;
2974                 } else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) {
2975                         if (!dongle_caps->dfp_cap_ext.encoding_format_caps.support_rgb)
2976                                 return false;
2977                         if (timing->display_color_depth == COLOR_DEPTH_888 &&
2978                                         !dongle_caps->dfp_cap_ext.ycbcr420_color_depth_caps.support_8bpc)
2979                                 return false;
2980                         else if (timing->display_color_depth == COLOR_DEPTH_101010 &&
2981                                         !dongle_caps->dfp_cap_ext.ycbcr420_color_depth_caps.support_10bpc)
2982                                 return false;
2983                         else if (timing->display_color_depth == COLOR_DEPTH_121212 &&
2984                                         !dongle_caps->dfp_cap_ext.ycbcr420_color_depth_caps.support_12bpc)
2985                                 return false;
2986                         else if (timing->display_color_depth == COLOR_DEPTH_161616 &&
2987                                         !dongle_caps->dfp_cap_ext.ycbcr420_color_depth_caps.support_16bpc)
2988                                 return false;
2989                 }
2990         }
2991
2992         return true;
2993 }
2994
2995 enum dc_status dc_link_validate_mode_timing(
2996                 const struct dc_stream_state *stream,
2997                 struct dc_link *link,
2998                 const struct dc_crtc_timing *timing)
2999 {
3000         uint32_t max_pix_clk = stream->link->dongle_max_pix_clk * 10;
3001         struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
3002
3003         /* A hack to avoid failing any modes for EDID override feature on
3004          * topology change such as lower quality cable for DP or different dongle
3005          */
3006         if (link->remote_sinks[0] && link->remote_sinks[0]->sink_signal == SIGNAL_TYPE_VIRTUAL)
3007                 return DC_OK;
3008
3009         /* Passive Dongle */
3010         if (max_pix_clk != 0 && get_timing_pixel_clock_100hz(timing) > max_pix_clk)
3011                 return DC_EXCEED_DONGLE_CAP;
3012
3013         /* Active Dongle*/
3014         if (!dp_active_dongle_validate_timing(timing, dpcd_caps))
3015                 return DC_EXCEED_DONGLE_CAP;
3016
3017         switch (stream->signal) {
3018         case SIGNAL_TYPE_EDP:
3019         case SIGNAL_TYPE_DISPLAY_PORT:
3020                 if (!dp_validate_mode_timing(
3021                                 link,
3022                                 timing))
3023                         return DC_NO_DP_LINK_BANDWIDTH;
3024                 break;
3025
3026         default:
3027                 break;
3028         }
3029
3030         return DC_OK;
3031 }
3032
3033 static struct abm *get_abm_from_stream_res(const struct dc_link *link)
3034 {
3035         int i;
3036         struct dc *dc = NULL;
3037         struct abm *abm = NULL;
3038
3039         if (!link || !link->ctx)
3040                 return NULL;
3041
3042         dc = link->ctx->dc;
3043
3044         for (i = 0; i < MAX_PIPES; i++) {
3045                 struct pipe_ctx pipe_ctx = dc->current_state->res_ctx.pipe_ctx[i];
3046                 struct dc_stream_state *stream = pipe_ctx.stream;
3047
3048                 if (stream && stream->link == link) {
3049                         abm = pipe_ctx.stream_res.abm;
3050                         break;
3051                 }
3052         }
3053         return abm;
3054 }
3055
3056 int dc_link_get_backlight_level(const struct dc_link *link)
3057 {
3058         struct abm *abm = get_abm_from_stream_res(link);
3059         struct panel_cntl *panel_cntl = link->panel_cntl;
3060         struct dc  *dc = link->ctx->dc;
3061         struct dmcu *dmcu = dc->res_pool->dmcu;
3062         bool fw_set_brightness = true;
3063
3064         if (dmcu)
3065                 fw_set_brightness = dmcu->funcs->is_dmcu_initialized(dmcu);
3066
3067         if (!fw_set_brightness && panel_cntl->funcs->get_current_backlight)
3068                 return panel_cntl->funcs->get_current_backlight(panel_cntl);
3069         else if (abm != NULL && abm->funcs->get_current_backlight != NULL)
3070                 return (int) abm->funcs->get_current_backlight(abm);
3071         else
3072                 return DC_ERROR_UNEXPECTED;
3073 }
3074
3075 int dc_link_get_target_backlight_pwm(const struct dc_link *link)
3076 {
3077         struct abm *abm = get_abm_from_stream_res(link);
3078
3079         if (abm == NULL || abm->funcs->get_target_backlight == NULL)
3080                 return DC_ERROR_UNEXPECTED;
3081
3082         return (int) abm->funcs->get_target_backlight(abm);
3083 }
3084
3085 static struct pipe_ctx *get_pipe_from_link(const struct dc_link *link)
3086 {
3087         int i;
3088         struct dc *dc = link->ctx->dc;
3089         struct pipe_ctx *pipe_ctx = NULL;
3090
3091         for (i = 0; i < MAX_PIPES; i++) {
3092                 if (dc->current_state->res_ctx.pipe_ctx[i].stream) {
3093                         if (dc->current_state->res_ctx.pipe_ctx[i].stream->link == link) {
3094                                 pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
3095                                 break;
3096                         }
3097                 }
3098         }
3099
3100         return pipe_ctx;
3101 }
3102
3103 bool dc_link_set_backlight_level(const struct dc_link *link,
3104                 uint32_t backlight_pwm_u16_16,
3105                 uint32_t frame_ramp)
3106 {
3107         struct dc  *dc = link->ctx->dc;
3108
3109         DC_LOGGER_INIT(link->ctx->logger);
3110         DC_LOG_BACKLIGHT("New Backlight level: %d (0x%X)\n",
3111                         backlight_pwm_u16_16, backlight_pwm_u16_16);
3112
3113         if (dc_is_embedded_signal(link->connector_signal)) {
3114                 struct pipe_ctx *pipe_ctx = get_pipe_from_link(link);
3115
3116                 if (pipe_ctx) {
3117                         /* Disable brightness ramping when the display is blanked
3118                          * as it can hang the DMCU
3119                          */
3120                         if (pipe_ctx->plane_state == NULL)
3121                                 frame_ramp = 0;
3122                 } else {
3123                         return false;
3124                 }
3125
3126                 dc->hwss.set_backlight_level(
3127                                 pipe_ctx,
3128                                 backlight_pwm_u16_16,
3129                                 frame_ramp);
3130         }
3131         return true;
3132 }
3133
3134 bool dc_link_set_psr_allow_active(struct dc_link *link, const bool *allow_active,
3135                 bool wait, bool force_static, const unsigned int *power_opts)
3136 {
3137         struct dc  *dc = link->ctx->dc;
3138         struct dmcu *dmcu = dc->res_pool->dmcu;
3139         struct dmub_psr *psr = dc->res_pool->psr;
3140         unsigned int panel_inst;
3141
3142         if (psr == NULL && force_static)
3143                 return false;
3144
3145         if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
3146                 return false;
3147
3148         if (allow_active && link->type == dc_connection_none) {
3149                 // Don't enter PSR if panel is not connected
3150                 return false;
3151         }
3152
3153         /* Set power optimization flag */
3154         if (power_opts && link->psr_settings.psr_power_opt != *power_opts) {
3155                 link->psr_settings.psr_power_opt = *power_opts;
3156
3157                 if (psr != NULL && link->psr_settings.psr_feature_enabled && psr->funcs->psr_set_power_opt)
3158                         psr->funcs->psr_set_power_opt(psr, link->psr_settings.psr_power_opt, panel_inst);
3159         }
3160
3161         if (psr != NULL && link->psr_settings.psr_feature_enabled &&
3162                         force_static && psr->funcs->psr_force_static)
3163                 psr->funcs->psr_force_static(psr, panel_inst);
3164
3165         /* Enable or Disable PSR */
3166         if (allow_active && link->psr_settings.psr_allow_active != *allow_active) {
3167                 link->psr_settings.psr_allow_active = *allow_active;
3168
3169                 if (!link->psr_settings.psr_allow_active)
3170                         dc_z10_restore(dc);
3171
3172                 if (psr != NULL && link->psr_settings.psr_feature_enabled) {
3173                         psr->funcs->psr_enable(psr, link->psr_settings.psr_allow_active, wait, panel_inst);
3174                 } else if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu)) &&
3175                         link->psr_settings.psr_feature_enabled)
3176                         dmcu->funcs->set_psr_enable(dmcu, link->psr_settings.psr_allow_active, wait);
3177                 else
3178                         return false;
3179         }
3180
3181         return true;
3182 }
3183
3184 bool dc_link_get_psr_state(const struct dc_link *link, enum dc_psr_state *state)
3185 {
3186         struct dc  *dc = link->ctx->dc;
3187         struct dmcu *dmcu = dc->res_pool->dmcu;
3188         struct dmub_psr *psr = dc->res_pool->psr;
3189         unsigned int panel_inst;
3190
3191         if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
3192                 return false;
3193
3194         if (psr != NULL && link->psr_settings.psr_feature_enabled)
3195                 psr->funcs->psr_get_state(psr, state, panel_inst);
3196         else if (dmcu != NULL && link->psr_settings.psr_feature_enabled)
3197                 dmcu->funcs->get_psr_state(dmcu, state);
3198
3199         return true;
3200 }
3201
3202 static inline enum physical_phy_id
3203 transmitter_to_phy_id(enum transmitter transmitter_value)
3204 {
3205         switch (transmitter_value) {
3206         case TRANSMITTER_UNIPHY_A:
3207                 return PHYLD_0;
3208         case TRANSMITTER_UNIPHY_B:
3209                 return PHYLD_1;
3210         case TRANSMITTER_UNIPHY_C:
3211                 return PHYLD_2;
3212         case TRANSMITTER_UNIPHY_D:
3213                 return PHYLD_3;
3214         case TRANSMITTER_UNIPHY_E:
3215                 return PHYLD_4;
3216         case TRANSMITTER_UNIPHY_F:
3217                 return PHYLD_5;
3218         case TRANSMITTER_NUTMEG_CRT:
3219                 return PHYLD_6;
3220         case TRANSMITTER_TRAVIS_CRT:
3221                 return PHYLD_7;
3222         case TRANSMITTER_TRAVIS_LCD:
3223                 return PHYLD_8;
3224         case TRANSMITTER_UNIPHY_G:
3225                 return PHYLD_9;
3226         case TRANSMITTER_COUNT:
3227                 return PHYLD_COUNT;
3228         case TRANSMITTER_UNKNOWN:
3229                 return PHYLD_UNKNOWN;
3230         default:
3231                 WARN_ONCE(1, "Unknown transmitter value %d\n",
3232                           transmitter_value);
3233                 return PHYLD_UNKNOWN;
3234         }
3235 }
3236
3237 bool dc_link_setup_psr(struct dc_link *link,
3238                 const struct dc_stream_state *stream, struct psr_config *psr_config,
3239                 struct psr_context *psr_context)
3240 {
3241         struct dc *dc;
3242         struct dmcu *dmcu;
3243         struct dmub_psr *psr;
3244         int i;
3245         unsigned int panel_inst;
3246         /* updateSinkPsrDpcdConfig*/
3247         union dpcd_psr_configuration psr_configuration;
3248         union dpcd_sink_active_vtotal_control_mode vtotal_control = {0};
3249
3250         psr_context->controllerId = CONTROLLER_ID_UNDEFINED;
3251
3252         if (!link)
3253                 return false;
3254
3255         dc = link->ctx->dc;
3256         dmcu = dc->res_pool->dmcu;
3257         psr = dc->res_pool->psr;
3258
3259         if (!dmcu && !psr)
3260                 return false;
3261
3262         if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
3263                 return false;
3264
3265
3266         memset(&psr_configuration, 0, sizeof(psr_configuration));
3267
3268         psr_configuration.bits.ENABLE                    = 1;
3269         psr_configuration.bits.CRC_VERIFICATION          = 1;
3270         psr_configuration.bits.FRAME_CAPTURE_INDICATION  =
3271                         psr_config->psr_frame_capture_indication_req;
3272
3273         /* Check for PSR v2*/
3274         if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) {
3275                 /* For PSR v2 selective update.
3276                  * Indicates whether sink should start capturing
3277                  * immediately following active scan line,
3278                  * or starting with the 2nd active scan line.
3279                  */
3280                 psr_configuration.bits.LINE_CAPTURE_INDICATION = 0;
3281                 /*For PSR v2, determines whether Sink should generate
3282                  * IRQ_HPD when CRC mismatch is detected.
3283                  */
3284                 psr_configuration.bits.IRQ_HPD_WITH_CRC_ERROR    = 1;
3285                 /* For PSR v2, set the bit when the Source device will
3286                  * be enabling PSR2 operation.
3287                  */
3288                 psr_configuration.bits.ENABLE_PSR2    = 1;
3289                 /* For PSR v2, the Sink device must be able to receive
3290                  * SU region updates early in the frame time.
3291                  */
3292                 psr_configuration.bits.EARLY_TRANSPORT_ENABLE    = 1;
3293         }
3294
3295         dm_helpers_dp_write_dpcd(
3296                 link->ctx,
3297                 link,
3298                 368,
3299                 &psr_configuration.raw,
3300                 sizeof(psr_configuration.raw));
3301
3302         if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) {
3303                 dc_power_alpm_dpcd_enable(link, true);
3304                 psr_context->su_granularity_required =
3305                         psr_config->su_granularity_required;
3306                 psr_context->su_y_granularity =
3307                         psr_config->su_y_granularity;
3308                 psr_context->line_time_in_us =
3309                         psr_config->line_time_in_us;
3310
3311                 if (link->psr_settings.psr_vtotal_control_support) {
3312                         psr_context->rate_control_caps = psr_config->rate_control_caps;
3313                         vtotal_control.bits.ENABLE = true;
3314                         core_link_write_dpcd(link, DP_SINK_PSR_ACTIVE_VTOTAL_CONTROL_MODE,
3315                                                         &vtotal_control.raw, sizeof(vtotal_control.raw));
3316                 }
3317         }
3318
3319         psr_context->channel = link->ddc->ddc_pin->hw_info.ddc_channel;
3320         psr_context->transmitterId = link->link_enc->transmitter;
3321         psr_context->engineId = link->link_enc->preferred_engine;
3322
3323         for (i = 0; i < MAX_PIPES; i++) {
3324                 if (dc->current_state->res_ctx.pipe_ctx[i].stream
3325                                 == stream) {
3326                         /* dmcu -1 for all controller id values,
3327                          * therefore +1 here
3328                          */
3329                         psr_context->controllerId =
3330                                 dc->current_state->res_ctx.
3331                                 pipe_ctx[i].stream_res.tg->inst + 1;
3332                         break;
3333                 }
3334         }
3335
3336         /* Hardcoded for now.  Can be Pcie or Uniphy (or Unknown)*/
3337         psr_context->phyType = PHY_TYPE_UNIPHY;
3338         /*PhyId is associated with the transmitter id*/
3339         psr_context->smuPhyId =
3340                 transmitter_to_phy_id(link->link_enc->transmitter);
3341
3342         psr_context->crtcTimingVerticalTotal = stream->timing.v_total;
3343         psr_context->vsync_rate_hz = div64_u64(div64_u64((stream->
3344                                         timing.pix_clk_100hz * 100),
3345                                         stream->timing.v_total),
3346                                         stream->timing.h_total);
3347
3348         psr_context->psrSupportedDisplayConfig = true;
3349         psr_context->psrExitLinkTrainingRequired =
3350                 psr_config->psr_exit_link_training_required;
3351         psr_context->sdpTransmitLineNumDeadline =
3352                 psr_config->psr_sdp_transmit_line_num_deadline;
3353         psr_context->psrFrameCaptureIndicationReq =
3354                 psr_config->psr_frame_capture_indication_req;
3355
3356         psr_context->skipPsrWaitForPllLock = 0; /* only = 1 in KV */
3357
3358         psr_context->numberOfControllers =
3359                         link->dc->res_pool->timing_generator_count;
3360
3361         psr_context->rfb_update_auto_en = true;
3362
3363         /* 2 frames before enter PSR. */
3364         psr_context->timehyst_frames = 2;
3365         /* half a frame
3366          * (units in 100 lines, i.e. a value of 1 represents 100 lines)
3367          */
3368         psr_context->hyst_lines = stream->timing.v_total / 2 / 100;
3369         psr_context->aux_repeats = 10;
3370
3371         psr_context->psr_level.u32all = 0;
3372
3373         /*skip power down the single pipe since it blocks the cstate*/
3374 #if defined(CONFIG_DRM_AMD_DC_DCN)
3375         if (link->ctx->asic_id.chip_family >= FAMILY_RV) {
3376                 switch(link->ctx->asic_id.chip_family) {
3377                 case FAMILY_YELLOW_CARP:
3378                 case AMDGPU_FAMILY_GC_10_3_6:
3379                 case AMDGPU_FAMILY_GC_11_0_1:
3380                         if(!dc->debug.disable_z10)
3381                                 psr_context->psr_level.bits.SKIP_CRTC_DISABLE = false;
3382                         break;
3383                 default:
3384                         psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true;
3385                         break;
3386                 }
3387         }
3388 #else
3389         if (link->ctx->asic_id.chip_family >= FAMILY_RV)
3390                 psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true;
3391 #endif
3392
3393         /* SMU will perform additional powerdown sequence.
3394          * For unsupported ASICs, set psr_level flag to skip PSR
3395          *  static screen notification to SMU.
3396          *  (Always set for DAL2, did not check ASIC)
3397          */
3398         psr_context->allow_smu_optimizations = psr_config->allow_smu_optimizations;
3399         psr_context->allow_multi_disp_optimizations = psr_config->allow_multi_disp_optimizations;
3400
3401         /* Complete PSR entry before aborting to prevent intermittent
3402          * freezes on certain eDPs
3403          */
3404         psr_context->psr_level.bits.DISABLE_PSR_ENTRY_ABORT = 1;
3405
3406         /* enable ALPM */
3407         psr_context->psr_level.bits.DISABLE_ALPM = 0;
3408         psr_context->psr_level.bits.ALPM_DEFAULT_PD_MODE = 1;
3409
3410         /* Controls additional delay after remote frame capture before
3411          * continuing power down, default = 0
3412          */
3413         psr_context->frame_delay = 0;
3414
3415         if (psr) {
3416                 link->psr_settings.psr_feature_enabled = psr->funcs->psr_copy_settings(psr,
3417                         link, psr_context, panel_inst);
3418                 link->psr_settings.psr_power_opt = 0;
3419                 link->psr_settings.psr_allow_active = 0;
3420         }
3421         else
3422                 link->psr_settings.psr_feature_enabled = dmcu->funcs->setup_psr(dmcu, link, psr_context);
3423
3424         /* psr_enabled == 0 indicates setup_psr did not succeed, but this
3425          * should not happen since firmware should be running at this point
3426          */
3427         if (link->psr_settings.psr_feature_enabled == 0)
3428                 ASSERT(0);
3429
3430         return true;
3431
3432 }
3433
3434 void dc_link_get_psr_residency(const struct dc_link *link, uint32_t *residency)
3435 {
3436         struct dc  *dc = link->ctx->dc;
3437         struct dmub_psr *psr = dc->res_pool->psr;
3438         unsigned int panel_inst;
3439
3440         if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
3441                 return;
3442
3443         /* PSR residency measurements only supported on DMCUB */
3444         if (psr != NULL && link->psr_settings.psr_feature_enabled)
3445                 psr->funcs->psr_get_residency(psr, residency, panel_inst);
3446         else
3447                 *residency = 0;
3448 }
3449
3450 bool dc_link_set_sink_vtotal_in_psr_active(const struct dc_link *link, uint16_t psr_vtotal_idle, uint16_t psr_vtotal_su)
3451 {
3452         struct dc *dc = link->ctx->dc;
3453         struct dmub_psr *psr = dc->res_pool->psr;
3454
3455         if (psr == NULL || !link->psr_settings.psr_feature_enabled || !link->psr_settings.psr_vtotal_control_support)
3456                 return false;
3457
3458         psr->funcs->psr_set_sink_vtotal_in_psr_active(psr, psr_vtotal_idle, psr_vtotal_su);
3459
3460         return true;
3461 }
3462
3463 const struct dc_link_status *dc_link_get_status(const struct dc_link *link)
3464 {
3465         return &link->link_status;
3466 }
3467
3468 void core_link_resume(struct dc_link *link)
3469 {
3470         if (link->connector_signal != SIGNAL_TYPE_VIRTUAL)
3471                 program_hpd_filter(link);
3472 }
3473
3474 static struct fixed31_32 get_pbn_per_slot(struct dc_stream_state *stream)
3475 {
3476         struct fixed31_32 mbytes_per_sec;
3477         uint32_t link_rate_in_mbytes_per_sec = dc_link_bandwidth_kbps(stream->link,
3478                         &stream->link->cur_link_settings);
3479         link_rate_in_mbytes_per_sec /= 8000; /* Kbits to MBytes */
3480
3481         mbytes_per_sec = dc_fixpt_from_int(link_rate_in_mbytes_per_sec);
3482
3483         return dc_fixpt_div_int(mbytes_per_sec, 54);
3484 }
3485
3486 static struct fixed31_32 get_pbn_from_bw_in_kbps(uint64_t kbps)
3487 {
3488         struct fixed31_32 peak_kbps;
3489         uint32_t numerator = 0;
3490         uint32_t denominator = 1;
3491
3492         /*
3493          * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
3494          * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on
3495          * common multiplier to render an integer PBN for all link rate/lane
3496          * counts combinations
3497          * calculate
3498          * peak_kbps *= (1006/1000)
3499          * peak_kbps *= (64/54)
3500          * peak_kbps *= 8    convert to bytes
3501          */
3502
3503         numerator = 64 * PEAK_FACTOR_X1000;
3504         denominator = 54 * 8 * 1000 * 1000;
3505         kbps *= numerator;
3506         peak_kbps = dc_fixpt_from_fraction(kbps, denominator);
3507
3508         return peak_kbps;
3509 }
3510
3511 static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx)
3512 {
3513         uint64_t kbps;
3514
3515         kbps = dc_bandwidth_in_kbps_from_timing(&pipe_ctx->stream->timing);
3516         return get_pbn_from_bw_in_kbps(kbps);
3517 }
3518
3519 static void update_mst_stream_alloc_table(
3520         struct dc_link *link,
3521         struct stream_encoder *stream_enc,
3522         struct hpo_dp_stream_encoder *hpo_dp_stream_enc, // TODO: Rename stream_enc to dio_stream_enc?
3523         const struct dc_dp_mst_stream_allocation_table *proposed_table)
3524 {
3525         struct link_mst_stream_allocation work_table[MAX_CONTROLLER_NUM] = { 0 };
3526         struct link_mst_stream_allocation *dc_alloc;
3527
3528         int i;
3529         int j;
3530
3531         /* if DRM proposed_table has more than one new payload */
3532         ASSERT(proposed_table->stream_count -
3533                         link->mst_stream_alloc_table.stream_count < 2);
3534
3535         /* copy proposed_table to link, add stream encoder */
3536         for (i = 0; i < proposed_table->stream_count; i++) {
3537
3538                 for (j = 0; j < link->mst_stream_alloc_table.stream_count; j++) {
3539                         dc_alloc =
3540                         &link->mst_stream_alloc_table.stream_allocations[j];
3541
3542                         if (dc_alloc->vcp_id ==
3543                                 proposed_table->stream_allocations[i].vcp_id) {
3544
3545                                 work_table[i] = *dc_alloc;
3546                                 work_table[i].slot_count = proposed_table->stream_allocations[i].slot_count;
3547                                 break; /* exit j loop */
3548                         }
3549                 }
3550
3551                 /* new vcp_id */
3552                 if (j == link->mst_stream_alloc_table.stream_count) {
3553                         work_table[i].vcp_id =
3554                                 proposed_table->stream_allocations[i].vcp_id;
3555                         work_table[i].slot_count =
3556                                 proposed_table->stream_allocations[i].slot_count;
3557                         work_table[i].stream_enc = stream_enc;
3558                         work_table[i].hpo_dp_stream_enc = hpo_dp_stream_enc;
3559                 }
3560         }
3561
3562         /* update link->mst_stream_alloc_table with work_table */
3563         link->mst_stream_alloc_table.stream_count =
3564                         proposed_table->stream_count;
3565         for (i = 0; i < MAX_CONTROLLER_NUM; i++)
3566                 link->mst_stream_alloc_table.stream_allocations[i] =
3567                                 work_table[i];
3568 }
3569
3570 static void dc_log_vcp_x_y(const struct dc_link *link, struct fixed31_32 avg_time_slots_per_mtp)
3571 {
3572         const uint32_t VCP_Y_PRECISION = 1000;
3573         uint64_t vcp_x, vcp_y;
3574
3575         // Add 0.5*(1/VCP_Y_PRECISION) to round up to decimal precision
3576         avg_time_slots_per_mtp = dc_fixpt_add(
3577                         avg_time_slots_per_mtp, dc_fixpt_from_fraction(1, 2 * VCP_Y_PRECISION));
3578
3579         vcp_x = dc_fixpt_floor(avg_time_slots_per_mtp);
3580         vcp_y = dc_fixpt_floor(
3581                         dc_fixpt_mul_int(
3582                                 dc_fixpt_sub_int(avg_time_slots_per_mtp, dc_fixpt_floor(avg_time_slots_per_mtp)),
3583                                 VCP_Y_PRECISION));
3584
3585         if (link->type == dc_connection_mst_branch)
3586                 DC_LOG_DP2("MST Update Payload: set_throttled_vcp_size slot X.Y for MST stream "
3587                                 "X: %lld Y: %lld/%d", vcp_x, vcp_y, VCP_Y_PRECISION);
3588         else
3589                 DC_LOG_DP2("SST Update Payload: set_throttled_vcp_size slot X.Y for SST stream "
3590                                 "X: %lld Y: %lld/%d", vcp_x, vcp_y, VCP_Y_PRECISION);
3591 }
3592
3593 /*
3594  * Payload allocation/deallocation for SST introduced in DP2.0
3595  */
3596 static enum dc_status dc_link_update_sst_payload(struct pipe_ctx *pipe_ctx,
3597                                                  bool allocate)
3598 {
3599         struct dc_stream_state *stream = pipe_ctx->stream;
3600         struct dc_link *link = stream->link;
3601         struct link_mst_stream_allocation_table proposed_table = {0};
3602         struct fixed31_32 avg_time_slots_per_mtp;
3603         const struct dc_link_settings empty_link_settings = {0};
3604         const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
3605         DC_LOGGER_INIT(link->ctx->logger);
3606
3607         /* slot X.Y for SST payload deallocate */
3608         if (!allocate) {
3609                 avg_time_slots_per_mtp = dc_fixpt_from_int(0);
3610
3611                 dc_log_vcp_x_y(link, avg_time_slots_per_mtp);
3612
3613                 if (link_hwss->ext.set_throttled_vcp_size)
3614                         link_hwss->ext.set_throttled_vcp_size(pipe_ctx,
3615                                         avg_time_slots_per_mtp);
3616                 if (link_hwss->ext.set_hblank_min_symbol_width)
3617                         link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx,
3618                                         &empty_link_settings,
3619                                         avg_time_slots_per_mtp);
3620         }
3621
3622         /* calculate VC payload and update branch with new payload allocation table*/
3623         if (!dpcd_write_128b_132b_sst_payload_allocation_table(
3624                         stream,
3625                         link,
3626                         &proposed_table,
3627                         allocate)) {
3628                 DC_LOG_ERROR("SST Update Payload: Failed to update "
3629                                                 "allocation table for "
3630                                                 "pipe idx: %d\n",
3631                                                 pipe_ctx->pipe_idx);
3632                 return DC_FAIL_DP_PAYLOAD_ALLOCATION;
3633         }
3634
3635         proposed_table.stream_allocations[0].hpo_dp_stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc;
3636
3637         ASSERT(proposed_table.stream_count == 1);
3638
3639         //TODO - DP2.0 Logging: Instead of hpo_dp_stream_enc pointer, log instance id
3640         DC_LOG_DP2("SST Update Payload: hpo_dp_stream_enc: %p      "
3641                 "vcp_id: %d      "
3642                 "slot_count: %d\n",
3643                 (void *) proposed_table.stream_allocations[0].hpo_dp_stream_enc,
3644                 proposed_table.stream_allocations[0].vcp_id,
3645                 proposed_table.stream_allocations[0].slot_count);
3646
3647         /* program DP source TX for payload */
3648         link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res,
3649                         &proposed_table);
3650
3651         /* poll for ACT handled */
3652         if (!dpcd_poll_for_allocation_change_trigger(link)) {
3653                 // Failures will result in blackscreen and errors logged
3654                 BREAK_TO_DEBUGGER();
3655         }
3656
3657         /* slot X.Y for SST payload allocate */
3658         if (allocate && dp_get_link_encoding_format(&link->cur_link_settings) ==
3659                         DP_128b_132b_ENCODING) {
3660                 avg_time_slots_per_mtp = calculate_sst_avg_time_slots_per_mtp(stream, link);
3661
3662                 dc_log_vcp_x_y(link, avg_time_slots_per_mtp);
3663
3664                 if (link_hwss->ext.set_throttled_vcp_size)
3665                         link_hwss->ext.set_throttled_vcp_size(pipe_ctx,
3666                                         avg_time_slots_per_mtp);
3667                 if (link_hwss->ext.set_hblank_min_symbol_width)
3668                         link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx,
3669                                         &link->cur_link_settings,
3670                                         avg_time_slots_per_mtp);
3671         }
3672
3673         /* Always return DC_OK.
3674          * If part of sequence fails, log failure(s) and show blackscreen
3675          */
3676         return DC_OK;
3677 }
3678
3679 /* convert link_mst_stream_alloc_table to dm dp_mst_stream_alloc_table
3680  * because stream_encoder is not exposed to dm
3681  */
3682 enum dc_status dc_link_allocate_mst_payload(struct pipe_ctx *pipe_ctx)
3683 {
3684         struct dc_stream_state *stream = pipe_ctx->stream;
3685         struct dc_link *link = stream->link;
3686         struct dc_dp_mst_stream_allocation_table proposed_table = {0};
3687         struct fixed31_32 avg_time_slots_per_mtp;
3688         struct fixed31_32 pbn;
3689         struct fixed31_32 pbn_per_slot;
3690         int i;
3691         enum act_return_status ret;
3692         const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
3693         DC_LOGGER_INIT(link->ctx->logger);
3694
3695         /* enable_link_dp_mst already check link->enabled_stream_count
3696          * and stream is in link->stream[]. This is called during set mode,
3697          * stream_enc is available.
3698          */
3699
3700         /* get calculate VC payload for stream: stream_alloc */
3701         if (dm_helpers_dp_mst_write_payload_allocation_table(
3702                 stream->ctx,
3703                 stream,
3704                 &proposed_table,
3705                 true))
3706                 update_mst_stream_alloc_table(
3707                                         link,
3708                                         pipe_ctx->stream_res.stream_enc,
3709                                         pipe_ctx->stream_res.hpo_dp_stream_enc,
3710                                         &proposed_table);
3711         else
3712                 DC_LOG_WARNING("Failed to update"
3713                                 "MST allocation table for"
3714                                 "pipe idx:%d\n",
3715                                 pipe_ctx->pipe_idx);
3716
3717         DC_LOG_MST("%s  "
3718                         "stream_count: %d: \n ",
3719                         __func__,
3720                         link->mst_stream_alloc_table.stream_count);
3721
3722         for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
3723                 DC_LOG_MST("stream_enc[%d]: %p      "
3724                 "stream[%d].hpo_dp_stream_enc: %p      "
3725                 "stream[%d].vcp_id: %d      "
3726                 "stream[%d].slot_count: %d\n",
3727                 i,
3728                 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
3729                 i,
3730                 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc,
3731                 i,
3732                 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
3733                 i,
3734                 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
3735         }
3736
3737         ASSERT(proposed_table.stream_count > 0);
3738
3739         /* program DP source TX for payload */
3740         if (link_hwss->ext.update_stream_allocation_table == NULL ||
3741                         dp_get_link_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) {
3742                 DC_LOG_ERROR("Failure: unknown encoding format\n");
3743                 return DC_ERROR_UNEXPECTED;
3744         }
3745
3746         link_hwss->ext.update_stream_allocation_table(link,
3747                         &pipe_ctx->link_res,
3748                         &link->mst_stream_alloc_table);
3749
3750         /* send down message */
3751         ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger(
3752                         stream->ctx,
3753                         stream);
3754
3755         if (ret != ACT_LINK_LOST) {
3756                 dm_helpers_dp_mst_send_payload_allocation(
3757                                 stream->ctx,
3758                                 stream,
3759                                 true);
3760         }
3761
3762         /* slot X.Y for only current stream */
3763         pbn_per_slot = get_pbn_per_slot(stream);
3764         if (pbn_per_slot.value == 0) {
3765                 DC_LOG_ERROR("Failure: pbn_per_slot==0 not allowed. Cannot continue, returning DC_UNSUPPORTED_VALUE.\n");
3766                 return DC_UNSUPPORTED_VALUE;
3767         }
3768         pbn = get_pbn_from_timing(pipe_ctx);
3769         avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot);
3770
3771         dc_log_vcp_x_y(link, avg_time_slots_per_mtp);
3772
3773         if (link_hwss->ext.set_throttled_vcp_size)
3774                 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp);
3775         if (link_hwss->ext.set_hblank_min_symbol_width)
3776                 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx,
3777                                 &link->cur_link_settings,
3778                                 avg_time_slots_per_mtp);
3779
3780         return DC_OK;
3781
3782 }
3783
3784 enum dc_status dc_link_reduce_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps)
3785 {
3786         struct dc_stream_state *stream = pipe_ctx->stream;
3787         struct dc_link *link = stream->link;
3788         struct fixed31_32 avg_time_slots_per_mtp;
3789         struct fixed31_32 pbn;
3790         struct fixed31_32 pbn_per_slot;
3791         struct dc_dp_mst_stream_allocation_table proposed_table = {0};
3792         uint8_t i;
3793         const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
3794         DC_LOGGER_INIT(link->ctx->logger);
3795
3796         /* decrease throttled vcp size */
3797         pbn_per_slot = get_pbn_per_slot(stream);
3798         pbn = get_pbn_from_bw_in_kbps(bw_in_kbps);
3799         avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot);
3800
3801         if (link_hwss->ext.set_throttled_vcp_size)
3802                 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp);
3803         if (link_hwss->ext.set_hblank_min_symbol_width)
3804                 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx,
3805                                 &link->cur_link_settings,
3806                                 avg_time_slots_per_mtp);
3807
3808         /* send ALLOCATE_PAYLOAD sideband message with updated pbn */
3809         dm_helpers_dp_mst_send_payload_allocation(
3810                         stream->ctx,
3811                         stream,
3812                         true);
3813
3814         /* notify immediate branch device table update */
3815         if (dm_helpers_dp_mst_write_payload_allocation_table(
3816                         stream->ctx,
3817                         stream,
3818                         &proposed_table,
3819                         true)) {
3820                 /* update mst stream allocation table software state */
3821                 update_mst_stream_alloc_table(
3822                                 link,
3823                                 pipe_ctx->stream_res.stream_enc,
3824                                 pipe_ctx->stream_res.hpo_dp_stream_enc,
3825                                 &proposed_table);
3826         } else {
3827                 DC_LOG_WARNING("Failed to update"
3828                                 "MST allocation table for"
3829                                 "pipe idx:%d\n",
3830                                 pipe_ctx->pipe_idx);
3831         }
3832
3833         DC_LOG_MST("%s  "
3834                         "stream_count: %d: \n ",
3835                         __func__,
3836                         link->mst_stream_alloc_table.stream_count);
3837
3838         for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
3839                 DC_LOG_MST("stream_enc[%d]: %p      "
3840                                 "stream[%d].hpo_dp_stream_enc: %p      "
3841                                 "stream[%d].vcp_id: %d      "
3842                                 "stream[%d].slot_count: %d\n",
3843                                 i,
3844                                 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
3845                                 i,
3846                                 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc,
3847                                 i,
3848                                 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
3849                                 i,
3850                                 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
3851         }
3852
3853         ASSERT(proposed_table.stream_count > 0);
3854
3855         /* update mst stream allocation table hardware state */
3856         if (link_hwss->ext.update_stream_allocation_table == NULL ||
3857                         dp_get_link_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) {
3858                 DC_LOG_ERROR("Failure: unknown encoding format\n");
3859                 return DC_ERROR_UNEXPECTED;
3860         }
3861
3862         link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res,
3863                         &link->mst_stream_alloc_table);
3864
3865         /* poll for immediate branch device ACT handled */
3866         dm_helpers_dp_mst_poll_for_allocation_change_trigger(
3867                         stream->ctx,
3868                         stream);
3869
3870         return DC_OK;
3871 }
3872
3873 enum dc_status dc_link_increase_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in_kbps)
3874 {
3875         struct dc_stream_state *stream = pipe_ctx->stream;
3876         struct dc_link *link = stream->link;
3877         struct fixed31_32 avg_time_slots_per_mtp;
3878         struct fixed31_32 pbn;
3879         struct fixed31_32 pbn_per_slot;
3880         struct dc_dp_mst_stream_allocation_table proposed_table = {0};
3881         uint8_t i;
3882         enum act_return_status ret;
3883         const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
3884         DC_LOGGER_INIT(link->ctx->logger);
3885
3886         /* notify immediate branch device table update */
3887         if (dm_helpers_dp_mst_write_payload_allocation_table(
3888                                 stream->ctx,
3889                                 stream,
3890                                 &proposed_table,
3891                                 true)) {
3892                 /* update mst stream allocation table software state */
3893                 update_mst_stream_alloc_table(
3894                                 link,
3895                                 pipe_ctx->stream_res.stream_enc,
3896                                 pipe_ctx->stream_res.hpo_dp_stream_enc,
3897                                 &proposed_table);
3898         }
3899
3900         DC_LOG_MST("%s  "
3901                         "stream_count: %d: \n ",
3902                         __func__,
3903                         link->mst_stream_alloc_table.stream_count);
3904
3905         for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
3906                 DC_LOG_MST("stream_enc[%d]: %p      "
3907                                 "stream[%d].hpo_dp_stream_enc: %p      "
3908                                 "stream[%d].vcp_id: %d      "
3909                                 "stream[%d].slot_count: %d\n",
3910                                 i,
3911                                 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
3912                                 i,
3913                                 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc,
3914                                 i,
3915                                 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
3916                                 i,
3917                                 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
3918         }
3919
3920         ASSERT(proposed_table.stream_count > 0);
3921
3922         /* update mst stream allocation table hardware state */
3923         if (link_hwss->ext.update_stream_allocation_table == NULL ||
3924                         dp_get_link_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) {
3925                 DC_LOG_ERROR("Failure: unknown encoding format\n");
3926                 return DC_ERROR_UNEXPECTED;
3927         }
3928
3929         link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res,
3930                         &link->mst_stream_alloc_table);
3931
3932         /* poll for immediate branch device ACT handled */
3933         ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger(
3934                         stream->ctx,
3935                         stream);
3936
3937         if (ret != ACT_LINK_LOST) {
3938                 /* send ALLOCATE_PAYLOAD sideband message with updated pbn */
3939                 dm_helpers_dp_mst_send_payload_allocation(
3940                                 stream->ctx,
3941                                 stream,
3942                                 true);
3943         }
3944
3945         /* increase throttled vcp size */
3946         pbn = get_pbn_from_bw_in_kbps(bw_in_kbps);
3947         pbn_per_slot = get_pbn_per_slot(stream);
3948         avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot);
3949
3950         if (link_hwss->ext.set_throttled_vcp_size)
3951                 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp);
3952         if (link_hwss->ext.set_hblank_min_symbol_width)
3953                 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx,
3954                                 &link->cur_link_settings,
3955                                 avg_time_slots_per_mtp);
3956
3957         return DC_OK;
3958 }
3959
3960 static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx)
3961 {
3962         struct dc_stream_state *stream = pipe_ctx->stream;
3963         struct dc_link *link = stream->link;
3964         struct dc_dp_mst_stream_allocation_table proposed_table = {0};
3965         struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0);
3966         int i;
3967         bool mst_mode = (link->type == dc_connection_mst_branch);
3968         const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
3969         const struct dc_link_settings empty_link_settings = {0};
3970         DC_LOGGER_INIT(link->ctx->logger);
3971
3972         /* deallocate_mst_payload is called before disable link. When mode or
3973          * disable/enable monitor, new stream is created which is not in link
3974          * stream[] yet. For this, payload is not allocated yet, so de-alloc
3975          * should not done. For new mode set, map_resources will get engine
3976          * for new stream, so stream_enc->id should be validated until here.
3977          */
3978
3979         /* slot X.Y */
3980         if (link_hwss->ext.set_throttled_vcp_size)
3981                 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp);
3982         if (link_hwss->ext.set_hblank_min_symbol_width)
3983                 link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx,
3984                                 &empty_link_settings,
3985                                 avg_time_slots_per_mtp);
3986
3987         /* TODO: which component is responsible for remove payload table? */
3988         if (mst_mode) {
3989                 if (dm_helpers_dp_mst_write_payload_allocation_table(
3990                                 stream->ctx,
3991                                 stream,
3992                                 &proposed_table,
3993                                 false)) {
3994
3995                         update_mst_stream_alloc_table(
3996                                                 link,
3997                                                 pipe_ctx->stream_res.stream_enc,
3998                                                 pipe_ctx->stream_res.hpo_dp_stream_enc,
3999                                                 &proposed_table);
4000                 }
4001                 else {
4002                                 DC_LOG_WARNING("Failed to update"
4003                                                 "MST allocation table for"
4004                                                 "pipe idx:%d\n",
4005                                                 pipe_ctx->pipe_idx);
4006                 }
4007         }
4008
4009         DC_LOG_MST("%s"
4010                         "stream_count: %d: ",
4011                         __func__,
4012                         link->mst_stream_alloc_table.stream_count);
4013
4014         for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
4015                 DC_LOG_MST("stream_enc[%d]: %p      "
4016                 "stream[%d].hpo_dp_stream_enc: %p      "
4017                 "stream[%d].vcp_id: %d      "
4018                 "stream[%d].slot_count: %d\n",
4019                 i,
4020                 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
4021                 i,
4022                 (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc,
4023                 i,
4024                 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
4025                 i,
4026                 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
4027         }
4028
4029         /* update mst stream allocation table hardware state */
4030         if (link_hwss->ext.update_stream_allocation_table == NULL ||
4031                         dp_get_link_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) {
4032                 DC_LOG_DEBUG("Unknown encoding format\n");
4033                 return DC_ERROR_UNEXPECTED;
4034         }
4035
4036         link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res,
4037                         &link->mst_stream_alloc_table);
4038
4039         if (mst_mode) {
4040                 dm_helpers_dp_mst_poll_for_allocation_change_trigger(
4041                         stream->ctx,
4042                         stream);
4043
4044                 dm_helpers_dp_mst_send_payload_allocation(
4045                         stream->ctx,
4046                         stream,
4047                         false);
4048         }
4049
4050         return DC_OK;
4051 }
4052
4053
4054 #if defined(CONFIG_DRM_AMD_DC_HDCP)
4055 static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off)
4056 {
4057         struct cp_psp *cp_psp = &pipe_ctx->stream->ctx->cp_psp;
4058         struct link_encoder *link_enc = NULL;
4059         struct cp_psp_stream_config config = {0};
4060         enum dp_panel_mode panel_mode =
4061                         dp_get_panel_mode(pipe_ctx->stream->link);
4062
4063         if (cp_psp == NULL || cp_psp->funcs.update_stream_config == NULL)
4064                 return;
4065
4066         link_enc = link_enc_cfg_get_link_enc(pipe_ctx->stream->link);
4067         ASSERT(link_enc);
4068         if (link_enc == NULL)
4069                 return;
4070
4071         /* otg instance */
4072         config.otg_inst = (uint8_t) pipe_ctx->stream_res.tg->inst;
4073
4074         /* dig front end */
4075         config.dig_fe = (uint8_t) pipe_ctx->stream_res.stream_enc->stream_enc_inst;
4076
4077         /* stream encoder index */
4078         config.stream_enc_idx = pipe_ctx->stream_res.stream_enc->id - ENGINE_ID_DIGA;
4079         if (is_dp_128b_132b_signal(pipe_ctx))
4080                 config.stream_enc_idx =
4081                                 pipe_ctx->stream_res.hpo_dp_stream_enc->id - ENGINE_ID_HPO_DP_0;
4082
4083         /* dig back end */
4084         config.dig_be = pipe_ctx->stream->link->link_enc_hw_inst;
4085
4086         /* link encoder index */
4087         config.link_enc_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A;
4088         if (is_dp_128b_132b_signal(pipe_ctx))
4089                 config.link_enc_idx = pipe_ctx->link_res.hpo_dp_link_enc->inst;
4090
4091         /* dio output index is dpia index for DPIA endpoint & dcio index by default */
4092         if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
4093                 config.dio_output_idx = pipe_ctx->stream->link->link_id.enum_id - ENUM_ID_1;
4094         else
4095                 config.dio_output_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A;
4096
4097
4098         /* phy index */
4099         config.phy_idx = resource_transmitter_to_phy_idx(
4100                         pipe_ctx->stream->link->dc, link_enc->transmitter);
4101         if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
4102                 /* USB4 DPIA doesn't use PHY in our soc, initialize it to 0 */
4103                 config.phy_idx = 0;
4104
4105         /* stream properties */
4106         config.assr_enabled = (panel_mode == DP_PANEL_MODE_EDP) ? 1 : 0;
4107         config.mst_enabled = (pipe_ctx->stream->signal ==
4108                         SIGNAL_TYPE_DISPLAY_PORT_MST) ? 1 : 0;
4109         config.dp2_enabled = is_dp_128b_132b_signal(pipe_ctx) ? 1 : 0;
4110         config.usb4_enabled = (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) ?
4111                         1 : 0;
4112         config.dpms_off = dpms_off;
4113
4114         /* dm stream context */
4115         config.dm_stream_ctx = pipe_ctx->stream->dm_stream_context;
4116
4117         cp_psp->funcs.update_stream_config(cp_psp->handle, &config);
4118 }
4119 #endif
4120
4121 static void fpga_dp_hpo_enable_link_and_stream(struct dc_state *state, struct pipe_ctx *pipe_ctx)
4122 {
4123         struct dc *dc = pipe_ctx->stream->ctx->dc;
4124         struct dc_stream_state *stream = pipe_ctx->stream;
4125         struct link_mst_stream_allocation_table proposed_table = {0};
4126         struct fixed31_32 avg_time_slots_per_mtp;
4127         uint8_t req_slot_count = 0;
4128         uint8_t vc_id = 1; /// VC ID always 1 for SST
4129         struct dc_link_settings link_settings = pipe_ctx->link_config.dp_link_settings;
4130         const struct link_hwss *link_hwss = get_link_hwss(stream->link, &pipe_ctx->link_res);
4131         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
4132
4133         stream->link->cur_link_settings = link_settings;
4134
4135         if (link_hwss->ext.enable_dp_link_output)
4136                 link_hwss->ext.enable_dp_link_output(stream->link, &pipe_ctx->link_res,
4137                                 stream->signal, pipe_ctx->clock_source->id,
4138                                 &link_settings);
4139
4140 #ifdef DIAGS_BUILD
4141         /* Workaround for FPGA HPO capture DP link data:
4142          * HPO capture will set link to active mode
4143          * This workaround is required to get a capture from start of frame
4144          */
4145         if (!dc->debug.fpga_hpo_capture_en) {
4146                 struct encoder_set_dp_phy_pattern_param params = {0};
4147                 params.dp_phy_pattern = DP_TEST_PATTERN_VIDEO_MODE;
4148
4149                 /* Set link active */
4150                 stream->link->hpo_dp_link_enc->funcs->set_link_test_pattern(
4151                                 stream->link->hpo_dp_link_enc,
4152                                 &params);
4153         }
4154 #endif
4155
4156         /* Enable DP_STREAM_ENC */
4157         dc->hwss.enable_stream(pipe_ctx);
4158
4159         /* Set DPS PPS SDP (AKA "info frames") */
4160         if (pipe_ctx->stream->timing.flags.DSC) {
4161                 dp_set_dsc_pps_sdp(pipe_ctx, true, true);
4162         }
4163
4164         /* Allocate Payload */
4165         if ((stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) && (state->stream_count > 1)) {
4166                 // MST case
4167                 uint8_t i;
4168
4169                 proposed_table.stream_count = state->stream_count;
4170                 for (i = 0; i < state->stream_count; i++) {
4171                         avg_time_slots_per_mtp = calculate_sst_avg_time_slots_per_mtp(state->streams[i], state->streams[i]->link);
4172                         req_slot_count = dc_fixpt_ceil(avg_time_slots_per_mtp);
4173                         proposed_table.stream_allocations[i].slot_count = req_slot_count;
4174                         proposed_table.stream_allocations[i].vcp_id = i+1;
4175                         /* NOTE: This makes assumption that pipe_ctx index is same as stream index */
4176                         proposed_table.stream_allocations[i].hpo_dp_stream_enc = state->res_ctx.pipe_ctx[i].stream_res.hpo_dp_stream_enc;
4177                 }
4178         } else {
4179                 // SST case
4180                 avg_time_slots_per_mtp = calculate_sst_avg_time_slots_per_mtp(stream, stream->link);
4181                 req_slot_count = dc_fixpt_ceil(avg_time_slots_per_mtp);
4182                 proposed_table.stream_count = 1; /// Always 1 stream for SST
4183                 proposed_table.stream_allocations[0].slot_count = req_slot_count;
4184                 proposed_table.stream_allocations[0].vcp_id = vc_id;
4185                 proposed_table.stream_allocations[0].hpo_dp_stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc;
4186         }
4187
4188         link_hwss->ext.update_stream_allocation_table(stream->link,
4189                         &pipe_ctx->link_res,
4190                         &proposed_table);
4191
4192         if (link_hwss->ext.set_throttled_vcp_size)
4193                 link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp);
4194
4195         dc->hwss.unblank_stream(pipe_ctx, &stream->link->cur_link_settings);
4196 }
4197
4198 void core_link_enable_stream(
4199                 struct dc_state *state,
4200                 struct pipe_ctx *pipe_ctx)
4201 {
4202         struct dc *dc = pipe_ctx->stream->ctx->dc;
4203         struct dc_stream_state *stream = pipe_ctx->stream;
4204         struct dc_link *link = stream->sink->link;
4205         enum dc_status status;
4206         struct link_encoder *link_enc;
4207         enum otg_out_mux_dest otg_out_dest = OUT_MUX_DIO;
4208         struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg;
4209         const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
4210
4211         if (is_dp_128b_132b_signal(pipe_ctx))
4212                 vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg;
4213
4214         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
4215
4216         if (pipe_ctx->stream->sink) {
4217                 if (pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&
4218                         pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_NONE) {
4219                         DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x\n", __func__,
4220                         pipe_ctx->stream->sink->edid_caps.display_name,
4221                         pipe_ctx->stream->signal);
4222                 }
4223         }
4224
4225         if (!IS_DIAG_DC(dc->ctx->dce_environment) &&
4226                         dc_is_virtual_signal(pipe_ctx->stream->signal))
4227                 return;
4228
4229         link_enc = link_enc_cfg_get_link_enc(link);
4230         ASSERT(link_enc);
4231
4232         if (!dc_is_virtual_signal(pipe_ctx->stream->signal)
4233                         && !is_dp_128b_132b_signal(pipe_ctx)) {
4234                 if (link_enc)
4235                         link_enc->funcs->setup(
4236                                 link_enc,
4237                                 pipe_ctx->stream->signal);
4238         }
4239
4240         pipe_ctx->stream->link->link_state_valid = true;
4241
4242         if (pipe_ctx->stream_res.tg->funcs->set_out_mux) {
4243                 if (is_dp_128b_132b_signal(pipe_ctx))
4244                         otg_out_dest = OUT_MUX_HPO_DP;
4245                 else
4246                         otg_out_dest = OUT_MUX_DIO;
4247                 pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, otg_out_dest);
4248         }
4249
4250         link_hwss->setup_stream_attribute(pipe_ctx);
4251
4252         if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
4253                 bool apply_edp_fast_boot_optimization =
4254                         pipe_ctx->stream->apply_edp_fast_boot_optimization;
4255
4256                 pipe_ctx->stream->apply_edp_fast_boot_optimization = false;
4257
4258                 // Enable VPG before building infoframe
4259                 if (vpg && vpg->funcs->vpg_poweron)
4260                         vpg->funcs->vpg_poweron(vpg);
4261
4262                 resource_build_info_frame(pipe_ctx);
4263                 dc->hwss.update_info_frame(pipe_ctx);
4264
4265                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
4266                         dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME);
4267
4268                 /* Do not touch link on seamless boot optimization. */
4269                 if (pipe_ctx->stream->apply_seamless_boot_optimization) {
4270                         pipe_ctx->stream->dpms_off = false;
4271
4272                         /* Still enable stream features & audio on seamless boot for DP external displays */
4273                         if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT) {
4274                                 enable_stream_features(pipe_ctx);
4275                                 if (pipe_ctx->stream_res.audio != NULL) {
4276                                         pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc);
4277                                         dc->hwss.enable_audio_stream(pipe_ctx);
4278                                 }
4279                         }
4280
4281 #if defined(CONFIG_DRM_AMD_DC_HDCP)
4282                         update_psp_stream_config(pipe_ctx, false);
4283 #endif
4284                         return;
4285                 }
4286
4287                 /* eDP lit up by bios already, no need to enable again. */
4288                 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&
4289                                         apply_edp_fast_boot_optimization &&
4290                                         !pipe_ctx->stream->timing.flags.DSC &&
4291                                         !pipe_ctx->next_odm_pipe) {
4292                         pipe_ctx->stream->dpms_off = false;
4293 #if defined(CONFIG_DRM_AMD_DC_HDCP)
4294                         update_psp_stream_config(pipe_ctx, false);
4295 #endif
4296                         return;
4297                 }
4298
4299                 if (pipe_ctx->stream->dpms_off)
4300                         return;
4301
4302                 status = enable_link(state, pipe_ctx);
4303
4304                 if (status != DC_OK) {
4305                         DC_LOG_WARNING("enabling link %u failed: %d\n",
4306                         pipe_ctx->stream->link->link_index,
4307                         status);
4308
4309                         /* Abort stream enable *unless* the failure was due to
4310                          * DP link training - some DP monitors will recover and
4311                          * show the stream anyway. But MST displays can't proceed
4312                          * without link training.
4313                          */
4314                         if (status != DC_FAIL_DP_LINK_TRAINING ||
4315                                         pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
4316                                 if (false == stream->link->link_status.link_active)
4317                                         disable_link(stream->link, &pipe_ctx->link_res,
4318                                                         pipe_ctx->stream->signal);
4319                                 BREAK_TO_DEBUGGER();
4320                                 return;
4321                         }
4322                 }
4323
4324                 /* turn off otg test pattern if enable */
4325                 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
4326                         pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
4327                                         CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
4328                                         COLOR_DEPTH_UNDEFINED);
4329
4330                 /* This second call is needed to reconfigure the DIG
4331                  * as a workaround for the incorrect value being applied
4332                  * from transmitter control.
4333                  */
4334                 if (!(dc_is_virtual_signal(pipe_ctx->stream->signal) ||
4335                                 is_dp_128b_132b_signal(pipe_ctx)))
4336                         if (link_enc)
4337                                 link_enc->funcs->setup(
4338                                         link_enc,
4339                                         pipe_ctx->stream->signal);
4340
4341                 dc->hwss.enable_stream(pipe_ctx);
4342
4343                 /* Set DPS PPS SDP (AKA "info frames") */
4344                 if (pipe_ctx->stream->timing.flags.DSC) {
4345                         if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
4346                                         dc_is_virtual_signal(pipe_ctx->stream->signal)) {
4347                                 dp_set_dsc_on_rx(pipe_ctx, true);
4348                                 dp_set_dsc_pps_sdp(pipe_ctx, true, true);
4349                         }
4350                 }
4351
4352                 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
4353                         dc_link_allocate_mst_payload(pipe_ctx);
4354                 else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT &&
4355                                 is_dp_128b_132b_signal(pipe_ctx))
4356                         dc_link_update_sst_payload(pipe_ctx, true);
4357
4358                 dc->hwss.unblank_stream(pipe_ctx,
4359                         &pipe_ctx->stream->link->cur_link_settings);
4360
4361                 if (stream->sink_patches.delay_ignore_msa > 0)
4362                         msleep(stream->sink_patches.delay_ignore_msa);
4363
4364                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
4365                         enable_stream_features(pipe_ctx);
4366 #if defined(CONFIG_DRM_AMD_DC_HDCP)
4367                 update_psp_stream_config(pipe_ctx, false);
4368 #endif
4369
4370                 dc->hwss.enable_audio_stream(pipe_ctx);
4371
4372         } else { // if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
4373                 if (is_dp_128b_132b_signal(pipe_ctx))
4374                         fpga_dp_hpo_enable_link_and_stream(state, pipe_ctx);
4375                 if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
4376                                 dc_is_virtual_signal(pipe_ctx->stream->signal))
4377                         dp_set_dsc_enable(pipe_ctx, true);
4378         }
4379
4380         if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
4381                 core_link_set_avmute(pipe_ctx, false);
4382         }
4383 }
4384
4385 void core_link_disable_stream(struct pipe_ctx *pipe_ctx)
4386 {
4387         struct dc  *dc = pipe_ctx->stream->ctx->dc;
4388         struct dc_stream_state *stream = pipe_ctx->stream;
4389         struct dc_link *link = stream->sink->link;
4390         struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg;
4391
4392         if (is_dp_128b_132b_signal(pipe_ctx))
4393                 vpg = pipe_ctx->stream_res.hpo_dp_stream_enc->vpg;
4394
4395         DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
4396
4397         if (pipe_ctx->stream->sink) {
4398                 if (pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&
4399                         pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_NONE) {
4400                         DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x\n", __func__,
4401                         pipe_ctx->stream->sink->edid_caps.display_name,
4402                         pipe_ctx->stream->signal);
4403                 }
4404         }
4405
4406         if (!IS_DIAG_DC(dc->ctx->dce_environment) &&
4407                         dc_is_virtual_signal(pipe_ctx->stream->signal))
4408                 return;
4409
4410         if (!pipe_ctx->stream->sink->edid_caps.panel_patch.skip_avmute) {
4411                 if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
4412                         core_link_set_avmute(pipe_ctx, true);
4413         }
4414
4415         dc->hwss.disable_audio_stream(pipe_ctx);
4416
4417 #if defined(CONFIG_DRM_AMD_DC_HDCP)
4418         update_psp_stream_config(pipe_ctx, true);
4419 #endif
4420         dc->hwss.blank_stream(pipe_ctx);
4421
4422         if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
4423                 deallocate_mst_payload(pipe_ctx);
4424         else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT &&
4425                         is_dp_128b_132b_signal(pipe_ctx))
4426                 dc_link_update_sst_payload(pipe_ctx, false);
4427
4428         if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
4429                 struct ext_hdmi_settings settings = {0};
4430                 enum engine_id eng_id = pipe_ctx->stream_res.stream_enc->id;
4431
4432                 unsigned short masked_chip_caps = link->chip_caps &
4433                                 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
4434                 //Need to inform that sink is going to use legacy HDMI mode.
4435                 dal_ddc_service_write_scdc_data(
4436                         link->ddc,
4437                         165000,//vbios only handles 165Mhz.
4438                         false);
4439                 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {
4440                         /* DP159, Retimer settings */
4441                         if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings))
4442                                 write_i2c_retimer_setting(pipe_ctx,
4443                                                 false, false, &settings);
4444                         else
4445                                 write_i2c_default_retimer_setting(pipe_ctx,
4446                                                 false, false);
4447                 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {
4448                         /* PI3EQX1204, Redriver settings */
4449                         write_i2c_redriver_setting(pipe_ctx, false);
4450                 }
4451         }
4452
4453         if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT &&
4454                         !is_dp_128b_132b_signal(pipe_ctx)) {
4455
4456                 /* In DP1.x SST mode, our encoder will go to TPS1
4457                  * when link is on but stream is off.
4458                  * Disabling link before stream will avoid exposing TPS1 pattern
4459                  * during the disable sequence as it will confuse some receivers
4460                  * state machine.
4461                  * In DP2 or MST mode, our encoder will stay video active
4462                  */
4463                 disable_link(pipe_ctx->stream->link, &pipe_ctx->link_res, pipe_ctx->stream->signal);
4464                 dc->hwss.disable_stream(pipe_ctx);
4465         } else {
4466                 dc->hwss.disable_stream(pipe_ctx);
4467                 disable_link(pipe_ctx->stream->link, &pipe_ctx->link_res, pipe_ctx->stream->signal);
4468         }
4469
4470         if (pipe_ctx->stream->timing.flags.DSC) {
4471                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
4472                         dp_set_dsc_enable(pipe_ctx, false);
4473         }
4474         if (is_dp_128b_132b_signal(pipe_ctx)) {
4475                 if (pipe_ctx->stream_res.tg->funcs->set_out_mux)
4476                         pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, OUT_MUX_DIO);
4477         }
4478
4479         if (vpg && vpg->funcs->vpg_powerdown)
4480                 vpg->funcs->vpg_powerdown(vpg);
4481 }
4482
4483 void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
4484 {
4485         struct dc  *dc = pipe_ctx->stream->ctx->dc;
4486
4487         if (!dc_is_hdmi_signal(pipe_ctx->stream->signal))
4488                 return;
4489
4490         dc->hwss.set_avmute(pipe_ctx, enable);
4491 }
4492
4493 /**
4494  *  dc_link_enable_hpd_filter:
4495  *     If enable is true, programs HPD filter on associated HPD line using
4496  *     delay_on_disconnect/delay_on_connect values dependent on
4497  *     link->connector_signal
4498  *
4499  *     If enable is false, programs HPD filter on associated HPD line with no
4500  *     delays on connect or disconnect
4501  *
4502  *  @link:   pointer to the dc link
4503  *  @enable: boolean specifying whether to enable hbd
4504  */
4505 void dc_link_enable_hpd_filter(struct dc_link *link, bool enable)
4506 {
4507         struct gpio *hpd;
4508
4509         if (enable) {
4510                 link->is_hpd_filter_disabled = false;
4511                 program_hpd_filter(link);
4512         } else {
4513                 link->is_hpd_filter_disabled = true;
4514                 /* Obtain HPD handle */
4515                 hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
4516
4517                 if (!hpd)
4518                         return;
4519
4520                 /* Setup HPD filtering */
4521                 if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) {
4522                         struct gpio_hpd_config config;
4523
4524                         config.delay_on_connect = 0;
4525                         config.delay_on_disconnect = 0;
4526
4527                         dal_irq_setup_hpd_filter(hpd, &config);
4528
4529                         dal_gpio_close(hpd);
4530                 } else {
4531                         ASSERT_CRITICAL(false);
4532                 }
4533                 /* Release HPD handle */
4534                 dal_gpio_destroy_irq(&hpd);
4535         }
4536 }
4537
4538 void dc_link_set_drive_settings(struct dc *dc,
4539                                 struct link_training_settings *lt_settings,
4540                                 const struct dc_link *link)
4541 {
4542
4543         int i;
4544         struct link_resource link_res;
4545
4546         for (i = 0; i < dc->link_count; i++)
4547                 if (dc->links[i] == link)
4548                         break;
4549
4550         if (i >= dc->link_count)
4551                 ASSERT_CRITICAL(false);
4552
4553         dc_link_get_cur_link_res(link, &link_res);
4554         dc_link_dp_set_drive_settings(dc->links[i], &link_res, lt_settings);
4555 }
4556
4557 void dc_link_set_preferred_link_settings(struct dc *dc,
4558                                          struct dc_link_settings *link_setting,
4559                                          struct dc_link *link)
4560 {
4561         int i;
4562         struct pipe_ctx *pipe;
4563         struct dc_stream_state *link_stream;
4564         struct dc_link_settings store_settings = *link_setting;
4565
4566         link->preferred_link_setting = store_settings;
4567
4568         /* Retrain with preferred link settings only relevant for
4569          * DP signal type
4570          * Check for non-DP signal or if passive dongle present
4571          */
4572         if (!dc_is_dp_signal(link->connector_signal) ||
4573                 link->dongle_max_pix_clk > 0)
4574                 return;
4575
4576         for (i = 0; i < MAX_PIPES; i++) {
4577                 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
4578                 if (pipe->stream && pipe->stream->link) {
4579                         if (pipe->stream->link == link) {
4580                                 link_stream = pipe->stream;
4581                                 break;
4582                         }
4583                 }
4584         }
4585
4586         /* Stream not found */
4587         if (i == MAX_PIPES)
4588                 return;
4589
4590         /* Cannot retrain link if backend is off */
4591         if (link_stream->dpms_off)
4592                 return;
4593
4594         if (decide_link_settings(link_stream, &store_settings))
4595                 dp_retrain_link_dp_test(link, &store_settings, false);
4596 }
4597
4598 void dc_link_set_preferred_training_settings(struct dc *dc,
4599                                                  struct dc_link_settings *link_setting,
4600                                                  struct dc_link_training_overrides *lt_overrides,
4601                                                  struct dc_link *link,
4602                                                  bool skip_immediate_retrain)
4603 {
4604         if (lt_overrides != NULL)
4605                 link->preferred_training_settings = *lt_overrides;
4606         else
4607                 memset(&link->preferred_training_settings, 0, sizeof(link->preferred_training_settings));
4608
4609         if (link_setting != NULL) {
4610                 link->preferred_link_setting = *link_setting;
4611                 if (dp_get_link_encoding_format(link_setting) == DP_128b_132b_ENCODING)
4612                         /* TODO: add dc update for acquiring link res  */
4613                         skip_immediate_retrain = true;
4614         } else {
4615                 link->preferred_link_setting.lane_count = LANE_COUNT_UNKNOWN;
4616                 link->preferred_link_setting.link_rate = LINK_RATE_UNKNOWN;
4617         }
4618
4619         /* Retrain now, or wait until next stream update to apply */
4620         if (skip_immediate_retrain == false)
4621                 dc_link_set_preferred_link_settings(dc, &link->preferred_link_setting, link);
4622 }
4623
4624 void dc_link_enable_hpd(const struct dc_link *link)
4625 {
4626         dc_link_dp_enable_hpd(link);
4627 }
4628
4629 void dc_link_disable_hpd(const struct dc_link *link)
4630 {
4631         dc_link_dp_disable_hpd(link);
4632 }
4633
4634 void dc_link_set_test_pattern(struct dc_link *link,
4635                               enum dp_test_pattern test_pattern,
4636                               enum dp_test_pattern_color_space test_pattern_color_space,
4637                               const struct link_training_settings *p_link_settings,
4638                               const unsigned char *p_custom_pattern,
4639                               unsigned int cust_pattern_size)
4640 {
4641         if (link != NULL)
4642                 dc_link_dp_set_test_pattern(
4643                         link,
4644                         test_pattern,
4645                         test_pattern_color_space,
4646                         p_link_settings,
4647                         p_custom_pattern,
4648                         cust_pattern_size);
4649 }
4650
4651 uint32_t dc_link_bandwidth_kbps(
4652         const struct dc_link *link,
4653         const struct dc_link_settings *link_setting)
4654 {
4655         uint32_t total_data_bw_efficiency_x10000 = 0;
4656         uint32_t link_rate_per_lane_kbps = 0;
4657
4658         switch (dp_get_link_encoding_format(link_setting)) {
4659         case DP_8b_10b_ENCODING:
4660                 /* For 8b/10b encoding:
4661                  * link rate is defined in the unit of LINK_RATE_REF_FREQ_IN_KHZ per DP byte per lane.
4662                  * data bandwidth efficiency is 80% with additional 3% overhead if FEC is supported.
4663                  */
4664                 link_rate_per_lane_kbps = link_setting->link_rate * LINK_RATE_REF_FREQ_IN_KHZ * BITS_PER_DP_BYTE;
4665                 total_data_bw_efficiency_x10000 = DATA_EFFICIENCY_8b_10b_x10000;
4666                 if (dc_link_should_enable_fec(link)) {
4667                         total_data_bw_efficiency_x10000 /= 100;
4668                         total_data_bw_efficiency_x10000 *= DATA_EFFICIENCY_8b_10b_FEC_EFFICIENCY_x100;
4669                 }
4670                 break;
4671         case DP_128b_132b_ENCODING:
4672                 /* For 128b/132b encoding:
4673                  * link rate is defined in the unit of 10mbps per lane.
4674                  * total data bandwidth efficiency is always 96.71%.
4675                  */
4676                 link_rate_per_lane_kbps = link_setting->link_rate * 10000;
4677                 total_data_bw_efficiency_x10000 = DATA_EFFICIENCY_128b_132b_x10000;
4678                 break;
4679         default:
4680                 break;
4681         }
4682
4683         /* overall effective link bandwidth = link rate per lane * lane count * total data bandwidth efficiency */
4684         return link_rate_per_lane_kbps * link_setting->lane_count / 10000 * total_data_bw_efficiency_x10000;
4685 }
4686
4687 const struct dc_link_settings *dc_link_get_link_cap(
4688                 const struct dc_link *link)
4689 {
4690         if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN &&
4691                         link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN)
4692                 return &link->preferred_link_setting;
4693         return &link->verified_link_cap;
4694 }
4695
4696 void dc_link_overwrite_extended_receiver_cap(
4697                 struct dc_link *link)
4698 {
4699         dp_overwrite_extended_receiver_cap(link);
4700 }
4701
4702 bool dc_link_is_fec_supported(const struct dc_link *link)
4703 {
4704         /* TODO - use asic cap instead of link_enc->features
4705          * we no longer know which link enc to use for this link before commit
4706          */
4707         struct link_encoder *link_enc = NULL;
4708
4709         link_enc = link_enc_cfg_get_link_enc(link);
4710         ASSERT(link_enc);
4711
4712         return (dc_is_dp_signal(link->connector_signal) && link_enc &&
4713                         link_enc->features.fec_supported &&
4714                         link->dpcd_caps.fec_cap.bits.FEC_CAPABLE &&
4715                         !IS_FPGA_MAXIMUS_DC(link->ctx->dce_environment));
4716 }
4717
4718 bool dc_link_should_enable_fec(const struct dc_link *link)
4719 {
4720         bool force_disable = false;
4721
4722         if (link->fec_state == dc_link_fec_enabled)
4723                 force_disable = false;
4724         else if (link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT_MST &&
4725                         link->local_sink &&
4726                         link->local_sink->edid_caps.panel_patch.disable_fec)
4727                 force_disable = true;
4728         else if (link->connector_signal == SIGNAL_TYPE_EDP
4729                         && (link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.
4730                          dsc_support.DSC_SUPPORT == false
4731                                 || link->panel_config.dsc.disable_dsc_edp
4732                                 || !link->dc->caps.edp_dsc_support))
4733                 force_disable = true;
4734
4735         return !force_disable && dc_link_is_fec_supported(link);
4736 }
4737
4738 uint32_t dc_bandwidth_in_kbps_from_timing(
4739                 const struct dc_crtc_timing *timing)
4740 {
4741         uint32_t bits_per_channel = 0;
4742         uint32_t kbps;
4743
4744 #if defined(CONFIG_DRM_AMD_DC_DCN)
4745         if (timing->flags.DSC)
4746                 return dc_dsc_stream_bandwidth_in_kbps(timing,
4747                                 timing->dsc_cfg.bits_per_pixel,
4748                                 timing->dsc_cfg.num_slices_h,
4749                                 timing->dsc_cfg.is_dp);
4750 #endif /* CONFIG_DRM_AMD_DC_DCN */
4751
4752         switch (timing->display_color_depth) {
4753         case COLOR_DEPTH_666:
4754                 bits_per_channel = 6;
4755                 break;
4756         case COLOR_DEPTH_888:
4757                 bits_per_channel = 8;
4758                 break;
4759         case COLOR_DEPTH_101010:
4760                 bits_per_channel = 10;
4761                 break;
4762         case COLOR_DEPTH_121212:
4763                 bits_per_channel = 12;
4764                 break;
4765         case COLOR_DEPTH_141414:
4766                 bits_per_channel = 14;
4767                 break;
4768         case COLOR_DEPTH_161616:
4769                 bits_per_channel = 16;
4770                 break;
4771         default:
4772                 ASSERT(bits_per_channel != 0);
4773                 bits_per_channel = 8;
4774                 break;
4775         }
4776
4777         kbps = timing->pix_clk_100hz / 10;
4778         kbps *= bits_per_channel;
4779
4780         if (timing->flags.Y_ONLY != 1) {
4781                 /*Only YOnly make reduce bandwidth by 1/3 compares to RGB*/
4782                 kbps *= 3;
4783                 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
4784                         kbps /= 2;
4785                 else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
4786                         kbps = kbps * 2 / 3;
4787         }
4788
4789         return kbps;
4790
4791 }
4792
4793 void dc_link_get_cur_link_res(const struct dc_link *link,
4794                 struct link_resource *link_res)
4795 {
4796         int i;
4797         struct pipe_ctx *pipe = NULL;
4798
4799         memset(link_res, 0, sizeof(*link_res));
4800
4801         for (i = 0; i < MAX_PIPES; i++) {
4802                 pipe = &link->dc->current_state->res_ctx.pipe_ctx[i];
4803                 if (pipe->stream && pipe->stream->link && pipe->top_pipe == NULL) {
4804                         if (pipe->stream->link == link) {
4805                                 *link_res = pipe->link_res;
4806                                 break;
4807                         }
4808                 }
4809         }
4810
4811 }
4812
4813 /**
4814  * dc_get_cur_link_res_map() - take a snapshot of current link resource allocation state
4815  * @dc: pointer to dc of the dm calling this
4816  * @map: a dc link resource snapshot defined internally to dc.
4817  *
4818  * DM needs to capture a snapshot of current link resource allocation mapping
4819  * and store it in its persistent storage.
4820  *
4821  * Some of the link resource is using first come first serve policy.
4822  * The allocation mapping depends on original hotplug order. This information
4823  * is lost after driver is loaded next time. The snapshot is used in order to
4824  * restore link resource to its previous state so user will get consistent
4825  * link capability allocation across reboot.
4826  *
4827  * Return: none (void function)
4828  *
4829  */
4830 void dc_get_cur_link_res_map(const struct dc *dc, uint32_t *map)
4831 {
4832         struct dc_link *link;
4833         uint32_t i;
4834         uint32_t hpo_dp_recycle_map = 0;
4835
4836         *map = 0;
4837
4838         if (dc->caps.dp_hpo) {
4839                 for (i = 0; i < dc->caps.max_links; i++) {
4840                         link = dc->links[i];
4841                         if (link->link_status.link_active &&
4842                                         dp_get_link_encoding_format(&link->reported_link_cap) == DP_128b_132b_ENCODING &&
4843                                         dp_get_link_encoding_format(&link->cur_link_settings) != DP_128b_132b_ENCODING)
4844                                 /* hpo dp link encoder is considered as recycled, when RX reports 128b/132b encoding capability
4845                                  * but current link doesn't use it.
4846                                  */
4847                                 hpo_dp_recycle_map |= (1 << i);
4848                 }
4849                 *map |= (hpo_dp_recycle_map << LINK_RES_HPO_DP_REC_MAP__SHIFT);
4850         }
4851 }
4852
4853 /**
4854  * dc_restore_link_res_map() - restore link resource allocation state from a snapshot
4855  * @dc: pointer to dc of the dm calling this
4856  * @map: a dc link resource snapshot defined internally to dc.
4857  *
4858  * DM needs to call this function after initial link detection on boot and
4859  * before first commit streams to restore link resource allocation state
4860  * from previous boot session.
4861  *
4862  * Some of the link resource is using first come first serve policy.
4863  * The allocation mapping depends on original hotplug order. This information
4864  * is lost after driver is loaded next time. The snapshot is used in order to
4865  * restore link resource to its previous state so user will get consistent
4866  * link capability allocation across reboot.
4867  *
4868  * Return: none (void function)
4869  *
4870  */
4871 void dc_restore_link_res_map(const struct dc *dc, uint32_t *map)
4872 {
4873         struct dc_link *link;
4874         uint32_t i;
4875         unsigned int available_hpo_dp_count;
4876         uint32_t hpo_dp_recycle_map = (*map & LINK_RES_HPO_DP_REC_MAP__MASK)
4877                         >> LINK_RES_HPO_DP_REC_MAP__SHIFT;
4878
4879         if (dc->caps.dp_hpo) {
4880                 available_hpo_dp_count = dc->res_pool->hpo_dp_link_enc_count;
4881                 /* remove excess 128b/132b encoding support for not recycled links */
4882                 for (i = 0; i < dc->caps.max_links; i++) {
4883                         if ((hpo_dp_recycle_map & (1 << i)) == 0) {
4884                                 link = dc->links[i];
4885                                 if (link->type != dc_connection_none &&
4886                                                 dp_get_link_encoding_format(&link->verified_link_cap) == DP_128b_132b_ENCODING) {
4887                                         if (available_hpo_dp_count > 0)
4888                                                 available_hpo_dp_count--;
4889                                         else
4890                                                 /* remove 128b/132b encoding capability by limiting verified link rate to HBR3 */
4891                                                 link->verified_link_cap.link_rate = LINK_RATE_HIGH3;
4892                                 }
4893                         }
4894                 }
4895                 /* remove excess 128b/132b encoding support for recycled links */
4896                 for (i = 0; i < dc->caps.max_links; i++) {
4897                         if ((hpo_dp_recycle_map & (1 << i)) != 0) {
4898                                 link = dc->links[i];
4899                                 if (link->type != dc_connection_none &&
4900                                                 dp_get_link_encoding_format(&link->verified_link_cap) == DP_128b_132b_ENCODING) {
4901                                         if (available_hpo_dp_count > 0)
4902                                                 available_hpo_dp_count--;
4903                                         else
4904                                                 /* remove 128b/132b encoding capability by limiting verified link rate to HBR3 */
4905                                                 link->verified_link_cap.link_rate = LINK_RATE_HIGH3;
4906                                 }
4907                         }
4908                 }
4909         }
4910 }