4 * Created on: Nov 3, 2016
8 #include "dm_services.h"
12 #include "core_status.h"
13 #include "core_types.h"
14 #include "hw_sequencer.h"
18 #define SURFACE_TRACE(...) do {\
19 if (dc->debug.surface_trace) \
20 dm_logger_write(logger, \
25 #define TIMING_TRACE(...) do {\
26 if (dc->debug.timing_trace) \
27 dm_logger_write(logger, \
32 #define CLOCK_TRACE(...) do {\
33 if (dc->debug.clock_trace) \
34 dm_logger_write(logger, \
35 LOG_BANDWIDTH_CALCS, \
39 void pre_surface_trace(
41 const struct dc_plane_state *const *plane_states,
45 struct dc *core_dc = dc;
46 struct dal_logger *logger = core_dc->ctx->logger;
48 for (i = 0; i < surface_count; i++) {
49 const struct dc_plane_state *plane_state = plane_states[i];
51 SURFACE_TRACE("Planes %d:\n", i);
54 "plane_state->visible = %d;\n"
55 "plane_state->flip_immediate = %d;\n"
56 "plane_state->address.type = %d;\n"
57 "plane_state->address.grph.addr.quad_part = 0x%X;\n"
58 "plane_state->address.grph.meta_addr.quad_part = 0x%X;\n"
59 "plane_state->scaling_quality.h_taps = %d;\n"
60 "plane_state->scaling_quality.v_taps = %d;\n"
61 "plane_state->scaling_quality.h_taps_c = %d;\n"
62 "plane_state->scaling_quality.v_taps_c = %d;\n",
64 plane_state->flip_immediate,
65 plane_state->address.type,
66 plane_state->address.grph.addr.quad_part,
67 plane_state->address.grph.meta_addr.quad_part,
68 plane_state->scaling_quality.h_taps,
69 plane_state->scaling_quality.v_taps,
70 plane_state->scaling_quality.h_taps_c,
71 plane_state->scaling_quality.v_taps_c);
74 "plane_state->src_rect.x = %d;\n"
75 "plane_state->src_rect.y = %d;\n"
76 "plane_state->src_rect.width = %d;\n"
77 "plane_state->src_rect.height = %d;\n"
78 "plane_state->dst_rect.x = %d;\n"
79 "plane_state->dst_rect.y = %d;\n"
80 "plane_state->dst_rect.width = %d;\n"
81 "plane_state->dst_rect.height = %d;\n"
82 "plane_state->clip_rect.x = %d;\n"
83 "plane_state->clip_rect.y = %d;\n"
84 "plane_state->clip_rect.width = %d;\n"
85 "plane_state->clip_rect.height = %d;\n",
86 plane_state->src_rect.x,
87 plane_state->src_rect.y,
88 plane_state->src_rect.width,
89 plane_state->src_rect.height,
90 plane_state->dst_rect.x,
91 plane_state->dst_rect.y,
92 plane_state->dst_rect.width,
93 plane_state->dst_rect.height,
94 plane_state->clip_rect.x,
95 plane_state->clip_rect.y,
96 plane_state->clip_rect.width,
97 plane_state->clip_rect.height);
100 "plane_state->plane_size.grph.surface_size.x = %d;\n"
101 "plane_state->plane_size.grph.surface_size.y = %d;\n"
102 "plane_state->plane_size.grph.surface_size.width = %d;\n"
103 "plane_state->plane_size.grph.surface_size.height = %d;\n"
104 "plane_state->plane_size.grph.surface_pitch = %d;\n",
105 plane_state->plane_size.grph.surface_size.x,
106 plane_state->plane_size.grph.surface_size.y,
107 plane_state->plane_size.grph.surface_size.width,
108 plane_state->plane_size.grph.surface_size.height,
109 plane_state->plane_size.grph.surface_pitch);
113 "plane_state->tiling_info.gfx8.num_banks = %d;\n"
114 "plane_state->tiling_info.gfx8.bank_width = %d;\n"
115 "plane_state->tiling_info.gfx8.bank_width_c = %d;\n"
116 "plane_state->tiling_info.gfx8.bank_height = %d;\n"
117 "plane_state->tiling_info.gfx8.bank_height_c = %d;\n"
118 "plane_state->tiling_info.gfx8.tile_aspect = %d;\n"
119 "plane_state->tiling_info.gfx8.tile_aspect_c = %d;\n"
120 "plane_state->tiling_info.gfx8.tile_split = %d;\n"
121 "plane_state->tiling_info.gfx8.tile_split_c = %d;\n"
122 "plane_state->tiling_info.gfx8.tile_mode = %d;\n"
123 "plane_state->tiling_info.gfx8.tile_mode_c = %d;\n",
124 plane_state->tiling_info.gfx8.num_banks,
125 plane_state->tiling_info.gfx8.bank_width,
126 plane_state->tiling_info.gfx8.bank_width_c,
127 plane_state->tiling_info.gfx8.bank_height,
128 plane_state->tiling_info.gfx8.bank_height_c,
129 plane_state->tiling_info.gfx8.tile_aspect,
130 plane_state->tiling_info.gfx8.tile_aspect_c,
131 plane_state->tiling_info.gfx8.tile_split,
132 plane_state->tiling_info.gfx8.tile_split_c,
133 plane_state->tiling_info.gfx8.tile_mode,
134 plane_state->tiling_info.gfx8.tile_mode_c);
137 "plane_state->tiling_info.gfx8.pipe_config = %d;\n"
138 "plane_state->tiling_info.gfx8.array_mode = %d;\n"
139 "plane_state->color_space = %d;\n"
140 "plane_state->dcc.enable = %d;\n"
141 "plane_state->format = %d;\n"
142 "plane_state->rotation = %d;\n"
143 "plane_state->stereo_format = %d;\n",
144 plane_state->tiling_info.gfx8.pipe_config,
145 plane_state->tiling_info.gfx8.array_mode,
146 plane_state->color_space,
147 plane_state->dcc.enable,
149 plane_state->rotation,
150 plane_state->stereo_format);
152 SURFACE_TRACE("plane_state->tiling_info.gfx9.swizzle = %d;\n",
153 plane_state->tiling_info.gfx9.swizzle);
160 void update_surface_trace(
162 const struct dc_surface_update *updates,
166 struct dc *core_dc = dc;
167 struct dal_logger *logger = core_dc->ctx->logger;
169 for (i = 0; i < surface_count; i++) {
170 const struct dc_surface_update *update = &updates[i];
172 SURFACE_TRACE("Update %d\n", i);
173 if (update->flip_addr) {
174 SURFACE_TRACE("flip_addr->address.type = %d;\n"
175 "flip_addr->address.grph.addr.quad_part = 0x%X;\n"
176 "flip_addr->address.grph.meta_addr.quad_part = 0x%X;\n"
177 "flip_addr->flip_immediate = %d;\n",
178 update->flip_addr->address.type,
179 update->flip_addr->address.grph.addr.quad_part,
180 update->flip_addr->address.grph.meta_addr.quad_part,
181 update->flip_addr->flip_immediate);
184 if (update->plane_info) {
186 "plane_info->color_space = %d;\n"
187 "plane_info->format = %d;\n"
188 "plane_info->plane_size.grph.surface_pitch = %d;\n"
189 "plane_info->plane_size.grph.surface_size.height = %d;\n"
190 "plane_info->plane_size.grph.surface_size.width = %d;\n"
191 "plane_info->plane_size.grph.surface_size.x = %d;\n"
192 "plane_info->plane_size.grph.surface_size.y = %d;\n"
193 "plane_info->rotation = %d;\n",
194 update->plane_info->color_space,
195 update->plane_info->format,
196 update->plane_info->plane_size.grph.surface_pitch,
197 update->plane_info->plane_size.grph.surface_size.height,
198 update->plane_info->plane_size.grph.surface_size.width,
199 update->plane_info->plane_size.grph.surface_size.x,
200 update->plane_info->plane_size.grph.surface_size.y,
201 update->plane_info->rotation,
202 update->plane_info->stereo_format);
205 "plane_info->tiling_info.gfx8.num_banks = %d;\n"
206 "plane_info->tiling_info.gfx8.bank_width = %d;\n"
207 "plane_info->tiling_info.gfx8.bank_width_c = %d;\n"
208 "plane_info->tiling_info.gfx8.bank_height = %d;\n"
209 "plane_info->tiling_info.gfx8.bank_height_c = %d;\n"
210 "plane_info->tiling_info.gfx8.tile_aspect = %d;\n"
211 "plane_info->tiling_info.gfx8.tile_aspect_c = %d;\n"
212 "plane_info->tiling_info.gfx8.tile_split = %d;\n"
213 "plane_info->tiling_info.gfx8.tile_split_c = %d;\n"
214 "plane_info->tiling_info.gfx8.tile_mode = %d;\n"
215 "plane_info->tiling_info.gfx8.tile_mode_c = %d;\n",
216 update->plane_info->tiling_info.gfx8.num_banks,
217 update->plane_info->tiling_info.gfx8.bank_width,
218 update->plane_info->tiling_info.gfx8.bank_width_c,
219 update->plane_info->tiling_info.gfx8.bank_height,
220 update->plane_info->tiling_info.gfx8.bank_height_c,
221 update->plane_info->tiling_info.gfx8.tile_aspect,
222 update->plane_info->tiling_info.gfx8.tile_aspect_c,
223 update->plane_info->tiling_info.gfx8.tile_split,
224 update->plane_info->tiling_info.gfx8.tile_split_c,
225 update->plane_info->tiling_info.gfx8.tile_mode,
226 update->plane_info->tiling_info.gfx8.tile_mode_c);
229 "plane_info->tiling_info.gfx8.pipe_config = %d;\n"
230 "plane_info->tiling_info.gfx8.array_mode = %d;\n"
231 "plane_info->visible = %d;\n"
232 "plane_info->per_pixel_alpha = %d;\n",
233 update->plane_info->tiling_info.gfx8.pipe_config,
234 update->plane_info->tiling_info.gfx8.array_mode,
235 update->plane_info->visible,
236 update->plane_info->per_pixel_alpha);
238 SURFACE_TRACE("surface->tiling_info.gfx9.swizzle = %d;\n",
239 update->plane_info->tiling_info.gfx9.swizzle);
242 if (update->scaling_info) {
244 "scaling_info->src_rect.x = %d;\n"
245 "scaling_info->src_rect.y = %d;\n"
246 "scaling_info->src_rect.width = %d;\n"
247 "scaling_info->src_rect.height = %d;\n"
248 "scaling_info->dst_rect.x = %d;\n"
249 "scaling_info->dst_rect.y = %d;\n"
250 "scaling_info->dst_rect.width = %d;\n"
251 "scaling_info->dst_rect.height = %d;\n"
252 "scaling_info->clip_rect.x = %d;\n"
253 "scaling_info->clip_rect.y = %d;\n"
254 "scaling_info->clip_rect.width = %d;\n"
255 "scaling_info->clip_rect.height = %d;\n"
256 "scaling_info->scaling_quality.h_taps = %d;\n"
257 "scaling_info->scaling_quality.v_taps = %d;\n"
258 "scaling_info->scaling_quality.h_taps_c = %d;\n"
259 "scaling_info->scaling_quality.v_taps_c = %d;\n",
260 update->scaling_info->src_rect.x,
261 update->scaling_info->src_rect.y,
262 update->scaling_info->src_rect.width,
263 update->scaling_info->src_rect.height,
264 update->scaling_info->dst_rect.x,
265 update->scaling_info->dst_rect.y,
266 update->scaling_info->dst_rect.width,
267 update->scaling_info->dst_rect.height,
268 update->scaling_info->clip_rect.x,
269 update->scaling_info->clip_rect.y,
270 update->scaling_info->clip_rect.width,
271 update->scaling_info->clip_rect.height,
272 update->scaling_info->scaling_quality.h_taps,
273 update->scaling_info->scaling_quality.v_taps,
274 update->scaling_info->scaling_quality.h_taps_c,
275 update->scaling_info->scaling_quality.v_taps_c);
282 void post_surface_trace(struct dc *dc)
284 struct dc *core_dc = dc;
285 struct dal_logger *logger = core_dc->ctx->logger;
287 SURFACE_TRACE("post surface process.\n");
291 void context_timing_trace(
293 struct resource_context *res_ctx)
296 struct dc *core_dc = dc;
297 struct dal_logger *logger = core_dc->ctx->logger;
298 int h_pos[MAX_PIPES], v_pos[MAX_PIPES];
299 struct crtc_position position;
300 unsigned int underlay_idx = core_dc->res_pool->underlay_pipe_index;
303 for (i = 0; i < core_dc->res_pool->pipe_count; i++) {
304 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
305 /* get_position() returns CRTC vertical/horizontal counter
306 * hence not applicable for underlay pipe
308 if (pipe_ctx->stream == NULL
309 || pipe_ctx->pipe_idx == underlay_idx)
312 pipe_ctx->stream_res.tg->funcs->get_position(pipe_ctx->stream_res.tg, &position);
313 h_pos[i] = position.horizontal_count;
314 v_pos[i] = position.vertical_count;
316 for (i = 0; i < core_dc->res_pool->pipe_count; i++) {
317 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
319 if (pipe_ctx->stream == NULL)
322 TIMING_TRACE("OTG_%d H_tot:%d V_tot:%d H_pos:%d V_pos:%d\n",
323 pipe_ctx->stream_res.tg->inst,
324 pipe_ctx->stream->timing.h_total,
325 pipe_ctx->stream->timing.v_total,
330 void context_clock_trace(
332 struct dc_state *context)
334 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
335 struct dc *core_dc = dc;
336 struct dal_logger *logger = core_dc->ctx->logger;
338 CLOCK_TRACE("Current: dispclk_khz:%d dppclk_div:%d dcfclk_khz:%d\n"
339 "dcfclk_deep_sleep_khz:%d fclk_khz:%d\n"
340 "dram_ccm_us:%d min_active_dram_ccm_us:%d\n",
341 context->bw.dcn.calc_clk.dispclk_khz,
342 context->bw.dcn.calc_clk.dppclk_div,
343 context->bw.dcn.calc_clk.dcfclk_khz,
344 context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz,
345 context->bw.dcn.calc_clk.fclk_khz,
346 context->bw.dcn.calc_clk.dram_ccm_us,
347 context->bw.dcn.calc_clk.min_active_dram_ccm_us);
348 CLOCK_TRACE("Calculated: dispclk_khz:%d dppclk_div:%d dcfclk_khz:%d\n"
349 "dcfclk_deep_sleep_khz:%d fclk_khz:%d\n"
350 "dram_ccm_us:%d min_active_dram_ccm_us:%d\n",
351 context->bw.dcn.calc_clk.dispclk_khz,
352 context->bw.dcn.calc_clk.dppclk_div,
353 context->bw.dcn.calc_clk.dcfclk_khz,
354 context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz,
355 context->bw.dcn.calc_clk.fclk_khz,
356 context->bw.dcn.calc_clk.dram_ccm_us,
357 context->bw.dcn.calc_clk.min_active_dram_ccm_us);