2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include "dm_services.h"
29 #include "core_status.h"
30 #include "core_types.h"
31 #include "hw_sequencer.h"
35 #include "clock_source.h"
36 #include "dc_bios_types.h"
38 #include "dce_calcs.h"
39 #include "bios_parser_interface.h"
40 #include "include/irq_service_interface.h"
41 #include "transform.h"
42 #include "timing_generator.h"
43 #include "virtual/virtual_link_encoder.h"
45 #include "link_hwss.h"
46 #include "link_encoder.h"
48 #include "dc_link_ddc.h"
49 #include "dm_helpers.h"
50 #include "mem_input.h"
52 /*******************************************************************************
54 ******************************************************************************/
55 static void destroy_links(struct core_dc *dc)
59 for (i = 0; i < dc->link_count; i++) {
60 if (NULL != dc->links[i])
61 link_destroy(&dc->links[i]);
65 static bool create_links(
67 uint32_t num_virtual_links)
71 struct dc_bios *bios = dc->ctx->dc_bios;
75 connectors_num = bios->funcs->get_connectors_number(bios);
77 if (connectors_num > ENUM_ID_COUNT) {
79 "DC: Number of connectors %d exceeds maximum of %d!\n",
85 if (connectors_num == 0 && num_virtual_links == 0) {
86 dm_error("DC: Number of connectors is zero!\n");
90 "DC: %s: connectors_num: physical:%d, virtual:%d\n",
95 for (i = 0; i < connectors_num; i++) {
96 struct link_init_data link_init_params = {0};
97 struct core_link *link;
99 link_init_params.ctx = dc->ctx;
100 /* next BIOS object table connector */
101 link_init_params.connector_index = i;
102 link_init_params.link_index = dc->link_count;
103 link_init_params.dc = dc;
104 link = link_create(&link_init_params);
107 dc->links[dc->link_count] = link;
113 for (i = 0; i < num_virtual_links; i++) {
114 struct core_link *link = dm_alloc(sizeof(*link));
115 struct encoder_init_data enc_init = {0};
124 link->public.connector_signal = SIGNAL_TYPE_VIRTUAL;
125 link->link_id.type = OBJECT_TYPE_CONNECTOR;
126 link->link_id.id = CONNECTOR_ID_VIRTUAL;
127 link->link_id.enum_id = ENUM_ID_1;
128 link->link_enc = dm_alloc(sizeof(*link->link_enc));
130 enc_init.ctx = dc->ctx;
131 enc_init.channel = CHANNEL_ID_UNKNOWN;
132 enc_init.hpd_source = HPD_SOURCEID_UNKNOWN;
133 enc_init.transmitter = TRANSMITTER_UNKNOWN;
134 enc_init.connector = link->link_id;
135 enc_init.encoder.type = OBJECT_TYPE_ENCODER;
136 enc_init.encoder.id = ENCODER_ID_INTERNAL_VIRTUAL;
137 enc_init.encoder.enum_id = ENUM_ID_1;
138 virtual_link_encoder_construct(link->link_enc, &enc_init);
140 link->public.link_index = dc->link_count;
141 dc->links[dc->link_count] = link;
151 static bool stream_adjust_vmin_vmax(struct dc *dc,
152 const struct dc_stream **stream, int num_streams,
155 /* TODO: Support multiple streams */
156 struct core_dc *core_dc = DC_TO_CORE(dc);
157 struct core_stream *core_stream = DC_STREAM_TO_CORE(stream[0]);
161 for (i = 0; i < MAX_PIPES; i++) {
162 struct pipe_ctx *pipe = &core_dc->current_context->res_ctx.pipe_ctx[i];
164 if (pipe->stream == core_stream && pipe->stream_enc) {
165 core_dc->hwss.set_drr(&pipe, 1, vmin, vmax);
167 /* build and update the info frame */
168 resource_build_info_frame(pipe);
169 core_dc->hwss.update_info_frame(pipe);
177 static bool stream_get_crtc_position(struct dc *dc,
178 const struct dc_stream **stream, int num_streams,
179 unsigned int *v_pos, unsigned int *nom_v_pos)
181 /* TODO: Support multiple streams */
182 struct core_dc *core_dc = DC_TO_CORE(dc);
183 struct core_stream *core_stream = DC_STREAM_TO_CORE(stream[0]);
186 struct crtc_position position;
188 for (i = 0; i < MAX_PIPES; i++) {
189 struct pipe_ctx *pipe =
190 &core_dc->current_context->res_ctx.pipe_ctx[i];
192 if (pipe->stream == core_stream && pipe->stream_enc) {
193 core_dc->hwss.get_position(&pipe, 1, &position);
195 *v_pos = position.vertical_count;
196 *nom_v_pos = position.nominal_vcount;
203 static bool set_gamut_remap(struct dc *dc, const struct dc_stream *stream)
205 struct core_dc *core_dc = DC_TO_CORE(dc);
206 struct core_stream *core_stream = DC_STREAM_TO_CORE(stream);
209 struct pipe_ctx *pipes;
211 for (i = 0; i < MAX_PIPES; i++) {
212 if (core_dc->current_context->res_ctx.pipe_ctx[i].stream
215 pipes = &core_dc->current_context->res_ctx.pipe_ctx[i];
216 core_dc->hwss.program_gamut_remap(pipes);
224 static void set_static_screen_events(struct dc *dc,
225 const struct dc_stream **stream,
227 const struct dc_static_screen_events *events)
229 struct core_dc *core_dc = DC_TO_CORE(dc);
232 struct pipe_ctx *pipes_affected[MAX_PIPES];
233 int num_pipes_affected = 0;
235 for (i = 0; i < num_streams; i++) {
236 struct core_stream *core_stream = DC_STREAM_TO_CORE(stream[i]);
238 for (j = 0; j < MAX_PIPES; j++) {
239 if (core_dc->current_context->res_ctx.pipe_ctx[j].stream
241 pipes_affected[num_pipes_affected++] =
242 &core_dc->current_context->res_ctx.pipe_ctx[j];
247 core_dc->hwss.set_static_screen_control(pipes_affected, num_pipes_affected, events);
250 static void set_drive_settings(struct dc *dc,
251 struct link_training_settings *lt_settings,
252 const struct dc_link *link)
254 struct core_dc *core_dc = DC_TO_CORE(dc);
257 for (i = 0; i < core_dc->link_count; i++) {
258 if (&core_dc->links[i]->public == link)
262 if (i >= core_dc->link_count)
263 ASSERT_CRITICAL(false);
265 dc_link_dp_set_drive_settings(&core_dc->links[i]->public, lt_settings);
268 static void perform_link_training(struct dc *dc,
269 struct dc_link_settings *link_setting,
270 bool skip_video_pattern)
272 struct core_dc *core_dc = DC_TO_CORE(dc);
275 for (i = 0; i < core_dc->link_count; i++)
276 dc_link_dp_perform_link_training(
277 &core_dc->links[i]->public,
282 static void set_preferred_link_settings(struct dc *dc,
283 struct dc_link_settings *link_setting,
284 const struct dc_link *link)
286 struct core_link *core_link = DC_LINK_TO_CORE(link);
288 core_link->public.verified_link_cap.lane_count =
289 link_setting->lane_count;
290 core_link->public.verified_link_cap.link_rate =
291 link_setting->link_rate;
292 dp_retrain_link_dp_test(core_link, link_setting, false);
295 static void enable_hpd(const struct dc_link *link)
297 dc_link_dp_enable_hpd(link);
300 static void disable_hpd(const struct dc_link *link)
302 dc_link_dp_disable_hpd(link);
306 static void set_test_pattern(
307 const struct dc_link *link,
308 enum dp_test_pattern test_pattern,
309 const struct link_training_settings *p_link_settings,
310 const unsigned char *p_custom_pattern,
311 unsigned int cust_pattern_size)
314 dc_link_dp_set_test_pattern(
322 void set_dither_option(const struct dc_stream *dc_stream,
323 enum dc_dither_option option)
325 struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream);
326 struct bit_depth_reduction_params params;
327 struct core_link *core_link = DC_LINK_TO_CORE(stream->status.link);
328 struct pipe_ctx *pipes =
329 core_link->dc->current_context->res_ctx.pipe_ctx;
331 memset(¶ms, 0, sizeof(params));
334 if (option > DITHER_OPTION_MAX)
336 if (option == DITHER_OPTION_DEFAULT) {
337 switch (stream->public.timing.display_color_depth) {
338 case COLOR_DEPTH_666:
339 stream->public.dither_option = DITHER_OPTION_SPATIAL6;
341 case COLOR_DEPTH_888:
342 stream->public.dither_option = DITHER_OPTION_SPATIAL8;
344 case COLOR_DEPTH_101010:
345 stream->public.dither_option = DITHER_OPTION_SPATIAL10;
348 option = DITHER_OPTION_DISABLE;
351 stream->public.dither_option = option;
353 resource_build_bit_depth_reduction_params(stream,
355 stream->bit_depth_params = params;
357 opp_program_bit_depth_reduction(pipes->opp, ¶ms);
360 static void allocate_dc_stream_funcs(struct core_dc *core_dc)
362 if (core_dc->hwss.set_drr != NULL) {
363 core_dc->public.stream_funcs.adjust_vmin_vmax =
364 stream_adjust_vmin_vmax;
367 core_dc->public.stream_funcs.set_static_screen_events =
368 set_static_screen_events;
370 core_dc->public.stream_funcs.get_crtc_position =
371 stream_get_crtc_position;
373 core_dc->public.stream_funcs.set_gamut_remap =
376 core_dc->public.stream_funcs.set_dither_option =
379 core_dc->public.link_funcs.set_drive_settings =
382 core_dc->public.link_funcs.perform_link_training =
383 perform_link_training;
385 core_dc->public.link_funcs.set_preferred_link_settings =
386 set_preferred_link_settings;
388 core_dc->public.link_funcs.enable_hpd =
391 core_dc->public.link_funcs.disable_hpd =
394 core_dc->public.link_funcs.set_test_pattern =
398 static void destruct(struct core_dc *dc)
400 dc_resource_validate_ctx_destruct(dc->current_context);
404 dc_destroy_resource_pool(dc);
406 if (dc->ctx->gpio_service)
407 dal_gpio_service_destroy(&dc->ctx->gpio_service);
410 dal_i2caux_destroy(&dc->ctx->i2caux);
412 if (dc->ctx->created_bios)
413 dal_bios_parser_destroy(&dc->ctx->dc_bios);
416 dal_logger_destroy(&dc->ctx->logger);
418 dm_free(dc->current_context);
419 dc->current_context = NULL;
425 static bool construct(struct core_dc *dc,
426 const struct dc_init_data *init_params)
428 struct dal_logger *logger;
429 struct dc_context *dc_ctx = dm_alloc(sizeof(*dc_ctx));
430 enum dce_version dc_version = DCE_VERSION_UNKNOWN;
433 dm_error("%s: failed to create ctx\n", __func__);
437 dc->current_context = dm_alloc(sizeof(*dc->current_context));
439 if (!dc->current_context) {
440 dm_error("%s: failed to create validate ctx\n", __func__);
444 dc_ctx->cgs_device = init_params->cgs_device;
445 dc_ctx->driver_context = init_params->driver;
446 dc_ctx->dc = &dc->public;
447 dc_ctx->asic_id = init_params->asic_id;
450 logger = dal_logger_create(dc_ctx);
453 /* can *not* call logger. call base driver 'print error' */
454 dm_error("%s: failed to create Logger!\n", __func__);
457 dc_ctx->logger = logger;
459 dc->ctx->dce_environment = init_params->dce_environment;
461 dc_version = resource_parse_asic_id(init_params->asic_id);
462 dc->ctx->dce_version = dc_version;
464 /* Resource should construct all asic specific resources.
465 * This should be the only place where we need to parse the asic id
467 if (init_params->vbios_override)
468 dc_ctx->dc_bios = init_params->vbios_override;
470 /* Create BIOS parser */
471 struct bp_init_data bp_init_data;
473 bp_init_data.ctx = dc_ctx;
474 bp_init_data.bios = init_params->asic_id.atombios_base_address;
476 dc_ctx->dc_bios = dal_bios_parser_create(
477 &bp_init_data, dc_version);
479 if (!dc_ctx->dc_bios) {
480 ASSERT_CRITICAL(false);
484 dc_ctx->created_bios = true;
488 dc_ctx->i2caux = dal_i2caux_create(dc_ctx);
490 if (!dc_ctx->i2caux) {
491 ASSERT_CRITICAL(false);
492 goto failed_to_create_i2caux;
495 /* Create GPIO service */
496 dc_ctx->gpio_service = dal_gpio_service_create(
498 dc_ctx->dce_environment,
501 if (!dc_ctx->gpio_service) {
502 ASSERT_CRITICAL(false);
506 dc->res_pool = dc_create_resource_pool(
508 init_params->num_virtual_links,
510 init_params->asic_id);
512 goto create_resource_fail;
514 if (!create_links(dc, init_params->num_virtual_links))
515 goto create_links_fail;
517 allocate_dc_stream_funcs(dc);
521 /**** error handling here ****/
523 create_resource_fail:
525 failed_to_create_i2caux:
535 void ProgramPixelDurationV(unsigned int pixelClockInKHz )
537 fixed31_32 pixel_duration = Fixed31_32(100000000, pixelClockInKHz) * 10;
538 unsigned int pixDurationInPico = round(pixel_duration);
540 DPG_PIPE_ARBITRATION_CONTROL1 arb_control;
542 arb_control.u32All = ReadReg (mmDPGV0_PIPE_ARBITRATION_CONTROL1);
543 arb_control.bits.PIXEL_DURATION = pixDurationInPico;
544 WriteReg (mmDPGV0_PIPE_ARBITRATION_CONTROL1, arb_control.u32All);
546 arb_control.u32All = ReadReg (mmDPGV1_PIPE_ARBITRATION_CONTROL1);
547 arb_control.bits.PIXEL_DURATION = pixDurationInPico;
548 WriteReg (mmDPGV1_PIPE_ARBITRATION_CONTROL1, arb_control.u32All);
550 WriteReg (mmDPGV0_PIPE_ARBITRATION_CONTROL2, 0x4000800);
551 WriteReg (mmDPGV0_REPEATER_PROGRAM, 0x11);
553 WriteReg (mmDPGV1_PIPE_ARBITRATION_CONTROL2, 0x4000800);
554 WriteReg (mmDPGV1_REPEATER_PROGRAM, 0x11);
558 /*******************************************************************************
560 ******************************************************************************/
562 struct dc *dc_create(const struct dc_init_data *init_params)
564 struct core_dc *core_dc = dm_alloc(sizeof(*core_dc));
565 unsigned int full_pipe_count;
570 if (false == construct(core_dc, init_params))
573 /*TODO: separate HW and SW initialization*/
574 core_dc->hwss.init_hw(core_dc);
576 full_pipe_count = core_dc->res_pool->pipe_count;
577 if (core_dc->res_pool->underlay_pipe_index != NO_UNDERLAY_PIPE)
579 core_dc->public.caps.max_streams = min(
581 core_dc->res_pool->stream_enc_count);
583 core_dc->public.caps.max_links = core_dc->link_count;
584 core_dc->public.caps.max_audios = core_dc->res_pool->audio_count;
586 core_dc->public.config = init_params->flags;
588 dm_logger_write(core_dc->ctx->logger, LOG_DC,
589 "Display Core initialized\n");
592 /* TODO: missing feature to be enabled */
593 core_dc->public.debug.disable_dfs_bypass = true;
595 return &core_dc->public;
604 void dc_destroy(struct dc **dc)
606 struct core_dc *core_dc = DC_TO_CORE(*dc);
612 static bool is_validation_required(
613 const struct core_dc *dc,
614 const struct dc_validation_set set[],
617 const struct validate_context *context = dc->current_context;
620 if (context->stream_count != set_count)
623 for (i = 0; i < set_count; i++) {
625 if (set[i].surface_count != context->stream_status[i].surface_count)
627 if (!is_stream_unchanged(DC_STREAM_TO_CORE(set[i].stream), context->streams[i]))
630 for (j = 0; j < set[i].surface_count; j++) {
631 struct dc_surface temp_surf = { 0 };
633 temp_surf = *context->stream_status[i].surfaces[j];
634 temp_surf.clip_rect = set[i].surfaces[j]->clip_rect;
635 temp_surf.dst_rect.x = set[i].surfaces[j]->dst_rect.x;
636 temp_surf.dst_rect.y = set[i].surfaces[j]->dst_rect.y;
638 if (memcmp(&temp_surf, set[i].surfaces[j], sizeof(temp_surf)) != 0)
646 struct validate_context *dc_get_validate_context(
648 const struct dc_validation_set set[],
651 struct core_dc *core_dc = DC_TO_CORE(dc);
652 enum dc_status result = DC_ERROR_UNEXPECTED;
653 struct validate_context *context;
655 context = dm_alloc(sizeof(struct validate_context));
657 goto context_alloc_fail;
659 if (!is_validation_required(core_dc, set, set_count)) {
660 dc_resource_validate_ctx_copy_construct(core_dc->current_context, context);
664 result = core_dc->res_pool->funcs->validate_with_context(
665 core_dc, set, set_count, context, core_dc->current_context);
668 if (result != DC_OK) {
669 dm_logger_write(core_dc->ctx->logger, LOG_WARNING,
670 "%s:resource validation failed, dc_status:%d\n",
674 dc_resource_validate_ctx_destruct(context);
683 bool dc_validate_resources(
685 const struct dc_validation_set set[],
688 struct core_dc *core_dc = DC_TO_CORE(dc);
689 enum dc_status result = DC_ERROR_UNEXPECTED;
690 struct validate_context *context;
692 context = dm_alloc(sizeof(struct validate_context));
694 goto context_alloc_fail;
696 result = core_dc->res_pool->funcs->validate_with_context(
697 core_dc, set, set_count, context, NULL);
700 if (result != DC_OK) {
701 dm_logger_write(core_dc->ctx->logger, LOG_WARNING,
702 "%s:resource validation failed, dc_status:%d\n",
707 dc_resource_validate_ctx_destruct(context);
711 return result == DC_OK;
714 bool dc_validate_guaranteed(
716 const struct dc_stream *stream)
718 struct core_dc *core_dc = DC_TO_CORE(dc);
719 enum dc_status result = DC_ERROR_UNEXPECTED;
720 struct validate_context *context;
722 context = dm_alloc(sizeof(struct validate_context));
724 goto context_alloc_fail;
726 result = core_dc->res_pool->funcs->validate_guaranteed(
727 core_dc, stream, context);
729 dc_resource_validate_ctx_destruct(context);
733 if (result != DC_OK) {
734 dm_logger_write(core_dc->ctx->logger, LOG_WARNING,
735 "%s:guaranteed validation failed, dc_status:%d\n",
740 return (result == DC_OK);
743 static void program_timing_sync(
744 struct core_dc *core_dc,
745 struct validate_context *ctx)
749 int pipe_count = core_dc->res_pool->pipe_count;
750 struct pipe_ctx *unsynced_pipes[MAX_PIPES] = { NULL };
752 for (i = 0; i < pipe_count; i++) {
753 if (!ctx->res_ctx.pipe_ctx[i].stream || ctx->res_ctx.pipe_ctx[i].top_pipe)
756 unsynced_pipes[i] = &ctx->res_ctx.pipe_ctx[i];
759 for (i = 0; i < pipe_count; i++) {
761 struct pipe_ctx *pipe_set[MAX_PIPES];
763 if (!unsynced_pipes[i])
766 pipe_set[0] = unsynced_pipes[i];
767 unsynced_pipes[i] = NULL;
769 /* Add tg to the set, search rest of the tg's for ones with
770 * same timing, add all tgs with same timing to the group
772 for (j = i + 1; j < pipe_count; j++) {
773 if (!unsynced_pipes[j])
776 if (resource_are_streams_timing_synchronizable(
777 unsynced_pipes[j]->stream,
778 pipe_set[0]->stream)) {
779 pipe_set[group_size] = unsynced_pipes[j];
780 unsynced_pipes[j] = NULL;
785 /* set first unblanked pipe as master */
786 for (j = 0; j < group_size; j++) {
787 struct pipe_ctx *temp;
789 if (!pipe_set[j]->tg->funcs->is_blanked(pipe_set[j]->tg)) {
794 pipe_set[0] = pipe_set[j];
800 /* remove any other unblanked pipes as they have already been synced */
801 for (j = j + 1; j < group_size; j++) {
802 if (!pipe_set[j]->tg->funcs->is_blanked(pipe_set[j]->tg)) {
804 pipe_set[j] = pipe_set[group_size];
809 if (group_size > 1) {
810 core_dc->hwss.enable_timing_synchronization(
811 core_dc, group_index, group_size, pipe_set);
817 static bool streams_changed(
819 const struct dc_stream *streams[],
820 uint8_t stream_count)
824 if (stream_count != dc->current_context->stream_count)
827 for (i = 0; i < dc->current_context->stream_count; i++) {
828 if (&dc->current_context->streams[i]->public != streams[i])
835 bool dc_commit_streams(
837 const struct dc_stream *streams[],
838 uint8_t stream_count)
840 struct core_dc *core_dc = DC_TO_CORE(dc);
841 struct dc_bios *dcb = core_dc->ctx->dc_bios;
842 enum dc_status result = DC_ERROR_UNEXPECTED;
843 struct validate_context *context;
844 struct dc_validation_set set[MAX_STREAMS] = { {0, {0} } };
847 if (false == streams_changed(core_dc, streams, stream_count))
850 dm_logger_write(core_dc->ctx->logger, LOG_DC, "%s: %d streams\n",
851 __func__, stream_count);
853 for (i = 0; i < stream_count; i++) {
854 const struct dc_stream *stream = streams[i];
855 const struct dc_stream_status *status = dc_stream_get_status(stream);
858 dc_stream_log(stream,
859 core_dc->ctx->logger,
862 set[i].stream = stream;
865 set[i].surface_count = status->surface_count;
866 for (j = 0; j < status->surface_count; j++)
867 set[i].surfaces[j] = status->surfaces[j];
872 context = dm_alloc(sizeof(struct validate_context));
874 goto context_alloc_fail;
876 result = core_dc->res_pool->funcs->validate_with_context(
877 core_dc, set, stream_count, context, core_dc->current_context);
878 if (result != DC_OK){
879 dm_logger_write(core_dc->ctx->logger, LOG_ERROR,
880 "%s: Context validation failed! dc_status:%d\n",
884 dc_resource_validate_ctx_destruct(context);
888 if (!dcb->funcs->is_accelerated_mode(dcb)) {
889 core_dc->hwss.enable_accelerated_mode(core_dc);
892 if (result == DC_OK) {
893 result = core_dc->hwss.apply_ctx_to_hw(core_dc, context);
896 program_timing_sync(core_dc, context);
898 for (i = 0; i < context->stream_count; i++) {
899 const struct core_sink *sink = context->streams[i]->sink;
901 for (j = 0; j < context->stream_status[i].surface_count; j++) {
902 struct core_surface *surface =
903 DC_SURFACE_TO_CORE(context->stream_status[i].surfaces[j]);
905 core_dc->hwss.apply_ctx_for_surface(core_dc, surface, context);
908 CONN_MSG_MODE(sink->link, "{%dx%d, %dx%d@%dKhz}",
909 context->streams[i]->public.timing.h_addressable,
910 context->streams[i]->public.timing.v_addressable,
911 context->streams[i]->public.timing.h_total,
912 context->streams[i]->public.timing.v_total,
913 context->streams[i]->public.timing.pix_clk_khz);
916 dc_resource_validate_ctx_destruct(core_dc->current_context);
917 dm_free(core_dc->current_context);
919 core_dc->current_context = context;
921 return (result == DC_OK);
927 return (result == DC_OK);
930 bool dc_pre_update_surfaces_to_stream(
932 const struct dc_surface *const *new_surfaces,
933 uint8_t new_surface_count,
934 const struct dc_stream *dc_stream)
939 bool dc_post_update_surfaces_to_stream(struct dc *dc)
942 struct core_dc *core_dc = DC_TO_CORE(dc);
943 struct validate_context *context = core_dc->current_context;
945 post_surface_trace(dc);
947 for (i = 0; i < core_dc->res_pool->pipe_count; i++)
948 if (context->res_ctx.pipe_ctx[i].stream == NULL) {
949 context->res_ctx.pipe_ctx[i].pipe_idx = i;
950 core_dc->hwss.power_down_front_end(
951 core_dc, &context->res_ctx.pipe_ctx[i]);
954 core_dc->hwss.set_bandwidth(core_dc, context, true);
959 bool dc_commit_surfaces_to_stream(
961 const struct dc_surface **new_surfaces,
962 uint8_t new_surface_count,
963 const struct dc_stream *dc_stream)
965 struct dc_surface_update updates[MAX_SURFACES];
966 struct dc_flip_addrs flip_addr[MAX_SURFACES];
967 struct dc_plane_info plane_info[MAX_SURFACES];
968 struct dc_scaling_info scaling_info[MAX_SURFACES];
971 struct dc_stream_update *stream_update =
972 dm_alloc(sizeof(struct dc_stream_update));
974 if (!stream_update) {
979 memset(updates, 0, sizeof(updates));
980 memset(flip_addr, 0, sizeof(flip_addr));
981 memset(plane_info, 0, sizeof(plane_info));
982 memset(scaling_info, 0, sizeof(scaling_info));
984 stream_update->src = dc_stream->src;
985 stream_update->dst = dc_stream->dst;
987 for (i = 0; i < new_surface_count; i++) {
988 updates[i].surface = new_surfaces[i];
990 (struct dc_gamma *)new_surfaces[i]->gamma_correction;
991 flip_addr[i].address = new_surfaces[i]->address;
992 flip_addr[i].flip_immediate = new_surfaces[i]->flip_immediate;
993 plane_info[i].color_space = new_surfaces[i]->color_space;
994 plane_info[i].format = new_surfaces[i]->format;
995 plane_info[i].plane_size = new_surfaces[i]->plane_size;
996 plane_info[i].rotation = new_surfaces[i]->rotation;
997 plane_info[i].horizontal_mirror = new_surfaces[i]->horizontal_mirror;
998 plane_info[i].stereo_format = new_surfaces[i]->stereo_format;
999 plane_info[i].tiling_info = new_surfaces[i]->tiling_info;
1000 plane_info[i].visible = new_surfaces[i]->visible;
1001 plane_info[i].per_pixel_alpha = new_surfaces[i]->per_pixel_alpha;
1002 plane_info[i].dcc = new_surfaces[i]->dcc;
1003 scaling_info[i].scaling_quality = new_surfaces[i]->scaling_quality;
1004 scaling_info[i].src_rect = new_surfaces[i]->src_rect;
1005 scaling_info[i].dst_rect = new_surfaces[i]->dst_rect;
1006 scaling_info[i].clip_rect = new_surfaces[i]->clip_rect;
1008 updates[i].flip_addr = &flip_addr[i];
1009 updates[i].plane_info = &plane_info[i];
1010 updates[i].scaling_info = &scaling_info[i];
1013 dc_update_surfaces_and_stream(
1017 dc_stream, stream_update);
1019 ret = dc_post_update_surfaces_to_stream(dc);
1021 dm_free(stream_update);
1025 static bool is_surface_in_context(
1026 const struct validate_context *context,
1027 const struct dc_surface *surface)
1031 for (j = 0; j < MAX_PIPES; j++) {
1032 const struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1034 if (surface == &pipe_ctx->surface->public) {
1042 static unsigned int pixel_format_to_bpp(enum surface_pixel_format format)
1045 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
1046 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
1048 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
1049 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
1050 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
1051 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
1053 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
1054 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
1055 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
1056 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
1058 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
1059 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
1060 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
1063 ASSERT_CRITICAL(false);
1068 static enum surface_update_type get_plane_info_update_type(
1069 const struct dc_surface_update *u,
1072 struct dc_plane_info temp_plane_info = { 0 };
1075 return UPDATE_TYPE_FAST;
1077 /* Copy all parameters that will cause a full update
1078 * from current surface, the rest of the parameters
1079 * from provided plane configuration.
1080 * Perform memory compare and special validation
1081 * for those that can cause fast/medium updates
1084 /* Full update parameters */
1085 temp_plane_info.color_space = u->surface->color_space;
1086 temp_plane_info.dcc = u->surface->dcc;
1087 temp_plane_info.horizontal_mirror = u->surface->horizontal_mirror;
1088 temp_plane_info.plane_size = u->surface->plane_size;
1089 temp_plane_info.rotation = u->surface->rotation;
1090 temp_plane_info.stereo_format = u->surface->stereo_format;
1091 temp_plane_info.tiling_info = u->surface->tiling_info;
1093 /* Special Validation parameters */
1094 temp_plane_info.format = u->plane_info->format;
1095 temp_plane_info.per_pixel_alpha = u->plane_info->per_pixel_alpha;
1097 if (surface_index == 0)
1098 temp_plane_info.visible = u->plane_info->visible;
1100 temp_plane_info.visible = u->surface->visible;
1102 if (memcmp(u->plane_info, &temp_plane_info,
1103 sizeof(struct dc_plane_info)) != 0)
1104 return UPDATE_TYPE_FULL;
1106 if (pixel_format_to_bpp(u->plane_info->format) !=
1107 pixel_format_to_bpp(u->surface->format)) {
1108 return UPDATE_TYPE_FULL;
1110 return UPDATE_TYPE_MED;
1114 static enum surface_update_type get_scaling_info_update_type(
1115 const struct dc_surface_update *u)
1117 if (!u->scaling_info)
1118 return UPDATE_TYPE_FAST;
1120 if (u->scaling_info->src_rect.width != u->surface->src_rect.width
1121 || u->scaling_info->src_rect.height != u->surface->src_rect.height
1122 || u->scaling_info->clip_rect.width != u->surface->clip_rect.width
1123 || u->scaling_info->clip_rect.height != u->surface->clip_rect.height
1124 || u->scaling_info->dst_rect.width != u->surface->dst_rect.width
1125 || u->scaling_info->dst_rect.height != u->surface->dst_rect.height)
1126 return UPDATE_TYPE_FULL;
1128 if (u->scaling_info->src_rect.x != u->surface->src_rect.x
1129 || u->scaling_info->src_rect.y != u->surface->src_rect.y
1130 || u->scaling_info->clip_rect.x != u->surface->clip_rect.x
1131 || u->scaling_info->clip_rect.y != u->surface->clip_rect.y
1132 || u->scaling_info->dst_rect.x != u->surface->dst_rect.x
1133 || u->scaling_info->dst_rect.y != u->surface->dst_rect.y)
1134 return UPDATE_TYPE_MED;
1136 return UPDATE_TYPE_FAST;
1139 static enum surface_update_type det_surface_update(
1140 const struct core_dc *dc,
1141 const struct dc_surface_update *u,
1144 const struct validate_context *context = dc->current_context;
1145 enum surface_update_type type = UPDATE_TYPE_FAST;
1146 enum surface_update_type overall_type = UPDATE_TYPE_FAST;
1148 if (!is_surface_in_context(context, u->surface))
1149 return UPDATE_TYPE_FULL;
1151 type = get_plane_info_update_type(u, surface_index);
1152 if (overall_type < type)
1153 overall_type = type;
1155 type = get_scaling_info_update_type(u);
1156 if (overall_type < type)
1157 overall_type = type;
1159 if (u->in_transfer_func ||
1160 u->hdr_static_metadata) {
1161 if (overall_type < UPDATE_TYPE_MED)
1162 overall_type = UPDATE_TYPE_MED;
1165 return overall_type;
1168 enum surface_update_type dc_check_update_surfaces_for_stream(
1170 struct dc_surface_update *updates,
1172 struct dc_stream_update *stream_update,
1173 const struct dc_stream_status *stream_status)
1175 struct core_dc *core_dc = DC_TO_CORE(dc);
1177 enum surface_update_type overall_type = UPDATE_TYPE_FAST;
1179 if (stream_status == NULL || stream_status->surface_count != surface_count)
1180 return UPDATE_TYPE_FULL;
1183 return UPDATE_TYPE_FULL;
1185 for (i = 0 ; i < surface_count; i++) {
1186 enum surface_update_type type =
1187 det_surface_update(core_dc, &updates[i], i);
1189 if (type == UPDATE_TYPE_FULL)
1192 if (overall_type < type)
1193 overall_type = type;
1196 return overall_type;
1199 void dc_update_surfaces_for_stream(struct dc *dc,
1200 struct dc_surface_update *surface_updates, int surface_count,
1201 const struct dc_stream *dc_stream)
1203 dc_update_surfaces_and_stream(dc, surface_updates, surface_count,
1207 enum surface_update_type update_surface_trace_level = UPDATE_TYPE_FULL;
1209 void dc_update_surfaces_and_stream(struct dc *dc,
1210 struct dc_surface_update *srf_updates, int surface_count,
1211 const struct dc_stream *dc_stream,
1212 struct dc_stream_update *stream_update)
1214 struct core_dc *core_dc = DC_TO_CORE(dc);
1215 struct validate_context *context;
1217 enum surface_update_type update_type;
1218 const struct dc_stream_status *stream_status;
1219 struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream);
1221 stream_status = dc_stream_get_status(dc_stream);
1222 ASSERT(stream_status);
1224 return; /* Cannot commit surface to stream that is not committed */
1226 context = core_dc->current_context;
1228 /* update current stream with the new updates */
1229 if (stream_update) {
1230 if ((stream_update->src.height != 0) &&
1231 (stream_update->src.width != 0))
1232 stream->public.src = stream_update->src;
1234 if ((stream_update->dst.height != 0) &&
1235 (stream_update->dst.width != 0))
1236 stream->public.dst = stream_update->dst;
1238 if (stream_update->out_transfer_func &&
1239 stream_update->out_transfer_func !=
1240 dc_stream->out_transfer_func) {
1241 if (stream_update->out_transfer_func->type !=
1243 if (dc_stream->out_transfer_func != NULL)
1244 dc_transfer_func_release
1245 (dc_stream->out_transfer_func);
1246 dc_transfer_func_retain(stream_update->
1248 stream->public.out_transfer_func =
1249 stream_update->out_transfer_func;
1254 /* do not perform surface update if surface has invalid dimensions
1255 * (all zero) and no scaling_info is provided
1257 if (surface_count > 0 &&
1258 srf_updates->surface->src_rect.width == 0 &&
1259 srf_updates->surface->src_rect.height == 0 &&
1260 srf_updates->surface->dst_rect.width == 0 &&
1261 srf_updates->surface->dst_rect.height == 0 &&
1262 !srf_updates->scaling_info) {
1267 update_type = dc_check_update_surfaces_for_stream(
1268 dc, srf_updates, surface_count, stream_update, stream_status);
1270 if (update_type >= update_surface_trace_level)
1271 update_surface_trace(dc, srf_updates, surface_count);
1273 if (update_type >= UPDATE_TYPE_FULL) {
1274 const struct dc_surface *new_surfaces[MAX_SURFACES] = { 0 };
1276 for (i = 0; i < surface_count; i++)
1277 new_surfaces[i] = srf_updates[i].surface;
1279 /* initialize scratch memory for building context */
1280 context = dm_alloc(sizeof(*context));
1281 dc_resource_validate_ctx_copy_construct(
1282 core_dc->current_context, context);
1284 /* add surface to context */
1285 if (!resource_attach_surfaces_to_context(
1286 new_surfaces, surface_count, dc_stream,
1287 context, core_dc->res_pool)) {
1288 BREAK_TO_DEBUGGER();
1293 /* save update parameters into surface */
1294 for (i = 0; i < surface_count; i++) {
1295 struct core_surface *surface =
1296 DC_SURFACE_TO_CORE(srf_updates[i].surface);
1298 if (srf_updates[i].flip_addr) {
1299 surface->public.address = srf_updates[i].flip_addr->address;
1300 surface->public.flip_immediate =
1301 srf_updates[i].flip_addr->flip_immediate;
1304 if (srf_updates[i].scaling_info) {
1305 surface->public.scaling_quality =
1306 srf_updates[i].scaling_info->scaling_quality;
1307 surface->public.dst_rect =
1308 srf_updates[i].scaling_info->dst_rect;
1309 surface->public.src_rect =
1310 srf_updates[i].scaling_info->src_rect;
1311 surface->public.clip_rect =
1312 srf_updates[i].scaling_info->clip_rect;
1315 if (srf_updates[i].plane_info) {
1316 surface->public.color_space =
1317 srf_updates[i].plane_info->color_space;
1318 surface->public.format =
1319 srf_updates[i].plane_info->format;
1320 surface->public.plane_size =
1321 srf_updates[i].plane_info->plane_size;
1322 surface->public.rotation =
1323 srf_updates[i].plane_info->rotation;
1324 surface->public.horizontal_mirror =
1325 srf_updates[i].plane_info->horizontal_mirror;
1326 surface->public.stereo_format =
1327 srf_updates[i].plane_info->stereo_format;
1328 surface->public.tiling_info =
1329 srf_updates[i].plane_info->tiling_info;
1330 surface->public.visible =
1331 srf_updates[i].plane_info->visible;
1332 surface->public.per_pixel_alpha =
1333 srf_updates[i].plane_info->per_pixel_alpha;
1334 surface->public.dcc =
1335 srf_updates[i].plane_info->dcc;
1338 if (update_type >= UPDATE_TYPE_MED) {
1339 for (j = 0; j < core_dc->res_pool->pipe_count; j++) {
1340 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1342 if (pipe_ctx->surface != surface)
1345 resource_build_scaling_params(pipe_ctx);
1349 if (srf_updates[i].gamma &&
1350 srf_updates[i].gamma != surface->public.gamma_correction) {
1351 if (surface->public.gamma_correction != NULL)
1352 dc_gamma_release(&surface->public.
1355 dc_gamma_retain(srf_updates[i].gamma);
1356 surface->public.gamma_correction =
1357 srf_updates[i].gamma;
1360 if (srf_updates[i].in_transfer_func &&
1361 srf_updates[i].in_transfer_func != surface->public.in_transfer_func) {
1362 if (surface->public.in_transfer_func != NULL)
1363 dc_transfer_func_release(
1367 dc_transfer_func_retain(
1368 srf_updates[i].in_transfer_func);
1369 surface->public.in_transfer_func =
1370 srf_updates[i].in_transfer_func;
1373 if (srf_updates[i].hdr_static_metadata)
1374 surface->public.hdr_static_ctx =
1375 *(srf_updates[i].hdr_static_metadata);
1378 if (update_type == UPDATE_TYPE_FULL) {
1379 if (!core_dc->res_pool->funcs->validate_bandwidth(core_dc, context)) {
1380 BREAK_TO_DEBUGGER();
1383 core_dc->hwss.set_bandwidth(core_dc, context, false);
1386 if (!surface_count) /* reset */
1387 core_dc->hwss.apply_ctx_for_surface(core_dc, NULL, context);
1389 /* Lock pipes for provided surfaces */
1390 for (i = 0; i < surface_count; i++) {
1391 struct core_surface *surface = DC_SURFACE_TO_CORE(srf_updates[i].surface);
1393 for (j = 0; j < core_dc->res_pool->pipe_count; j++) {
1394 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1396 if (pipe_ctx->surface != surface)
1398 if (!pipe_ctx->tg->funcs->is_blanked(pipe_ctx->tg)) {
1399 core_dc->hwss.pipe_control_lock(
1407 /* Perform requested Updates */
1408 for (i = 0; i < surface_count; i++) {
1409 struct core_surface *surface = DC_SURFACE_TO_CORE(srf_updates[i].surface);
1411 if (update_type >= UPDATE_TYPE_MED) {
1412 core_dc->hwss.apply_ctx_for_surface(
1413 core_dc, surface, context);
1414 context_timing_trace(dc, &context->res_ctx);
1417 for (j = 0; j < core_dc->res_pool->pipe_count; j++) {
1418 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
1419 struct pipe_ctx *cur_pipe_ctx;
1420 bool is_new_pipe_surface = true;
1422 if (pipe_ctx->surface != surface)
1425 if (srf_updates[i].flip_addr)
1426 core_dc->hwss.update_plane_addr(core_dc, pipe_ctx);
1428 if (update_type == UPDATE_TYPE_FAST)
1431 cur_pipe_ctx = &core_dc->current_context->res_ctx.pipe_ctx[j];
1432 if (cur_pipe_ctx->surface == pipe_ctx->surface)
1433 is_new_pipe_surface = false;
1435 if (is_new_pipe_surface ||
1436 srf_updates[i].in_transfer_func)
1437 core_dc->hwss.set_input_transfer_func(
1438 pipe_ctx, pipe_ctx->surface);
1440 if (is_new_pipe_surface ||
1441 (stream_update != NULL &&
1442 stream_update->out_transfer_func !=
1444 core_dc->hwss.set_output_transfer_func(
1445 pipe_ctx, pipe_ctx->stream);
1448 if (srf_updates[i].hdr_static_metadata) {
1449 resource_build_info_frame(pipe_ctx);
1450 core_dc->hwss.update_info_frame(pipe_ctx);
1456 for (i = core_dc->res_pool->pipe_count - 1; i >= 0; i--) {
1457 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1459 for (j = 0; j < surface_count; j++) {
1460 if (srf_updates[j].surface == &pipe_ctx->surface->public) {
1461 if (!pipe_ctx->tg->funcs->is_blanked(pipe_ctx->tg)) {
1462 core_dc->hwss.pipe_control_lock(
1472 if (core_dc->current_context != context) {
1473 dc_resource_validate_ctx_destruct(core_dc->current_context);
1474 dm_free(core_dc->current_context);
1476 core_dc->current_context = context;
1481 dc_resource_validate_ctx_destruct(context);
1485 uint8_t dc_get_current_stream_count(const struct dc *dc)
1487 struct core_dc *core_dc = DC_TO_CORE(dc);
1488 return core_dc->current_context->stream_count;
1491 struct dc_stream *dc_get_stream_at_index(const struct dc *dc, uint8_t i)
1493 struct core_dc *core_dc = DC_TO_CORE(dc);
1494 if (i < core_dc->current_context->stream_count)
1495 return &(core_dc->current_context->streams[i]->public);
1499 const struct dc_link *dc_get_link_at_index(const struct dc *dc, uint32_t link_index)
1501 struct core_dc *core_dc = DC_TO_CORE(dc);
1502 return &core_dc->links[link_index]->public;
1505 const struct graphics_object_id dc_get_link_id_at_index(
1506 struct dc *dc, uint32_t link_index)
1508 struct core_dc *core_dc = DC_TO_CORE(dc);
1509 return core_dc->links[link_index]->link_id;
1512 enum dc_irq_source dc_get_hpd_irq_source_at_index(
1513 struct dc *dc, uint32_t link_index)
1515 struct core_dc *core_dc = DC_TO_CORE(dc);
1516 return core_dc->links[link_index]->public.irq_source_hpd;
1519 const struct audio **dc_get_audios(struct dc *dc)
1521 struct core_dc *core_dc = DC_TO_CORE(dc);
1522 return (const struct audio **)core_dc->res_pool->audios;
1525 enum dc_irq_source dc_interrupt_to_irq_source(
1530 struct core_dc *core_dc = DC_TO_CORE(dc);
1531 return dal_irq_service_to_irq_source(core_dc->res_pool->irqs, src_id, ext_id);
1534 void dc_interrupt_set(const struct dc *dc, enum dc_irq_source src, bool enable)
1536 struct core_dc *core_dc;
1540 core_dc = DC_TO_CORE(dc);
1542 dal_irq_service_set(core_dc->res_pool->irqs, src, enable);
1545 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src)
1547 struct core_dc *core_dc = DC_TO_CORE(dc);
1548 dal_irq_service_ack(core_dc->res_pool->irqs, src);
1551 void dc_set_power_state(
1553 enum dc_acpi_cm_power_state power_state)
1555 struct core_dc *core_dc = DC_TO_CORE(dc);
1557 switch (power_state) {
1558 case DC_ACPI_CM_POWER_STATE_D0:
1559 core_dc->hwss.init_hw(core_dc);
1563 core_dc->hwss.power_down(core_dc);
1565 /* Zero out the current context so that on resume we start with
1566 * clean state, and dc hw programming optimizations will not
1567 * cause any trouble.
1569 memset(core_dc->current_context, 0,
1570 sizeof(*core_dc->current_context));
1577 void dc_resume(const struct dc *dc)
1579 struct core_dc *core_dc = DC_TO_CORE(dc);
1583 for (i = 0; i < core_dc->link_count; i++)
1584 core_link_resume(core_dc->links[i]);
1587 bool dc_read_aux_dpcd(
1589 uint32_t link_index,
1594 struct core_dc *core_dc = DC_TO_CORE(dc);
1596 struct core_link *link = core_dc->links[link_index];
1597 enum ddc_result r = dal_ddc_service_read_dpcd_data(
1604 return r == DDC_RESULT_SUCESSFULL;
1607 bool dc_write_aux_dpcd(
1609 uint32_t link_index,
1611 const uint8_t *data,
1614 struct core_dc *core_dc = DC_TO_CORE(dc);
1615 struct core_link *link = core_dc->links[link_index];
1617 enum ddc_result r = dal_ddc_service_write_dpcd_data(
1624 return r == DDC_RESULT_SUCESSFULL;
1627 bool dc_read_aux_i2c(
1629 uint32_t link_index,
1630 enum i2c_mot_mode mot,
1635 struct core_dc *core_dc = DC_TO_CORE(dc);
1637 struct core_link *link = core_dc->links[link_index];
1638 enum ddc_result r = dal_ddc_service_read_dpcd_data(
1645 return r == DDC_RESULT_SUCESSFULL;
1648 bool dc_write_aux_i2c(
1650 uint32_t link_index,
1651 enum i2c_mot_mode mot,
1653 const uint8_t *data,
1656 struct core_dc *core_dc = DC_TO_CORE(dc);
1657 struct core_link *link = core_dc->links[link_index];
1659 enum ddc_result r = dal_ddc_service_write_dpcd_data(
1666 return r == DDC_RESULT_SUCESSFULL;
1669 bool dc_query_ddc_data(
1671 uint32_t link_index,
1674 uint32_t write_size,
1676 uint32_t read_size) {
1678 struct core_dc *core_dc = DC_TO_CORE(dc);
1680 struct core_link *link = core_dc->links[link_index];
1682 bool result = dal_ddc_service_query_ddc_data(
1695 uint32_t link_index,
1696 struct i2c_command *cmd)
1698 struct core_dc *core_dc = DC_TO_CORE(dc);
1700 struct core_link *link = core_dc->links[link_index];
1701 struct ddc_service *ddc = link->public.ddc;
1703 return dal_i2caux_submit_i2c_command(
1709 static bool link_add_remote_sink_helper(struct core_link *core_link, struct dc_sink *sink)
1711 struct dc_link *dc_link = &core_link->public;
1713 if (dc_link->sink_count >= MAX_SINKS_PER_LINK) {
1714 BREAK_TO_DEBUGGER();
1718 dc_sink_retain(sink);
1720 dc_link->remote_sinks[dc_link->sink_count] = sink;
1721 dc_link->sink_count++;
1726 struct dc_sink *dc_link_add_remote_sink(
1727 const struct dc_link *link,
1728 const uint8_t *edid,
1730 struct dc_sink_init_data *init_data)
1732 struct dc_sink *dc_sink;
1733 enum dc_edid_status edid_status;
1734 struct core_link *core_link = DC_LINK_TO_LINK(link);
1736 if (len > MAX_EDID_BUFFER_SIZE) {
1737 dm_error("Max EDID buffer size breached!\n");
1742 BREAK_TO_DEBUGGER();
1746 if (!init_data->link) {
1747 BREAK_TO_DEBUGGER();
1751 dc_sink = dc_sink_create(init_data);
1756 memmove(dc_sink->dc_edid.raw_edid, edid, len);
1757 dc_sink->dc_edid.length = len;
1759 if (!link_add_remote_sink_helper(
1764 edid_status = dm_helpers_parse_edid_caps(
1767 &dc_sink->edid_caps);
1769 if (edid_status != EDID_OK)
1774 dc_link_remove_remote_sink(link, dc_sink);
1776 dc_sink_release(dc_sink);
1780 void dc_link_set_sink(const struct dc_link *link, struct dc_sink *sink)
1782 struct core_link *core_link = DC_LINK_TO_LINK(link);
1783 struct dc_link *dc_link = &core_link->public;
1785 dc_link->local_sink = sink;
1788 dc_link->type = dc_connection_none;
1790 dc_link->type = dc_connection_single;
1794 void dc_link_remove_remote_sink(const struct dc_link *link, const struct dc_sink *sink)
1797 struct core_link *core_link = DC_LINK_TO_LINK(link);
1798 struct dc_link *dc_link = &core_link->public;
1800 if (!link->sink_count) {
1801 BREAK_TO_DEBUGGER();
1805 for (i = 0; i < dc_link->sink_count; i++) {
1806 if (dc_link->remote_sinks[i] == sink) {
1807 dc_sink_release(sink);
1808 dc_link->remote_sinks[i] = NULL;
1810 /* shrink array to remove empty place */
1811 while (i < dc_link->sink_count - 1) {
1812 dc_link->remote_sinks[i] = dc_link->remote_sinks[i+1];
1815 dc_link->remote_sinks[i] = NULL;
1816 dc_link->sink_count--;
1822 bool dc_init_dchub(struct dc *dc, struct dchub_init_data *dh_data)
1825 struct core_dc *core_dc = DC_TO_CORE(dc);
1826 struct mem_input *mi = NULL;
1828 for (i = 0; i < core_dc->res_pool->pipe_count; i++) {
1829 if (core_dc->res_pool->mis[i] != NULL) {
1830 mi = core_dc->res_pool->mis[i];
1835 dm_error("no mem_input!\n");
1839 if (mi->funcs->mem_input_update_dchub)
1840 mi->funcs->mem_input_update_dchub(mi, dh_data);
1842 ASSERT(mi->funcs->mem_input_update_dchub);