drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

   1 /*
   2  * Copyright 2021 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26
  27
  28 #include "dccg.h"
  29 #include "clk_mgr_internal.h"
  30
  31 // For dce12_get_dp_ref_freq_khz
  32 #include "dce100/dce_clk_mgr.h"
  33 // For dcn20_update_clocks_update_dpp_dto
  34 #include "dcn20/dcn20_clk_mgr.h"
  35 #include "dcn31/dcn31_clk_mgr.h"
  36 #include "dcn316_clk_mgr.h"
  37 #include "reg_helper.h"
  38 #include "core_types.h"
  39 #include "dcn316_smu.h"
  40 #include "dm_helpers.h"
  41 #include "dc_dmub_srv.h"
  42 #include "link.h"
  43
  44 // DCN316 this is CLK1 instance
  45 #define MAX_INSTANCE                                        7
  46 #define MAX_SEGMENT                                         6
  47
  48 struct IP_BASE_INSTANCE {
  49     unsigned int segment[MAX_SEGMENT];
  50 };
  51
  52 struct IP_BASE {
  53     struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
  54 };
  55
  56 #define regCLK1_CLK_PLL_REQ                                             0x0237
  57 #define regCLK1_CLK_PLL_REQ_BASE_IDX                    0
  58
  59 #define CLK1_CLK_PLL_REQ__FbMult_int__SHIFT             0x0
  60 #define CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT    0xc
  61 #define CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT    0x10
  62 #define CLK1_CLK_PLL_REQ__FbMult_int_MASK               0x000001FFL
  63 #define CLK1_CLK_PLL_REQ__PllSpineDiv_MASK              0x0000F000L
  64 #define CLK1_CLK_PLL_REQ__FbMult_frac_MASK              0xFFFF0000L
  65
  66 #define TO_CLK_MGR_DCN316(clk_mgr)\
  67         container_of(clk_mgr, struct clk_mgr_dcn316, base)
  68
  69 static int dcn316_get_active_display_cnt_wa(
  70                 struct dc *dc,
  71                 struct dc_state *context)
  72 {
  73         int i, display_count;
  74         bool tmds_present = false;
  75
  76         display_count = 0;
  77         for (i = 0; i < context->stream_count; i++) {
  78                 const struct dc_stream_state *stream = context->streams[i];
  79
  80                 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A ||
  81                                 stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
  82                                 stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK)
  83                         tmds_present = true;
  84         }
  85
  86         for (i = 0; i < dc->link_count; i++) {
  87                 const struct dc_link *link = dc->links[i];
  88
  89                 /* abusing the fact that the dig and phy are coupled to see if the phy is enabled */
  90                 if (link->link_enc && link->link_enc->funcs->is_dig_enabled &&
  91                                 link->link_enc->funcs->is_dig_enabled(link->link_enc))
  92                         display_count++;
  93         }
  94
  95         /* WA for hang on HDMI after display off back back on*/
  96         if (display_count == 0 && tmds_present)
  97                 display_count = 1;
  98
  99         return display_count;
 100 }
 101
 102 static void dcn316_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disable)
 103 {
 104         struct dc *dc = clk_mgr_base->ctx->dc;
 105         int i;
 106
 107         for (i = 0; i < dc->res_pool->pipe_count; ++i) {
 108                 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 109
 110                 if (pipe->top_pipe || pipe->prev_odm_pipe)
 111                         continue;
 112                 if (pipe->stream && (pipe->stream->dpms_off || pipe->plane_state == NULL ||
 113                                      dc_is_virtual_signal(pipe->stream->signal))) {
 114                         if (disable) {
 115                                 pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg);
 116                                 reset_sync_context_for_pipe(dc, context, i);
 117                         } else
 118                                 pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);
 119                 }
 120         }
 121 }
 122
 123 static void dcn316_enable_pme_wa(struct clk_mgr *clk_mgr_base)
 124 {
 125         struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
 126
 127         dcn316_smu_enable_pme_wa(clk_mgr);
 128 }
 129
 130 static void dcn316_update_clocks(struct clk_mgr *clk_mgr_base,
 131                         struct dc_state *context,
 132                         bool safe_to_lower)
 133 {
 134         union dmub_rb_cmd cmd;
 135         struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
 136         struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
 137         struct dc *dc = clk_mgr_base->ctx->dc;
 138         int display_count;
 139         bool update_dppclk = false;
 140         bool update_dispclk = false;
 141         bool dpp_clock_lowered = false;
 142
 143         if (dc->work_arounds.skip_clock_update)
 144                 return;
 145
 146         /*
 147          * if it is safe to lower, but we are already in the lower state, we don't have to do anything
 148          * also if safe to lower is false, we just go in the higher state
 149          */
 150         clk_mgr_base->clks.zstate_support = new_clocks->zstate_support;
 151         if (safe_to_lower) {
 152                 if (clk_mgr_base->clks.dtbclk_en && !new_clocks->dtbclk_en) {
 153                         dcn316_smu_set_dtbclk(clk_mgr, false);
 154                         clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en;
 155                 }
 156                 /* check that we're not already in lower */
 157                 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
 158                         display_count = dcn316_get_active_display_cnt_wa(dc, context);
 159                         /* if we can go lower, go lower */
 160                         if (display_count == 0) {
 161                                 union display_idle_optimization_u idle_info = { 0 };
 162                                 idle_info.idle_info.df_request_disabled = 1;
 163                                 idle_info.idle_info.phy_ref_clk_off = 1;
 164                                 idle_info.idle_info.s0i2_rdy = 1;
 165                                 dcn316_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
 166                                 /* update power state */
 167                                 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
 168                         }
 169                 }
 170         } else {
 171                 if (!clk_mgr_base->clks.dtbclk_en && new_clocks->dtbclk_en) {
 172                         dcn316_smu_set_dtbclk(clk_mgr, true);
 173                         clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en;
 174                 }
 175
 176                 /* check that we're not already in D0 */
 177                 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) {
 178                         union display_idle_optimization_u idle_info = { 0 };
 179                         dcn316_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
 180                         /* update power state */
 181                         clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE;
 182                 }
 183         }
 184
 185         if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
 186                 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
 187                 dcn316_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz);
 188         }
 189
 190         if (should_set_clock(safe_to_lower,
 191                         new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
 192                 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
 193                 dcn316_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz);
 194         }
 195
 196         // workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow.
 197         if (new_clocks->dppclk_khz < 100000)
 198                 new_clocks->dppclk_khz = 100000;
 199         if (new_clocks->dispclk_khz < 100000)
 200                 new_clocks->dispclk_khz = 100000;
 201
 202         if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
 203                 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
 204                         dpp_clock_lowered = true;
 205                 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
 206                 update_dppclk = true;
 207         }
 208
 209         if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
 210                 dcn316_disable_otg_wa(clk_mgr_base, context, true);
 211
 212                 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
 213                 dcn316_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);
 214                 dcn316_disable_otg_wa(clk_mgr_base, context, false);
 215
 216                 update_dispclk = true;
 217         }
 218
 219         if (dpp_clock_lowered) {
 220                 // increase per DPP DTO before lowering global dppclk
 221                 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
 222                 dcn316_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
 223         } else {
 224                 // increase global DPPCLK before lowering per DPP DTO
 225                 if (update_dppclk || update_dispclk)
 226                         dcn316_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
 227                 // always update dtos unless clock is lowered and not safe to lower
 228                 if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz)
 229                         dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
 230         }
 231
 232         // notify DMCUB of latest clocks
 233         memset(&cmd, 0, sizeof(cmd));
 234         cmd.notify_clocks.header.type = DMUB_CMD__CLK_MGR;
 235         cmd.notify_clocks.header.sub_type = DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS;
 236         cmd.notify_clocks.clocks.dcfclk_khz = clk_mgr_base->clks.dcfclk_khz;
 237         cmd.notify_clocks.clocks.dcfclk_deep_sleep_khz =
 238                 clk_mgr_base->clks.dcfclk_deep_sleep_khz;
 239         cmd.notify_clocks.clocks.dispclk_khz = clk_mgr_base->clks.dispclk_khz;
 240         cmd.notify_clocks.clocks.dppclk_khz = clk_mgr_base->clks.dppclk_khz;
 241
 242         dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
 243 }
 244
 245 static void dcn316_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,
 246                 struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)
 247 {
 248         return;
 249 }
 250
 251 static struct clk_bw_params dcn316_bw_params = {
 252         .vram_type = Ddr4MemType,
 253         .num_channels = 1,
 254         .clk_table = {
 255                 .num_entries = 5,
 256         },
 257
 258 };
 259
 260 static struct wm_table ddr4_wm_table = {
 261         .entries = {
 262                 {
 263                         .wm_inst = WM_A,
 264                         .wm_type = WM_TYPE_PSTATE_CHG,
 265                         .pstate_latency_us = 11.72,
 266                         .sr_exit_time_us = 6.09,
 267                         .sr_enter_plus_exit_time_us = 7.14,
 268                         .valid = true,
 269                 },
 270                 {
 271                         .wm_inst = WM_B,
 272                         .wm_type = WM_TYPE_PSTATE_CHG,
 273                         .pstate_latency_us = 11.72,
 274                         .sr_exit_time_us = 10.12,
 275                         .sr_enter_plus_exit_time_us = 11.48,
 276                         .valid = true,
 277                 },
 278                 {
 279                         .wm_inst = WM_C,
 280                         .wm_type = WM_TYPE_PSTATE_CHG,
 281                         .pstate_latency_us = 11.72,
 282                         .sr_exit_time_us = 10.12,
 283                         .sr_enter_plus_exit_time_us = 11.48,
 284                         .valid = true,
 285                 },
 286                 {
 287                         .wm_inst = WM_D,
 288                         .wm_type = WM_TYPE_PSTATE_CHG,
 289                         .pstate_latency_us = 11.72,
 290                         .sr_exit_time_us = 10.12,
 291                         .sr_enter_plus_exit_time_us = 11.48,
 292                         .valid = true,
 293                 },
 294         }
 295 };
 296
 297 static struct wm_table lpddr5_wm_table = {
 298         .entries = {
 299                 {
 300                         .wm_inst = WM_A,
 301                         .wm_type = WM_TYPE_PSTATE_CHG,
 302                         .pstate_latency_us = 11.65333,
 303                         .sr_exit_time_us = 11.5,
 304                         .sr_enter_plus_exit_time_us = 14.5,
 305                         .valid = true,
 306                 },
 307                 {
 308                         .wm_inst = WM_B,
 309                         .wm_type = WM_TYPE_PSTATE_CHG,
 310                         .pstate_latency_us = 11.65333,
 311                         .sr_exit_time_us = 11.5,
 312                         .sr_enter_plus_exit_time_us = 14.5,
 313                         .valid = true,
 314                 },
 315                 {
 316                         .wm_inst = WM_C,
 317                         .wm_type = WM_TYPE_PSTATE_CHG,
 318                         .pstate_latency_us = 11.65333,
 319                         .sr_exit_time_us = 11.5,
 320                         .sr_enter_plus_exit_time_us = 14.5,
 321                         .valid = true,
 322                 },
 323                 {
 324                         .wm_inst = WM_D,
 325                         .wm_type = WM_TYPE_PSTATE_CHG,
 326                         .pstate_latency_us = 11.65333,
 327                         .sr_exit_time_us = 11.5,
 328                         .sr_enter_plus_exit_time_us = 14.5,
 329                         .valid = true,
 330                 },
 331         }
 332 };
 333
 334 static DpmClocks_316_t dummy_clocks;
 335
 336 static struct dcn316_watermarks dummy_wms = { 0 };
 337
 338 static void dcn316_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn316_watermarks *table)
 339 {
 340         int i, num_valid_sets;
 341
 342         num_valid_sets = 0;
 343
 344         for (i = 0; i < WM_SET_COUNT; i++) {
 345                 /* skip empty entries, the smu array has no holes*/
 346                 if (!bw_params->wm_table.entries[i].valid)
 347                         continue;
 348
 349                 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
 350                 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
 351                 /* We will not select WM based on fclk, so leave it as unconstrained */
 352                 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
 353                 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
 354
 355                 if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) {
 356                         if (i == 0)
 357                                 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0;
 358                         else {
 359                                 /* add 1 to make it non-overlapping with next lvl */
 360                                 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk =
 361                                                 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
 362                         }
 363                         table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =
 364                                         bw_params->clk_table.entries[i].dcfclk_mhz;
 365
 366                 } else {
 367                         /* unconstrained for memory retraining */
 368                         table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
 369                         table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
 370
 371                         /* Modify previous watermark range to cover up to max */
 372                         table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
 373                 }
 374                 num_valid_sets++;
 375         }
 376
 377         ASSERT(num_valid_sets != 0); /* Must have at least one set of valid watermarks */
 378
 379         /* modify the min and max to make sure we cover the whole range*/
 380         table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0;
 381         table->WatermarkRow[WM_DCFCLK][0].MinClock = 0;
 382         table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxMclk = 0xFFFF;
 383         table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
 384
 385         /* This is for writeback only, does not matter currently as no writeback support*/
 386         table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A;
 387         table->WatermarkRow[WM_SOCCLK][0].MinClock = 0;
 388         table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF;
 389         table->WatermarkRow[WM_SOCCLK][0].MinMclk = 0;
 390         table->WatermarkRow[WM_SOCCLK][0].MaxMclk = 0xFFFF;
 391 }
 392
 393 static void dcn316_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
 394 {
 395         struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
 396         struct clk_mgr_dcn316 *clk_mgr_dcn316 = TO_CLK_MGR_DCN316(clk_mgr);
 397         struct dcn316_watermarks *table = clk_mgr_dcn316->smu_wm_set.wm_set;
 398
 399         if (!clk_mgr->smu_ver)
 400                 return;
 401
 402         if (!table || clk_mgr_dcn316->smu_wm_set.mc_address.quad_part == 0)
 403                 return;
 404
 405         memset(table, 0, sizeof(*table));
 406
 407         dcn316_build_watermark_ranges(clk_mgr_base->bw_params, table);
 408
 409         dcn316_smu_set_dram_addr_high(clk_mgr,
 410                         clk_mgr_dcn316->smu_wm_set.mc_address.high_part);
 411         dcn316_smu_set_dram_addr_low(clk_mgr,
 412                         clk_mgr_dcn316->smu_wm_set.mc_address.low_part);
 413         dcn316_smu_transfer_wm_table_dram_2_smu(clk_mgr);
 414 }
 415
 416 static void dcn316_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr,
 417                 struct dcn316_smu_dpm_clks *smu_dpm_clks)
 418 {
 419         DpmClocks_316_t *table = smu_dpm_clks->dpm_clks;
 420
 421         if (!clk_mgr->smu_ver)
 422                 return;
 423
 424         if (!table || smu_dpm_clks->mc_address.quad_part == 0)
 425                 return;
 426
 427         memset(table, 0, sizeof(*table));
 428
 429         dcn316_smu_set_dram_addr_high(clk_mgr,
 430                         smu_dpm_clks->mc_address.high_part);
 431         dcn316_smu_set_dram_addr_low(clk_mgr,
 432                         smu_dpm_clks->mc_address.low_part);
 433         dcn316_smu_transfer_dpm_table_smu_2_dram(clk_mgr);
 434 }
 435
 436 static uint32_t find_max_clk_value(const uint32_t clocks[], uint32_t num_clocks)
 437 {
 438         uint32_t max = 0;
 439         int i;
 440
 441         for (i = 0; i < num_clocks; ++i) {
 442                 if (clocks[i] > max)
 443                         max = clocks[i];
 444         }
 445
 446         return max;
 447 }
 448
 449 static unsigned int find_clk_for_voltage(
 450                 const DpmClocks_316_t *clock_table,
 451                 const uint32_t clocks[],
 452                 unsigned int voltage)
 453 {
 454         int i;
 455         int max_voltage = 0;
 456         int clock = 0;
 457
 458         for (i = 0; i < NUM_SOC_VOLTAGE_LEVELS; i++) {
 459                 if (clock_table->SocVoltage[i] == voltage) {
 460                         return clocks[i];
 461                 } else if (clock_table->SocVoltage[i] >= max_voltage &&
 462                                 clock_table->SocVoltage[i] < voltage) {
 463                         max_voltage = clock_table->SocVoltage[i];
 464                         clock = clocks[i];
 465                 }
 466         }
 467
 468         ASSERT(clock);
 469         return clock;
 470 }
 471
 472 static void dcn316_clk_mgr_helper_populate_bw_params(
 473                 struct clk_mgr_internal *clk_mgr,
 474                 struct integrated_info *bios_info,
 475                 const DpmClocks_316_t *clock_table)
 476 {
 477         int i, j;
 478         struct clk_bw_params *bw_params = clk_mgr->base.bw_params;
 479         uint32_t max_dispclk = 0, max_dppclk = 0;
 480
 481         j = -1;
 482
 483         ASSERT(NUM_DF_PSTATE_LEVELS <= MAX_NUM_DPM_LVL);
 484
 485         /* Find lowest DPM, FCLK is filled in reverse order*/
 486
 487         for (i = NUM_DF_PSTATE_LEVELS - 1; i >= 0; i--) {
 488                 if (clock_table->DfPstateTable[i].FClk != 0) {
 489                         j = i;
 490                         break;
 491                 }
 492         }
 493
 494         if (j == -1) {
 495                 /* clock table is all 0s, just use our own hardcode */
 496                 ASSERT(0);
 497                 return;
 498         }
 499
 500         bw_params->clk_table.num_entries = j + 1;
 501
 502         /* dispclk and dppclk can be max at any voltage, same number of levels for both */
 503         if (clock_table->NumDispClkLevelsEnabled <= NUM_DISPCLK_DPM_LEVELS &&
 504             clock_table->NumDispClkLevelsEnabled <= NUM_DPPCLK_DPM_LEVELS) {
 505                 max_dispclk = find_max_clk_value(clock_table->DispClocks, clock_table->NumDispClkLevelsEnabled);
 506                 max_dppclk = find_max_clk_value(clock_table->DppClocks, clock_table->NumDispClkLevelsEnabled);
 507         } else {
 508                 ASSERT(0);
 509         }
 510
 511         for (i = 0; i < bw_params->clk_table.num_entries; i++, j--) {
 512                 int temp;
 513
 514                 bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].FClk;
 515                 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[j].MemClk;
 516                 bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[j].Voltage;
 517                 switch (clock_table->DfPstateTable[j].WckRatio) {
 518                 case WCK_RATIO_1_2:
 519                         bw_params->clk_table.entries[i].wck_ratio = 2;
 520                         break;
 521                 case WCK_RATIO_1_4:
 522                         bw_params->clk_table.entries[i].wck_ratio = 4;
 523                         break;
 524                 default:
 525                         bw_params->clk_table.entries[i].wck_ratio = 1;
 526                 }
 527                 temp = find_clk_for_voltage(clock_table, clock_table->DcfClocks, clock_table->DfPstateTable[j].Voltage);
 528                 if (temp)
 529                         bw_params->clk_table.entries[i].dcfclk_mhz = temp;
 530                 temp = find_clk_for_voltage(clock_table, clock_table->SocClocks, clock_table->DfPstateTable[j].Voltage);
 531                 if (temp)
 532                         bw_params->clk_table.entries[i].socclk_mhz = temp;
 533                 bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk;
 534                 bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk;
 535         }
 536
 537         bw_params->vram_type = bios_info->memory_type;
 538         bw_params->num_channels = bios_info->ma_channel_number;
 539         bw_params->dram_channel_width_bytes = bios_info->memory_type == 0x22 ? 8 : 4;
 540
 541         for (i = 0; i < WM_SET_COUNT; i++) {
 542                 bw_params->wm_table.entries[i].wm_inst = i;
 543
 544                 if (i >= bw_params->clk_table.num_entries) {
 545                         bw_params->wm_table.entries[i].valid = false;
 546                         continue;
 547                 }
 548
 549                 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG;
 550                 bw_params->wm_table.entries[i].valid = true;
 551         }
 552 }
 553
 554
 555
 556 static struct clk_mgr_funcs dcn316_funcs = {
 557         .enable_pme_wa = dcn316_enable_pme_wa,
 558         .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
 559         .get_dtb_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz,
 560         .update_clocks = dcn316_update_clocks,
 561         .init_clocks = dcn31_init_clocks,
 562         .are_clock_states_equal = dcn31_are_clock_states_equal,
 563         .notify_wm_ranges = dcn316_notify_wm_ranges
 564 };
 565 extern struct clk_mgr_funcs dcn3_fpga_funcs;
 566
 567 void dcn316_clk_mgr_construct(
 568                 struct dc_context *ctx,
 569                 struct clk_mgr_dcn316 *clk_mgr,
 570                 struct pp_smu_funcs *pp_smu,
 571                 struct dccg *dccg)
 572 {
 573         struct dcn316_smu_dpm_clks smu_dpm_clks = { 0 };
 574         struct clk_log_info log_info = {0};
 575
 576         clk_mgr->base.base.ctx = ctx;
 577         clk_mgr->base.base.funcs = &dcn316_funcs;
 578
 579         clk_mgr->base.pp_smu = pp_smu;
 580
 581         clk_mgr->base.dccg = dccg;
 582         clk_mgr->base.dfs_bypass_disp_clk = 0;
 583
 584         clk_mgr->base.dprefclk_ss_percentage = 0;
 585         clk_mgr->base.dprefclk_ss_divider = 1000;
 586         clk_mgr->base.ss_on_dprefclk = false;
 587         clk_mgr->base.dfs_ref_freq_khz = 48000;
 588
 589         clk_mgr->smu_wm_set.wm_set = (struct dcn316_watermarks *)dm_helpers_allocate_gpu_mem(
 590                                 clk_mgr->base.base.ctx,
 591                                 DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
 592                                 sizeof(struct dcn316_watermarks),
 593                                 &clk_mgr->smu_wm_set.mc_address.quad_part);
 594
 595         if (!clk_mgr->smu_wm_set.wm_set) {
 596                 clk_mgr->smu_wm_set.wm_set = &dummy_wms;
 597                 clk_mgr->smu_wm_set.mc_address.quad_part = 0;
 598         }
 599         ASSERT(clk_mgr->smu_wm_set.wm_set);
 600
 601         smu_dpm_clks.dpm_clks = (DpmClocks_316_t *)dm_helpers_allocate_gpu_mem(
 602                                 clk_mgr->base.base.ctx,
 603                                 DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
 604                                 sizeof(DpmClocks_316_t),
 605                                 &smu_dpm_clks.mc_address.quad_part);
 606
 607         if (smu_dpm_clks.dpm_clks == NULL) {
 608                 smu_dpm_clks.dpm_clks = &dummy_clocks;
 609                 smu_dpm_clks.mc_address.quad_part = 0;
 610         }
 611
 612         ASSERT(smu_dpm_clks.dpm_clks);
 613
 614         clk_mgr->base.smu_ver = dcn316_smu_get_smu_version(&clk_mgr->base);
 615
 616         if (clk_mgr->base.smu_ver > 0)
 617                 clk_mgr->base.smu_present = true;
 618
 619         // Skip this for now as it did not work on DCN315, renable during bring up
 620         //clk_mgr->base.base.dentist_vco_freq_khz = get_vco_frequency_from_reg(&clk_mgr->base);
 621         clk_mgr->base.base.dentist_vco_freq_khz = 2500000;
 622
 623         /* in case we don't get a value from the register, use default */
 624         if (clk_mgr->base.base.dentist_vco_freq_khz == 0)
 625                 clk_mgr->base.base.dentist_vco_freq_khz = 2500000; /* 2400MHz */
 626
 627
 628         if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) {
 629                 dcn316_bw_params.wm_table = lpddr5_wm_table;
 630         } else {
 631                 dcn316_bw_params.wm_table = ddr4_wm_table;
 632         }
 633         /* Saved clocks configured at boot for debug purposes */
 634         dcn316_dump_clk_registers(&clk_mgr->base.base.boot_snapshot,
 635                                   &clk_mgr->base.base, &log_info);
 636
 637         clk_mgr->base.base.dprefclk_khz = 600000;
 638         clk_mgr->base.base.dprefclk_khz = dcn316_smu_get_dpref_clk(&clk_mgr->base);
 639         clk_mgr->base.base.clks.ref_dtbclk_khz = clk_mgr->base.base.dprefclk_khz;
 640         dce_clock_read_ss_info(&clk_mgr->base);
 641         /*clk_mgr->base.dccg->ref_dtbclk_khz =
 642         dce_adjust_dp_ref_freq_for_ss(&clk_mgr->base, clk_mgr->base.base.dprefclk_khz);*/
 643
 644         clk_mgr->base.base.bw_params = &dcn316_bw_params;
 645
 646         if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) {
 647                 dcn316_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks);
 648
 649                 if (ctx->dc_bios && ctx->dc_bios->integrated_info) {
 650                         dcn316_clk_mgr_helper_populate_bw_params(
 651                                         &clk_mgr->base,
 652                                         ctx->dc_bios->integrated_info,
 653                                         smu_dpm_clks.dpm_clks);
 654                 }
 655         }
 656
 657         if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0)
 658                 dm_helpers_free_gpu_mem(clk_mgr->base.base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
 659                                 smu_dpm_clks.dpm_clks);
 660 }
 661
 662 void dcn316_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int)
 663 {
 664         struct clk_mgr_dcn316 *clk_mgr = TO_CLK_MGR_DCN316(clk_mgr_int);
 665
 666         if (clk_mgr->smu_wm_set.wm_set && clk_mgr->smu_wm_set.mc_address.quad_part != 0)
 667                 dm_helpers_free_gpu_mem(clk_mgr_int->base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
 668                                 clk_mgr->smu_wm_set.wm_set);
 669 }