drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dccg.h"
  27 #include "clk_mgr_internal.h"
  28
  29
  30 #include "dcn20/dcn20_clk_mgr.h"
  31 #include "rn_clk_mgr.h"
  32
  33
  34 #include "dce100/dce_clk_mgr.h"
  35 #include "rn_clk_mgr_vbios_smu.h"
  36 #include "reg_helper.h"
  37 #include "core_types.h"
  38 #include "dm_helpers.h"
  39
  40 #include "atomfirmware.h"
  41 #include "clk/clk_10_0_2_offset.h"
  42 #include "clk/clk_10_0_2_sh_mask.h"
  43 #include "renoir_ip_offset.h"
  44
  45
  46 /* Constants */
  47
  48 #define LPDDR_MEM_RETRAIN_LATENCY 4.977 /* Number obtained from LPDDR4 Training Counter Requirement doc */
  49
  50 /* Macros */
  51
  52 #define REG(reg_name) \
  53         (CLK_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
  54
  55
  56 /* TODO: evaluate how to lower or disable all dcn clocks in screen off case */
  57 int rn_get_active_display_cnt_wa(
  58                 struct dc *dc,
  59                 struct dc_state *context)
  60 {
  61         int i, display_count;
  62         bool tmds_present = false;
  63
  64         display_count = 0;
  65         for (i = 0; i < context->stream_count; i++) {
  66                 const struct dc_stream_state *stream = context->streams[i];
  67
  68                 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A ||
  69                                 stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
  70                                 stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK)
  71                         tmds_present = true;
  72         }
  73
  74         for (i = 0; i < dc->link_count; i++) {
  75                 const struct dc_link *link = dc->links[i];
  76
  77                 /*
  78                  * Only notify active stream or virtual stream.
  79                  * Need to notify virtual stream to work around
  80                  * headless case. HPD does not fire when system is in
  81                  * S0i2.
  82                  */
  83                 /* abusing the fact that the dig and phy are coupled to see if the phy is enabled */
  84                 if (link->connector_signal == SIGNAL_TYPE_VIRTUAL ||
  85                                 link->link_enc->funcs->is_dig_enabled(link->link_enc))
  86                         display_count++;
  87         }
  88
  89         /* WA for hang on HDMI after display off back back on*/
  90         if (display_count == 0 && tmds_present)
  91                 display_count = 1;
  92
  93         return display_count;
  94 }
  95
  96 void rn_update_clocks(struct clk_mgr *clk_mgr_base,
  97                         struct dc_state *context,
  98                         bool safe_to_lower)
  99 {
 100         struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
 101         struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
 102         struct dc *dc = clk_mgr_base->ctx->dc;
 103         int display_count;
 104         bool update_dppclk = false;
 105         bool update_dispclk = false;
 106         bool dpp_clock_lowered = false;
 107
 108         struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;
 109
 110         if (dc->work_arounds.skip_clock_update)
 111                 return;
 112
 113         /*
 114          * if it is safe to lower, but we are already in the lower state, we don't have to do anything
 115          * also if safe to lower is false, we just go in the higher state
 116          */
 117         if (safe_to_lower) {
 118                 /* check that we're not already in lower */
 119                 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
 120
 121                         display_count = rn_get_active_display_cnt_wa(dc, context);
 122                         /* if we can go lower, go lower */
 123                         if (display_count == 0) {
 124                                 rn_vbios_smu_set_dcn_low_power_state(clk_mgr, DCN_PWR_STATE_LOW_POWER);
 125                                 /* update power state */
 126                                 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
 127                         }
 128                 }
 129         } else {
 130                 /* check that we're not already in D0 */
 131                 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) {
 132                         rn_vbios_smu_set_dcn_low_power_state(clk_mgr, DCN_PWR_STATE_MISSION_MODE);
 133                         /* update power state */
 134                         clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE;
 135                 }
 136         }
 137
 138         if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr_base->clks.phyclk_khz)) {
 139                 clk_mgr_base->clks.phyclk_khz = new_clocks->phyclk_khz;
 140                 rn_vbios_smu_set_phyclk(clk_mgr, clk_mgr_base->clks.phyclk_khz);
 141         }
 142
 143         if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
 144                 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
 145                 rn_vbios_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz);
 146         }
 147
 148         if (should_set_clock(safe_to_lower,
 149                         new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
 150                 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
 151                 rn_vbios_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz);
 152         }
 153
 154         if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
 155                 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
 156                         dpp_clock_lowered = true;
 157                 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
 158                 update_dppclk = true;
 159         }
 160
 161         if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
 162                 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
 163                 rn_vbios_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);
 164
 165                 update_dispclk = true;
 166         }
 167
 168         if (dpp_clock_lowered) {
 169                 // increase per DPP DTO before lowering global dppclk
 170                 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
 171                 rn_vbios_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
 172         } else {
 173                 // increase global DPPCLK before lowering per DPP DTO
 174                 if (update_dppclk || update_dispclk)
 175                         rn_vbios_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
 176                 // always update dtos unless clock is lowered and not safe to lower
 177                 if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz)
 178                         dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
 179         }
 180
 181         if (update_dispclk &&
 182                         dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
 183                 /*update dmcu for wait_loop count*/
 184                 dmcu->funcs->set_psr_wait_loop(dmcu,
 185                         clk_mgr_base->clks.dispclk_khz / 1000 / 7);
 186         }
 187 }
 188
 189
 190 static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)
 191 {
 192         /* get FbMult value */
 193         struct fixed31_32 pll_req;
 194         unsigned int fbmult_frac_val = 0;
 195         unsigned int fbmult_int_val = 0;
 196
 197
 198         /*
 199          * Register value of fbmult is in 8.16 format, we are converting to 31.32
 200          * to leverage the fix point operations available in driver
 201          */
 202
 203         REG_GET(CLK1_CLK_PLL_REQ, FbMult_frac, &fbmult_frac_val); /* 16 bit fractional part*/
 204         REG_GET(CLK1_CLK_PLL_REQ, FbMult_int, &fbmult_int_val); /* 8 bit integer part */
 205
 206         pll_req = dc_fixpt_from_int(fbmult_int_val);
 207
 208         /*
 209          * since fractional part is only 16 bit in register definition but is 32 bit
 210          * in our fix point definiton, need to shift left by 16 to obtain correct value
 211          */
 212         pll_req.value |= fbmult_frac_val << 16;
 213
 214         /* multiply by REFCLK period */
 215         pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz);
 216
 217         /* integer part is now VCO frequency in kHz */
 218         return dc_fixpt_floor(pll_req);
 219 }
 220
 221 static void rn_dump_clk_registers_internal(struct rn_clk_internal *internal, struct clk_mgr *clk_mgr_base)
 222 {
 223         struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
 224
 225         internal->CLK1_CLK3_CURRENT_CNT = REG_READ(CLK1_CLK3_CURRENT_CNT);
 226         internal->CLK1_CLK3_BYPASS_CNTL = REG_READ(CLK1_CLK3_BYPASS_CNTL);
 227
 228         internal->CLK1_CLK3_DS_CNTL = REG_READ(CLK1_CLK3_DS_CNTL);      //dcf deep sleep divider
 229         internal->CLK1_CLK3_ALLOW_DS = REG_READ(CLK1_CLK3_ALLOW_DS);
 230
 231         internal->CLK1_CLK1_CURRENT_CNT = REG_READ(CLK1_CLK1_CURRENT_CNT);
 232         internal->CLK1_CLK1_BYPASS_CNTL = REG_READ(CLK1_CLK1_BYPASS_CNTL);
 233
 234         internal->CLK1_CLK2_CURRENT_CNT = REG_READ(CLK1_CLK2_CURRENT_CNT);
 235         internal->CLK1_CLK2_BYPASS_CNTL = REG_READ(CLK1_CLK2_BYPASS_CNTL);
 236
 237         internal->CLK1_CLK0_CURRENT_CNT = REG_READ(CLK1_CLK0_CURRENT_CNT);
 238         internal->CLK1_CLK0_BYPASS_CNTL = REG_READ(CLK1_CLK0_BYPASS_CNTL);
 239 }
 240
 241 /* This function collect raw clk register values */
 242 static void rn_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,
 243                 struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)
 244 {
 245         struct rn_clk_internal internal = {0};
 246         char *bypass_clks[5] = {"0x0 DFS", "0x1 REFCLK", "0x2 ERROR", "0x3 400 FCH", "0x4 600 FCH"};
 247         unsigned int chars_printed = 0;
 248         unsigned int remaining_buffer = log_info->bufSize;
 249
 250         rn_dump_clk_registers_internal(&internal, clk_mgr_base);
 251
 252         regs_and_bypass->dcfclk = internal.CLK1_CLK3_CURRENT_CNT / 10;
 253         regs_and_bypass->dcf_deep_sleep_divider = internal.CLK1_CLK3_DS_CNTL / 10;
 254         regs_and_bypass->dcf_deep_sleep_allow = internal.CLK1_CLK3_ALLOW_DS;
 255         regs_and_bypass->dprefclk = internal.CLK1_CLK2_CURRENT_CNT / 10;
 256         regs_and_bypass->dispclk = internal.CLK1_CLK0_CURRENT_CNT / 10;
 257         regs_and_bypass->dppclk = internal.CLK1_CLK1_CURRENT_CNT / 10;
 258
 259         regs_and_bypass->dppclk_bypass = internal.CLK1_CLK1_BYPASS_CNTL & 0x0007;
 260         if (regs_and_bypass->dppclk_bypass < 0 || regs_and_bypass->dppclk_bypass > 4)
 261                 regs_and_bypass->dppclk_bypass = 0;
 262         regs_and_bypass->dcfclk_bypass = internal.CLK1_CLK3_BYPASS_CNTL & 0x0007;
 263         if (regs_and_bypass->dcfclk_bypass < 0 || regs_and_bypass->dcfclk_bypass > 4)
 264                 regs_and_bypass->dcfclk_bypass = 0;
 265         regs_and_bypass->dispclk_bypass = internal.CLK1_CLK0_BYPASS_CNTL & 0x0007;
 266         if (regs_and_bypass->dispclk_bypass < 0 || regs_and_bypass->dispclk_bypass > 4)
 267                 regs_and_bypass->dispclk_bypass = 0;
 268         regs_and_bypass->dprefclk_bypass = internal.CLK1_CLK2_BYPASS_CNTL & 0x0007;
 269         if (regs_and_bypass->dprefclk_bypass < 0 || regs_and_bypass->dprefclk_bypass > 4)
 270                 regs_and_bypass->dprefclk_bypass = 0;
 271
 272         if (log_info->enabled) {
 273                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "clk_type,clk_value,deepsleep_cntl,deepsleep_allow,bypass\n");
 274                 remaining_buffer -= chars_printed;
 275                 *log_info->sum_chars_printed += chars_printed;
 276                 log_info->pBuf += chars_printed;
 277
 278                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "dcfclk,%d,%d,%d,%s\n",
 279                         regs_and_bypass->dcfclk,
 280                         regs_and_bypass->dcf_deep_sleep_divider,
 281                         regs_and_bypass->dcf_deep_sleep_allow,
 282                         bypass_clks[(int) regs_and_bypass->dcfclk_bypass]);
 283                 remaining_buffer -= chars_printed;
 284                 *log_info->sum_chars_printed += chars_printed;
 285                 log_info->pBuf += chars_printed;
 286
 287                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "dprefclk,%d,N/A,N/A,%s\n",
 288                         regs_and_bypass->dprefclk,
 289                         bypass_clks[(int) regs_and_bypass->dprefclk_bypass]);
 290                 remaining_buffer -= chars_printed;
 291                 *log_info->sum_chars_printed += chars_printed;
 292                 log_info->pBuf += chars_printed;
 293
 294                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "dispclk,%d,N/A,N/A,%s\n",
 295                         regs_and_bypass->dispclk,
 296                         bypass_clks[(int) regs_and_bypass->dispclk_bypass]);
 297                 remaining_buffer -= chars_printed;
 298                 *log_info->sum_chars_printed += chars_printed;
 299                 log_info->pBuf += chars_printed;
 300
 301                 //split
 302                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "SPLIT\n");
 303                 remaining_buffer -= chars_printed;
 304                 *log_info->sum_chars_printed += chars_printed;
 305                 log_info->pBuf += chars_printed;
 306
 307                 // REGISTER VALUES
 308                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "reg_name,value,clk_type\n");
 309                 remaining_buffer -= chars_printed;
 310                 *log_info->sum_chars_printed += chars_printed;
 311                 log_info->pBuf += chars_printed;
 312
 313                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_CURRENT_CNT,%d,dcfclk\n",
 314                                 internal.CLK1_CLK3_CURRENT_CNT);
 315                 remaining_buffer -= chars_printed;
 316                 *log_info->sum_chars_printed += chars_printed;
 317                 log_info->pBuf += chars_printed;
 318
 319                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_DS_CNTL,%d,dcf_deep_sleep_divider\n",
 320                                         internal.CLK1_CLK3_DS_CNTL);
 321                 remaining_buffer -= chars_printed;
 322                 *log_info->sum_chars_printed += chars_printed;
 323                 log_info->pBuf += chars_printed;
 324
 325                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_ALLOW_DS,%d,dcf_deep_sleep_allow\n",
 326                                         internal.CLK1_CLK3_ALLOW_DS);
 327                 remaining_buffer -= chars_printed;
 328                 *log_info->sum_chars_printed += chars_printed;
 329                 log_info->pBuf += chars_printed;
 330
 331                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK2_CURRENT_CNT,%d,dprefclk\n",
 332                                         internal.CLK1_CLK2_CURRENT_CNT);
 333                 remaining_buffer -= chars_printed;
 334                 *log_info->sum_chars_printed += chars_printed;
 335                 log_info->pBuf += chars_printed;
 336
 337                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK0_CURRENT_CNT,%d,dispclk\n",
 338                                         internal.CLK1_CLK0_CURRENT_CNT);
 339                 remaining_buffer -= chars_printed;
 340                 *log_info->sum_chars_printed += chars_printed;
 341                 log_info->pBuf += chars_printed;
 342
 343                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK1_CURRENT_CNT,%d,dppclk\n",
 344                                         internal.CLK1_CLK1_CURRENT_CNT);
 345                 remaining_buffer -= chars_printed;
 346                 *log_info->sum_chars_printed += chars_printed;
 347                 log_info->pBuf += chars_printed;
 348
 349                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_BYPASS_CNTL,%d,dcfclk_bypass\n",
 350                                         internal.CLK1_CLK3_BYPASS_CNTL);
 351                 remaining_buffer -= chars_printed;
 352                 *log_info->sum_chars_printed += chars_printed;
 353                 log_info->pBuf += chars_printed;
 354
 355                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK2_BYPASS_CNTL,%d,dprefclk_bypass\n",
 356                                         internal.CLK1_CLK2_BYPASS_CNTL);
 357                 remaining_buffer -= chars_printed;
 358                 *log_info->sum_chars_printed += chars_printed;
 359                 log_info->pBuf += chars_printed;
 360
 361                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK0_BYPASS_CNTL,%d,dispclk_bypass\n",
 362                                         internal.CLK1_CLK0_BYPASS_CNTL);
 363                 remaining_buffer -= chars_printed;
 364                 *log_info->sum_chars_printed += chars_printed;
 365                 log_info->pBuf += chars_printed;
 366
 367                 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK1_BYPASS_CNTL,%d,dppclk_bypass\n",
 368                                         internal.CLK1_CLK1_BYPASS_CNTL);
 369                 remaining_buffer -= chars_printed;
 370                 *log_info->sum_chars_printed += chars_printed;
 371                 log_info->pBuf += chars_printed;
 372         }
 373 }
 374
 375 /* This function produce translated logical clk state values*/
 376 void rn_get_clk_states(struct clk_mgr *clk_mgr_base, struct clk_states *s)
 377 {
 378         struct clk_state_registers_and_bypass sb = { 0 };
 379         struct clk_log_info log_info = { 0 };
 380
 381         rn_dump_clk_registers(&sb, clk_mgr_base, &log_info);
 382
 383         s->dprefclk_khz = sb.dprefclk * 1000;
 384 }
 385
 386 void rn_enable_pme_wa(struct clk_mgr *clk_mgr_base)
 387 {
 388         struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
 389
 390         rn_vbios_smu_enable_pme_wa(clk_mgr);
 391 }
 392
 393 void rn_init_clocks(struct clk_mgr *clk_mgr)
 394 {
 395         memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));
 396         // Assumption is that boot state always supports pstate
 397         clk_mgr->clks.p_state_change_support = true;
 398         clk_mgr->clks.prev_p_state_change_support = true;
 399         clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN;
 400 }
 401
 402 void build_watermark_ranges(struct clk_bw_params *bw_params, struct pp_smu_wm_range_sets *ranges)
 403 {
 404         int i, num_valid_sets;
 405
 406         num_valid_sets = 0;
 407
 408         for (i = 0; i < WM_SET_COUNT; i++) {
 409                 /* skip empty entries, the smu array has no holes*/
 410                 if (!bw_params->wm_table.entries[i].valid)
 411                         continue;
 412
 413                 ranges->reader_wm_sets[num_valid_sets].wm_inst = bw_params->wm_table.entries[i].wm_inst;
 414                 ranges->reader_wm_sets[num_valid_sets].wm_type = bw_params->wm_table.entries[i].wm_type;
 415                 /* We will not select WM based on dcfclk, so leave it as unconstrained */
 416                 ranges->reader_wm_sets[num_valid_sets].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
 417                 ranges->reader_wm_sets[num_valid_sets].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
 418                 /* fclk wil be used to select WM*/
 419
 420                 if (ranges->reader_wm_sets[num_valid_sets].wm_type == WM_TYPE_PSTATE_CHG) {
 421                         if (i == 0)
 422                                 ranges->reader_wm_sets[num_valid_sets].min_fill_clk_mhz = 0;
 423                         else {
 424                                 /* add 1 to make it non-overlapping with next lvl */
 425                                 ranges->reader_wm_sets[num_valid_sets].min_fill_clk_mhz = bw_params->clk_table.entries[i - 1].fclk_mhz + 1;
 426                         }
 427                         ranges->reader_wm_sets[num_valid_sets].max_fill_clk_mhz = bw_params->clk_table.entries[i].fclk_mhz;
 428
 429                 } else {
 430                         /* unconstrained for memory retraining */
 431                         ranges->reader_wm_sets[num_valid_sets].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
 432                         ranges->reader_wm_sets[num_valid_sets].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
 433
 434                         /* Modify previous watermark range to cover up to max */
 435                         ranges->reader_wm_sets[num_valid_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
 436                 }
 437                 num_valid_sets++;
 438         }
 439
 440         ASSERT(num_valid_sets != 0); /* Must have at least one set of valid watermarks */
 441         ranges->num_reader_wm_sets = num_valid_sets;
 442
 443         /* modify the min and max to make sure we cover the whole range*/
 444         ranges->reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
 445         ranges->reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
 446         ranges->reader_wm_sets[ranges->num_reader_wm_sets - 1].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
 447         ranges->reader_wm_sets[ranges->num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
 448
 449         /* This is for writeback only, does not matter currently as no writeback support*/
 450         ranges->num_writer_wm_sets = 1;
 451         ranges->writer_wm_sets[0].wm_inst = WM_A;
 452         ranges->writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
 453         ranges->writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
 454         ranges->writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
 455         ranges->writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
 456
 457 }
 458
 459 static void rn_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
 460 {
 461         struct dc_debug_options *debug = &clk_mgr_base->ctx->dc->debug;
 462         struct pp_smu_wm_range_sets ranges = {0};
 463         struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
 464         struct pp_smu_funcs *pp_smu = clk_mgr->pp_smu;
 465
 466         if (!debug->disable_pplib_wm_range) {
 467                 build_watermark_ranges(clk_mgr_base->bw_params, &ranges);
 468
 469                 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
 470                 if (pp_smu && pp_smu->rn_funcs.set_wm_ranges)
 471                         pp_smu->rn_funcs.set_wm_ranges(&pp_smu->rn_funcs.pp_smu, &ranges);
 472         }
 473
 474 }
 475
 476 static bool rn_are_clock_states_equal(struct dc_clocks *a,
 477                 struct dc_clocks *b)
 478 {
 479         if (a->dispclk_khz != b->dispclk_khz)
 480                 return false;
 481         else if (a->dppclk_khz != b->dppclk_khz)
 482                 return false;
 483         else if (a->dcfclk_khz != b->dcfclk_khz)
 484                 return false;
 485         else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz)
 486                 return false;
 487
 488         return true;
 489 }
 490
 491
 492 static struct clk_mgr_funcs dcn21_funcs = {
 493         .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
 494         .update_clocks = rn_update_clocks,
 495         .init_clocks = rn_init_clocks,
 496         .enable_pme_wa = rn_enable_pme_wa,
 497         .are_clock_states_equal = rn_are_clock_states_equal,
 498         .notify_wm_ranges = rn_notify_wm_ranges
 499 };
 500
 501 struct clk_bw_params rn_bw_params = {
 502         .vram_type = Ddr4MemType,
 503         .num_channels = 1,
 504         .clk_table = {
 505                 .entries = {
 506                         {
 507                                 .voltage = 0,
 508                                 .dcfclk_mhz = 400,
 509                                 .fclk_mhz = 400,
 510                                 .memclk_mhz = 800,
 511                                 .socclk_mhz = 0,
 512                         },
 513                         {
 514                                 .voltage = 0,
 515                                 .dcfclk_mhz = 483,
 516                                 .fclk_mhz = 800,
 517                                 .memclk_mhz = 1600,
 518                                 .socclk_mhz = 0,
 519                         },
 520                         {
 521                                 .voltage = 0,
 522                                 .dcfclk_mhz = 602,
 523                                 .fclk_mhz = 1067,
 524                                 .memclk_mhz = 1067,
 525                                 .socclk_mhz = 0,
 526                         },
 527                         {
 528                                 .voltage = 0,
 529                                 .dcfclk_mhz = 738,
 530                                 .fclk_mhz = 1333,
 531                                 .memclk_mhz = 1600,
 532                                 .socclk_mhz = 0,
 533                         },
 534                 },
 535
 536                 .num_entries = 4,
 537         },
 538
 539 };
 540
 541 struct wm_table ddr4_wm_table = {
 542         .entries = {
 543                 {
 544                         .wm_inst = WM_A,
 545                         .wm_type = WM_TYPE_PSTATE_CHG,
 546                         .pstate_latency_us = 11.72,
 547                         .sr_exit_time_us = 6.09,
 548                         .sr_enter_plus_exit_time_us = 7.14,
 549                         .valid = true,
 550                 },
 551                 {
 552                         .wm_inst = WM_B,
 553                         .wm_type = WM_TYPE_PSTATE_CHG,
 554                         .pstate_latency_us = 11.72,
 555                         .sr_exit_time_us = 10.12,
 556                         .sr_enter_plus_exit_time_us = 11.48,
 557                         .valid = true,
 558                 },
 559                 {
 560                         .wm_inst = WM_C,
 561                         .wm_type = WM_TYPE_PSTATE_CHG,
 562                         .pstate_latency_us = 11.72,
 563                         .sr_exit_time_us = 10.12,
 564                         .sr_enter_plus_exit_time_us = 11.48,
 565                         .valid = true,
 566                 },
 567                 {
 568                         .wm_inst = WM_D,
 569                         .wm_type = WM_TYPE_PSTATE_CHG,
 570                         .pstate_latency_us = 11.72,
 571                         .sr_exit_time_us = 10.12,
 572                         .sr_enter_plus_exit_time_us = 11.48,
 573                         .valid = true,
 574                 },
 575         }
 576 };
 577
 578 struct wm_table lpddr4_wm_table = {
 579         .entries = {
 580                 {
 581                         .wm_inst = WM_A,
 582                         .wm_type = WM_TYPE_PSTATE_CHG,
 583                         .pstate_latency_us = 11.65333,
 584                         .sr_exit_time_us = 5.32,
 585                         .sr_enter_plus_exit_time_us = 6.38,
 586                         .valid = true,
 587                 },
 588                 {
 589                         .wm_inst = WM_B,
 590                         .wm_type = WM_TYPE_PSTATE_CHG,
 591                         .pstate_latency_us = 11.65333,
 592                         .sr_exit_time_us = 9.82,
 593                         .sr_enter_plus_exit_time_us = 11.196,
 594                         .valid = true,
 595                 },
 596                 {
 597                         .wm_inst = WM_C,
 598                         .wm_type = WM_TYPE_PSTATE_CHG,
 599                         .pstate_latency_us = 11.65333,
 600                         .sr_exit_time_us = 9.89,
 601                         .sr_enter_plus_exit_time_us = 11.24,
 602                         .valid = true,
 603                 },
 604                 {
 605                         .wm_inst = WM_D,
 606                         .wm_type = WM_TYPE_PSTATE_CHG,
 607                         .pstate_latency_us = 11.65333,
 608                         .sr_exit_time_us = 9.748,
 609                         .sr_enter_plus_exit_time_us = 11.102,
 610                         .valid = true,
 611                 },
 612         }
 613 };
 614
 615
 616 static unsigned int find_dcfclk_for_voltage(struct dpm_clocks *clock_table, unsigned int voltage)
 617 {
 618         int i;
 619
 620         for (i = 0; i < PP_SMU_NUM_DCFCLK_DPM_LEVELS; i++) {
 621                 if (clock_table->DcfClocks[i].Vol == voltage)
 622                         return clock_table->DcfClocks[i].Freq;
 623         }
 624
 625         ASSERT(0);
 626         return 0;
 627 }
 628
 629 static void rn_clk_mgr_helper_populate_bw_params(struct clk_bw_params *bw_params, struct dpm_clocks *clock_table, struct integrated_info *bios_info)
 630 {
 631         int i, j = 0;
 632
 633         j = -1;
 634
 635         ASSERT(PP_SMU_NUM_FCLK_DPM_LEVELS <= MAX_NUM_DPM_LVL);
 636
 637         /* Find lowest DPM, FCLK is filled in reverse order*/
 638
 639         for (i = PP_SMU_NUM_FCLK_DPM_LEVELS - 1; i >= 0; i--) {
 640                 if (clock_table->FClocks[i].Freq != 0) {
 641                         j = i;
 642                         break;
 643                 }
 644         }
 645
 646         if (j == -1) {
 647                 /* clock table is all 0s, just use our own hardcode */
 648                 ASSERT(0);
 649                 return;
 650         }
 651
 652         bw_params->clk_table.num_entries = j + 1;
 653
 654         for (i = 0; i < bw_params->clk_table.num_entries; i++, j--) {
 655                 bw_params->clk_table.entries[i].fclk_mhz = clock_table->FClocks[j].Freq;
 656                 bw_params->clk_table.entries[i].memclk_mhz = clock_table->MemClocks[j].Freq;
 657                 bw_params->clk_table.entries[i].voltage = clock_table->FClocks[j].Vol;
 658                 bw_params->clk_table.entries[i].dcfclk_mhz = find_dcfclk_for_voltage(clock_table, clock_table->FClocks[j].Vol);
 659         }
 660
 661         bw_params->vram_type = bios_info->memory_type;
 662         bw_params->num_channels = bios_info->ma_channel_number;
 663
 664         for (i = 0; i < WM_SET_COUNT; i++) {
 665                 bw_params->wm_table.entries[i].wm_inst = i;
 666
 667                 if (i >= bw_params->clk_table.num_entries) {
 668                         bw_params->wm_table.entries[i].valid = false;
 669                         continue;
 670                 }
 671
 672                 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG;
 673                 bw_params->wm_table.entries[i].valid = true;
 674         }
 675
 676         if (bw_params->vram_type == LpDdr4MemType) {
 677                 /*
 678                  * WM set D will be re-purposed for memory retraining
 679                  */
 680                 bw_params->wm_table.entries[WM_D].pstate_latency_us = LPDDR_MEM_RETRAIN_LATENCY;
 681                 bw_params->wm_table.entries[WM_D].wm_inst = WM_D;
 682                 bw_params->wm_table.entries[WM_D].wm_type = WM_TYPE_RETRAINING;
 683                 bw_params->wm_table.entries[WM_D].valid = true;
 684         }
 685
 686 }
 687
 688 void rn_clk_mgr_construct(
 689                 struct dc_context *ctx,
 690                 struct clk_mgr_internal *clk_mgr,
 691                 struct pp_smu_funcs *pp_smu,
 692                 struct dccg *dccg)
 693 {
 694         struct dc_debug_options *debug = &ctx->dc->debug;
 695         struct dpm_clocks clock_table = { 0 };
 696
 697         clk_mgr->base.ctx = ctx;
 698         clk_mgr->base.funcs = &dcn21_funcs;
 699
 700         clk_mgr->pp_smu = pp_smu;
 701
 702         clk_mgr->dccg = dccg;
 703         clk_mgr->dfs_bypass_disp_clk = 0;
 704
 705         clk_mgr->dprefclk_ss_percentage = 0;
 706         clk_mgr->dprefclk_ss_divider = 1000;
 707         clk_mgr->ss_on_dprefclk = false;
 708         clk_mgr->dfs_ref_freq_khz = 48000;
 709
 710         clk_mgr->smu_ver = rn_vbios_smu_get_smu_version(clk_mgr);
 711
 712         if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
 713                 dcn21_funcs.update_clocks = dcn2_update_clocks_fpga;
 714                 clk_mgr->base.dentist_vco_freq_khz = 3600000;
 715         } else {
 716                 struct clk_log_info log_info = {0};
 717
 718                 /* TODO: Check we get what we expect during bringup */
 719                 clk_mgr->base.dentist_vco_freq_khz = get_vco_frequency_from_reg(clk_mgr);
 720
 721                 /* in case we don't get a value from the register, use default */
 722                 if (clk_mgr->base.dentist_vco_freq_khz == 0)
 723                         clk_mgr->base.dentist_vco_freq_khz = 3600000;
 724
 725                 if (ctx->dc_bios->integrated_info->memory_type == LpDdr4MemType) {
 726                         rn_bw_params.wm_table = lpddr4_wm_table;
 727                 } else {
 728                         rn_bw_params.wm_table = ddr4_wm_table;
 729                 }
 730                 /* Saved clocks configured at boot for debug purposes */
 731                 rn_dump_clk_registers(&clk_mgr->base.boot_snapshot, &clk_mgr->base, &log_info);
 732         }
 733
 734         clk_mgr->base.dprefclk_khz = 600000;
 735         dce_clock_read_ss_info(clk_mgr);
 736
 737
 738         clk_mgr->base.bw_params = &rn_bw_params;
 739
 740         if (pp_smu && pp_smu->rn_funcs.get_dpm_clock_table) {
 741                 pp_smu->rn_funcs.get_dpm_clock_table(&pp_smu->rn_funcs.pp_smu, &clock_table);
 742                 if (ctx->dc_bios && ctx->dc_bios->integrated_info) {
 743                         rn_clk_mgr_helper_populate_bw_params (clk_mgr->base.bw_params, &clock_table, ctx->dc_bios->integrated_info);
 744                 }
 745         }
 746
 747         if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment) && clk_mgr->smu_ver >= 0x00371500) {
 748                 /* enable powerfeatures when displaycount goes to 0 */
 749                 rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(clk_mgr, !debug->disable_48mhz_pwrdwn);
 750         }
 751 }
 752