drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c

   1 /*
   2  * Copyright 2021 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "amdgpu_dm_psr.h"
  27 #include "dc.h"
  28 #include "dm_helpers.h"
  29 #include "amdgpu_dm.h"
  30
  31 #ifdef CONFIG_DRM_AMD_DC_DCN
  32 static bool link_supports_psrsu(struct dc_link *link)
  33 {
  34         struct dc *dc = link->ctx->dc;
  35
  36         if (!dc->caps.dmcub_support)
  37                 return false;
  38
  39         if (dc->ctx->dce_version < DCN_VERSION_3_1)
  40                 return false;
  41
  42         if (!link->dpcd_caps.alpm_caps.bits.AUX_WAKE_ALPM_CAP ||
  43             !link->dpcd_caps.psr_info.psr_dpcd_caps.bits.Y_COORDINATE_REQUIRED)
  44                 return false;
  45
  46         if (link->dpcd_caps.psr_info.psr_dpcd_caps.bits.SU_GRANULARITY_REQUIRED &&
  47             !link->dpcd_caps.psr_info.psr2_su_y_granularity_cap)
  48                 return false;
  49
  50         return true;
  51 }
  52 #endif
  53
  54 /*
  55  * amdgpu_dm_set_psr_caps() - set link psr capabilities
  56  * @link: link
  57  *
  58  */
  59 void amdgpu_dm_set_psr_caps(struct dc_link *link)
  60 {
  61         if (!(link->connector_signal & SIGNAL_TYPE_EDP))
  62                 return;
  63
  64         if (link->type == dc_connection_none)
  65                 return;
  66
  67         if (link->dpcd_caps.psr_info.psr_version == 0) {
  68                 link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
  69                 link->psr_settings.psr_feature_enabled = false;
  70
  71         } else {
  72 #ifdef CONFIG_DRM_AMD_DC_DCN
  73                 if (link_supports_psrsu(link))
  74                         link->psr_settings.psr_version = DC_PSR_VERSION_SU_1;
  75                 else
  76 #endif
  77                         link->psr_settings.psr_version = DC_PSR_VERSION_1;
  78
  79                 link->psr_settings.psr_feature_enabled = true;
  80         }
  81
  82         DRM_INFO("PSR support:%d\n", link->psr_settings.psr_feature_enabled);
  83
  84 }
  85
  86 /*
  87  * amdgpu_dm_link_setup_psr() - configure psr link
  88  * @stream: stream state
  89  *
  90  * Return: true if success
  91  */
  92 bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream)
  93 {
  94         struct dc_link *link = NULL;
  95         struct psr_config psr_config = {0};
  96         struct psr_context psr_context = {0};
  97         bool ret = false;
  98
  99         if (stream == NULL)
 100                 return false;
 101
 102         link = stream->link;
 103
 104         if (link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED) {
 105                 psr_config.psr_version = link->psr_settings.psr_version;
 106                 psr_config.psr_frame_capture_indication_req = 0;
 107                 psr_config.psr_rfb_setup_time = 0x37;
 108                 psr_config.psr_sdp_transmit_line_num_deadline = 0x20;
 109                 psr_config.allow_smu_optimizations = 0x0;
 110
 111                 ret = dc_link_setup_psr(link, stream, &psr_config, &psr_context);
 112
 113         }
 114         DRM_DEBUG_DRIVER("PSR link: %d\n",      link->psr_settings.psr_feature_enabled);
 115
 116         return ret;
 117 }
 118
 119 /*
 120  * amdgpu_dm_psr_enable() - enable psr f/w
 121  * @stream: stream state
 122  *
 123  * Return: true if success
 124  */
 125 bool amdgpu_dm_psr_enable(struct dc_stream_state *stream)
 126 {
 127         struct dc_link *link = stream->link;
 128         unsigned int vsync_rate_hz = 0;
 129         struct dc_static_screen_params params = {0};
 130         /* Calculate number of static frames before generating interrupt to
 131          * enter PSR.
 132          */
 133         // Init fail safe of 2 frames static
 134         unsigned int num_frames_static = 2;
 135         unsigned int power_opt = 0;
 136         bool psr_enable = true;
 137
 138         DRM_DEBUG_DRIVER("Enabling psr...\n");
 139
 140         vsync_rate_hz = div64_u64(div64_u64((
 141                         stream->timing.pix_clk_100hz * 100),
 142                         stream->timing.v_total),
 143                         stream->timing.h_total);
 144
 145         /* Round up
 146          * Calculate number of frames such that at least 30 ms of time has
 147          * passed.
 148          */
 149         if (vsync_rate_hz != 0) {
 150                 unsigned int frame_time_microsec = 1000000 / vsync_rate_hz;
 151                 num_frames_static = (30000 / frame_time_microsec) + 1;
 152         }
 153
 154         params.triggers.cursor_update = true;
 155         params.triggers.overlay_update = true;
 156         params.triggers.surface_update = true;
 157         params.num_frames = num_frames_static;
 158
 159         dc_stream_set_static_screen_params(link->ctx->dc,
 160                                            &stream, 1,
 161                                            &params);
 162
 163         power_opt |= psr_power_opt_z10_static_screen;
 164
 165         return dc_link_set_psr_allow_active(link, &psr_enable, false, false, &power_opt);
 166 }
 167
 168 /*
 169  * amdgpu_dm_psr_disable() - disable psr f/w
 170  * @stream:  stream state
 171  *
 172  * Return: true if success
 173  */
 174 bool amdgpu_dm_psr_disable(struct dc_stream_state *stream)
 175 {
 176         unsigned int power_opt = 0;
 177         bool psr_enable = false;
 178
 179         DRM_DEBUG_DRIVER("Disabling psr...\n");
 180
 181         return dc_link_set_psr_allow_active(stream->link, &psr_enable, true, false, &power_opt);
 182 }
 183
 184 /*
 185  * amdgpu_dm_psr_disable() - disable psr f/w
 186  * if psr is enabled on any stream
 187  *
 188  * Return: true if success
 189  */
 190 bool amdgpu_dm_psr_disable_all(struct amdgpu_display_manager *dm)
 191 {
 192         DRM_DEBUG_DRIVER("Disabling psr if psr is enabled on any stream\n");
 193         return dc_set_psr_allow_active(dm->dc, false);
 194 }
 195