drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c

   1 /*
   2  * Copyright 2021 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "amdgpu_dm_psr.h"
  27 #include "dc.h"
  28 #include "dm_helpers.h"
  29 #include "amdgpu_dm.h"
  30 #include "modules/power/power_helpers.h"
  31
  32 static bool link_supports_psrsu(struct dc_link *link)
  33 {
  34         struct dc *dc = link->ctx->dc;
  35
  36         if (!dc->caps.dmcub_support)
  37                 return false;
  38
  39         if (dc->ctx->dce_version < DCN_VERSION_3_1)
  40                 return false;
  41
  42         if (!is_psr_su_specific_panel(link))
  43                 return false;
  44
  45         if (!link->dpcd_caps.alpm_caps.bits.AUX_WAKE_ALPM_CAP ||
  46             !link->dpcd_caps.psr_info.psr_dpcd_caps.bits.Y_COORDINATE_REQUIRED)
  47                 return false;
  48
  49         if (link->dpcd_caps.psr_info.psr_dpcd_caps.bits.SU_GRANULARITY_REQUIRED &&
  50             !link->dpcd_caps.psr_info.psr2_su_y_granularity_cap)
  51                 return false;
  52
  53         return true;
  54 }
  55
  56 /*
  57  * amdgpu_dm_set_psr_caps() - set link psr capabilities
  58  * @link: link
  59  *
  60  */
  61 void amdgpu_dm_set_psr_caps(struct dc_link *link)
  62 {
  63         if (!(link->connector_signal & SIGNAL_TYPE_EDP)) {
  64                 link->psr_settings.psr_feature_enabled = false;
  65                 return;
  66         }
  67
  68         if (link->type == dc_connection_none) {
  69                 link->psr_settings.psr_feature_enabled = false;
  70                 return;
  71         }
  72
  73         if (link->dpcd_caps.psr_info.psr_version == 0) {
  74                 link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
  75                 link->psr_settings.psr_feature_enabled = false;
  76
  77         } else {
  78                 if (link_supports_psrsu(link))
  79                         link->psr_settings.psr_version = DC_PSR_VERSION_SU_1;
  80                 else
  81                         link->psr_settings.psr_version = DC_PSR_VERSION_1;
  82
  83                 link->psr_settings.psr_feature_enabled = true;
  84         }
  85
  86         DRM_INFO("PSR support %d, DC PSR ver %d, sink PSR ver %d DPCD caps 0x%x su_y_granularity %d\n",
  87                 link->psr_settings.psr_feature_enabled,
  88                 link->psr_settings.psr_version,
  89                 link->dpcd_caps.psr_info.psr_version,
  90                 link->dpcd_caps.psr_info.psr_dpcd_caps.raw,
  91                 link->dpcd_caps.psr_info.psr2_su_y_granularity_cap);
  92
  93 }
  94
  95 /*
  96  * amdgpu_dm_link_setup_psr() - configure psr link
  97  * @stream: stream state
  98  *
  99  * Return: true if success
 100  */
 101 bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream)
 102 {
 103         struct dc_link *link = NULL;
 104         struct psr_config psr_config = {0};
 105         struct psr_context psr_context = {0};
 106         struct dc *dc = NULL;
 107         bool ret = false;
 108
 109         if (stream == NULL)
 110                 return false;
 111
 112         link = stream->link;
 113         dc = link->ctx->dc;
 114
 115         if (link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED) {
 116                 mod_power_calc_psr_configs(&psr_config, link, stream);
 117
 118                 /* linux DM specific updating for psr config fields */
 119                 psr_config.allow_smu_optimizations =
 120                         (amdgpu_dc_feature_mask & DC_PSR_ALLOW_SMU_OPT) &&
 121                         mod_power_only_edp(dc->current_state, stream);
 122                 psr_config.allow_multi_disp_optimizations =
 123                         (amdgpu_dc_feature_mask & DC_PSR_ALLOW_MULTI_DISP_OPT);
 124
 125                 if (!psr_su_set_dsc_slice_height(dc, link, stream, &psr_config))
 126                         return false;
 127
 128                 ret = dc_link_setup_psr(link, stream, &psr_config, &psr_context);
 129
 130         }
 131         DRM_DEBUG_DRIVER("PSR link: %d\n",      link->psr_settings.psr_feature_enabled);
 132
 133         return ret;
 134 }
 135
 136 /*
 137  * amdgpu_dm_psr_enable() - enable psr f/w
 138  * @stream: stream state
 139  *
 140  * Return: true if success
 141  */
 142 bool amdgpu_dm_psr_enable(struct dc_stream_state *stream)
 143 {
 144         struct dc_link *link = stream->link;
 145         unsigned int vsync_rate_hz = 0;
 146         struct dc_static_screen_params params = {0};
 147         /* Calculate number of static frames before generating interrupt to
 148          * enter PSR.
 149          */
 150         // Init fail safe of 2 frames static
 151         unsigned int num_frames_static = 2;
 152         unsigned int power_opt = 0;
 153         bool psr_enable = true;
 154
 155         DRM_DEBUG_DRIVER("Enabling psr...\n");
 156
 157         vsync_rate_hz = div64_u64(div64_u64((
 158                         stream->timing.pix_clk_100hz * 100),
 159                         stream->timing.v_total),
 160                         stream->timing.h_total);
 161
 162         /* Round up
 163          * Calculate number of frames such that at least 30 ms of time has
 164          * passed.
 165          */
 166         if (vsync_rate_hz != 0) {
 167                 unsigned int frame_time_microsec = 1000000 / vsync_rate_hz;
 168                 num_frames_static = (30000 / frame_time_microsec) + 1;
 169         }
 170
 171         params.triggers.cursor_update = true;
 172         params.triggers.overlay_update = true;
 173         params.triggers.surface_update = true;
 174         params.num_frames = num_frames_static;
 175
 176         dc_stream_set_static_screen_params(link->ctx->dc,
 177                                            &stream, 1,
 178                                            &params);
 179
 180         /*
 181          * Only enable static-screen optimizations for PSR1. For PSR SU, this
 182          * causes vstartup interrupt issues, used by amdgpu_dm to send vblank
 183          * events.
 184          */
 185         if (link->psr_settings.psr_version < DC_PSR_VERSION_SU_1)
 186                 power_opt |= psr_power_opt_z10_static_screen;
 187
 188         return dc_link_set_psr_allow_active(link, &psr_enable, false, false, &power_opt);
 189 }
 190
 191 /*
 192  * amdgpu_dm_psr_disable() - disable psr f/w
 193  * @stream:  stream state
 194  *
 195  * Return: true if success
 196  */
 197 bool amdgpu_dm_psr_disable(struct dc_stream_state *stream)
 198 {
 199         unsigned int power_opt = 0;
 200         bool psr_enable = false;
 201
 202         DRM_DEBUG_DRIVER("Disabling psr...\n");
 203
 204         return dc_link_set_psr_allow_active(stream->link, &psr_enable, true, false, &power_opt);
 205 }
 206
 207 /*
 208  * amdgpu_dm_psr_disable() - disable psr f/w
 209  * if psr is enabled on any stream
 210  *
 211  * Return: true if success
 212  */
 213 bool amdgpu_dm_psr_disable_all(struct amdgpu_display_manager *dm)
 214 {
 215         DRM_DEBUG_DRIVER("Disabling psr if psr is enabled on any stream\n");
 216         return dc_set_psr_allow_active(dm->dc, false);
 217 }
 218