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26 #ifndef __DAL_AMDGPU_DM_MST_TYPES_H__
27 #define __DAL_AMDGPU_DM_MST_TYPES_H__
29 #define DP_BRANCH_DEVICE_ID_90CC24 0x90CC24
31 #define SYNAPTICS_RC_COMMAND 0x4B2
32 #define SYNAPTICS_RC_RESULT 0x4B3
33 #define SYNAPTICS_RC_LENGTH 0x4B8
34 #define SYNAPTICS_RC_OFFSET 0x4BC
35 #define SYNAPTICS_RC_DATA 0x4C0
37 struct amdgpu_display_manager;
38 struct amdgpu_dm_connector;
40 int dm_mst_get_pbn_divider(struct dc_link *link);
42 void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm,
43 struct amdgpu_dm_connector *aconnector,
47 dm_dp_create_fake_mst_encoders(struct amdgpu_device *adev);
49 struct dsc_mst_fairness_vars {
53 struct amdgpu_dm_connector *aconnector;
56 int compute_mst_dsc_configs_for_state(struct drm_atomic_state *state,
57 struct dc_state *dc_state,
58 struct dsc_mst_fairness_vars *vars);
60 bool needs_dsc_aux_workaround(struct dc_link *link);
62 int pre_validate_dsc(struct drm_atomic_state *state,
63 struct dm_atomic_state **dm_state_ptr,
64 struct dsc_mst_fairness_vars *vars);
66 enum dc_status dm_dp_mst_is_port_support_mode(
67 struct amdgpu_dm_connector *aconnector,
68 struct dc_stream_state *stream);