drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <drm/display/drm_dp_helper.h>
  27 #include <drm/display/drm_dp_mst_helper.h>
  28 #include <drm/drm_atomic.h>
  29 #include <drm/drm_atomic_helper.h>
  30 #include "dm_services.h"
  31 #include "amdgpu.h"
  32 #include "amdgpu_dm.h"
  33 #include "amdgpu_dm_mst_types.h"
  34
  35 #include "dc.h"
  36 #include "dm_helpers.h"
  37
  38 #include "dc_link_ddc.h"
  39 #include "dc_link_dp.h"
  40 #include "ddc_service_types.h"
  41 #include "dpcd_defs.h"
  42
  43 #include "i2caux_interface.h"
  44 #include "dmub_cmd.h"
  45 #if defined(CONFIG_DEBUG_FS)
  46 #include "amdgpu_dm_debugfs.h"
  47 #endif
  48
  49 #include "dc/dcn20/dcn20_resource.h"
  50 bool is_timing_changed(struct dc_stream_state *cur_stream,
  51                        struct dc_stream_state *new_stream);
  52
  53
  54 static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux,
  55                                   struct drm_dp_aux_msg *msg)
  56 {
  57         ssize_t result = 0;
  58         struct aux_payload payload;
  59         enum aux_return_code_type operation_result;
  60         struct amdgpu_device *adev;
  61         struct ddc_service *ddc;
  62
  63         if (WARN_ON(msg->size > 16))
  64                 return -E2BIG;
  65
  66         payload.address = msg->address;
  67         payload.data = msg->buffer;
  68         payload.length = msg->size;
  69         payload.reply = &msg->reply;
  70         payload.i2c_over_aux = (msg->request & DP_AUX_NATIVE_WRITE) == 0;
  71         payload.write = (msg->request & DP_AUX_I2C_READ) == 0;
  72         payload.mot = (msg->request & DP_AUX_I2C_MOT) != 0;
  73         payload.write_status_update =
  74                         (msg->request & DP_AUX_I2C_WRITE_STATUS_UPDATE) != 0;
  75         payload.defer_delay = 0;
  76
  77         result = dc_link_aux_transfer_raw(TO_DM_AUX(aux)->ddc_service, &payload,
  78                                       &operation_result);
  79
  80         /*
  81          * w/a on certain intel platform where hpd is unexpected to pull low during
  82          * 1st sideband message transaction by return AUX_RET_ERROR_HPD_DISCON
  83          * aux transaction is succuess in such case, therefore bypass the error
  84          */
  85         ddc = TO_DM_AUX(aux)->ddc_service;
  86         adev = ddc->ctx->driver_context;
  87         if (adev->dm.aux_hpd_discon_quirk) {
  88                 if (msg->address == DP_SIDEBAND_MSG_DOWN_REQ_BASE &&
  89                         operation_result == AUX_RET_ERROR_HPD_DISCON) {
  90                         result = 0;
  91                         operation_result = AUX_RET_SUCCESS;
  92                 }
  93         }
  94
  95         if (payload.write && result >= 0)
  96                 result = msg->size;
  97
  98         if (result < 0)
  99                 switch (operation_result) {
 100                 case AUX_RET_SUCCESS:
 101                         break;
 102                 case AUX_RET_ERROR_HPD_DISCON:
 103                 case AUX_RET_ERROR_UNKNOWN:
 104                 case AUX_RET_ERROR_INVALID_OPERATION:
 105                 case AUX_RET_ERROR_PROTOCOL_ERROR:
 106                         result = -EIO;
 107                         break;
 108                 case AUX_RET_ERROR_INVALID_REPLY:
 109                 case AUX_RET_ERROR_ENGINE_ACQUIRE:
 110                         result = -EBUSY;
 111                         break;
 112                 case AUX_RET_ERROR_TIMEOUT:
 113                         result = -ETIMEDOUT;
 114                         break;
 115                 }
 116
 117         return result;
 118 }
 119
 120 static void
 121 dm_dp_mst_connector_destroy(struct drm_connector *connector)
 122 {
 123         struct amdgpu_dm_connector *aconnector =
 124                 to_amdgpu_dm_connector(connector);
 125
 126         if (aconnector->dc_sink) {
 127                 dc_link_remove_remote_sink(aconnector->dc_link,
 128                                            aconnector->dc_sink);
 129                 dc_sink_release(aconnector->dc_sink);
 130         }
 131
 132         kfree(aconnector->edid);
 133
 134         drm_connector_cleanup(connector);
 135         drm_dp_mst_put_port_malloc(aconnector->port);
 136         kfree(aconnector);
 137 }
 138
 139 static int
 140 amdgpu_dm_mst_connector_late_register(struct drm_connector *connector)
 141 {
 142         struct amdgpu_dm_connector *amdgpu_dm_connector =
 143                 to_amdgpu_dm_connector(connector);
 144         int r;
 145
 146         r = drm_dp_mst_connector_late_register(connector,
 147                                                amdgpu_dm_connector->port);
 148         if (r < 0)
 149                 return r;
 150
 151 #if defined(CONFIG_DEBUG_FS)
 152         connector_debugfs_init(amdgpu_dm_connector);
 153 #endif
 154
 155         return 0;
 156 }
 157
 158 static void
 159 amdgpu_dm_mst_connector_early_unregister(struct drm_connector *connector)
 160 {
 161         struct amdgpu_dm_connector *aconnector =
 162                 to_amdgpu_dm_connector(connector);
 163         struct drm_dp_mst_port *port = aconnector->port;
 164         struct amdgpu_dm_connector *root = aconnector->mst_port;
 165         struct dc_link *dc_link = aconnector->dc_link;
 166         struct dc_sink *dc_sink = aconnector->dc_sink;
 167
 168         drm_dp_mst_connector_early_unregister(connector, port);
 169
 170         /*
 171          * Release dc_sink for connector which its attached port is
 172          * no longer in the mst topology
 173          */
 174         drm_modeset_lock(&root->mst_mgr.base.lock, NULL);
 175         if (dc_sink) {
 176                 if (dc_link->sink_count)
 177                         dc_link_remove_remote_sink(dc_link, dc_sink);
 178
 179                 dc_sink_release(dc_sink);
 180                 aconnector->dc_sink = NULL;
 181                 aconnector->edid = NULL;
 182         }
 183
 184         aconnector->mst_status = MST_STATUS_DEFAULT;
 185         drm_modeset_unlock(&root->mst_mgr.base.lock);
 186 }
 187
 188 static const struct drm_connector_funcs dm_dp_mst_connector_funcs = {
 189         .fill_modes = drm_helper_probe_single_connector_modes,
 190         .destroy = dm_dp_mst_connector_destroy,
 191         .reset = amdgpu_dm_connector_funcs_reset,
 192         .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
 193         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 194         .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
 195         .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
 196         .late_register = amdgpu_dm_mst_connector_late_register,
 197         .early_unregister = amdgpu_dm_mst_connector_early_unregister,
 198 };
 199
 200 #if defined(CONFIG_DRM_AMD_DC_DCN)
 201 bool needs_dsc_aux_workaround(struct dc_link *link)
 202 {
 203         if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 &&
 204             (link->dpcd_caps.dpcd_rev.raw == DPCD_REV_14 || link->dpcd_caps.dpcd_rev.raw == DPCD_REV_12) &&
 205             link->dpcd_caps.sink_count.bits.SINK_COUNT >= 2)
 206                 return true;
 207
 208         return false;
 209 }
 210
 211 static bool validate_dsc_caps_on_connector(struct amdgpu_dm_connector *aconnector)
 212 {
 213         struct dc_sink *dc_sink = aconnector->dc_sink;
 214         struct drm_dp_mst_port *port = aconnector->port;
 215         u8 dsc_caps[16] = { 0 };
 216         u8 dsc_branch_dec_caps_raw[3] = { 0 };  // DSC branch decoder caps 0xA0 ~ 0xA2
 217         u8 *dsc_branch_dec_caps = NULL;
 218
 219         aconnector->dsc_aux = drm_dp_mst_dsc_aux_for_port(port);
 220
 221         /*
 222          * drm_dp_mst_dsc_aux_for_port() will return NULL for certain configs
 223          * because it only check the dsc/fec caps of the "port variable" and not the dock
 224          *
 225          * This case will return NULL: DSC capabe MST dock connected to a non fec/dsc capable display
 226          *
 227          * Workaround: explicitly check the use case above and use the mst dock's aux as dsc_aux
 228          *
 229          */
 230         if (!aconnector->dsc_aux && !port->parent->port_parent &&
 231             needs_dsc_aux_workaround(aconnector->dc_link))
 232                 aconnector->dsc_aux = &aconnector->mst_port->dm_dp_aux.aux;
 233
 234         if (!aconnector->dsc_aux)
 235                 return false;
 236
 237         if (drm_dp_dpcd_read(aconnector->dsc_aux, DP_DSC_SUPPORT, dsc_caps, 16) < 0)
 238                 return false;
 239
 240         if (drm_dp_dpcd_read(aconnector->dsc_aux,
 241                         DP_DSC_BRANCH_OVERALL_THROUGHPUT_0, dsc_branch_dec_caps_raw, 3) == 3)
 242                 dsc_branch_dec_caps = dsc_branch_dec_caps_raw;
 243
 244         if (!dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
 245                                   dsc_caps, dsc_branch_dec_caps,
 246                                   &dc_sink->dsc_caps.dsc_dec_caps))
 247                 return false;
 248
 249         return true;
 250 }
 251
 252 static bool retrieve_downstream_port_device(struct amdgpu_dm_connector *aconnector)
 253 {
 254         union dp_downstream_port_present ds_port_present;
 255
 256         if (!aconnector->dsc_aux)
 257                 return false;
 258
 259         if (drm_dp_dpcd_read(aconnector->dsc_aux, DP_DOWNSTREAMPORT_PRESENT, &ds_port_present, 1) < 0) {
 260                 DRM_INFO("Failed to read downstream_port_present 0x05 from DFP of branch device\n");
 261                 return false;
 262         }
 263
 264         aconnector->mst_downstream_port_present = ds_port_present;
 265         DRM_INFO("Downstream port present %d, type %d\n",
 266                         ds_port_present.fields.PORT_PRESENT, ds_port_present.fields.PORT_TYPE);
 267
 268         return true;
 269 }
 270 #endif
 271
 272 static int dm_dp_mst_get_modes(struct drm_connector *connector)
 273 {
 274         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
 275         int ret = 0;
 276
 277         if (!aconnector)
 278                 return drm_add_edid_modes(connector, NULL);
 279
 280         if (!aconnector->edid) {
 281                 struct edid *edid;
 282                 edid = drm_dp_mst_get_edid(connector, &aconnector->mst_port->mst_mgr, aconnector->port);
 283
 284                 if (!edid) {
 285                         amdgpu_dm_set_mst_status(&aconnector->mst_status,
 286                         MST_REMOTE_EDID, false);
 287
 288                         drm_connector_update_edid_property(
 289                                 &aconnector->base,
 290                                 NULL);
 291
 292                         DRM_DEBUG_KMS("Can't get EDID of %s. Add default remote sink.", connector->name);
 293                         if (!aconnector->dc_sink) {
 294                                 struct dc_sink *dc_sink;
 295                                 struct dc_sink_init_data init_params = {
 296                                         .link = aconnector->dc_link,
 297                                         .sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST };
 298
 299                                 dc_sink = dc_link_add_remote_sink(
 300                                         aconnector->dc_link,
 301                                         NULL,
 302                                         0,
 303                                         &init_params);
 304
 305                                 if (!dc_sink) {
 306                                         DRM_ERROR("Unable to add a remote sink\n");
 307                                         return 0;
 308                                 }
 309
 310                                 dc_sink->priv = aconnector;
 311                                 aconnector->dc_sink = dc_sink;
 312                         }
 313
 314                         return ret;
 315                 }
 316
 317                 aconnector->edid = edid;
 318                 amdgpu_dm_set_mst_status(&aconnector->mst_status,
 319                         MST_REMOTE_EDID, true);
 320         }
 321
 322         if (aconnector->dc_sink && aconnector->dc_sink->sink_signal == SIGNAL_TYPE_VIRTUAL) {
 323                 dc_sink_release(aconnector->dc_sink);
 324                 aconnector->dc_sink = NULL;
 325         }
 326
 327         if (!aconnector->dc_sink) {
 328                 struct dc_sink *dc_sink;
 329                 struct dc_sink_init_data init_params = {
 330                                 .link = aconnector->dc_link,
 331                                 .sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST };
 332                 dc_sink = dc_link_add_remote_sink(
 333                         aconnector->dc_link,
 334                         (uint8_t *)aconnector->edid,
 335                         (aconnector->edid->extensions + 1) * EDID_LENGTH,
 336                         &init_params);
 337
 338                 if (!dc_sink) {
 339                         DRM_ERROR("Unable to add a remote sink\n");
 340                         return 0;
 341                 }
 342
 343                 dc_sink->priv = aconnector;
 344                 /* dc_link_add_remote_sink returns a new reference */
 345                 aconnector->dc_sink = dc_sink;
 346
 347                 if (aconnector->dc_sink) {
 348                         amdgpu_dm_update_freesync_caps(
 349                                         connector, aconnector->edid);
 350
 351 #if defined(CONFIG_DRM_AMD_DC_DCN)
 352                         if (!validate_dsc_caps_on_connector(aconnector))
 353                                 memset(&aconnector->dc_sink->dsc_caps,
 354                                        0, sizeof(aconnector->dc_sink->dsc_caps));
 355
 356                         if (!retrieve_downstream_port_device(aconnector))
 357                                 memset(&aconnector->mst_downstream_port_present,
 358                                         0, sizeof(aconnector->mst_downstream_port_present));
 359 #endif
 360                 }
 361         }
 362
 363         drm_connector_update_edid_property(
 364                                         &aconnector->base, aconnector->edid);
 365
 366         ret = drm_add_edid_modes(connector, aconnector->edid);
 367
 368         return ret;
 369 }
 370
 371 static struct drm_encoder *
 372 dm_mst_atomic_best_encoder(struct drm_connector *connector,
 373                            struct drm_atomic_state *state)
 374 {
 375         struct drm_connector_state *connector_state = drm_atomic_get_new_connector_state(state,
 376                                                                                          connector);
 377         struct drm_device *dev = connector->dev;
 378         struct amdgpu_device *adev = drm_to_adev(dev);
 379         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(connector_state->crtc);
 380
 381         return &adev->dm.mst_encoders[acrtc->crtc_id].base;
 382 }
 383
 384 static int
 385 dm_dp_mst_detect(struct drm_connector *connector,
 386                  struct drm_modeset_acquire_ctx *ctx, bool force)
 387 {
 388         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
 389         struct amdgpu_dm_connector *master = aconnector->mst_port;
 390         struct drm_dp_mst_port *port = aconnector->port;
 391         int connection_status;
 392
 393         if (drm_connector_is_unregistered(connector))
 394                 return connector_status_disconnected;
 395
 396         connection_status = drm_dp_mst_detect_port(connector, ctx, &master->mst_mgr,
 397                                                         aconnector->port);
 398
 399         if (port->pdt != DP_PEER_DEVICE_NONE && !port->dpcd_rev) {
 400                 uint8_t dpcd_rev;
 401                 int ret;
 402
 403                 ret = drm_dp_dpcd_readb(&port->aux, DP_DP13_DPCD_REV, &dpcd_rev);
 404
 405                 if (ret == 1) {
 406                         port->dpcd_rev = dpcd_rev;
 407
 408                         /* Could be DP1.2 DP Rx case*/
 409                         if (!dpcd_rev) {
 410                                 ret = drm_dp_dpcd_readb(&port->aux, DP_DPCD_REV, &dpcd_rev);
 411
 412                                 if (ret == 1)
 413                                         port->dpcd_rev = dpcd_rev;
 414                         }
 415
 416                         if (!dpcd_rev)
 417                                 DRM_DEBUG_KMS("Can't decide DPCD revision number!");
 418                 }
 419
 420                 /*
 421                  * Could be legacy sink, logical port etc on DP1.2.
 422                  * Will get Nack under these cases when issue remote
 423                  * DPCD read.
 424                  */
 425                 if (ret != 1)
 426                         DRM_DEBUG_KMS("Can't access DPCD");
 427         } else if (port->pdt == DP_PEER_DEVICE_NONE) {
 428                 port->dpcd_rev = 0;
 429         }
 430
 431         /*
 432          * Release dc_sink for connector which unplug event is notified by CSN msg
 433          */
 434         if (connection_status == connector_status_disconnected && aconnector->dc_sink) {
 435                 if (aconnector->dc_link->sink_count)
 436                         dc_link_remove_remote_sink(aconnector->dc_link, aconnector->dc_sink);
 437
 438                 dc_sink_release(aconnector->dc_sink);
 439                 aconnector->dc_sink = NULL;
 440                 aconnector->edid = NULL;
 441
 442                 amdgpu_dm_set_mst_status(&aconnector->mst_status,
 443                         MST_REMOTE_EDID | MST_ALLOCATE_NEW_PAYLOAD | MST_CLEAR_ALLOCATED_PAYLOAD,
 444                         false);
 445         }
 446
 447         return connection_status;
 448 }
 449
 450 static int dm_dp_mst_atomic_check(struct drm_connector *connector,
 451                                   struct drm_atomic_state *state)
 452 {
 453         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
 454         struct drm_dp_mst_topology_mgr *mst_mgr = &aconnector->mst_port->mst_mgr;
 455         struct drm_dp_mst_port *mst_port = aconnector->port;
 456
 457         return drm_dp_atomic_release_time_slots(state, mst_mgr, mst_port);
 458 }
 459
 460 static const struct drm_connector_helper_funcs dm_dp_mst_connector_helper_funcs = {
 461         .get_modes = dm_dp_mst_get_modes,
 462         .mode_valid = amdgpu_dm_connector_mode_valid,
 463         .atomic_best_encoder = dm_mst_atomic_best_encoder,
 464         .detect_ctx = dm_dp_mst_detect,
 465         .atomic_check = dm_dp_mst_atomic_check,
 466 };
 467
 468 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
 469 {
 470         drm_encoder_cleanup(encoder);
 471         kfree(encoder);
 472 }
 473
 474 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
 475         .destroy = amdgpu_dm_encoder_destroy,
 476 };
 477
 478 void
 479 dm_dp_create_fake_mst_encoders(struct amdgpu_device *adev)
 480 {
 481         struct drm_device *dev = adev_to_drm(adev);
 482         int i;
 483
 484         for (i = 0; i < adev->dm.display_indexes_num; i++) {
 485                 struct amdgpu_encoder *amdgpu_encoder = &adev->dm.mst_encoders[i];
 486                 struct drm_encoder *encoder = &amdgpu_encoder->base;
 487
 488                 encoder->possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
 489
 490                 drm_encoder_init(
 491                         dev,
 492                         &amdgpu_encoder->base,
 493                         &amdgpu_dm_encoder_funcs,
 494                         DRM_MODE_ENCODER_DPMST,
 495                         NULL);
 496
 497                 drm_encoder_helper_add(encoder, &amdgpu_dm_encoder_helper_funcs);
 498         }
 499 }
 500
 501 static struct drm_connector *
 502 dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
 503                         struct drm_dp_mst_port *port,
 504                         const char *pathprop)
 505 {
 506         struct amdgpu_dm_connector *master = container_of(mgr, struct amdgpu_dm_connector, mst_mgr);
 507         struct drm_device *dev = master->base.dev;
 508         struct amdgpu_device *adev = drm_to_adev(dev);
 509         struct amdgpu_dm_connector *aconnector;
 510         struct drm_connector *connector;
 511         int i;
 512
 513         aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
 514         if (!aconnector)
 515                 return NULL;
 516
 517         connector = &aconnector->base;
 518         aconnector->port = port;
 519         aconnector->mst_port = master;
 520         amdgpu_dm_set_mst_status(&aconnector->mst_status,
 521                         MST_PROBE, true);
 522
 523         if (drm_connector_init(
 524                 dev,
 525                 connector,
 526                 &dm_dp_mst_connector_funcs,
 527                 DRM_MODE_CONNECTOR_DisplayPort)) {
 528                 kfree(aconnector);
 529                 return NULL;
 530         }
 531         drm_connector_helper_add(connector, &dm_dp_mst_connector_helper_funcs);
 532
 533         amdgpu_dm_connector_init_helper(
 534                 &adev->dm,
 535                 aconnector,
 536                 DRM_MODE_CONNECTOR_DisplayPort,
 537                 master->dc_link,
 538                 master->connector_id);
 539
 540         for (i = 0; i < adev->dm.display_indexes_num; i++) {
 541                 drm_connector_attach_encoder(&aconnector->base,
 542                                              &adev->dm.mst_encoders[i].base);
 543         }
 544
 545         connector->max_bpc_property = master->base.max_bpc_property;
 546         if (connector->max_bpc_property)
 547                 drm_connector_attach_max_bpc_property(connector, 8, 16);
 548
 549         connector->vrr_capable_property = master->base.vrr_capable_property;
 550         if (connector->vrr_capable_property)
 551                 drm_connector_attach_vrr_capable_property(connector);
 552
 553         drm_object_attach_property(
 554                 &connector->base,
 555                 dev->mode_config.path_property,
 556                 0);
 557         drm_object_attach_property(
 558                 &connector->base,
 559                 dev->mode_config.tile_property,
 560                 0);
 561
 562         drm_connector_set_path_property(connector, pathprop);
 563
 564         /*
 565          * Initialize connector state before adding the connectror to drm and
 566          * framebuffer lists
 567          */
 568         amdgpu_dm_connector_funcs_reset(connector);
 569
 570         drm_dp_mst_get_port_malloc(port);
 571
 572         return connector;
 573 }
 574
 575 static const struct drm_dp_mst_topology_cbs dm_mst_cbs = {
 576         .add_connector = dm_dp_add_mst_connector,
 577 };
 578
 579 void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm,
 580                                        struct amdgpu_dm_connector *aconnector,
 581                                        int link_index)
 582 {
 583         struct dc_link_settings max_link_enc_cap = {0};
 584
 585         aconnector->dm_dp_aux.aux.name =
 586                 kasprintf(GFP_KERNEL, "AMDGPU DM aux hw bus %d",
 587                           link_index);
 588         aconnector->dm_dp_aux.aux.transfer = dm_dp_aux_transfer;
 589         aconnector->dm_dp_aux.aux.drm_dev = dm->ddev;
 590         aconnector->dm_dp_aux.ddc_service = aconnector->dc_link->ddc;
 591
 592         drm_dp_aux_init(&aconnector->dm_dp_aux.aux);
 593         drm_dp_cec_register_connector(&aconnector->dm_dp_aux.aux,
 594                                       &aconnector->base);
 595
 596         if (aconnector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
 597                 return;
 598
 599         dc_link_dp_get_max_link_enc_cap(aconnector->dc_link, &max_link_enc_cap);
 600         aconnector->mst_mgr.cbs = &dm_mst_cbs;
 601         drm_dp_mst_topology_mgr_init(&aconnector->mst_mgr, adev_to_drm(dm->adev),
 602                                      &aconnector->dm_dp_aux.aux, 16, 4, aconnector->connector_id);
 603
 604         drm_connector_attach_dp_subconnector_property(&aconnector->base);
 605 }
 606
 607 int dm_mst_get_pbn_divider(struct dc_link *link)
 608 {
 609         if (!link)
 610                 return 0;
 611
 612         return dc_link_bandwidth_kbps(link,
 613                         dc_link_get_link_cap(link)) / (8 * 1000 * 54);
 614 }
 615
 616 #if defined(CONFIG_DRM_AMD_DC_DCN)
 617
 618 struct dsc_mst_fairness_params {
 619         struct dc_crtc_timing *timing;
 620         struct dc_sink *sink;
 621         struct dc_dsc_bw_range bw_range;
 622         bool compression_possible;
 623         struct drm_dp_mst_port *port;
 624         enum dsc_clock_force_state clock_force_enable;
 625         uint32_t num_slices_h;
 626         uint32_t num_slices_v;
 627         uint32_t bpp_overwrite;
 628         struct amdgpu_dm_connector *aconnector;
 629 };
 630
 631 static int kbps_to_peak_pbn(int kbps)
 632 {
 633         u64 peak_kbps = kbps;
 634
 635         peak_kbps *= 1006;
 636         peak_kbps = div_u64(peak_kbps, 1000);
 637         return (int) DIV64_U64_ROUND_UP(peak_kbps * 64, (54 * 8 * 1000));
 638 }
 639
 640 static void set_dsc_configs_from_fairness_vars(struct dsc_mst_fairness_params *params,
 641                 struct dsc_mst_fairness_vars *vars,
 642                 int count,
 643                 int k)
 644 {
 645         int i;
 646
 647         for (i = 0; i < count; i++) {
 648                 memset(&params[i].timing->dsc_cfg, 0, sizeof(params[i].timing->dsc_cfg));
 649                 if (vars[i + k].dsc_enabled && dc_dsc_compute_config(
 650                                         params[i].sink->ctx->dc->res_pool->dscs[0],
 651                                         &params[i].sink->dsc_caps.dsc_dec_caps,
 652                                         params[i].sink->ctx->dc->debug.dsc_min_slice_height_override,
 653                                         params[i].sink->edid_caps.panel_patch.max_dsc_target_bpp_limit,
 654                                         0,
 655                                         params[i].timing,
 656                                         &params[i].timing->dsc_cfg)) {
 657                         params[i].timing->flags.DSC = 1;
 658
 659                         if (params[i].bpp_overwrite)
 660                                 params[i].timing->dsc_cfg.bits_per_pixel = params[i].bpp_overwrite;
 661                         else
 662                                 params[i].timing->dsc_cfg.bits_per_pixel = vars[i + k].bpp_x16;
 663
 664                         if (params[i].num_slices_h)
 665                                 params[i].timing->dsc_cfg.num_slices_h = params[i].num_slices_h;
 666
 667                         if (params[i].num_slices_v)
 668                                 params[i].timing->dsc_cfg.num_slices_v = params[i].num_slices_v;
 669                 } else {
 670                         params[i].timing->flags.DSC = 0;
 671                 }
 672                 params[i].timing->dsc_cfg.mst_pbn = vars[i + k].pbn;
 673         }
 674
 675         for (i = 0; i < count; i++) {
 676                 if (params[i].sink) {
 677                         if (params[i].sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&
 678                                 params[i].sink->sink_signal != SIGNAL_TYPE_NONE)
 679                                 DRM_DEBUG_DRIVER("%s i=%d dispname=%s\n", __func__, i,
 680                                         params[i].sink->edid_caps.display_name);
 681                 }
 682
 683                 DRM_DEBUG_DRIVER("dsc=%d bits_per_pixel=%d pbn=%d\n",
 684                         params[i].timing->flags.DSC,
 685                         params[i].timing->dsc_cfg.bits_per_pixel,
 686                         vars[i + k].pbn);
 687         }
 688 }
 689
 690 static int bpp_x16_from_pbn(struct dsc_mst_fairness_params param, int pbn)
 691 {
 692         struct dc_dsc_config dsc_config;
 693         u64 kbps;
 694
 695         kbps = div_u64((u64)pbn * 994 * 8 * 54, 64);
 696         dc_dsc_compute_config(
 697                         param.sink->ctx->dc->res_pool->dscs[0],
 698                         &param.sink->dsc_caps.dsc_dec_caps,
 699                         param.sink->ctx->dc->debug.dsc_min_slice_height_override,
 700                         param.sink->edid_caps.panel_patch.max_dsc_target_bpp_limit,
 701                         (int) kbps, param.timing, &dsc_config);
 702
 703         return dsc_config.bits_per_pixel;
 704 }
 705
 706 static bool increase_dsc_bpp(struct drm_atomic_state *state,
 707                              struct drm_dp_mst_topology_state *mst_state,
 708                              struct dc_link *dc_link,
 709                              struct dsc_mst_fairness_params *params,
 710                              struct dsc_mst_fairness_vars *vars,
 711                              int count,
 712                              int k)
 713 {
 714         int i;
 715         bool bpp_increased[MAX_PIPES];
 716         int initial_slack[MAX_PIPES];
 717         int min_initial_slack;
 718         int next_index;
 719         int remaining_to_increase = 0;
 720         int link_timeslots_used;
 721         int fair_pbn_alloc;
 722
 723         for (i = 0; i < count; i++) {
 724                 if (vars[i + k].dsc_enabled) {
 725                         initial_slack[i] =
 726                         kbps_to_peak_pbn(params[i].bw_range.max_kbps) - vars[i + k].pbn;
 727                         bpp_increased[i] = false;
 728                         remaining_to_increase += 1;
 729                 } else {
 730                         initial_slack[i] = 0;
 731                         bpp_increased[i] = true;
 732                 }
 733         }
 734
 735         while (remaining_to_increase) {
 736                 next_index = -1;
 737                 min_initial_slack = -1;
 738                 for (i = 0; i < count; i++) {
 739                         if (!bpp_increased[i]) {
 740                                 if (min_initial_slack == -1 || min_initial_slack > initial_slack[i]) {
 741                                         min_initial_slack = initial_slack[i];
 742                                         next_index = i;
 743                                 }
 744                         }
 745                 }
 746
 747                 if (next_index == -1)
 748                         break;
 749
 750                 link_timeslots_used = 0;
 751
 752                 for (i = 0; i < count; i++)
 753                         link_timeslots_used += DIV_ROUND_UP(vars[i + k].pbn, mst_state->pbn_div);
 754
 755                 fair_pbn_alloc =
 756                         (63 - link_timeslots_used) / remaining_to_increase * mst_state->pbn_div;
 757
 758                 if (initial_slack[next_index] > fair_pbn_alloc) {
 759                         vars[next_index].pbn += fair_pbn_alloc;
 760                         if (drm_dp_atomic_find_time_slots(state,
 761                                                           params[next_index].port->mgr,
 762                                                           params[next_index].port,
 763                                                           vars[next_index].pbn) < 0)
 764                                 return false;
 765                         if (!drm_dp_mst_atomic_check(state)) {
 766                                 vars[next_index].bpp_x16 = bpp_x16_from_pbn(params[next_index], vars[next_index].pbn);
 767                         } else {
 768                                 vars[next_index].pbn -= fair_pbn_alloc;
 769                                 if (drm_dp_atomic_find_time_slots(state,
 770                                                                   params[next_index].port->mgr,
 771                                                                   params[next_index].port,
 772                                                                   vars[next_index].pbn) < 0)
 773                                         return false;
 774                         }
 775                 } else {
 776                         vars[next_index].pbn += initial_slack[next_index];
 777                         if (drm_dp_atomic_find_time_slots(state,
 778                                                           params[next_index].port->mgr,
 779                                                           params[next_index].port,
 780                                                           vars[next_index].pbn) < 0)
 781                                 return false;
 782                         if (!drm_dp_mst_atomic_check(state)) {
 783                                 vars[next_index].bpp_x16 = params[next_index].bw_range.max_target_bpp_x16;
 784                         } else {
 785                                 vars[next_index].pbn -= initial_slack[next_index];
 786                                 if (drm_dp_atomic_find_time_slots(state,
 787                                                                   params[next_index].port->mgr,
 788                                                                   params[next_index].port,
 789                                                                   vars[next_index].pbn) < 0)
 790                                         return false;
 791                         }
 792                 }
 793
 794                 bpp_increased[next_index] = true;
 795                 remaining_to_increase--;
 796         }
 797         return true;
 798 }
 799
 800 static bool try_disable_dsc(struct drm_atomic_state *state,
 801                             struct dc_link *dc_link,
 802                             struct dsc_mst_fairness_params *params,
 803                             struct dsc_mst_fairness_vars *vars,
 804                             int count,
 805                             int k)
 806 {
 807         int i;
 808         bool tried[MAX_PIPES];
 809         int kbps_increase[MAX_PIPES];
 810         int max_kbps_increase;
 811         int next_index;
 812         int remaining_to_try = 0;
 813
 814         for (i = 0; i < count; i++) {
 815                 if (vars[i + k].dsc_enabled
 816                                 && vars[i + k].bpp_x16 == params[i].bw_range.max_target_bpp_x16
 817                                 && params[i].clock_force_enable == DSC_CLK_FORCE_DEFAULT) {
 818                         kbps_increase[i] = params[i].bw_range.stream_kbps - params[i].bw_range.max_kbps;
 819                         tried[i] = false;
 820                         remaining_to_try += 1;
 821                 } else {
 822                         kbps_increase[i] = 0;
 823                         tried[i] = true;
 824                 }
 825         }
 826
 827         while (remaining_to_try) {
 828                 next_index = -1;
 829                 max_kbps_increase = -1;
 830                 for (i = 0; i < count; i++) {
 831                         if (!tried[i]) {
 832                                 if (max_kbps_increase == -1 || max_kbps_increase < kbps_increase[i]) {
 833                                         max_kbps_increase = kbps_increase[i];
 834                                         next_index = i;
 835                                 }
 836                         }
 837                 }
 838
 839                 if (next_index == -1)
 840                         break;
 841
 842                 vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.stream_kbps);
 843                 if (drm_dp_atomic_find_time_slots(state,
 844                                                   params[next_index].port->mgr,
 845                                                   params[next_index].port,
 846                                                   vars[next_index].pbn) < 0)
 847                         return false;
 848
 849                 if (!drm_dp_mst_atomic_check(state)) {
 850                         vars[next_index].dsc_enabled = false;
 851                         vars[next_index].bpp_x16 = 0;
 852                 } else {
 853                         vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.max_kbps);
 854                         if (drm_dp_atomic_find_time_slots(state,
 855                                                           params[next_index].port->mgr,
 856                                                           params[next_index].port,
 857                                                           vars[next_index].pbn) < 0)
 858                                 return false;
 859                 }
 860
 861                 tried[next_index] = true;
 862                 remaining_to_try--;
 863         }
 864         return true;
 865 }
 866
 867 static bool compute_mst_dsc_configs_for_link(struct drm_atomic_state *state,
 868                                              struct dc_state *dc_state,
 869                                              struct dc_link *dc_link,
 870                                              struct dsc_mst_fairness_vars *vars,
 871                                              struct drm_dp_mst_topology_mgr *mgr,
 872                                              int *link_vars_start_index)
 873 {
 874         struct dc_stream_state *stream;
 875         struct dsc_mst_fairness_params params[MAX_PIPES];
 876         struct amdgpu_dm_connector *aconnector;
 877         struct drm_dp_mst_topology_state *mst_state = drm_atomic_get_mst_topology_state(state, mgr);
 878         int count = 0;
 879         int i, k;
 880         bool debugfs_overwrite = false;
 881
 882         memset(params, 0, sizeof(params));
 883
 884         if (IS_ERR(mst_state))
 885                 return false;
 886
 887         mst_state->pbn_div = dm_mst_get_pbn_divider(dc_link);
 888 #if defined(CONFIG_DRM_AMD_DC_DCN)
 889         drm_dp_mst_update_slots(mst_state, dc_link_dp_mst_decide_link_encoding_format(dc_link));
 890 #endif
 891
 892         /* Set up params */
 893         for (i = 0; i < dc_state->stream_count; i++) {
 894                 struct dc_dsc_policy dsc_policy = {0};
 895
 896                 stream = dc_state->streams[i];
 897
 898                 if (stream->link != dc_link)
 899                         continue;
 900
 901                 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
 902                 if (!aconnector)
 903                         continue;
 904
 905                 if (!aconnector->port)
 906                         continue;
 907
 908                 stream->timing.flags.DSC = 0;
 909
 910                 params[count].timing = &stream->timing;
 911                 params[count].sink = stream->sink;
 912                 params[count].aconnector = aconnector;
 913                 params[count].port = aconnector->port;
 914                 params[count].clock_force_enable = aconnector->dsc_settings.dsc_force_enable;
 915                 if (params[count].clock_force_enable == DSC_CLK_FORCE_ENABLE)
 916                         debugfs_overwrite = true;
 917                 params[count].num_slices_h = aconnector->dsc_settings.dsc_num_slices_h;
 918                 params[count].num_slices_v = aconnector->dsc_settings.dsc_num_slices_v;
 919                 params[count].bpp_overwrite = aconnector->dsc_settings.dsc_bits_per_pixel;
 920                 params[count].compression_possible = stream->sink->dsc_caps.dsc_dec_caps.is_dsc_supported;
 921                 dc_dsc_get_policy_for_timing(params[count].timing, 0, &dsc_policy);
 922                 if (!dc_dsc_compute_bandwidth_range(
 923                                 stream->sink->ctx->dc->res_pool->dscs[0],
 924                                 stream->sink->ctx->dc->debug.dsc_min_slice_height_override,
 925                                 dsc_policy.min_target_bpp * 16,
 926                                 dsc_policy.max_target_bpp * 16,
 927                                 &stream->sink->dsc_caps.dsc_dec_caps,
 928                                 &stream->timing, &params[count].bw_range))
 929                         params[count].bw_range.stream_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing);
 930
 931                 count++;
 932         }
 933
 934         if (count == 0) {
 935                 ASSERT(0);
 936                 return true;
 937         }
 938
 939         /* k is start index of vars for current phy link used by mst hub */
 940         k = *link_vars_start_index;
 941         /* set vars start index for next mst hub phy link */
 942         *link_vars_start_index += count;
 943
 944         /* Try no compression */
 945         for (i = 0; i < count; i++) {
 946                 vars[i + k].aconnector = params[i].aconnector;
 947                 vars[i + k].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps);
 948                 vars[i + k].dsc_enabled = false;
 949                 vars[i + k].bpp_x16 = 0;
 950                 if (drm_dp_atomic_find_time_slots(state, params[i].port->mgr, params[i].port,
 951                                                   vars[i + k].pbn) < 0)
 952                         return false;
 953         }
 954         if (!drm_dp_mst_atomic_check(state) && !debugfs_overwrite) {
 955                 set_dsc_configs_from_fairness_vars(params, vars, count, k);
 956                 return true;
 957         }
 958
 959         /* Try max compression */
 960         for (i = 0; i < count; i++) {
 961                 if (params[i].compression_possible && params[i].clock_force_enable != DSC_CLK_FORCE_DISABLE) {
 962                         vars[i + k].pbn = kbps_to_peak_pbn(params[i].bw_range.min_kbps);
 963                         vars[i + k].dsc_enabled = true;
 964                         vars[i + k].bpp_x16 = params[i].bw_range.min_target_bpp_x16;
 965                         if (drm_dp_atomic_find_time_slots(state, params[i].port->mgr,
 966                                                           params[i].port, vars[i + k].pbn) < 0)
 967                                 return false;
 968                 } else {
 969                         vars[i + k].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps);
 970                         vars[i + k].dsc_enabled = false;
 971                         vars[i + k].bpp_x16 = 0;
 972                         if (drm_dp_atomic_find_time_slots(state, params[i].port->mgr,
 973                                                           params[i].port, vars[i + k].pbn) < 0)
 974                                 return false;
 975                 }
 976         }
 977         if (drm_dp_mst_atomic_check(state))
 978                 return false;
 979
 980         /* Optimize degree of compression */
 981         if (!increase_dsc_bpp(state, mst_state, dc_link, params, vars, count, k))
 982                 return false;
 983
 984         if (!try_disable_dsc(state, dc_link, params, vars, count, k))
 985                 return false;
 986
 987         set_dsc_configs_from_fairness_vars(params, vars, count, k);
 988
 989         return true;
 990 }
 991
 992 static bool is_dsc_need_re_compute(
 993         struct drm_atomic_state *state,
 994         struct dc_state *dc_state,
 995         struct dc_link *dc_link)
 996 {
 997         int i, j;
 998         bool is_dsc_need_re_compute = false;
 999         struct amdgpu_dm_connector *stream_on_link[MAX_PIPES];
1000         int new_stream_on_link_num = 0;
1001         struct amdgpu_dm_connector *aconnector;
1002         struct dc_stream_state *stream;
1003         const struct dc *dc = dc_link->dc;
1004
1005         /* only check phy used by dsc mst branch */
1006         if (dc_link->type != dc_connection_mst_branch)
1007                 return false;
1008
1009         if (!(dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT ||
1010                 dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_PASSTHROUGH_SUPPORT))
1011                 return false;
1012
1013         for (i = 0; i < MAX_PIPES; i++)
1014                 stream_on_link[i] = NULL;
1015
1016         /* check if there is mode change in new request */
1017         for (i = 0; i < dc_state->stream_count; i++) {
1018                 struct drm_crtc_state *new_crtc_state;
1019                 struct drm_connector_state *new_conn_state;
1020
1021                 stream = dc_state->streams[i];
1022                 if (!stream)
1023                         continue;
1024
1025                 /* check if stream using the same link for mst */
1026                 if (stream->link != dc_link)
1027                         continue;
1028
1029                 aconnector = (struct amdgpu_dm_connector *) stream->dm_stream_context;
1030                 if (!aconnector)
1031                         continue;
1032
1033                 stream_on_link[new_stream_on_link_num] = aconnector;
1034                 new_stream_on_link_num++;
1035
1036                 new_conn_state = drm_atomic_get_new_connector_state(state, &aconnector->base);
1037                 if (!new_conn_state)
1038                         continue;
1039
1040                 if (IS_ERR(new_conn_state))
1041                         continue;
1042
1043                 if (!new_conn_state->crtc)
1044                         continue;
1045
1046                 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
1047                 if (!new_crtc_state)
1048                         continue;
1049
1050                 if (IS_ERR(new_crtc_state))
1051                         continue;
1052
1053                 if (new_crtc_state->enable && new_crtc_state->active) {
1054                         if (new_crtc_state->mode_changed || new_crtc_state->active_changed ||
1055                                 new_crtc_state->connectors_changed)
1056                                 return true;
1057                 }
1058         }
1059
1060         /* check current_state if there stream on link but it is not in
1061          * new request state
1062          */
1063         for (i = 0; i < dc->current_state->stream_count; i++) {
1064                 stream = dc->current_state->streams[i];
1065                 /* only check stream on the mst hub */
1066                 if (stream->link != dc_link)
1067                         continue;
1068
1069                 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
1070                 if (!aconnector)
1071                         continue;
1072
1073                 for (j = 0; j < new_stream_on_link_num; j++) {
1074                         if (stream_on_link[j]) {
1075                                 if (aconnector == stream_on_link[j])
1076                                         break;
1077                         }
1078                 }
1079
1080                 if (j == new_stream_on_link_num) {
1081                         /* not in new state */
1082                         is_dsc_need_re_compute = true;
1083                         break;
1084                 }
1085         }
1086
1087         return is_dsc_need_re_compute;
1088 }
1089
1090 bool compute_mst_dsc_configs_for_state(struct drm_atomic_state *state,
1091                                        struct dc_state *dc_state,
1092                                        struct dsc_mst_fairness_vars *vars)
1093 {
1094         int i, j;
1095         struct dc_stream_state *stream;
1096         bool computed_streams[MAX_PIPES];
1097         struct amdgpu_dm_connector *aconnector;
1098         int link_vars_start_index = 0;
1099
1100         for (i = 0; i < dc_state->stream_count; i++)
1101                 computed_streams[i] = false;
1102
1103         for (i = 0; i < dc_state->stream_count; i++) {
1104                 stream = dc_state->streams[i];
1105
1106                 if (stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST)
1107                         continue;
1108
1109                 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
1110
1111                 if (!aconnector || !aconnector->dc_sink)
1112                         continue;
1113
1114                 if (!aconnector->dc_sink->dsc_caps.dsc_dec_caps.is_dsc_supported)
1115                         continue;
1116
1117                 if (computed_streams[i])
1118                         continue;
1119
1120                 if (dcn20_remove_stream_from_ctx(stream->ctx->dc, dc_state, stream) != DC_OK)
1121                         return false;
1122
1123                 if (!is_dsc_need_re_compute(state, dc_state, stream->link))
1124                         continue;
1125
1126                 mutex_lock(&aconnector->mst_mgr.lock);
1127                 if (!compute_mst_dsc_configs_for_link(state, dc_state, stream->link, vars,
1128                                                       &aconnector->mst_mgr,
1129                                                       &link_vars_start_index)) {
1130                         mutex_unlock(&aconnector->mst_mgr.lock);
1131                         return false;
1132                 }
1133                 mutex_unlock(&aconnector->mst_mgr.lock);
1134
1135                 for (j = 0; j < dc_state->stream_count; j++) {
1136                         if (dc_state->streams[j]->link == stream->link)
1137                                 computed_streams[j] = true;
1138                 }
1139         }
1140
1141         for (i = 0; i < dc_state->stream_count; i++) {
1142                 stream = dc_state->streams[i];
1143
1144                 if (stream->timing.flags.DSC == 1)
1145                         if (dc_stream_add_dsc_to_resource(stream->ctx->dc, dc_state, stream) != DC_OK)
1146                                 return false;
1147         }
1148
1149         return true;
1150 }
1151
1152 static bool
1153         pre_compute_mst_dsc_configs_for_state(struct drm_atomic_state *state,
1154                                               struct dc_state *dc_state,
1155                                               struct dsc_mst_fairness_vars *vars)
1156 {
1157         int i, j;
1158         struct dc_stream_state *stream;
1159         bool computed_streams[MAX_PIPES];
1160         struct amdgpu_dm_connector *aconnector;
1161         int link_vars_start_index = 0;
1162
1163         for (i = 0; i < dc_state->stream_count; i++)
1164                 computed_streams[i] = false;
1165
1166         for (i = 0; i < dc_state->stream_count; i++) {
1167                 stream = dc_state->streams[i];
1168
1169                 if (stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST)
1170                         continue;
1171
1172                 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
1173
1174                 if (!aconnector || !aconnector->dc_sink)
1175                         continue;
1176
1177                 if (!aconnector->dc_sink->dsc_caps.dsc_dec_caps.is_dsc_supported)
1178                         continue;
1179
1180                 if (computed_streams[i])
1181                         continue;
1182
1183                 if (!is_dsc_need_re_compute(state, dc_state, stream->link))
1184                         continue;
1185
1186                 mutex_lock(&aconnector->mst_mgr.lock);
1187                 if (!compute_mst_dsc_configs_for_link(state, dc_state, stream->link, vars,
1188                                                       &aconnector->mst_mgr,
1189                                                       &link_vars_start_index)) {
1190                         mutex_unlock(&aconnector->mst_mgr.lock);
1191                         return false;
1192                 }
1193                 mutex_unlock(&aconnector->mst_mgr.lock);
1194
1195                 for (j = 0; j < dc_state->stream_count; j++) {
1196                         if (dc_state->streams[j]->link == stream->link)
1197                                 computed_streams[j] = true;
1198                 }
1199         }
1200
1201         return true;
1202 }
1203
1204 static int find_crtc_index_in_state_by_stream(struct drm_atomic_state *state,
1205                                               struct dc_stream_state *stream)
1206 {
1207         int i;
1208         struct drm_crtc *crtc;
1209         struct drm_crtc_state *new_state, *old_state;
1210
1211         for_each_oldnew_crtc_in_state(state, crtc, old_state, new_state, i) {
1212                 struct dm_crtc_state *dm_state = to_dm_crtc_state(new_state);
1213
1214                 if (dm_state->stream == stream)
1215                         return i;
1216         }
1217         return -1;
1218 }
1219
1220 static bool is_link_to_dschub(struct dc_link *dc_link)
1221 {
1222         union dpcd_dsc_basic_capabilities *dsc_caps =
1223                         &dc_link->dpcd_caps.dsc_caps.dsc_basic_caps;
1224
1225         /* only check phy used by dsc mst branch */
1226         if (dc_link->type != dc_connection_mst_branch)
1227                 return false;
1228
1229         if (!(dsc_caps->fields.dsc_support.DSC_SUPPORT ||
1230               dsc_caps->fields.dsc_support.DSC_PASSTHROUGH_SUPPORT))
1231                 return false;
1232         return true;
1233 }
1234
1235 static bool is_dsc_precompute_needed(struct drm_atomic_state *state)
1236 {
1237         int i;
1238         struct drm_crtc *crtc;
1239         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
1240         bool ret = false;
1241
1242         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
1243                 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(new_crtc_state);
1244
1245                 if (!amdgpu_dm_find_first_crtc_matching_connector(state, crtc)) {
1246                         ret =  false;
1247                         break;
1248                 }
1249                 if (dm_crtc_state->stream && dm_crtc_state->stream->link)
1250                         if (is_link_to_dschub(dm_crtc_state->stream->link))
1251                                 ret = true;
1252         }
1253         return ret;
1254 }
1255
1256 bool pre_validate_dsc(struct drm_atomic_state *state,
1257                       struct dm_atomic_state **dm_state_ptr,
1258                       struct dsc_mst_fairness_vars *vars)
1259 {
1260         int i;
1261         struct dm_atomic_state *dm_state;
1262         struct dc_state *local_dc_state = NULL;
1263         int ret = 0;
1264
1265         if (!is_dsc_precompute_needed(state)) {
1266                 DRM_INFO_ONCE("DSC precompute is not needed.\n");
1267                 return true;
1268         }
1269         if (dm_atomic_get_state(state, dm_state_ptr)) {
1270                 DRM_INFO_ONCE("dm_atomic_get_state() failed\n");
1271                 return false;
1272         }
1273         dm_state = *dm_state_ptr;
1274
1275         /*
1276          * create local vailable for dc_state. copy content of streams of dm_state->context
1277          * to local variable. make sure stream pointer of local variable not the same as stream
1278          * from dm_state->context.
1279          */
1280
1281         local_dc_state = kmemdup(dm_state->context, sizeof(struct dc_state), GFP_KERNEL);
1282         if (!local_dc_state)
1283                 return false;
1284
1285         for (i = 0; i < local_dc_state->stream_count; i++) {
1286                 struct dc_stream_state *stream = dm_state->context->streams[i];
1287                 int ind = find_crtc_index_in_state_by_stream(state, stream);
1288
1289                 if (ind >= 0) {
1290                         struct amdgpu_dm_connector *aconnector;
1291                         struct drm_connector_state *drm_new_conn_state;
1292                         struct dm_connector_state *dm_new_conn_state;
1293                         struct dm_crtc_state *dm_old_crtc_state;
1294
1295                         aconnector =
1296                                 amdgpu_dm_find_first_crtc_matching_connector(state,
1297                                                                              state->crtcs[ind].ptr);
1298                         drm_new_conn_state =
1299                                 drm_atomic_get_new_connector_state(state,
1300                                                                    &aconnector->base);
1301                         dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
1302                         dm_old_crtc_state = to_dm_crtc_state(state->crtcs[ind].old_state);
1303
1304                         local_dc_state->streams[i] =
1305                                 create_validate_stream_for_sink(aconnector,
1306                                                                 &state->crtcs[ind].new_state->mode,
1307                                                                 dm_new_conn_state,
1308                                                                 dm_old_crtc_state->stream);
1309                         if (local_dc_state->streams[i] == NULL) {
1310                                 ret = -EINVAL;
1311                                 break;
1312                         }
1313                 }
1314         }
1315
1316         if (ret != 0)
1317                 goto clean_exit;
1318
1319         if (!pre_compute_mst_dsc_configs_for_state(state, local_dc_state, vars)) {
1320                 DRM_INFO_ONCE("pre_compute_mst_dsc_configs_for_state() failed\n");
1321                 ret = -EINVAL;
1322                 goto clean_exit;
1323         }
1324
1325         /*
1326          * compare local_streams -> timing  with dm_state->context,
1327          * if the same set crtc_state->mode-change = 0;
1328          */
1329         for (i = 0; i < local_dc_state->stream_count; i++) {
1330                 struct dc_stream_state *stream = dm_state->context->streams[i];
1331
1332                 if (local_dc_state->streams[i] &&
1333                     is_timing_changed(stream, local_dc_state->streams[i])) {
1334                         DRM_INFO_ONCE("crtc[%d] needs mode_changed\n", i);
1335                 } else {
1336                         int ind = find_crtc_index_in_state_by_stream(state, stream);
1337
1338                         if (ind >= 0)
1339                                 state->crtcs[ind].new_state->mode_changed = 0;
1340                 }
1341         }
1342 clean_exit:
1343         for (i = 0; i < local_dc_state->stream_count; i++) {
1344                 struct dc_stream_state *stream = dm_state->context->streams[i];
1345
1346                 if (local_dc_state->streams[i] != stream)
1347                         dc_stream_release(local_dc_state->streams[i]);
1348         }
1349
1350         kfree(local_dc_state);
1351
1352         return (ret == 0);
1353 }
1354
1355 static unsigned int kbps_from_pbn(unsigned int pbn)
1356 {
1357         unsigned int kbps = pbn;
1358
1359         kbps *= (1000000 / PEAK_FACTOR_X1000);
1360         kbps *= 8;
1361         kbps *= 54;
1362         kbps /= 64;
1363
1364         return kbps;
1365 }
1366
1367 static bool is_dsc_common_config_possible(struct dc_stream_state *stream,
1368                                           struct dc_dsc_bw_range *bw_range)
1369 {
1370         struct dc_dsc_policy dsc_policy = {0};
1371
1372         dc_dsc_get_policy_for_timing(&stream->timing, 0, &dsc_policy);
1373         dc_dsc_compute_bandwidth_range(stream->sink->ctx->dc->res_pool->dscs[0],
1374                                        stream->sink->ctx->dc->debug.dsc_min_slice_height_override,
1375                                        dsc_policy.min_target_bpp * 16,
1376                                        dsc_policy.max_target_bpp * 16,
1377                                        &stream->sink->dsc_caps.dsc_dec_caps,
1378                                        &stream->timing, bw_range);
1379
1380         return bw_range->max_target_bpp_x16 && bw_range->min_target_bpp_x16;
1381 }
1382 #endif /* CONFIG_DRM_AMD_DC_DCN */
1383
1384 enum dc_status dm_dp_mst_is_port_support_mode(
1385         struct amdgpu_dm_connector *aconnector,
1386         struct dc_stream_state *stream)
1387 {
1388         int bpp, pbn, branch_max_throughput_mps = 0;
1389 #if defined(CONFIG_DRM_AMD_DC_DCN)
1390         struct dc_link_settings cur_link_settings;
1391         unsigned int end_to_end_bw_in_kbps = 0;
1392         unsigned int upper_link_bw_in_kbps = 0, down_link_bw_in_kbps = 0;
1393         unsigned int max_compressed_bw_in_kbps = 0;
1394         struct dc_dsc_bw_range bw_range = {0};
1395
1396         /*
1397          * check if the mode could be supported if DSC pass-through is supported
1398          * AND check if there enough bandwidth available to support the mode
1399          * with DSC enabled.
1400          */
1401         if (is_dsc_common_config_possible(stream, &bw_range) &&
1402             aconnector->port->passthrough_aux) {
1403                 mutex_lock(&aconnector->mst_mgr.lock);
1404
1405                 cur_link_settings = stream->link->verified_link_cap;
1406
1407                 upper_link_bw_in_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
1408                                                                &cur_link_settings
1409                                                                );
1410                 down_link_bw_in_kbps = kbps_from_pbn(aconnector->port->full_pbn);
1411
1412                 /* pick the bottleneck */
1413                 end_to_end_bw_in_kbps = min(upper_link_bw_in_kbps,
1414                                             down_link_bw_in_kbps);
1415
1416                 mutex_unlock(&aconnector->mst_mgr.lock);
1417
1418                 /*
1419                  * use the maximum dsc compression bandwidth as the required
1420                  * bandwidth for the mode
1421                  */
1422                 max_compressed_bw_in_kbps = bw_range.min_kbps;
1423
1424                 if (end_to_end_bw_in_kbps < max_compressed_bw_in_kbps) {
1425                         DRM_DEBUG_DRIVER("Mode does not fit into DSC pass-through bandwidth validation\n");
1426                         return DC_FAIL_BANDWIDTH_VALIDATE;
1427                 }
1428         } else {
1429 #endif
1430                 /* check if mode could be supported within full_pbn */
1431                 bpp = convert_dc_color_depth_into_bpc(stream->timing.display_color_depth) * 3;
1432                 pbn = drm_dp_calc_pbn_mode(stream->timing.pix_clk_100hz / 10, bpp, false);
1433
1434                 if (pbn > aconnector->port->full_pbn)
1435                         return DC_FAIL_BANDWIDTH_VALIDATE;
1436 #if defined(CONFIG_DRM_AMD_DC_DCN)
1437         }
1438 #endif
1439
1440         /* check is mst dsc output bandwidth branch_overall_throughput_0_mps */
1441         switch (stream->timing.pixel_encoding) {
1442         case PIXEL_ENCODING_RGB:
1443         case PIXEL_ENCODING_YCBCR444:
1444                 branch_max_throughput_mps =
1445                         aconnector->dc_sink->dsc_caps.dsc_dec_caps.branch_overall_throughput_0_mps;
1446                 break;
1447         case PIXEL_ENCODING_YCBCR422:
1448         case PIXEL_ENCODING_YCBCR420:
1449                 branch_max_throughput_mps =
1450                         aconnector->dc_sink->dsc_caps.dsc_dec_caps.branch_overall_throughput_1_mps;
1451                 break;
1452         default:
1453                 break;
1454         }
1455
1456         if (branch_max_throughput_mps != 0 &&
1457                 ((stream->timing.pix_clk_100hz / 10) >  branch_max_throughput_mps * 1000))
1458                 return DC_FAIL_BANDWIDTH_VALIDATE;
1459
1460         return DC_OK;
1461 }