2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include <linux/string.h>
27 #include <linux/acpi.h>
28 #include <linux/i2c.h>
30 #include <drm/drm_atomic.h>
31 #include <drm/drm_probe_helper.h>
32 #include <drm/amdgpu_drm.h>
33 #include <drm/drm_edid.h>
35 #include "dm_services.h"
38 #include "amdgpu_dm.h"
39 #include "amdgpu_dm_irq.h"
40 #include "amdgpu_dm_mst_types.h"
42 #include "dm_helpers.h"
43 #include "ddc_service_types.h"
45 struct monitor_patch_info {
46 unsigned int manufacturer_id;
47 unsigned int product_id;
48 void (*patch_func)(struct dc_edid_caps *edid_caps, unsigned int param);
49 unsigned int patch_param;
51 static void set_max_dsc_bpp_limit(struct dc_edid_caps *edid_caps, unsigned int param);
53 static const struct monitor_patch_info monitor_patch_table[] = {
54 {0x6D1E, 0x5BBF, set_max_dsc_bpp_limit, 15},
55 {0x6D1E, 0x5B9A, set_max_dsc_bpp_limit, 15},
58 static void set_max_dsc_bpp_limit(struct dc_edid_caps *edid_caps, unsigned int param)
61 edid_caps->panel_patch.max_dsc_target_bpp_limit = param;
64 static int amdgpu_dm_patch_edid_caps(struct dc_edid_caps *edid_caps)
68 for (i = 0; i < ARRAY_SIZE(monitor_patch_table); i++)
69 if ((edid_caps->manufacturer_id == monitor_patch_table[i].manufacturer_id)
70 && (edid_caps->product_id == monitor_patch_table[i].product_id)) {
71 monitor_patch_table[i].patch_func(edid_caps, monitor_patch_table[i].patch_param);
78 /* dm_helpers_parse_edid_caps
82 * @edid: [in] pointer to edid
83 * edid_caps: [in] pointer to edid caps
87 enum dc_edid_status dm_helpers_parse_edid_caps(
89 const struct dc_edid *edid,
90 struct dc_edid_caps *edid_caps)
92 struct amdgpu_dm_connector *aconnector = link->priv;
93 struct drm_connector *connector = &aconnector->base;
94 struct edid *edid_buf = edid ? (struct edid *) edid->raw_edid : NULL;
101 enum dc_edid_status result = EDID_OK;
103 if (!edid_caps || !edid)
104 return EDID_BAD_INPUT;
106 if (!drm_edid_is_valid(edid_buf))
107 result = EDID_BAD_CHECKSUM;
109 edid_caps->manufacturer_id = (uint16_t) edid_buf->mfg_id[0] |
110 ((uint16_t) edid_buf->mfg_id[1])<<8;
111 edid_caps->product_id = (uint16_t) edid_buf->prod_code[0] |
112 ((uint16_t) edid_buf->prod_code[1])<<8;
113 edid_caps->serial_number = edid_buf->serial;
114 edid_caps->manufacture_week = edid_buf->mfg_week;
115 edid_caps->manufacture_year = edid_buf->mfg_year;
117 drm_edid_get_monitor_name(edid_buf,
118 edid_caps->display_name,
119 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
121 edid_caps->edid_hdmi = connector->display_info.is_hdmi;
123 sad_count = drm_edid_to_sad((struct edid *) edid->raw_edid, &sads);
127 edid_caps->audio_mode_count = sad_count < DC_MAX_AUDIO_DESC_COUNT ? sad_count : DC_MAX_AUDIO_DESC_COUNT;
128 for (i = 0; i < edid_caps->audio_mode_count; ++i) {
129 struct cea_sad *sad = &sads[i];
131 edid_caps->audio_modes[i].format_code = sad->format;
132 edid_caps->audio_modes[i].channel_count = sad->channels + 1;
133 edid_caps->audio_modes[i].sample_rate = sad->freq;
134 edid_caps->audio_modes[i].sample_size = sad->byte2;
137 sadb_count = drm_edid_to_speaker_allocation((struct edid *) edid->raw_edid, &sadb);
139 if (sadb_count < 0) {
140 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sadb_count);
145 edid_caps->speaker_flags = sadb[0];
147 edid_caps->speaker_flags = DEFAULT_SPEAKER_LOCATION;
152 amdgpu_dm_patch_edid_caps(edid_caps);
158 fill_dc_mst_payload_table_from_drm(struct drm_dp_mst_topology_state *mst_state,
159 struct amdgpu_dm_connector *aconnector,
160 struct dc_dp_mst_stream_allocation_table *table)
162 struct dc_dp_mst_stream_allocation_table new_table = { 0 };
163 struct dc_dp_mst_stream_allocation *sa;
164 struct drm_dp_mst_atomic_payload *payload;
166 /* Fill payload info*/
167 list_for_each_entry(payload, &mst_state->payloads, next) {
171 sa = &new_table.stream_allocations[new_table.stream_count];
172 sa->slot_count = payload->time_slots;
173 sa->vcp_id = payload->vcpi;
174 new_table.stream_count++;
177 /* Overwrite the old table */
181 void dm_helpers_dp_update_branch_info(
182 struct dc_context *ctx,
183 const struct dc_link *link)
187 * Writes payload allocation table in immediate downstream device.
189 bool dm_helpers_dp_mst_write_payload_allocation_table(
190 struct dc_context *ctx,
191 const struct dc_stream_state *stream,
192 struct dc_dp_mst_stream_allocation_table *proposed_table,
195 struct amdgpu_dm_connector *aconnector;
196 struct drm_dp_mst_topology_state *mst_state;
197 struct drm_dp_mst_atomic_payload *payload;
198 struct drm_dp_mst_topology_mgr *mst_mgr;
200 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
201 /* Accessing the connector state is required for vcpi_slots allocation
202 * and directly relies on behaviour in commit check
203 * that blocks before commit guaranteeing that the state
204 * is not gonna be swapped while still in use in commit tail */
206 if (!aconnector || !aconnector->mst_port)
209 mst_mgr = &aconnector->mst_port->mst_mgr;
210 mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state);
212 /* It's OK for this to fail */
213 payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->port);
215 drm_dp_add_payload_part1(mst_mgr, mst_state, payload);
217 drm_dp_remove_payload(mst_mgr, mst_state, payload);
219 /* mst_mgr->->payloads are VC payload notify MST branch using DPCD or
220 * AUX message. The sequence is slot 1-63 allocated sequence for each
221 * stream. AMD ASIC stream slot allocation should follow the same
222 * sequence. copy DRM MST allocation to dc */
223 fill_dc_mst_payload_table_from_drm(mst_state, aconnector, proposed_table);
229 * poll pending down reply
231 void dm_helpers_dp_mst_poll_pending_down_reply(
232 struct dc_context *ctx,
233 const struct dc_link *link)
237 * Clear payload allocation table before enable MST DP link.
239 void dm_helpers_dp_mst_clear_payload_allocation_table(
240 struct dc_context *ctx,
241 const struct dc_link *link)
245 * Polls for ACT (allocation change trigger) handled and sends
246 * ALLOCATE_PAYLOAD message.
248 enum act_return_status dm_helpers_dp_mst_poll_for_allocation_change_trigger(
249 struct dc_context *ctx,
250 const struct dc_stream_state *stream)
252 struct amdgpu_dm_connector *aconnector;
253 struct drm_dp_mst_topology_mgr *mst_mgr;
256 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
258 if (!aconnector || !aconnector->mst_port)
261 mst_mgr = &aconnector->mst_port->mst_mgr;
263 if (!mst_mgr->mst_state)
266 ret = drm_dp_check_act_status(mst_mgr);
274 bool dm_helpers_dp_mst_send_payload_allocation(
275 struct dc_context *ctx,
276 const struct dc_stream_state *stream,
279 struct amdgpu_dm_connector *aconnector;
280 struct drm_dp_mst_topology_state *mst_state;
281 struct drm_dp_mst_topology_mgr *mst_mgr;
282 struct drm_dp_mst_atomic_payload *payload;
283 enum mst_progress_status set_flag = MST_ALLOCATE_NEW_PAYLOAD;
284 enum mst_progress_status clr_flag = MST_CLEAR_ALLOCATED_PAYLOAD;
286 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
288 if (!aconnector || !aconnector->mst_port)
291 mst_mgr = &aconnector->mst_port->mst_mgr;
292 mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state);
294 payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->port);
296 set_flag = MST_CLEAR_ALLOCATED_PAYLOAD;
297 clr_flag = MST_ALLOCATE_NEW_PAYLOAD;
300 if (enable && drm_dp_add_payload_part2(mst_mgr, mst_state->base.state, payload)) {
301 amdgpu_dm_set_mst_status(&aconnector->mst_status,
304 amdgpu_dm_set_mst_status(&aconnector->mst_status,
306 amdgpu_dm_set_mst_status(&aconnector->mst_status,
313 void dm_dtn_log_begin(struct dc_context *ctx,
314 struct dc_log_buffer_ctx *log_ctx)
316 static const char msg[] = "[dtn begin]\n";
323 dm_dtn_log_append_v(ctx, log_ctx, "%s", msg);
327 void dm_dtn_log_append_v(struct dc_context *ctx,
328 struct dc_log_buffer_ctx *log_ctx,
329 const char *msg, ...)
336 /* No context, redirect to dmesg. */
337 struct va_format vaf;
343 pr_info("%pV", &vaf);
349 /* Measure the output. */
351 n = vsnprintf(NULL, 0, msg, args);
357 /* Reallocate the string buffer as needed. */
358 total = log_ctx->pos + n + 1;
360 if (total > log_ctx->size) {
361 char *buf = (char *)kvcalloc(total, sizeof(char), GFP_KERNEL);
364 memcpy(buf, log_ctx->buf, log_ctx->pos);
368 log_ctx->size = total;
375 /* Write the formatted string to the log buffer. */
378 log_ctx->buf + log_ctx->pos,
379 log_ctx->size - log_ctx->pos,
388 void dm_dtn_log_end(struct dc_context *ctx,
389 struct dc_log_buffer_ctx *log_ctx)
391 static const char msg[] = "[dtn end]\n";
398 dm_dtn_log_append_v(ctx, log_ctx, "%s", msg);
401 bool dm_helpers_dp_mst_start_top_mgr(
402 struct dc_context *ctx,
403 const struct dc_link *link,
406 struct amdgpu_dm_connector *aconnector = link->priv;
409 DRM_ERROR("Failed to find connector for link!");
414 DRM_INFO("DM_MST: Differing MST start on aconnector: %p [id: %d]\n",
415 aconnector, aconnector->base.base.id);
419 DRM_INFO("DM_MST: starting TM on aconnector: %p [id: %d]\n",
420 aconnector, aconnector->base.base.id);
422 return (drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true) == 0);
425 bool dm_helpers_dp_mst_stop_top_mgr(
426 struct dc_context *ctx,
427 struct dc_link *link)
429 struct amdgpu_dm_connector *aconnector = link->priv;
432 DRM_ERROR("Failed to find connector for link!");
436 DRM_INFO("DM_MST: stopping TM on aconnector: %p [id: %d]\n",
437 aconnector, aconnector->base.base.id);
439 if (aconnector->mst_mgr.mst_state == true) {
440 drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, false);
441 link->cur_link_settings.lane_count = 0;
447 bool dm_helpers_dp_read_dpcd(
448 struct dc_context *ctx,
449 const struct dc_link *link,
455 struct amdgpu_dm_connector *aconnector = link->priv;
458 DC_LOG_DC("Failed to find connector for link!\n");
462 return drm_dp_dpcd_read(&aconnector->dm_dp_aux.aux, address,
466 bool dm_helpers_dp_write_dpcd(
467 struct dc_context *ctx,
468 const struct dc_link *link,
473 struct amdgpu_dm_connector *aconnector = link->priv;
476 DRM_ERROR("Failed to find connector for link!");
480 return drm_dp_dpcd_write(&aconnector->dm_dp_aux.aux,
481 address, (uint8_t *)data, size) > 0;
484 bool dm_helpers_submit_i2c(
485 struct dc_context *ctx,
486 const struct dc_link *link,
487 struct i2c_command *cmd)
489 struct amdgpu_dm_connector *aconnector = link->priv;
490 struct i2c_msg *msgs;
492 int num = cmd->number_of_payloads;
496 DRM_ERROR("Failed to find connector for link!");
500 msgs = kcalloc(num, sizeof(struct i2c_msg), GFP_KERNEL);
505 for (i = 0; i < num; i++) {
506 msgs[i].flags = cmd->payloads[i].write ? 0 : I2C_M_RD;
507 msgs[i].addr = cmd->payloads[i].address;
508 msgs[i].len = cmd->payloads[i].length;
509 msgs[i].buf = cmd->payloads[i].data;
512 result = i2c_transfer(&aconnector->i2c->base, msgs, num) == num;
519 #if defined(CONFIG_DRM_AMD_DC_DCN)
520 static bool execute_synaptics_rc_command(struct drm_dp_aux *aux,
527 bool success = false;
528 unsigned char rc_data[16] = {0};
529 unsigned char rc_offset[4] = {0};
530 unsigned char rc_length[2] = {0};
531 unsigned char rc_cmd = 0;
532 unsigned char rc_result = 0xFF;
538 memmove(rc_data, data, length);
539 ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_DATA, rc_data, sizeof(rc_data));
543 rc_offset[0] = (unsigned char) offset & 0xFF;
544 rc_offset[1] = (unsigned char) (offset >> 8) & 0xFF;
545 rc_offset[2] = (unsigned char) (offset >> 16) & 0xFF;
546 rc_offset[3] = (unsigned char) (offset >> 24) & 0xFF;
547 ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_OFFSET, rc_offset, sizeof(rc_offset));
550 rc_length[0] = (unsigned char) length & 0xFF;
551 rc_length[1] = (unsigned char) (length >> 8) & 0xFF;
552 ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_LENGTH, rc_length, sizeof(rc_length));
556 ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_COMMAND, &rc_cmd, sizeof(rc_cmd));
559 DRM_ERROR(" execute_synaptics_rc_command - write cmd ..., err = %d\n", ret);
563 // poll until active is 0
564 for (i = 0; i < 10; i++) {
565 drm_dp_dpcd_read(aux, SYNAPTICS_RC_COMMAND, &rc_cmd, sizeof(rc_cmd));
573 drm_dp_dpcd_read(aux, SYNAPTICS_RC_RESULT, &rc_result, sizeof(rc_result));
574 success = (rc_result == 0);
576 if (success && !is_write_cmd) {
578 drm_dp_dpcd_read(aux, SYNAPTICS_RC_DATA, data, length);
581 DC_LOG_DC(" execute_synaptics_rc_command - success = %d\n", success);
586 static void apply_synaptics_fifo_reset_wa(struct drm_dp_aux *aux)
588 unsigned char data[16] = {0};
590 DC_LOG_DC("Start apply_synaptics_fifo_reset_wa\n");
599 if (!execute_synaptics_rc_command(aux, true, 0x01, 5, 0, data))
603 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220998, data))
606 data[0] &= (~(1 << 1)); // set bit 1 to 0
607 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x220998, data))
610 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220D98, data))
613 data[0] &= (~(1 << 1)); // set bit 1 to 0
614 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x220D98, data))
617 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x221198, data))
620 data[0] &= (~(1 << 1)); // set bit 1 to 0
621 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x221198, data))
625 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220998, data))
628 data[0] |= (1 << 1); // set bit 1 to 1
629 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x220998, data))
632 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220D98, data))
635 data[0] |= (1 << 1); // set bit 1 to 1
638 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x221198, data))
641 data[0] |= (1 << 1); // set bit 1 to 1
642 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x221198, data))
646 if (!execute_synaptics_rc_command(aux, true, 0x02, 0, 0, NULL))
649 DC_LOG_DC("Done apply_synaptics_fifo_reset_wa\n");
652 static uint8_t write_dsc_enable_synaptics_non_virtual_dpcd_mst(
653 struct drm_dp_aux *aux,
654 const struct dc_stream_state *stream,
659 DC_LOG_DC("Configure DSC to non-virtual dpcd synaptics\n");
662 /* When DSC is enabled on previous boot and reboot with the hub,
663 * there is a chance that Synaptics hub gets stuck during reboot sequence.
664 * Applying a workaround to reset Synaptics SDP fifo before enabling the first stream
666 if (!stream->link->link_status.link_active &&
667 memcmp(stream->link->dpcd_caps.branch_dev_name,
668 (int8_t *)SYNAPTICS_DEVICE_ID, 4) == 0)
669 apply_synaptics_fifo_reset_wa(aux);
671 ret = drm_dp_dpcd_write(aux, DP_DSC_ENABLE, &enable, 1);
672 DRM_INFO("Send DSC enable to synaptics\n");
675 /* Synaptics hub not support virtual dpcd,
676 * external monitor occur garbage while disable DSC,
677 * Disable DSC only when entire link status turn to false,
679 if (!stream->link->link_status.link_active) {
680 ret = drm_dp_dpcd_write(aux, DP_DSC_ENABLE, &enable, 1);
681 DRM_INFO("Send DSC disable to synaptics\n");
689 bool dm_helpers_dp_write_dsc_enable(
690 struct dc_context *ctx,
691 const struct dc_stream_state *stream,
694 uint8_t enable_dsc = enable ? 1 : 0;
695 struct amdgpu_dm_connector *aconnector;
701 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
702 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
704 if (!aconnector->dsc_aux)
707 #if defined(CONFIG_DRM_AMD_DC_DCN)
708 // apply w/a to synaptics
709 if (needs_dsc_aux_workaround(aconnector->dc_link) &&
710 (aconnector->mst_downstream_port_present.byte & 0x7) != 0x3)
711 return write_dsc_enable_synaptics_non_virtual_dpcd_mst(
712 aconnector->dsc_aux, stream, enable_dsc);
715 ret = drm_dp_dpcd_write(aconnector->dsc_aux, DP_DSC_ENABLE, &enable_dsc, 1);
716 DC_LOG_DC("Send DSC %s to MST RX\n", enable_dsc ? "enable" : "disable");
719 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT || stream->signal == SIGNAL_TYPE_EDP) {
720 #if defined(CONFIG_DRM_AMD_DC_DCN)
721 if (stream->sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) {
723 ret = dm_helpers_dp_write_dpcd(ctx, stream->link, DP_DSC_ENABLE, &enable_dsc, 1);
724 DC_LOG_DC("Send DSC %s to SST RX\n", enable_dsc ? "enable" : "disable");
725 #if defined(CONFIG_DRM_AMD_DC_DCN)
726 } else if (stream->sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) {
727 ret = dm_helpers_dp_write_dpcd(ctx, stream->link, DP_DSC_ENABLE, &enable_dsc, 1);
728 DC_LOG_DC("Send DSC %s to DP-HDMI PCON\n", enable_dsc ? "enable" : "disable");
736 bool dm_helpers_is_dp_sink_present(struct dc_link *link)
738 bool dp_sink_present;
739 struct amdgpu_dm_connector *aconnector = link->priv;
742 BUG_ON("Failed to find connector for link!");
746 mutex_lock(&aconnector->dm_dp_aux.aux.hw_mutex);
747 dp_sink_present = dc_link_is_dp_sink_present(link);
748 mutex_unlock(&aconnector->dm_dp_aux.aux.hw_mutex);
749 return dp_sink_present;
752 enum dc_edid_status dm_helpers_read_local_edid(
753 struct dc_context *ctx,
754 struct dc_link *link,
755 struct dc_sink *sink)
757 struct amdgpu_dm_connector *aconnector = link->priv;
758 struct drm_connector *connector = &aconnector->base;
759 struct i2c_adapter *ddc;
761 enum dc_edid_status edid_status;
765 ddc = &aconnector->dm_dp_aux.aux.ddc;
767 ddc = &aconnector->i2c->base;
769 /* some dongles read edid incorrectly the first time,
770 * do check sum and retry to make sure read correct edid.
774 edid = drm_get_edid(&aconnector->base, ddc);
776 /* DP Compliance Test 4.2.2.6 */
777 if (link->aux_mode && connector->edid_corrupt)
778 drm_dp_send_real_edid_checksum(&aconnector->dm_dp_aux.aux, connector->real_edid_checksum);
780 if (!edid && connector->edid_corrupt) {
781 connector->edid_corrupt = false;
782 return EDID_BAD_CHECKSUM;
786 return EDID_NO_RESPONSE;
788 sink->dc_edid.length = EDID_LENGTH * (edid->extensions + 1);
789 memmove(sink->dc_edid.raw_edid, (uint8_t *)edid, sink->dc_edid.length);
791 /* We don't need the original edid anymore */
794 edid_status = dm_helpers_parse_edid_caps(
799 } while (edid_status == EDID_BAD_CHECKSUM && --retry > 0);
801 if (edid_status != EDID_OK)
802 DRM_ERROR("EDID err: %d, on connector: %s",
804 aconnector->base.name);
806 /* DP Compliance Test 4.2.2.3 */
808 drm_dp_send_real_edid_checksum(&aconnector->dm_dp_aux.aux, sink->dc_edid.raw_edid[sink->dc_edid.length-1]);
812 int dm_helper_dmub_aux_transfer_sync(
813 struct dc_context *ctx,
814 const struct dc_link *link,
815 struct aux_payload *payload,
816 enum aux_return_code_type *operation_result)
818 return amdgpu_dm_process_dmub_aux_transfer_sync(true, ctx,
819 link->link_index, (void *)payload,
820 (void *)operation_result);
823 int dm_helpers_dmub_set_config_sync(struct dc_context *ctx,
824 const struct dc_link *link,
825 struct set_config_cmd_payload *payload,
826 enum set_config_status *operation_result)
828 return amdgpu_dm_process_dmub_aux_transfer_sync(false, ctx,
829 link->link_index, (void *)payload,
830 (void *)operation_result);
833 void dm_set_dcn_clocks(struct dc_context *ctx, struct dc_clocks *clks)
835 /* TODO: something */
838 void dm_helpers_smu_timeout(struct dc_context *ctx, unsigned int msg_id, unsigned int param, unsigned int timeout_us)
841 //amdgpu_device_gpu_recover(dc_context->driver-context, NULL);
844 void *dm_helpers_allocate_gpu_mem(
845 struct dc_context *ctx,
846 enum dc_gpu_mem_alloc_type type,
850 struct amdgpu_device *adev = ctx->driver_context;
851 struct dal_allocation *da;
852 u32 domain = (type == DC_MEM_ALLOC_TYPE_GART) ?
853 AMDGPU_GEM_DOMAIN_GTT : AMDGPU_GEM_DOMAIN_VRAM;
856 da = kzalloc(sizeof(struct dal_allocation), GFP_KERNEL);
860 ret = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE,
862 &da->gpu_addr, &da->cpu_ptr);
864 *addr = da->gpu_addr;
871 /* add da to list in dm */
872 list_add(&da->list, &adev->dm.da_list);
877 void dm_helpers_free_gpu_mem(
878 struct dc_context *ctx,
879 enum dc_gpu_mem_alloc_type type,
882 struct amdgpu_device *adev = ctx->driver_context;
883 struct dal_allocation *da;
885 /* walk the da list in DM */
886 list_for_each_entry(da, &adev->dm.da_list, list) {
887 if (pvMem == da->cpu_ptr) {
888 amdgpu_bo_free_kernel(&da->bo, &da->gpu_addr, &da->cpu_ptr);
896 bool dm_helpers_dmub_outbox_interrupt_control(struct dc_context *ctx, bool enable)
898 enum dc_irq_source irq_source;
901 irq_source = DC_IRQ_SOURCE_DMCUB_OUTBOX;
903 ret = dc_interrupt_set(ctx->dc, irq_source, enable);
905 DRM_DEBUG_DRIVER("Dmub trace irq %sabling: r=%d\n",
906 enable ? "en" : "dis", ret);
910 void dm_helpers_mst_enable_stream_features(const struct dc_stream_state *stream)
912 /* TODO: virtual DPCD */
913 struct dc_link *link = stream->link;
914 union down_spread_ctrl old_downspread;
915 union down_spread_ctrl new_downspread;
917 if (link->aux_access_disabled)
920 if (!dm_helpers_dp_read_dpcd(link->ctx, link, DP_DOWNSPREAD_CTRL,
922 sizeof(old_downspread)))
925 new_downspread.raw = old_downspread.raw;
926 new_downspread.bits.IGNORE_MSA_TIMING_PARAM =
927 (stream->ignore_msa_timing_param) ? 1 : 0;
929 if (new_downspread.raw != old_downspread.raw)
930 dm_helpers_dp_write_dpcd(link->ctx, link, DP_DOWNSPREAD_CTRL,
932 sizeof(new_downspread));
935 void dm_set_phyd32clk(struct dc_context *ctx, int freq_khz)
940 void dm_helpers_enable_periodic_detection(struct dc_context *ctx, bool enable)
942 /* TODO: add periodic detection implementation */