2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include <linux/string.h>
27 #include <linux/acpi.h>
28 #include <linux/i2c.h>
30 #include <drm/drm_probe_helper.h>
31 #include <drm/amdgpu_drm.h>
32 #include <drm/drm_edid.h>
34 #include "dm_services.h"
37 #include "amdgpu_dm.h"
38 #include "amdgpu_dm_irq.h"
39 #include "amdgpu_dm_mst_types.h"
41 #include "dm_helpers.h"
42 #include "ddc_service_types.h"
44 struct monitor_patch_info {
45 unsigned int manufacturer_id;
46 unsigned int product_id;
47 void (*patch_func)(struct dc_edid_caps *edid_caps, unsigned int param);
48 unsigned int patch_param;
50 static void set_max_dsc_bpp_limit(struct dc_edid_caps *edid_caps, unsigned int param);
52 static const struct monitor_patch_info monitor_patch_table[] = {
53 {0x6D1E, 0x5BBF, set_max_dsc_bpp_limit, 15},
54 {0x6D1E, 0x5B9A, set_max_dsc_bpp_limit, 15},
57 static void set_max_dsc_bpp_limit(struct dc_edid_caps *edid_caps, unsigned int param)
60 edid_caps->panel_patch.max_dsc_target_bpp_limit = param;
63 static int amdgpu_dm_patch_edid_caps(struct dc_edid_caps *edid_caps)
67 for (i = 0; i < ARRAY_SIZE(monitor_patch_table); i++)
68 if ((edid_caps->manufacturer_id == monitor_patch_table[i].manufacturer_id)
69 && (edid_caps->product_id == monitor_patch_table[i].product_id)) {
70 monitor_patch_table[i].patch_func(edid_caps, monitor_patch_table[i].patch_param);
77 /* dm_helpers_parse_edid_caps
81 * @edid: [in] pointer to edid
82 * edid_caps: [in] pointer to edid caps
86 enum dc_edid_status dm_helpers_parse_edid_caps(
88 const struct dc_edid *edid,
89 struct dc_edid_caps *edid_caps)
91 struct amdgpu_dm_connector *aconnector = link->priv;
92 struct drm_connector *connector = &aconnector->base;
93 struct edid *edid_buf = edid ? (struct edid *) edid->raw_edid : NULL;
100 enum dc_edid_status result = EDID_OK;
102 if (!edid_caps || !edid)
103 return EDID_BAD_INPUT;
105 if (!drm_edid_is_valid(edid_buf))
106 result = EDID_BAD_CHECKSUM;
108 edid_caps->manufacturer_id = (uint16_t) edid_buf->mfg_id[0] |
109 ((uint16_t) edid_buf->mfg_id[1])<<8;
110 edid_caps->product_id = (uint16_t) edid_buf->prod_code[0] |
111 ((uint16_t) edid_buf->prod_code[1])<<8;
112 edid_caps->serial_number = edid_buf->serial;
113 edid_caps->manufacture_week = edid_buf->mfg_week;
114 edid_caps->manufacture_year = edid_buf->mfg_year;
116 drm_edid_get_monitor_name(edid_buf,
117 edid_caps->display_name,
118 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
120 edid_caps->edid_hdmi = connector->display_info.is_hdmi;
122 sad_count = drm_edid_to_sad((struct edid *) edid->raw_edid, &sads);
126 edid_caps->audio_mode_count = sad_count < DC_MAX_AUDIO_DESC_COUNT ? sad_count : DC_MAX_AUDIO_DESC_COUNT;
127 for (i = 0; i < edid_caps->audio_mode_count; ++i) {
128 struct cea_sad *sad = &sads[i];
130 edid_caps->audio_modes[i].format_code = sad->format;
131 edid_caps->audio_modes[i].channel_count = sad->channels + 1;
132 edid_caps->audio_modes[i].sample_rate = sad->freq;
133 edid_caps->audio_modes[i].sample_size = sad->byte2;
136 sadb_count = drm_edid_to_speaker_allocation((struct edid *) edid->raw_edid, &sadb);
138 if (sadb_count < 0) {
139 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sadb_count);
144 edid_caps->speaker_flags = sadb[0];
146 edid_caps->speaker_flags = DEFAULT_SPEAKER_LOCATION;
151 amdgpu_dm_patch_edid_caps(edid_caps);
156 static void get_payload_table(
157 struct amdgpu_dm_connector *aconnector,
158 struct dp_mst_stream_allocation_table *proposed_table)
161 struct drm_dp_mst_topology_mgr *mst_mgr =
162 &aconnector->mst_port->mst_mgr;
164 mutex_lock(&mst_mgr->payload_lock);
166 proposed_table->stream_count = 0;
168 /* number of active streams */
169 for (i = 0; i < mst_mgr->max_payloads; i++) {
170 if (mst_mgr->payloads[i].num_slots == 0)
171 break; /* end of vcp_id table */
173 ASSERT(mst_mgr->payloads[i].payload_state !=
174 DP_PAYLOAD_DELETE_LOCAL);
176 if (mst_mgr->payloads[i].payload_state == DP_PAYLOAD_LOCAL ||
177 mst_mgr->payloads[i].payload_state ==
180 struct dp_mst_stream_allocation *sa =
181 &proposed_table->stream_allocations[
182 proposed_table->stream_count];
184 sa->slot_count = mst_mgr->payloads[i].num_slots;
185 sa->vcp_id = mst_mgr->proposed_vcpis[i]->vcpi;
186 proposed_table->stream_count++;
190 mutex_unlock(&mst_mgr->payload_lock);
193 void dm_helpers_dp_update_branch_info(
194 struct dc_context *ctx,
195 const struct dc_link *link)
199 * Writes payload allocation table in immediate downstream device.
201 bool dm_helpers_dp_mst_write_payload_allocation_table(
202 struct dc_context *ctx,
203 const struct dc_stream_state *stream,
204 struct dp_mst_stream_allocation_table *proposed_table,
207 struct amdgpu_dm_connector *aconnector;
208 struct dm_connector_state *dm_conn_state;
209 struct drm_dp_mst_topology_mgr *mst_mgr;
210 struct drm_dp_mst_port *mst_port;
212 u8 link_coding_cap = DP_8b_10b_ENCODING;
214 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
215 /* Accessing the connector state is required for vcpi_slots allocation
216 * and directly relies on behaviour in commit check
217 * that blocks before commit guaranteeing that the state
218 * is not gonna be swapped while still in use in commit tail */
220 if (!aconnector || !aconnector->mst_port)
223 dm_conn_state = to_dm_connector_state(aconnector->base.state);
225 mst_mgr = &aconnector->mst_port->mst_mgr;
227 if (!mst_mgr->mst_state)
230 mst_port = aconnector->port;
232 #if defined(CONFIG_DRM_AMD_DC_DCN)
233 link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link);
238 ret = drm_dp_mst_allocate_vcpi(mst_mgr, mst_port,
240 dm_conn_state->vcpi_slots);
245 drm_dp_mst_reset_vcpi_slots(mst_mgr, mst_port);
248 /* It's OK for this to fail */
249 drm_dp_update_payload_part1(mst_mgr, (link_coding_cap == DP_CAP_ANSI_128B132B) ? 0:1);
251 /* mst_mgr->->payloads are VC payload notify MST branch using DPCD or
252 * AUX message. The sequence is slot 1-63 allocated sequence for each
253 * stream. AMD ASIC stream slot allocation should follow the same
254 * sequence. copy DRM MST allocation to dc */
256 get_payload_table(aconnector, proposed_table);
262 * poll pending down reply
264 void dm_helpers_dp_mst_poll_pending_down_reply(
265 struct dc_context *ctx,
266 const struct dc_link *link)
270 * Clear payload allocation table before enable MST DP link.
272 void dm_helpers_dp_mst_clear_payload_allocation_table(
273 struct dc_context *ctx,
274 const struct dc_link *link)
278 * Polls for ACT (allocation change trigger) handled and sends
279 * ALLOCATE_PAYLOAD message.
281 enum act_return_status dm_helpers_dp_mst_poll_for_allocation_change_trigger(
282 struct dc_context *ctx,
283 const struct dc_stream_state *stream)
285 struct amdgpu_dm_connector *aconnector;
286 struct drm_dp_mst_topology_mgr *mst_mgr;
289 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
291 if (!aconnector || !aconnector->mst_port)
294 mst_mgr = &aconnector->mst_port->mst_mgr;
296 if (!mst_mgr->mst_state)
299 ret = drm_dp_check_act_status(mst_mgr);
307 bool dm_helpers_dp_mst_send_payload_allocation(
308 struct dc_context *ctx,
309 const struct dc_stream_state *stream,
312 struct amdgpu_dm_connector *aconnector;
313 struct drm_dp_mst_topology_mgr *mst_mgr;
314 struct drm_dp_mst_port *mst_port;
316 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
318 if (!aconnector || !aconnector->mst_port)
321 mst_port = aconnector->port;
323 mst_mgr = &aconnector->mst_port->mst_mgr;
325 if (!mst_mgr->mst_state)
328 /* It's OK for this to fail */
329 drm_dp_update_payload_part2(mst_mgr);
332 drm_dp_mst_deallocate_vcpi(mst_mgr, mst_port);
337 void dm_dtn_log_begin(struct dc_context *ctx,
338 struct dc_log_buffer_ctx *log_ctx)
340 static const char msg[] = "[dtn begin]\n";
347 dm_dtn_log_append_v(ctx, log_ctx, "%s", msg);
351 void dm_dtn_log_append_v(struct dc_context *ctx,
352 struct dc_log_buffer_ctx *log_ctx,
353 const char *msg, ...)
360 /* No context, redirect to dmesg. */
361 struct va_format vaf;
367 pr_info("%pV", &vaf);
373 /* Measure the output. */
375 n = vsnprintf(NULL, 0, msg, args);
381 /* Reallocate the string buffer as needed. */
382 total = log_ctx->pos + n + 1;
384 if (total > log_ctx->size) {
385 char *buf = (char *)kvcalloc(total, sizeof(char), GFP_KERNEL);
388 memcpy(buf, log_ctx->buf, log_ctx->pos);
392 log_ctx->size = total;
399 /* Write the formatted string to the log buffer. */
402 log_ctx->buf + log_ctx->pos,
403 log_ctx->size - log_ctx->pos,
412 void dm_dtn_log_end(struct dc_context *ctx,
413 struct dc_log_buffer_ctx *log_ctx)
415 static const char msg[] = "[dtn end]\n";
422 dm_dtn_log_append_v(ctx, log_ctx, "%s", msg);
425 bool dm_helpers_dp_mst_start_top_mgr(
426 struct dc_context *ctx,
427 const struct dc_link *link,
430 struct amdgpu_dm_connector *aconnector = link->priv;
433 DRM_ERROR("Failed to find connector for link!");
438 DRM_INFO("DM_MST: Differing MST start on aconnector: %p [id: %d]\n",
439 aconnector, aconnector->base.base.id);
443 DRM_INFO("DM_MST: starting TM on aconnector: %p [id: %d]\n",
444 aconnector, aconnector->base.base.id);
446 return (drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true) == 0);
449 bool dm_helpers_dp_mst_stop_top_mgr(
450 struct dc_context *ctx,
451 struct dc_link *link)
453 struct amdgpu_dm_connector *aconnector = link->priv;
457 DRM_ERROR("Failed to find connector for link!");
461 DRM_INFO("DM_MST: stopping TM on aconnector: %p [id: %d]\n",
462 aconnector, aconnector->base.base.id);
464 if (aconnector->mst_mgr.mst_state == true) {
465 drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, false);
467 for (i = 0; i < MAX_SINKS_PER_LINK; i++) {
468 if (link->remote_sinks[i] == NULL)
471 if (link->remote_sinks[i]->sink_signal ==
472 SIGNAL_TYPE_DISPLAY_PORT_MST) {
473 dc_link_remove_remote_sink(link, link->remote_sinks[i]);
475 if (aconnector->dc_sink) {
476 dc_sink_release(aconnector->dc_sink);
477 aconnector->dc_sink = NULL;
478 aconnector->dc_link->cur_link_settings.lane_count = 0;
487 bool dm_helpers_dp_read_dpcd(
488 struct dc_context *ctx,
489 const struct dc_link *link,
495 struct amdgpu_dm_connector *aconnector = link->priv;
498 DC_LOG_DC("Failed to find connector for link!\n");
502 return drm_dp_dpcd_read(&aconnector->dm_dp_aux.aux, address,
506 bool dm_helpers_dp_write_dpcd(
507 struct dc_context *ctx,
508 const struct dc_link *link,
513 struct amdgpu_dm_connector *aconnector = link->priv;
516 DRM_ERROR("Failed to find connector for link!");
520 return drm_dp_dpcd_write(&aconnector->dm_dp_aux.aux,
521 address, (uint8_t *)data, size) > 0;
524 bool dm_helpers_submit_i2c(
525 struct dc_context *ctx,
526 const struct dc_link *link,
527 struct i2c_command *cmd)
529 struct amdgpu_dm_connector *aconnector = link->priv;
530 struct i2c_msg *msgs;
532 int num = cmd->number_of_payloads;
536 DRM_ERROR("Failed to find connector for link!");
540 msgs = kcalloc(num, sizeof(struct i2c_msg), GFP_KERNEL);
545 for (i = 0; i < num; i++) {
546 msgs[i].flags = cmd->payloads[i].write ? 0 : I2C_M_RD;
547 msgs[i].addr = cmd->payloads[i].address;
548 msgs[i].len = cmd->payloads[i].length;
549 msgs[i].buf = cmd->payloads[i].data;
552 result = i2c_transfer(&aconnector->i2c->base, msgs, num) == num;
559 #if defined(CONFIG_DRM_AMD_DC_DCN)
560 static bool execute_synaptics_rc_command(struct drm_dp_aux *aux,
567 bool success = false;
568 unsigned char rc_data[16] = {0};
569 unsigned char rc_offset[4] = {0};
570 unsigned char rc_length[2] = {0};
571 unsigned char rc_cmd = 0;
572 unsigned char rc_result = 0xFF;
578 memmove(rc_data, data, length);
579 ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_DATA, rc_data, sizeof(rc_data));
583 rc_offset[0] = (unsigned char) offset & 0xFF;
584 rc_offset[1] = (unsigned char) (offset >> 8) & 0xFF;
585 rc_offset[2] = (unsigned char) (offset >> 16) & 0xFF;
586 rc_offset[3] = (unsigned char) (offset >> 24) & 0xFF;
587 ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_OFFSET, rc_offset, sizeof(rc_offset));
590 rc_length[0] = (unsigned char) length & 0xFF;
591 rc_length[1] = (unsigned char) (length >> 8) & 0xFF;
592 ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_LENGTH, rc_length, sizeof(rc_length));
596 ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_COMMAND, &rc_cmd, sizeof(rc_cmd));
599 DRM_ERROR(" execute_synaptics_rc_command - write cmd ..., err = %d\n", ret);
603 // poll until active is 0
604 for (i = 0; i < 10; i++) {
605 drm_dp_dpcd_read(aux, SYNAPTICS_RC_COMMAND, &rc_cmd, sizeof(rc_cmd));
613 drm_dp_dpcd_read(aux, SYNAPTICS_RC_RESULT, &rc_result, sizeof(rc_result));
614 success = (rc_result == 0);
616 if (success && !is_write_cmd) {
618 drm_dp_dpcd_read(aux, SYNAPTICS_RC_DATA, data, length);
621 DC_LOG_DC(" execute_synaptics_rc_command - success = %d\n", success);
626 static void apply_synaptics_fifo_reset_wa(struct drm_dp_aux *aux)
628 unsigned char data[16] = {0};
630 DC_LOG_DC("Start apply_synaptics_fifo_reset_wa\n");
639 if (!execute_synaptics_rc_command(aux, true, 0x01, 5, 0, data))
643 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220998, data))
646 data[0] &= (~(1 << 1)); // set bit 1 to 0
647 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x220998, data))
650 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220D98, data))
653 data[0] &= (~(1 << 1)); // set bit 1 to 0
654 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x220D98, data))
657 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x221198, data))
660 data[0] &= (~(1 << 1)); // set bit 1 to 0
661 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x221198, data))
665 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220998, data))
668 data[0] |= (1 << 1); // set bit 1 to 1
669 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x220998, data))
672 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x220D98, data))
675 data[0] |= (1 << 1); // set bit 1 to 1
678 if (!execute_synaptics_rc_command(aux, false, 0x31, 4, 0x221198, data))
681 data[0] |= (1 << 1); // set bit 1 to 1
682 if (!execute_synaptics_rc_command(aux, true, 0x21, 4, 0x221198, data))
686 if (!execute_synaptics_rc_command(aux, true, 0x02, 0, 0, NULL))
689 DC_LOG_DC("Done apply_synaptics_fifo_reset_wa\n");
692 static uint8_t write_dsc_enable_synaptics_non_virtual_dpcd_mst(
693 struct drm_dp_aux *aux,
694 const struct dc_stream_state *stream,
699 DC_LOG_DC("Configure DSC to non-virtual dpcd synaptics\n");
702 /* When DSC is enabled on previous boot and reboot with the hub,
703 * there is a chance that Synaptics hub gets stuck during reboot sequence.
704 * Applying a workaround to reset Synaptics SDP fifo before enabling the first stream
706 if (!stream->link->link_status.link_active &&
707 memcmp(stream->link->dpcd_caps.branch_dev_name,
708 (int8_t *)SYNAPTICS_DEVICE_ID, 4) == 0)
709 apply_synaptics_fifo_reset_wa(aux);
711 ret = drm_dp_dpcd_write(aux, DP_DSC_ENABLE, &enable, 1);
712 DRM_INFO("Send DSC enable to synaptics\n");
715 /* Synaptics hub not support virtual dpcd,
716 * external monitor occur garbage while disable DSC,
717 * Disable DSC only when entire link status turn to false,
719 if (!stream->link->link_status.link_active) {
720 ret = drm_dp_dpcd_write(aux, DP_DSC_ENABLE, &enable, 1);
721 DRM_INFO("Send DSC disable to synaptics\n");
729 bool dm_helpers_dp_write_dsc_enable(
730 struct dc_context *ctx,
731 const struct dc_stream_state *stream,
734 uint8_t enable_dsc = enable ? 1 : 0;
735 struct amdgpu_dm_connector *aconnector;
741 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
742 aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
744 if (!aconnector->dsc_aux)
747 #if defined(CONFIG_DRM_AMD_DC_DCN)
748 // apply w/a to synaptics
749 if (needs_dsc_aux_workaround(aconnector->dc_link) &&
750 (aconnector->mst_downstream_port_present.byte & 0x7) != 0x3)
751 return write_dsc_enable_synaptics_non_virtual_dpcd_mst(
752 aconnector->dsc_aux, stream, enable_dsc);
755 ret = drm_dp_dpcd_write(aconnector->dsc_aux, DP_DSC_ENABLE, &enable_dsc, 1);
756 DC_LOG_DC("Send DSC %s to MST RX\n", enable_dsc ? "enable" : "disable");
759 if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT || stream->signal == SIGNAL_TYPE_EDP) {
760 #if defined(CONFIG_DRM_AMD_DC_DCN)
761 if (stream->sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) {
763 ret = dm_helpers_dp_write_dpcd(ctx, stream->link, DP_DSC_ENABLE, &enable_dsc, 1);
764 DC_LOG_DC("Send DSC %s to SST RX\n", enable_dsc ? "enable" : "disable");
765 #if defined(CONFIG_DRM_AMD_DC_DCN)
766 } else if (stream->sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) {
767 ret = dm_helpers_dp_write_dpcd(ctx, stream->link, DP_DSC_ENABLE, &enable_dsc, 1);
768 DC_LOG_DC("Send DSC %s to DP-HDMI PCON\n", enable_dsc ? "enable" : "disable");
776 bool dm_helpers_is_dp_sink_present(struct dc_link *link)
778 bool dp_sink_present;
779 struct amdgpu_dm_connector *aconnector = link->priv;
782 BUG_ON("Failed to find connector for link!");
786 mutex_lock(&aconnector->dm_dp_aux.aux.hw_mutex);
787 dp_sink_present = dc_link_is_dp_sink_present(link);
788 mutex_unlock(&aconnector->dm_dp_aux.aux.hw_mutex);
789 return dp_sink_present;
792 enum dc_edid_status dm_helpers_read_local_edid(
793 struct dc_context *ctx,
794 struct dc_link *link,
795 struct dc_sink *sink)
797 struct amdgpu_dm_connector *aconnector = link->priv;
798 struct drm_connector *connector = &aconnector->base;
799 struct i2c_adapter *ddc;
801 enum dc_edid_status edid_status;
805 ddc = &aconnector->dm_dp_aux.aux.ddc;
807 ddc = &aconnector->i2c->base;
809 /* some dongles read edid incorrectly the first time,
810 * do check sum and retry to make sure read correct edid.
814 edid = drm_get_edid(&aconnector->base, ddc);
816 /* DP Compliance Test 4.2.2.6 */
817 if (link->aux_mode && connector->edid_corrupt)
818 drm_dp_send_real_edid_checksum(&aconnector->dm_dp_aux.aux, connector->real_edid_checksum);
820 if (!edid && connector->edid_corrupt) {
821 connector->edid_corrupt = false;
822 return EDID_BAD_CHECKSUM;
826 return EDID_NO_RESPONSE;
828 sink->dc_edid.length = EDID_LENGTH * (edid->extensions + 1);
829 memmove(sink->dc_edid.raw_edid, (uint8_t *)edid, sink->dc_edid.length);
831 /* We don't need the original edid anymore */
834 edid_status = dm_helpers_parse_edid_caps(
839 } while (edid_status == EDID_BAD_CHECKSUM && --retry > 0);
841 if (edid_status != EDID_OK)
842 DRM_ERROR("EDID err: %d, on connector: %s",
844 aconnector->base.name);
846 /* DP Compliance Test 4.2.2.3 */
848 drm_dp_send_real_edid_checksum(&aconnector->dm_dp_aux.aux, sink->dc_edid.raw_edid[sink->dc_edid.length-1]);
852 int dm_helper_dmub_aux_transfer_sync(
853 struct dc_context *ctx,
854 const struct dc_link *link,
855 struct aux_payload *payload,
856 enum aux_return_code_type *operation_result)
858 return amdgpu_dm_process_dmub_aux_transfer_sync(true, ctx,
859 link->link_index, (void *)payload,
860 (void *)operation_result);
863 int dm_helpers_dmub_set_config_sync(struct dc_context *ctx,
864 const struct dc_link *link,
865 struct set_config_cmd_payload *payload,
866 enum set_config_status *operation_result)
868 return amdgpu_dm_process_dmub_aux_transfer_sync(false, ctx,
869 link->link_index, (void *)payload,
870 (void *)operation_result);
873 void dm_set_dcn_clocks(struct dc_context *ctx, struct dc_clocks *clks)
875 /* TODO: something */
878 void dm_helpers_smu_timeout(struct dc_context *ctx, unsigned int msg_id, unsigned int param, unsigned int timeout_us)
881 //amdgpu_device_gpu_recover(dc_context->driver-context, NULL);
884 void *dm_helpers_allocate_gpu_mem(
885 struct dc_context *ctx,
886 enum dc_gpu_mem_alloc_type type,
890 struct amdgpu_device *adev = ctx->driver_context;
891 struct dal_allocation *da;
892 u32 domain = (type == DC_MEM_ALLOC_TYPE_GART) ?
893 AMDGPU_GEM_DOMAIN_GTT : AMDGPU_GEM_DOMAIN_VRAM;
896 da = kzalloc(sizeof(struct dal_allocation), GFP_KERNEL);
900 ret = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE,
902 &da->gpu_addr, &da->cpu_ptr);
904 *addr = da->gpu_addr;
911 /* add da to list in dm */
912 list_add(&da->list, &adev->dm.da_list);
917 void dm_helpers_free_gpu_mem(
918 struct dc_context *ctx,
919 enum dc_gpu_mem_alloc_type type,
922 struct amdgpu_device *adev = ctx->driver_context;
923 struct dal_allocation *da;
925 /* walk the da list in DM */
926 list_for_each_entry(da, &adev->dm.da_list, list) {
927 if (pvMem == da->cpu_ptr) {
928 amdgpu_bo_free_kernel(&da->bo, &da->gpu_addr, &da->cpu_ptr);
936 bool dm_helpers_dmub_outbox_interrupt_control(struct dc_context *ctx, bool enable)
938 enum dc_irq_source irq_source;
941 irq_source = DC_IRQ_SOURCE_DMCUB_OUTBOX;
943 ret = dc_interrupt_set(ctx->dc, irq_source, enable);
945 DRM_DEBUG_DRIVER("Dmub trace irq %sabling: r=%d\n",
946 enable ? "en" : "dis", ret);
950 void dm_helpers_mst_enable_stream_features(const struct dc_stream_state *stream)
952 /* TODO: virtual DPCD */
953 struct dc_link *link = stream->link;
954 union down_spread_ctrl old_downspread;
955 union down_spread_ctrl new_downspread;
957 if (link->aux_access_disabled)
960 if (!dm_helpers_dp_read_dpcd(link->ctx, link, DP_DOWNSPREAD_CTRL,
962 sizeof(old_downspread)))
965 new_downspread.raw = old_downspread.raw;
966 new_downspread.bits.IGNORE_MSA_TIMING_PARAM =
967 (stream->ignore_msa_timing_param) ? 1 : 0;
969 if (new_downspread.raw != old_downspread.raw)
970 dm_helpers_dp_write_dpcd(link->ctx, link, DP_DOWNSPREAD_CTRL,
972 sizeof(new_downspread));
975 void dm_set_phyd32clk(struct dc_context *ctx, int freq_khz)
980 #if defined(CONFIG_DRM_AMD_DC_DCN)
981 void dm_helpers_enable_periodic_detection(struct dc_context *ctx, bool enable)
983 /* TODO: add periodic detection implementation */