drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <linux/uaccess.h>
  27
  28 #include "dc.h"
  29 #include "amdgpu.h"
  30 #include "amdgpu_dm.h"
  31 #include "amdgpu_dm_debugfs.h"
  32 #include "dm_helpers.h"
  33 #include "dmub/dmub_srv.h"
  34 #include "resource.h"
  35 #include "dsc.h"
  36 #include "dc_link_dp.h"
  37 #include "link_hwss.h"
  38 #include "dc/dc_dmub_srv.h"
  39
  40 struct dmub_debugfs_trace_header {
  41         uint32_t entry_count;
  42         uint32_t reserved[3];
  43 };
  44
  45 struct dmub_debugfs_trace_entry {
  46         uint32_t trace_code;
  47         uint32_t tick_count;
  48         uint32_t param0;
  49         uint32_t param1;
  50 };
  51
  52 static inline const char *yesno(bool v)
  53 {
  54         return v ? "yes" : "no";
  55 }
  56
  57 /* parse_write_buffer_into_params - Helper function to parse debugfs write buffer into an array
  58  *
  59  * Function takes in attributes passed to debugfs write entry
  60  * and writes into param array.
  61  * The user passes max_param_num to identify maximum number of
  62  * parameters that could be parsed.
  63  *
  64  */
  65 static int parse_write_buffer_into_params(char *wr_buf, uint32_t wr_buf_size,
  66                                           long *param, const char __user *buf,
  67                                           int max_param_num,
  68                                           uint8_t *param_nums)
  69 {
  70         char *wr_buf_ptr = NULL;
  71         uint32_t wr_buf_count = 0;
  72         int r;
  73         char *sub_str = NULL;
  74         const char delimiter[3] = {' ', '\n', '\0'};
  75         uint8_t param_index = 0;
  76
  77         *param_nums = 0;
  78
  79         wr_buf_ptr = wr_buf;
  80
  81         /* r is bytes not be copied */
  82         if (copy_from_user(wr_buf_ptr, buf, wr_buf_size)) {
  83                 DRM_DEBUG_DRIVER("user data could not be read successfully\n");
  84                 return -EFAULT;
  85         }
  86
  87         /* check number of parameters. isspace could not differ space and \n */
  88         while ((*wr_buf_ptr != 0xa) && (wr_buf_count < wr_buf_size)) {
  89                 /* skip space*/
  90                 while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) {
  91                         wr_buf_ptr++;
  92                         wr_buf_count++;
  93                         }
  94
  95                 if (wr_buf_count == wr_buf_size)
  96                         break;
  97
  98                 /* skip non-space*/
  99                 while ((!isspace(*wr_buf_ptr)) && (wr_buf_count < wr_buf_size)) {
 100                         wr_buf_ptr++;
 101                         wr_buf_count++;
 102                 }
 103
 104                 (*param_nums)++;
 105
 106                 if (wr_buf_count == wr_buf_size)
 107                         break;
 108         }
 109
 110         if (*param_nums > max_param_num)
 111                 *param_nums = max_param_num;
 112
 113         wr_buf_ptr = wr_buf; /* reset buf pointer */
 114         wr_buf_count = 0; /* number of char already checked */
 115
 116         while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) {
 117                 wr_buf_ptr++;
 118                 wr_buf_count++;
 119         }
 120
 121         while (param_index < *param_nums) {
 122                 /* after strsep, wr_buf_ptr will be moved to after space */
 123                 sub_str = strsep(&wr_buf_ptr, delimiter);
 124
 125                 r = kstrtol(sub_str, 16, &(param[param_index]));
 126
 127                 if (r)
 128                         DRM_DEBUG_DRIVER("string to int convert error code: %d\n", r);
 129
 130                 param_index++;
 131         }
 132
 133         return 0;
 134 }
 135
 136 /* function description
 137  * get/ set DP configuration: lane_count, link_rate, spread_spectrum
 138  *
 139  * valid lane count value: 1, 2, 4
 140  * valid link rate value:
 141  * 06h = 1.62Gbps per lane
 142  * 0Ah = 2.7Gbps per lane
 143  * 0Ch = 3.24Gbps per lane
 144  * 14h = 5.4Gbps per lane
 145  * 1Eh = 8.1Gbps per lane
 146  *
 147  * debugfs is located at /sys/kernel/debug/dri/0/DP-x/link_settings
 148  *
 149  * --- to get dp configuration
 150  *
 151  * cat /sys/kernel/debug/dri/0/DP-x/link_settings
 152  *
 153  * It will list current, verified, reported, preferred dp configuration.
 154  * current -- for current video mode
 155  * verified --- maximum configuration which pass link training
 156  * reported --- DP rx report caps (DPCD register offset 0, 1 2)
 157  * preferred --- user force settings
 158  *
 159  * --- set (or force) dp configuration
 160  *
 161  * echo <lane_count>  <link_rate> > link_settings
 162  *
 163  * for example, to force to  2 lane, 2.7GHz,
 164  * echo 4 0xa > /sys/kernel/debug/dri/0/DP-x/link_settings
 165  *
 166  * spread_spectrum could not be changed dynamically.
 167  *
 168  * in case invalid lane count, link rate are force, no hw programming will be
 169  * done. please check link settings after force operation to see if HW get
 170  * programming.
 171  *
 172  * cat /sys/kernel/debug/dri/0/DP-x/link_settings
 173  *
 174  * check current and preferred settings.
 175  *
 176  */
 177 static ssize_t dp_link_settings_read(struct file *f, char __user *buf,
 178                                  size_t size, loff_t *pos)
 179 {
 180         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
 181         struct dc_link *link = connector->dc_link;
 182         char *rd_buf = NULL;
 183         char *rd_buf_ptr = NULL;
 184         const uint32_t rd_buf_size = 100;
 185         uint32_t result = 0;
 186         uint8_t str_len = 0;
 187         int r;
 188
 189         if (*pos & 3 || size & 3)
 190                 return -EINVAL;
 191
 192         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
 193         if (!rd_buf)
 194                 return 0;
 195
 196         rd_buf_ptr = rd_buf;
 197
 198         str_len = strlen("Current:  %d  0x%x  %d  ");
 199         snprintf(rd_buf_ptr, str_len, "Current:  %d  0x%x  %d  ",
 200                         link->cur_link_settings.lane_count,
 201                         link->cur_link_settings.link_rate,
 202                         link->cur_link_settings.link_spread);
 203         rd_buf_ptr += str_len;
 204
 205         str_len = strlen("Verified:  %d  0x%x  %d  ");
 206         snprintf(rd_buf_ptr, str_len, "Verified:  %d  0x%x  %d  ",
 207                         link->verified_link_cap.lane_count,
 208                         link->verified_link_cap.link_rate,
 209                         link->verified_link_cap.link_spread);
 210         rd_buf_ptr += str_len;
 211
 212         str_len = strlen("Reported:  %d  0x%x  %d  ");
 213         snprintf(rd_buf_ptr, str_len, "Reported:  %d  0x%x  %d  ",
 214                         link->reported_link_cap.lane_count,
 215                         link->reported_link_cap.link_rate,
 216                         link->reported_link_cap.link_spread);
 217         rd_buf_ptr += str_len;
 218
 219         str_len = strlen("Preferred:  %d  0x%x  %d  ");
 220         snprintf(rd_buf_ptr, str_len, "Preferred:  %d  0x%x  %d\n",
 221                         link->preferred_link_setting.lane_count,
 222                         link->preferred_link_setting.link_rate,
 223                         link->preferred_link_setting.link_spread);
 224
 225         while (size) {
 226                 if (*pos >= rd_buf_size)
 227                         break;
 228
 229                 r = put_user(*(rd_buf + result), buf);
 230                 if (r)
 231                         return r; /* r = -EFAULT */
 232
 233                 buf += 1;
 234                 size -= 1;
 235                 *pos += 1;
 236                 result += 1;
 237         }
 238
 239         kfree(rd_buf);
 240         return result;
 241 }
 242
 243 static ssize_t dp_link_settings_write(struct file *f, const char __user *buf,
 244                                  size_t size, loff_t *pos)
 245 {
 246         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
 247         struct dc_link *link = connector->dc_link;
 248         struct dc *dc = (struct dc *)link->dc;
 249         struct dc_link_settings prefer_link_settings;
 250         char *wr_buf = NULL;
 251         const uint32_t wr_buf_size = 40;
 252         /* 0: lane_count; 1: link_rate */
 253         int max_param_num = 2;
 254         uint8_t param_nums = 0;
 255         long param[2];
 256         bool valid_input = true;
 257
 258         if (size == 0)
 259                 return -EINVAL;
 260
 261         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
 262         if (!wr_buf)
 263                 return -ENOSPC;
 264
 265         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
 266                                            (long *)param, buf,
 267                                            max_param_num,
 268                                            &param_nums)) {
 269                 kfree(wr_buf);
 270                 return -EINVAL;
 271         }
 272
 273         if (param_nums <= 0) {
 274                 kfree(wr_buf);
 275                 DRM_DEBUG_DRIVER("user data not be read\n");
 276                 return -EINVAL;
 277         }
 278
 279         switch (param[0]) {
 280         case LANE_COUNT_ONE:
 281         case LANE_COUNT_TWO:
 282         case LANE_COUNT_FOUR:
 283                 break;
 284         default:
 285                 valid_input = false;
 286                 break;
 287         }
 288
 289         switch (param[1]) {
 290         case LINK_RATE_LOW:
 291         case LINK_RATE_HIGH:
 292         case LINK_RATE_RBR2:
 293         case LINK_RATE_HIGH2:
 294         case LINK_RATE_HIGH3:
 295 #if defined(CONFIG_DRM_AMD_DC_DCN)
 296         case LINK_RATE_UHBR10:
 297 #endif
 298                 break;
 299         default:
 300                 valid_input = false;
 301                 break;
 302         }
 303
 304         if (!valid_input) {
 305                 kfree(wr_buf);
 306                 DRM_DEBUG_DRIVER("Invalid Input value No HW will be programmed\n");
 307                 return size;
 308         }
 309
 310         /* save user force lane_count, link_rate to preferred settings
 311          * spread spectrum will not be changed
 312          */
 313         prefer_link_settings.link_spread = link->cur_link_settings.link_spread;
 314         prefer_link_settings.use_link_rate_set = false;
 315         prefer_link_settings.lane_count = param[0];
 316         prefer_link_settings.link_rate = param[1];
 317
 318         dc_link_set_preferred_training_settings(dc, &prefer_link_settings, NULL, link, true);
 319
 320         kfree(wr_buf);
 321         return size;
 322 }
 323
 324 /* function: get current DP PHY settings: voltage swing, pre-emphasis,
 325  * post-cursor2 (defined by VESA DP specification)
 326  *
 327  * valid values
 328  * voltage swing: 0,1,2,3
 329  * pre-emphasis : 0,1,2,3
 330  * post cursor2 : 0,1,2,3
 331  *
 332  *
 333  * how to use this debugfs
 334  *
 335  * debugfs is located at /sys/kernel/debug/dri/0/DP-x
 336  *
 337  * there will be directories, like DP-1, DP-2,DP-3, etc. for DP display
 338  *
 339  * To figure out which DP-x is the display for DP to be check,
 340  * cd DP-x
 341  * ls -ll
 342  * There should be debugfs file, like link_settings, phy_settings.
 343  * cat link_settings
 344  * from lane_count, link_rate to figure which DP-x is for display to be worked
 345  * on
 346  *
 347  * To get current DP PHY settings,
 348  * cat phy_settings
 349  *
 350  * To change DP PHY settings,
 351  * echo <voltage_swing> <pre-emphasis> <post_cursor2> > phy_settings
 352  * for examle, to change voltage swing to 2, pre-emphasis to 3, post_cursor2 to
 353  * 0,
 354  * echo 2 3 0 > phy_settings
 355  *
 356  * To check if change be applied, get current phy settings by
 357  * cat phy_settings
 358  *
 359  * In case invalid values are set by user, like
 360  * echo 1 4 0 > phy_settings
 361  *
 362  * HW will NOT be programmed by these settings.
 363  * cat phy_settings will show the previous valid settings.
 364  */
 365 static ssize_t dp_phy_settings_read(struct file *f, char __user *buf,
 366                                  size_t size, loff_t *pos)
 367 {
 368         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
 369         struct dc_link *link = connector->dc_link;
 370         char *rd_buf = NULL;
 371         const uint32_t rd_buf_size = 20;
 372         uint32_t result = 0;
 373         int r;
 374
 375         if (*pos & 3 || size & 3)
 376                 return -EINVAL;
 377
 378         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
 379         if (!rd_buf)
 380                 return -EINVAL;
 381
 382         snprintf(rd_buf, rd_buf_size, "  %d  %d  %d\n",
 383                         link->cur_lane_setting[0].VOLTAGE_SWING,
 384                         link->cur_lane_setting[0].PRE_EMPHASIS,
 385                         link->cur_lane_setting[0].POST_CURSOR2);
 386
 387         while (size) {
 388                 if (*pos >= rd_buf_size)
 389                         break;
 390
 391                 r = put_user((*(rd_buf + result)), buf);
 392                 if (r)
 393                         return r; /* r = -EFAULT */
 394
 395                 buf += 1;
 396                 size -= 1;
 397                 *pos += 1;
 398                 result += 1;
 399         }
 400
 401         kfree(rd_buf);
 402         return result;
 403 }
 404
 405 static int dp_lttpr_status_show(struct seq_file *m, void *d)
 406 {
 407         char *data;
 408         struct amdgpu_dm_connector *connector = file_inode(m->file)->i_private;
 409         struct dc_link *link = connector->dc_link;
 410         uint32_t read_size = 1;
 411         uint8_t repeater_count = 0;
 412
 413         data = kzalloc(read_size, GFP_KERNEL);
 414         if (!data)
 415                 return 0;
 416
 417         dm_helpers_dp_read_dpcd(link->ctx, link, 0xF0002, data, read_size);
 418
 419         switch ((uint8_t)*data) {
 420         case 0x80:
 421                 repeater_count = 1;
 422                 break;
 423         case 0x40:
 424                 repeater_count = 2;
 425                 break;
 426         case 0x20:
 427                 repeater_count = 3;
 428                 break;
 429         case 0x10:
 430                 repeater_count = 4;
 431                 break;
 432         case 0x8:
 433                 repeater_count = 5;
 434                 break;
 435         case 0x4:
 436                 repeater_count = 6;
 437                 break;
 438         case 0x2:
 439                 repeater_count = 7;
 440                 break;
 441         case 0x1:
 442                 repeater_count = 8;
 443                 break;
 444         case 0x0:
 445                 repeater_count = 0;
 446                 break;
 447         default:
 448                 repeater_count = (uint8_t)*data;
 449                 break;
 450         }
 451
 452         seq_printf(m, "phy repeater count: %d\n", repeater_count);
 453
 454         dm_helpers_dp_read_dpcd(link->ctx, link, 0xF0003, data, read_size);
 455
 456         if ((uint8_t)*data == 0x55)
 457                 seq_printf(m, "phy repeater mode: transparent\n");
 458         else if ((uint8_t)*data == 0xAA)
 459                 seq_printf(m, "phy repeater mode: non-transparent\n");
 460         else if ((uint8_t)*data == 0x00)
 461                 seq_printf(m, "phy repeater mode: non lttpr\n");
 462         else
 463                 seq_printf(m, "phy repeater mode: read error\n");
 464
 465         kfree(data);
 466         return 0;
 467 }
 468
 469 static ssize_t dp_phy_settings_write(struct file *f, const char __user *buf,
 470                                  size_t size, loff_t *pos)
 471 {
 472         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
 473         struct dc_link *link = connector->dc_link;
 474         struct dc *dc = (struct dc *)link->dc;
 475         char *wr_buf = NULL;
 476         uint32_t wr_buf_size = 40;
 477         long param[3];
 478         bool use_prefer_link_setting;
 479         struct link_training_settings link_lane_settings;
 480         int max_param_num = 3;
 481         uint8_t param_nums = 0;
 482         int r = 0;
 483
 484
 485         if (size == 0)
 486                 return -EINVAL;
 487
 488         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
 489         if (!wr_buf)
 490                 return -ENOSPC;
 491
 492         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
 493                                            (long *)param, buf,
 494                                            max_param_num,
 495                                            &param_nums)) {
 496                 kfree(wr_buf);
 497                 return -EINVAL;
 498         }
 499
 500         if (param_nums <= 0) {
 501                 kfree(wr_buf);
 502                 DRM_DEBUG_DRIVER("user data not be read\n");
 503                 return -EINVAL;
 504         }
 505
 506         if ((param[0] > VOLTAGE_SWING_MAX_LEVEL) ||
 507                         (param[1] > PRE_EMPHASIS_MAX_LEVEL) ||
 508                         (param[2] > POST_CURSOR2_MAX_LEVEL)) {
 509                 kfree(wr_buf);
 510                 DRM_DEBUG_DRIVER("Invalid Input No HW will be programmed\n");
 511                 return size;
 512         }
 513
 514         /* get link settings: lane count, link rate */
 515         use_prefer_link_setting =
 516                 ((link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN) &&
 517                 (link->test_pattern_enabled));
 518
 519         memset(&link_lane_settings, 0, sizeof(link_lane_settings));
 520
 521         if (use_prefer_link_setting) {
 522                 link_lane_settings.link_settings.lane_count =
 523                                 link->preferred_link_setting.lane_count;
 524                 link_lane_settings.link_settings.link_rate =
 525                                 link->preferred_link_setting.link_rate;
 526                 link_lane_settings.link_settings.link_spread =
 527                                 link->preferred_link_setting.link_spread;
 528         } else {
 529                 link_lane_settings.link_settings.lane_count =
 530                                 link->cur_link_settings.lane_count;
 531                 link_lane_settings.link_settings.link_rate =
 532                                 link->cur_link_settings.link_rate;
 533                 link_lane_settings.link_settings.link_spread =
 534                                 link->cur_link_settings.link_spread;
 535         }
 536
 537         /* apply phy settings from user */
 538         for (r = 0; r < link_lane_settings.link_settings.lane_count; r++) {
 539                 link_lane_settings.lane_settings[r].VOLTAGE_SWING =
 540                                 (enum dc_voltage_swing) (param[0]);
 541                 link_lane_settings.lane_settings[r].PRE_EMPHASIS =
 542                                 (enum dc_pre_emphasis) (param[1]);
 543                 link_lane_settings.lane_settings[r].POST_CURSOR2 =
 544                                 (enum dc_post_cursor2) (param[2]);
 545         }
 546
 547         /* program ASIC registers and DPCD registers */
 548         dc_link_set_drive_settings(dc, &link_lane_settings, link);
 549
 550         kfree(wr_buf);
 551         return size;
 552 }
 553
 554 /* function description
 555  *
 556  * set PHY layer or Link layer test pattern
 557  * PHY test pattern is used for PHY SI check.
 558  * Link layer test will not affect PHY SI.
 559  *
 560  * Reset Test Pattern:
 561  * 0 = DP_TEST_PATTERN_VIDEO_MODE
 562  *
 563  * PHY test pattern supported:
 564  * 1 = DP_TEST_PATTERN_D102
 565  * 2 = DP_TEST_PATTERN_SYMBOL_ERROR
 566  * 3 = DP_TEST_PATTERN_PRBS7
 567  * 4 = DP_TEST_PATTERN_80BIT_CUSTOM
 568  * 5 = DP_TEST_PATTERN_CP2520_1
 569  * 6 = DP_TEST_PATTERN_CP2520_2 = DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE
 570  * 7 = DP_TEST_PATTERN_CP2520_3
 571  *
 572  * DP PHY Link Training Patterns
 573  * 8 = DP_TEST_PATTERN_TRAINING_PATTERN1
 574  * 9 = DP_TEST_PATTERN_TRAINING_PATTERN2
 575  * a = DP_TEST_PATTERN_TRAINING_PATTERN3
 576  * b = DP_TEST_PATTERN_TRAINING_PATTERN4
 577  *
 578  * DP Link Layer Test pattern
 579  * c = DP_TEST_PATTERN_COLOR_SQUARES
 580  * d = DP_TEST_PATTERN_COLOR_SQUARES_CEA
 581  * e = DP_TEST_PATTERN_VERTICAL_BARS
 582  * f = DP_TEST_PATTERN_HORIZONTAL_BARS
 583  * 10= DP_TEST_PATTERN_COLOR_RAMP
 584  *
 585  * debugfs phy_test_pattern is located at /syskernel/debug/dri/0/DP-x
 586  *
 587  * --- set test pattern
 588  * echo <test pattern #> > test_pattern
 589  *
 590  * If test pattern # is not supported, NO HW programming will be done.
 591  * for DP_TEST_PATTERN_80BIT_CUSTOM, it needs extra 10 bytes of data
 592  * for the user pattern. input 10 bytes data are separated by space
 593  *
 594  * echo 0x4 0x11 0x22 0x33 0x44 0x55 0x66 0x77 0x88 0x99 0xaa > test_pattern
 595  *
 596  * --- reset test pattern
 597  * echo 0 > test_pattern
 598  *
 599  * --- HPD detection is disabled when set PHY test pattern
 600  *
 601  * when PHY test pattern (pattern # within [1,7]) is set, HPD pin of HW ASIC
 602  * is disable. User could unplug DP display from DP connected and plug scope to
 603  * check test pattern PHY SI.
 604  * If there is need unplug scope and plug DP display back, do steps below:
 605  * echo 0 > phy_test_pattern
 606  * unplug scope
 607  * plug DP display.
 608  *
 609  * "echo 0 > phy_test_pattern" will re-enable HPD pin again so that video sw
 610  * driver could detect "unplug scope" and "plug DP display"
 611  */
 612 static ssize_t dp_phy_test_pattern_debugfs_write(struct file *f, const char __user *buf,
 613                                  size_t size, loff_t *pos)
 614 {
 615         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
 616         struct dc_link *link = connector->dc_link;
 617         char *wr_buf = NULL;
 618         uint32_t wr_buf_size = 100;
 619         long param[11] = {0x0};
 620         int max_param_num = 11;
 621         enum dp_test_pattern test_pattern = DP_TEST_PATTERN_UNSUPPORTED;
 622         bool disable_hpd = false;
 623         bool valid_test_pattern = false;
 624         uint8_t param_nums = 0;
 625         /* init with default 80bit custom pattern */
 626         uint8_t custom_pattern[10] = {
 627                         0x1f, 0x7c, 0xf0, 0xc1, 0x07,
 628                         0x1f, 0x7c, 0xf0, 0xc1, 0x07
 629                         };
 630         struct dc_link_settings prefer_link_settings = {LANE_COUNT_UNKNOWN,
 631                         LINK_RATE_UNKNOWN, LINK_SPREAD_DISABLED};
 632         struct dc_link_settings cur_link_settings = {LANE_COUNT_UNKNOWN,
 633                         LINK_RATE_UNKNOWN, LINK_SPREAD_DISABLED};
 634         struct link_training_settings link_training_settings;
 635         int i;
 636
 637         if (size == 0)
 638                 return -EINVAL;
 639
 640         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
 641         if (!wr_buf)
 642                 return -ENOSPC;
 643
 644         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
 645                                            (long *)param, buf,
 646                                            max_param_num,
 647                                            &param_nums)) {
 648                 kfree(wr_buf);
 649                 return -EINVAL;
 650         }
 651
 652         if (param_nums <= 0) {
 653                 kfree(wr_buf);
 654                 DRM_DEBUG_DRIVER("user data not be read\n");
 655                 return -EINVAL;
 656         }
 657
 658
 659         test_pattern = param[0];
 660
 661         switch (test_pattern) {
 662         case DP_TEST_PATTERN_VIDEO_MODE:
 663         case DP_TEST_PATTERN_COLOR_SQUARES:
 664         case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
 665         case DP_TEST_PATTERN_VERTICAL_BARS:
 666         case DP_TEST_PATTERN_HORIZONTAL_BARS:
 667         case DP_TEST_PATTERN_COLOR_RAMP:
 668                 valid_test_pattern = true;
 669                 break;
 670
 671         case DP_TEST_PATTERN_D102:
 672         case DP_TEST_PATTERN_SYMBOL_ERROR:
 673         case DP_TEST_PATTERN_PRBS7:
 674         case DP_TEST_PATTERN_80BIT_CUSTOM:
 675         case DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE:
 676         case DP_TEST_PATTERN_TRAINING_PATTERN4:
 677                 disable_hpd = true;
 678                 valid_test_pattern = true;
 679                 break;
 680
 681         default:
 682                 valid_test_pattern = false;
 683                 test_pattern = DP_TEST_PATTERN_UNSUPPORTED;
 684                 break;
 685         }
 686
 687         if (!valid_test_pattern) {
 688                 kfree(wr_buf);
 689                 DRM_DEBUG_DRIVER("Invalid Test Pattern Parameters\n");
 690                 return size;
 691         }
 692
 693         if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM) {
 694                 for (i = 0; i < 10; i++) {
 695                         if ((uint8_t) param[i + 1] != 0x0)
 696                                 break;
 697                 }
 698
 699                 if (i < 10) {
 700                         /* not use default value */
 701                         for (i = 0; i < 10; i++)
 702                                 custom_pattern[i] = (uint8_t) param[i + 1];
 703                 }
 704         }
 705
 706         /* Usage: set DP physical test pattern using debugfs with normal DP
 707          * panel. Then plug out DP panel and connect a scope to measure
 708          * For normal video mode and test pattern generated from CRCT,
 709          * they are visibile to user. So do not disable HPD.
 710          * Video Mode is also set to clear the test pattern, so enable HPD
 711          * because it might have been disabled after a test pattern was set.
 712          * AUX depends on HPD * sequence dependent, do not move!
 713          */
 714         if (!disable_hpd)
 715                 dc_link_enable_hpd(link);
 716
 717         prefer_link_settings.lane_count = link->verified_link_cap.lane_count;
 718         prefer_link_settings.link_rate = link->verified_link_cap.link_rate;
 719         prefer_link_settings.link_spread = link->verified_link_cap.link_spread;
 720
 721         cur_link_settings.lane_count = link->cur_link_settings.lane_count;
 722         cur_link_settings.link_rate = link->cur_link_settings.link_rate;
 723         cur_link_settings.link_spread = link->cur_link_settings.link_spread;
 724
 725         link_training_settings.link_settings = cur_link_settings;
 726
 727
 728         if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
 729                 if (prefer_link_settings.lane_count != LANE_COUNT_UNKNOWN &&
 730                         prefer_link_settings.link_rate !=  LINK_RATE_UNKNOWN &&
 731                         (prefer_link_settings.lane_count != cur_link_settings.lane_count ||
 732                         prefer_link_settings.link_rate != cur_link_settings.link_rate))
 733                         link_training_settings.link_settings = prefer_link_settings;
 734         }
 735
 736         for (i = 0; i < (unsigned int)(link_training_settings.link_settings.lane_count); i++)
 737                 link_training_settings.lane_settings[i] = link->cur_lane_setting[i];
 738
 739         dc_link_set_test_pattern(
 740                 link,
 741                 test_pattern,
 742                 DP_TEST_PATTERN_COLOR_SPACE_RGB,
 743                 &link_training_settings,
 744                 custom_pattern,
 745                 10);
 746
 747         /* Usage: Set DP physical test pattern using AMDDP with normal DP panel
 748          * Then plug out DP panel and connect a scope to measure DP PHY signal.
 749          * Need disable interrupt to avoid SW driver disable DP output. This is
 750          * done after the test pattern is set.
 751          */
 752         if (valid_test_pattern && disable_hpd)
 753                 dc_link_disable_hpd(link);
 754
 755         kfree(wr_buf);
 756
 757         return size;
 758 }
 759
 760 /*
 761  * Returns the DMCUB tracebuffer contents.
 762  * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmub_tracebuffer
 763  */
 764 static int dmub_tracebuffer_show(struct seq_file *m, void *data)
 765 {
 766         struct amdgpu_device *adev = m->private;
 767         struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
 768         struct dmub_debugfs_trace_entry *entries;
 769         uint8_t *tbuf_base;
 770         uint32_t tbuf_size, max_entries, num_entries, i;
 771
 772         if (!fb_info)
 773                 return 0;
 774
 775         tbuf_base = (uint8_t *)fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr;
 776         if (!tbuf_base)
 777                 return 0;
 778
 779         tbuf_size = fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size;
 780         max_entries = (tbuf_size - sizeof(struct dmub_debugfs_trace_header)) /
 781                       sizeof(struct dmub_debugfs_trace_entry);
 782
 783         num_entries =
 784                 ((struct dmub_debugfs_trace_header *)tbuf_base)->entry_count;
 785
 786         num_entries = min(num_entries, max_entries);
 787
 788         entries = (struct dmub_debugfs_trace_entry
 789                            *)(tbuf_base +
 790                               sizeof(struct dmub_debugfs_trace_header));
 791
 792         for (i = 0; i < num_entries; ++i) {
 793                 struct dmub_debugfs_trace_entry *entry = &entries[i];
 794
 795                 seq_printf(m,
 796                            "trace_code=%u tick_count=%u param0=%u param1=%u\n",
 797                            entry->trace_code, entry->tick_count, entry->param0,
 798                            entry->param1);
 799         }
 800
 801         return 0;
 802 }
 803
 804 /*
 805  * Returns the DMCUB firmware state contents.
 806  * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmub_fw_state
 807  */
 808 static int dmub_fw_state_show(struct seq_file *m, void *data)
 809 {
 810         struct amdgpu_device *adev = m->private;
 811         struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
 812         uint8_t *state_base;
 813         uint32_t state_size;
 814
 815         if (!fb_info)
 816                 return 0;
 817
 818         state_base = (uint8_t *)fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr;
 819         if (!state_base)
 820                 return 0;
 821
 822         state_size = fb_info->fb[DMUB_WINDOW_6_FW_STATE].size;
 823
 824         return seq_write(m, state_base, state_size);
 825 }
 826
 827 /* psr_capability_show() - show eDP panel PSR capability
 828  *
 829  * The read function: sink_psr_capability_show
 830  * Shows if sink has PSR capability or not.
 831  * If yes - the PSR version is appended
 832  *
 833  *      cat /sys/kernel/debug/dri/0/eDP-X/psr_capability
 834  *
 835  * Expected output:
 836  * "Sink support: no\n" - if panel doesn't support PSR
 837  * "Sink support: yes [0x01]\n" - if panel supports PSR1
 838  * "Driver support: no\n" - if driver doesn't support PSR
 839  * "Driver support: yes [0x01]\n" - if driver supports PSR1
 840  */
 841 static int psr_capability_show(struct seq_file *m, void *data)
 842 {
 843         struct drm_connector *connector = m->private;
 844         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
 845         struct dc_link *link = aconnector->dc_link;
 846
 847         if (!link)
 848                 return -ENODEV;
 849
 850         if (link->type == dc_connection_none)
 851                 return -ENODEV;
 852
 853         if (!(link->connector_signal & SIGNAL_TYPE_EDP))
 854                 return -ENODEV;
 855
 856         seq_printf(m, "Sink support: %s", yesno(link->dpcd_caps.psr_caps.psr_version != 0));
 857         if (link->dpcd_caps.psr_caps.psr_version)
 858                 seq_printf(m, " [0x%02x]", link->dpcd_caps.psr_caps.psr_version);
 859         seq_puts(m, "\n");
 860
 861         seq_printf(m, "Driver support: %s", yesno(link->psr_settings.psr_feature_enabled));
 862         if (link->psr_settings.psr_version)
 863                 seq_printf(m, " [0x%02x]", link->psr_settings.psr_version);
 864         seq_puts(m, "\n");
 865
 866         return 0;
 867 }
 868
 869 /*
 870  * Returns the current and maximum output bpc for the connector.
 871  * Example usage: cat /sys/kernel/debug/dri/0/DP-1/output_bpc
 872  */
 873 static int output_bpc_show(struct seq_file *m, void *data)
 874 {
 875         struct drm_connector *connector = m->private;
 876         struct drm_device *dev = connector->dev;
 877         struct drm_crtc *crtc = NULL;
 878         struct dm_crtc_state *dm_crtc_state = NULL;
 879         int res = -ENODEV;
 880         unsigned int bpc;
 881
 882         mutex_lock(&dev->mode_config.mutex);
 883         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
 884
 885         if (connector->state == NULL)
 886                 goto unlock;
 887
 888         crtc = connector->state->crtc;
 889         if (crtc == NULL)
 890                 goto unlock;
 891
 892         drm_modeset_lock(&crtc->mutex, NULL);
 893         if (crtc->state == NULL)
 894                 goto unlock;
 895
 896         dm_crtc_state = to_dm_crtc_state(crtc->state);
 897         if (dm_crtc_state->stream == NULL)
 898                 goto unlock;
 899
 900         switch (dm_crtc_state->stream->timing.display_color_depth) {
 901         case COLOR_DEPTH_666:
 902                 bpc = 6;
 903                 break;
 904         case COLOR_DEPTH_888:
 905                 bpc = 8;
 906                 break;
 907         case COLOR_DEPTH_101010:
 908                 bpc = 10;
 909                 break;
 910         case COLOR_DEPTH_121212:
 911                 bpc = 12;
 912                 break;
 913         case COLOR_DEPTH_161616:
 914                 bpc = 16;
 915                 break;
 916         default:
 917                 goto unlock;
 918         }
 919
 920         seq_printf(m, "Current: %u\n", bpc);
 921         seq_printf(m, "Maximum: %u\n", connector->display_info.bpc);
 922         res = 0;
 923
 924 unlock:
 925         if (crtc)
 926                 drm_modeset_unlock(&crtc->mutex);
 927
 928         drm_modeset_unlock(&dev->mode_config.connection_mutex);
 929         mutex_unlock(&dev->mode_config.mutex);
 930
 931         return res;
 932 }
 933
 934 /*
 935  * Example usage:
 936  * Disable dsc passthrough, i.e.,: have dsc decoding at converver, not external RX
 937  *   echo 1 /sys/kernel/debug/dri/0/DP-1/dsc_disable_passthrough
 938  * Enable dsc passthrough, i.e.,: have dsc passthrough to external RX
 939  *   echo 0 /sys/kernel/debug/dri/0/DP-1/dsc_disable_passthrough
 940  */
 941 static ssize_t dp_dsc_passthrough_set(struct file *f, const char __user *buf,
 942                                  size_t size, loff_t *pos)
 943 {
 944         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
 945         char *wr_buf = NULL;
 946         uint32_t wr_buf_size = 42;
 947         int max_param_num = 1;
 948         long param;
 949         uint8_t param_nums = 0;
 950
 951         if (size == 0)
 952                 return -EINVAL;
 953
 954         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
 955
 956         if (!wr_buf) {
 957                 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
 958                 return -ENOSPC;
 959         }
 960
 961         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
 962                                            &param, buf,
 963                                            max_param_num,
 964                                            &param_nums)) {
 965                 kfree(wr_buf);
 966                 return -EINVAL;
 967         }
 968
 969         aconnector->dsc_settings.dsc_force_disable_passthrough = param;
 970
 971         kfree(wr_buf);
 972         return 0;
 973 }
 974
 975 #ifdef CONFIG_DRM_AMD_DC_HDCP
 976 /*
 977  * Returns the HDCP capability of the Display (1.4 for now).
 978  *
 979  * NOTE* Not all HDMI displays report their HDCP caps even when they are capable.
 980  * Since its rare for a display to not be HDCP 1.4 capable, we set HDMI as always capable.
 981  *
 982  * Example usage: cat /sys/kernel/debug/dri/0/DP-1/hdcp_sink_capability
 983  *              or cat /sys/kernel/debug/dri/0/HDMI-A-1/hdcp_sink_capability
 984  */
 985 static int hdcp_sink_capability_show(struct seq_file *m, void *data)
 986 {
 987         struct drm_connector *connector = m->private;
 988         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
 989         bool hdcp_cap, hdcp2_cap;
 990
 991         if (connector->status != connector_status_connected)
 992                 return -ENODEV;
 993
 994         seq_printf(m, "%s:%d HDCP version: ", connector->name, connector->base.id);
 995
 996         hdcp_cap = dc_link_is_hdcp14(aconnector->dc_link, aconnector->dc_sink->sink_signal);
 997         hdcp2_cap = dc_link_is_hdcp22(aconnector->dc_link, aconnector->dc_sink->sink_signal);
 998
 999
1000         if (hdcp_cap)
1001                 seq_printf(m, "%s ", "HDCP1.4");
1002         if (hdcp2_cap)
1003                 seq_printf(m, "%s ", "HDCP2.2");
1004
1005         if (!hdcp_cap && !hdcp2_cap)
1006                 seq_printf(m, "%s ", "None");
1007
1008         seq_puts(m, "\n");
1009
1010         return 0;
1011 }
1012 #endif
1013
1014 /*
1015  * Returns whether the connected display is internal and not hotpluggable.
1016  * Example usage: cat /sys/kernel/debug/dri/0/DP-1/internal_display
1017  */
1018 static int internal_display_show(struct seq_file *m, void *data)
1019 {
1020         struct drm_connector *connector = m->private;
1021         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
1022         struct dc_link *link = aconnector->dc_link;
1023
1024         seq_printf(m, "Internal: %u\n", link->is_internal_display);
1025
1026         return 0;
1027 }
1028
1029 /* function description
1030  *
1031  * generic SDP message access for testing
1032  *
1033  * debugfs sdp_message is located at /syskernel/debug/dri/0/DP-x
1034  *
1035  * SDP header
1036  * Hb0 : Secondary-Data Packet ID
1037  * Hb1 : Secondary-Data Packet type
1038  * Hb2 : Secondary-Data-packet-specific header, Byte 0
1039  * Hb3 : Secondary-Data-packet-specific header, Byte 1
1040  *
1041  * for using custom sdp message: input 4 bytes SDP header and 32 bytes raw data
1042  */
1043 static ssize_t dp_sdp_message_debugfs_write(struct file *f, const char __user *buf,
1044                                  size_t size, loff_t *pos)
1045 {
1046         int r;
1047         uint8_t data[36];
1048         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
1049         struct dm_crtc_state *acrtc_state;
1050         uint32_t write_size = 36;
1051
1052         if (connector->base.status != connector_status_connected)
1053                 return -ENODEV;
1054
1055         if (size == 0)
1056                 return 0;
1057
1058         acrtc_state = to_dm_crtc_state(connector->base.state->crtc->state);
1059
1060         r = copy_from_user(data, buf, write_size);
1061
1062         write_size -= r;
1063
1064         dc_stream_send_dp_sdp(acrtc_state->stream, data, write_size);
1065
1066         return write_size;
1067 }
1068
1069 static ssize_t dp_dpcd_address_write(struct file *f, const char __user *buf,
1070                                  size_t size, loff_t *pos)
1071 {
1072         int r;
1073         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
1074
1075         if (size < sizeof(connector->debugfs_dpcd_address))
1076                 return -EINVAL;
1077
1078         r = copy_from_user(&connector->debugfs_dpcd_address,
1079                         buf, sizeof(connector->debugfs_dpcd_address));
1080
1081         return size - r;
1082 }
1083
1084 static ssize_t dp_dpcd_size_write(struct file *f, const char __user *buf,
1085                                  size_t size, loff_t *pos)
1086 {
1087         int r;
1088         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
1089
1090         if (size < sizeof(connector->debugfs_dpcd_size))
1091                 return -EINVAL;
1092
1093         r = copy_from_user(&connector->debugfs_dpcd_size,
1094                         buf, sizeof(connector->debugfs_dpcd_size));
1095
1096         if (connector->debugfs_dpcd_size > 256)
1097                 connector->debugfs_dpcd_size = 0;
1098
1099         return size - r;
1100 }
1101
1102 static ssize_t dp_dpcd_data_write(struct file *f, const char __user *buf,
1103                                  size_t size, loff_t *pos)
1104 {
1105         int r;
1106         char *data;
1107         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
1108         struct dc_link *link = connector->dc_link;
1109         uint32_t write_size = connector->debugfs_dpcd_size;
1110
1111         if (!write_size || size < write_size)
1112                 return -EINVAL;
1113
1114         data = kzalloc(write_size, GFP_KERNEL);
1115         if (!data)
1116                 return 0;
1117
1118         r = copy_from_user(data, buf, write_size);
1119
1120         dm_helpers_dp_write_dpcd(link->ctx, link,
1121                         connector->debugfs_dpcd_address, data, write_size - r);
1122         kfree(data);
1123         return write_size - r;
1124 }
1125
1126 static ssize_t dp_dpcd_data_read(struct file *f, char __user *buf,
1127                                  size_t size, loff_t *pos)
1128 {
1129         int r;
1130         char *data;
1131         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
1132         struct dc_link *link = connector->dc_link;
1133         uint32_t read_size = connector->debugfs_dpcd_size;
1134
1135         if (!read_size || size < read_size)
1136                 return 0;
1137
1138         data = kzalloc(read_size, GFP_KERNEL);
1139         if (!data)
1140                 return 0;
1141
1142         dm_helpers_dp_read_dpcd(link->ctx, link,
1143                         connector->debugfs_dpcd_address, data, read_size);
1144
1145         r = copy_to_user(buf, data, read_size);
1146
1147         kfree(data);
1148         return read_size - r;
1149 }
1150
1151 /* function: Read link's DSC & FEC capabilities
1152  *
1153  *
1154  * Access it with the following command (you need to specify
1155  * connector like DP-1):
1156  *
1157  *      cat /sys/kernel/debug/dri/0/DP-X/dp_dsc_fec_support
1158  *
1159  */
1160 static int dp_dsc_fec_support_show(struct seq_file *m, void *data)
1161 {
1162         struct drm_connector *connector = m->private;
1163         struct drm_modeset_acquire_ctx ctx;
1164         struct drm_device *dev = connector->dev;
1165         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
1166         int ret = 0;
1167         bool try_again = false;
1168         bool is_fec_supported = false;
1169         bool is_dsc_supported = false;
1170         struct dpcd_caps dpcd_caps;
1171
1172         drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE);
1173         do {
1174                 try_again = false;
1175                 ret = drm_modeset_lock(&dev->mode_config.connection_mutex, &ctx);
1176                 if (ret) {
1177                         if (ret == -EDEADLK) {
1178                                 ret = drm_modeset_backoff(&ctx);
1179                                 if (!ret) {
1180                                         try_again = true;
1181                                         continue;
1182                                 }
1183                         }
1184                         break;
1185                 }
1186                 if (connector->status != connector_status_connected) {
1187                         ret = -ENODEV;
1188                         break;
1189                 }
1190                 dpcd_caps = aconnector->dc_link->dpcd_caps;
1191                 if (aconnector->port) {
1192                         /* aconnector sets dsc_aux during get_modes call
1193                          * if MST connector has it means it can either
1194                          * enable DSC on the sink device or on MST branch
1195                          * its connected to.
1196                          */
1197                         if (aconnector->dsc_aux) {
1198                                 is_fec_supported = true;
1199                                 is_dsc_supported = true;
1200                         }
1201                 } else {
1202                         is_fec_supported = dpcd_caps.fec_cap.raw & 0x1;
1203                         is_dsc_supported = dpcd_caps.dsc_caps.dsc_basic_caps.raw[0] & 0x1;
1204                 }
1205         } while (try_again);
1206
1207         drm_modeset_drop_locks(&ctx);
1208         drm_modeset_acquire_fini(&ctx);
1209
1210         seq_printf(m, "FEC_Sink_Support: %s\n", yesno(is_fec_supported));
1211         seq_printf(m, "DSC_Sink_Support: %s\n", yesno(is_dsc_supported));
1212
1213         return ret;
1214 }
1215
1216 /* function: Trigger virtual HPD redetection on connector
1217  *
1218  * This function will perform link rediscovery, link disable
1219  * and enable, and dm connector state update.
1220  *
1221  * Retrigger HPD on an existing connector by echoing 1 into
1222  * its respectful "trigger_hotplug" debugfs entry:
1223  *
1224  *      echo 1 > /sys/kernel/debug/dri/0/DP-X/trigger_hotplug
1225  *
1226  * This function can perform HPD unplug:
1227  *
1228  *      echo 0 > /sys/kernel/debug/dri/0/DP-X/trigger_hotplug
1229  *
1230  */
1231 static ssize_t trigger_hotplug(struct file *f, const char __user *buf,
1232                                                         size_t size, loff_t *pos)
1233 {
1234         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1235         struct drm_connector *connector = &aconnector->base;
1236         struct dc_link *link = NULL;
1237         struct drm_device *dev = connector->dev;
1238         enum dc_connection_type new_connection_type = dc_connection_none;
1239         char *wr_buf = NULL;
1240         uint32_t wr_buf_size = 42;
1241         int max_param_num = 1;
1242         long param[1] = {0};
1243         uint8_t param_nums = 0;
1244
1245         if (!aconnector || !aconnector->dc_link)
1246                 return -EINVAL;
1247
1248         if (size == 0)
1249                 return -EINVAL;
1250
1251         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1252
1253         if (!wr_buf) {
1254                 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1255                 return -ENOSPC;
1256         }
1257
1258         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
1259                                                 (long *)param, buf,
1260                                                 max_param_num,
1261                                                 &param_nums)) {
1262                 kfree(wr_buf);
1263                 return -EINVAL;
1264         }
1265
1266         if (param_nums <= 0) {
1267                 DRM_DEBUG_DRIVER("user data not be read\n");
1268                 kfree(wr_buf);
1269                 return -EINVAL;
1270         }
1271
1272         if (param[0] == 1) {
1273                 mutex_lock(&aconnector->hpd_lock);
1274
1275                 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type) &&
1276                         new_connection_type != dc_connection_none)
1277                         goto unlock;
1278
1279                 if (!dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD))
1280                         goto unlock;
1281
1282                 amdgpu_dm_update_connector_after_detect(aconnector);
1283
1284                 drm_modeset_lock_all(dev);
1285                 dm_restore_drm_connector_state(dev, connector);
1286                 drm_modeset_unlock_all(dev);
1287
1288                 drm_kms_helper_connector_hotplug_event(connector);
1289         } else if (param[0] == 0) {
1290                 if (!aconnector->dc_link)
1291                         goto unlock;
1292
1293                 link = aconnector->dc_link;
1294
1295                 if (link->local_sink) {
1296                         dc_sink_release(link->local_sink);
1297                         link->local_sink = NULL;
1298                 }
1299
1300                 link->dpcd_sink_count = 0;
1301                 link->type = dc_connection_none;
1302                 link->dongle_max_pix_clk = 0;
1303
1304                 amdgpu_dm_update_connector_after_detect(aconnector);
1305
1306                 drm_modeset_lock_all(dev);
1307                 dm_restore_drm_connector_state(dev, connector);
1308                 drm_modeset_unlock_all(dev);
1309
1310                 drm_kms_helper_connector_hotplug_event(connector);
1311         }
1312
1313 unlock:
1314         mutex_unlock(&aconnector->hpd_lock);
1315
1316         kfree(wr_buf);
1317         return size;
1318 }
1319
1320 /* function: read DSC status on the connector
1321  *
1322  * The read function: dp_dsc_clock_en_read
1323  * returns current status of DSC clock on the connector.
1324  * The return is a boolean flag: 1 or 0.
1325  *
1326  * Access it with the following command (you need to specify
1327  * connector like DP-1):
1328  *
1329  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_clock_en
1330  *
1331  * Expected output:
1332  * 1 - means that DSC is currently enabled
1333  * 0 - means that DSC is disabled
1334  */
1335 static ssize_t dp_dsc_clock_en_read(struct file *f, char __user *buf,
1336                                     size_t size, loff_t *pos)
1337 {
1338         char *rd_buf = NULL;
1339         char *rd_buf_ptr = NULL;
1340         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1341         struct display_stream_compressor *dsc;
1342         struct dcn_dsc_state dsc_state = {0};
1343         const uint32_t rd_buf_size = 10;
1344         struct pipe_ctx *pipe_ctx;
1345         ssize_t result = 0;
1346         int i, r, str_len = 30;
1347
1348         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
1349
1350         if (!rd_buf)
1351                 return -ENOMEM;
1352
1353         rd_buf_ptr = rd_buf;
1354
1355         for (i = 0; i < MAX_PIPES; i++) {
1356                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1357                         if (pipe_ctx && pipe_ctx->stream &&
1358                             pipe_ctx->stream->link == aconnector->dc_link)
1359                                 break;
1360         }
1361
1362         if (!pipe_ctx)
1363                 return -ENXIO;
1364
1365         dsc = pipe_ctx->stream_res.dsc;
1366         if (dsc)
1367                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
1368
1369         snprintf(rd_buf_ptr, str_len,
1370                 "%d\n",
1371                 dsc_state.dsc_clock_en);
1372         rd_buf_ptr += str_len;
1373
1374         while (size) {
1375                 if (*pos >= rd_buf_size)
1376                         break;
1377
1378                 r = put_user(*(rd_buf + result), buf);
1379                 if (r)
1380                         return r; /* r = -EFAULT */
1381
1382                 buf += 1;
1383                 size -= 1;
1384                 *pos += 1;
1385                 result += 1;
1386         }
1387
1388         kfree(rd_buf);
1389         return result;
1390 }
1391
1392 /* function: write force DSC on the connector
1393  *
1394  * The write function: dp_dsc_clock_en_write
1395  * enables to force DSC on the connector.
1396  * User can write to either force enable or force disable DSC
1397  * on the next modeset or set it to driver default
1398  *
1399  * Accepted inputs:
1400  * 0 - default DSC enablement policy
1401  * 1 - force enable DSC on the connector
1402  * 2 - force disable DSC on the connector (might cause fail in atomic_check)
1403  *
1404  * Writing DSC settings is done with the following command:
1405  * - To force enable DSC (you need to specify
1406  * connector like DP-1):
1407  *
1408  *      echo 0x1 > /sys/kernel/debug/dri/0/DP-X/dsc_clock_en
1409  *
1410  * - To return to default state set the flag to zero and
1411  * let driver deal with DSC automatically
1412  * (you need to specify connector like DP-1):
1413  *
1414  *      echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_clock_en
1415  *
1416  */
1417 static ssize_t dp_dsc_clock_en_write(struct file *f, const char __user *buf,
1418                                      size_t size, loff_t *pos)
1419 {
1420         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1421         struct drm_connector *connector = &aconnector->base;
1422         struct drm_device *dev = connector->dev;
1423         struct drm_crtc *crtc = NULL;
1424         struct dm_crtc_state *dm_crtc_state = NULL;
1425         struct pipe_ctx *pipe_ctx;
1426         int i;
1427         char *wr_buf = NULL;
1428         uint32_t wr_buf_size = 42;
1429         int max_param_num = 1;
1430         long param[1] = {0};
1431         uint8_t param_nums = 0;
1432
1433         if (size == 0)
1434                 return -EINVAL;
1435
1436         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1437
1438         if (!wr_buf) {
1439                 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1440                 return -ENOSPC;
1441         }
1442
1443         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
1444                                             (long *)param, buf,
1445                                             max_param_num,
1446                                             &param_nums)) {
1447                 kfree(wr_buf);
1448                 return -EINVAL;
1449         }
1450
1451         if (param_nums <= 0) {
1452                 DRM_DEBUG_DRIVER("user data not be read\n");
1453                 kfree(wr_buf);
1454                 return -EINVAL;
1455         }
1456
1457         for (i = 0; i < MAX_PIPES; i++) {
1458                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1459                         if (pipe_ctx && pipe_ctx->stream &&
1460                             pipe_ctx->stream->link == aconnector->dc_link)
1461                                 break;
1462         }
1463
1464         if (!pipe_ctx || !pipe_ctx->stream)
1465                 goto done;
1466
1467         // Get CRTC state
1468         mutex_lock(&dev->mode_config.mutex);
1469         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
1470
1471         if (connector->state == NULL)
1472                 goto unlock;
1473
1474         crtc = connector->state->crtc;
1475         if (crtc == NULL)
1476                 goto unlock;
1477
1478         drm_modeset_lock(&crtc->mutex, NULL);
1479         if (crtc->state == NULL)
1480                 goto unlock;
1481
1482         dm_crtc_state = to_dm_crtc_state(crtc->state);
1483         if (dm_crtc_state->stream == NULL)
1484                 goto unlock;
1485
1486         if (param[0] == 1)
1487                 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_ENABLE;
1488         else if (param[0] == 2)
1489                 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_DISABLE;
1490         else
1491                 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_DEFAULT;
1492
1493         dm_crtc_state->dsc_force_changed = true;
1494
1495 unlock:
1496         if (crtc)
1497                 drm_modeset_unlock(&crtc->mutex);
1498         drm_modeset_unlock(&dev->mode_config.connection_mutex);
1499         mutex_unlock(&dev->mode_config.mutex);
1500
1501 done:
1502         kfree(wr_buf);
1503         return size;
1504 }
1505
1506 /* function: read DSC slice width parameter on the connector
1507  *
1508  * The read function: dp_dsc_slice_width_read
1509  * returns dsc slice width used in the current configuration
1510  * The return is an integer: 0 or other positive number
1511  *
1512  * Access the status with the following command:
1513  *
1514  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_width
1515  *
1516  * 0 - means that DSC is disabled
1517  *
1518  * Any other number more than zero represents the
1519  * slice width currently used by DSC in pixels
1520  *
1521  */
1522 static ssize_t dp_dsc_slice_width_read(struct file *f, char __user *buf,
1523                                     size_t size, loff_t *pos)
1524 {
1525         char *rd_buf = NULL;
1526         char *rd_buf_ptr = NULL;
1527         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1528         struct display_stream_compressor *dsc;
1529         struct dcn_dsc_state dsc_state = {0};
1530         const uint32_t rd_buf_size = 100;
1531         struct pipe_ctx *pipe_ctx;
1532         ssize_t result = 0;
1533         int i, r, str_len = 30;
1534
1535         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
1536
1537         if (!rd_buf)
1538                 return -ENOMEM;
1539
1540         rd_buf_ptr = rd_buf;
1541
1542         for (i = 0; i < MAX_PIPES; i++) {
1543                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1544                         if (pipe_ctx && pipe_ctx->stream &&
1545                             pipe_ctx->stream->link == aconnector->dc_link)
1546                                 break;
1547         }
1548
1549         if (!pipe_ctx)
1550                 return -ENXIO;
1551
1552         dsc = pipe_ctx->stream_res.dsc;
1553         if (dsc)
1554                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
1555
1556         snprintf(rd_buf_ptr, str_len,
1557                 "%d\n",
1558                 dsc_state.dsc_slice_width);
1559         rd_buf_ptr += str_len;
1560
1561         while (size) {
1562                 if (*pos >= rd_buf_size)
1563                         break;
1564
1565                 r = put_user(*(rd_buf + result), buf);
1566                 if (r)
1567                         return r; /* r = -EFAULT */
1568
1569                 buf += 1;
1570                 size -= 1;
1571                 *pos += 1;
1572                 result += 1;
1573         }
1574
1575         kfree(rd_buf);
1576         return result;
1577 }
1578
1579 /* function: write DSC slice width parameter
1580  *
1581  * The write function: dp_dsc_slice_width_write
1582  * overwrites automatically generated DSC configuration
1583  * of slice width.
1584  *
1585  * The user has to write the slice width divisible by the
1586  * picture width.
1587  *
1588  * Also the user has to write width in hexidecimal
1589  * rather than in decimal.
1590  *
1591  * Writing DSC settings is done with the following command:
1592  * - To force overwrite slice width: (example sets to 1920 pixels)
1593  *
1594  *      echo 0x780 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_width
1595  *
1596  *  - To stop overwriting and let driver find the optimal size,
1597  * set the width to zero:
1598  *
1599  *      echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_width
1600  *
1601  */
1602 static ssize_t dp_dsc_slice_width_write(struct file *f, const char __user *buf,
1603                                      size_t size, loff_t *pos)
1604 {
1605         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1606         struct pipe_ctx *pipe_ctx;
1607         struct drm_connector *connector = &aconnector->base;
1608         struct drm_device *dev = connector->dev;
1609         struct drm_crtc *crtc = NULL;
1610         struct dm_crtc_state *dm_crtc_state = NULL;
1611         int i;
1612         char *wr_buf = NULL;
1613         uint32_t wr_buf_size = 42;
1614         int max_param_num = 1;
1615         long param[1] = {0};
1616         uint8_t param_nums = 0;
1617
1618         if (size == 0)
1619                 return -EINVAL;
1620
1621         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1622
1623         if (!wr_buf) {
1624                 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1625                 return -ENOSPC;
1626         }
1627
1628         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
1629                                             (long *)param, buf,
1630                                             max_param_num,
1631                                             &param_nums)) {
1632                 kfree(wr_buf);
1633                 return -EINVAL;
1634         }
1635
1636         if (param_nums <= 0) {
1637                 DRM_DEBUG_DRIVER("user data not be read\n");
1638                 kfree(wr_buf);
1639                 return -EINVAL;
1640         }
1641
1642         for (i = 0; i < MAX_PIPES; i++) {
1643                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1644                         if (pipe_ctx && pipe_ctx->stream &&
1645                             pipe_ctx->stream->link == aconnector->dc_link)
1646                                 break;
1647         }
1648
1649         if (!pipe_ctx || !pipe_ctx->stream)
1650                 goto done;
1651
1652         // Safely get CRTC state
1653         mutex_lock(&dev->mode_config.mutex);
1654         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
1655
1656         if (connector->state == NULL)
1657                 goto unlock;
1658
1659         crtc = connector->state->crtc;
1660         if (crtc == NULL)
1661                 goto unlock;
1662
1663         drm_modeset_lock(&crtc->mutex, NULL);
1664         if (crtc->state == NULL)
1665                 goto unlock;
1666
1667         dm_crtc_state = to_dm_crtc_state(crtc->state);
1668         if (dm_crtc_state->stream == NULL)
1669                 goto unlock;
1670
1671         if (param[0] > 0)
1672                 aconnector->dsc_settings.dsc_num_slices_h = DIV_ROUND_UP(
1673                                         pipe_ctx->stream->timing.h_addressable,
1674                                         param[0]);
1675         else
1676                 aconnector->dsc_settings.dsc_num_slices_h = 0;
1677
1678         dm_crtc_state->dsc_force_changed = true;
1679
1680 unlock:
1681         if (crtc)
1682                 drm_modeset_unlock(&crtc->mutex);
1683         drm_modeset_unlock(&dev->mode_config.connection_mutex);
1684         mutex_unlock(&dev->mode_config.mutex);
1685
1686 done:
1687         kfree(wr_buf);
1688         return size;
1689 }
1690
1691 /* function: read DSC slice height parameter on the connector
1692  *
1693  * The read function: dp_dsc_slice_height_read
1694  * returns dsc slice height used in the current configuration
1695  * The return is an integer: 0 or other positive number
1696  *
1697  * Access the status with the following command:
1698  *
1699  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_height
1700  *
1701  * 0 - means that DSC is disabled
1702  *
1703  * Any other number more than zero represents the
1704  * slice height currently used by DSC in pixels
1705  *
1706  */
1707 static ssize_t dp_dsc_slice_height_read(struct file *f, char __user *buf,
1708                                     size_t size, loff_t *pos)
1709 {
1710         char *rd_buf = NULL;
1711         char *rd_buf_ptr = NULL;
1712         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1713         struct display_stream_compressor *dsc;
1714         struct dcn_dsc_state dsc_state = {0};
1715         const uint32_t rd_buf_size = 100;
1716         struct pipe_ctx *pipe_ctx;
1717         ssize_t result = 0;
1718         int i, r, str_len = 30;
1719
1720         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
1721
1722         if (!rd_buf)
1723                 return -ENOMEM;
1724
1725         rd_buf_ptr = rd_buf;
1726
1727         for (i = 0; i < MAX_PIPES; i++) {
1728                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1729                         if (pipe_ctx && pipe_ctx->stream &&
1730                             pipe_ctx->stream->link == aconnector->dc_link)
1731                                 break;
1732         }
1733
1734         if (!pipe_ctx)
1735                 return -ENXIO;
1736
1737         dsc = pipe_ctx->stream_res.dsc;
1738         if (dsc)
1739                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
1740
1741         snprintf(rd_buf_ptr, str_len,
1742                 "%d\n",
1743                 dsc_state.dsc_slice_height);
1744         rd_buf_ptr += str_len;
1745
1746         while (size) {
1747                 if (*pos >= rd_buf_size)
1748                         break;
1749
1750                 r = put_user(*(rd_buf + result), buf);
1751                 if (r)
1752                         return r; /* r = -EFAULT */
1753
1754                 buf += 1;
1755                 size -= 1;
1756                 *pos += 1;
1757                 result += 1;
1758         }
1759
1760         kfree(rd_buf);
1761         return result;
1762 }
1763
1764 /* function: write DSC slice height parameter
1765  *
1766  * The write function: dp_dsc_slice_height_write
1767  * overwrites automatically generated DSC configuration
1768  * of slice height.
1769  *
1770  * The user has to write the slice height divisible by the
1771  * picture height.
1772  *
1773  * Also the user has to write height in hexidecimal
1774  * rather than in decimal.
1775  *
1776  * Writing DSC settings is done with the following command:
1777  * - To force overwrite slice height (example sets to 128 pixels):
1778  *
1779  *      echo 0x80 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_height
1780  *
1781  *  - To stop overwriting and let driver find the optimal size,
1782  * set the height to zero:
1783  *
1784  *      echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_height
1785  *
1786  */
1787 static ssize_t dp_dsc_slice_height_write(struct file *f, const char __user *buf,
1788                                      size_t size, loff_t *pos)
1789 {
1790         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1791         struct drm_connector *connector = &aconnector->base;
1792         struct drm_device *dev = connector->dev;
1793         struct drm_crtc *crtc = NULL;
1794         struct dm_crtc_state *dm_crtc_state = NULL;
1795         struct pipe_ctx *pipe_ctx;
1796         int i;
1797         char *wr_buf = NULL;
1798         uint32_t wr_buf_size = 42;
1799         int max_param_num = 1;
1800         uint8_t param_nums = 0;
1801         long param[1] = {0};
1802
1803         if (size == 0)
1804                 return -EINVAL;
1805
1806         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1807
1808         if (!wr_buf) {
1809                 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1810                 return -ENOSPC;
1811         }
1812
1813         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
1814                                             (long *)param, buf,
1815                                             max_param_num,
1816                                             &param_nums)) {
1817                 kfree(wr_buf);
1818                 return -EINVAL;
1819         }
1820
1821         if (param_nums <= 0) {
1822                 DRM_DEBUG_DRIVER("user data not be read\n");
1823                 kfree(wr_buf);
1824                 return -EINVAL;
1825         }
1826
1827         for (i = 0; i < MAX_PIPES; i++) {
1828                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1829                         if (pipe_ctx && pipe_ctx->stream &&
1830                             pipe_ctx->stream->link == aconnector->dc_link)
1831                                 break;
1832         }
1833
1834         if (!pipe_ctx || !pipe_ctx->stream)
1835                 goto done;
1836
1837         // Get CRTC state
1838         mutex_lock(&dev->mode_config.mutex);
1839         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
1840
1841         if (connector->state == NULL)
1842                 goto unlock;
1843
1844         crtc = connector->state->crtc;
1845         if (crtc == NULL)
1846                 goto unlock;
1847
1848         drm_modeset_lock(&crtc->mutex, NULL);
1849         if (crtc->state == NULL)
1850                 goto unlock;
1851
1852         dm_crtc_state = to_dm_crtc_state(crtc->state);
1853         if (dm_crtc_state->stream == NULL)
1854                 goto unlock;
1855
1856         if (param[0] > 0)
1857                 aconnector->dsc_settings.dsc_num_slices_v = DIV_ROUND_UP(
1858                                         pipe_ctx->stream->timing.v_addressable,
1859                                         param[0]);
1860         else
1861                 aconnector->dsc_settings.dsc_num_slices_v = 0;
1862
1863         dm_crtc_state->dsc_force_changed = true;
1864
1865 unlock:
1866         if (crtc)
1867                 drm_modeset_unlock(&crtc->mutex);
1868         drm_modeset_unlock(&dev->mode_config.connection_mutex);
1869         mutex_unlock(&dev->mode_config.mutex);
1870
1871 done:
1872         kfree(wr_buf);
1873         return size;
1874 }
1875
1876 /* function: read DSC target rate on the connector in bits per pixel
1877  *
1878  * The read function: dp_dsc_bits_per_pixel_read
1879  * returns target rate of compression in bits per pixel
1880  * The return is an integer: 0 or other positive integer
1881  *
1882  * Access it with the following command:
1883  *
1884  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel
1885  *
1886  *  0 - means that DSC is disabled
1887  */
1888 static ssize_t dp_dsc_bits_per_pixel_read(struct file *f, char __user *buf,
1889                                     size_t size, loff_t *pos)
1890 {
1891         char *rd_buf = NULL;
1892         char *rd_buf_ptr = NULL;
1893         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1894         struct display_stream_compressor *dsc;
1895         struct dcn_dsc_state dsc_state = {0};
1896         const uint32_t rd_buf_size = 100;
1897         struct pipe_ctx *pipe_ctx;
1898         ssize_t result = 0;
1899         int i, r, str_len = 30;
1900
1901         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
1902
1903         if (!rd_buf)
1904                 return -ENOMEM;
1905
1906         rd_buf_ptr = rd_buf;
1907
1908         for (i = 0; i < MAX_PIPES; i++) {
1909                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1910                         if (pipe_ctx && pipe_ctx->stream &&
1911                             pipe_ctx->stream->link == aconnector->dc_link)
1912                                 break;
1913         }
1914
1915         if (!pipe_ctx)
1916                 return -ENXIO;
1917
1918         dsc = pipe_ctx->stream_res.dsc;
1919         if (dsc)
1920                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
1921
1922         snprintf(rd_buf_ptr, str_len,
1923                 "%d\n",
1924                 dsc_state.dsc_bits_per_pixel);
1925         rd_buf_ptr += str_len;
1926
1927         while (size) {
1928                 if (*pos >= rd_buf_size)
1929                         break;
1930
1931                 r = put_user(*(rd_buf + result), buf);
1932                 if (r)
1933                         return r; /* r = -EFAULT */
1934
1935                 buf += 1;
1936                 size -= 1;
1937                 *pos += 1;
1938                 result += 1;
1939         }
1940
1941         kfree(rd_buf);
1942         return result;
1943 }
1944
1945 /* function: write DSC target rate in bits per pixel
1946  *
1947  * The write function: dp_dsc_bits_per_pixel_write
1948  * overwrites automatically generated DSC configuration
1949  * of DSC target bit rate.
1950  *
1951  * Also the user has to write bpp in hexidecimal
1952  * rather than in decimal.
1953  *
1954  * Writing DSC settings is done with the following command:
1955  * - To force overwrite rate (example sets to 256 bpp x 1/16):
1956  *
1957  *      echo 0x100 > /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel
1958  *
1959  *  - To stop overwriting and let driver find the optimal rate,
1960  * set the rate to zero:
1961  *
1962  *      echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel
1963  *
1964  */
1965 static ssize_t dp_dsc_bits_per_pixel_write(struct file *f, const char __user *buf,
1966                                      size_t size, loff_t *pos)
1967 {
1968         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1969         struct drm_connector *connector = &aconnector->base;
1970         struct drm_device *dev = connector->dev;
1971         struct drm_crtc *crtc = NULL;
1972         struct dm_crtc_state *dm_crtc_state = NULL;
1973         struct pipe_ctx *pipe_ctx;
1974         int i;
1975         char *wr_buf = NULL;
1976         uint32_t wr_buf_size = 42;
1977         int max_param_num = 1;
1978         uint8_t param_nums = 0;
1979         long param[1] = {0};
1980
1981         if (size == 0)
1982                 return -EINVAL;
1983
1984         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1985
1986         if (!wr_buf) {
1987                 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1988                 return -ENOSPC;
1989         }
1990
1991         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
1992                                             (long *)param, buf,
1993                                             max_param_num,
1994                                             &param_nums)) {
1995                 kfree(wr_buf);
1996                 return -EINVAL;
1997         }
1998
1999         if (param_nums <= 0) {
2000                 DRM_DEBUG_DRIVER("user data not be read\n");
2001                 kfree(wr_buf);
2002                 return -EINVAL;
2003         }
2004
2005         for (i = 0; i < MAX_PIPES; i++) {
2006                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2007                         if (pipe_ctx && pipe_ctx->stream &&
2008                             pipe_ctx->stream->link == aconnector->dc_link)
2009                                 break;
2010         }
2011
2012         if (!pipe_ctx || !pipe_ctx->stream)
2013                 goto done;
2014
2015         // Get CRTC state
2016         mutex_lock(&dev->mode_config.mutex);
2017         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
2018
2019         if (connector->state == NULL)
2020                 goto unlock;
2021
2022         crtc = connector->state->crtc;
2023         if (crtc == NULL)
2024                 goto unlock;
2025
2026         drm_modeset_lock(&crtc->mutex, NULL);
2027         if (crtc->state == NULL)
2028                 goto unlock;
2029
2030         dm_crtc_state = to_dm_crtc_state(crtc->state);
2031         if (dm_crtc_state->stream == NULL)
2032                 goto unlock;
2033
2034         aconnector->dsc_settings.dsc_bits_per_pixel = param[0];
2035
2036         dm_crtc_state->dsc_force_changed = true;
2037
2038 unlock:
2039         if (crtc)
2040                 drm_modeset_unlock(&crtc->mutex);
2041         drm_modeset_unlock(&dev->mode_config.connection_mutex);
2042         mutex_unlock(&dev->mode_config.mutex);
2043
2044 done:
2045         kfree(wr_buf);
2046         return size;
2047 }
2048
2049 /* function: read DSC picture width parameter on the connector
2050  *
2051  * The read function: dp_dsc_pic_width_read
2052  * returns dsc picture width used in the current configuration
2053  * It is the same as h_addressable of the current
2054  * display's timing
2055  * The return is an integer: 0 or other positive integer
2056  * If 0 then DSC is disabled.
2057  *
2058  * Access it with the following command:
2059  *
2060  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_pic_width
2061  *
2062  * 0 - means that DSC is disabled
2063  */
2064 static ssize_t dp_dsc_pic_width_read(struct file *f, char __user *buf,
2065                                     size_t size, loff_t *pos)
2066 {
2067         char *rd_buf = NULL;
2068         char *rd_buf_ptr = NULL;
2069         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2070         struct display_stream_compressor *dsc;
2071         struct dcn_dsc_state dsc_state = {0};
2072         const uint32_t rd_buf_size = 100;
2073         struct pipe_ctx *pipe_ctx;
2074         ssize_t result = 0;
2075         int i, r, str_len = 30;
2076
2077         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2078
2079         if (!rd_buf)
2080                 return -ENOMEM;
2081
2082         rd_buf_ptr = rd_buf;
2083
2084         for (i = 0; i < MAX_PIPES; i++) {
2085                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2086                         if (pipe_ctx && pipe_ctx->stream &&
2087                             pipe_ctx->stream->link == aconnector->dc_link)
2088                                 break;
2089         }
2090
2091         if (!pipe_ctx)
2092                 return -ENXIO;
2093
2094         dsc = pipe_ctx->stream_res.dsc;
2095         if (dsc)
2096                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
2097
2098         snprintf(rd_buf_ptr, str_len,
2099                 "%d\n",
2100                 dsc_state.dsc_pic_width);
2101         rd_buf_ptr += str_len;
2102
2103         while (size) {
2104                 if (*pos >= rd_buf_size)
2105                         break;
2106
2107                 r = put_user(*(rd_buf + result), buf);
2108                 if (r)
2109                         return r; /* r = -EFAULT */
2110
2111                 buf += 1;
2112                 size -= 1;
2113                 *pos += 1;
2114                 result += 1;
2115         }
2116
2117         kfree(rd_buf);
2118         return result;
2119 }
2120
2121 static ssize_t dp_dsc_pic_height_read(struct file *f, char __user *buf,
2122                                     size_t size, loff_t *pos)
2123 {
2124         char *rd_buf = NULL;
2125         char *rd_buf_ptr = NULL;
2126         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2127         struct display_stream_compressor *dsc;
2128         struct dcn_dsc_state dsc_state = {0};
2129         const uint32_t rd_buf_size = 100;
2130         struct pipe_ctx *pipe_ctx;
2131         ssize_t result = 0;
2132         int i, r, str_len = 30;
2133
2134         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2135
2136         if (!rd_buf)
2137                 return -ENOMEM;
2138
2139         rd_buf_ptr = rd_buf;
2140
2141         for (i = 0; i < MAX_PIPES; i++) {
2142                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2143                         if (pipe_ctx && pipe_ctx->stream &&
2144                             pipe_ctx->stream->link == aconnector->dc_link)
2145                                 break;
2146         }
2147
2148         if (!pipe_ctx)
2149                 return -ENXIO;
2150
2151         dsc = pipe_ctx->stream_res.dsc;
2152         if (dsc)
2153                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
2154
2155         snprintf(rd_buf_ptr, str_len,
2156                 "%d\n",
2157                 dsc_state.dsc_pic_height);
2158         rd_buf_ptr += str_len;
2159
2160         while (size) {
2161                 if (*pos >= rd_buf_size)
2162                         break;
2163
2164                 r = put_user(*(rd_buf + result), buf);
2165                 if (r)
2166                         return r; /* r = -EFAULT */
2167
2168                 buf += 1;
2169                 size -= 1;
2170                 *pos += 1;
2171                 result += 1;
2172         }
2173
2174         kfree(rd_buf);
2175         return result;
2176 }
2177
2178 /* function: read DSC chunk size parameter on the connector
2179  *
2180  * The read function: dp_dsc_chunk_size_read
2181  * returns dsc chunk size set in the current configuration
2182  * The value is calculated automatically by DSC code
2183  * and depends on slice parameters and bpp target rate
2184  * The return is an integer: 0 or other positive integer
2185  * If 0 then DSC is disabled.
2186  *
2187  * Access it with the following command:
2188  *
2189  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_chunk_size
2190  *
2191  * 0 - means that DSC is disabled
2192  */
2193 static ssize_t dp_dsc_chunk_size_read(struct file *f, char __user *buf,
2194                                     size_t size, loff_t *pos)
2195 {
2196         char *rd_buf = NULL;
2197         char *rd_buf_ptr = NULL;
2198         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2199         struct display_stream_compressor *dsc;
2200         struct dcn_dsc_state dsc_state = {0};
2201         const uint32_t rd_buf_size = 100;
2202         struct pipe_ctx *pipe_ctx;
2203         ssize_t result = 0;
2204         int i, r, str_len = 30;
2205
2206         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2207
2208         if (!rd_buf)
2209                 return -ENOMEM;
2210
2211         rd_buf_ptr = rd_buf;
2212
2213         for (i = 0; i < MAX_PIPES; i++) {
2214                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2215                         if (pipe_ctx && pipe_ctx->stream &&
2216                             pipe_ctx->stream->link == aconnector->dc_link)
2217                                 break;
2218         }
2219
2220         if (!pipe_ctx)
2221                 return -ENXIO;
2222
2223         dsc = pipe_ctx->stream_res.dsc;
2224         if (dsc)
2225                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
2226
2227         snprintf(rd_buf_ptr, str_len,
2228                 "%d\n",
2229                 dsc_state.dsc_chunk_size);
2230         rd_buf_ptr += str_len;
2231
2232         while (size) {
2233                 if (*pos >= rd_buf_size)
2234                         break;
2235
2236                 r = put_user(*(rd_buf + result), buf);
2237                 if (r)
2238                         return r; /* r = -EFAULT */
2239
2240                 buf += 1;
2241                 size -= 1;
2242                 *pos += 1;
2243                 result += 1;
2244         }
2245
2246         kfree(rd_buf);
2247         return result;
2248 }
2249
2250 /* function: read DSC slice bpg offset on the connector
2251  *
2252  * The read function: dp_dsc_slice_bpg_offset_read
2253  * returns dsc bpg slice offset set in the current configuration
2254  * The value is calculated automatically by DSC code
2255  * and depends on slice parameters and bpp target rate
2256  * The return is an integer: 0 or other positive integer
2257  * If 0 then DSC is disabled.
2258  *
2259  * Access it with the following command:
2260  *
2261  *      cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_bpg_offset
2262  *
2263  * 0 - means that DSC is disabled
2264  */
2265 static ssize_t dp_dsc_slice_bpg_offset_read(struct file *f, char __user *buf,
2266                                     size_t size, loff_t *pos)
2267 {
2268         char *rd_buf = NULL;
2269         char *rd_buf_ptr = NULL;
2270         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2271         struct display_stream_compressor *dsc;
2272         struct dcn_dsc_state dsc_state = {0};
2273         const uint32_t rd_buf_size = 100;
2274         struct pipe_ctx *pipe_ctx;
2275         ssize_t result = 0;
2276         int i, r, str_len = 30;
2277
2278         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2279
2280         if (!rd_buf)
2281                 return -ENOMEM;
2282
2283         rd_buf_ptr = rd_buf;
2284
2285         for (i = 0; i < MAX_PIPES; i++) {
2286                 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2287                         if (pipe_ctx && pipe_ctx->stream &&
2288                             pipe_ctx->stream->link == aconnector->dc_link)
2289                                 break;
2290         }
2291
2292         if (!pipe_ctx)
2293                 return -ENXIO;
2294
2295         dsc = pipe_ctx->stream_res.dsc;
2296         if (dsc)
2297                 dsc->funcs->dsc_read_state(dsc, &dsc_state);
2298
2299         snprintf(rd_buf_ptr, str_len,
2300                 "%d\n",
2301                 dsc_state.dsc_slice_bpg_offset);
2302         rd_buf_ptr += str_len;
2303
2304         while (size) {
2305                 if (*pos >= rd_buf_size)
2306                         break;
2307
2308                 r = put_user(*(rd_buf + result), buf);
2309                 if (r)
2310                         return r; /* r = -EFAULT */
2311
2312                 buf += 1;
2313                 size -= 1;
2314                 *pos += 1;
2315                 result += 1;
2316         }
2317
2318         kfree(rd_buf);
2319         return result;
2320 }
2321
2322
2323 /*
2324  * function description: Read max_requested_bpc property from the connector
2325  *
2326  * Access it with the following command:
2327  *
2328  *      cat /sys/kernel/debug/dri/0/DP-X/max_bpc
2329  *
2330  */
2331 static ssize_t dp_max_bpc_read(struct file *f, char __user *buf,
2332                 size_t size, loff_t *pos)
2333 {
2334         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2335         struct drm_connector *connector = &aconnector->base;
2336         struct drm_device *dev = connector->dev;
2337         struct dm_connector_state *state;
2338         ssize_t result = 0;
2339         char *rd_buf = NULL;
2340         char *rd_buf_ptr = NULL;
2341         const uint32_t rd_buf_size = 10;
2342         int r;
2343
2344         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2345
2346         if (!rd_buf)
2347                 return -ENOMEM;
2348
2349         mutex_lock(&dev->mode_config.mutex);
2350         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
2351
2352         if (connector->state == NULL)
2353                 goto unlock;
2354
2355         state = to_dm_connector_state(connector->state);
2356
2357         rd_buf_ptr = rd_buf;
2358         snprintf(rd_buf_ptr, rd_buf_size,
2359                 "%u\n",
2360                 state->base.max_requested_bpc);
2361
2362         while (size) {
2363                 if (*pos >= rd_buf_size)
2364                         break;
2365
2366                 r = put_user(*(rd_buf + result), buf);
2367                 if (r) {
2368                         result = r; /* r = -EFAULT */
2369                         goto unlock;
2370                 }
2371                 buf += 1;
2372                 size -= 1;
2373                 *pos += 1;
2374                 result += 1;
2375         }
2376 unlock:
2377         drm_modeset_unlock(&dev->mode_config.connection_mutex);
2378         mutex_unlock(&dev->mode_config.mutex);
2379         kfree(rd_buf);
2380         return result;
2381 }
2382
2383
2384 /*
2385  * function description: Set max_requested_bpc property on the connector
2386  *
2387  * This function will not force the input BPC on connector, it will only
2388  * change the max value. This is equivalent to setting max_bpc through
2389  * xrandr.
2390  *
2391  * The BPC value written must be >= 6 and <= 16. Values outside of this
2392  * range will result in errors.
2393  *
2394  * BPC values:
2395  *      0x6 - 6 BPC
2396  *      0x8 - 8 BPC
2397  *      0xa - 10 BPC
2398  *      0xc - 12 BPC
2399  *      0x10 - 16 BPC
2400  *
2401  * Write the max_bpc in the following way:
2402  *
2403  * echo 0x6 > /sys/kernel/debug/dri/0/DP-X/max_bpc
2404  *
2405  */
2406 static ssize_t dp_max_bpc_write(struct file *f, const char __user *buf,
2407                                      size_t size, loff_t *pos)
2408 {
2409         struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2410         struct drm_connector *connector = &aconnector->base;
2411         struct dm_connector_state *state;
2412         struct drm_device *dev = connector->dev;
2413         char *wr_buf = NULL;
2414         uint32_t wr_buf_size = 42;
2415         int max_param_num = 1;
2416         long param[1] = {0};
2417         uint8_t param_nums = 0;
2418
2419         if (size == 0)
2420                 return -EINVAL;
2421
2422         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
2423
2424         if (!wr_buf) {
2425                 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
2426                 return -ENOSPC;
2427         }
2428
2429         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
2430                                            (long *)param, buf,
2431                                            max_param_num,
2432                                            &param_nums)) {
2433                 kfree(wr_buf);
2434                 return -EINVAL;
2435         }
2436
2437         if (param_nums <= 0) {
2438                 DRM_DEBUG_DRIVER("user data not be read\n");
2439                 kfree(wr_buf);
2440                 return -EINVAL;
2441         }
2442
2443         if (param[0] < 6 || param[0] > 16) {
2444                 DRM_DEBUG_DRIVER("bad max_bpc value\n");
2445                 kfree(wr_buf);
2446                 return -EINVAL;
2447         }
2448
2449         mutex_lock(&dev->mode_config.mutex);
2450         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
2451
2452         if (connector->state == NULL)
2453                 goto unlock;
2454
2455         state = to_dm_connector_state(connector->state);
2456         state->base.max_requested_bpc = param[0];
2457 unlock:
2458         drm_modeset_unlock(&dev->mode_config.connection_mutex);
2459         mutex_unlock(&dev->mode_config.mutex);
2460
2461         kfree(wr_buf);
2462         return size;
2463 }
2464
2465 /*
2466  * Backlight at this moment.  Read only.
2467  * As written to display, taking ABM and backlight lut into account.
2468  * Ranges from 0x0 to 0x10000 (= 100% PWM)
2469  *
2470  * Example usage: cat /sys/kernel/debug/dri/0/eDP-1/current_backlight
2471  */
2472 static int current_backlight_show(struct seq_file *m, void *unused)
2473 {
2474         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private);
2475         struct dc_link *link = aconnector->dc_link;
2476         unsigned int backlight;
2477
2478         backlight = dc_link_get_backlight_level(link);
2479         seq_printf(m, "0x%x\n", backlight);
2480
2481         return 0;
2482 }
2483
2484 /*
2485  * Backlight value that is being approached.  Read only.
2486  * As written to display, taking ABM and backlight lut into account.
2487  * Ranges from 0x0 to 0x10000 (= 100% PWM)
2488  *
2489  * Example usage: cat /sys/kernel/debug/dri/0/eDP-1/target_backlight
2490  */
2491 static int target_backlight_show(struct seq_file *m, void *unused)
2492 {
2493         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private);
2494         struct dc_link *link = aconnector->dc_link;
2495         unsigned int backlight;
2496
2497         backlight = dc_link_get_target_backlight_pwm(link);
2498         seq_printf(m, "0x%x\n", backlight);
2499
2500         return 0;
2501 }
2502
2503 DEFINE_SHOW_ATTRIBUTE(dp_dsc_fec_support);
2504 DEFINE_SHOW_ATTRIBUTE(dmub_fw_state);
2505 DEFINE_SHOW_ATTRIBUTE(dmub_tracebuffer);
2506 DEFINE_SHOW_ATTRIBUTE(output_bpc);
2507 DEFINE_SHOW_ATTRIBUTE(dp_lttpr_status);
2508 #ifdef CONFIG_DRM_AMD_DC_HDCP
2509 DEFINE_SHOW_ATTRIBUTE(hdcp_sink_capability);
2510 #endif
2511 DEFINE_SHOW_ATTRIBUTE(internal_display);
2512 DEFINE_SHOW_ATTRIBUTE(psr_capability);
2513
2514 static const struct file_operations dp_dsc_clock_en_debugfs_fops = {
2515         .owner = THIS_MODULE,
2516         .read = dp_dsc_clock_en_read,
2517         .write = dp_dsc_clock_en_write,
2518         .llseek = default_llseek
2519 };
2520
2521 static const struct file_operations dp_dsc_slice_width_debugfs_fops = {
2522         .owner = THIS_MODULE,
2523         .read = dp_dsc_slice_width_read,
2524         .write = dp_dsc_slice_width_write,
2525         .llseek = default_llseek
2526 };
2527
2528 static const struct file_operations dp_dsc_slice_height_debugfs_fops = {
2529         .owner = THIS_MODULE,
2530         .read = dp_dsc_slice_height_read,
2531         .write = dp_dsc_slice_height_write,
2532         .llseek = default_llseek
2533 };
2534
2535 static const struct file_operations dp_dsc_bits_per_pixel_debugfs_fops = {
2536         .owner = THIS_MODULE,
2537         .read = dp_dsc_bits_per_pixel_read,
2538         .write = dp_dsc_bits_per_pixel_write,
2539         .llseek = default_llseek
2540 };
2541
2542 static const struct file_operations dp_dsc_pic_width_debugfs_fops = {
2543         .owner = THIS_MODULE,
2544         .read = dp_dsc_pic_width_read,
2545         .llseek = default_llseek
2546 };
2547
2548 static const struct file_operations dp_dsc_pic_height_debugfs_fops = {
2549         .owner = THIS_MODULE,
2550         .read = dp_dsc_pic_height_read,
2551         .llseek = default_llseek
2552 };
2553
2554 static const struct file_operations dp_dsc_chunk_size_debugfs_fops = {
2555         .owner = THIS_MODULE,
2556         .read = dp_dsc_chunk_size_read,
2557         .llseek = default_llseek
2558 };
2559
2560 static const struct file_operations dp_dsc_slice_bpg_offset_debugfs_fops = {
2561         .owner = THIS_MODULE,
2562         .read = dp_dsc_slice_bpg_offset_read,
2563         .llseek = default_llseek
2564 };
2565
2566 static const struct file_operations trigger_hotplug_debugfs_fops = {
2567         .owner = THIS_MODULE,
2568         .write = trigger_hotplug,
2569         .llseek = default_llseek
2570 };
2571
2572 static const struct file_operations dp_link_settings_debugfs_fops = {
2573         .owner = THIS_MODULE,
2574         .read = dp_link_settings_read,
2575         .write = dp_link_settings_write,
2576         .llseek = default_llseek
2577 };
2578
2579 static const struct file_operations dp_phy_settings_debugfs_fop = {
2580         .owner = THIS_MODULE,
2581         .read = dp_phy_settings_read,
2582         .write = dp_phy_settings_write,
2583         .llseek = default_llseek
2584 };
2585
2586 static const struct file_operations dp_phy_test_pattern_fops = {
2587         .owner = THIS_MODULE,
2588         .write = dp_phy_test_pattern_debugfs_write,
2589         .llseek = default_llseek
2590 };
2591
2592 static const struct file_operations sdp_message_fops = {
2593         .owner = THIS_MODULE,
2594         .write = dp_sdp_message_debugfs_write,
2595         .llseek = default_llseek
2596 };
2597
2598 static const struct file_operations dp_dpcd_address_debugfs_fops = {
2599         .owner = THIS_MODULE,
2600         .write = dp_dpcd_address_write,
2601         .llseek = default_llseek
2602 };
2603
2604 static const struct file_operations dp_dpcd_size_debugfs_fops = {
2605         .owner = THIS_MODULE,
2606         .write = dp_dpcd_size_write,
2607         .llseek = default_llseek
2608 };
2609
2610 static const struct file_operations dp_dpcd_data_debugfs_fops = {
2611         .owner = THIS_MODULE,
2612         .read = dp_dpcd_data_read,
2613         .write = dp_dpcd_data_write,
2614         .llseek = default_llseek
2615 };
2616
2617 static const struct file_operations dp_max_bpc_debugfs_fops = {
2618         .owner = THIS_MODULE,
2619         .read = dp_max_bpc_read,
2620         .write = dp_max_bpc_write,
2621         .llseek = default_llseek
2622 };
2623
2624 static const struct file_operations dp_dsc_disable_passthrough_debugfs_fops = {
2625         .owner = THIS_MODULE,
2626         .write = dp_dsc_passthrough_set,
2627         .llseek = default_llseek
2628 };
2629
2630 static const struct {
2631         char *name;
2632         const struct file_operations *fops;
2633 } dp_debugfs_entries[] = {
2634                 {"link_settings", &dp_link_settings_debugfs_fops},
2635                 {"phy_settings", &dp_phy_settings_debugfs_fop},
2636                 {"lttpr_status", &dp_lttpr_status_fops},
2637                 {"test_pattern", &dp_phy_test_pattern_fops},
2638 #ifdef CONFIG_DRM_AMD_DC_HDCP
2639                 {"hdcp_sink_capability", &hdcp_sink_capability_fops},
2640 #endif
2641                 {"sdp_message", &sdp_message_fops},
2642                 {"aux_dpcd_address", &dp_dpcd_address_debugfs_fops},
2643                 {"aux_dpcd_size", &dp_dpcd_size_debugfs_fops},
2644                 {"aux_dpcd_data", &dp_dpcd_data_debugfs_fops},
2645                 {"dsc_clock_en", &dp_dsc_clock_en_debugfs_fops},
2646                 {"dsc_slice_width", &dp_dsc_slice_width_debugfs_fops},
2647                 {"dsc_slice_height", &dp_dsc_slice_height_debugfs_fops},
2648                 {"dsc_bits_per_pixel", &dp_dsc_bits_per_pixel_debugfs_fops},
2649                 {"dsc_pic_width", &dp_dsc_pic_width_debugfs_fops},
2650                 {"dsc_pic_height", &dp_dsc_pic_height_debugfs_fops},
2651                 {"dsc_chunk_size", &dp_dsc_chunk_size_debugfs_fops},
2652                 {"dsc_slice_bpg", &dp_dsc_slice_bpg_offset_debugfs_fops},
2653                 {"dp_dsc_fec_support", &dp_dsc_fec_support_fops},
2654                 {"max_bpc", &dp_max_bpc_debugfs_fops},
2655                 {"dsc_disable_passthrough", &dp_dsc_disable_passthrough_debugfs_fops},
2656 };
2657
2658 #ifdef CONFIG_DRM_AMD_DC_HDCP
2659 static const struct {
2660         char *name;
2661         const struct file_operations *fops;
2662 } hdmi_debugfs_entries[] = {
2663                 {"hdcp_sink_capability", &hdcp_sink_capability_fops}
2664 };
2665 #endif
2666 /*
2667  * Force YUV420 output if available from the given mode
2668  */
2669 static int force_yuv420_output_set(void *data, u64 val)
2670 {
2671         struct amdgpu_dm_connector *connector = data;
2672
2673         connector->force_yuv420_output = (bool)val;
2674
2675         return 0;
2676 }
2677
2678 /*
2679  * Check if YUV420 is forced when available from the given mode
2680  */
2681 static int force_yuv420_output_get(void *data, u64 *val)
2682 {
2683         struct amdgpu_dm_connector *connector = data;
2684
2685         *val = connector->force_yuv420_output;
2686
2687         return 0;
2688 }
2689
2690 DEFINE_DEBUGFS_ATTRIBUTE(force_yuv420_output_fops, force_yuv420_output_get,
2691                          force_yuv420_output_set, "%llu\n");
2692
2693 /*
2694  *  Read PSR state
2695  */
2696 static int psr_get(void *data, u64 *val)
2697 {
2698         struct amdgpu_dm_connector *connector = data;
2699         struct dc_link *link = connector->dc_link;
2700         enum dc_psr_state state = PSR_STATE0;
2701
2702         dc_link_get_psr_state(link, &state);
2703
2704         *val = state;
2705
2706         return 0;
2707 }
2708
2709 /*
2710  * Set dmcub trace event IRQ enable or disable.
2711  * Usage to enable dmcub trace event IRQ: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en
2712  * Usage to disable dmcub trace event IRQ: echo 0 > /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en
2713  */
2714 static int dmcub_trace_event_state_set(void *data, u64 val)
2715 {
2716         struct amdgpu_device *adev = data;
2717
2718         if (val == 1 || val == 0) {
2719                 dc_dmub_trace_event_control(adev->dm.dc, val);
2720                 adev->dm.dmcub_trace_event_en = (bool)val;
2721         } else
2722                 return 0;
2723
2724         return 0;
2725 }
2726
2727 /*
2728  * The interface doesn't need get function, so it will return the
2729  * value of zero
2730  * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en
2731  */
2732 static int dmcub_trace_event_state_get(void *data, u64 *val)
2733 {
2734         struct amdgpu_device *adev = data;
2735
2736         *val = adev->dm.dmcub_trace_event_en;
2737         return 0;
2738 }
2739
2740 DEFINE_DEBUGFS_ATTRIBUTE(dmcub_trace_event_state_fops, dmcub_trace_event_state_get,
2741                          dmcub_trace_event_state_set, "%llu\n");
2742
2743 DEFINE_DEBUGFS_ATTRIBUTE(psr_fops, psr_get, NULL, "%llu\n");
2744
2745 DEFINE_SHOW_ATTRIBUTE(current_backlight);
2746 DEFINE_SHOW_ATTRIBUTE(target_backlight);
2747
2748 static const struct {
2749         char *name;
2750         const struct file_operations *fops;
2751 } connector_debugfs_entries[] = {
2752                 {"force_yuv420_output", &force_yuv420_output_fops},
2753                 {"output_bpc", &output_bpc_fops},
2754                 {"trigger_hotplug", &trigger_hotplug_debugfs_fops},
2755                 {"internal_display", &internal_display_fops}
2756 };
2757
2758 /*
2759  * Returns supported customized link rates by this eDP panel.
2760  * Example usage: cat /sys/kernel/debug/dri/0/eDP-x/ilr_setting
2761  */
2762 static int edp_ilr_show(struct seq_file *m, void *unused)
2763 {
2764         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private);
2765         struct dc_link *link = aconnector->dc_link;
2766         uint8_t supported_link_rates[16];
2767         uint32_t link_rate_in_khz;
2768         uint32_t entry = 0;
2769         uint8_t dpcd_rev;
2770
2771         memset(supported_link_rates, 0, sizeof(supported_link_rates));
2772         dm_helpers_dp_read_dpcd(link->ctx, link, DP_SUPPORTED_LINK_RATES,
2773                 supported_link_rates, sizeof(supported_link_rates));
2774
2775         dpcd_rev = link->dpcd_caps.dpcd_rev.raw;
2776
2777         if (dpcd_rev >= DP_DPCD_REV_13 &&
2778                 (supported_link_rates[entry+1] != 0 || supported_link_rates[entry] != 0)) {
2779
2780                 for (entry = 0; entry < 16; entry += 2) {
2781                         link_rate_in_khz = (supported_link_rates[entry+1] * 0x100 +
2782                                                                                 supported_link_rates[entry]) * 200;
2783                         seq_printf(m, "[%d] %d kHz\n", entry/2, link_rate_in_khz);
2784                 }
2785         } else {
2786                 seq_printf(m, "ILR is not supported by this eDP panel.\n");
2787         }
2788
2789         return 0;
2790 }
2791
2792 /*
2793  * Set supported customized link rate to eDP panel.
2794  *
2795  * echo <lane_count>  <link_rate option> > ilr_setting
2796  *
2797  * for example, supported ILR : [0] 1620000 kHz [1] 2160000 kHz [2] 2430000 kHz ...
2798  * echo 4 1 > /sys/kernel/debug/dri/0/eDP-x/ilr_setting
2799  * to set 4 lanes and 2.16 GHz
2800  */
2801 static ssize_t edp_ilr_write(struct file *f, const char __user *buf,
2802                                  size_t size, loff_t *pos)
2803 {
2804         struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
2805         struct dc_link *link = connector->dc_link;
2806         struct amdgpu_device *adev = drm_to_adev(connector->base.dev);
2807         struct dc *dc = (struct dc *)link->dc;
2808         struct dc_link_settings prefer_link_settings;
2809         char *wr_buf = NULL;
2810         const uint32_t wr_buf_size = 40;
2811         /* 0: lane_count; 1: link_rate */
2812         int max_param_num = 2;
2813         uint8_t param_nums = 0;
2814         long param[2];
2815         bool valid_input = true;
2816
2817         if (size == 0)
2818                 return -EINVAL;
2819
2820         wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
2821         if (!wr_buf)
2822                 return -ENOMEM;
2823
2824         if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
2825                                            (long *)param, buf,
2826                                            max_param_num,
2827                                            &param_nums)) {
2828                 kfree(wr_buf);
2829                 return -EINVAL;
2830         }
2831
2832         if (param_nums <= 0) {
2833                 kfree(wr_buf);
2834                 return -EINVAL;
2835         }
2836
2837         switch (param[0]) {
2838         case LANE_COUNT_ONE:
2839         case LANE_COUNT_TWO:
2840         case LANE_COUNT_FOUR:
2841                 break;
2842         default:
2843                 valid_input = false;
2844                 break;
2845         }
2846
2847         if (param[1] >= link->dpcd_caps.edp_supported_link_rates_count)
2848                 valid_input = false;
2849
2850         if (!valid_input) {
2851                 kfree(wr_buf);
2852                 DRM_DEBUG_DRIVER("Invalid Input value. No HW will be programmed\n");
2853                 prefer_link_settings.use_link_rate_set = false;
2854                 dc_link_set_preferred_training_settings(dc, NULL, NULL, link, true);
2855                 return size;
2856         }
2857
2858         /* save user force lane_count, link_rate to preferred settings
2859          * spread spectrum will not be changed
2860          */
2861         prefer_link_settings.link_spread = link->cur_link_settings.link_spread;
2862         prefer_link_settings.lane_count = param[0];
2863         prefer_link_settings.use_link_rate_set = true;
2864         prefer_link_settings.link_rate_set = param[1];
2865         prefer_link_settings.link_rate = link->dpcd_caps.edp_supported_link_rates[param[1]];
2866
2867         mutex_lock(&adev->dm.dc_lock);
2868         dc_link_set_preferred_training_settings(dc, &prefer_link_settings,
2869                                                 NULL, link, false);
2870         mutex_unlock(&adev->dm.dc_lock);
2871
2872         kfree(wr_buf);
2873         return size;
2874 }
2875
2876 static int edp_ilr_open(struct inode *inode, struct file *file)
2877 {
2878         return single_open(file, edp_ilr_show, inode->i_private);
2879 }
2880
2881 static const struct file_operations edp_ilr_debugfs_fops = {
2882         .owner = THIS_MODULE,
2883         .open = edp_ilr_open,
2884         .read = seq_read,
2885         .llseek = seq_lseek,
2886         .release = single_release,
2887         .write = edp_ilr_write
2888 };
2889
2890 void connector_debugfs_init(struct amdgpu_dm_connector *connector)
2891 {
2892         int i;
2893         struct dentry *dir = connector->base.debugfs_entry;
2894
2895         if (connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
2896             connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) {
2897                 for (i = 0; i < ARRAY_SIZE(dp_debugfs_entries); i++) {
2898                         debugfs_create_file(dp_debugfs_entries[i].name,
2899                                             0644, dir, connector,
2900                                             dp_debugfs_entries[i].fops);
2901                 }
2902         }
2903         if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) {
2904                 debugfs_create_file_unsafe("psr_capability", 0444, dir, connector, &psr_capability_fops);
2905                 debugfs_create_file_unsafe("psr_state", 0444, dir, connector, &psr_fops);
2906                 debugfs_create_file("amdgpu_current_backlight_pwm", 0444, dir, connector,
2907                                     &current_backlight_fops);
2908                 debugfs_create_file("amdgpu_target_backlight_pwm", 0444, dir, connector,
2909                                     &target_backlight_fops);
2910                 debugfs_create_file("ilr_setting", 0644, dir, connector,
2911                                         &edp_ilr_debugfs_fops);
2912         }
2913
2914         for (i = 0; i < ARRAY_SIZE(connector_debugfs_entries); i++) {
2915                 debugfs_create_file(connector_debugfs_entries[i].name,
2916                                     0644, dir, connector,
2917                                     connector_debugfs_entries[i].fops);
2918         }
2919
2920         connector->debugfs_dpcd_address = 0;
2921         connector->debugfs_dpcd_size = 0;
2922
2923 #ifdef CONFIG_DRM_AMD_DC_HDCP
2924         if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) {
2925                 for (i = 0; i < ARRAY_SIZE(hdmi_debugfs_entries); i++) {
2926                         debugfs_create_file(hdmi_debugfs_entries[i].name,
2927                                             0644, dir, connector,
2928                                             hdmi_debugfs_entries[i].fops);
2929                 }
2930         }
2931 #endif
2932 }
2933
2934 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
2935 /*
2936  * Set crc window coordinate x start
2937  */
2938 static int crc_win_x_start_set(void *data, u64 val)
2939 {
2940         struct drm_crtc *crtc = data;
2941         struct drm_device *drm_dev = crtc->dev;
2942         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2943
2944         spin_lock_irq(&drm_dev->event_lock);
2945         acrtc->dm_irq_params.crc_window.x_start = (uint16_t) val;
2946         acrtc->dm_irq_params.crc_window.update_win = false;
2947         spin_unlock_irq(&drm_dev->event_lock);
2948
2949         return 0;
2950 }
2951
2952 /*
2953  * Get crc window coordinate x start
2954  */
2955 static int crc_win_x_start_get(void *data, u64 *val)
2956 {
2957         struct drm_crtc *crtc = data;
2958         struct drm_device *drm_dev = crtc->dev;
2959         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2960
2961         spin_lock_irq(&drm_dev->event_lock);
2962         *val = acrtc->dm_irq_params.crc_window.x_start;
2963         spin_unlock_irq(&drm_dev->event_lock);
2964
2965         return 0;
2966 }
2967
2968 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_x_start_fops, crc_win_x_start_get,
2969                          crc_win_x_start_set, "%llu\n");
2970
2971
2972 /*
2973  * Set crc window coordinate y start
2974  */
2975 static int crc_win_y_start_set(void *data, u64 val)
2976 {
2977         struct drm_crtc *crtc = data;
2978         struct drm_device *drm_dev = crtc->dev;
2979         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2980
2981         spin_lock_irq(&drm_dev->event_lock);
2982         acrtc->dm_irq_params.crc_window.y_start = (uint16_t) val;
2983         acrtc->dm_irq_params.crc_window.update_win = false;
2984         spin_unlock_irq(&drm_dev->event_lock);
2985
2986         return 0;
2987 }
2988
2989 /*
2990  * Get crc window coordinate y start
2991  */
2992 static int crc_win_y_start_get(void *data, u64 *val)
2993 {
2994         struct drm_crtc *crtc = data;
2995         struct drm_device *drm_dev = crtc->dev;
2996         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2997
2998         spin_lock_irq(&drm_dev->event_lock);
2999         *val = acrtc->dm_irq_params.crc_window.y_start;
3000         spin_unlock_irq(&drm_dev->event_lock);
3001
3002         return 0;
3003 }
3004
3005 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_y_start_fops, crc_win_y_start_get,
3006                          crc_win_y_start_set, "%llu\n");
3007
3008 /*
3009  * Set crc window coordinate x end
3010  */
3011 static int crc_win_x_end_set(void *data, u64 val)
3012 {
3013         struct drm_crtc *crtc = data;
3014         struct drm_device *drm_dev = crtc->dev;
3015         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3016
3017         spin_lock_irq(&drm_dev->event_lock);
3018         acrtc->dm_irq_params.crc_window.x_end = (uint16_t) val;
3019         acrtc->dm_irq_params.crc_window.update_win = false;
3020         spin_unlock_irq(&drm_dev->event_lock);
3021
3022         return 0;
3023 }
3024
3025 /*
3026  * Get crc window coordinate x end
3027  */
3028 static int crc_win_x_end_get(void *data, u64 *val)
3029 {
3030         struct drm_crtc *crtc = data;
3031         struct drm_device *drm_dev = crtc->dev;
3032         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3033
3034         spin_lock_irq(&drm_dev->event_lock);
3035         *val = acrtc->dm_irq_params.crc_window.x_end;
3036         spin_unlock_irq(&drm_dev->event_lock);
3037
3038         return 0;
3039 }
3040
3041 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_x_end_fops, crc_win_x_end_get,
3042                          crc_win_x_end_set, "%llu\n");
3043
3044 /*
3045  * Set crc window coordinate y end
3046  */
3047 static int crc_win_y_end_set(void *data, u64 val)
3048 {
3049         struct drm_crtc *crtc = data;
3050         struct drm_device *drm_dev = crtc->dev;
3051         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3052
3053         spin_lock_irq(&drm_dev->event_lock);
3054         acrtc->dm_irq_params.crc_window.y_end = (uint16_t) val;
3055         acrtc->dm_irq_params.crc_window.update_win = false;
3056         spin_unlock_irq(&drm_dev->event_lock);
3057
3058         return 0;
3059 }
3060
3061 /*
3062  * Get crc window coordinate y end
3063  */
3064 static int crc_win_y_end_get(void *data, u64 *val)
3065 {
3066         struct drm_crtc *crtc = data;
3067         struct drm_device *drm_dev = crtc->dev;
3068         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3069
3070         spin_lock_irq(&drm_dev->event_lock);
3071         *val = acrtc->dm_irq_params.crc_window.y_end;
3072         spin_unlock_irq(&drm_dev->event_lock);
3073
3074         return 0;
3075 }
3076
3077 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_y_end_fops, crc_win_y_end_get,
3078                          crc_win_y_end_set, "%llu\n");
3079 /*
3080  * Trigger to commit crc window
3081  */
3082 static int crc_win_update_set(void *data, u64 val)
3083 {
3084         struct drm_crtc *new_crtc = data;
3085         struct drm_crtc *old_crtc = NULL;
3086         struct amdgpu_crtc *new_acrtc, *old_acrtc;
3087         struct amdgpu_device *adev = drm_to_adev(new_crtc->dev);
3088         struct crc_rd_work *crc_rd_wrk = adev->dm.crc_rd_wrk;
3089
3090         if (!crc_rd_wrk)
3091                 return 0;
3092
3093         if (val) {
3094                 spin_lock_irq(&adev_to_drm(adev)->event_lock);
3095                 spin_lock_irq(&crc_rd_wrk->crc_rd_work_lock);
3096                 if (crc_rd_wrk->crtc) {
3097                         old_crtc = crc_rd_wrk->crtc;
3098                         old_acrtc = to_amdgpu_crtc(old_crtc);
3099                 }
3100                 new_acrtc = to_amdgpu_crtc(new_crtc);
3101
3102                 if (old_crtc && old_crtc != new_crtc) {
3103                         old_acrtc->dm_irq_params.crc_window.activated = false;
3104                         old_acrtc->dm_irq_params.crc_window.update_win = false;
3105                         old_acrtc->dm_irq_params.crc_window.skip_frame_cnt = 0;
3106
3107                         new_acrtc->dm_irq_params.crc_window.activated = true;
3108                         new_acrtc->dm_irq_params.crc_window.update_win = true;
3109                         new_acrtc->dm_irq_params.crc_window.skip_frame_cnt = 0;
3110                         crc_rd_wrk->crtc = new_crtc;
3111                 } else {
3112                         new_acrtc->dm_irq_params.crc_window.activated = true;
3113                         new_acrtc->dm_irq_params.crc_window.update_win = true;
3114                         new_acrtc->dm_irq_params.crc_window.skip_frame_cnt = 0;
3115                         crc_rd_wrk->crtc = new_crtc;
3116                 }
3117                 spin_unlock_irq(&crc_rd_wrk->crc_rd_work_lock);
3118                 spin_unlock_irq(&adev_to_drm(adev)->event_lock);
3119         }
3120
3121         return 0;
3122 }
3123
3124 /*
3125  * Get crc window update flag
3126  */
3127 static int crc_win_update_get(void *data, u64 *val)
3128 {
3129         *val = 0;
3130         return 0;
3131 }
3132
3133 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_update_fops, crc_win_update_get,
3134                          crc_win_update_set, "%llu\n");
3135
3136 void crtc_debugfs_init(struct drm_crtc *crtc)
3137 {
3138         struct dentry *dir = debugfs_lookup("crc", crtc->debugfs_entry);
3139
3140         if (!dir)
3141                 return;
3142
3143         debugfs_create_file_unsafe("crc_win_x_start", 0644, dir, crtc,
3144                                    &crc_win_x_start_fops);
3145         debugfs_create_file_unsafe("crc_win_y_start", 0644, dir, crtc,
3146                                    &crc_win_y_start_fops);
3147         debugfs_create_file_unsafe("crc_win_x_end", 0644, dir, crtc,
3148                                    &crc_win_x_end_fops);
3149         debugfs_create_file_unsafe("crc_win_y_end", 0644, dir, crtc,
3150                                    &crc_win_y_end_fops);
3151         debugfs_create_file_unsafe("crc_win_update", 0644, dir, crtc,
3152                                    &crc_win_update_fops);
3153
3154 }
3155 #endif
3156 /*
3157  * Writes DTN log state to the user supplied buffer.
3158  * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log
3159  */
3160 static ssize_t dtn_log_read(
3161         struct file *f,
3162         char __user *buf,
3163         size_t size,
3164         loff_t *pos)
3165 {
3166         struct amdgpu_device *adev = file_inode(f)->i_private;
3167         struct dc *dc = adev->dm.dc;
3168         struct dc_log_buffer_ctx log_ctx = { 0 };
3169         ssize_t result = 0;
3170
3171         if (!buf || !size)
3172                 return -EINVAL;
3173
3174         if (!dc->hwss.log_hw_state)
3175                 return 0;
3176
3177         dc->hwss.log_hw_state(dc, &log_ctx);
3178
3179         if (*pos < log_ctx.pos) {
3180                 size_t to_copy = log_ctx.pos - *pos;
3181
3182                 to_copy = min(to_copy, size);
3183
3184                 if (!copy_to_user(buf, log_ctx.buf + *pos, to_copy)) {
3185                         *pos += to_copy;
3186                         result = to_copy;
3187                 }
3188         }
3189
3190         kfree(log_ctx.buf);
3191
3192         return result;
3193 }
3194
3195 /*
3196  * Writes DTN log state to dmesg when triggered via a write.
3197  * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log
3198  */
3199 static ssize_t dtn_log_write(
3200         struct file *f,
3201         const char __user *buf,
3202         size_t size,
3203         loff_t *pos)
3204 {
3205         struct amdgpu_device *adev = file_inode(f)->i_private;
3206         struct dc *dc = adev->dm.dc;
3207
3208         /* Write triggers log output via dmesg. */
3209         if (size == 0)
3210                 return 0;
3211
3212         if (dc->hwss.log_hw_state)
3213                 dc->hwss.log_hw_state(dc, NULL);
3214
3215         return size;
3216 }
3217
3218 static int mst_topo_show(struct seq_file *m, void *unused)
3219 {
3220         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
3221         struct drm_device *dev = adev_to_drm(adev);
3222         struct drm_connector *connector;
3223         struct drm_connector_list_iter conn_iter;
3224         struct amdgpu_dm_connector *aconnector;
3225
3226         drm_connector_list_iter_begin(dev, &conn_iter);
3227         drm_for_each_connector_iter(connector, &conn_iter) {
3228                 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
3229                         continue;
3230
3231                 aconnector = to_amdgpu_dm_connector(connector);
3232
3233                 /* Ensure we're only dumping the topology of a root mst node */
3234                 if (!aconnector->mst_mgr.mst_state)
3235                         continue;
3236
3237                 seq_printf(m, "\nMST topology for connector %d\n", aconnector->connector_id);
3238                 drm_dp_mst_dump_topology(m, &aconnector->mst_mgr);
3239         }
3240         drm_connector_list_iter_end(&conn_iter);
3241
3242         return 0;
3243 }
3244
3245 /*
3246  * Sets trigger hpd for MST topologies.
3247  * All connected connectors will be rediscovered and re started as needed if val of 1 is sent.
3248  * All topologies will be disconnected if val of 0 is set .
3249  * Usage to enable topologies: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst
3250  * Usage to disable topologies: echo 0 > /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst
3251  */
3252 static int trigger_hpd_mst_set(void *data, u64 val)
3253 {
3254         struct amdgpu_device *adev = data;
3255         struct drm_device *dev = adev_to_drm(adev);
3256         struct drm_connector_list_iter iter;
3257         struct amdgpu_dm_connector *aconnector;
3258         struct drm_connector *connector;
3259         struct dc_link *link = NULL;
3260
3261         if (val == 1) {
3262                 drm_connector_list_iter_begin(dev, &iter);
3263                 drm_for_each_connector_iter(connector, &iter) {
3264                         aconnector = to_amdgpu_dm_connector(connector);
3265                         if (aconnector->dc_link->type == dc_connection_mst_branch &&
3266                             aconnector->mst_mgr.aux) {
3267                                 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
3268                                 drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
3269                         }
3270                 }
3271         } else if (val == 0) {
3272                 drm_connector_list_iter_begin(dev, &iter);
3273                 drm_for_each_connector_iter(connector, &iter) {
3274                         aconnector = to_amdgpu_dm_connector(connector);
3275                         if (!aconnector->dc_link)
3276                                 continue;
3277
3278                         if (!aconnector->mst_port)
3279                                 continue;
3280
3281                         link = aconnector->dc_link;
3282                         dp_receiver_power_ctrl(link, false);
3283                         drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_port->mst_mgr, false);
3284                         link->mst_stream_alloc_table.stream_count = 0;
3285                         memset(link->mst_stream_alloc_table.stream_allocations, 0,
3286                                         sizeof(link->mst_stream_alloc_table.stream_allocations));
3287                 }
3288         } else {
3289                 return 0;
3290         }
3291         drm_kms_helper_hotplug_event(dev);
3292
3293         return 0;
3294 }
3295
3296 /*
3297  * The interface doesn't need get function, so it will return the
3298  * value of zero
3299  * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst
3300  */
3301 static int trigger_hpd_mst_get(void *data, u64 *val)
3302 {
3303         *val = 0;
3304         return 0;
3305 }
3306
3307 DEFINE_DEBUGFS_ATTRIBUTE(trigger_hpd_mst_ops, trigger_hpd_mst_get,
3308                          trigger_hpd_mst_set, "%llu\n");
3309
3310
3311 /*
3312  * Sets the force_timing_sync debug option from the given string.
3313  * All connected displays will be force synchronized immediately.
3314  * Usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_force_timing_sync
3315  */
3316 static int force_timing_sync_set(void *data, u64 val)
3317 {
3318         struct amdgpu_device *adev = data;
3319
3320         adev->dm.force_timing_sync = (bool)val;
3321
3322         amdgpu_dm_trigger_timing_sync(adev_to_drm(adev));
3323
3324         return 0;
3325 }
3326
3327 /*
3328  * Gets the force_timing_sync debug option value into the given buffer.
3329  * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_force_timing_sync
3330  */
3331 static int force_timing_sync_get(void *data, u64 *val)
3332 {
3333         struct amdgpu_device *adev = data;
3334
3335         *val = adev->dm.force_timing_sync;
3336
3337         return 0;
3338 }
3339
3340 DEFINE_DEBUGFS_ATTRIBUTE(force_timing_sync_ops, force_timing_sync_get,
3341                          force_timing_sync_set, "%llu\n");
3342
3343
3344 /*
3345  * Disables all HPD and HPD RX interrupt handling in the
3346  * driver when set to 1. Default is 0.
3347  */
3348 static int disable_hpd_set(void *data, u64 val)
3349 {
3350         struct amdgpu_device *adev = data;
3351
3352         adev->dm.disable_hpd_irq = (bool)val;
3353
3354         return 0;
3355 }
3356
3357
3358 /*
3359  * Returns 1 if HPD and HPRX interrupt handling is disabled,
3360  * 0 otherwise.
3361  */
3362 static int disable_hpd_get(void *data, u64 *val)
3363 {
3364         struct amdgpu_device *adev = data;
3365
3366         *val = adev->dm.disable_hpd_irq;
3367
3368         return 0;
3369 }
3370
3371 DEFINE_DEBUGFS_ATTRIBUTE(disable_hpd_ops, disable_hpd_get,
3372                          disable_hpd_set, "%llu\n");
3373
3374 #if defined(CONFIG_DRM_AMD_DC_DCN)
3375 /*
3376  * Temporary w/a to force sst sequence in M42D DP2 mst receiver
3377  * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dp_set_mst_en_for_sst
3378  */
3379 static int dp_force_sst_set(void *data, u64 val)
3380 {
3381         struct amdgpu_device *adev = data;
3382
3383         adev->dm.dc->debug.set_mst_en_for_sst = val;
3384
3385         return 0;
3386 }
3387
3388 static int dp_force_sst_get(void *data, u64 *val)
3389 {
3390         struct amdgpu_device *adev = data;
3391
3392         *val = adev->dm.dc->debug.set_mst_en_for_sst;
3393
3394         return 0;
3395 }
3396 DEFINE_DEBUGFS_ATTRIBUTE(dp_set_mst_en_for_sst_ops, dp_force_sst_get,
3397                          dp_force_sst_set, "%llu\n");
3398 #endif
3399
3400 /*
3401  * Sets the DC visual confirm debug option from the given string.
3402  * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_visual_confirm
3403  */
3404 static int visual_confirm_set(void *data, u64 val)
3405 {
3406         struct amdgpu_device *adev = data;
3407
3408         adev->dm.dc->debug.visual_confirm = (enum visual_confirm)val;
3409
3410         return 0;
3411 }
3412
3413 /*
3414  * Reads the DC visual confirm debug option value into the given buffer.
3415  * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_visual_confirm
3416  */
3417 static int visual_confirm_get(void *data, u64 *val)
3418 {
3419         struct amdgpu_device *adev = data;
3420
3421         *val = adev->dm.dc->debug.visual_confirm;
3422
3423         return 0;
3424 }
3425
3426 DEFINE_SHOW_ATTRIBUTE(mst_topo);
3427 DEFINE_DEBUGFS_ATTRIBUTE(visual_confirm_fops, visual_confirm_get,
3428                          visual_confirm_set, "%llu\n");
3429
3430 /*
3431  * Dumps the DCC_EN bit for each pipe.
3432  * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dcc_en
3433  */
3434 static ssize_t dcc_en_bits_read(
3435         struct file *f,
3436         char __user *buf,
3437         size_t size,
3438         loff_t *pos)
3439 {
3440         struct amdgpu_device *adev = file_inode(f)->i_private;
3441         struct dc *dc = adev->dm.dc;
3442         char *rd_buf = NULL;
3443         const uint32_t rd_buf_size = 32;
3444         uint32_t result = 0;
3445         int offset = 0;
3446         int num_pipes = dc->res_pool->pipe_count;
3447         int *dcc_en_bits;
3448         int i, r;
3449
3450         dcc_en_bits = kcalloc(num_pipes, sizeof(int), GFP_KERNEL);
3451         if (!dcc_en_bits)
3452                 return -ENOMEM;
3453
3454         if (!dc->hwss.get_dcc_en_bits) {
3455                 kfree(dcc_en_bits);
3456                 return 0;
3457         }
3458
3459         dc->hwss.get_dcc_en_bits(dc, dcc_en_bits);
3460
3461         rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
3462         if (!rd_buf)
3463                 return -ENOMEM;
3464
3465         for (i = 0; i < num_pipes; i++)
3466                 offset += snprintf(rd_buf + offset, rd_buf_size - offset,
3467                                    "%d  ", dcc_en_bits[i]);
3468         rd_buf[strlen(rd_buf)] = '\n';
3469
3470         kfree(dcc_en_bits);
3471
3472         while (size) {
3473                 if (*pos >= rd_buf_size)
3474                         break;
3475                 r = put_user(*(rd_buf + result), buf);
3476                 if (r)
3477                         return r; /* r = -EFAULT */
3478                 buf += 1;
3479                 size -= 1;
3480                 *pos += 1;
3481                 result += 1;
3482         }
3483
3484         kfree(rd_buf);
3485         return result;
3486 }
3487
3488 void dtn_debugfs_init(struct amdgpu_device *adev)
3489 {
3490         static const struct file_operations dtn_log_fops = {
3491                 .owner = THIS_MODULE,
3492                 .read = dtn_log_read,
3493                 .write = dtn_log_write,
3494                 .llseek = default_llseek
3495         };
3496         static const struct file_operations dcc_en_bits_fops = {
3497                 .owner = THIS_MODULE,
3498                 .read = dcc_en_bits_read,
3499                 .llseek = default_llseek
3500         };
3501
3502         struct drm_minor *minor = adev_to_drm(adev)->primary;
3503         struct dentry *root = minor->debugfs_root;
3504
3505         debugfs_create_file("amdgpu_mst_topology", 0444, root,
3506                             adev, &mst_topo_fops);
3507         debugfs_create_file("amdgpu_dm_dtn_log", 0644, root, adev,
3508                             &dtn_log_fops);
3509 #if defined(CONFIG_DRM_AMD_DC_DCN)
3510         debugfs_create_file("amdgpu_dm_dp_set_mst_en_for_sst", 0644, root, adev,
3511                                 &dp_set_mst_en_for_sst_ops);
3512 #endif
3513
3514         debugfs_create_file_unsafe("amdgpu_dm_visual_confirm", 0644, root, adev,
3515                                    &visual_confirm_fops);
3516
3517         debugfs_create_file_unsafe("amdgpu_dm_dmub_tracebuffer", 0644, root,
3518                                    adev, &dmub_tracebuffer_fops);
3519
3520         debugfs_create_file_unsafe("amdgpu_dm_dmub_fw_state", 0644, root,
3521                                    adev, &dmub_fw_state_fops);
3522
3523         debugfs_create_file_unsafe("amdgpu_dm_force_timing_sync", 0644, root,
3524                                    adev, &force_timing_sync_ops);
3525
3526         debugfs_create_file_unsafe("amdgpu_dm_dmcub_trace_event_en", 0644, root,
3527                                    adev, &dmcub_trace_event_state_fops);
3528
3529         debugfs_create_file_unsafe("amdgpu_dm_trigger_hpd_mst", 0644, root,
3530                                    adev, &trigger_hpd_mst_ops);
3531
3532         debugfs_create_file_unsafe("amdgpu_dm_dcc_en", 0644, root, adev,
3533                                    &dcc_en_bits_fops);
3534
3535         debugfs_create_file_unsafe("amdgpu_dm_disable_hpd", 0644, root, adev,
3536                                    &disable_hpd_ops);
3537
3538 }