2 * Copyright (C) 2015-2020 Advanced Micro Devices, Inc. All rights reserved.
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26 #ifndef __AMDGPU_DM_H__
27 #define __AMDGPU_DM_H__
29 #include <drm/display/drm_dp_mst_helper.h>
30 #include <drm/drm_atomic.h>
31 #include <drm/drm_connector.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_plane.h>
34 #include "link_service_types.h"
35 #include <drm/drm_writeback.h>
38 * This file contains the definition for amdgpu_display_manager
39 * and its API for amdgpu driver's use.
40 * This component provides all the display related functionality
41 * and this is the only component that calls DAL API.
42 * The API contained here intended for amdgpu driver use.
43 * The API that is called directly from KMS framework is located
44 * in amdgpu_dm_kms.h file
47 #define AMDGPU_DM_MAX_DISPLAY_INDEX 31
49 #define AMDGPU_DM_MAX_CRTC 6
51 #define AMDGPU_DM_MAX_NUM_EDP 2
53 #define AMDGPU_DMUB_NOTIFICATION_MAX 5
55 #define HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_IEEE_REGISTRATION_ID 0x00001A
56 #define AMD_VSDB_VERSION_3_FEATURECAP_REPLAYMODE 0x40
57 #define HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3 0x3
59 #define AMDGPU_HDR_MULT_DEFAULT (0x100000000LL)
62 #include "include/amdgpu_dal_power_if.h"
63 #include "amdgpu_dm_irq.h"
66 #include "irq_types.h"
67 #include "signal_types.h"
68 #include "amdgpu_dm_crc.h"
69 #include "mod_info_packet.h"
71 struct set_config_cmd_payload;
72 enum aux_return_code_type;
73 enum set_config_status;
75 /* Forward declarations */
82 struct dc_plane_state;
83 struct dmub_notification;
85 struct amd_vsdb_block {
86 unsigned char ieee_id[3];
87 unsigned char version;
88 unsigned char feature_caps;
91 struct common_irq_params {
92 struct amdgpu_device *adev;
93 enum dc_irq_source irq_src;
94 atomic64_t previous_timestamp;
98 * struct dm_compressor_info - Buffer info used by frame buffer compression
99 * @cpu_addr: MMIO cpu addr
100 * @bo_ptr: Pointer to the buffer object
101 * @gpu_addr: MMIO gpu addr
103 struct dm_compressor_info {
105 struct amdgpu_bo *bo_ptr;
109 typedef void (*dmub_notify_interrupt_callback_t)(struct amdgpu_device *adev, struct dmub_notification *notify);
112 * struct dmub_hpd_work - Handle time consuming work in low priority outbox IRQ
114 * @handle_hpd_work: Work to be executed in a separate thread to handle hpd_low_irq
115 * @dmub_notify: notification for callback function
116 * @adev: amdgpu_device pointer
118 struct dmub_hpd_work {
119 struct work_struct handle_hpd_work;
120 struct dmub_notification *dmub_notify;
121 struct amdgpu_device *adev;
125 * struct vblank_control_work - Work data for vblank control
126 * @work: Kernel work data for the work event
127 * @dm: amdgpu display manager device
128 * @acrtc: amdgpu CRTC instance for which the event has occurred
129 * @stream: DC stream for which the event has occurred
130 * @enable: true if enabling vblank
132 struct vblank_control_work {
133 struct work_struct work;
134 struct amdgpu_display_manager *dm;
135 struct amdgpu_crtc *acrtc;
136 struct dc_stream_state *stream;
141 * struct amdgpu_dm_backlight_caps - Information about backlight
143 * Describe the backlight support for ACPI or eDP AUX.
145 struct amdgpu_dm_backlight_caps {
147 * @ext_caps: Keep the data struct with all the information about the
148 * display support for HDR.
150 union dpcd_sink_ext_caps *ext_caps;
152 * @aux_min_input_signal: Min brightness value supported by the display
154 u32 aux_min_input_signal;
156 * @aux_max_input_signal: Max brightness value supported by the display
159 u32 aux_max_input_signal;
161 * @min_input_signal: minimum possible input in range 0-255.
163 int min_input_signal;
165 * @max_input_signal: maximum possible input in range 0-255.
167 int max_input_signal;
169 * @caps_valid: true if these values are from the ACPI interface.
173 * @aux_support: Describes if the display supports AUX backlight.
179 * struct dal_allocation - Tracks mapped FB memory for SMU communication
180 * @list: list of dal allocations
181 * @bo: GPU buffer object
182 * @cpu_ptr: CPU virtual address of the GPU buffer object
183 * @gpu_addr: GPU virtual address of the GPU buffer object
185 struct dal_allocation {
186 struct list_head list;
187 struct amdgpu_bo *bo;
193 * struct hpd_rx_irq_offload_work_queue - Work queue to handle hpd_rx_irq
196 struct hpd_rx_irq_offload_work_queue {
198 * @wq: workqueue structure to queue offload work.
200 struct workqueue_struct *wq;
202 * @offload_lock: To protect fields of offload work queue.
204 spinlock_t offload_lock;
206 * @is_handling_link_loss: Used to prevent inserting link loss event when
207 * we're handling link loss
209 bool is_handling_link_loss;
211 * @is_handling_mst_msg_rdy_event: Used to prevent inserting mst message
212 * ready event when we're already handling mst message ready event
214 bool is_handling_mst_msg_rdy_event;
216 * @aconnector: The aconnector that this work queue is attached to
218 struct amdgpu_dm_connector *aconnector;
222 * struct hpd_rx_irq_offload_work - hpd_rx_irq offload work structure
224 struct hpd_rx_irq_offload_work {
226 * @work: offload work
228 struct work_struct work;
230 * @data: reference irq data which is used while handling offload work
232 union hpd_irq_data data;
234 * @offload_wq: offload work queue that this work is queued to
236 struct hpd_rx_irq_offload_work_queue *offload_wq;
240 * struct amdgpu_display_manager - Central amdgpu display manager device
242 * @dc: Display Core control structure
243 * @adev: AMDGPU base driver structure
244 * @ddev: DRM base driver structure
245 * @display_indexes_num: Max number of display streams supported
246 * @irq_handler_list_table_lock: Synchronizes access to IRQ tables
247 * @backlight_dev: Backlight control device
248 * @backlight_link: Link on which to control backlight
249 * @backlight_caps: Capabilities of the backlight device
250 * @freesync_module: Module handling freesync calculations
251 * @hdcp_workqueue: AMDGPU content protection queue
252 * @fw_dmcu: Reference to DMCU firmware
253 * @dmcu_fw_version: Version of the DMCU firmware
254 * @soc_bounding_box: SOC bounding box values provided by gpu_info FW
255 * @cached_state: Caches device atomic state for suspend/resume
256 * @cached_dc_state: Cached state of content streams
257 * @compressor: Frame buffer compression buffer. See &struct dm_compressor_info
258 * @force_timing_sync: set via debugfs. When set, indicates that all connected
259 * displays will be forced to synchronize.
260 * @dmcub_trace_event_en: enable dmcub trace events
261 * @dmub_outbox_params: DMUB Outbox parameters
262 * @num_of_edps: number of backlight eDPs
263 * @disable_hpd_irq: disables all HPD and HPD RX interrupt handling in the
265 * @dmub_aux_transfer_done: struct completion used to indicate when DMUB
267 * @delayed_hpd_wq: work queue used to delay DMUB HPD work
269 struct amdgpu_display_manager {
276 * DMUB service, used for controlling the DMUB on hardware
277 * that supports it. The pointer to the dmub_srv will be
278 * NULL on hardware that does not support it.
280 struct dmub_srv *dmub_srv;
285 * Notification from DMUB.
288 struct dmub_notification *dmub_notify;
293 * Callback functions to handle notification from DMUB.
296 dmub_notify_interrupt_callback_t dmub_callback[AMDGPU_DMUB_NOTIFICATION_MAX];
299 * @dmub_thread_offload:
301 * Flag to indicate if callback is offload.
304 bool dmub_thread_offload[AMDGPU_DMUB_NOTIFICATION_MAX];
309 * Framebuffer regions for the DMUB.
311 struct dmub_srv_fb_info *dmub_fb_info;
316 * DMUB firmware, required on hardware that has DMUB support.
318 const struct firmware *dmub_fw;
323 * Buffer object for the DMUB.
325 struct amdgpu_bo *dmub_bo;
330 * GPU virtual address for the DMUB buffer object.
332 u64 dmub_bo_gpu_addr;
337 * CPU address for the DMUB buffer object.
339 void *dmub_bo_cpu_addr;
344 * DMCUB firmware version.
346 uint32_t dmcub_fw_version;
351 * The Common Graphics Services device. It provides an interface for
352 * accessing registers.
354 struct cgs_device *cgs_device;
356 struct amdgpu_device *adev;
357 struct drm_device *ddev;
358 u16 display_indexes_num;
363 * In combination with &dm_atomic_state it helps manage
364 * global atomic state that doesn't map cleanly into existing
365 * drm resources, like &dc_context.
367 struct drm_private_obj atomic_obj;
372 * Guards access to DC functions that can issue register write
375 struct mutex dc_lock;
380 * Guards access to audio instance changes.
382 struct mutex audio_lock;
387 * Used to notify ELD changes to sound driver.
389 struct drm_audio_component *audio_component;
394 * True if the audio component has been registered
395 * successfully, false otherwise.
397 bool audio_registered;
400 * @irq_handler_list_low_tab:
402 * Low priority IRQ handler table.
404 * It is a n*m table consisting of n IRQ sources, and m handlers per IRQ
405 * source. Low priority IRQ handlers are deferred to a workqueue to be
406 * processed. Hence, they can sleep.
408 * Note that handlers are called in the same order as they were
411 struct list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER];
414 * @irq_handler_list_high_tab:
416 * High priority IRQ handler table.
418 * It is a n*m table, same as &irq_handler_list_low_tab. However,
419 * handlers in this table are not deferred and are called immediately.
421 struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER];
426 * Page flip IRQ parameters, passed to registered handlers when
429 struct common_irq_params
430 pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1];
435 * Vertical blanking IRQ parameters, passed to registered handlers when
438 struct common_irq_params
439 vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1];
444 * OTG vertical interrupt0 IRQ parameters, passed to registered
445 * handlers when triggered.
447 struct common_irq_params
448 vline0_params[DC_IRQ_SOURCE_DC6_VLINE0 - DC_IRQ_SOURCE_DC1_VLINE0 + 1];
453 * Vertical update IRQ parameters, passed to registered handlers when
456 struct common_irq_params
457 vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1];
460 * @dmub_trace_params:
462 * DMUB trace event IRQ parameters, passed to registered handlers when
465 struct common_irq_params
466 dmub_trace_params[1];
468 struct common_irq_params
469 dmub_outbox_params[1];
471 spinlock_t irq_handler_list_table_lock;
473 struct backlight_device *backlight_dev[AMDGPU_DM_MAX_NUM_EDP];
475 const struct dc_link *backlight_link[AMDGPU_DM_MAX_NUM_EDP];
479 struct amdgpu_dm_backlight_caps backlight_caps[AMDGPU_DM_MAX_NUM_EDP];
481 struct mod_freesync *freesync_module;
482 struct hdcp_workqueue *hdcp_workqueue;
485 * @vblank_control_workqueue:
487 * Deferred work for vblank control events.
489 struct workqueue_struct *vblank_control_workqueue;
491 struct drm_atomic_state *cached_state;
492 struct dc_state *cached_dc_state;
494 struct dm_compressor_info compressor;
496 const struct firmware *fw_dmcu;
497 uint32_t dmcu_fw_version;
501 * gpu_info FW provided soc bounding box struct or 0 if not
504 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box;
507 * @active_vblank_irq_count:
509 * number of currently active vblank irqs
511 uint32_t active_vblank_irq_count;
513 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
515 * @secure_display_ctxs:
517 * Store the ROI information and the work_struct to command dmub and psp for
520 struct secure_display_context *secure_display_ctxs;
523 * @hpd_rx_offload_wq:
525 * Work queue to offload works of hpd_rx_irq
527 struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq;
531 * fake encoders used for DP MST.
533 struct amdgpu_encoder mst_encoders[AMDGPU_DM_MAX_CRTC];
534 bool force_timing_sync;
535 bool disable_hpd_irq;
536 bool dmcub_trace_event_en;
540 * DAL fb memory allocation list, for communication with SMU.
542 struct list_head da_list;
543 struct completion dmub_aux_transfer_done;
544 struct workqueue_struct *delayed_hpd_wq;
549 * cached backlight values.
551 u32 brightness[AMDGPU_DM_MAX_NUM_EDP];
553 * @actual_brightness:
555 * last successfully applied backlight values.
557 u32 actual_brightness[AMDGPU_DM_MAX_NUM_EDP];
560 * @aux_hpd_discon_quirk:
562 * quirk for hpd discon while aux is on-going.
563 * occurred on certain intel platform
565 bool aux_hpd_discon_quirk;
570 * Guards access to DPIA AUX
572 struct mutex dpia_aux_lock;
575 enum dsc_clock_force_state {
576 DSC_CLK_FORCE_DEFAULT = 0,
577 DSC_CLK_FORCE_ENABLE,
578 DSC_CLK_FORCE_DISABLE,
581 struct dsc_preferred_settings {
582 enum dsc_clock_force_state dsc_force_enable;
583 uint32_t dsc_num_slices_v;
584 uint32_t dsc_num_slices_h;
585 uint32_t dsc_bits_per_pixel;
586 bool dsc_force_disable_passthrough;
589 enum mst_progress_status {
590 MST_STATUS_DEFAULT = 0,
592 MST_REMOTE_EDID = BIT(1),
593 MST_ALLOCATE_NEW_PAYLOAD = BIT(2),
594 MST_CLEAR_ALLOCATED_PAYLOAD = BIT(3),
598 * struct amdgpu_hdmi_vsdb_info - Keep track of the VSDB info
600 * AMDGPU supports FreeSync over HDMI by using the VSDB section, and this
601 * struct is useful to keep track of the display-specific information about
604 struct amdgpu_hdmi_vsdb_info {
606 * @amd_vsdb_version: Vendor Specific Data Block Version, should be
607 * used to determine which Vendor Specific InfoFrame (VSIF) to send.
609 unsigned int amd_vsdb_version;
612 * @freesync_supported: FreeSync Supported.
614 bool freesync_supported;
617 * @min_refresh_rate_hz: FreeSync Minimum Refresh Rate in Hz.
619 unsigned int min_refresh_rate_hz;
622 * @max_refresh_rate_hz: FreeSync Maximum Refresh Rate in Hz
624 unsigned int max_refresh_rate_hz;
627 * @replay_mode: Replay supported
632 struct amdgpu_dm_connector {
634 struct drm_connector base;
635 uint32_t connector_id;
638 /* we need to mind the EDID between detect
639 and get modes due to analog/digital/tvencoder */
642 /* shared with amdgpu */
643 struct amdgpu_hpd hpd;
645 /* number of modes generated from EDID at 'dc_sink' */
648 /* The 'old' sink - before an HPD.
649 * The 'current' sink is in dc_link->sink. */
650 struct dc_sink *dc_sink;
651 struct dc_link *dc_link;
654 * @dc_em_sink: Reference to the emulated (virtual) sink.
656 struct dc_sink *dc_em_sink;
659 struct drm_dp_mst_topology_mgr mst_mgr;
660 struct amdgpu_dm_dp_aux dm_dp_aux;
661 struct drm_dp_mst_port *mst_output_port;
662 struct amdgpu_dm_connector *mst_root;
663 struct drm_dp_aux *dsc_aux;
664 struct mutex handle_mst_msg_ready;
666 /* TODO see if we can merge with ddc_bus or make a dm_connector */
667 struct amdgpu_i2c_adapter *i2c;
669 /* Monitor range limits */
671 * @min_vfreq: Minimal frequency supported by the display in Hz. This
672 * value is set to zero when there is no FreeSync support.
677 * @max_vfreq: Maximum frequency supported by the display in Hz. This
678 * value is set to zero when there is no FreeSync support.
683 /* Audio instance - protected by audio_lock. */
686 struct mutex hpd_lock;
689 bool force_yuv420_output;
690 struct dsc_preferred_settings dsc_settings;
691 union dp_downstream_port_present mst_downstream_port_present;
692 /* Cached display modes */
693 struct drm_display_mode freesync_vid_base;
697 /* Record progress status of mst*/
700 /* Automated testing */
702 struct dc_crtc_timing *timing_requested;
706 enum adaptive_sync_type as_type;
707 struct amdgpu_hdmi_vsdb_info vsdb_info;
710 static inline void amdgpu_dm_set_mst_status(uint8_t *status,
711 uint8_t flags, bool set)
719 #define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base)
721 struct amdgpu_dm_wb_connector {
722 struct drm_writeback_connector base;
723 struct dc_link *link;
726 #define to_amdgpu_dm_wb_connector(x) container_of(x, struct amdgpu_dm_wb_connector, base)
728 extern const struct amdgpu_ip_block_version dm_ip_block;
730 /* enum amdgpu_transfer_function: pre-defined transfer function supported by AMD.
732 * It includes standardized transfer functions and pure power functions. The
733 * transfer function coefficients are available at modules/color/color_gamma.c
735 enum amdgpu_transfer_function {
736 AMDGPU_TRANSFER_FUNCTION_DEFAULT,
737 AMDGPU_TRANSFER_FUNCTION_SRGB_EOTF,
738 AMDGPU_TRANSFER_FUNCTION_BT709_INV_OETF,
739 AMDGPU_TRANSFER_FUNCTION_PQ_EOTF,
740 AMDGPU_TRANSFER_FUNCTION_IDENTITY,
741 AMDGPU_TRANSFER_FUNCTION_GAMMA22_EOTF,
742 AMDGPU_TRANSFER_FUNCTION_GAMMA24_EOTF,
743 AMDGPU_TRANSFER_FUNCTION_GAMMA26_EOTF,
744 AMDGPU_TRANSFER_FUNCTION_SRGB_INV_EOTF,
745 AMDGPU_TRANSFER_FUNCTION_BT709_OETF,
746 AMDGPU_TRANSFER_FUNCTION_PQ_INV_EOTF,
747 AMDGPU_TRANSFER_FUNCTION_GAMMA22_INV_EOTF,
748 AMDGPU_TRANSFER_FUNCTION_GAMMA24_INV_EOTF,
749 AMDGPU_TRANSFER_FUNCTION_GAMMA26_INV_EOTF,
750 AMDGPU_TRANSFER_FUNCTION_COUNT
753 struct dm_plane_state {
754 struct drm_plane_state base;
755 struct dc_plane_state *dc_state;
757 /* Plane color mgmt */
761 * 1D LUT for mapping framebuffer/plane pixel data before sampling or
762 * blending operations. It's usually applied to linearize input space.
763 * The blob (if not NULL) is an array of &struct drm_color_lut.
765 struct drm_property_blob *degamma_lut;
769 * Predefined transfer function to tell DC driver the input space to
772 enum amdgpu_transfer_function degamma_tf;
776 * Multiplier to 'gain' the plane. When PQ is decoded using the fixed
777 * func transfer function to the internal FP16 fb, 1.0 -> 80 nits (on
778 * AMD at least). When sRGB is decoded, 1.0 -> 1.0, obviously.
779 * Therefore, 1.0 multiplier = 80 nits for SDR content. So if you
780 * want, 203 nits for SDR content, pass in (203.0 / 80.0). Format is
781 * S31.32 sign-magnitude.
783 * HDR multiplier can wide range beyond [0.0, 1.0]. This means that PQ
784 * TF is needed for any subsequent linear-to-non-linear transforms.
788 * @shaper_lut: shaper lookup table blob. The blob (if not NULL) is an
789 * array of &struct drm_color_lut.
791 struct drm_property_blob *shaper_lut;
795 * Predefined transfer function to delinearize color space.
797 enum amdgpu_transfer_function shaper_tf;
799 * @lut3d: 3D lookup table blob. The blob (if not NULL) is an array of
800 * &struct drm_color_lut.
802 struct drm_property_blob *lut3d;
804 * @blend_lut: blend lut lookup table blob. The blob (if not NULL) is an
805 * array of &struct drm_color_lut.
807 struct drm_property_blob *blend_lut;
811 * Pre-defined transfer function for converting plane pixel data before
812 * applying blend LUT.
814 enum amdgpu_transfer_function blend_tf;
817 struct dm_crtc_state {
818 struct drm_crtc_state base;
819 struct dc_stream_state *stream;
822 bool cm_is_degamma_srgb;
831 bool freesync_vrr_info_changed;
833 bool dsc_force_changed;
835 struct mod_freesync_config freesync_config;
836 struct dc_info_packet vrr_infopacket;
843 * Pre-defined transfer function for converting internal FB -> wire
846 enum amdgpu_transfer_function regamma_tf;
849 #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base)
851 struct dm_atomic_state {
852 struct drm_private_state base;
854 struct dc_state *context;
857 #define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base)
859 struct dm_connector_state {
860 struct drm_connector_state base;
862 enum amdgpu_rmx_type scaling;
863 uint8_t underscan_vborder;
864 uint8_t underscan_hborder;
865 bool underscan_enable;
866 bool freesync_capable;
873 #define to_dm_connector_state(x)\
874 container_of((x), struct dm_connector_state, base)
876 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector);
877 struct drm_connector_state *
878 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector);
879 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
880 struct drm_connector_state *state,
881 struct drm_property *property,
884 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
885 const struct drm_connector_state *state,
886 struct drm_property *property,
889 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev);
891 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
892 struct amdgpu_dm_connector *aconnector,
894 struct dc_link *link,
897 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
898 struct drm_display_mode *mode);
900 void dm_restore_drm_connector_state(struct drm_device *dev,
901 struct drm_connector *connector);
903 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
906 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev);
908 /* 3D LUT max size is 17x17x17 (4913 entries) */
909 #define MAX_COLOR_3DLUT_SIZE 17
910 #define MAX_COLOR_3DLUT_BITDEPTH 12
912 #define MAX_COLOR_LUT_ENTRIES 4096
913 /* Legacy gamm LUT users such as X doesn't like large LUT sizes */
914 #define MAX_COLOR_LEGACY_LUT_ENTRIES 256
916 void amdgpu_dm_init_color_mod(void);
917 int amdgpu_dm_create_color_properties(struct amdgpu_device *adev);
918 int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state);
919 int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc);
920 int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc,
921 struct drm_plane_state *plane_state,
922 struct dc_plane_state *dc_plane_state);
924 void amdgpu_dm_update_connector_after_detect(
925 struct amdgpu_dm_connector *aconnector);
927 extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs;
929 int amdgpu_dm_process_dmub_aux_transfer_sync(struct dc_context *ctx, unsigned int link_index,
930 struct aux_payload *payload, enum aux_return_code_type *operation_result);
932 int amdgpu_dm_process_dmub_set_config_sync(struct dc_context *ctx, unsigned int link_index,
933 struct set_config_cmd_payload *payload, enum set_config_status *operation_result);
935 struct dc_stream_state *
936 create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector,
937 const struct drm_display_mode *drm_mode,
938 const struct dm_connector_state *dm_state,
939 const struct dc_stream_state *old_stream);
941 int dm_atomic_get_state(struct drm_atomic_state *state,
942 struct dm_atomic_state **dm_state);
944 struct drm_connector *
945 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
946 struct drm_crtc *crtc);
948 int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth);
949 #endif /* __AMDGPU_DM_H__ */