2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 /* The caprices of the preprocessor require that this be declared right here */
27 #define CREATE_TRACE_POINTS
29 #include "dm_services_types.h"
31 #include "link_enc_cfg.h"
32 #include "dc/inc/core_types.h"
33 #include "dal_asic_id.h"
34 #include "dmub/dmub_srv.h"
35 #include "dc/inc/hw/dmcu.h"
36 #include "dc/inc/hw/abm.h"
37 #include "dc/dc_dmub_srv.h"
38 #include "dc/dc_edid_parser.h"
39 #include "dc/dc_stat.h"
40 #include "amdgpu_dm_trace.h"
41 #include "dpcd_defs.h"
42 #include "link/protocols/link_dpcd.h"
43 #include "link_service_types.h"
44 #include "link/protocols/link_dp_capability.h"
45 #include "link/protocols/link_ddc.h"
49 #include "amdgpu_display.h"
50 #include "amdgpu_ucode.h"
52 #include "amdgpu_dm.h"
53 #include "amdgpu_dm_plane.h"
54 #include "amdgpu_dm_crtc.h"
55 #include "amdgpu_dm_hdcp.h"
56 #include <drm/display/drm_hdcp_helper.h>
57 #include "amdgpu_pm.h"
58 #include "amdgpu_atombios.h"
60 #include "amd_shared.h"
61 #include "amdgpu_dm_irq.h"
62 #include "dm_helpers.h"
63 #include "amdgpu_dm_mst_types.h"
64 #if defined(CONFIG_DEBUG_FS)
65 #include "amdgpu_dm_debugfs.h"
67 #include "amdgpu_dm_psr.h"
69 #include "ivsrcid/ivsrcid_vislands30.h"
71 #include <linux/backlight.h>
72 #include <linux/module.h>
73 #include <linux/moduleparam.h>
74 #include <linux/types.h>
75 #include <linux/pm_runtime.h>
76 #include <linux/pci.h>
77 #include <linux/firmware.h>
78 #include <linux/component.h>
79 #include <linux/dmi.h>
81 #include <drm/display/drm_dp_mst_helper.h>
82 #include <drm/display/drm_hdmi_helper.h>
83 #include <drm/drm_atomic.h>
84 #include <drm/drm_atomic_uapi.h>
85 #include <drm/drm_atomic_helper.h>
86 #include <drm/drm_blend.h>
87 #include <drm/drm_fourcc.h>
88 #include <drm/drm_edid.h>
89 #include <drm/drm_vblank.h>
90 #include <drm/drm_audio_component.h>
91 #include <drm/drm_gem_atomic_helper.h>
92 #include <drm/drm_plane_helper.h>
94 #include <acpi/video.h>
96 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
98 #include "dcn/dcn_1_0_offset.h"
99 #include "dcn/dcn_1_0_sh_mask.h"
100 #include "soc15_hw_ip.h"
101 #include "soc15_common.h"
102 #include "vega10_ip_offset.h"
104 #include "gc/gc_11_0_0_offset.h"
105 #include "gc/gc_11_0_0_sh_mask.h"
107 #include "modules/inc/mod_freesync.h"
108 #include "modules/power/power_helpers.h"
110 #define FIRMWARE_RENOIR_DMUB "amdgpu/renoir_dmcub.bin"
111 MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB);
112 #define FIRMWARE_SIENNA_CICHLID_DMUB "amdgpu/sienna_cichlid_dmcub.bin"
113 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID_DMUB);
114 #define FIRMWARE_NAVY_FLOUNDER_DMUB "amdgpu/navy_flounder_dmcub.bin"
115 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER_DMUB);
116 #define FIRMWARE_GREEN_SARDINE_DMUB "amdgpu/green_sardine_dmcub.bin"
117 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE_DMUB);
118 #define FIRMWARE_VANGOGH_DMUB "amdgpu/vangogh_dmcub.bin"
119 MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB);
120 #define FIRMWARE_DIMGREY_CAVEFISH_DMUB "amdgpu/dimgrey_cavefish_dmcub.bin"
121 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH_DMUB);
122 #define FIRMWARE_BEIGE_GOBY_DMUB "amdgpu/beige_goby_dmcub.bin"
123 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY_DMUB);
124 #define FIRMWARE_YELLOW_CARP_DMUB "amdgpu/yellow_carp_dmcub.bin"
125 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP_DMUB);
126 #define FIRMWARE_DCN_314_DMUB "amdgpu/dcn_3_1_4_dmcub.bin"
127 MODULE_FIRMWARE(FIRMWARE_DCN_314_DMUB);
128 #define FIRMWARE_DCN_315_DMUB "amdgpu/dcn_3_1_5_dmcub.bin"
129 MODULE_FIRMWARE(FIRMWARE_DCN_315_DMUB);
130 #define FIRMWARE_DCN316_DMUB "amdgpu/dcn_3_1_6_dmcub.bin"
131 MODULE_FIRMWARE(FIRMWARE_DCN316_DMUB);
133 #define FIRMWARE_DCN_V3_2_0_DMCUB "amdgpu/dcn_3_2_0_dmcub.bin"
134 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_0_DMCUB);
135 #define FIRMWARE_DCN_V3_2_1_DMCUB "amdgpu/dcn_3_2_1_dmcub.bin"
136 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_1_DMCUB);
138 #define FIRMWARE_RAVEN_DMCU "amdgpu/raven_dmcu.bin"
139 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
141 #define FIRMWARE_NAVI12_DMCU "amdgpu/navi12_dmcu.bin"
142 MODULE_FIRMWARE(FIRMWARE_NAVI12_DMCU);
144 /* Number of bytes in PSP header for firmware. */
145 #define PSP_HEADER_BYTES 0x100
147 /* Number of bytes in PSP footer for firmware. */
148 #define PSP_FOOTER_BYTES 0x100
153 * The AMDgpu display manager, **amdgpu_dm** (or even simpler,
154 * **dm**) sits between DRM and DC. It acts as a liaison, converting DRM
155 * requests into DC requests, and DC responses into DRM responses.
157 * The root control structure is &struct amdgpu_display_manager.
160 /* basic init/fini API */
161 static int amdgpu_dm_init(struct amdgpu_device *adev);
162 static void amdgpu_dm_fini(struct amdgpu_device *adev);
163 static bool is_freesync_video_mode(const struct drm_display_mode *mode, struct amdgpu_dm_connector *aconnector);
165 static enum drm_mode_subconnector get_subconnector_type(struct dc_link *link)
167 switch (link->dpcd_caps.dongle_type) {
168 case DISPLAY_DONGLE_NONE:
169 return DRM_MODE_SUBCONNECTOR_Native;
170 case DISPLAY_DONGLE_DP_VGA_CONVERTER:
171 return DRM_MODE_SUBCONNECTOR_VGA;
172 case DISPLAY_DONGLE_DP_DVI_CONVERTER:
173 case DISPLAY_DONGLE_DP_DVI_DONGLE:
174 return DRM_MODE_SUBCONNECTOR_DVID;
175 case DISPLAY_DONGLE_DP_HDMI_CONVERTER:
176 case DISPLAY_DONGLE_DP_HDMI_DONGLE:
177 return DRM_MODE_SUBCONNECTOR_HDMIA;
178 case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
180 return DRM_MODE_SUBCONNECTOR_Unknown;
184 static void update_subconnector_property(struct amdgpu_dm_connector *aconnector)
186 struct dc_link *link = aconnector->dc_link;
187 struct drm_connector *connector = &aconnector->base;
188 enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
190 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
193 if (aconnector->dc_sink)
194 subconnector = get_subconnector_type(link);
196 drm_object_property_set_value(&connector->base,
197 connector->dev->mode_config.dp_subconnector_property,
202 * initializes drm_device display related structures, based on the information
203 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
204 * drm_encoder, drm_mode_config
206 * Returns 0 on success
208 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
209 /* removes and deallocates the drm structures, created by the above function */
210 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
212 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
213 struct amdgpu_dm_connector *amdgpu_dm_connector,
215 struct amdgpu_encoder *amdgpu_encoder);
216 static int amdgpu_dm_encoder_init(struct drm_device *dev,
217 struct amdgpu_encoder *aencoder,
218 uint32_t link_index);
220 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
222 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
224 static int amdgpu_dm_atomic_check(struct drm_device *dev,
225 struct drm_atomic_state *state);
227 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector);
228 static void handle_hpd_rx_irq(void *param);
231 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
232 struct drm_crtc_state *new_crtc_state);
234 * dm_vblank_get_counter
237 * Get counter for number of vertical blanks
240 * struct amdgpu_device *adev - [in] desired amdgpu device
241 * int disp_idx - [in] which CRTC to get the counter from
244 * Counter for vertical blanks
246 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
248 if (crtc >= adev->mode_info.num_crtc)
251 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
253 if (acrtc->dm_irq_params.stream == NULL) {
254 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
259 return dc_stream_get_vblank_counter(acrtc->dm_irq_params.stream);
263 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
264 u32 *vbl, u32 *position)
266 u32 v_blank_start, v_blank_end, h_position, v_position;
268 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
271 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
273 if (acrtc->dm_irq_params.stream == NULL) {
274 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
280 * TODO rework base driver to use values directly.
281 * for now parse it back into reg-format
283 dc_stream_get_scanoutpos(acrtc->dm_irq_params.stream,
289 *position = v_position | (h_position << 16);
290 *vbl = v_blank_start | (v_blank_end << 16);
296 static bool dm_is_idle(void *handle)
302 static int dm_wait_for_idle(void *handle)
308 static bool dm_check_soft_reset(void *handle)
313 static int dm_soft_reset(void *handle)
319 static struct amdgpu_crtc *
320 get_crtc_by_otg_inst(struct amdgpu_device *adev,
323 struct drm_device *dev = adev_to_drm(adev);
324 struct drm_crtc *crtc;
325 struct amdgpu_crtc *amdgpu_crtc;
327 if (WARN_ON(otg_inst == -1))
328 return adev->mode_info.crtcs[0];
330 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
331 amdgpu_crtc = to_amdgpu_crtc(crtc);
333 if (amdgpu_crtc->otg_inst == otg_inst)
340 static inline bool is_dc_timing_adjust_needed(struct dm_crtc_state *old_state,
341 struct dm_crtc_state *new_state)
343 if (new_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)
345 else if (amdgpu_dm_crtc_vrr_active(old_state) != amdgpu_dm_crtc_vrr_active(new_state))
351 static inline void reverse_planes_order(struct dc_surface_update *array_of_surface_update,
356 for (i = 0, j = planes_count - 1; i < j; i++, j--)
357 swap(array_of_surface_update[i], array_of_surface_update[j]);
361 * update_planes_and_stream_adapter() - Send planes to be updated in DC
363 * DC has a generic way to update planes and stream via
364 * dc_update_planes_and_stream function; however, DM might need some
365 * adjustments and preparation before calling it. This function is a wrapper
366 * for the dc_update_planes_and_stream that does any required configuration
367 * before passing control to DC.
369 static inline bool update_planes_and_stream_adapter(struct dc *dc,
372 struct dc_stream_state *stream,
373 struct dc_stream_update *stream_update,
374 struct dc_surface_update *array_of_surface_update)
376 reverse_planes_order(array_of_surface_update, planes_count);
379 * Previous frame finished and HW is ready for optimization.
381 if (update_type == UPDATE_TYPE_FAST)
382 dc_post_update_surfaces_to_stream(dc);
384 return dc_update_planes_and_stream(dc,
385 array_of_surface_update,
392 * dm_pflip_high_irq() - Handle pageflip interrupt
393 * @interrupt_params: ignored
395 * Handles the pageflip interrupt by notifying all interested parties
396 * that the pageflip has been completed.
398 static void dm_pflip_high_irq(void *interrupt_params)
400 struct amdgpu_crtc *amdgpu_crtc;
401 struct common_irq_params *irq_params = interrupt_params;
402 struct amdgpu_device *adev = irq_params->adev;
404 struct drm_pending_vblank_event *e;
405 u32 vpos, hpos, v_blank_start, v_blank_end;
408 amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
410 /* IRQ could occur when in initial stage */
411 /* TODO work and BO cleanup */
412 if (amdgpu_crtc == NULL) {
413 DC_LOG_PFLIP("CRTC is null, returning.\n");
417 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
419 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
420 DC_LOG_PFLIP("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
421 amdgpu_crtc->pflip_status,
422 AMDGPU_FLIP_SUBMITTED,
423 amdgpu_crtc->crtc_id,
425 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
429 /* page flip completed. */
430 e = amdgpu_crtc->event;
431 amdgpu_crtc->event = NULL;
435 vrr_active = amdgpu_dm_crtc_vrr_active_irq(amdgpu_crtc);
437 /* Fixed refresh rate, or VRR scanout position outside front-porch? */
439 !dc_stream_get_scanoutpos(amdgpu_crtc->dm_irq_params.stream, &v_blank_start,
440 &v_blank_end, &hpos, &vpos) ||
441 (vpos < v_blank_start)) {
442 /* Update to correct count and vblank timestamp if racing with
443 * vblank irq. This also updates to the correct vblank timestamp
444 * even in VRR mode, as scanout is past the front-porch atm.
446 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
448 /* Wake up userspace by sending the pageflip event with proper
449 * count and timestamp of vblank of flip completion.
452 drm_crtc_send_vblank_event(&amdgpu_crtc->base, e);
454 /* Event sent, so done with vblank for this flip */
455 drm_crtc_vblank_put(&amdgpu_crtc->base);
458 /* VRR active and inside front-porch: vblank count and
459 * timestamp for pageflip event will only be up to date after
460 * drm_crtc_handle_vblank() has been executed from late vblank
461 * irq handler after start of back-porch (vline 0). We queue the
462 * pageflip event for send-out by drm_crtc_handle_vblank() with
463 * updated timestamp and count, once it runs after us.
465 * We need to open-code this instead of using the helper
466 * drm_crtc_arm_vblank_event(), as that helper would
467 * call drm_crtc_accurate_vblank_count(), which we must
468 * not call in VRR mode while we are in front-porch!
471 /* sequence will be replaced by real count during send-out. */
472 e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base);
473 e->pipe = amdgpu_crtc->crtc_id;
475 list_add_tail(&e->base.link, &adev_to_drm(adev)->vblank_event_list);
479 /* Keep track of vblank of this flip for flip throttling. We use the
480 * cooked hw counter, as that one incremented at start of this vblank
481 * of pageflip completion, so last_flip_vblank is the forbidden count
482 * for queueing new pageflips if vsync + VRR is enabled.
484 amdgpu_crtc->dm_irq_params.last_flip_vblank =
485 amdgpu_get_vblank_counter_kms(&amdgpu_crtc->base);
487 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
488 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
490 DC_LOG_PFLIP("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n",
491 amdgpu_crtc->crtc_id, amdgpu_crtc,
492 vrr_active, (int) !e);
495 static void dm_vupdate_high_irq(void *interrupt_params)
497 struct common_irq_params *irq_params = interrupt_params;
498 struct amdgpu_device *adev = irq_params->adev;
499 struct amdgpu_crtc *acrtc;
500 struct drm_device *drm_dev;
501 struct drm_vblank_crtc *vblank;
502 ktime_t frame_duration_ns, previous_timestamp;
506 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE);
509 vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc);
510 drm_dev = acrtc->base.dev;
511 vblank = &drm_dev->vblank[acrtc->base.index];
512 previous_timestamp = atomic64_read(&irq_params->previous_timestamp);
513 frame_duration_ns = vblank->time - previous_timestamp;
515 if (frame_duration_ns > 0) {
516 trace_amdgpu_refresh_rate_track(acrtc->base.index,
518 ktime_divns(NSEC_PER_SEC, frame_duration_ns));
519 atomic64_set(&irq_params->previous_timestamp, vblank->time);
522 DC_LOG_VBLANK("crtc:%d, vupdate-vrr:%d\n",
526 /* Core vblank handling is done here after end of front-porch in
527 * vrr mode, as vblank timestamping will give valid results
528 * while now done after front-porch. This will also deliver
529 * page-flip completion events that have been queued to us
530 * if a pageflip happened inside front-porch.
533 amdgpu_dm_crtc_handle_vblank(acrtc);
535 /* BTR processing for pre-DCE12 ASICs */
536 if (acrtc->dm_irq_params.stream &&
537 adev->family < AMDGPU_FAMILY_AI) {
538 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
539 mod_freesync_handle_v_update(
540 adev->dm.freesync_module,
541 acrtc->dm_irq_params.stream,
542 &acrtc->dm_irq_params.vrr_params);
544 dc_stream_adjust_vmin_vmax(
546 acrtc->dm_irq_params.stream,
547 &acrtc->dm_irq_params.vrr_params.adjust);
548 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
555 * dm_crtc_high_irq() - Handles CRTC interrupt
556 * @interrupt_params: used for determining the CRTC instance
558 * Handles the CRTC/VSYNC interrupt by notfying DRM's VBLANK
561 static void dm_crtc_high_irq(void *interrupt_params)
563 struct common_irq_params *irq_params = interrupt_params;
564 struct amdgpu_device *adev = irq_params->adev;
565 struct amdgpu_crtc *acrtc;
569 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
573 vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc);
575 DC_LOG_VBLANK("crtc:%d, vupdate-vrr:%d, planes:%d\n", acrtc->crtc_id,
576 vrr_active, acrtc->dm_irq_params.active_planes);
579 * Core vblank handling at start of front-porch is only possible
580 * in non-vrr mode, as only there vblank timestamping will give
581 * valid results while done in front-porch. Otherwise defer it
582 * to dm_vupdate_high_irq after end of front-porch.
585 amdgpu_dm_crtc_handle_vblank(acrtc);
588 * Following stuff must happen at start of vblank, for crc
589 * computation and below-the-range btr support in vrr mode.
591 amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
593 /* BTR updates need to happen before VUPDATE on Vega and above. */
594 if (adev->family < AMDGPU_FAMILY_AI)
597 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
599 if (acrtc->dm_irq_params.stream &&
600 acrtc->dm_irq_params.vrr_params.supported &&
601 acrtc->dm_irq_params.freesync_config.state ==
602 VRR_STATE_ACTIVE_VARIABLE) {
603 mod_freesync_handle_v_update(adev->dm.freesync_module,
604 acrtc->dm_irq_params.stream,
605 &acrtc->dm_irq_params.vrr_params);
607 dc_stream_adjust_vmin_vmax(adev->dm.dc, acrtc->dm_irq_params.stream,
608 &acrtc->dm_irq_params.vrr_params.adjust);
612 * If there aren't any active_planes then DCH HUBP may be clock-gated.
613 * In that case, pageflip completion interrupts won't fire and pageflip
614 * completion events won't get delivered. Prevent this by sending
615 * pending pageflip events from here if a flip is still pending.
617 * If any planes are enabled, use dm_pflip_high_irq() instead, to
618 * avoid race conditions between flip programming and completion,
619 * which could cause too early flip completion events.
621 if (adev->family >= AMDGPU_FAMILY_RV &&
622 acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED &&
623 acrtc->dm_irq_params.active_planes == 0) {
625 drm_crtc_send_vblank_event(&acrtc->base, acrtc->event);
627 drm_crtc_vblank_put(&acrtc->base);
629 acrtc->pflip_status = AMDGPU_FLIP_NONE;
632 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
635 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
637 * dm_dcn_vertical_interrupt0_high_irq() - Handles OTG Vertical interrupt0 for
638 * DCN generation ASICs
639 * @interrupt_params: interrupt parameters
641 * Used to set crc window/read out crc value at vertical line 0 position
643 static void dm_dcn_vertical_interrupt0_high_irq(void *interrupt_params)
645 struct common_irq_params *irq_params = interrupt_params;
646 struct amdgpu_device *adev = irq_params->adev;
647 struct amdgpu_crtc *acrtc;
649 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VLINE0);
654 amdgpu_dm_crtc_handle_crc_window_irq(&acrtc->base);
656 #endif /* CONFIG_DRM_AMD_SECURE_DISPLAY */
659 * dmub_aux_setconfig_callback - Callback for AUX or SET_CONFIG command.
660 * @adev: amdgpu_device pointer
661 * @notify: dmub notification structure
663 * Dmub AUX or SET_CONFIG command completion processing callback
664 * Copies dmub notification to DM which is to be read by AUX command.
665 * issuing thread and also signals the event to wake up the thread.
667 static void dmub_aux_setconfig_callback(struct amdgpu_device *adev,
668 struct dmub_notification *notify)
670 if (adev->dm.dmub_notify)
671 memcpy(adev->dm.dmub_notify, notify, sizeof(struct dmub_notification));
672 if (notify->type == DMUB_NOTIFICATION_AUX_REPLY)
673 complete(&adev->dm.dmub_aux_transfer_done);
677 * dmub_hpd_callback - DMUB HPD interrupt processing callback.
678 * @adev: amdgpu_device pointer
679 * @notify: dmub notification structure
681 * Dmub Hpd interrupt processing callback. Gets displayindex through the
682 * ink index and calls helper to do the processing.
684 static void dmub_hpd_callback(struct amdgpu_device *adev,
685 struct dmub_notification *notify)
687 struct amdgpu_dm_connector *aconnector;
688 struct amdgpu_dm_connector *hpd_aconnector = NULL;
689 struct drm_connector *connector;
690 struct drm_connector_list_iter iter;
691 struct dc_link *link;
693 struct drm_device *dev;
698 if (notify == NULL) {
699 DRM_ERROR("DMUB HPD callback notification was NULL");
703 if (notify->link_index > adev->dm.dc->link_count) {
704 DRM_ERROR("DMUB HPD index (%u)is abnormal", notify->link_index);
708 link_index = notify->link_index;
709 link = adev->dm.dc->links[link_index];
712 drm_connector_list_iter_begin(dev, &iter);
713 drm_for_each_connector_iter(connector, &iter) {
714 aconnector = to_amdgpu_dm_connector(connector);
715 if (link && aconnector->dc_link == link) {
716 if (notify->type == DMUB_NOTIFICATION_HPD)
717 DRM_INFO("DMUB HPD callback: link_index=%u\n", link_index);
718 else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ)
719 DRM_INFO("DMUB HPD IRQ callback: link_index=%u\n", link_index);
721 DRM_WARN("DMUB Unknown HPD callback type %d, link_index=%u\n",
722 notify->type, link_index);
724 hpd_aconnector = aconnector;
728 drm_connector_list_iter_end(&iter);
730 if (hpd_aconnector) {
731 if (notify->type == DMUB_NOTIFICATION_HPD)
732 handle_hpd_irq_helper(hpd_aconnector);
733 else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ)
734 handle_hpd_rx_irq(hpd_aconnector);
739 * register_dmub_notify_callback - Sets callback for DMUB notify
740 * @adev: amdgpu_device pointer
741 * @type: Type of dmub notification
742 * @callback: Dmub interrupt callback function
743 * @dmub_int_thread_offload: offload indicator
745 * API to register a dmub callback handler for a dmub notification
746 * Also sets indicator whether callback processing to be offloaded.
747 * to dmub interrupt handling thread
748 * Return: true if successfully registered, false if there is existing registration
750 static bool register_dmub_notify_callback(struct amdgpu_device *adev,
751 enum dmub_notification_type type,
752 dmub_notify_interrupt_callback_t callback,
753 bool dmub_int_thread_offload)
755 if (callback != NULL && type < ARRAY_SIZE(adev->dm.dmub_thread_offload)) {
756 adev->dm.dmub_callback[type] = callback;
757 adev->dm.dmub_thread_offload[type] = dmub_int_thread_offload;
764 static void dm_handle_hpd_work(struct work_struct *work)
766 struct dmub_hpd_work *dmub_hpd_wrk;
768 dmub_hpd_wrk = container_of(work, struct dmub_hpd_work, handle_hpd_work);
770 if (!dmub_hpd_wrk->dmub_notify) {
771 DRM_ERROR("dmub_hpd_wrk dmub_notify is NULL");
775 if (dmub_hpd_wrk->dmub_notify->type < ARRAY_SIZE(dmub_hpd_wrk->adev->dm.dmub_callback)) {
776 dmub_hpd_wrk->adev->dm.dmub_callback[dmub_hpd_wrk->dmub_notify->type](dmub_hpd_wrk->adev,
777 dmub_hpd_wrk->dmub_notify);
780 kfree(dmub_hpd_wrk->dmub_notify);
785 #define DMUB_TRACE_MAX_READ 64
787 * dm_dmub_outbox1_low_irq() - Handles Outbox interrupt
788 * @interrupt_params: used for determining the Outbox instance
790 * Handles the Outbox Interrupt
793 static void dm_dmub_outbox1_low_irq(void *interrupt_params)
795 struct dmub_notification notify;
796 struct common_irq_params *irq_params = interrupt_params;
797 struct amdgpu_device *adev = irq_params->adev;
798 struct amdgpu_display_manager *dm = &adev->dm;
799 struct dmcub_trace_buf_entry entry = { 0 };
801 struct dmub_hpd_work *dmub_hpd_wrk;
802 struct dc_link *plink = NULL;
804 if (dc_enable_dmub_notifications(adev->dm.dc) &&
805 irq_params->irq_src == DC_IRQ_SOURCE_DMCUB_OUTBOX) {
808 dc_stat_get_dmub_notification(adev->dm.dc, ¬ify);
809 if (notify.type >= ARRAY_SIZE(dm->dmub_thread_offload)) {
810 DRM_ERROR("DM: notify type %d invalid!", notify.type);
813 if (!dm->dmub_callback[notify.type]) {
814 DRM_DEBUG_DRIVER("DMUB notification skipped, no handler: type=%d\n", notify.type);
817 if (dm->dmub_thread_offload[notify.type] == true) {
818 dmub_hpd_wrk = kzalloc(sizeof(*dmub_hpd_wrk), GFP_ATOMIC);
820 DRM_ERROR("Failed to allocate dmub_hpd_wrk");
823 dmub_hpd_wrk->dmub_notify = kmemdup(¬ify, sizeof(struct dmub_notification),
825 if (!dmub_hpd_wrk->dmub_notify) {
827 DRM_ERROR("Failed to allocate dmub_hpd_wrk->dmub_notify");
830 INIT_WORK(&dmub_hpd_wrk->handle_hpd_work, dm_handle_hpd_work);
831 dmub_hpd_wrk->adev = adev;
832 if (notify.type == DMUB_NOTIFICATION_HPD) {
833 plink = adev->dm.dc->links[notify.link_index];
836 notify.hpd_status == DP_HPD_PLUG;
839 queue_work(adev->dm.delayed_hpd_wq, &dmub_hpd_wrk->handle_hpd_work);
841 dm->dmub_callback[notify.type](adev, ¬ify);
843 } while (notify.pending_notification);
848 if (dc_dmub_srv_get_dmub_outbox0_msg(dm->dc, &entry)) {
849 trace_amdgpu_dmub_trace_high_irq(entry.trace_code, entry.tick_count,
850 entry.param0, entry.param1);
852 DRM_DEBUG_DRIVER("trace_code:%u, tick_count:%u, param0:%u, param1:%u\n",
853 entry.trace_code, entry.tick_count, entry.param0, entry.param1);
859 } while (count <= DMUB_TRACE_MAX_READ);
861 if (count > DMUB_TRACE_MAX_READ)
862 DRM_DEBUG_DRIVER("Warning : count > DMUB_TRACE_MAX_READ");
865 static int dm_set_clockgating_state(void *handle,
866 enum amd_clockgating_state state)
871 static int dm_set_powergating_state(void *handle,
872 enum amd_powergating_state state)
877 /* Prototypes of private functions */
878 static int dm_early_init(void* handle);
880 /* Allocate memory for FBC compressed data */
881 static void amdgpu_dm_fbc_init(struct drm_connector *connector)
883 struct drm_device *dev = connector->dev;
884 struct amdgpu_device *adev = drm_to_adev(dev);
885 struct dm_compressor_info *compressor = &adev->dm.compressor;
886 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
887 struct drm_display_mode *mode;
888 unsigned long max_size = 0;
890 if (adev->dm.dc->fbc_compressor == NULL)
893 if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
896 if (compressor->bo_ptr)
900 list_for_each_entry(mode, &connector->modes, head) {
901 if (max_size < mode->htotal * mode->vtotal)
902 max_size = mode->htotal * mode->vtotal;
906 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,
907 AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr,
908 &compressor->gpu_addr, &compressor->cpu_addr);
911 DRM_ERROR("DM: Failed to initialize FBC\n");
913 adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
914 DRM_INFO("DM: FBC alloc %lu\n", max_size*4);
921 static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port,
922 int pipe, bool *enabled,
923 unsigned char *buf, int max_bytes)
925 struct drm_device *dev = dev_get_drvdata(kdev);
926 struct amdgpu_device *adev = drm_to_adev(dev);
927 struct drm_connector *connector;
928 struct drm_connector_list_iter conn_iter;
929 struct amdgpu_dm_connector *aconnector;
934 mutex_lock(&adev->dm.audio_lock);
936 drm_connector_list_iter_begin(dev, &conn_iter);
937 drm_for_each_connector_iter(connector, &conn_iter) {
938 aconnector = to_amdgpu_dm_connector(connector);
939 if (aconnector->audio_inst != port)
943 ret = drm_eld_size(connector->eld);
944 memcpy(buf, connector->eld, min(max_bytes, ret));
948 drm_connector_list_iter_end(&conn_iter);
950 mutex_unlock(&adev->dm.audio_lock);
952 DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled);
957 static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = {
958 .get_eld = amdgpu_dm_audio_component_get_eld,
961 static int amdgpu_dm_audio_component_bind(struct device *kdev,
962 struct device *hda_kdev, void *data)
964 struct drm_device *dev = dev_get_drvdata(kdev);
965 struct amdgpu_device *adev = drm_to_adev(dev);
966 struct drm_audio_component *acomp = data;
968 acomp->ops = &amdgpu_dm_audio_component_ops;
970 adev->dm.audio_component = acomp;
975 static void amdgpu_dm_audio_component_unbind(struct device *kdev,
976 struct device *hda_kdev, void *data)
978 struct drm_device *dev = dev_get_drvdata(kdev);
979 struct amdgpu_device *adev = drm_to_adev(dev);
980 struct drm_audio_component *acomp = data;
984 adev->dm.audio_component = NULL;
987 static const struct component_ops amdgpu_dm_audio_component_bind_ops = {
988 .bind = amdgpu_dm_audio_component_bind,
989 .unbind = amdgpu_dm_audio_component_unbind,
992 static int amdgpu_dm_audio_init(struct amdgpu_device *adev)
999 adev->mode_info.audio.enabled = true;
1001 adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count;
1003 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1004 adev->mode_info.audio.pin[i].channels = -1;
1005 adev->mode_info.audio.pin[i].rate = -1;
1006 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1007 adev->mode_info.audio.pin[i].status_bits = 0;
1008 adev->mode_info.audio.pin[i].category_code = 0;
1009 adev->mode_info.audio.pin[i].connected = false;
1010 adev->mode_info.audio.pin[i].id =
1011 adev->dm.dc->res_pool->audios[i]->inst;
1012 adev->mode_info.audio.pin[i].offset = 0;
1015 ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops);
1019 adev->dm.audio_registered = true;
1024 static void amdgpu_dm_audio_fini(struct amdgpu_device *adev)
1029 if (!adev->mode_info.audio.enabled)
1032 if (adev->dm.audio_registered) {
1033 component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops);
1034 adev->dm.audio_registered = false;
1037 /* TODO: Disable audio? */
1039 adev->mode_info.audio.enabled = false;
1042 static void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin)
1044 struct drm_audio_component *acomp = adev->dm.audio_component;
1046 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) {
1047 DRM_DEBUG_KMS("Notify ELD: %d\n", pin);
1049 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
1054 static int dm_dmub_hw_init(struct amdgpu_device *adev)
1056 const struct dmcub_firmware_header_v1_0 *hdr;
1057 struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
1058 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
1059 const struct firmware *dmub_fw = adev->dm.dmub_fw;
1060 struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
1061 struct abm *abm = adev->dm.dc->res_pool->abm;
1062 struct dmub_srv_hw_params hw_params;
1063 enum dmub_status status;
1064 const unsigned char *fw_inst_const, *fw_bss_data;
1065 u32 i, fw_inst_const_size, fw_bss_data_size;
1066 bool has_hw_support;
1069 /* DMUB isn't supported on the ASIC. */
1073 DRM_ERROR("No framebuffer info for DMUB service.\n");
1078 /* Firmware required for DMUB support. */
1079 DRM_ERROR("No firmware provided for DMUB.\n");
1083 status = dmub_srv_has_hw_support(dmub_srv, &has_hw_support);
1084 if (status != DMUB_STATUS_OK) {
1085 DRM_ERROR("Error checking HW support for DMUB: %d\n", status);
1089 if (!has_hw_support) {
1090 DRM_INFO("DMUB unsupported on ASIC\n");
1094 /* Reset DMCUB if it was previously running - before we overwrite its memory. */
1095 status = dmub_srv_hw_reset(dmub_srv);
1096 if (status != DMUB_STATUS_OK)
1097 DRM_WARN("Error resetting DMUB HW: %d\n", status);
1099 hdr = (const struct dmcub_firmware_header_v1_0 *)dmub_fw->data;
1101 fw_inst_const = dmub_fw->data +
1102 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1105 fw_bss_data = dmub_fw->data +
1106 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1107 le32_to_cpu(hdr->inst_const_bytes);
1109 /* Copy firmware and bios info into FB memory. */
1110 fw_inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
1111 PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
1113 fw_bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
1115 /* if adev->firmware.load_type == AMDGPU_FW_LOAD_PSP,
1116 * amdgpu_ucode_init_single_fw will load dmub firmware
1117 * fw_inst_const part to cw0; otherwise, the firmware back door load
1118 * will be done by dm_dmub_hw_init
1120 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1121 memcpy(fb_info->fb[DMUB_WINDOW_0_INST_CONST].cpu_addr, fw_inst_const,
1122 fw_inst_const_size);
1125 if (fw_bss_data_size)
1126 memcpy(fb_info->fb[DMUB_WINDOW_2_BSS_DATA].cpu_addr,
1127 fw_bss_data, fw_bss_data_size);
1129 /* Copy firmware bios info into FB memory. */
1130 memcpy(fb_info->fb[DMUB_WINDOW_3_VBIOS].cpu_addr, adev->bios,
1133 /* Reset regions that need to be reset. */
1134 memset(fb_info->fb[DMUB_WINDOW_4_MAILBOX].cpu_addr, 0,
1135 fb_info->fb[DMUB_WINDOW_4_MAILBOX].size);
1137 memset(fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr, 0,
1138 fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size);
1140 memset(fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr, 0,
1141 fb_info->fb[DMUB_WINDOW_6_FW_STATE].size);
1143 /* Initialize hardware. */
1144 memset(&hw_params, 0, sizeof(hw_params));
1145 hw_params.fb_base = adev->gmc.fb_start;
1146 hw_params.fb_offset = adev->vm_manager.vram_base_offset;
1148 /* backdoor load firmware and trigger dmub running */
1149 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
1150 hw_params.load_inst_const = true;
1153 hw_params.psp_version = dmcu->psp_version;
1155 for (i = 0; i < fb_info->num_fb; ++i)
1156 hw_params.fb[i] = &fb_info->fb[i];
1158 switch (adev->ip_versions[DCE_HWIP][0]) {
1159 case IP_VERSION(3, 1, 3):
1160 case IP_VERSION(3, 1, 4):
1161 hw_params.dpia_supported = true;
1162 hw_params.disable_dpia = adev->dm.dc->debug.dpia_debug.bits.disable_dpia;
1168 status = dmub_srv_hw_init(dmub_srv, &hw_params);
1169 if (status != DMUB_STATUS_OK) {
1170 DRM_ERROR("Error initializing DMUB HW: %d\n", status);
1174 /* Wait for firmware load to finish. */
1175 status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
1176 if (status != DMUB_STATUS_OK)
1177 DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
1179 /* Init DMCU and ABM if available. */
1181 dmcu->funcs->dmcu_init(dmcu);
1182 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
1185 if (!adev->dm.dc->ctx->dmub_srv)
1186 adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv);
1187 if (!adev->dm.dc->ctx->dmub_srv) {
1188 DRM_ERROR("Couldn't allocate DC DMUB server!\n");
1192 DRM_INFO("DMUB hardware initialized: version=0x%08X\n",
1193 adev->dm.dmcub_fw_version);
1198 static void dm_dmub_hw_resume(struct amdgpu_device *adev)
1200 struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
1201 enum dmub_status status;
1205 /* DMUB isn't supported on the ASIC. */
1209 status = dmub_srv_is_hw_init(dmub_srv, &init);
1210 if (status != DMUB_STATUS_OK)
1211 DRM_WARN("DMUB hardware init check failed: %d\n", status);
1213 if (status == DMUB_STATUS_OK && init) {
1214 /* Wait for firmware load to finish. */
1215 status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
1216 if (status != DMUB_STATUS_OK)
1217 DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
1219 /* Perform the full hardware initialization. */
1220 dm_dmub_hw_init(adev);
1224 static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_addr_space_config *pa_config)
1227 u32 logical_addr_low;
1228 u32 logical_addr_high;
1229 u32 agp_base, agp_bot, agp_top;
1230 PHYSICAL_ADDRESS_LOC page_table_start, page_table_end, page_table_base;
1232 memset(pa_config, 0, sizeof(*pa_config));
1235 agp_bot = adev->gmc.agp_start >> 24;
1236 agp_top = adev->gmc.agp_end >> 24;
1238 /* AGP aperture is disabled */
1239 if (agp_bot == agp_top) {
1240 logical_addr_low = adev->gmc.fb_start >> 18;
1241 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1243 * Raven2 has a HW issue that it is unable to use the vram which
1244 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
1245 * workaround that increase system aperture high address (add 1)
1246 * to get rid of the VM fault and hardware hang.
1248 logical_addr_high = (adev->gmc.fb_end >> 18) + 0x1;
1250 logical_addr_high = adev->gmc.fb_end >> 18;
1252 logical_addr_low = min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18;
1253 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1255 * Raven2 has a HW issue that it is unable to use the vram which
1256 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
1257 * workaround that increase system aperture high address (add 1)
1258 * to get rid of the VM fault and hardware hang.
1260 logical_addr_high = max((adev->gmc.fb_end >> 18) + 0x1, adev->gmc.agp_end >> 18);
1262 logical_addr_high = max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18;
1265 pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
1267 page_table_start.high_part = (u32)(adev->gmc.gart_start >> 44) & 0xF;
1268 page_table_start.low_part = (u32)(adev->gmc.gart_start >> 12);
1269 page_table_end.high_part = (u32)(adev->gmc.gart_end >> 44) & 0xF;
1270 page_table_end.low_part = (u32)(adev->gmc.gart_end >> 12);
1271 page_table_base.high_part = upper_32_bits(pt_base) & 0xF;
1272 page_table_base.low_part = lower_32_bits(pt_base);
1274 pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18;
1275 pa_config->system_aperture.end_addr = (uint64_t)logical_addr_high << 18;
1277 pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24 ;
1278 pa_config->system_aperture.agp_bot = (uint64_t)agp_bot << 24;
1279 pa_config->system_aperture.agp_top = (uint64_t)agp_top << 24;
1281 pa_config->system_aperture.fb_base = adev->gmc.fb_start;
1282 pa_config->system_aperture.fb_offset = adev->vm_manager.vram_base_offset;
1283 pa_config->system_aperture.fb_top = adev->gmc.fb_end;
1285 pa_config->gart_config.page_table_start_addr = page_table_start.quad_part << 12;
1286 pa_config->gart_config.page_table_end_addr = page_table_end.quad_part << 12;
1287 pa_config->gart_config.page_table_base_addr = page_table_base.quad_part;
1289 pa_config->is_hvm_enabled = adev->mode_info.gpu_vm_support;
1293 static void force_connector_state(
1294 struct amdgpu_dm_connector *aconnector,
1295 enum drm_connector_force force_state)
1297 struct drm_connector *connector = &aconnector->base;
1299 mutex_lock(&connector->dev->mode_config.mutex);
1300 aconnector->base.force = force_state;
1301 mutex_unlock(&connector->dev->mode_config.mutex);
1303 mutex_lock(&aconnector->hpd_lock);
1304 drm_kms_helper_connector_hotplug_event(connector);
1305 mutex_unlock(&aconnector->hpd_lock);
1308 static void dm_handle_hpd_rx_offload_work(struct work_struct *work)
1310 struct hpd_rx_irq_offload_work *offload_work;
1311 struct amdgpu_dm_connector *aconnector;
1312 struct dc_link *dc_link;
1313 struct amdgpu_device *adev;
1314 enum dc_connection_type new_connection_type = dc_connection_none;
1315 unsigned long flags;
1316 union test_response test_response;
1318 memset(&test_response, 0, sizeof(test_response));
1320 offload_work = container_of(work, struct hpd_rx_irq_offload_work, work);
1321 aconnector = offload_work->offload_wq->aconnector;
1324 DRM_ERROR("Can't retrieve aconnector in hpd_rx_irq_offload_work");
1328 adev = drm_to_adev(aconnector->base.dev);
1329 dc_link = aconnector->dc_link;
1331 mutex_lock(&aconnector->hpd_lock);
1332 if (!dc_link_detect_connection_type(dc_link, &new_connection_type))
1333 DRM_ERROR("KMS: Failed to detect connector\n");
1334 mutex_unlock(&aconnector->hpd_lock);
1336 if (new_connection_type == dc_connection_none)
1339 if (amdgpu_in_reset(adev))
1342 mutex_lock(&adev->dm.dc_lock);
1343 if (offload_work->data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
1344 dc_link_dp_handle_automated_test(dc_link);
1346 if (aconnector->timing_changed) {
1347 /* force connector disconnect and reconnect */
1348 force_connector_state(aconnector, DRM_FORCE_OFF);
1350 force_connector_state(aconnector, DRM_FORCE_UNSPECIFIED);
1353 test_response.bits.ACK = 1;
1355 core_link_write_dpcd(
1359 sizeof(test_response));
1361 else if ((dc_link->connector_signal != SIGNAL_TYPE_EDP) &&
1362 dc_link_check_link_loss_status(dc_link, &offload_work->data) &&
1363 dc_link_dp_allow_hpd_rx_irq(dc_link)) {
1364 /* offload_work->data is from handle_hpd_rx_irq->
1365 * schedule_hpd_rx_offload_work.this is defer handle
1366 * for hpd short pulse. upon here, link status may be
1367 * changed, need get latest link status from dpcd
1368 * registers. if link status is good, skip run link
1371 union hpd_irq_data irq_data;
1373 memset(&irq_data, 0, sizeof(irq_data));
1375 /* before dc_link_dp_handle_link_loss, allow new link lost handle
1376 * request be added to work queue if link lost at end of dc_link_
1377 * dp_handle_link_loss
1379 spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags);
1380 offload_work->offload_wq->is_handling_link_loss = false;
1381 spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags);
1383 if ((dc_link_dp_read_hpd_rx_irq_data(dc_link, &irq_data) == DC_OK) &&
1384 dc_link_check_link_loss_status(dc_link, &irq_data))
1385 dc_link_dp_handle_link_loss(dc_link);
1387 mutex_unlock(&adev->dm.dc_lock);
1390 kfree(offload_work);
1394 static struct hpd_rx_irq_offload_work_queue *hpd_rx_irq_create_workqueue(struct dc *dc)
1396 int max_caps = dc->caps.max_links;
1398 struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq = NULL;
1400 hpd_rx_offload_wq = kcalloc(max_caps, sizeof(*hpd_rx_offload_wq), GFP_KERNEL);
1402 if (!hpd_rx_offload_wq)
1406 for (i = 0; i < max_caps; i++) {
1407 hpd_rx_offload_wq[i].wq =
1408 create_singlethread_workqueue("amdgpu_dm_hpd_rx_offload_wq");
1410 if (hpd_rx_offload_wq[i].wq == NULL) {
1411 DRM_ERROR("create amdgpu_dm_hpd_rx_offload_wq fail!");
1415 spin_lock_init(&hpd_rx_offload_wq[i].offload_lock);
1418 return hpd_rx_offload_wq;
1421 for (i = 0; i < max_caps; i++) {
1422 if (hpd_rx_offload_wq[i].wq)
1423 destroy_workqueue(hpd_rx_offload_wq[i].wq);
1425 kfree(hpd_rx_offload_wq);
1429 struct amdgpu_stutter_quirk {
1437 static const struct amdgpu_stutter_quirk amdgpu_stutter_quirk_list[] = {
1438 /* https://bugzilla.kernel.org/show_bug.cgi?id=214417 */
1439 { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 },
1443 static bool dm_should_disable_stutter(struct pci_dev *pdev)
1445 const struct amdgpu_stutter_quirk *p = amdgpu_stutter_quirk_list;
1447 while (p && p->chip_device != 0) {
1448 if (pdev->vendor == p->chip_vendor &&
1449 pdev->device == p->chip_device &&
1450 pdev->subsystem_vendor == p->subsys_vendor &&
1451 pdev->subsystem_device == p->subsys_device &&
1452 pdev->revision == p->revision) {
1460 static const struct dmi_system_id hpd_disconnect_quirk_table[] = {
1463 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1464 DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3660"),
1469 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1470 DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3260"),
1475 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1476 DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3460"),
1481 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1482 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower Plus 7010"),
1487 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1488 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower 7010"),
1493 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1494 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF Plus 7010"),
1499 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1500 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF 7010"),
1505 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1506 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro Plus 7010"),
1511 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1512 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro 7010"),
1516 /* TODO: refactor this from a fixed table to a dynamic option */
1519 static void retrieve_dmi_info(struct amdgpu_display_manager *dm)
1521 const struct dmi_system_id *dmi_id;
1523 dm->aux_hpd_discon_quirk = false;
1525 dmi_id = dmi_first_match(hpd_disconnect_quirk_table);
1527 dm->aux_hpd_discon_quirk = true;
1528 DRM_INFO("aux_hpd_discon_quirk attached\n");
1532 static int amdgpu_dm_init(struct amdgpu_device *adev)
1534 struct dc_init_data init_data;
1535 struct dc_callback_init init_params;
1538 adev->dm.ddev = adev_to_drm(adev);
1539 adev->dm.adev = adev;
1541 /* Zero all the fields */
1542 memset(&init_data, 0, sizeof(init_data));
1543 memset(&init_params, 0, sizeof(init_params));
1545 mutex_init(&adev->dm.dpia_aux_lock);
1546 mutex_init(&adev->dm.dc_lock);
1547 mutex_init(&adev->dm.audio_lock);
1549 if(amdgpu_dm_irq_init(adev)) {
1550 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
1554 init_data.asic_id.chip_family = adev->family;
1556 init_data.asic_id.pci_revision_id = adev->pdev->revision;
1557 init_data.asic_id.hw_internal_rev = adev->external_rev_id;
1558 init_data.asic_id.chip_id = adev->pdev->device;
1560 init_data.asic_id.vram_width = adev->gmc.vram_width;
1561 /* TODO: initialize init_data.asic_id.vram_type here!!!! */
1562 init_data.asic_id.atombios_base_address =
1563 adev->mode_info.atom_context->bios;
1565 init_data.driver = adev;
1567 adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
1569 if (!adev->dm.cgs_device) {
1570 DRM_ERROR("amdgpu: failed to create cgs device.\n");
1574 init_data.cgs_device = adev->dm.cgs_device;
1576 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
1578 switch (adev->ip_versions[DCE_HWIP][0]) {
1579 case IP_VERSION(2, 1, 0):
1580 switch (adev->dm.dmcub_fw_version) {
1581 case 0: /* development */
1582 case 0x1: /* linux-firmware.git hash 6d9f399 */
1583 case 0x01000000: /* linux-firmware.git hash 9a0b0f4 */
1584 init_data.flags.disable_dmcu = false;
1587 init_data.flags.disable_dmcu = true;
1590 case IP_VERSION(2, 0, 3):
1591 init_data.flags.disable_dmcu = true;
1597 switch (adev->asic_type) {
1600 init_data.flags.gpu_vm_support = true;
1603 switch (adev->ip_versions[DCE_HWIP][0]) {
1604 case IP_VERSION(1, 0, 0):
1605 case IP_VERSION(1, 0, 1):
1606 /* enable S/G on PCO and RV2 */
1607 if ((adev->apu_flags & AMD_APU_IS_RAVEN2) ||
1608 (adev->apu_flags & AMD_APU_IS_PICASSO))
1609 init_data.flags.gpu_vm_support = true;
1611 case IP_VERSION(2, 1, 0):
1612 case IP_VERSION(3, 0, 1):
1613 case IP_VERSION(3, 1, 2):
1614 case IP_VERSION(3, 1, 3):
1615 case IP_VERSION(3, 1, 4):
1616 case IP_VERSION(3, 1, 5):
1617 case IP_VERSION(3, 1, 6):
1618 init_data.flags.gpu_vm_support = true;
1625 if (init_data.flags.gpu_vm_support &&
1626 (amdgpu_sg_display == 0))
1627 init_data.flags.gpu_vm_support = false;
1629 if (init_data.flags.gpu_vm_support)
1630 adev->mode_info.gpu_vm_support = true;
1632 if (amdgpu_dc_feature_mask & DC_FBC_MASK)
1633 init_data.flags.fbc_support = true;
1635 if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK)
1636 init_data.flags.multi_mon_pp_mclk_switch = true;
1638 if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK)
1639 init_data.flags.disable_fractional_pwm = true;
1641 if (amdgpu_dc_feature_mask & DC_EDP_NO_POWER_SEQUENCING)
1642 init_data.flags.edp_no_power_sequencing = true;
1644 if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP1_4A)
1645 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP1_4A = true;
1646 if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP2_0)
1647 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP2_0 = true;
1649 /* Disable SubVP + DRR config by default */
1650 init_data.flags.disable_subvp_drr = true;
1651 if (amdgpu_dc_feature_mask & DC_ENABLE_SUBVP_DRR)
1652 init_data.flags.disable_subvp_drr = false;
1654 init_data.flags.seamless_boot_edp_requested = false;
1656 if (check_seamless_boot_capability(adev)) {
1657 init_data.flags.seamless_boot_edp_requested = true;
1658 init_data.flags.allow_seamless_boot_optimization = true;
1659 DRM_INFO("Seamless boot condition check passed\n");
1662 init_data.flags.enable_mipi_converter_optimization = true;
1664 init_data.dcn_reg_offsets = adev->reg_offset[DCE_HWIP][0];
1665 init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0];
1667 INIT_LIST_HEAD(&adev->dm.da_list);
1669 retrieve_dmi_info(&adev->dm);
1671 /* Display Core create. */
1672 adev->dm.dc = dc_create(&init_data);
1675 DRM_INFO("Display Core initialized with v%s!\n", DC_VER);
1677 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER);
1681 if (amdgpu_dc_debug_mask & DC_DISABLE_PIPE_SPLIT) {
1682 adev->dm.dc->debug.force_single_disp_pipe_split = false;
1683 adev->dm.dc->debug.pipe_split_policy = MPC_SPLIT_AVOID;
1686 if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY)
1687 adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;
1688 if (dm_should_disable_stutter(adev->pdev))
1689 adev->dm.dc->debug.disable_stutter = true;
1691 if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER)
1692 adev->dm.dc->debug.disable_stutter = true;
1694 if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) {
1695 adev->dm.dc->debug.disable_dsc = true;
1698 if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING)
1699 adev->dm.dc->debug.disable_clock_gate = true;
1701 if (amdgpu_dc_debug_mask & DC_FORCE_SUBVP_MCLK_SWITCH)
1702 adev->dm.dc->debug.force_subvp_mclk_switch = true;
1704 adev->dm.dc->debug.visual_confirm = amdgpu_dc_visual_confirm;
1706 /* TODO: Remove after DP2 receiver gets proper support of Cable ID feature */
1707 adev->dm.dc->debug.ignore_cable_id = true;
1709 /* TODO: There is a new drm mst change where the freedom of
1710 * vc_next_start_slot update is revoked/moved into drm, instead of in
1711 * driver. This forces us to make sure to get vc_next_start_slot updated
1712 * in drm function each time without considering if mst_state is active
1713 * or not. Otherwise, next time hotplug will give wrong start_slot
1714 * number. We are implementing a temporary solution to even notify drm
1715 * mst deallocation when link is no longer of MST type when uncommitting
1716 * the stream so we will have more time to work on a proper solution.
1717 * Ideally when dm_helpers_dp_mst_stop_top_mgr message is triggered, we
1718 * should notify drm to do a complete "reset" of its states and stop
1719 * calling further drm mst functions when link is no longer of an MST
1720 * type. This could happen when we unplug an MST hubs/displays. When
1721 * uncommit stream comes later after unplug, we should just reset
1722 * hardware states only.
1724 adev->dm.dc->debug.temp_mst_deallocation_sequence = true;
1726 if (adev->dm.dc->caps.dp_hdmi21_pcon_support)
1727 DRM_INFO("DP-HDMI FRL PCON supported\n");
1729 r = dm_dmub_hw_init(adev);
1731 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
1735 dc_hardware_init(adev->dm.dc);
1737 adev->dm.hpd_rx_offload_wq = hpd_rx_irq_create_workqueue(adev->dm.dc);
1738 if (!adev->dm.hpd_rx_offload_wq) {
1739 DRM_ERROR("amdgpu: failed to create hpd rx offload workqueue.\n");
1743 if ((adev->flags & AMD_IS_APU) && (adev->asic_type >= CHIP_CARRIZO)) {
1744 struct dc_phy_addr_space_config pa_config;
1746 mmhub_read_system_context(adev, &pa_config);
1748 // Call the DC init_memory func
1749 dc_setup_system_context(adev->dm.dc, &pa_config);
1752 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
1753 if (!adev->dm.freesync_module) {
1755 "amdgpu: failed to initialize freesync_module.\n");
1757 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
1758 adev->dm.freesync_module);
1760 amdgpu_dm_init_color_mod();
1762 if (adev->dm.dc->caps.max_links > 0) {
1763 adev->dm.vblank_control_workqueue =
1764 create_singlethread_workqueue("dm_vblank_control_workqueue");
1765 if (!adev->dm.vblank_control_workqueue)
1766 DRM_ERROR("amdgpu: failed to initialize vblank_workqueue.\n");
1769 if (adev->dm.dc->caps.max_links > 0 && adev->family >= AMDGPU_FAMILY_RV) {
1770 adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc);
1772 if (!adev->dm.hdcp_workqueue)
1773 DRM_ERROR("amdgpu: failed to initialize hdcp_workqueue.\n");
1775 DRM_DEBUG_DRIVER("amdgpu: hdcp_workqueue init done %p.\n", adev->dm.hdcp_workqueue);
1777 dc_init_callbacks(adev->dm.dc, &init_params);
1779 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
1780 adev->dm.secure_display_ctxs = amdgpu_dm_crtc_secure_display_create_contexts(adev);
1781 if (!adev->dm.secure_display_ctxs) {
1782 DRM_ERROR("amdgpu: failed to initialize secure_display_ctxs.\n");
1785 if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
1786 init_completion(&adev->dm.dmub_aux_transfer_done);
1787 adev->dm.dmub_notify = kzalloc(sizeof(struct dmub_notification), GFP_KERNEL);
1788 if (!adev->dm.dmub_notify) {
1789 DRM_INFO("amdgpu: fail to allocate adev->dm.dmub_notify");
1793 adev->dm.delayed_hpd_wq = create_singlethread_workqueue("amdgpu_dm_hpd_wq");
1794 if (!adev->dm.delayed_hpd_wq) {
1795 DRM_ERROR("amdgpu: failed to create hpd offload workqueue.\n");
1799 amdgpu_dm_outbox_init(adev);
1800 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_AUX_REPLY,
1801 dmub_aux_setconfig_callback, false)) {
1802 DRM_ERROR("amdgpu: fail to register dmub aux callback");
1805 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD, dmub_hpd_callback, true)) {
1806 DRM_ERROR("amdgpu: fail to register dmub hpd callback");
1809 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD_IRQ, dmub_hpd_callback, true)) {
1810 DRM_ERROR("amdgpu: fail to register dmub hpd callback");
1815 /* Enable outbox notification only after IRQ handlers are registered and DMUB is alive.
1816 * It is expected that DMUB will resend any pending notifications at this point, for
1817 * example HPD from DPIA.
1819 if (dc_is_dmub_outbox_supported(adev->dm.dc))
1820 dc_enable_dmub_outbox(adev->dm.dc);
1822 if (amdgpu_dm_initialize_drm_device(adev)) {
1824 "amdgpu: failed to initialize sw for display support.\n");
1828 /* create fake encoders for MST */
1829 dm_dp_create_fake_mst_encoders(adev);
1831 /* TODO: Add_display_info? */
1833 /* TODO use dynamic cursor width */
1834 adev_to_drm(adev)->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
1835 adev_to_drm(adev)->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
1837 if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) {
1839 "amdgpu: failed to initialize sw for display support.\n");
1844 DRM_DEBUG_DRIVER("KMS initialized.\n");
1848 amdgpu_dm_fini(adev);
1853 static int amdgpu_dm_early_fini(void *handle)
1855 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1857 amdgpu_dm_audio_fini(adev);
1862 static void amdgpu_dm_fini(struct amdgpu_device *adev)
1866 if (adev->dm.vblank_control_workqueue) {
1867 destroy_workqueue(adev->dm.vblank_control_workqueue);
1868 adev->dm.vblank_control_workqueue = NULL;
1871 amdgpu_dm_destroy_drm_device(&adev->dm);
1873 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
1874 if (adev->dm.secure_display_ctxs) {
1875 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1876 if (adev->dm.secure_display_ctxs[i].crtc) {
1877 flush_work(&adev->dm.secure_display_ctxs[i].notify_ta_work);
1878 flush_work(&adev->dm.secure_display_ctxs[i].forward_roi_work);
1881 kfree(adev->dm.secure_display_ctxs);
1882 adev->dm.secure_display_ctxs = NULL;
1885 if (adev->dm.hdcp_workqueue) {
1886 hdcp_destroy(&adev->dev->kobj, adev->dm.hdcp_workqueue);
1887 adev->dm.hdcp_workqueue = NULL;
1891 dc_deinit_callbacks(adev->dm.dc);
1893 dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv);
1895 if (dc_enable_dmub_notifications(adev->dm.dc)) {
1896 kfree(adev->dm.dmub_notify);
1897 adev->dm.dmub_notify = NULL;
1898 destroy_workqueue(adev->dm.delayed_hpd_wq);
1899 adev->dm.delayed_hpd_wq = NULL;
1902 if (adev->dm.dmub_bo)
1903 amdgpu_bo_free_kernel(&adev->dm.dmub_bo,
1904 &adev->dm.dmub_bo_gpu_addr,
1905 &adev->dm.dmub_bo_cpu_addr);
1907 if (adev->dm.hpd_rx_offload_wq) {
1908 for (i = 0; i < adev->dm.dc->caps.max_links; i++) {
1909 if (adev->dm.hpd_rx_offload_wq[i].wq) {
1910 destroy_workqueue(adev->dm.hpd_rx_offload_wq[i].wq);
1911 adev->dm.hpd_rx_offload_wq[i].wq = NULL;
1915 kfree(adev->dm.hpd_rx_offload_wq);
1916 adev->dm.hpd_rx_offload_wq = NULL;
1919 /* DC Destroy TODO: Replace destroy DAL */
1921 dc_destroy(&adev->dm.dc);
1923 * TODO: pageflip, vlank interrupt
1925 * amdgpu_dm_irq_fini(adev);
1928 if (adev->dm.cgs_device) {
1929 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
1930 adev->dm.cgs_device = NULL;
1932 if (adev->dm.freesync_module) {
1933 mod_freesync_destroy(adev->dm.freesync_module);
1934 adev->dm.freesync_module = NULL;
1937 mutex_destroy(&adev->dm.audio_lock);
1938 mutex_destroy(&adev->dm.dc_lock);
1939 mutex_destroy(&adev->dm.dpia_aux_lock);
1944 static int load_dmcu_fw(struct amdgpu_device *adev)
1946 const char *fw_name_dmcu = NULL;
1948 const struct dmcu_firmware_header_v1_0 *hdr;
1950 switch(adev->asic_type) {
1951 #if defined(CONFIG_DRM_AMD_DC_SI)
1966 case CHIP_POLARIS11:
1967 case CHIP_POLARIS10:
1968 case CHIP_POLARIS12:
1975 fw_name_dmcu = FIRMWARE_NAVI12_DMCU;
1978 if (ASICREV_IS_PICASSO(adev->external_rev_id))
1979 fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
1980 else if (ASICREV_IS_RAVEN2(adev->external_rev_id))
1981 fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
1986 switch (adev->ip_versions[DCE_HWIP][0]) {
1987 case IP_VERSION(2, 0, 2):
1988 case IP_VERSION(2, 0, 3):
1989 case IP_VERSION(2, 0, 0):
1990 case IP_VERSION(2, 1, 0):
1991 case IP_VERSION(3, 0, 0):
1992 case IP_VERSION(3, 0, 2):
1993 case IP_VERSION(3, 0, 3):
1994 case IP_VERSION(3, 0, 1):
1995 case IP_VERSION(3, 1, 2):
1996 case IP_VERSION(3, 1, 3):
1997 case IP_VERSION(3, 1, 4):
1998 case IP_VERSION(3, 1, 5):
1999 case IP_VERSION(3, 1, 6):
2000 case IP_VERSION(3, 2, 0):
2001 case IP_VERSION(3, 2, 1):
2006 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
2010 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
2011 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n");
2015 r = amdgpu_ucode_request(adev, &adev->dm.fw_dmcu, fw_name_dmcu);
2017 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */
2018 DRM_DEBUG_KMS("dm: DMCU firmware not found\n");
2019 adev->dm.fw_dmcu = NULL;
2023 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n",
2025 amdgpu_ucode_release(&adev->dm.fw_dmcu);
2029 hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data;
2030 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM;
2031 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu;
2032 adev->firmware.fw_size +=
2033 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
2035 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV;
2036 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu;
2037 adev->firmware.fw_size +=
2038 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
2040 adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version);
2042 DRM_DEBUG_KMS("PSP loading DMCU firmware\n");
2047 static uint32_t amdgpu_dm_dmub_reg_read(void *ctx, uint32_t address)
2049 struct amdgpu_device *adev = ctx;
2051 return dm_read_reg(adev->dm.dc->ctx, address);
2054 static void amdgpu_dm_dmub_reg_write(void *ctx, uint32_t address,
2057 struct amdgpu_device *adev = ctx;
2059 return dm_write_reg(adev->dm.dc->ctx, address, value);
2062 static int dm_dmub_sw_init(struct amdgpu_device *adev)
2064 struct dmub_srv_create_params create_params;
2065 struct dmub_srv_region_params region_params;
2066 struct dmub_srv_region_info region_info;
2067 struct dmub_srv_fb_params fb_params;
2068 struct dmub_srv_fb_info *fb_info;
2069 struct dmub_srv *dmub_srv;
2070 const struct dmcub_firmware_header_v1_0 *hdr;
2071 enum dmub_asic dmub_asic;
2072 enum dmub_status status;
2075 switch (adev->ip_versions[DCE_HWIP][0]) {
2076 case IP_VERSION(2, 1, 0):
2077 dmub_asic = DMUB_ASIC_DCN21;
2079 case IP_VERSION(3, 0, 0):
2080 dmub_asic = DMUB_ASIC_DCN30;
2082 case IP_VERSION(3, 0, 1):
2083 dmub_asic = DMUB_ASIC_DCN301;
2085 case IP_VERSION(3, 0, 2):
2086 dmub_asic = DMUB_ASIC_DCN302;
2088 case IP_VERSION(3, 0, 3):
2089 dmub_asic = DMUB_ASIC_DCN303;
2091 case IP_VERSION(3, 1, 2):
2092 case IP_VERSION(3, 1, 3):
2093 dmub_asic = (adev->external_rev_id == YELLOW_CARP_B0) ? DMUB_ASIC_DCN31B : DMUB_ASIC_DCN31;
2095 case IP_VERSION(3, 1, 4):
2096 dmub_asic = DMUB_ASIC_DCN314;
2098 case IP_VERSION(3, 1, 5):
2099 dmub_asic = DMUB_ASIC_DCN315;
2101 case IP_VERSION(3, 1, 6):
2102 dmub_asic = DMUB_ASIC_DCN316;
2104 case IP_VERSION(3, 2, 0):
2105 dmub_asic = DMUB_ASIC_DCN32;
2107 case IP_VERSION(3, 2, 1):
2108 dmub_asic = DMUB_ASIC_DCN321;
2111 /* ASIC doesn't support DMUB. */
2115 hdr = (const struct dmcub_firmware_header_v1_0 *)adev->dm.dmub_fw->data;
2116 adev->dm.dmcub_fw_version = le32_to_cpu(hdr->header.ucode_version);
2118 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
2119 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].ucode_id =
2120 AMDGPU_UCODE_ID_DMCUB;
2121 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].fw =
2123 adev->firmware.fw_size +=
2124 ALIGN(le32_to_cpu(hdr->inst_const_bytes), PAGE_SIZE);
2126 DRM_INFO("Loading DMUB firmware via PSP: version=0x%08X\n",
2127 adev->dm.dmcub_fw_version);
2131 adev->dm.dmub_srv = kzalloc(sizeof(*adev->dm.dmub_srv), GFP_KERNEL);
2132 dmub_srv = adev->dm.dmub_srv;
2135 DRM_ERROR("Failed to allocate DMUB service!\n");
2139 memset(&create_params, 0, sizeof(create_params));
2140 create_params.user_ctx = adev;
2141 create_params.funcs.reg_read = amdgpu_dm_dmub_reg_read;
2142 create_params.funcs.reg_write = amdgpu_dm_dmub_reg_write;
2143 create_params.asic = dmub_asic;
2145 /* Create the DMUB service. */
2146 status = dmub_srv_create(dmub_srv, &create_params);
2147 if (status != DMUB_STATUS_OK) {
2148 DRM_ERROR("Error creating DMUB service: %d\n", status);
2152 /* Calculate the size of all the regions for the DMUB service. */
2153 memset(®ion_params, 0, sizeof(region_params));
2155 region_params.inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
2156 PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
2157 region_params.bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
2158 region_params.vbios_size = adev->bios_size;
2159 region_params.fw_bss_data = region_params.bss_data_size ?
2160 adev->dm.dmub_fw->data +
2161 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
2162 le32_to_cpu(hdr->inst_const_bytes) : NULL;
2163 region_params.fw_inst_const =
2164 adev->dm.dmub_fw->data +
2165 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
2168 status = dmub_srv_calc_region_info(dmub_srv, ®ion_params,
2171 if (status != DMUB_STATUS_OK) {
2172 DRM_ERROR("Error calculating DMUB region info: %d\n", status);
2177 * Allocate a framebuffer based on the total size of all the regions.
2178 * TODO: Move this into GART.
2180 r = amdgpu_bo_create_kernel(adev, region_info.fb_size, PAGE_SIZE,
2181 AMDGPU_GEM_DOMAIN_VRAM |
2182 AMDGPU_GEM_DOMAIN_GTT,
2184 &adev->dm.dmub_bo_gpu_addr,
2185 &adev->dm.dmub_bo_cpu_addr);
2189 /* Rebase the regions on the framebuffer address. */
2190 memset(&fb_params, 0, sizeof(fb_params));
2191 fb_params.cpu_addr = adev->dm.dmub_bo_cpu_addr;
2192 fb_params.gpu_addr = adev->dm.dmub_bo_gpu_addr;
2193 fb_params.region_info = ®ion_info;
2195 adev->dm.dmub_fb_info =
2196 kzalloc(sizeof(*adev->dm.dmub_fb_info), GFP_KERNEL);
2197 fb_info = adev->dm.dmub_fb_info;
2201 "Failed to allocate framebuffer info for DMUB service!\n");
2205 status = dmub_srv_calc_fb_info(dmub_srv, &fb_params, fb_info);
2206 if (status != DMUB_STATUS_OK) {
2207 DRM_ERROR("Error calculating DMUB FB info: %d\n", status);
2214 static int dm_sw_init(void *handle)
2216 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2219 r = dm_dmub_sw_init(adev);
2223 return load_dmcu_fw(adev);
2226 static int dm_sw_fini(void *handle)
2228 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2230 kfree(adev->dm.dmub_fb_info);
2231 adev->dm.dmub_fb_info = NULL;
2233 if (adev->dm.dmub_srv) {
2234 dmub_srv_destroy(adev->dm.dmub_srv);
2235 adev->dm.dmub_srv = NULL;
2238 amdgpu_ucode_release(&adev->dm.dmub_fw);
2239 amdgpu_ucode_release(&adev->dm.fw_dmcu);
2244 static int detect_mst_link_for_all_connectors(struct drm_device *dev)
2246 struct amdgpu_dm_connector *aconnector;
2247 struct drm_connector *connector;
2248 struct drm_connector_list_iter iter;
2251 drm_connector_list_iter_begin(dev, &iter);
2252 drm_for_each_connector_iter(connector, &iter) {
2253 aconnector = to_amdgpu_dm_connector(connector);
2254 if (aconnector->dc_link->type == dc_connection_mst_branch &&
2255 aconnector->mst_mgr.aux) {
2256 DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
2258 aconnector->base.base.id);
2260 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
2262 DRM_ERROR("DM_MST: Failed to start MST\n");
2263 aconnector->dc_link->type =
2264 dc_connection_single;
2265 ret = dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,
2266 aconnector->dc_link);
2271 drm_connector_list_iter_end(&iter);
2276 static int dm_late_init(void *handle)
2278 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2280 struct dmcu_iram_parameters params;
2281 unsigned int linear_lut[16];
2283 struct dmcu *dmcu = NULL;
2285 dmcu = adev->dm.dc->res_pool->dmcu;
2287 for (i = 0; i < 16; i++)
2288 linear_lut[i] = 0xFFFF * i / 15;
2291 params.backlight_ramping_override = false;
2292 params.backlight_ramping_start = 0xCCCC;
2293 params.backlight_ramping_reduction = 0xCCCCCCCC;
2294 params.backlight_lut_array_size = 16;
2295 params.backlight_lut_array = linear_lut;
2297 /* Min backlight level after ABM reduction, Don't allow below 1%
2298 * 0xFFFF x 0.01 = 0x28F
2300 params.min_abm_backlight = 0x28F;
2301 /* In the case where abm is implemented on dmcub,
2302 * dmcu object will be null.
2303 * ABM 2.4 and up are implemented on dmcub.
2306 if (!dmcu_load_iram(dmcu, params))
2308 } else if (adev->dm.dc->ctx->dmub_srv) {
2309 struct dc_link *edp_links[MAX_NUM_EDP];
2312 dc_get_edp_links(adev->dm.dc, edp_links, &edp_num);
2313 for (i = 0; i < edp_num; i++) {
2314 if (!dmub_init_abm_config(adev->dm.dc->res_pool, params, i))
2319 return detect_mst_link_for_all_connectors(adev_to_drm(adev));
2322 static void s3_handle_mst(struct drm_device *dev, bool suspend)
2324 struct amdgpu_dm_connector *aconnector;
2325 struct drm_connector *connector;
2326 struct drm_connector_list_iter iter;
2327 struct drm_dp_mst_topology_mgr *mgr;
2329 bool need_hotplug = false;
2331 drm_connector_list_iter_begin(dev, &iter);
2332 drm_for_each_connector_iter(connector, &iter) {
2333 aconnector = to_amdgpu_dm_connector(connector);
2334 if (aconnector->dc_link->type != dc_connection_mst_branch ||
2335 aconnector->mst_root)
2338 mgr = &aconnector->mst_mgr;
2341 drm_dp_mst_topology_mgr_suspend(mgr);
2343 /* if extended timeout is supported in hardware,
2344 * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer
2345 * CTS 4.2.1.1 regression introduced by CTS specs requirement update.
2347 try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD);
2348 if (!dp_is_lttpr_present(aconnector->dc_link))
2349 try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
2351 ret = drm_dp_mst_topology_mgr_resume(mgr, true);
2353 dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,
2354 aconnector->dc_link);
2355 need_hotplug = true;
2359 drm_connector_list_iter_end(&iter);
2362 drm_kms_helper_hotplug_event(dev);
2365 static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev)
2369 /* This interface is for dGPU Navi1x.Linux dc-pplib interface depends
2370 * on window driver dc implementation.
2371 * For Navi1x, clock settings of dcn watermarks are fixed. the settings
2372 * should be passed to smu during boot up and resume from s3.
2373 * boot up: dc calculate dcn watermark clock settings within dc_create,
2374 * dcn20_resource_construct
2375 * then call pplib functions below to pass the settings to smu:
2376 * smu_set_watermarks_for_clock_ranges
2377 * smu_set_watermarks_table
2378 * navi10_set_watermarks_table
2379 * smu_write_watermarks_table
2381 * For Renoir, clock settings of dcn watermark are also fixed values.
2382 * dc has implemented different flow for window driver:
2383 * dc_hardware_init / dc_set_power_state
2388 * smu_set_watermarks_for_clock_ranges
2389 * renoir_set_watermarks_table
2390 * smu_write_watermarks_table
2393 * dc_hardware_init -> amdgpu_dm_init
2394 * dc_set_power_state --> dm_resume
2396 * therefore, this function apply to navi10/12/14 but not Renoir
2399 switch (adev->ip_versions[DCE_HWIP][0]) {
2400 case IP_VERSION(2, 0, 2):
2401 case IP_VERSION(2, 0, 0):
2407 ret = amdgpu_dpm_write_watermarks_table(adev);
2409 DRM_ERROR("Failed to update WMTABLE!\n");
2417 * dm_hw_init() - Initialize DC device
2418 * @handle: The base driver device containing the amdgpu_dm device.
2420 * Initialize the &struct amdgpu_display_manager device. This involves calling
2421 * the initializers of each DM component, then populating the struct with them.
2423 * Although the function implies hardware initialization, both hardware and
2424 * software are initialized here. Splitting them out to their relevant init
2425 * hooks is a future TODO item.
2427 * Some notable things that are initialized here:
2429 * - Display Core, both software and hardware
2430 * - DC modules that we need (freesync and color management)
2431 * - DRM software states
2432 * - Interrupt sources and handlers
2434 * - Debug FS entries, if enabled
2436 static int dm_hw_init(void *handle)
2438 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2439 /* Create DAL display manager */
2440 amdgpu_dm_init(adev);
2441 amdgpu_dm_hpd_init(adev);
2447 * dm_hw_fini() - Teardown DC device
2448 * @handle: The base driver device containing the amdgpu_dm device.
2450 * Teardown components within &struct amdgpu_display_manager that require
2451 * cleanup. This involves cleaning up the DRM device, DC, and any modules that
2452 * were loaded. Also flush IRQ workqueues and disable them.
2454 static int dm_hw_fini(void *handle)
2456 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2458 amdgpu_dm_hpd_fini(adev);
2460 amdgpu_dm_irq_fini(adev);
2461 amdgpu_dm_fini(adev);
2466 static void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev,
2467 struct dc_state *state, bool enable)
2469 enum dc_irq_source irq_source;
2470 struct amdgpu_crtc *acrtc;
2474 for (i = 0; i < state->stream_count; i++) {
2475 acrtc = get_crtc_by_otg_inst(
2476 adev, state->stream_status[i].primary_otg_inst);
2478 if (acrtc && state->stream_status[i].plane_count != 0) {
2479 irq_source = IRQ_TYPE_PFLIP + acrtc->otg_inst;
2480 rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
2481 DRM_DEBUG_VBL("crtc %d - vupdate irq %sabling: r=%d\n",
2482 acrtc->crtc_id, enable ? "en" : "dis", rc);
2484 DRM_WARN("Failed to %s pflip interrupts\n",
2485 enable ? "enable" : "disable");
2488 rc = amdgpu_dm_crtc_enable_vblank(&acrtc->base);
2490 DRM_WARN("Failed to enable vblank interrupts\n");
2492 amdgpu_dm_crtc_disable_vblank(&acrtc->base);
2500 static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc)
2502 struct dc_state *context = NULL;
2503 enum dc_status res = DC_ERROR_UNEXPECTED;
2505 struct dc_stream_state *del_streams[MAX_PIPES];
2506 int del_streams_count = 0;
2508 memset(del_streams, 0, sizeof(del_streams));
2510 context = dc_create_state(dc);
2511 if (context == NULL)
2512 goto context_alloc_fail;
2514 dc_resource_state_copy_construct_current(dc, context);
2516 /* First remove from context all streams */
2517 for (i = 0; i < context->stream_count; i++) {
2518 struct dc_stream_state *stream = context->streams[i];
2520 del_streams[del_streams_count++] = stream;
2523 /* Remove all planes for removed streams and then remove the streams */
2524 for (i = 0; i < del_streams_count; i++) {
2525 if (!dc_rem_all_planes_for_stream(dc, del_streams[i], context)) {
2526 res = DC_FAIL_DETACH_SURFACES;
2530 res = dc_remove_stream_from_ctx(dc, context, del_streams[i]);
2535 res = dc_commit_streams(dc, context->streams, context->stream_count);
2538 dc_release_state(context);
2544 static void hpd_rx_irq_work_suspend(struct amdgpu_display_manager *dm)
2548 if (dm->hpd_rx_offload_wq) {
2549 for (i = 0; i < dm->dc->caps.max_links; i++)
2550 flush_workqueue(dm->hpd_rx_offload_wq[i].wq);
2554 static int dm_suspend(void *handle)
2556 struct amdgpu_device *adev = handle;
2557 struct amdgpu_display_manager *dm = &adev->dm;
2560 if (amdgpu_in_reset(adev)) {
2561 mutex_lock(&dm->dc_lock);
2563 dc_allow_idle_optimizations(adev->dm.dc, false);
2565 dm->cached_dc_state = dc_copy_state(dm->dc->current_state);
2567 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false);
2569 amdgpu_dm_commit_zero_streams(dm->dc);
2571 amdgpu_dm_irq_suspend(adev);
2573 hpd_rx_irq_work_suspend(dm);
2578 WARN_ON(adev->dm.cached_state);
2579 adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev));
2581 s3_handle_mst(adev_to_drm(adev), true);
2583 amdgpu_dm_irq_suspend(adev);
2585 hpd_rx_irq_work_suspend(dm);
2587 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
2592 struct amdgpu_dm_connector *
2593 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
2594 struct drm_crtc *crtc)
2597 struct drm_connector_state *new_con_state;
2598 struct drm_connector *connector;
2599 struct drm_crtc *crtc_from_state;
2601 for_each_new_connector_in_state(state, connector, new_con_state, i) {
2602 crtc_from_state = new_con_state->crtc;
2604 if (crtc_from_state == crtc)
2605 return to_amdgpu_dm_connector(connector);
2611 static void emulated_link_detect(struct dc_link *link)
2613 struct dc_sink_init_data sink_init_data = { 0 };
2614 struct display_sink_capability sink_caps = { 0 };
2615 enum dc_edid_status edid_status;
2616 struct dc_context *dc_ctx = link->ctx;
2617 struct dc_sink *sink = NULL;
2618 struct dc_sink *prev_sink = NULL;
2620 link->type = dc_connection_none;
2621 prev_sink = link->local_sink;
2624 dc_sink_release(prev_sink);
2626 switch (link->connector_signal) {
2627 case SIGNAL_TYPE_HDMI_TYPE_A: {
2628 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2629 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
2633 case SIGNAL_TYPE_DVI_SINGLE_LINK: {
2634 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2635 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
2639 case SIGNAL_TYPE_DVI_DUAL_LINK: {
2640 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2641 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
2645 case SIGNAL_TYPE_LVDS: {
2646 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2647 sink_caps.signal = SIGNAL_TYPE_LVDS;
2651 case SIGNAL_TYPE_EDP: {
2652 sink_caps.transaction_type =
2653 DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
2654 sink_caps.signal = SIGNAL_TYPE_EDP;
2658 case SIGNAL_TYPE_DISPLAY_PORT: {
2659 sink_caps.transaction_type =
2660 DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
2661 sink_caps.signal = SIGNAL_TYPE_VIRTUAL;
2666 DC_ERROR("Invalid connector type! signal:%d\n",
2667 link->connector_signal);
2671 sink_init_data.link = link;
2672 sink_init_data.sink_signal = sink_caps.signal;
2674 sink = dc_sink_create(&sink_init_data);
2676 DC_ERROR("Failed to create sink!\n");
2680 /* dc_sink_create returns a new reference */
2681 link->local_sink = sink;
2683 edid_status = dm_helpers_read_local_edid(
2688 if (edid_status != EDID_OK)
2689 DC_ERROR("Failed to read EDID");
2693 static void dm_gpureset_commit_state(struct dc_state *dc_state,
2694 struct amdgpu_display_manager *dm)
2697 struct dc_surface_update surface_updates[MAX_SURFACES];
2698 struct dc_plane_info plane_infos[MAX_SURFACES];
2699 struct dc_scaling_info scaling_infos[MAX_SURFACES];
2700 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
2701 struct dc_stream_update stream_update;
2705 bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
2708 dm_error("Failed to allocate update bundle\n");
2712 for (k = 0; k < dc_state->stream_count; k++) {
2713 bundle->stream_update.stream = dc_state->streams[k];
2715 for (m = 0; m < dc_state->stream_status->plane_count; m++) {
2716 bundle->surface_updates[m].surface =
2717 dc_state->stream_status->plane_states[m];
2718 bundle->surface_updates[m].surface->force_full_update =
2722 update_planes_and_stream_adapter(dm->dc,
2724 dc_state->stream_status->plane_count,
2725 dc_state->streams[k],
2726 &bundle->stream_update,
2727 bundle->surface_updates);
2736 static int dm_resume(void *handle)
2738 struct amdgpu_device *adev = handle;
2739 struct drm_device *ddev = adev_to_drm(adev);
2740 struct amdgpu_display_manager *dm = &adev->dm;
2741 struct amdgpu_dm_connector *aconnector;
2742 struct drm_connector *connector;
2743 struct drm_connector_list_iter iter;
2744 struct drm_crtc *crtc;
2745 struct drm_crtc_state *new_crtc_state;
2746 struct dm_crtc_state *dm_new_crtc_state;
2747 struct drm_plane *plane;
2748 struct drm_plane_state *new_plane_state;
2749 struct dm_plane_state *dm_new_plane_state;
2750 struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state);
2751 enum dc_connection_type new_connection_type = dc_connection_none;
2752 struct dc_state *dc_state;
2755 if (amdgpu_in_reset(adev)) {
2756 dc_state = dm->cached_dc_state;
2759 * The dc->current_state is backed up into dm->cached_dc_state
2760 * before we commit 0 streams.
2762 * DC will clear link encoder assignments on the real state
2763 * but the changes won't propagate over to the copy we made
2764 * before the 0 streams commit.
2766 * DC expects that link encoder assignments are *not* valid
2767 * when committing a state, so as a workaround we can copy
2768 * off of the current state.
2770 * We lose the previous assignments, but we had already
2771 * commit 0 streams anyway.
2773 link_enc_cfg_copy(adev->dm.dc->current_state, dc_state);
2775 r = dm_dmub_hw_init(adev);
2777 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
2779 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
2782 amdgpu_dm_irq_resume_early(adev);
2784 for (i = 0; i < dc_state->stream_count; i++) {
2785 dc_state->streams[i]->mode_changed = true;
2786 for (j = 0; j < dc_state->stream_status[i].plane_count; j++) {
2787 dc_state->stream_status[i].plane_states[j]->update_flags.raw
2792 if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
2793 amdgpu_dm_outbox_init(adev);
2794 dc_enable_dmub_outbox(adev->dm.dc);
2797 WARN_ON(!dc_commit_streams(dm->dc, dc_state->streams, dc_state->stream_count));
2799 dm_gpureset_commit_state(dm->cached_dc_state, dm);
2801 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, true);
2803 dc_release_state(dm->cached_dc_state);
2804 dm->cached_dc_state = NULL;
2806 amdgpu_dm_irq_resume_late(adev);
2808 mutex_unlock(&dm->dc_lock);
2812 /* Recreate dc_state - DC invalidates it when setting power state to S3. */
2813 dc_release_state(dm_state->context);
2814 dm_state->context = dc_create_state(dm->dc);
2815 /* TODO: Remove dc_state->dccg, use dc->dccg directly. */
2816 dc_resource_state_construct(dm->dc, dm_state->context);
2818 /* Before powering on DC we need to re-initialize DMUB. */
2819 dm_dmub_hw_resume(adev);
2821 /* Re-enable outbox interrupts for DPIA. */
2822 if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
2823 amdgpu_dm_outbox_init(adev);
2824 dc_enable_dmub_outbox(adev->dm.dc);
2827 /* power on hardware */
2828 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
2830 /* program HPD filter */
2834 * early enable HPD Rx IRQ, should be done before set mode as short
2835 * pulse interrupts are used for MST
2837 amdgpu_dm_irq_resume_early(adev);
2839 /* On resume we need to rewrite the MSTM control bits to enable MST*/
2840 s3_handle_mst(ddev, false);
2843 drm_connector_list_iter_begin(ddev, &iter);
2844 drm_for_each_connector_iter(connector, &iter) {
2845 aconnector = to_amdgpu_dm_connector(connector);
2847 if (!aconnector->dc_link)
2851 * this is the case when traversing through already created
2852 * MST connectors, should be skipped
2854 if (aconnector->dc_link->type == dc_connection_mst_branch)
2857 mutex_lock(&aconnector->hpd_lock);
2858 if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type))
2859 DRM_ERROR("KMS: Failed to detect connector\n");
2861 if (aconnector->base.force && new_connection_type == dc_connection_none) {
2862 emulated_link_detect(aconnector->dc_link);
2864 mutex_lock(&dm->dc_lock);
2865 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
2866 mutex_unlock(&dm->dc_lock);
2869 if (aconnector->fake_enable && aconnector->dc_link->local_sink)
2870 aconnector->fake_enable = false;
2872 if (aconnector->dc_sink)
2873 dc_sink_release(aconnector->dc_sink);
2874 aconnector->dc_sink = NULL;
2875 amdgpu_dm_update_connector_after_detect(aconnector);
2876 mutex_unlock(&aconnector->hpd_lock);
2878 drm_connector_list_iter_end(&iter);
2880 /* Force mode set in atomic commit */
2881 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)
2882 new_crtc_state->active_changed = true;
2885 * atomic_check is expected to create the dc states. We need to release
2886 * them here, since they were duplicated as part of the suspend
2889 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {
2890 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
2891 if (dm_new_crtc_state->stream) {
2892 WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
2893 dc_stream_release(dm_new_crtc_state->stream);
2894 dm_new_crtc_state->stream = NULL;
2898 for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) {
2899 dm_new_plane_state = to_dm_plane_state(new_plane_state);
2900 if (dm_new_plane_state->dc_state) {
2901 WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
2902 dc_plane_state_release(dm_new_plane_state->dc_state);
2903 dm_new_plane_state->dc_state = NULL;
2907 drm_atomic_helper_resume(ddev, dm->cached_state);
2909 dm->cached_state = NULL;
2911 amdgpu_dm_irq_resume_late(adev);
2913 amdgpu_dm_smu_write_watermarks_table(adev);
2921 * DM (and consequently DC) is registered in the amdgpu base driver as a IP
2922 * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to
2923 * the base driver's device list to be initialized and torn down accordingly.
2925 * The functions to do so are provided as hooks in &struct amd_ip_funcs.
2928 static const struct amd_ip_funcs amdgpu_dm_funcs = {
2930 .early_init = dm_early_init,
2931 .late_init = dm_late_init,
2932 .sw_init = dm_sw_init,
2933 .sw_fini = dm_sw_fini,
2934 .early_fini = amdgpu_dm_early_fini,
2935 .hw_init = dm_hw_init,
2936 .hw_fini = dm_hw_fini,
2937 .suspend = dm_suspend,
2938 .resume = dm_resume,
2939 .is_idle = dm_is_idle,
2940 .wait_for_idle = dm_wait_for_idle,
2941 .check_soft_reset = dm_check_soft_reset,
2942 .soft_reset = dm_soft_reset,
2943 .set_clockgating_state = dm_set_clockgating_state,
2944 .set_powergating_state = dm_set_powergating_state,
2947 const struct amdgpu_ip_block_version dm_ip_block =
2949 .type = AMD_IP_BLOCK_TYPE_DCE,
2953 .funcs = &amdgpu_dm_funcs,
2963 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
2964 .fb_create = amdgpu_display_user_framebuffer_create,
2965 .get_format_info = amdgpu_dm_plane_get_format_info,
2966 .atomic_check = amdgpu_dm_atomic_check,
2967 .atomic_commit = drm_atomic_helper_commit,
2970 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
2971 .atomic_commit_tail = amdgpu_dm_atomic_commit_tail,
2972 .atomic_commit_setup = drm_dp_mst_atomic_setup_commit,
2975 static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector)
2977 struct amdgpu_dm_backlight_caps *caps;
2978 struct drm_connector *conn_base;
2979 struct amdgpu_device *adev;
2980 struct drm_luminance_range_info *luminance_range;
2982 if (aconnector->bl_idx == -1 ||
2983 aconnector->dc_link->connector_signal != SIGNAL_TYPE_EDP)
2986 conn_base = &aconnector->base;
2987 adev = drm_to_adev(conn_base->dev);
2989 caps = &adev->dm.backlight_caps[aconnector->bl_idx];
2990 caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps;
2991 caps->aux_support = false;
2993 if (caps->ext_caps->bits.oled == 1 /*||
2994 caps->ext_caps->bits.sdr_aux_backlight_control == 1 ||
2995 caps->ext_caps->bits.hdr_aux_backlight_control == 1*/)
2996 caps->aux_support = true;
2998 if (amdgpu_backlight == 0)
2999 caps->aux_support = false;
3000 else if (amdgpu_backlight == 1)
3001 caps->aux_support = true;
3003 luminance_range = &conn_base->display_info.luminance_range;
3005 if (luminance_range->max_luminance) {
3006 caps->aux_min_input_signal = luminance_range->min_luminance;
3007 caps->aux_max_input_signal = luminance_range->max_luminance;
3009 caps->aux_min_input_signal = 0;
3010 caps->aux_max_input_signal = 512;
3014 void amdgpu_dm_update_connector_after_detect(
3015 struct amdgpu_dm_connector *aconnector)
3017 struct drm_connector *connector = &aconnector->base;
3018 struct drm_device *dev = connector->dev;
3019 struct dc_sink *sink;
3021 /* MST handled by drm_mst framework */
3022 if (aconnector->mst_mgr.mst_state == true)
3025 sink = aconnector->dc_link->local_sink;
3027 dc_sink_retain(sink);
3030 * Edid mgmt connector gets first update only in mode_valid hook and then
3031 * the connector sink is set to either fake or physical sink depends on link status.
3032 * Skip if already done during boot.
3034 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
3035 && aconnector->dc_em_sink) {
3038 * For S3 resume with headless use eml_sink to fake stream
3039 * because on resume connector->sink is set to NULL
3041 mutex_lock(&dev->mode_config.mutex);
3044 if (aconnector->dc_sink) {
3045 amdgpu_dm_update_freesync_caps(connector, NULL);
3047 * retain and release below are used to
3048 * bump up refcount for sink because the link doesn't point
3049 * to it anymore after disconnect, so on next crtc to connector
3050 * reshuffle by UMD we will get into unwanted dc_sink release
3052 dc_sink_release(aconnector->dc_sink);
3054 aconnector->dc_sink = sink;
3055 dc_sink_retain(aconnector->dc_sink);
3056 amdgpu_dm_update_freesync_caps(connector,
3059 amdgpu_dm_update_freesync_caps(connector, NULL);
3060 if (!aconnector->dc_sink) {
3061 aconnector->dc_sink = aconnector->dc_em_sink;
3062 dc_sink_retain(aconnector->dc_sink);
3066 mutex_unlock(&dev->mode_config.mutex);
3069 dc_sink_release(sink);
3074 * TODO: temporary guard to look for proper fix
3075 * if this sink is MST sink, we should not do anything
3077 if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
3078 dc_sink_release(sink);
3082 if (aconnector->dc_sink == sink) {
3084 * We got a DP short pulse (Link Loss, DP CTS, etc...).
3087 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
3088 aconnector->connector_id);
3090 dc_sink_release(sink);
3094 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
3095 aconnector->connector_id, aconnector->dc_sink, sink);
3097 mutex_lock(&dev->mode_config.mutex);
3100 * 1. Update status of the drm connector
3101 * 2. Send an event and let userspace tell us what to do
3105 * TODO: check if we still need the S3 mode update workaround.
3106 * If yes, put it here.
3108 if (aconnector->dc_sink) {
3109 amdgpu_dm_update_freesync_caps(connector, NULL);
3110 dc_sink_release(aconnector->dc_sink);
3113 aconnector->dc_sink = sink;
3114 dc_sink_retain(aconnector->dc_sink);
3115 if (sink->dc_edid.length == 0) {
3116 aconnector->edid = NULL;
3117 if (aconnector->dc_link->aux_mode) {
3118 drm_dp_cec_unset_edid(
3119 &aconnector->dm_dp_aux.aux);
3123 (struct edid *)sink->dc_edid.raw_edid;
3125 if (aconnector->dc_link->aux_mode)
3126 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,
3130 aconnector->timing_requested = kzalloc(sizeof(struct dc_crtc_timing), GFP_KERNEL);
3131 if (!aconnector->timing_requested)
3132 dm_error("%s: failed to create aconnector->requested_timing\n", __func__);
3134 drm_connector_update_edid_property(connector, aconnector->edid);
3135 amdgpu_dm_update_freesync_caps(connector, aconnector->edid);
3136 update_connector_ext_caps(aconnector);
3138 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
3139 amdgpu_dm_update_freesync_caps(connector, NULL);
3140 drm_connector_update_edid_property(connector, NULL);
3141 aconnector->num_modes = 0;
3142 dc_sink_release(aconnector->dc_sink);
3143 aconnector->dc_sink = NULL;
3144 aconnector->edid = NULL;
3145 kfree(aconnector->timing_requested);
3146 aconnector->timing_requested = NULL;
3147 /* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */
3148 if (connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
3149 connector->state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
3152 mutex_unlock(&dev->mode_config.mutex);
3154 update_subconnector_property(aconnector);
3157 dc_sink_release(sink);
3160 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector)
3162 struct drm_connector *connector = &aconnector->base;
3163 struct drm_device *dev = connector->dev;
3164 enum dc_connection_type new_connection_type = dc_connection_none;
3165 struct amdgpu_device *adev = drm_to_adev(dev);
3166 struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
3169 if (adev->dm.disable_hpd_irq)
3173 * In case of failure or MST no need to update connector status or notify the OS
3174 * since (for MST case) MST does this in its own context.
3176 mutex_lock(&aconnector->hpd_lock);
3178 if (adev->dm.hdcp_workqueue) {
3179 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
3180 dm_con_state->update_hdcp = true;
3182 if (aconnector->fake_enable)
3183 aconnector->fake_enable = false;
3185 aconnector->timing_changed = false;
3187 if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type))
3188 DRM_ERROR("KMS: Failed to detect connector\n");
3190 if (aconnector->base.force && new_connection_type == dc_connection_none) {
3191 emulated_link_detect(aconnector->dc_link);
3193 drm_modeset_lock_all(dev);
3194 dm_restore_drm_connector_state(dev, connector);
3195 drm_modeset_unlock_all(dev);
3197 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
3198 drm_kms_helper_connector_hotplug_event(connector);
3200 mutex_lock(&adev->dm.dc_lock);
3201 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
3202 mutex_unlock(&adev->dm.dc_lock);
3204 amdgpu_dm_update_connector_after_detect(aconnector);
3206 drm_modeset_lock_all(dev);
3207 dm_restore_drm_connector_state(dev, connector);
3208 drm_modeset_unlock_all(dev);
3210 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
3211 drm_kms_helper_connector_hotplug_event(connector);
3214 mutex_unlock(&aconnector->hpd_lock);
3218 static void handle_hpd_irq(void *param)
3220 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
3222 handle_hpd_irq_helper(aconnector);
3226 static void dm_handle_mst_sideband_msg(struct amdgpu_dm_connector *aconnector)
3228 u8 esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
3230 bool new_irq_handled = false;
3232 int dpcd_bytes_to_read;
3234 const int max_process_count = 30;
3235 int process_count = 0;
3237 const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
3239 if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
3240 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
3241 /* DPCD 0x200 - 0x201 for downstream IRQ */
3242 dpcd_addr = DP_SINK_COUNT;
3244 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
3245 /* DPCD 0x2002 - 0x2005 for downstream IRQ */
3246 dpcd_addr = DP_SINK_COUNT_ESI;
3249 dret = drm_dp_dpcd_read(
3250 &aconnector->dm_dp_aux.aux,
3253 dpcd_bytes_to_read);
3255 while (dret == dpcd_bytes_to_read &&
3256 process_count < max_process_count) {
3262 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3263 /* handle HPD short pulse irq */
3264 if (aconnector->mst_mgr.mst_state)
3266 &aconnector->mst_mgr,
3270 if (new_irq_handled) {
3271 /* ACK at DPCD to notify down stream */
3272 const int ack_dpcd_bytes_to_write =
3273 dpcd_bytes_to_read - 1;
3275 for (retry = 0; retry < 3; retry++) {
3278 wret = drm_dp_dpcd_write(
3279 &aconnector->dm_dp_aux.aux,
3282 ack_dpcd_bytes_to_write);
3283 if (wret == ack_dpcd_bytes_to_write)
3287 /* check if there is new irq to be handled */
3288 dret = drm_dp_dpcd_read(
3289 &aconnector->dm_dp_aux.aux,
3292 dpcd_bytes_to_read);
3294 new_irq_handled = false;
3300 if (process_count == max_process_count)
3301 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
3304 static void schedule_hpd_rx_offload_work(struct hpd_rx_irq_offload_work_queue *offload_wq,
3305 union hpd_irq_data hpd_irq_data)
3307 struct hpd_rx_irq_offload_work *offload_work =
3308 kzalloc(sizeof(*offload_work), GFP_KERNEL);
3310 if (!offload_work) {
3311 DRM_ERROR("Failed to allocate hpd_rx_irq_offload_work.\n");
3315 INIT_WORK(&offload_work->work, dm_handle_hpd_rx_offload_work);
3316 offload_work->data = hpd_irq_data;
3317 offload_work->offload_wq = offload_wq;
3319 queue_work(offload_wq->wq, &offload_work->work);
3320 DRM_DEBUG_KMS("queue work to handle hpd_rx offload work");
3323 static void handle_hpd_rx_irq(void *param)
3325 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
3326 struct drm_connector *connector = &aconnector->base;
3327 struct drm_device *dev = connector->dev;
3328 struct dc_link *dc_link = aconnector->dc_link;
3329 bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
3330 bool result = false;
3331 enum dc_connection_type new_connection_type = dc_connection_none;
3332 struct amdgpu_device *adev = drm_to_adev(dev);
3333 union hpd_irq_data hpd_irq_data;
3334 bool link_loss = false;
3335 bool has_left_work = false;
3336 int idx = dc_link->link_index;
3337 struct hpd_rx_irq_offload_work_queue *offload_wq = &adev->dm.hpd_rx_offload_wq[idx];
3339 memset(&hpd_irq_data, 0, sizeof(hpd_irq_data));
3341 if (adev->dm.disable_hpd_irq)
3345 * TODO:Temporary add mutex to protect hpd interrupt not have a gpio
3346 * conflict, after implement i2c helper, this mutex should be
3349 mutex_lock(&aconnector->hpd_lock);
3351 result = dc_link_handle_hpd_rx_irq(dc_link, &hpd_irq_data,
3352 &link_loss, true, &has_left_work);
3357 if (hpd_irq_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
3358 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3362 if (dc_link_dp_allow_hpd_rx_irq(dc_link)) {
3363 if (hpd_irq_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY ||
3364 hpd_irq_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) {
3365 dm_handle_mst_sideband_msg(aconnector);
3372 spin_lock(&offload_wq->offload_lock);
3373 skip = offload_wq->is_handling_link_loss;
3376 offload_wq->is_handling_link_loss = true;
3378 spin_unlock(&offload_wq->offload_lock);
3381 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3388 if (result && !is_mst_root_connector) {
3389 /* Downstream Port status changed. */
3390 if (!dc_link_detect_connection_type(dc_link, &new_connection_type))
3391 DRM_ERROR("KMS: Failed to detect connector\n");
3393 if (aconnector->base.force && new_connection_type == dc_connection_none) {
3394 emulated_link_detect(dc_link);
3396 if (aconnector->fake_enable)
3397 aconnector->fake_enable = false;
3399 amdgpu_dm_update_connector_after_detect(aconnector);
3402 drm_modeset_lock_all(dev);
3403 dm_restore_drm_connector_state(dev, connector);
3404 drm_modeset_unlock_all(dev);
3406 drm_kms_helper_connector_hotplug_event(connector);
3410 mutex_lock(&adev->dm.dc_lock);
3411 ret = dc_link_detect(dc_link, DETECT_REASON_HPDRX);
3412 mutex_unlock(&adev->dm.dc_lock);
3415 if (aconnector->fake_enable)
3416 aconnector->fake_enable = false;
3418 amdgpu_dm_update_connector_after_detect(aconnector);
3420 drm_modeset_lock_all(dev);
3421 dm_restore_drm_connector_state(dev, connector);
3422 drm_modeset_unlock_all(dev);
3424 drm_kms_helper_connector_hotplug_event(connector);
3428 if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ) {
3429 if (adev->dm.hdcp_workqueue)
3430 hdcp_handle_cpirq(adev->dm.hdcp_workqueue, aconnector->base.index);
3433 if (dc_link->type != dc_connection_mst_branch)
3434 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux);
3436 mutex_unlock(&aconnector->hpd_lock);
3439 static void register_hpd_handlers(struct amdgpu_device *adev)
3441 struct drm_device *dev = adev_to_drm(adev);
3442 struct drm_connector *connector;
3443 struct amdgpu_dm_connector *aconnector;
3444 const struct dc_link *dc_link;
3445 struct dc_interrupt_params int_params = {0};
3447 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3448 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3450 list_for_each_entry(connector,
3451 &dev->mode_config.connector_list, head) {
3453 aconnector = to_amdgpu_dm_connector(connector);
3454 dc_link = aconnector->dc_link;
3456 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
3457 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3458 int_params.irq_source = dc_link->irq_source_hpd;
3460 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3462 (void *) aconnector);
3465 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
3467 /* Also register for DP short pulse (hpd_rx). */
3468 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3469 int_params.irq_source = dc_link->irq_source_hpd_rx;
3471 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3473 (void *) aconnector);
3475 if (adev->dm.hpd_rx_offload_wq)
3476 adev->dm.hpd_rx_offload_wq[dc_link->link_index].aconnector =
3482 #if defined(CONFIG_DRM_AMD_DC_SI)
3483 /* Register IRQ sources and initialize IRQ callbacks */
3484 static int dce60_register_irq_handlers(struct amdgpu_device *adev)
3486 struct dc *dc = adev->dm.dc;
3487 struct common_irq_params *c_irq_params;
3488 struct dc_interrupt_params int_params = {0};
3491 unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
3493 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3494 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3497 * Actions of amdgpu_irq_add_id():
3498 * 1. Register a set() function with base driver.
3499 * Base driver will call set() function to enable/disable an
3500 * interrupt in DC hardware.
3501 * 2. Register amdgpu_dm_irq_handler().
3502 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3503 * coming from DC hardware.
3504 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3505 * for acknowledging and handling. */
3507 /* Use VBLANK interrupt */
3508 for (i = 0; i < adev->mode_info.num_crtc; i++) {
3509 r = amdgpu_irq_add_id(adev, client_id, i+1 , &adev->crtc_irq);
3511 DRM_ERROR("Failed to add crtc irq id!\n");
3515 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3516 int_params.irq_source =
3517 dc_interrupt_to_irq_source(dc, i+1 , 0);
3519 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3521 c_irq_params->adev = adev;
3522 c_irq_params->irq_src = int_params.irq_source;
3524 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3525 dm_crtc_high_irq, c_irq_params);
3528 /* Use GRPH_PFLIP interrupt */
3529 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
3530 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
3531 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
3533 DRM_ERROR("Failed to add page flip irq id!\n");
3537 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3538 int_params.irq_source =
3539 dc_interrupt_to_irq_source(dc, i, 0);
3541 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3543 c_irq_params->adev = adev;
3544 c_irq_params->irq_src = int_params.irq_source;
3546 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3547 dm_pflip_high_irq, c_irq_params);
3552 r = amdgpu_irq_add_id(adev, client_id,
3553 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
3555 DRM_ERROR("Failed to add hpd irq id!\n");
3559 register_hpd_handlers(adev);
3565 /* Register IRQ sources and initialize IRQ callbacks */
3566 static int dce110_register_irq_handlers(struct amdgpu_device *adev)
3568 struct dc *dc = adev->dm.dc;
3569 struct common_irq_params *c_irq_params;
3570 struct dc_interrupt_params int_params = {0};
3573 unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
3575 if (adev->family >= AMDGPU_FAMILY_AI)
3576 client_id = SOC15_IH_CLIENTID_DCE;
3578 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3579 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3582 * Actions of amdgpu_irq_add_id():
3583 * 1. Register a set() function with base driver.
3584 * Base driver will call set() function to enable/disable an
3585 * interrupt in DC hardware.
3586 * 2. Register amdgpu_dm_irq_handler().
3587 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3588 * coming from DC hardware.
3589 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3590 * for acknowledging and handling. */
3592 /* Use VBLANK interrupt */
3593 for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
3594 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
3596 DRM_ERROR("Failed to add crtc irq id!\n");
3600 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3601 int_params.irq_source =
3602 dc_interrupt_to_irq_source(dc, i, 0);
3604 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3606 c_irq_params->adev = adev;
3607 c_irq_params->irq_src = int_params.irq_source;
3609 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3610 dm_crtc_high_irq, c_irq_params);
3613 /* Use VUPDATE interrupt */
3614 for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) {
3615 r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq);
3617 DRM_ERROR("Failed to add vupdate irq id!\n");
3621 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3622 int_params.irq_source =
3623 dc_interrupt_to_irq_source(dc, i, 0);
3625 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
3627 c_irq_params->adev = adev;
3628 c_irq_params->irq_src = int_params.irq_source;
3630 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3631 dm_vupdate_high_irq, c_irq_params);
3634 /* Use GRPH_PFLIP interrupt */
3635 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
3636 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
3637 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
3639 DRM_ERROR("Failed to add page flip irq id!\n");
3643 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3644 int_params.irq_source =
3645 dc_interrupt_to_irq_source(dc, i, 0);
3647 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3649 c_irq_params->adev = adev;
3650 c_irq_params->irq_src = int_params.irq_source;
3652 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3653 dm_pflip_high_irq, c_irq_params);
3658 r = amdgpu_irq_add_id(adev, client_id,
3659 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
3661 DRM_ERROR("Failed to add hpd irq id!\n");
3665 register_hpd_handlers(adev);
3670 /* Register IRQ sources and initialize IRQ callbacks */
3671 static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
3673 struct dc *dc = adev->dm.dc;
3674 struct common_irq_params *c_irq_params;
3675 struct dc_interrupt_params int_params = {0};
3678 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
3679 static const unsigned int vrtl_int_srcid[] = {
3680 DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL,
3681 DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL,
3682 DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL,
3683 DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL,
3684 DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL,
3685 DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL
3689 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3690 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3693 * Actions of amdgpu_irq_add_id():
3694 * 1. Register a set() function with base driver.
3695 * Base driver will call set() function to enable/disable an
3696 * interrupt in DC hardware.
3697 * 2. Register amdgpu_dm_irq_handler().
3698 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3699 * coming from DC hardware.
3700 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3701 * for acknowledging and handling.
3704 /* Use VSTARTUP interrupt */
3705 for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
3706 i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
3708 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);
3711 DRM_ERROR("Failed to add crtc irq id!\n");
3715 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3716 int_params.irq_source =
3717 dc_interrupt_to_irq_source(dc, i, 0);
3719 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3721 c_irq_params->adev = adev;
3722 c_irq_params->irq_src = int_params.irq_source;
3724 amdgpu_dm_irq_register_interrupt(
3725 adev, &int_params, dm_crtc_high_irq, c_irq_params);
3728 /* Use otg vertical line interrupt */
3729 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
3730 for (i = 0; i <= adev->mode_info.num_crtc - 1; i++) {
3731 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE,
3732 vrtl_int_srcid[i], &adev->vline0_irq);
3735 DRM_ERROR("Failed to add vline0 irq id!\n");
3739 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3740 int_params.irq_source =
3741 dc_interrupt_to_irq_source(dc, vrtl_int_srcid[i], 0);
3743 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID) {
3744 DRM_ERROR("Failed to register vline0 irq %d!\n", vrtl_int_srcid[i]);
3748 c_irq_params = &adev->dm.vline0_params[int_params.irq_source
3749 - DC_IRQ_SOURCE_DC1_VLINE0];
3751 c_irq_params->adev = adev;
3752 c_irq_params->irq_src = int_params.irq_source;
3754 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3755 dm_dcn_vertical_interrupt0_high_irq, c_irq_params);
3759 /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to
3760 * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx
3761 * to trigger at end of each vblank, regardless of state of the lock,
3762 * matching DCE behaviour.
3764 for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT;
3765 i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1;
3767 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq);
3770 DRM_ERROR("Failed to add vupdate irq id!\n");
3774 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3775 int_params.irq_source =
3776 dc_interrupt_to_irq_source(dc, i, 0);
3778 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
3780 c_irq_params->adev = adev;
3781 c_irq_params->irq_src = int_params.irq_source;
3783 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3784 dm_vupdate_high_irq, c_irq_params);
3787 /* Use GRPH_PFLIP interrupt */
3788 for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
3789 i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + dc->caps.max_otg_num - 1;
3791 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
3793 DRM_ERROR("Failed to add page flip irq id!\n");
3797 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3798 int_params.irq_source =
3799 dc_interrupt_to_irq_source(dc, i, 0);
3801 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3803 c_irq_params->adev = adev;
3804 c_irq_params->irq_src = int_params.irq_source;
3806 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3807 dm_pflip_high_irq, c_irq_params);
3812 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
3815 DRM_ERROR("Failed to add hpd irq id!\n");
3819 register_hpd_handlers(adev);
3823 /* Register Outbox IRQ sources and initialize IRQ callbacks */
3824 static int register_outbox_irq_handlers(struct amdgpu_device *adev)
3826 struct dc *dc = adev->dm.dc;
3827 struct common_irq_params *c_irq_params;
3828 struct dc_interrupt_params int_params = {0};
3831 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3832 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3834 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT,
3835 &adev->dmub_outbox_irq);
3837 DRM_ERROR("Failed to add outbox irq id!\n");
3841 if (dc->ctx->dmub_srv) {
3842 i = DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT;
3843 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3844 int_params.irq_source =
3845 dc_interrupt_to_irq_source(dc, i, 0);
3847 c_irq_params = &adev->dm.dmub_outbox_params[0];
3849 c_irq_params->adev = adev;
3850 c_irq_params->irq_src = int_params.irq_source;
3852 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3853 dm_dmub_outbox1_low_irq, c_irq_params);
3860 * Acquires the lock for the atomic state object and returns
3861 * the new atomic state.
3863 * This should only be called during atomic check.
3865 int dm_atomic_get_state(struct drm_atomic_state *state,
3866 struct dm_atomic_state **dm_state)
3868 struct drm_device *dev = state->dev;
3869 struct amdgpu_device *adev = drm_to_adev(dev);
3870 struct amdgpu_display_manager *dm = &adev->dm;
3871 struct drm_private_state *priv_state;
3876 priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj);
3877 if (IS_ERR(priv_state))
3878 return PTR_ERR(priv_state);
3880 *dm_state = to_dm_atomic_state(priv_state);
3885 static struct dm_atomic_state *
3886 dm_atomic_get_new_state(struct drm_atomic_state *state)
3888 struct drm_device *dev = state->dev;
3889 struct amdgpu_device *adev = drm_to_adev(dev);
3890 struct amdgpu_display_manager *dm = &adev->dm;
3891 struct drm_private_obj *obj;
3892 struct drm_private_state *new_obj_state;
3895 for_each_new_private_obj_in_state(state, obj, new_obj_state, i) {
3896 if (obj->funcs == dm->atomic_obj.funcs)
3897 return to_dm_atomic_state(new_obj_state);
3903 static struct drm_private_state *
3904 dm_atomic_duplicate_state(struct drm_private_obj *obj)
3906 struct dm_atomic_state *old_state, *new_state;
3908 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
3912 __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base);
3914 old_state = to_dm_atomic_state(obj->state);
3916 if (old_state && old_state->context)
3917 new_state->context = dc_copy_state(old_state->context);
3919 if (!new_state->context) {
3924 return &new_state->base;
3927 static void dm_atomic_destroy_state(struct drm_private_obj *obj,
3928 struct drm_private_state *state)
3930 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
3932 if (dm_state && dm_state->context)
3933 dc_release_state(dm_state->context);
3938 static struct drm_private_state_funcs dm_atomic_state_funcs = {
3939 .atomic_duplicate_state = dm_atomic_duplicate_state,
3940 .atomic_destroy_state = dm_atomic_destroy_state,
3943 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
3945 struct dm_atomic_state *state;
3948 adev->mode_info.mode_config_initialized = true;
3950 adev_to_drm(adev)->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
3951 adev_to_drm(adev)->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
3953 adev_to_drm(adev)->mode_config.max_width = 16384;
3954 adev_to_drm(adev)->mode_config.max_height = 16384;
3956 adev_to_drm(adev)->mode_config.preferred_depth = 24;
3957 if (adev->asic_type == CHIP_HAWAII)
3958 /* disable prefer shadow for now due to hibernation issues */
3959 adev_to_drm(adev)->mode_config.prefer_shadow = 0;
3961 adev_to_drm(adev)->mode_config.prefer_shadow = 1;
3962 /* indicates support for immediate flip */
3963 adev_to_drm(adev)->mode_config.async_page_flip = true;
3965 state = kzalloc(sizeof(*state), GFP_KERNEL);
3969 state->context = dc_create_state(adev->dm.dc);
3970 if (!state->context) {
3975 dc_resource_state_copy_construct_current(adev->dm.dc, state->context);
3977 drm_atomic_private_obj_init(adev_to_drm(adev),
3978 &adev->dm.atomic_obj,
3980 &dm_atomic_state_funcs);
3982 r = amdgpu_display_modeset_create_props(adev);
3984 dc_release_state(state->context);
3989 r = amdgpu_dm_audio_init(adev);
3991 dc_release_state(state->context);
3999 #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12
4000 #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255
4001 #define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50
4003 static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm,
4006 #if defined(CONFIG_ACPI)
4007 struct amdgpu_dm_backlight_caps caps;
4009 memset(&caps, 0, sizeof(caps));
4011 if (dm->backlight_caps[bl_idx].caps_valid)
4014 amdgpu_acpi_get_backlight_caps(&caps);
4015 if (caps.caps_valid) {
4016 dm->backlight_caps[bl_idx].caps_valid = true;
4017 if (caps.aux_support)
4019 dm->backlight_caps[bl_idx].min_input_signal = caps.min_input_signal;
4020 dm->backlight_caps[bl_idx].max_input_signal = caps.max_input_signal;
4022 dm->backlight_caps[bl_idx].min_input_signal =
4023 AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
4024 dm->backlight_caps[bl_idx].max_input_signal =
4025 AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
4028 if (dm->backlight_caps[bl_idx].aux_support)
4031 dm->backlight_caps[bl_idx].min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
4032 dm->backlight_caps[bl_idx].max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
4036 static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps,
4037 unsigned *min, unsigned *max)
4042 if (caps->aux_support) {
4043 // Firmware limits are in nits, DC API wants millinits.
4044 *max = 1000 * caps->aux_max_input_signal;
4045 *min = 1000 * caps->aux_min_input_signal;
4047 // Firmware limits are 8-bit, PWM control is 16-bit.
4048 *max = 0x101 * caps->max_input_signal;
4049 *min = 0x101 * caps->min_input_signal;
4054 static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *caps,
4055 uint32_t brightness)
4059 if (!get_brightness_range(caps, &min, &max))
4062 // Rescale 0..255 to min..max
4063 return min + DIV_ROUND_CLOSEST((max - min) * brightness,
4064 AMDGPU_MAX_BL_LEVEL);
4067 static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *caps,
4068 uint32_t brightness)
4072 if (!get_brightness_range(caps, &min, &max))
4075 if (brightness < min)
4077 // Rescale min..max to 0..255
4078 return DIV_ROUND_CLOSEST(AMDGPU_MAX_BL_LEVEL * (brightness - min),
4082 static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm,
4084 u32 user_brightness)
4086 struct amdgpu_dm_backlight_caps caps;
4087 struct dc_link *link;
4091 amdgpu_dm_update_backlight_caps(dm, bl_idx);
4092 caps = dm->backlight_caps[bl_idx];
4094 dm->brightness[bl_idx] = user_brightness;
4095 /* update scratch register */
4097 amdgpu_atombios_scratch_regs_set_backlight_level(dm->adev, dm->brightness[bl_idx]);
4098 brightness = convert_brightness_from_user(&caps, dm->brightness[bl_idx]);
4099 link = (struct dc_link *)dm->backlight_link[bl_idx];
4101 /* Change brightness based on AUX property */
4102 if (caps.aux_support) {
4103 rc = dc_link_set_backlight_level_nits(link, true, brightness,
4104 AUX_BL_DEFAULT_TRANSITION_TIME_MS);
4106 DRM_DEBUG("DM: Failed to update backlight via AUX on eDP[%d]\n", bl_idx);
4108 rc = dc_link_set_backlight_level(link, brightness, 0);
4110 DRM_DEBUG("DM: Failed to update backlight on eDP[%d]\n", bl_idx);
4114 dm->actual_brightness[bl_idx] = user_brightness;
4117 static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
4119 struct amdgpu_display_manager *dm = bl_get_data(bd);
4122 for (i = 0; i < dm->num_of_edps; i++) {
4123 if (bd == dm->backlight_dev[i])
4126 if (i >= AMDGPU_DM_MAX_NUM_EDP)
4128 amdgpu_dm_backlight_set_level(dm, i, bd->props.brightness);
4133 static u32 amdgpu_dm_backlight_get_level(struct amdgpu_display_manager *dm,
4136 struct amdgpu_dm_backlight_caps caps;
4137 struct dc_link *link = (struct dc_link *)dm->backlight_link[bl_idx];
4139 amdgpu_dm_update_backlight_caps(dm, bl_idx);
4140 caps = dm->backlight_caps[bl_idx];
4142 if (caps.aux_support) {
4146 rc = dc_link_get_backlight_level_nits(link, &avg, &peak);
4148 return dm->brightness[bl_idx];
4149 return convert_brightness_to_user(&caps, avg);
4151 int ret = dc_link_get_backlight_level(link);
4153 if (ret == DC_ERROR_UNEXPECTED)
4154 return dm->brightness[bl_idx];
4155 return convert_brightness_to_user(&caps, ret);
4159 static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
4161 struct amdgpu_display_manager *dm = bl_get_data(bd);
4164 for (i = 0; i < dm->num_of_edps; i++) {
4165 if (bd == dm->backlight_dev[i])
4168 if (i >= AMDGPU_DM_MAX_NUM_EDP)
4170 return amdgpu_dm_backlight_get_level(dm, i);
4173 static const struct backlight_ops amdgpu_dm_backlight_ops = {
4174 .options = BL_CORE_SUSPENDRESUME,
4175 .get_brightness = amdgpu_dm_backlight_get_brightness,
4176 .update_status = amdgpu_dm_backlight_update_status,
4180 amdgpu_dm_register_backlight_device(struct amdgpu_dm_connector *aconnector)
4182 struct drm_device *drm = aconnector->base.dev;
4183 struct amdgpu_display_manager *dm = &drm_to_adev(drm)->dm;
4184 struct backlight_properties props = { 0 };
4187 if (aconnector->bl_idx == -1)
4190 if (!acpi_video_backlight_use_native()) {
4191 drm_info(drm, "Skipping amdgpu DM backlight registration\n");
4192 /* Try registering an ACPI video backlight device instead. */
4193 acpi_video_register_backlight();
4197 props.max_brightness = AMDGPU_MAX_BL_LEVEL;
4198 props.brightness = AMDGPU_MAX_BL_LEVEL;
4199 props.type = BACKLIGHT_RAW;
4201 snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
4202 drm->primary->index + aconnector->bl_idx);
4204 dm->backlight_dev[aconnector->bl_idx] =
4205 backlight_device_register(bl_name, aconnector->base.kdev, dm,
4206 &amdgpu_dm_backlight_ops, &props);
4208 if (IS_ERR(dm->backlight_dev[aconnector->bl_idx])) {
4209 DRM_ERROR("DM: Backlight registration failed!\n");
4210 dm->backlight_dev[aconnector->bl_idx] = NULL;
4212 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
4215 static int initialize_plane(struct amdgpu_display_manager *dm,
4216 struct amdgpu_mode_info *mode_info, int plane_id,
4217 enum drm_plane_type plane_type,
4218 const struct dc_plane_cap *plane_cap)
4220 struct drm_plane *plane;
4221 unsigned long possible_crtcs;
4224 plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL);
4226 DRM_ERROR("KMS: Failed to allocate plane\n");
4229 plane->type = plane_type;
4232 * HACK: IGT tests expect that the primary plane for a CRTC
4233 * can only have one possible CRTC. Only expose support for
4234 * any CRTC if they're not going to be used as a primary plane
4235 * for a CRTC - like overlay or underlay planes.
4237 possible_crtcs = 1 << plane_id;
4238 if (plane_id >= dm->dc->caps.max_streams)
4239 possible_crtcs = 0xff;
4241 ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap);
4244 DRM_ERROR("KMS: Failed to initialize plane\n");
4250 mode_info->planes[plane_id] = plane;
4256 static void setup_backlight_device(struct amdgpu_display_manager *dm,
4257 struct amdgpu_dm_connector *aconnector)
4259 struct dc_link *link = aconnector->dc_link;
4260 int bl_idx = dm->num_of_edps;
4262 if (!(link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) ||
4263 link->type == dc_connection_none)
4266 if (dm->num_of_edps >= AMDGPU_DM_MAX_NUM_EDP) {
4267 drm_warn(adev_to_drm(dm->adev), "Too much eDP connections, skipping backlight setup for additional eDPs\n");
4271 aconnector->bl_idx = bl_idx;
4273 amdgpu_dm_update_backlight_caps(dm, bl_idx);
4274 dm->brightness[bl_idx] = AMDGPU_MAX_BL_LEVEL;
4275 dm->backlight_link[bl_idx] = link;
4278 update_connector_ext_caps(aconnector);
4281 static void amdgpu_set_panel_orientation(struct drm_connector *connector);
4284 * In this architecture, the association
4285 * connector -> encoder -> crtc
4286 * id not really requried. The crtc and connector will hold the
4287 * display_index as an abstraction to use with DAL component
4289 * Returns 0 on success
4291 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
4293 struct amdgpu_display_manager *dm = &adev->dm;
4295 struct amdgpu_dm_connector *aconnector = NULL;
4296 struct amdgpu_encoder *aencoder = NULL;
4297 struct amdgpu_mode_info *mode_info = &adev->mode_info;
4300 enum dc_connection_type new_connection_type = dc_connection_none;
4301 const struct dc_plane_cap *plane;
4302 bool psr_feature_enabled = false;
4303 int max_overlay = dm->dc->caps.max_slave_planes;
4305 dm->display_indexes_num = dm->dc->caps.max_streams;
4306 /* Update the actual used number of crtc */
4307 adev->mode_info.num_crtc = adev->dm.display_indexes_num;
4309 amdgpu_dm_set_irq_funcs(adev);
4311 link_cnt = dm->dc->caps.max_links;
4312 if (amdgpu_dm_mode_config_init(dm->adev)) {
4313 DRM_ERROR("DM: Failed to initialize mode config\n");
4317 /* There is one primary plane per CRTC */
4318 primary_planes = dm->dc->caps.max_streams;
4319 ASSERT(primary_planes <= AMDGPU_MAX_PLANES);
4322 * Initialize primary planes, implicit planes for legacy IOCTLS.
4323 * Order is reversed to match iteration order in atomic check.
4325 for (i = (primary_planes - 1); i >= 0; i--) {
4326 plane = &dm->dc->caps.planes[i];
4328 if (initialize_plane(dm, mode_info, i,
4329 DRM_PLANE_TYPE_PRIMARY, plane)) {
4330 DRM_ERROR("KMS: Failed to initialize primary plane\n");
4336 * Initialize overlay planes, index starting after primary planes.
4337 * These planes have a higher DRM index than the primary planes since
4338 * they should be considered as having a higher z-order.
4339 * Order is reversed to match iteration order in atomic check.
4341 * Only support DCN for now, and only expose one so we don't encourage
4342 * userspace to use up all the pipes.
4344 for (i = 0; i < dm->dc->caps.max_planes; ++i) {
4345 struct dc_plane_cap *plane = &dm->dc->caps.planes[i];
4347 /* Do not create overlay if MPO disabled */
4348 if (amdgpu_dc_debug_mask & DC_DISABLE_MPO)
4351 if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL)
4354 if (!plane->pixel_format_support.argb8888)
4357 if (max_overlay-- == 0)
4360 if (initialize_plane(dm, NULL, primary_planes + i,
4361 DRM_PLANE_TYPE_OVERLAY, plane)) {
4362 DRM_ERROR("KMS: Failed to initialize overlay plane\n");
4367 for (i = 0; i < dm->dc->caps.max_streams; i++)
4368 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) {
4369 DRM_ERROR("KMS: Failed to initialize crtc\n");
4373 /* Use Outbox interrupt */
4374 switch (adev->ip_versions[DCE_HWIP][0]) {
4375 case IP_VERSION(3, 0, 0):
4376 case IP_VERSION(3, 1, 2):
4377 case IP_VERSION(3, 1, 3):
4378 case IP_VERSION(3, 1, 4):
4379 case IP_VERSION(3, 1, 5):
4380 case IP_VERSION(3, 1, 6):
4381 case IP_VERSION(3, 2, 0):
4382 case IP_VERSION(3, 2, 1):
4383 case IP_VERSION(2, 1, 0):
4384 if (register_outbox_irq_handlers(dm->adev)) {
4385 DRM_ERROR("DM: Failed to initialize IRQ\n");
4390 DRM_DEBUG_KMS("Unsupported DCN IP version for outbox: 0x%X\n",
4391 adev->ip_versions[DCE_HWIP][0]);
4394 /* Determine whether to enable PSR support by default. */
4395 if (!(amdgpu_dc_debug_mask & DC_DISABLE_PSR)) {
4396 switch (adev->ip_versions[DCE_HWIP][0]) {
4397 case IP_VERSION(3, 1, 2):
4398 case IP_VERSION(3, 1, 3):
4399 case IP_VERSION(3, 1, 4):
4400 case IP_VERSION(3, 1, 5):
4401 case IP_VERSION(3, 1, 6):
4402 case IP_VERSION(3, 2, 0):
4403 case IP_VERSION(3, 2, 1):
4404 psr_feature_enabled = true;
4407 psr_feature_enabled = amdgpu_dc_feature_mask & DC_PSR_MASK;
4412 /* loops over all connectors on the board */
4413 for (i = 0; i < link_cnt; i++) {
4414 struct dc_link *link = NULL;
4416 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
4418 "KMS: Cannot support more than %d display indexes\n",
4419 AMDGPU_DM_MAX_DISPLAY_INDEX);
4423 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
4427 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
4431 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
4432 DRM_ERROR("KMS: Failed to initialize encoder\n");
4436 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
4437 DRM_ERROR("KMS: Failed to initialize connector\n");
4441 link = dc_get_link_at_index(dm->dc, i);
4443 if (!dc_link_detect_connection_type(link, &new_connection_type))
4444 DRM_ERROR("KMS: Failed to detect connector\n");
4446 if (aconnector->base.force && new_connection_type == dc_connection_none) {
4447 emulated_link_detect(link);
4448 amdgpu_dm_update_connector_after_detect(aconnector);
4452 mutex_lock(&dm->dc_lock);
4453 ret = dc_link_detect(link, DETECT_REASON_BOOT);
4454 mutex_unlock(&dm->dc_lock);
4457 amdgpu_dm_update_connector_after_detect(aconnector);
4458 setup_backlight_device(dm, aconnector);
4460 if (psr_feature_enabled)
4461 amdgpu_dm_set_psr_caps(link);
4463 /* TODO: Fix vblank control helpers to delay PSR entry to allow this when
4464 * PSR is also supported.
4466 if (link->psr_settings.psr_feature_enabled)
4467 adev_to_drm(adev)->vblank_disable_immediate = false;
4470 amdgpu_set_panel_orientation(&aconnector->base);
4473 /* If we didn't find a panel, notify the acpi video detection */
4474 if (dm->adev->flags & AMD_IS_APU && dm->num_of_edps == 0)
4475 acpi_video_report_nolcd();
4477 /* Software is initialized. Now we can register interrupt handlers. */
4478 switch (adev->asic_type) {
4479 #if defined(CONFIG_DRM_AMD_DC_SI)
4484 if (dce60_register_irq_handlers(dm->adev)) {
4485 DRM_ERROR("DM: Failed to initialize IRQ\n");
4499 case CHIP_POLARIS11:
4500 case CHIP_POLARIS10:
4501 case CHIP_POLARIS12:
4506 if (dce110_register_irq_handlers(dm->adev)) {
4507 DRM_ERROR("DM: Failed to initialize IRQ\n");
4512 switch (adev->ip_versions[DCE_HWIP][0]) {
4513 case IP_VERSION(1, 0, 0):
4514 case IP_VERSION(1, 0, 1):
4515 case IP_VERSION(2, 0, 2):
4516 case IP_VERSION(2, 0, 3):
4517 case IP_VERSION(2, 0, 0):
4518 case IP_VERSION(2, 1, 0):
4519 case IP_VERSION(3, 0, 0):
4520 case IP_VERSION(3, 0, 2):
4521 case IP_VERSION(3, 0, 3):
4522 case IP_VERSION(3, 0, 1):
4523 case IP_VERSION(3, 1, 2):
4524 case IP_VERSION(3, 1, 3):
4525 case IP_VERSION(3, 1, 4):
4526 case IP_VERSION(3, 1, 5):
4527 case IP_VERSION(3, 1, 6):
4528 case IP_VERSION(3, 2, 0):
4529 case IP_VERSION(3, 2, 1):
4530 if (dcn10_register_irq_handlers(dm->adev)) {
4531 DRM_ERROR("DM: Failed to initialize IRQ\n");
4536 DRM_ERROR("Unsupported DCE IP versions: 0x%X\n",
4537 adev->ip_versions[DCE_HWIP][0]);
4551 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
4553 drm_atomic_private_obj_fini(&dm->atomic_obj);
4557 /******************************************************************************
4558 * amdgpu_display_funcs functions
4559 *****************************************************************************/
4562 * dm_bandwidth_update - program display watermarks
4564 * @adev: amdgpu_device pointer
4566 * Calculate and program the display watermarks and line buffer allocation.
4568 static void dm_bandwidth_update(struct amdgpu_device *adev)
4570 /* TODO: implement later */
4573 static const struct amdgpu_display_funcs dm_display_funcs = {
4574 .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
4575 .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
4576 .backlight_set_level = NULL, /* never called for DC */
4577 .backlight_get_level = NULL, /* never called for DC */
4578 .hpd_sense = NULL,/* called unconditionally */
4579 .hpd_set_polarity = NULL, /* called unconditionally */
4580 .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
4581 .page_flip_get_scanoutpos =
4582 dm_crtc_get_scanoutpos,/* called unconditionally */
4583 .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
4584 .add_connector = NULL, /* VBIOS parsing. DAL does it. */
4587 #if defined(CONFIG_DEBUG_KERNEL_DC)
4589 static ssize_t s3_debug_store(struct device *device,
4590 struct device_attribute *attr,
4596 struct drm_device *drm_dev = dev_get_drvdata(device);
4597 struct amdgpu_device *adev = drm_to_adev(drm_dev);
4599 ret = kstrtoint(buf, 0, &s3_state);
4604 drm_kms_helper_hotplug_event(adev_to_drm(adev));
4609 return ret == 0 ? count : 0;
4612 DEVICE_ATTR_WO(s3_debug);
4616 static int dm_init_microcode(struct amdgpu_device *adev)
4621 switch (adev->ip_versions[DCE_HWIP][0]) {
4622 case IP_VERSION(2, 1, 0):
4623 fw_name_dmub = FIRMWARE_RENOIR_DMUB;
4624 if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
4625 fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB;
4627 case IP_VERSION(3, 0, 0):
4628 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0))
4629 fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB;
4631 fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB;
4633 case IP_VERSION(3, 0, 1):
4634 fw_name_dmub = FIRMWARE_VANGOGH_DMUB;
4636 case IP_VERSION(3, 0, 2):
4637 fw_name_dmub = FIRMWARE_DIMGREY_CAVEFISH_DMUB;
4639 case IP_VERSION(3, 0, 3):
4640 fw_name_dmub = FIRMWARE_BEIGE_GOBY_DMUB;
4642 case IP_VERSION(3, 1, 2):
4643 case IP_VERSION(3, 1, 3):
4644 fw_name_dmub = FIRMWARE_YELLOW_CARP_DMUB;
4646 case IP_VERSION(3, 1, 4):
4647 fw_name_dmub = FIRMWARE_DCN_314_DMUB;
4649 case IP_VERSION(3, 1, 5):
4650 fw_name_dmub = FIRMWARE_DCN_315_DMUB;
4652 case IP_VERSION(3, 1, 6):
4653 fw_name_dmub = FIRMWARE_DCN316_DMUB;
4655 case IP_VERSION(3, 2, 0):
4656 fw_name_dmub = FIRMWARE_DCN_V3_2_0_DMCUB;
4658 case IP_VERSION(3, 2, 1):
4659 fw_name_dmub = FIRMWARE_DCN_V3_2_1_DMCUB;
4662 /* ASIC doesn't support DMUB. */
4665 r = amdgpu_ucode_request(adev, &adev->dm.dmub_fw, fw_name_dmub);
4667 DRM_ERROR("DMUB firmware loading failed: %d\n", r);
4671 static int dm_early_init(void *handle)
4673 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4674 struct amdgpu_mode_info *mode_info = &adev->mode_info;
4675 struct atom_context *ctx = mode_info->atom_context;
4676 int index = GetIndexIntoMasterTable(DATA, Object_Header);
4679 /* if there is no object header, skip DM */
4680 if (!amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) {
4681 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
4682 dev_info(adev->dev, "No object header, skipping DM\n");
4686 switch (adev->asic_type) {
4687 #if defined(CONFIG_DRM_AMD_DC_SI)
4691 adev->mode_info.num_crtc = 6;
4692 adev->mode_info.num_hpd = 6;
4693 adev->mode_info.num_dig = 6;
4696 adev->mode_info.num_crtc = 2;
4697 adev->mode_info.num_hpd = 2;
4698 adev->mode_info.num_dig = 2;
4703 adev->mode_info.num_crtc = 6;
4704 adev->mode_info.num_hpd = 6;
4705 adev->mode_info.num_dig = 6;
4708 adev->mode_info.num_crtc = 4;
4709 adev->mode_info.num_hpd = 6;
4710 adev->mode_info.num_dig = 7;
4714 adev->mode_info.num_crtc = 2;
4715 adev->mode_info.num_hpd = 6;
4716 adev->mode_info.num_dig = 6;
4720 adev->mode_info.num_crtc = 6;
4721 adev->mode_info.num_hpd = 6;
4722 adev->mode_info.num_dig = 7;
4725 adev->mode_info.num_crtc = 3;
4726 adev->mode_info.num_hpd = 6;
4727 adev->mode_info.num_dig = 9;
4730 adev->mode_info.num_crtc = 2;
4731 adev->mode_info.num_hpd = 6;
4732 adev->mode_info.num_dig = 9;
4734 case CHIP_POLARIS11:
4735 case CHIP_POLARIS12:
4736 adev->mode_info.num_crtc = 5;
4737 adev->mode_info.num_hpd = 5;
4738 adev->mode_info.num_dig = 5;
4740 case CHIP_POLARIS10:
4742 adev->mode_info.num_crtc = 6;
4743 adev->mode_info.num_hpd = 6;
4744 adev->mode_info.num_dig = 6;
4749 adev->mode_info.num_crtc = 6;
4750 adev->mode_info.num_hpd = 6;
4751 adev->mode_info.num_dig = 6;
4755 switch (adev->ip_versions[DCE_HWIP][0]) {
4756 case IP_VERSION(2, 0, 2):
4757 case IP_VERSION(3, 0, 0):
4758 adev->mode_info.num_crtc = 6;
4759 adev->mode_info.num_hpd = 6;
4760 adev->mode_info.num_dig = 6;
4762 case IP_VERSION(2, 0, 0):
4763 case IP_VERSION(3, 0, 2):
4764 adev->mode_info.num_crtc = 5;
4765 adev->mode_info.num_hpd = 5;
4766 adev->mode_info.num_dig = 5;
4768 case IP_VERSION(2, 0, 3):
4769 case IP_VERSION(3, 0, 3):
4770 adev->mode_info.num_crtc = 2;
4771 adev->mode_info.num_hpd = 2;
4772 adev->mode_info.num_dig = 2;
4774 case IP_VERSION(1, 0, 0):
4775 case IP_VERSION(1, 0, 1):
4776 case IP_VERSION(3, 0, 1):
4777 case IP_VERSION(2, 1, 0):
4778 case IP_VERSION(3, 1, 2):
4779 case IP_VERSION(3, 1, 3):
4780 case IP_VERSION(3, 1, 4):
4781 case IP_VERSION(3, 1, 5):
4782 case IP_VERSION(3, 1, 6):
4783 case IP_VERSION(3, 2, 0):
4784 case IP_VERSION(3, 2, 1):
4785 adev->mode_info.num_crtc = 4;
4786 adev->mode_info.num_hpd = 4;
4787 adev->mode_info.num_dig = 4;
4790 DRM_ERROR("Unsupported DCE IP versions: 0x%x\n",
4791 adev->ip_versions[DCE_HWIP][0]);
4797 if (adev->mode_info.funcs == NULL)
4798 adev->mode_info.funcs = &dm_display_funcs;
4801 * Note: Do NOT change adev->audio_endpt_rreg and
4802 * adev->audio_endpt_wreg because they are initialised in
4803 * amdgpu_device_init()
4805 #if defined(CONFIG_DEBUG_KERNEL_DC)
4807 adev_to_drm(adev)->dev,
4808 &dev_attr_s3_debug);
4810 adev->dc_enabled = true;
4812 return dm_init_microcode(adev);
4815 static bool modereset_required(struct drm_crtc_state *crtc_state)
4817 return !crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state);
4820 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
4822 drm_encoder_cleanup(encoder);
4826 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
4827 .destroy = amdgpu_dm_encoder_destroy,
4831 fill_plane_color_attributes(const struct drm_plane_state *plane_state,
4832 const enum surface_pixel_format format,
4833 enum dc_color_space *color_space)
4837 *color_space = COLOR_SPACE_SRGB;
4839 /* DRM color properties only affect non-RGB formats. */
4840 if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
4843 full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE);
4845 switch (plane_state->color_encoding) {
4846 case DRM_COLOR_YCBCR_BT601:
4848 *color_space = COLOR_SPACE_YCBCR601;
4850 *color_space = COLOR_SPACE_YCBCR601_LIMITED;
4853 case DRM_COLOR_YCBCR_BT709:
4855 *color_space = COLOR_SPACE_YCBCR709;
4857 *color_space = COLOR_SPACE_YCBCR709_LIMITED;
4860 case DRM_COLOR_YCBCR_BT2020:
4862 *color_space = COLOR_SPACE_2020_YCBCR;
4875 fill_dc_plane_info_and_addr(struct amdgpu_device *adev,
4876 const struct drm_plane_state *plane_state,
4877 const u64 tiling_flags,
4878 struct dc_plane_info *plane_info,
4879 struct dc_plane_address *address,
4881 bool force_disable_dcc)
4883 const struct drm_framebuffer *fb = plane_state->fb;
4884 const struct amdgpu_framebuffer *afb =
4885 to_amdgpu_framebuffer(plane_state->fb);
4888 memset(plane_info, 0, sizeof(*plane_info));
4890 switch (fb->format->format) {
4892 plane_info->format =
4893 SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
4895 case DRM_FORMAT_RGB565:
4896 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
4898 case DRM_FORMAT_XRGB8888:
4899 case DRM_FORMAT_ARGB8888:
4900 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
4902 case DRM_FORMAT_XRGB2101010:
4903 case DRM_FORMAT_ARGB2101010:
4904 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
4906 case DRM_FORMAT_XBGR2101010:
4907 case DRM_FORMAT_ABGR2101010:
4908 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
4910 case DRM_FORMAT_XBGR8888:
4911 case DRM_FORMAT_ABGR8888:
4912 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888;
4914 case DRM_FORMAT_NV21:
4915 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
4917 case DRM_FORMAT_NV12:
4918 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
4920 case DRM_FORMAT_P010:
4921 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb;
4923 case DRM_FORMAT_XRGB16161616F:
4924 case DRM_FORMAT_ARGB16161616F:
4925 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F;
4927 case DRM_FORMAT_XBGR16161616F:
4928 case DRM_FORMAT_ABGR16161616F:
4929 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F;
4931 case DRM_FORMAT_XRGB16161616:
4932 case DRM_FORMAT_ARGB16161616:
4933 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616;
4935 case DRM_FORMAT_XBGR16161616:
4936 case DRM_FORMAT_ABGR16161616:
4937 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616;
4941 "Unsupported screen format %p4cc\n",
4942 &fb->format->format);
4946 switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
4947 case DRM_MODE_ROTATE_0:
4948 plane_info->rotation = ROTATION_ANGLE_0;
4950 case DRM_MODE_ROTATE_90:
4951 plane_info->rotation = ROTATION_ANGLE_90;
4953 case DRM_MODE_ROTATE_180:
4954 plane_info->rotation = ROTATION_ANGLE_180;
4956 case DRM_MODE_ROTATE_270:
4957 plane_info->rotation = ROTATION_ANGLE_270;
4960 plane_info->rotation = ROTATION_ANGLE_0;
4965 plane_info->visible = true;
4966 plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE;
4968 plane_info->layer_index = plane_state->normalized_zpos;
4970 ret = fill_plane_color_attributes(plane_state, plane_info->format,
4971 &plane_info->color_space);
4975 ret = amdgpu_dm_plane_fill_plane_buffer_attributes(adev, afb, plane_info->format,
4976 plane_info->rotation, tiling_flags,
4977 &plane_info->tiling_info,
4978 &plane_info->plane_size,
4979 &plane_info->dcc, address,
4980 tmz_surface, force_disable_dcc);
4984 amdgpu_dm_plane_fill_blending_from_plane_state(
4985 plane_state, &plane_info->per_pixel_alpha, &plane_info->pre_multiplied_alpha,
4986 &plane_info->global_alpha, &plane_info->global_alpha_value);
4991 static int fill_dc_plane_attributes(struct amdgpu_device *adev,
4992 struct dc_plane_state *dc_plane_state,
4993 struct drm_plane_state *plane_state,
4994 struct drm_crtc_state *crtc_state)
4996 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
4997 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)plane_state->fb;
4998 struct dc_scaling_info scaling_info;
4999 struct dc_plane_info plane_info;
5001 bool force_disable_dcc = false;
5003 ret = amdgpu_dm_plane_fill_dc_scaling_info(adev, plane_state, &scaling_info);
5007 dc_plane_state->src_rect = scaling_info.src_rect;
5008 dc_plane_state->dst_rect = scaling_info.dst_rect;
5009 dc_plane_state->clip_rect = scaling_info.clip_rect;
5010 dc_plane_state->scaling_quality = scaling_info.scaling_quality;
5012 force_disable_dcc = adev->asic_type == CHIP_RAVEN && adev->in_suspend;
5013 ret = fill_dc_plane_info_and_addr(adev, plane_state,
5016 &dc_plane_state->address,
5022 dc_plane_state->format = plane_info.format;
5023 dc_plane_state->color_space = plane_info.color_space;
5024 dc_plane_state->format = plane_info.format;
5025 dc_plane_state->plane_size = plane_info.plane_size;
5026 dc_plane_state->rotation = plane_info.rotation;
5027 dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror;
5028 dc_plane_state->stereo_format = plane_info.stereo_format;
5029 dc_plane_state->tiling_info = plane_info.tiling_info;
5030 dc_plane_state->visible = plane_info.visible;
5031 dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha;
5032 dc_plane_state->pre_multiplied_alpha = plane_info.pre_multiplied_alpha;
5033 dc_plane_state->global_alpha = plane_info.global_alpha;
5034 dc_plane_state->global_alpha_value = plane_info.global_alpha_value;
5035 dc_plane_state->dcc = plane_info.dcc;
5036 dc_plane_state->layer_index = plane_info.layer_index;
5037 dc_plane_state->flip_int_enabled = true;
5040 * Always set input transfer function, since plane state is refreshed
5043 ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dc_plane_state);
5050 static inline void fill_dc_dirty_rect(struct drm_plane *plane,
5051 struct rect *dirty_rect, int32_t x,
5052 s32 y, s32 width, s32 height,
5055 if (*i > DC_MAX_DIRTY_RECTS)
5058 if (*i == DC_MAX_DIRTY_RECTS)
5063 dirty_rect->width = width;
5064 dirty_rect->height = height;
5068 "[PLANE:%d] PSR FFU dirty rect size (%d, %d)\n",
5069 plane->base.id, width, height);
5072 "[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)",
5073 plane->base.id, x, y, width, height);
5080 * fill_dc_dirty_rects() - Fill DC dirty regions for PSR selective updates
5082 * @plane: DRM plane containing dirty regions that need to be flushed to the eDP
5084 * @old_plane_state: Old state of @plane
5085 * @new_plane_state: New state of @plane
5086 * @crtc_state: New state of CRTC connected to the @plane
5087 * @flip_addrs: DC flip tracking struct, which also tracts dirty rects
5088 * @dirty_regions_changed: dirty regions changed
5090 * For PSR SU, DC informs the DMUB uController of dirty rectangle regions
5091 * (referred to as "damage clips" in DRM nomenclature) that require updating on
5092 * the eDP remote buffer. The responsibility of specifying the dirty regions is
5095 * A damage-aware DRM client should fill the FB_DAMAGE_CLIPS property on the
5096 * plane with regions that require flushing to the eDP remote buffer. In
5097 * addition, certain use cases - such as cursor and multi-plane overlay (MPO) -
5098 * implicitly provide damage clips without any client support via the plane
5101 static void fill_dc_dirty_rects(struct drm_plane *plane,
5102 struct drm_plane_state *old_plane_state,
5103 struct drm_plane_state *new_plane_state,
5104 struct drm_crtc_state *crtc_state,
5105 struct dc_flip_addrs *flip_addrs,
5106 bool *dirty_regions_changed)
5108 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
5109 struct rect *dirty_rects = flip_addrs->dirty_rects;
5111 struct drm_mode_rect *clips;
5115 *dirty_regions_changed = false;
5118 * Cursor plane has it's own dirty rect update interface. See
5119 * dcn10_dmub_update_cursor_data and dmub_cmd_update_cursor_info_data
5121 if (plane->type == DRM_PLANE_TYPE_CURSOR)
5124 num_clips = drm_plane_get_damage_clips_count(new_plane_state);
5125 clips = drm_plane_get_damage_clips(new_plane_state);
5127 if (!dm_crtc_state->mpo_requested) {
5128 if (!num_clips || num_clips > DC_MAX_DIRTY_RECTS)
5131 for (; flip_addrs->dirty_rect_count < num_clips; clips++)
5132 fill_dc_dirty_rect(new_plane_state->plane,
5133 &dirty_rects[flip_addrs->dirty_rect_count],
5134 clips->x1, clips->y1,
5135 clips->x2 - clips->x1, clips->y2 - clips->y1,
5136 &flip_addrs->dirty_rect_count,
5142 * MPO is requested. Add entire plane bounding box to dirty rects if
5143 * flipped to or damaged.
5145 * If plane is moved or resized, also add old bounding box to dirty
5148 fb_changed = old_plane_state->fb->base.id !=
5149 new_plane_state->fb->base.id;
5150 bb_changed = (old_plane_state->crtc_x != new_plane_state->crtc_x ||
5151 old_plane_state->crtc_y != new_plane_state->crtc_y ||
5152 old_plane_state->crtc_w != new_plane_state->crtc_w ||
5153 old_plane_state->crtc_h != new_plane_state->crtc_h);
5156 "[PLANE:%d] PSR bb_changed:%d fb_changed:%d num_clips:%d\n",
5157 new_plane_state->plane->base.id,
5158 bb_changed, fb_changed, num_clips);
5160 *dirty_regions_changed = bb_changed;
5163 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5164 new_plane_state->crtc_x,
5165 new_plane_state->crtc_y,
5166 new_plane_state->crtc_w,
5167 new_plane_state->crtc_h, &i, false);
5169 /* Add old plane bounding-box if plane is moved or resized */
5170 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5171 old_plane_state->crtc_x,
5172 old_plane_state->crtc_y,
5173 old_plane_state->crtc_w,
5174 old_plane_state->crtc_h, &i, false);
5178 for (; i < num_clips; clips++)
5179 fill_dc_dirty_rect(new_plane_state->plane,
5180 &dirty_rects[i], clips->x1,
5181 clips->y1, clips->x2 - clips->x1,
5182 clips->y2 - clips->y1, &i, false);
5183 } else if (fb_changed && !bb_changed) {
5184 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5185 new_plane_state->crtc_x,
5186 new_plane_state->crtc_y,
5187 new_plane_state->crtc_w,
5188 new_plane_state->crtc_h, &i, false);
5191 if (i > DC_MAX_DIRTY_RECTS)
5194 flip_addrs->dirty_rect_count = i;
5198 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[0], 0, 0,
5199 dm_crtc_state->base.mode.crtc_hdisplay,
5200 dm_crtc_state->base.mode.crtc_vdisplay,
5201 &flip_addrs->dirty_rect_count, true);
5204 static void update_stream_scaling_settings(const struct drm_display_mode *mode,
5205 const struct dm_connector_state *dm_state,
5206 struct dc_stream_state *stream)
5208 enum amdgpu_rmx_type rmx_type;
5210 struct rect src = { 0 }; /* viewport in composition space*/
5211 struct rect dst = { 0 }; /* stream addressable area */
5213 /* no mode. nothing to be done */
5217 /* Full screen scaling by default */
5218 src.width = mode->hdisplay;
5219 src.height = mode->vdisplay;
5220 dst.width = stream->timing.h_addressable;
5221 dst.height = stream->timing.v_addressable;
5224 rmx_type = dm_state->scaling;
5225 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
5226 if (src.width * dst.height <
5227 src.height * dst.width) {
5228 /* height needs less upscaling/more downscaling */
5229 dst.width = src.width *
5230 dst.height / src.height;
5232 /* width needs less upscaling/more downscaling */
5233 dst.height = src.height *
5234 dst.width / src.width;
5236 } else if (rmx_type == RMX_CENTER) {
5240 dst.x = (stream->timing.h_addressable - dst.width) / 2;
5241 dst.y = (stream->timing.v_addressable - dst.height) / 2;
5243 if (dm_state->underscan_enable) {
5244 dst.x += dm_state->underscan_hborder / 2;
5245 dst.y += dm_state->underscan_vborder / 2;
5246 dst.width -= dm_state->underscan_hborder;
5247 dst.height -= dm_state->underscan_vborder;
5254 DRM_DEBUG_KMS("Destination Rectangle x:%d y:%d width:%d height:%d\n",
5255 dst.x, dst.y, dst.width, dst.height);
5259 static enum dc_color_depth
5260 convert_color_depth_from_display_info(const struct drm_connector *connector,
5261 bool is_y420, int requested_bpc)
5268 /* Cap display bpc based on HDMI 2.0 HF-VSDB */
5269 if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48)
5271 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36)
5273 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30)
5276 bpc = (uint8_t)connector->display_info.bpc;
5277 /* Assume 8 bpc by default if no bpc is specified. */
5278 bpc = bpc ? bpc : 8;
5281 if (requested_bpc > 0) {
5283 * Cap display bpc based on the user requested value.
5285 * The value for state->max_bpc may not correctly updated
5286 * depending on when the connector gets added to the state
5287 * or if this was called outside of atomic check, so it
5288 * can't be used directly.
5290 bpc = min_t(u8, bpc, requested_bpc);
5292 /* Round down to the nearest even number. */
5293 bpc = bpc - (bpc & 1);
5299 * Temporary Work around, DRM doesn't parse color depth for
5300 * EDID revision before 1.4
5301 * TODO: Fix edid parsing
5303 return COLOR_DEPTH_888;
5305 return COLOR_DEPTH_666;
5307 return COLOR_DEPTH_888;
5309 return COLOR_DEPTH_101010;
5311 return COLOR_DEPTH_121212;
5313 return COLOR_DEPTH_141414;
5315 return COLOR_DEPTH_161616;
5317 return COLOR_DEPTH_UNDEFINED;
5321 static enum dc_aspect_ratio
5322 get_aspect_ratio(const struct drm_display_mode *mode_in)
5324 /* 1-1 mapping, since both enums follow the HDMI spec. */
5325 return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio;
5328 static enum dc_color_space
5329 get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
5331 enum dc_color_space color_space = COLOR_SPACE_SRGB;
5333 switch (dc_crtc_timing->pixel_encoding) {
5334 case PIXEL_ENCODING_YCBCR422:
5335 case PIXEL_ENCODING_YCBCR444:
5336 case PIXEL_ENCODING_YCBCR420:
5339 * 27030khz is the separation point between HDTV and SDTV
5340 * according to HDMI spec, we use YCbCr709 and YCbCr601
5343 if (dc_crtc_timing->pix_clk_100hz > 270300) {
5344 if (dc_crtc_timing->flags.Y_ONLY)
5346 COLOR_SPACE_YCBCR709_LIMITED;
5348 color_space = COLOR_SPACE_YCBCR709;
5350 if (dc_crtc_timing->flags.Y_ONLY)
5352 COLOR_SPACE_YCBCR601_LIMITED;
5354 color_space = COLOR_SPACE_YCBCR601;
5359 case PIXEL_ENCODING_RGB:
5360 color_space = COLOR_SPACE_SRGB;
5371 static bool adjust_colour_depth_from_display_info(
5372 struct dc_crtc_timing *timing_out,
5373 const struct drm_display_info *info)
5375 enum dc_color_depth depth = timing_out->display_color_depth;
5378 normalized_clk = timing_out->pix_clk_100hz / 10;
5379 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */
5380 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
5381 normalized_clk /= 2;
5382 /* Adjusting pix clock following on HDMI spec based on colour depth */
5384 case COLOR_DEPTH_888:
5386 case COLOR_DEPTH_101010:
5387 normalized_clk = (normalized_clk * 30) / 24;
5389 case COLOR_DEPTH_121212:
5390 normalized_clk = (normalized_clk * 36) / 24;
5392 case COLOR_DEPTH_161616:
5393 normalized_clk = (normalized_clk * 48) / 24;
5396 /* The above depths are the only ones valid for HDMI. */
5399 if (normalized_clk <= info->max_tmds_clock) {
5400 timing_out->display_color_depth = depth;
5403 } while (--depth > COLOR_DEPTH_666);
5407 static void fill_stream_properties_from_drm_display_mode(
5408 struct dc_stream_state *stream,
5409 const struct drm_display_mode *mode_in,
5410 const struct drm_connector *connector,
5411 const struct drm_connector_state *connector_state,
5412 const struct dc_stream_state *old_stream,
5415 struct dc_crtc_timing *timing_out = &stream->timing;
5416 const struct drm_display_info *info = &connector->display_info;
5417 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
5418 struct hdmi_vendor_infoframe hv_frame;
5419 struct hdmi_avi_infoframe avi_frame;
5421 memset(&hv_frame, 0, sizeof(hv_frame));
5422 memset(&avi_frame, 0, sizeof(avi_frame));
5424 timing_out->h_border_left = 0;
5425 timing_out->h_border_right = 0;
5426 timing_out->v_border_top = 0;
5427 timing_out->v_border_bottom = 0;
5428 /* TODO: un-hardcode */
5429 if (drm_mode_is_420_only(info, mode_in)
5430 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5431 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5432 else if (drm_mode_is_420_also(info, mode_in)
5433 && aconnector->force_yuv420_output)
5434 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5435 else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR444)
5436 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5437 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
5439 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
5441 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
5442 timing_out->display_color_depth = convert_color_depth_from_display_info(
5444 (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420),
5446 timing_out->scan_type = SCANNING_TYPE_NODATA;
5447 timing_out->hdmi_vic = 0;
5450 timing_out->vic = old_stream->timing.vic;
5451 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY;
5452 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY;
5454 timing_out->vic = drm_match_cea_mode(mode_in);
5455 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
5456 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
5457 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
5458 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
5461 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
5462 drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, (struct drm_connector *)connector, mode_in);
5463 timing_out->vic = avi_frame.video_code;
5464 drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, (struct drm_connector *)connector, mode_in);
5465 timing_out->hdmi_vic = hv_frame.vic;
5468 if (is_freesync_video_mode(mode_in, aconnector)) {
5469 timing_out->h_addressable = mode_in->hdisplay;
5470 timing_out->h_total = mode_in->htotal;
5471 timing_out->h_sync_width = mode_in->hsync_end - mode_in->hsync_start;
5472 timing_out->h_front_porch = mode_in->hsync_start - mode_in->hdisplay;
5473 timing_out->v_total = mode_in->vtotal;
5474 timing_out->v_addressable = mode_in->vdisplay;
5475 timing_out->v_front_porch = mode_in->vsync_start - mode_in->vdisplay;
5476 timing_out->v_sync_width = mode_in->vsync_end - mode_in->vsync_start;
5477 timing_out->pix_clk_100hz = mode_in->clock * 10;
5479 timing_out->h_addressable = mode_in->crtc_hdisplay;
5480 timing_out->h_total = mode_in->crtc_htotal;
5481 timing_out->h_sync_width = mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
5482 timing_out->h_front_porch = mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
5483 timing_out->v_total = mode_in->crtc_vtotal;
5484 timing_out->v_addressable = mode_in->crtc_vdisplay;
5485 timing_out->v_front_porch = mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
5486 timing_out->v_sync_width = mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
5487 timing_out->pix_clk_100hz = mode_in->crtc_clock * 10;
5490 timing_out->aspect_ratio = get_aspect_ratio(mode_in);
5492 stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
5493 stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
5494 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
5495 if (!adjust_colour_depth_from_display_info(timing_out, info) &&
5496 drm_mode_is_420_also(info, mode_in) &&
5497 timing_out->pixel_encoding != PIXEL_ENCODING_YCBCR420) {
5498 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5499 adjust_colour_depth_from_display_info(timing_out, info);
5503 stream->output_color_space = get_output_color_space(timing_out);
5506 static void fill_audio_info(struct audio_info *audio_info,
5507 const struct drm_connector *drm_connector,
5508 const struct dc_sink *dc_sink)
5511 int cea_revision = 0;
5512 const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
5514 audio_info->manufacture_id = edid_caps->manufacturer_id;
5515 audio_info->product_id = edid_caps->product_id;
5517 cea_revision = drm_connector->display_info.cea_rev;
5519 strscpy(audio_info->display_name,
5520 edid_caps->display_name,
5521 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
5523 if (cea_revision >= 3) {
5524 audio_info->mode_count = edid_caps->audio_mode_count;
5526 for (i = 0; i < audio_info->mode_count; ++i) {
5527 audio_info->modes[i].format_code =
5528 (enum audio_format_code)
5529 (edid_caps->audio_modes[i].format_code);
5530 audio_info->modes[i].channel_count =
5531 edid_caps->audio_modes[i].channel_count;
5532 audio_info->modes[i].sample_rates.all =
5533 edid_caps->audio_modes[i].sample_rate;
5534 audio_info->modes[i].sample_size =
5535 edid_caps->audio_modes[i].sample_size;
5539 audio_info->flags.all = edid_caps->speaker_flags;
5541 /* TODO: We only check for the progressive mode, check for interlace mode too */
5542 if (drm_connector->latency_present[0]) {
5543 audio_info->video_latency = drm_connector->video_latency[0];
5544 audio_info->audio_latency = drm_connector->audio_latency[0];
5547 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
5552 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
5553 struct drm_display_mode *dst_mode)
5555 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
5556 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
5557 dst_mode->crtc_clock = src_mode->crtc_clock;
5558 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
5559 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
5560 dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start;
5561 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
5562 dst_mode->crtc_htotal = src_mode->crtc_htotal;
5563 dst_mode->crtc_hskew = src_mode->crtc_hskew;
5564 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
5565 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
5566 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
5567 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
5568 dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
5572 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
5573 const struct drm_display_mode *native_mode,
5576 if (scale_enabled) {
5577 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
5578 } else if (native_mode->clock == drm_mode->clock &&
5579 native_mode->htotal == drm_mode->htotal &&
5580 native_mode->vtotal == drm_mode->vtotal) {
5581 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
5583 /* no scaling nor amdgpu inserted, no need to patch */
5587 static struct dc_sink *
5588 create_fake_sink(struct amdgpu_dm_connector *aconnector)
5590 struct dc_sink_init_data sink_init_data = { 0 };
5591 struct dc_sink *sink = NULL;
5592 sink_init_data.link = aconnector->dc_link;
5593 sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
5595 sink = dc_sink_create(&sink_init_data);
5597 DRM_ERROR("Failed to create sink!\n");
5600 sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
5605 static void set_multisync_trigger_params(
5606 struct dc_stream_state *stream)
5608 struct dc_stream_state *master = NULL;
5610 if (stream->triggered_crtc_reset.enabled) {
5611 master = stream->triggered_crtc_reset.event_source;
5612 stream->triggered_crtc_reset.event =
5613 master->timing.flags.VSYNC_POSITIVE_POLARITY ?
5614 CRTC_EVENT_VSYNC_RISING : CRTC_EVENT_VSYNC_FALLING;
5615 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_PIXEL;
5619 static void set_master_stream(struct dc_stream_state *stream_set[],
5622 int j, highest_rfr = 0, master_stream = 0;
5624 for (j = 0; j < stream_count; j++) {
5625 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
5626 int refresh_rate = 0;
5628 refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/
5629 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
5630 if (refresh_rate > highest_rfr) {
5631 highest_rfr = refresh_rate;
5636 for (j = 0; j < stream_count; j++) {
5638 stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
5642 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
5645 struct dc_stream_state *stream;
5647 if (context->stream_count < 2)
5649 for (i = 0; i < context->stream_count ; i++) {
5650 if (!context->streams[i])
5653 * TODO: add a function to read AMD VSDB bits and set
5654 * crtc_sync_master.multi_sync_enabled flag
5655 * For now it's set to false
5659 set_master_stream(context->streams, context->stream_count);
5661 for (i = 0; i < context->stream_count ; i++) {
5662 stream = context->streams[i];
5667 set_multisync_trigger_params(stream);
5672 * DOC: FreeSync Video
5674 * When a userspace application wants to play a video, the content follows a
5675 * standard format definition that usually specifies the FPS for that format.
5676 * The below list illustrates some video format and the expected FPS,
5679 * - TV/NTSC (23.976 FPS)
5682 * - TV/NTSC (29.97 FPS)
5683 * - TV/NTSC (30 FPS)
5684 * - Cinema HFR (48 FPS)
5686 * - Commonly used (60 FPS)
5687 * - Multiples of 24 (48,72,96 FPS)
5689 * The list of standards video format is not huge and can be added to the
5690 * connector modeset list beforehand. With that, userspace can leverage
5691 * FreeSync to extends the front porch in order to attain the target refresh
5692 * rate. Such a switch will happen seamlessly, without screen blanking or
5693 * reprogramming of the output in any other way. If the userspace requests a
5694 * modesetting change compatible with FreeSync modes that only differ in the
5695 * refresh rate, DC will skip the full update and avoid blink during the
5696 * transition. For example, the video player can change the modesetting from
5697 * 60Hz to 30Hz for playing TV/NTSC content when it goes full screen without
5698 * causing any display blink. This same concept can be applied to a mode
5701 static struct drm_display_mode *
5702 get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector,
5703 bool use_probed_modes)
5705 struct drm_display_mode *m, *m_pref = NULL;
5706 u16 current_refresh, highest_refresh;
5707 struct list_head *list_head = use_probed_modes ?
5708 &aconnector->base.probed_modes :
5709 &aconnector->base.modes;
5711 if (aconnector->freesync_vid_base.clock != 0)
5712 return &aconnector->freesync_vid_base;
5714 /* Find the preferred mode */
5715 list_for_each_entry (m, list_head, head) {
5716 if (m->type & DRM_MODE_TYPE_PREFERRED) {
5723 /* Probably an EDID with no preferred mode. Fallback to first entry */
5724 m_pref = list_first_entry_or_null(
5725 &aconnector->base.modes, struct drm_display_mode, head);
5727 DRM_DEBUG_DRIVER("No preferred mode found in EDID\n");
5732 highest_refresh = drm_mode_vrefresh(m_pref);
5735 * Find the mode with highest refresh rate with same resolution.
5736 * For some monitors, preferred mode is not the mode with highest
5737 * supported refresh rate.
5739 list_for_each_entry (m, list_head, head) {
5740 current_refresh = drm_mode_vrefresh(m);
5742 if (m->hdisplay == m_pref->hdisplay &&
5743 m->vdisplay == m_pref->vdisplay &&
5744 highest_refresh < current_refresh) {
5745 highest_refresh = current_refresh;
5750 drm_mode_copy(&aconnector->freesync_vid_base, m_pref);
5754 static bool is_freesync_video_mode(const struct drm_display_mode *mode,
5755 struct amdgpu_dm_connector *aconnector)
5757 struct drm_display_mode *high_mode;
5760 high_mode = get_highest_refresh_rate_mode(aconnector, false);
5761 if (!high_mode || !mode)
5764 timing_diff = high_mode->vtotal - mode->vtotal;
5766 if (high_mode->clock == 0 || high_mode->clock != mode->clock ||
5767 high_mode->hdisplay != mode->hdisplay ||
5768 high_mode->vdisplay != mode->vdisplay ||
5769 high_mode->hsync_start != mode->hsync_start ||
5770 high_mode->hsync_end != mode->hsync_end ||
5771 high_mode->htotal != mode->htotal ||
5772 high_mode->hskew != mode->hskew ||
5773 high_mode->vscan != mode->vscan ||
5774 high_mode->vsync_start - mode->vsync_start != timing_diff ||
5775 high_mode->vsync_end - mode->vsync_end != timing_diff)
5781 static void update_dsc_caps(struct amdgpu_dm_connector *aconnector,
5782 struct dc_sink *sink, struct dc_stream_state *stream,
5783 struct dsc_dec_dpcd_caps *dsc_caps)
5785 stream->timing.flags.DSC = 0;
5786 dsc_caps->is_dsc_supported = false;
5788 if (aconnector->dc_link && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT ||
5789 sink->sink_signal == SIGNAL_TYPE_EDP)) {
5790 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE ||
5791 sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER)
5792 dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
5793 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
5794 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
5800 static void apply_dsc_policy_for_edp(struct amdgpu_dm_connector *aconnector,
5801 struct dc_sink *sink, struct dc_stream_state *stream,
5802 struct dsc_dec_dpcd_caps *dsc_caps,
5803 uint32_t max_dsc_target_bpp_limit_override)
5805 const struct dc_link_settings *verified_link_cap = NULL;
5806 u32 link_bw_in_kbps;
5807 u32 edp_min_bpp_x16, edp_max_bpp_x16;
5808 struct dc *dc = sink->ctx->dc;
5809 struct dc_dsc_bw_range bw_range = {0};
5810 struct dc_dsc_config dsc_cfg = {0};
5811 struct dc_dsc_config_options dsc_options = {0};
5813 dc_dsc_get_default_config_option(dc, &dsc_options);
5814 dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16;
5816 verified_link_cap = dc_link_get_link_cap(stream->link);
5817 link_bw_in_kbps = dc_link_bandwidth_kbps(stream->link, verified_link_cap);
5818 edp_min_bpp_x16 = 8 * 16;
5819 edp_max_bpp_x16 = 8 * 16;
5821 if (edp_max_bpp_x16 > dsc_caps->edp_max_bits_per_pixel)
5822 edp_max_bpp_x16 = dsc_caps->edp_max_bits_per_pixel;
5824 if (edp_max_bpp_x16 < edp_min_bpp_x16)
5825 edp_min_bpp_x16 = edp_max_bpp_x16;
5827 if (dc_dsc_compute_bandwidth_range(dc->res_pool->dscs[0],
5828 dc->debug.dsc_min_slice_height_override,
5829 edp_min_bpp_x16, edp_max_bpp_x16,
5834 if (bw_range.max_kbps < link_bw_in_kbps) {
5835 if (dc_dsc_compute_config(dc->res_pool->dscs[0],
5841 stream->timing.dsc_cfg = dsc_cfg;
5842 stream->timing.flags.DSC = 1;
5843 stream->timing.dsc_cfg.bits_per_pixel = edp_max_bpp_x16;
5849 if (dc_dsc_compute_config(dc->res_pool->dscs[0],
5855 stream->timing.dsc_cfg = dsc_cfg;
5856 stream->timing.flags.DSC = 1;
5861 static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector,
5862 struct dc_sink *sink, struct dc_stream_state *stream,
5863 struct dsc_dec_dpcd_caps *dsc_caps)
5865 struct drm_connector *drm_connector = &aconnector->base;
5866 u32 link_bandwidth_kbps;
5867 struct dc *dc = sink->ctx->dc;
5868 u32 max_supported_bw_in_kbps, timing_bw_in_kbps;
5869 u32 dsc_max_supported_bw_in_kbps;
5870 u32 max_dsc_target_bpp_limit_override =
5871 drm_connector->display_info.max_dsc_bpp;
5872 struct dc_dsc_config_options dsc_options = {0};
5874 dc_dsc_get_default_config_option(dc, &dsc_options);
5875 dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16;
5877 link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
5878 dc_link_get_link_cap(aconnector->dc_link));
5880 /* Set DSC policy according to dsc_clock_en */
5881 dc_dsc_policy_set_enable_dsc_when_not_needed(
5882 aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE);
5884 if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_EDP &&
5885 !aconnector->dc_link->panel_config.dsc.disable_dsc_edp &&
5886 dc->caps.edp_dsc_support && aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE) {
5888 apply_dsc_policy_for_edp(aconnector, sink, stream, dsc_caps, max_dsc_target_bpp_limit_override);
5890 } else if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) {
5891 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) {
5892 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
5895 link_bandwidth_kbps,
5897 &stream->timing.dsc_cfg)) {
5898 stream->timing.flags.DSC = 1;
5899 DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from SST RX\n", __func__, drm_connector->name);
5901 } else if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) {
5902 timing_bw_in_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing);
5903 max_supported_bw_in_kbps = link_bandwidth_kbps;
5904 dsc_max_supported_bw_in_kbps = link_bandwidth_kbps;
5906 if (timing_bw_in_kbps > max_supported_bw_in_kbps &&
5907 max_supported_bw_in_kbps > 0 &&
5908 dsc_max_supported_bw_in_kbps > 0)
5909 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
5912 dsc_max_supported_bw_in_kbps,
5914 &stream->timing.dsc_cfg)) {
5915 stream->timing.flags.DSC = 1;
5916 DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from DP-HDMI PCON\n",
5917 __func__, drm_connector->name);
5922 /* Overwrite the stream flag if DSC is enabled through debugfs */
5923 if (aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE)
5924 stream->timing.flags.DSC = 1;
5926 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_h)
5927 stream->timing.dsc_cfg.num_slices_h = aconnector->dsc_settings.dsc_num_slices_h;
5929 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_v)
5930 stream->timing.dsc_cfg.num_slices_v = aconnector->dsc_settings.dsc_num_slices_v;
5932 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_bits_per_pixel)
5933 stream->timing.dsc_cfg.bits_per_pixel = aconnector->dsc_settings.dsc_bits_per_pixel;
5936 static struct dc_stream_state *
5937 create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
5938 const struct drm_display_mode *drm_mode,
5939 const struct dm_connector_state *dm_state,
5940 const struct dc_stream_state *old_stream,
5943 struct drm_display_mode *preferred_mode = NULL;
5944 struct drm_connector *drm_connector;
5945 const struct drm_connector_state *con_state =
5946 dm_state ? &dm_state->base : NULL;
5947 struct dc_stream_state *stream = NULL;
5948 struct drm_display_mode mode;
5949 struct drm_display_mode saved_mode;
5950 struct drm_display_mode *freesync_mode = NULL;
5951 bool native_mode_found = false;
5952 bool recalculate_timing = false;
5953 bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false;
5955 int preferred_refresh = 0;
5956 enum color_transfer_func tf = TRANSFER_FUNC_UNKNOWN;
5957 struct dsc_dec_dpcd_caps dsc_caps;
5959 struct dc_sink *sink = NULL;
5961 drm_mode_init(&mode, drm_mode);
5962 memset(&saved_mode, 0, sizeof(saved_mode));
5964 if (aconnector == NULL) {
5965 DRM_ERROR("aconnector is NULL!\n");
5969 drm_connector = &aconnector->base;
5971 if (!aconnector->dc_sink) {
5972 sink = create_fake_sink(aconnector);
5976 sink = aconnector->dc_sink;
5977 dc_sink_retain(sink);
5980 stream = dc_create_stream_for_sink(sink);
5982 if (stream == NULL) {
5983 DRM_ERROR("Failed to create stream for sink!\n");
5987 stream->dm_stream_context = aconnector;
5989 stream->timing.flags.LTE_340MCSC_SCRAMBLE =
5990 drm_connector->display_info.hdmi.scdc.scrambling.low_rates;
5992 list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
5993 /* Search for preferred mode */
5994 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
5995 native_mode_found = true;
5999 if (!native_mode_found)
6000 preferred_mode = list_first_entry_or_null(
6001 &aconnector->base.modes,
6002 struct drm_display_mode,
6005 mode_refresh = drm_mode_vrefresh(&mode);
6007 if (preferred_mode == NULL) {
6009 * This may not be an error, the use case is when we have no
6010 * usermode calls to reset and set mode upon hotplug. In this
6011 * case, we call set mode ourselves to restore the previous mode
6012 * and the modelist may not be filled in in time.
6014 DRM_DEBUG_DRIVER("No preferred mode found\n");
6016 recalculate_timing = amdgpu_freesync_vid_mode &&
6017 is_freesync_video_mode(&mode, aconnector);
6018 if (recalculate_timing) {
6019 freesync_mode = get_highest_refresh_rate_mode(aconnector, false);
6020 drm_mode_copy(&saved_mode, &mode);
6021 drm_mode_copy(&mode, freesync_mode);
6023 decide_crtc_timing_for_drm_display_mode(
6024 &mode, preferred_mode, scale);
6026 preferred_refresh = drm_mode_vrefresh(preferred_mode);
6030 if (recalculate_timing)
6031 drm_mode_set_crtcinfo(&saved_mode, 0);
6033 drm_mode_set_crtcinfo(&mode, 0);
6036 * If scaling is enabled and refresh rate didn't change
6037 * we copy the vic and polarities of the old timings
6039 if (!scale || mode_refresh != preferred_refresh)
6040 fill_stream_properties_from_drm_display_mode(
6041 stream, &mode, &aconnector->base, con_state, NULL,
6044 fill_stream_properties_from_drm_display_mode(
6045 stream, &mode, &aconnector->base, con_state, old_stream,
6048 if (aconnector->timing_changed) {
6049 DC_LOG_DEBUG("%s: overriding timing for automated test, bpc %d, changing to %d\n",
6051 stream->timing.display_color_depth,
6052 aconnector->timing_requested->display_color_depth);
6053 stream->timing = *aconnector->timing_requested;
6056 /* SST DSC determination policy */
6057 update_dsc_caps(aconnector, sink, stream, &dsc_caps);
6058 if (aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE && dsc_caps.is_dsc_supported)
6059 apply_dsc_policy_for_stream(aconnector, sink, stream, &dsc_caps);
6061 update_stream_scaling_settings(&mode, dm_state, stream);
6064 &stream->audio_info,
6068 update_stream_signal(stream, sink);
6070 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
6071 mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket);
6073 if (stream->link->psr_settings.psr_feature_enabled) {
6075 // should decide stream support vsc sdp colorimetry capability
6076 // before building vsc info packet
6078 stream->use_vsc_sdp_for_colorimetry = false;
6079 if (aconnector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
6080 stream->use_vsc_sdp_for_colorimetry =
6081 aconnector->dc_sink->is_vsc_sdp_colorimetry_supported;
6083 if (stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED)
6084 stream->use_vsc_sdp_for_colorimetry = true;
6086 if (stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22)
6087 tf = TRANSFER_FUNC_GAMMA_22;
6088 mod_build_vsc_infopacket(stream, &stream->vsc_infopacket, stream->output_color_space, tf);
6089 aconnector->psr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY;
6093 dc_sink_release(sink);
6098 static enum drm_connector_status
6099 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
6102 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6106 * 1. This interface is NOT called in context of HPD irq.
6107 * 2. This interface *is called* in context of user-mode ioctl. Which
6108 * makes it a bad place for *any* MST-related activity.
6111 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
6112 !aconnector->fake_enable)
6113 connected = (aconnector->dc_sink != NULL);
6115 connected = (aconnector->base.force == DRM_FORCE_ON ||
6116 aconnector->base.force == DRM_FORCE_ON_DIGITAL);
6118 update_subconnector_property(aconnector);
6120 return (connected ? connector_status_connected :
6121 connector_status_disconnected);
6124 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
6125 struct drm_connector_state *connector_state,
6126 struct drm_property *property,
6129 struct drm_device *dev = connector->dev;
6130 struct amdgpu_device *adev = drm_to_adev(dev);
6131 struct dm_connector_state *dm_old_state =
6132 to_dm_connector_state(connector->state);
6133 struct dm_connector_state *dm_new_state =
6134 to_dm_connector_state(connector_state);
6138 if (property == dev->mode_config.scaling_mode_property) {
6139 enum amdgpu_rmx_type rmx_type;
6142 case DRM_MODE_SCALE_CENTER:
6143 rmx_type = RMX_CENTER;
6145 case DRM_MODE_SCALE_ASPECT:
6146 rmx_type = RMX_ASPECT;
6148 case DRM_MODE_SCALE_FULLSCREEN:
6149 rmx_type = RMX_FULL;
6151 case DRM_MODE_SCALE_NONE:
6157 if (dm_old_state->scaling == rmx_type)
6160 dm_new_state->scaling = rmx_type;
6162 } else if (property == adev->mode_info.underscan_hborder_property) {
6163 dm_new_state->underscan_hborder = val;
6165 } else if (property == adev->mode_info.underscan_vborder_property) {
6166 dm_new_state->underscan_vborder = val;
6168 } else if (property == adev->mode_info.underscan_property) {
6169 dm_new_state->underscan_enable = val;
6171 } else if (property == adev->mode_info.abm_level_property) {
6172 dm_new_state->abm_level = val;
6179 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
6180 const struct drm_connector_state *state,
6181 struct drm_property *property,
6184 struct drm_device *dev = connector->dev;
6185 struct amdgpu_device *adev = drm_to_adev(dev);
6186 struct dm_connector_state *dm_state =
6187 to_dm_connector_state(state);
6190 if (property == dev->mode_config.scaling_mode_property) {
6191 switch (dm_state->scaling) {
6193 *val = DRM_MODE_SCALE_CENTER;
6196 *val = DRM_MODE_SCALE_ASPECT;
6199 *val = DRM_MODE_SCALE_FULLSCREEN;
6203 *val = DRM_MODE_SCALE_NONE;
6207 } else if (property == adev->mode_info.underscan_hborder_property) {
6208 *val = dm_state->underscan_hborder;
6210 } else if (property == adev->mode_info.underscan_vborder_property) {
6211 *val = dm_state->underscan_vborder;
6213 } else if (property == adev->mode_info.underscan_property) {
6214 *val = dm_state->underscan_enable;
6216 } else if (property == adev->mode_info.abm_level_property) {
6217 *val = dm_state->abm_level;
6224 static void amdgpu_dm_connector_unregister(struct drm_connector *connector)
6226 struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector);
6228 drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux);
6231 static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
6233 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6234 struct amdgpu_device *adev = drm_to_adev(connector->dev);
6235 struct amdgpu_display_manager *dm = &adev->dm;
6238 * Call only if mst_mgr was initialized before since it's not done
6239 * for all connector types.
6241 if (aconnector->mst_mgr.dev)
6242 drm_dp_mst_topology_mgr_destroy(&aconnector->mst_mgr);
6244 if (aconnector->bl_idx != -1) {
6245 backlight_device_unregister(dm->backlight_dev[aconnector->bl_idx]);
6246 dm->backlight_dev[aconnector->bl_idx] = NULL;
6249 if (aconnector->dc_em_sink)
6250 dc_sink_release(aconnector->dc_em_sink);
6251 aconnector->dc_em_sink = NULL;
6252 if (aconnector->dc_sink)
6253 dc_sink_release(aconnector->dc_sink);
6254 aconnector->dc_sink = NULL;
6256 drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux);
6257 drm_connector_unregister(connector);
6258 drm_connector_cleanup(connector);
6259 if (aconnector->i2c) {
6260 i2c_del_adapter(&aconnector->i2c->base);
6261 kfree(aconnector->i2c);
6263 kfree(aconnector->dm_dp_aux.aux.name);
6268 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
6270 struct dm_connector_state *state =
6271 to_dm_connector_state(connector->state);
6273 if (connector->state)
6274 __drm_atomic_helper_connector_destroy_state(connector->state);
6278 state = kzalloc(sizeof(*state), GFP_KERNEL);
6281 state->scaling = RMX_OFF;
6282 state->underscan_enable = false;
6283 state->underscan_hborder = 0;
6284 state->underscan_vborder = 0;
6285 state->base.max_requested_bpc = 8;
6286 state->vcpi_slots = 0;
6289 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
6290 state->abm_level = amdgpu_dm_abm_level;
6292 __drm_atomic_helper_connector_reset(connector, &state->base);
6296 struct drm_connector_state *
6297 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
6299 struct dm_connector_state *state =
6300 to_dm_connector_state(connector->state);
6302 struct dm_connector_state *new_state =
6303 kmemdup(state, sizeof(*state), GFP_KERNEL);
6308 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
6310 new_state->freesync_capable = state->freesync_capable;
6311 new_state->abm_level = state->abm_level;
6312 new_state->scaling = state->scaling;
6313 new_state->underscan_enable = state->underscan_enable;
6314 new_state->underscan_hborder = state->underscan_hborder;
6315 new_state->underscan_vborder = state->underscan_vborder;
6316 new_state->vcpi_slots = state->vcpi_slots;
6317 new_state->pbn = state->pbn;
6318 return &new_state->base;
6322 amdgpu_dm_connector_late_register(struct drm_connector *connector)
6324 struct amdgpu_dm_connector *amdgpu_dm_connector =
6325 to_amdgpu_dm_connector(connector);
6328 amdgpu_dm_register_backlight_device(amdgpu_dm_connector);
6330 if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
6331 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
6332 amdgpu_dm_connector->dm_dp_aux.aux.dev = connector->kdev;
6333 r = drm_dp_aux_register(&amdgpu_dm_connector->dm_dp_aux.aux);
6338 #if defined(CONFIG_DEBUG_FS)
6339 connector_debugfs_init(amdgpu_dm_connector);
6345 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
6346 .reset = amdgpu_dm_connector_funcs_reset,
6347 .detect = amdgpu_dm_connector_detect,
6348 .fill_modes = drm_helper_probe_single_connector_modes,
6349 .destroy = amdgpu_dm_connector_destroy,
6350 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
6351 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
6352 .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
6353 .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
6354 .late_register = amdgpu_dm_connector_late_register,
6355 .early_unregister = amdgpu_dm_connector_unregister
6358 static int get_modes(struct drm_connector *connector)
6360 return amdgpu_dm_connector_get_modes(connector);
6363 static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
6365 struct dc_sink_init_data init_params = {
6366 .link = aconnector->dc_link,
6367 .sink_signal = SIGNAL_TYPE_VIRTUAL
6371 if (!aconnector->base.edid_blob_ptr) {
6372 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
6373 aconnector->base.name);
6375 aconnector->base.force = DRM_FORCE_OFF;
6379 edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
6381 aconnector->edid = edid;
6383 aconnector->dc_em_sink = dc_link_add_remote_sink(
6384 aconnector->dc_link,
6386 (edid->extensions + 1) * EDID_LENGTH,
6389 if (aconnector->base.force == DRM_FORCE_ON) {
6390 aconnector->dc_sink = aconnector->dc_link->local_sink ?
6391 aconnector->dc_link->local_sink :
6392 aconnector->dc_em_sink;
6393 dc_sink_retain(aconnector->dc_sink);
6397 static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
6399 struct dc_link *link = (struct dc_link *)aconnector->dc_link;
6402 * In case of headless boot with force on for DP managed connector
6403 * Those settings have to be != 0 to get initial modeset
6405 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
6406 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
6407 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
6410 create_eml_sink(aconnector);
6413 static enum dc_status dm_validate_stream_and_context(struct dc *dc,
6414 struct dc_stream_state *stream)
6416 enum dc_status dc_result = DC_ERROR_UNEXPECTED;
6417 struct dc_plane_state *dc_plane_state = NULL;
6418 struct dc_state *dc_state = NULL;
6423 dc_plane_state = dc_create_plane_state(dc);
6424 if (!dc_plane_state)
6427 dc_state = dc_create_state(dc);
6431 /* populate stream to plane */
6432 dc_plane_state->src_rect.height = stream->src.height;
6433 dc_plane_state->src_rect.width = stream->src.width;
6434 dc_plane_state->dst_rect.height = stream->src.height;
6435 dc_plane_state->dst_rect.width = stream->src.width;
6436 dc_plane_state->clip_rect.height = stream->src.height;
6437 dc_plane_state->clip_rect.width = stream->src.width;
6438 dc_plane_state->plane_size.surface_pitch = ((stream->src.width + 255) / 256) * 256;
6439 dc_plane_state->plane_size.surface_size.height = stream->src.height;
6440 dc_plane_state->plane_size.surface_size.width = stream->src.width;
6441 dc_plane_state->plane_size.chroma_size.height = stream->src.height;
6442 dc_plane_state->plane_size.chroma_size.width = stream->src.width;
6443 dc_plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
6444 dc_plane_state->tiling_info.gfx9.swizzle = DC_SW_UNKNOWN;
6445 dc_plane_state->rotation = ROTATION_ANGLE_0;
6446 dc_plane_state->is_tiling_rotated = false;
6447 dc_plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_LINEAR_GENERAL;
6449 dc_result = dc_validate_stream(dc, stream);
6450 if (dc_result == DC_OK)
6451 dc_result = dc_validate_plane(dc, dc_plane_state);
6453 if (dc_result == DC_OK)
6454 dc_result = dc_add_stream_to_ctx(dc, dc_state, stream);
6456 if (dc_result == DC_OK && !dc_add_plane_to_context(
6461 dc_result = DC_FAIL_ATTACH_SURFACES;
6463 if (dc_result == DC_OK)
6464 dc_result = dc_validate_global_state(dc, dc_state, true);
6468 dc_release_state(dc_state);
6471 dc_plane_state_release(dc_plane_state);
6476 struct dc_stream_state *
6477 create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector,
6478 const struct drm_display_mode *drm_mode,
6479 const struct dm_connector_state *dm_state,
6480 const struct dc_stream_state *old_stream)
6482 struct drm_connector *connector = &aconnector->base;
6483 struct amdgpu_device *adev = drm_to_adev(connector->dev);
6484 struct dc_stream_state *stream;
6485 const struct drm_connector_state *drm_state = dm_state ? &dm_state->base : NULL;
6486 int requested_bpc = drm_state ? drm_state->max_requested_bpc : 8;
6487 enum dc_status dc_result = DC_OK;
6490 stream = create_stream_for_sink(aconnector, drm_mode,
6491 dm_state, old_stream,
6493 if (stream == NULL) {
6494 DRM_ERROR("Failed to create stream for sink!\n");
6498 dc_result = dc_validate_stream(adev->dm.dc, stream);
6499 if (dc_result == DC_OK && stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
6500 dc_result = dm_dp_mst_is_port_support_mode(aconnector, stream);
6502 if (dc_result == DC_OK)
6503 dc_result = dm_validate_stream_and_context(adev->dm.dc, stream);
6505 if (dc_result != DC_OK) {
6506 DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n",
6511 dc_status_to_str(dc_result));
6513 dc_stream_release(stream);
6515 requested_bpc -= 2; /* lower bpc to retry validation */
6518 } while (stream == NULL && requested_bpc >= 6);
6520 if (dc_result == DC_FAIL_ENC_VALIDATE && !aconnector->force_yuv420_output) {
6521 DRM_DEBUG_KMS("Retry forcing YCbCr420 encoding\n");
6523 aconnector->force_yuv420_output = true;
6524 stream = create_validate_stream_for_sink(aconnector, drm_mode,
6525 dm_state, old_stream);
6526 aconnector->force_yuv420_output = false;
6532 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
6533 struct drm_display_mode *mode)
6535 int result = MODE_ERROR;
6536 struct dc_sink *dc_sink;
6537 /* TODO: Unhardcode stream count */
6538 struct dc_stream_state *stream;
6539 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6541 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
6542 (mode->flags & DRM_MODE_FLAG_DBLSCAN))
6546 * Only run this the first time mode_valid is called to initilialize
6549 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
6550 !aconnector->dc_em_sink)
6551 handle_edid_mgmt(aconnector);
6553 dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
6555 if (dc_sink == NULL && aconnector->base.force != DRM_FORCE_ON_DIGITAL &&
6556 aconnector->base.force != DRM_FORCE_ON) {
6557 DRM_ERROR("dc_sink is NULL!\n");
6561 stream = create_validate_stream_for_sink(aconnector, mode, NULL, NULL);
6563 dc_stream_release(stream);
6568 /* TODO: error handling*/
6572 static int fill_hdr_info_packet(const struct drm_connector_state *state,
6573 struct dc_info_packet *out)
6575 struct hdmi_drm_infoframe frame;
6576 unsigned char buf[30]; /* 26 + 4 */
6580 memset(out, 0, sizeof(*out));
6582 if (!state->hdr_output_metadata)
6585 ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state);
6589 len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf));
6593 /* Static metadata is a fixed 26 bytes + 4 byte header. */
6597 /* Prepare the infopacket for DC. */
6598 switch (state->connector->connector_type) {
6599 case DRM_MODE_CONNECTOR_HDMIA:
6600 out->hb0 = 0x87; /* type */
6601 out->hb1 = 0x01; /* version */
6602 out->hb2 = 0x1A; /* length */
6603 out->sb[0] = buf[3]; /* checksum */
6607 case DRM_MODE_CONNECTOR_DisplayPort:
6608 case DRM_MODE_CONNECTOR_eDP:
6609 out->hb0 = 0x00; /* sdp id, zero */
6610 out->hb1 = 0x87; /* type */
6611 out->hb2 = 0x1D; /* payload len - 1 */
6612 out->hb3 = (0x13 << 2); /* sdp version */
6613 out->sb[0] = 0x01; /* version */
6614 out->sb[1] = 0x1A; /* length */
6622 memcpy(&out->sb[i], &buf[4], 26);
6625 print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb,
6626 sizeof(out->sb), false);
6632 amdgpu_dm_connector_atomic_check(struct drm_connector *conn,
6633 struct drm_atomic_state *state)
6635 struct drm_connector_state *new_con_state =
6636 drm_atomic_get_new_connector_state(state, conn);
6637 struct drm_connector_state *old_con_state =
6638 drm_atomic_get_old_connector_state(state, conn);
6639 struct drm_crtc *crtc = new_con_state->crtc;
6640 struct drm_crtc_state *new_crtc_state;
6641 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(conn);
6644 trace_amdgpu_dm_connector_atomic_check(new_con_state);
6646 if (conn->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
6647 ret = drm_dp_mst_root_conn_atomic_check(new_con_state, &aconn->mst_mgr);
6655 if (!drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state)) {
6656 struct dc_info_packet hdr_infopacket;
6658 ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket);
6662 new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
6663 if (IS_ERR(new_crtc_state))
6664 return PTR_ERR(new_crtc_state);
6667 * DC considers the stream backends changed if the
6668 * static metadata changes. Forcing the modeset also
6669 * gives a simple way for userspace to switch from
6670 * 8bpc to 10bpc when setting the metadata to enter
6673 * Changing the static metadata after it's been
6674 * set is permissible, however. So only force a
6675 * modeset if we're entering or exiting HDR.
6677 new_crtc_state->mode_changed =
6678 !old_con_state->hdr_output_metadata ||
6679 !new_con_state->hdr_output_metadata;
6685 static const struct drm_connector_helper_funcs
6686 amdgpu_dm_connector_helper_funcs = {
6688 * If hotplugging a second bigger display in FB Con mode, bigger resolution
6689 * modes will be filtered by drm_mode_validate_size(), and those modes
6690 * are missing after user start lightdm. So we need to renew modes list.
6691 * in get_modes call back, not just return the modes count
6693 .get_modes = get_modes,
6694 .mode_valid = amdgpu_dm_connector_mode_valid,
6695 .atomic_check = amdgpu_dm_connector_atomic_check,
6698 static void dm_encoder_helper_disable(struct drm_encoder *encoder)
6703 int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth)
6705 switch (display_color_depth) {
6706 case COLOR_DEPTH_666:
6708 case COLOR_DEPTH_888:
6710 case COLOR_DEPTH_101010:
6712 case COLOR_DEPTH_121212:
6714 case COLOR_DEPTH_141414:
6716 case COLOR_DEPTH_161616:
6724 static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
6725 struct drm_crtc_state *crtc_state,
6726 struct drm_connector_state *conn_state)
6728 struct drm_atomic_state *state = crtc_state->state;
6729 struct drm_connector *connector = conn_state->connector;
6730 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6731 struct dm_connector_state *dm_new_connector_state = to_dm_connector_state(conn_state);
6732 const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
6733 struct drm_dp_mst_topology_mgr *mst_mgr;
6734 struct drm_dp_mst_port *mst_port;
6735 struct drm_dp_mst_topology_state *mst_state;
6736 enum dc_color_depth color_depth;
6738 bool is_y420 = false;
6740 if (!aconnector->mst_output_port || !aconnector->dc_sink)
6743 mst_port = aconnector->mst_output_port;
6744 mst_mgr = &aconnector->mst_root->mst_mgr;
6746 if (!crtc_state->connectors_changed && !crtc_state->mode_changed)
6749 mst_state = drm_atomic_get_mst_topology_state(state, mst_mgr);
6750 if (IS_ERR(mst_state))
6751 return PTR_ERR(mst_state);
6753 if (!mst_state->pbn_div)
6754 mst_state->pbn_div = dm_mst_get_pbn_divider(aconnector->mst_root->dc_link);
6756 if (!state->duplicated) {
6757 int max_bpc = conn_state->max_requested_bpc;
6758 is_y420 = drm_mode_is_420_also(&connector->display_info, adjusted_mode) &&
6759 aconnector->force_yuv420_output;
6760 color_depth = convert_color_depth_from_display_info(connector,
6763 bpp = convert_dc_color_depth_into_bpc(color_depth) * 3;
6764 clock = adjusted_mode->clock;
6765 dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp, false);
6768 dm_new_connector_state->vcpi_slots =
6769 drm_dp_atomic_find_time_slots(state, mst_mgr, mst_port,
6770 dm_new_connector_state->pbn);
6771 if (dm_new_connector_state->vcpi_slots < 0) {
6772 DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots);
6773 return dm_new_connector_state->vcpi_slots;
6778 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
6779 .disable = dm_encoder_helper_disable,
6780 .atomic_check = dm_encoder_helper_atomic_check
6783 static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state,
6784 struct dc_state *dc_state,
6785 struct dsc_mst_fairness_vars *vars)
6787 struct dc_stream_state *stream = NULL;
6788 struct drm_connector *connector;
6789 struct drm_connector_state *new_con_state;
6790 struct amdgpu_dm_connector *aconnector;
6791 struct dm_connector_state *dm_conn_state;
6793 int vcpi, pbn_div, pbn, slot_num = 0;
6795 for_each_new_connector_in_state(state, connector, new_con_state, i) {
6797 aconnector = to_amdgpu_dm_connector(connector);
6799 if (!aconnector->mst_output_port)
6802 if (!new_con_state || !new_con_state->crtc)
6805 dm_conn_state = to_dm_connector_state(new_con_state);
6807 for (j = 0; j < dc_state->stream_count; j++) {
6808 stream = dc_state->streams[j];
6812 if ((struct amdgpu_dm_connector *)stream->dm_stream_context == aconnector)
6821 pbn_div = dm_mst_get_pbn_divider(stream->link);
6822 /* pbn is calculated by compute_mst_dsc_configs_for_state*/
6823 for (j = 0; j < dc_state->stream_count; j++) {
6824 if (vars[j].aconnector == aconnector) {
6830 if (j == dc_state->stream_count)
6833 slot_num = DIV_ROUND_UP(pbn, pbn_div);
6835 if (stream->timing.flags.DSC != 1) {
6836 dm_conn_state->pbn = pbn;
6837 dm_conn_state->vcpi_slots = slot_num;
6839 ret = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port,
6840 dm_conn_state->pbn, false);
6847 vcpi = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, pbn, true);
6851 dm_conn_state->pbn = pbn;
6852 dm_conn_state->vcpi_slots = vcpi;
6857 static int to_drm_connector_type(enum signal_type st)
6860 case SIGNAL_TYPE_HDMI_TYPE_A:
6861 return DRM_MODE_CONNECTOR_HDMIA;
6862 case SIGNAL_TYPE_EDP:
6863 return DRM_MODE_CONNECTOR_eDP;
6864 case SIGNAL_TYPE_LVDS:
6865 return DRM_MODE_CONNECTOR_LVDS;
6866 case SIGNAL_TYPE_RGB:
6867 return DRM_MODE_CONNECTOR_VGA;
6868 case SIGNAL_TYPE_DISPLAY_PORT:
6869 case SIGNAL_TYPE_DISPLAY_PORT_MST:
6870 return DRM_MODE_CONNECTOR_DisplayPort;
6871 case SIGNAL_TYPE_DVI_DUAL_LINK:
6872 case SIGNAL_TYPE_DVI_SINGLE_LINK:
6873 return DRM_MODE_CONNECTOR_DVID;
6874 case SIGNAL_TYPE_VIRTUAL:
6875 return DRM_MODE_CONNECTOR_VIRTUAL;
6878 return DRM_MODE_CONNECTOR_Unknown;
6882 static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector)
6884 struct drm_encoder *encoder;
6886 /* There is only one encoder per connector */
6887 drm_connector_for_each_possible_encoder(connector, encoder)
6893 static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
6895 struct drm_encoder *encoder;
6896 struct amdgpu_encoder *amdgpu_encoder;
6898 encoder = amdgpu_dm_connector_to_encoder(connector);
6900 if (encoder == NULL)
6903 amdgpu_encoder = to_amdgpu_encoder(encoder);
6905 amdgpu_encoder->native_mode.clock = 0;
6907 if (!list_empty(&connector->probed_modes)) {
6908 struct drm_display_mode *preferred_mode = NULL;
6910 list_for_each_entry(preferred_mode,
6911 &connector->probed_modes,
6913 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
6914 amdgpu_encoder->native_mode = *preferred_mode;
6922 static struct drm_display_mode *
6923 amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
6925 int hdisplay, int vdisplay)
6927 struct drm_device *dev = encoder->dev;
6928 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
6929 struct drm_display_mode *mode = NULL;
6930 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
6932 mode = drm_mode_duplicate(dev, native_mode);
6937 mode->hdisplay = hdisplay;
6938 mode->vdisplay = vdisplay;
6939 mode->type &= ~DRM_MODE_TYPE_PREFERRED;
6940 strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
6946 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
6947 struct drm_connector *connector)
6949 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
6950 struct drm_display_mode *mode = NULL;
6951 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
6952 struct amdgpu_dm_connector *amdgpu_dm_connector =
6953 to_amdgpu_dm_connector(connector);
6957 char name[DRM_DISPLAY_MODE_LEN];
6960 } common_modes[] = {
6961 { "640x480", 640, 480},
6962 { "800x600", 800, 600},
6963 { "1024x768", 1024, 768},
6964 { "1280x720", 1280, 720},
6965 { "1280x800", 1280, 800},
6966 {"1280x1024", 1280, 1024},
6967 { "1440x900", 1440, 900},
6968 {"1680x1050", 1680, 1050},
6969 {"1600x1200", 1600, 1200},
6970 {"1920x1080", 1920, 1080},
6971 {"1920x1200", 1920, 1200}
6974 n = ARRAY_SIZE(common_modes);
6976 for (i = 0; i < n; i++) {
6977 struct drm_display_mode *curmode = NULL;
6978 bool mode_existed = false;
6980 if (common_modes[i].w > native_mode->hdisplay ||
6981 common_modes[i].h > native_mode->vdisplay ||
6982 (common_modes[i].w == native_mode->hdisplay &&
6983 common_modes[i].h == native_mode->vdisplay))
6986 list_for_each_entry(curmode, &connector->probed_modes, head) {
6987 if (common_modes[i].w == curmode->hdisplay &&
6988 common_modes[i].h == curmode->vdisplay) {
6989 mode_existed = true;
6997 mode = amdgpu_dm_create_common_mode(encoder,
6998 common_modes[i].name, common_modes[i].w,
7003 drm_mode_probed_add(connector, mode);
7004 amdgpu_dm_connector->num_modes++;
7008 static void amdgpu_set_panel_orientation(struct drm_connector *connector)
7010 struct drm_encoder *encoder;
7011 struct amdgpu_encoder *amdgpu_encoder;
7012 const struct drm_display_mode *native_mode;
7014 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP &&
7015 connector->connector_type != DRM_MODE_CONNECTOR_LVDS)
7018 mutex_lock(&connector->dev->mode_config.mutex);
7019 amdgpu_dm_connector_get_modes(connector);
7020 mutex_unlock(&connector->dev->mode_config.mutex);
7022 encoder = amdgpu_dm_connector_to_encoder(connector);
7026 amdgpu_encoder = to_amdgpu_encoder(encoder);
7028 native_mode = &amdgpu_encoder->native_mode;
7029 if (native_mode->hdisplay == 0 || native_mode->vdisplay == 0)
7032 drm_connector_set_panel_orientation_with_quirk(connector,
7033 DRM_MODE_PANEL_ORIENTATION_UNKNOWN,
7034 native_mode->hdisplay,
7035 native_mode->vdisplay);
7038 static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
7041 struct amdgpu_dm_connector *amdgpu_dm_connector =
7042 to_amdgpu_dm_connector(connector);
7045 /* empty probed_modes */
7046 INIT_LIST_HEAD(&connector->probed_modes);
7047 amdgpu_dm_connector->num_modes =
7048 drm_add_edid_modes(connector, edid);
7050 /* sorting the probed modes before calling function
7051 * amdgpu_dm_get_native_mode() since EDID can have
7052 * more than one preferred mode. The modes that are
7053 * later in the probed mode list could be of higher
7054 * and preferred resolution. For example, 3840x2160
7055 * resolution in base EDID preferred timing and 4096x2160
7056 * preferred resolution in DID extension block later.
7058 drm_mode_sort(&connector->probed_modes);
7059 amdgpu_dm_get_native_mode(connector);
7061 /* Freesync capabilities are reset by calling
7062 * drm_add_edid_modes() and need to be
7065 amdgpu_dm_update_freesync_caps(connector, edid);
7067 amdgpu_dm_connector->num_modes = 0;
7071 static bool is_duplicate_mode(struct amdgpu_dm_connector *aconnector,
7072 struct drm_display_mode *mode)
7074 struct drm_display_mode *m;
7076 list_for_each_entry (m, &aconnector->base.probed_modes, head) {
7077 if (drm_mode_equal(m, mode))
7084 static uint add_fs_modes(struct amdgpu_dm_connector *aconnector)
7086 const struct drm_display_mode *m;
7087 struct drm_display_mode *new_mode;
7089 u32 new_modes_count = 0;
7091 /* Standard FPS values
7100 * 60 - Commonly used
7101 * 48,72,96,120 - Multiples of 24
7103 static const u32 common_rates[] = {
7104 23976, 24000, 25000, 29970, 30000,
7105 48000, 50000, 60000, 72000, 96000, 120000
7109 * Find mode with highest refresh rate with the same resolution
7110 * as the preferred mode. Some monitors report a preferred mode
7111 * with lower resolution than the highest refresh rate supported.
7114 m = get_highest_refresh_rate_mode(aconnector, true);
7118 for (i = 0; i < ARRAY_SIZE(common_rates); i++) {
7119 u64 target_vtotal, target_vtotal_diff;
7122 if (drm_mode_vrefresh(m) * 1000 < common_rates[i])
7125 if (common_rates[i] < aconnector->min_vfreq * 1000 ||
7126 common_rates[i] > aconnector->max_vfreq * 1000)
7129 num = (unsigned long long)m->clock * 1000 * 1000;
7130 den = common_rates[i] * (unsigned long long)m->htotal;
7131 target_vtotal = div_u64(num, den);
7132 target_vtotal_diff = target_vtotal - m->vtotal;
7134 /* Check for illegal modes */
7135 if (m->vsync_start + target_vtotal_diff < m->vdisplay ||
7136 m->vsync_end + target_vtotal_diff < m->vsync_start ||
7137 m->vtotal + target_vtotal_diff < m->vsync_end)
7140 new_mode = drm_mode_duplicate(aconnector->base.dev, m);
7144 new_mode->vtotal += (u16)target_vtotal_diff;
7145 new_mode->vsync_start += (u16)target_vtotal_diff;
7146 new_mode->vsync_end += (u16)target_vtotal_diff;
7147 new_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
7148 new_mode->type |= DRM_MODE_TYPE_DRIVER;
7150 if (!is_duplicate_mode(aconnector, new_mode)) {
7151 drm_mode_probed_add(&aconnector->base, new_mode);
7152 new_modes_count += 1;
7154 drm_mode_destroy(aconnector->base.dev, new_mode);
7157 return new_modes_count;
7160 static void amdgpu_dm_connector_add_freesync_modes(struct drm_connector *connector,
7163 struct amdgpu_dm_connector *amdgpu_dm_connector =
7164 to_amdgpu_dm_connector(connector);
7166 if (!(amdgpu_freesync_vid_mode && edid))
7169 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
7170 amdgpu_dm_connector->num_modes +=
7171 add_fs_modes(amdgpu_dm_connector);
7174 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
7176 struct amdgpu_dm_connector *amdgpu_dm_connector =
7177 to_amdgpu_dm_connector(connector);
7178 struct drm_encoder *encoder;
7179 struct edid *edid = amdgpu_dm_connector->edid;
7180 struct dc_link_settings *verified_link_cap =
7181 &amdgpu_dm_connector->dc_link->verified_link_cap;
7182 const struct dc *dc = amdgpu_dm_connector->dc_link->dc;
7184 encoder = amdgpu_dm_connector_to_encoder(connector);
7186 if (!drm_edid_is_valid(edid)) {
7187 amdgpu_dm_connector->num_modes =
7188 drm_add_modes_noedid(connector, 640, 480);
7189 if (dc->link_srv->dp_get_encoding_format(verified_link_cap) == DP_128b_132b_ENCODING)
7190 amdgpu_dm_connector->num_modes +=
7191 drm_add_modes_noedid(connector, 1920, 1080);
7193 amdgpu_dm_connector_ddc_get_modes(connector, edid);
7194 amdgpu_dm_connector_add_common_modes(encoder, connector);
7195 amdgpu_dm_connector_add_freesync_modes(connector, edid);
7197 amdgpu_dm_fbc_init(connector);
7199 return amdgpu_dm_connector->num_modes;
7202 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
7203 struct amdgpu_dm_connector *aconnector,
7205 struct dc_link *link,
7208 struct amdgpu_device *adev = drm_to_adev(dm->ddev);
7211 * Some of the properties below require access to state, like bpc.
7212 * Allocate some default initial connector state with our reset helper.
7214 if (aconnector->base.funcs->reset)
7215 aconnector->base.funcs->reset(&aconnector->base);
7217 aconnector->connector_id = link_index;
7218 aconnector->bl_idx = -1;
7219 aconnector->dc_link = link;
7220 aconnector->base.interlace_allowed = false;
7221 aconnector->base.doublescan_allowed = false;
7222 aconnector->base.stereo_allowed = false;
7223 aconnector->base.dpms = DRM_MODE_DPMS_OFF;
7224 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
7225 aconnector->audio_inst = -1;
7226 aconnector->pack_sdp_v1_3 = false;
7227 aconnector->as_type = ADAPTIVE_SYNC_TYPE_NONE;
7228 memset(&aconnector->vsdb_info, 0, sizeof(aconnector->vsdb_info));
7229 mutex_init(&aconnector->hpd_lock);
7232 * configure support HPD hot plug connector_>polled default value is 0
7233 * which means HPD hot plug not supported
7235 switch (connector_type) {
7236 case DRM_MODE_CONNECTOR_HDMIA:
7237 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7238 aconnector->base.ycbcr_420_allowed =
7239 link->link_enc->features.hdmi_ycbcr420_supported ? true : false;
7241 case DRM_MODE_CONNECTOR_DisplayPort:
7242 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7243 link->link_enc = link_enc_cfg_get_link_enc(link);
7244 ASSERT(link->link_enc);
7246 aconnector->base.ycbcr_420_allowed =
7247 link->link_enc->features.dp_ycbcr420_supported ? true : false;
7249 case DRM_MODE_CONNECTOR_DVID:
7250 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7256 drm_object_attach_property(&aconnector->base.base,
7257 dm->ddev->mode_config.scaling_mode_property,
7258 DRM_MODE_SCALE_NONE);
7260 drm_object_attach_property(&aconnector->base.base,
7261 adev->mode_info.underscan_property,
7263 drm_object_attach_property(&aconnector->base.base,
7264 adev->mode_info.underscan_hborder_property,
7266 drm_object_attach_property(&aconnector->base.base,
7267 adev->mode_info.underscan_vborder_property,
7270 if (!aconnector->mst_root)
7271 drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16);
7273 aconnector->base.state->max_bpc = 16;
7274 aconnector->base.state->max_requested_bpc = aconnector->base.state->max_bpc;
7276 if (connector_type == DRM_MODE_CONNECTOR_eDP &&
7277 (dc_is_dmcu_initialized(adev->dm.dc) || adev->dm.dc->ctx->dmub_srv)) {
7278 drm_object_attach_property(&aconnector->base.base,
7279 adev->mode_info.abm_level_property, 0);
7282 if (connector_type == DRM_MODE_CONNECTOR_HDMIA ||
7283 connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
7284 connector_type == DRM_MODE_CONNECTOR_eDP) {
7285 drm_connector_attach_hdr_output_metadata_property(&aconnector->base);
7287 if (!aconnector->mst_root)
7288 drm_connector_attach_vrr_capable_property(&aconnector->base);
7290 if (adev->dm.hdcp_workqueue)
7291 drm_connector_attach_content_protection_property(&aconnector->base, true);
7295 static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
7296 struct i2c_msg *msgs, int num)
7298 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
7299 struct ddc_service *ddc_service = i2c->ddc_service;
7300 struct i2c_command cmd;
7304 cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
7309 cmd.number_of_payloads = num;
7310 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
7313 for (i = 0; i < num; i++) {
7314 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
7315 cmd.payloads[i].address = msgs[i].addr;
7316 cmd.payloads[i].length = msgs[i].len;
7317 cmd.payloads[i].data = msgs[i].buf;
7321 ddc_service->ctx->dc,
7322 ddc_service->link->link_index,
7326 kfree(cmd.payloads);
7330 static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
7332 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
7335 static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
7336 .master_xfer = amdgpu_dm_i2c_xfer,
7337 .functionality = amdgpu_dm_i2c_func,
7340 static struct amdgpu_i2c_adapter *
7341 create_i2c(struct ddc_service *ddc_service,
7345 struct amdgpu_device *adev = ddc_service->ctx->driver_context;
7346 struct amdgpu_i2c_adapter *i2c;
7348 i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
7351 i2c->base.owner = THIS_MODULE;
7352 i2c->base.class = I2C_CLASS_DDC;
7353 i2c->base.dev.parent = &adev->pdev->dev;
7354 i2c->base.algo = &amdgpu_dm_i2c_algo;
7355 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
7356 i2c_set_adapdata(&i2c->base, i2c);
7357 i2c->ddc_service = ddc_service;
7364 * Note: this function assumes that dc_link_detect() was called for the
7365 * dc_link which will be represented by this aconnector.
7367 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
7368 struct amdgpu_dm_connector *aconnector,
7370 struct amdgpu_encoder *aencoder)
7374 struct dc *dc = dm->dc;
7375 struct dc_link *link = dc_get_link_at_index(dc, link_index);
7376 struct amdgpu_i2c_adapter *i2c;
7378 link->priv = aconnector;
7380 DRM_DEBUG_DRIVER("%s()\n", __func__);
7382 i2c = create_i2c(link->ddc, link->link_index, &res);
7384 DRM_ERROR("Failed to create i2c adapter data\n");
7388 aconnector->i2c = i2c;
7389 res = i2c_add_adapter(&i2c->base);
7392 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
7396 connector_type = to_drm_connector_type(link->connector_signal);
7398 res = drm_connector_init_with_ddc(
7401 &amdgpu_dm_connector_funcs,
7406 DRM_ERROR("connector_init failed\n");
7407 aconnector->connector_id = -1;
7411 drm_connector_helper_add(
7413 &amdgpu_dm_connector_helper_funcs);
7415 amdgpu_dm_connector_init_helper(
7422 drm_connector_attach_encoder(
7423 &aconnector->base, &aencoder->base);
7425 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
7426 || connector_type == DRM_MODE_CONNECTOR_eDP)
7427 amdgpu_dm_initialize_dp_connector(dm, aconnector, link->link_index);
7432 aconnector->i2c = NULL;
7437 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
7439 switch (adev->mode_info.num_crtc) {
7456 static int amdgpu_dm_encoder_init(struct drm_device *dev,
7457 struct amdgpu_encoder *aencoder,
7458 uint32_t link_index)
7460 struct amdgpu_device *adev = drm_to_adev(dev);
7462 int res = drm_encoder_init(dev,
7464 &amdgpu_dm_encoder_funcs,
7465 DRM_MODE_ENCODER_TMDS,
7468 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
7471 aencoder->encoder_id = link_index;
7473 aencoder->encoder_id = -1;
7475 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
7480 static void manage_dm_interrupts(struct amdgpu_device *adev,
7481 struct amdgpu_crtc *acrtc,
7485 * We have no guarantee that the frontend index maps to the same
7486 * backend index - some even map to more than one.
7488 * TODO: Use a different interrupt or check DC itself for the mapping.
7491 amdgpu_display_crtc_idx_to_irq_type(
7496 drm_crtc_vblank_on(&acrtc->base);
7499 &adev->pageflip_irq,
7501 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
7508 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
7516 &adev->pageflip_irq,
7518 drm_crtc_vblank_off(&acrtc->base);
7522 static void dm_update_pflip_irq_state(struct amdgpu_device *adev,
7523 struct amdgpu_crtc *acrtc)
7526 amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id);
7529 * This reads the current state for the IRQ and force reapplies
7530 * the setting to hardware.
7532 amdgpu_irq_update(adev, &adev->pageflip_irq, irq_type);
7536 is_scaling_state_different(const struct dm_connector_state *dm_state,
7537 const struct dm_connector_state *old_dm_state)
7539 if (dm_state->scaling != old_dm_state->scaling)
7541 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
7542 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
7544 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
7545 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
7547 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
7548 dm_state->underscan_vborder != old_dm_state->underscan_vborder)
7553 static bool is_content_protection_different(struct drm_crtc_state *new_crtc_state,
7554 struct drm_crtc_state *old_crtc_state,
7555 struct drm_connector_state *new_conn_state,
7556 struct drm_connector_state *old_conn_state,
7557 const struct drm_connector *connector,
7558 struct hdcp_workqueue *hdcp_w)
7560 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
7561 struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
7563 pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n",
7564 connector->index, connector->status, connector->dpms);
7565 pr_debug("[HDCP_DM] state protection old: %x new: %x\n",
7566 old_conn_state->content_protection, new_conn_state->content_protection);
7569 pr_debug("[HDCP_DM] old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
7570 old_crtc_state->enable,
7571 old_crtc_state->active,
7572 old_crtc_state->mode_changed,
7573 old_crtc_state->active_changed,
7574 old_crtc_state->connectors_changed);
7577 pr_debug("[HDCP_DM] NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
7578 new_crtc_state->enable,
7579 new_crtc_state->active,
7580 new_crtc_state->mode_changed,
7581 new_crtc_state->active_changed,
7582 new_crtc_state->connectors_changed);
7584 /* hdcp content type change */
7585 if (old_conn_state->hdcp_content_type != new_conn_state->hdcp_content_type &&
7586 new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
7587 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7588 pr_debug("[HDCP_DM] Type0/1 change %s :true\n", __func__);
7592 /* CP is being re enabled, ignore this */
7593 if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED &&
7594 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7595 if (new_crtc_state && new_crtc_state->mode_changed) {
7596 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7597 pr_debug("[HDCP_DM] ENABLED->DESIRED & mode_changed %s :true\n", __func__);
7600 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED;
7601 pr_debug("[HDCP_DM] ENABLED -> DESIRED %s :false\n", __func__);
7605 /* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED
7607 * Handles: UNDESIRED -> ENABLED
7609 if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED &&
7610 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
7611 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7613 /* Stream removed and re-enabled
7615 * Can sometimes overlap with the HPD case,
7616 * thus set update_hdcp to false to avoid
7617 * setting HDCP multiple times.
7619 * Handles: DESIRED -> DESIRED (Special case)
7621 if (!(old_conn_state->crtc && old_conn_state->crtc->enabled) &&
7622 new_conn_state->crtc && new_conn_state->crtc->enabled &&
7623 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7624 dm_con_state->update_hdcp = false;
7625 pr_debug("[HDCP_DM] DESIRED->DESIRED (Stream removed and re-enabled) %s :true\n",
7630 /* Hot-plug, headless s3, dpms
7632 * Only start HDCP if the display is connected/enabled.
7633 * update_hdcp flag will be set to false until the next
7636 * Handles: DESIRED -> DESIRED (Special case)
7638 if (dm_con_state->update_hdcp &&
7639 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED &&
7640 connector->dpms == DRM_MODE_DPMS_ON && aconnector->dc_sink != NULL) {
7641 dm_con_state->update_hdcp = false;
7642 pr_debug("[HDCP_DM] DESIRED->DESIRED (Hot-plug, headless s3, dpms) %s :true\n",
7647 if (old_conn_state->content_protection == new_conn_state->content_protection) {
7648 if (new_conn_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7649 if (new_crtc_state && new_crtc_state->mode_changed) {
7650 pr_debug("[HDCP_DM] DESIRED->DESIRED or ENABLE->ENABLE mode_change %s :true\n",
7654 pr_debug("[HDCP_DM] DESIRED->DESIRED & ENABLE->ENABLE %s :false\n",
7659 pr_debug("[HDCP_DM] UNDESIRED->UNDESIRED %s :false\n", __func__);
7663 if (new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_ENABLED) {
7664 pr_debug("[HDCP_DM] UNDESIRED->DESIRED or DESIRED->UNDESIRED or ENABLED->UNDESIRED %s :true\n",
7669 pr_debug("[HDCP_DM] DESIRED->ENABLED %s :false\n", __func__);
7673 static void remove_stream(struct amdgpu_device *adev,
7674 struct amdgpu_crtc *acrtc,
7675 struct dc_stream_state *stream)
7677 /* this is the update mode case */
7679 acrtc->otg_inst = -1;
7680 acrtc->enabled = false;
7683 static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
7686 assert_spin_locked(&acrtc->base.dev->event_lock);
7687 WARN_ON(acrtc->event);
7689 acrtc->event = acrtc->base.state->event;
7691 /* Set the flip status */
7692 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
7694 /* Mark this event as consumed */
7695 acrtc->base.state->event = NULL;
7697 DC_LOG_PFLIP("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
7701 static void update_freesync_state_on_stream(
7702 struct amdgpu_display_manager *dm,
7703 struct dm_crtc_state *new_crtc_state,
7704 struct dc_stream_state *new_stream,
7705 struct dc_plane_state *surface,
7706 u32 flip_timestamp_in_us)
7708 struct mod_vrr_params vrr_params;
7709 struct dc_info_packet vrr_infopacket = {0};
7710 struct amdgpu_device *adev = dm->adev;
7711 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
7712 unsigned long flags;
7713 bool pack_sdp_v1_3 = false;
7714 struct amdgpu_dm_connector *aconn;
7715 enum vrr_packet_type packet_type = PACKET_TYPE_VRR;
7721 * TODO: Determine why min/max totals and vrefresh can be 0 here.
7722 * For now it's sufficient to just guard against these conditions.
7725 if (!new_stream->timing.h_total || !new_stream->timing.v_total)
7728 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
7729 vrr_params = acrtc->dm_irq_params.vrr_params;
7732 mod_freesync_handle_preflip(
7733 dm->freesync_module,
7736 flip_timestamp_in_us,
7739 if (adev->family < AMDGPU_FAMILY_AI &&
7740 amdgpu_dm_crtc_vrr_active(new_crtc_state)) {
7741 mod_freesync_handle_v_update(dm->freesync_module,
7742 new_stream, &vrr_params);
7744 /* Need to call this before the frame ends. */
7745 dc_stream_adjust_vmin_vmax(dm->dc,
7746 new_crtc_state->stream,
7747 &vrr_params.adjust);
7751 aconn = (struct amdgpu_dm_connector *)new_stream->dm_stream_context;
7753 if (aconn && aconn->as_type == FREESYNC_TYPE_PCON_IN_WHITELIST) {
7754 pack_sdp_v1_3 = aconn->pack_sdp_v1_3;
7756 if (aconn->vsdb_info.amd_vsdb_version == 1)
7757 packet_type = PACKET_TYPE_FS_V1;
7758 else if (aconn->vsdb_info.amd_vsdb_version == 2)
7759 packet_type = PACKET_TYPE_FS_V2;
7760 else if (aconn->vsdb_info.amd_vsdb_version == 3)
7761 packet_type = PACKET_TYPE_FS_V3;
7763 mod_build_adaptive_sync_infopacket(new_stream, aconn->as_type, NULL,
7764 &new_stream->adaptive_sync_infopacket);
7767 mod_freesync_build_vrr_infopacket(
7768 dm->freesync_module,
7772 TRANSFER_FUNC_UNKNOWN,
7776 new_crtc_state->freesync_vrr_info_changed |=
7777 (memcmp(&new_crtc_state->vrr_infopacket,
7779 sizeof(vrr_infopacket)) != 0);
7781 acrtc->dm_irq_params.vrr_params = vrr_params;
7782 new_crtc_state->vrr_infopacket = vrr_infopacket;
7784 new_stream->vrr_infopacket = vrr_infopacket;
7785 new_stream->allow_freesync = mod_freesync_get_freesync_enabled(&vrr_params);
7787 if (new_crtc_state->freesync_vrr_info_changed)
7788 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d",
7789 new_crtc_state->base.crtc->base.id,
7790 (int)new_crtc_state->base.vrr_enabled,
7791 (int)vrr_params.state);
7793 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
7796 static void update_stream_irq_parameters(
7797 struct amdgpu_display_manager *dm,
7798 struct dm_crtc_state *new_crtc_state)
7800 struct dc_stream_state *new_stream = new_crtc_state->stream;
7801 struct mod_vrr_params vrr_params;
7802 struct mod_freesync_config config = new_crtc_state->freesync_config;
7803 struct amdgpu_device *adev = dm->adev;
7804 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
7805 unsigned long flags;
7811 * TODO: Determine why min/max totals and vrefresh can be 0 here.
7812 * For now it's sufficient to just guard against these conditions.
7814 if (!new_stream->timing.h_total || !new_stream->timing.v_total)
7817 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
7818 vrr_params = acrtc->dm_irq_params.vrr_params;
7820 if (new_crtc_state->vrr_supported &&
7821 config.min_refresh_in_uhz &&
7822 config.max_refresh_in_uhz) {
7824 * if freesync compatible mode was set, config.state will be set
7827 if (config.state == VRR_STATE_ACTIVE_FIXED && config.fixed_refresh_in_uhz &&
7828 (!drm_atomic_crtc_needs_modeset(&new_crtc_state->base) ||
7829 new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)) {
7830 vrr_params.max_refresh_in_uhz = config.max_refresh_in_uhz;
7831 vrr_params.min_refresh_in_uhz = config.min_refresh_in_uhz;
7832 vrr_params.fixed_refresh_in_uhz = config.fixed_refresh_in_uhz;
7833 vrr_params.state = VRR_STATE_ACTIVE_FIXED;
7835 config.state = new_crtc_state->base.vrr_enabled ?
7836 VRR_STATE_ACTIVE_VARIABLE :
7840 config.state = VRR_STATE_UNSUPPORTED;
7843 mod_freesync_build_vrr_params(dm->freesync_module,
7845 &config, &vrr_params);
7847 new_crtc_state->freesync_config = config;
7848 /* Copy state for access from DM IRQ handler */
7849 acrtc->dm_irq_params.freesync_config = config;
7850 acrtc->dm_irq_params.active_planes = new_crtc_state->active_planes;
7851 acrtc->dm_irq_params.vrr_params = vrr_params;
7852 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
7855 static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state,
7856 struct dm_crtc_state *new_state)
7858 bool old_vrr_active = amdgpu_dm_crtc_vrr_active(old_state);
7859 bool new_vrr_active = amdgpu_dm_crtc_vrr_active(new_state);
7861 if (!old_vrr_active && new_vrr_active) {
7862 /* Transition VRR inactive -> active:
7863 * While VRR is active, we must not disable vblank irq, as a
7864 * reenable after disable would compute bogus vblank/pflip
7865 * timestamps if it likely happened inside display front-porch.
7867 * We also need vupdate irq for the actual core vblank handling
7870 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, true) != 0);
7871 WARN_ON(drm_crtc_vblank_get(new_state->base.crtc) != 0);
7872 DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n",
7873 __func__, new_state->base.crtc->base.id);
7874 } else if (old_vrr_active && !new_vrr_active) {
7875 /* Transition VRR active -> inactive:
7876 * Allow vblank irq disable again for fixed refresh rate.
7878 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, false) != 0);
7879 drm_crtc_vblank_put(new_state->base.crtc);
7880 DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n",
7881 __func__, new_state->base.crtc->base.id);
7885 static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state)
7887 struct drm_plane *plane;
7888 struct drm_plane_state *old_plane_state;
7892 * TODO: Make this per-stream so we don't issue redundant updates for
7893 * commits with multiple streams.
7895 for_each_old_plane_in_state(state, plane, old_plane_state, i)
7896 if (plane->type == DRM_PLANE_TYPE_CURSOR)
7897 amdgpu_dm_plane_handle_cursor_update(plane, old_plane_state);
7900 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
7901 struct dc_state *dc_state,
7902 struct drm_device *dev,
7903 struct amdgpu_display_manager *dm,
7904 struct drm_crtc *pcrtc,
7905 bool wait_for_vblank)
7908 u64 timestamp_ns = ktime_get_ns();
7909 struct drm_plane *plane;
7910 struct drm_plane_state *old_plane_state, *new_plane_state;
7911 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
7912 struct drm_crtc_state *new_pcrtc_state =
7913 drm_atomic_get_new_crtc_state(state, pcrtc);
7914 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
7915 struct dm_crtc_state *dm_old_crtc_state =
7916 to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
7917 int planes_count = 0, vpos, hpos;
7918 unsigned long flags;
7919 u32 target_vblank, last_flip_vblank;
7920 bool vrr_active = amdgpu_dm_crtc_vrr_active(acrtc_state);
7921 bool cursor_update = false;
7922 bool pflip_present = false;
7923 bool dirty_rects_changed = false;
7925 struct dc_surface_update surface_updates[MAX_SURFACES];
7926 struct dc_plane_info plane_infos[MAX_SURFACES];
7927 struct dc_scaling_info scaling_infos[MAX_SURFACES];
7928 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
7929 struct dc_stream_update stream_update;
7932 bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
7935 dm_error("Failed to allocate update bundle\n");
7940 * Disable the cursor first if we're disabling all the planes.
7941 * It'll remain on the screen after the planes are re-enabled
7944 if (acrtc_state->active_planes == 0)
7945 amdgpu_dm_commit_cursors(state);
7947 /* update planes when needed */
7948 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
7949 struct drm_crtc *crtc = new_plane_state->crtc;
7950 struct drm_crtc_state *new_crtc_state;
7951 struct drm_framebuffer *fb = new_plane_state->fb;
7952 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)fb;
7953 bool plane_needs_flip;
7954 struct dc_plane_state *dc_plane;
7955 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
7957 /* Cursor plane is handled after stream updates */
7958 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
7959 if ((fb && crtc == pcrtc) ||
7960 (old_plane_state->fb && old_plane_state->crtc == pcrtc))
7961 cursor_update = true;
7966 if (!fb || !crtc || pcrtc != crtc)
7969 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
7970 if (!new_crtc_state->active)
7973 dc_plane = dm_new_plane_state->dc_state;
7975 bundle->surface_updates[planes_count].surface = dc_plane;
7976 if (new_pcrtc_state->color_mgmt_changed) {
7977 bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction;
7978 bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func;
7979 bundle->surface_updates[planes_count].gamut_remap_matrix = &dc_plane->gamut_remap_matrix;
7982 amdgpu_dm_plane_fill_dc_scaling_info(dm->adev, new_plane_state,
7983 &bundle->scaling_infos[planes_count]);
7985 bundle->surface_updates[planes_count].scaling_info =
7986 &bundle->scaling_infos[planes_count];
7988 plane_needs_flip = old_plane_state->fb && new_plane_state->fb;
7990 pflip_present = pflip_present || plane_needs_flip;
7992 if (!plane_needs_flip) {
7997 fill_dc_plane_info_and_addr(
7998 dm->adev, new_plane_state,
8000 &bundle->plane_infos[planes_count],
8001 &bundle->flip_addrs[planes_count].address,
8002 afb->tmz_surface, false);
8004 drm_dbg_state(state->dev, "plane: id=%d dcc_en=%d\n",
8005 new_plane_state->plane->index,
8006 bundle->plane_infos[planes_count].dcc.enable);
8008 bundle->surface_updates[planes_count].plane_info =
8009 &bundle->plane_infos[planes_count];
8011 if (acrtc_state->stream->link->psr_settings.psr_feature_enabled) {
8012 fill_dc_dirty_rects(plane, old_plane_state,
8013 new_plane_state, new_crtc_state,
8014 &bundle->flip_addrs[planes_count],
8015 &dirty_rects_changed);
8018 * If the dirty regions changed, PSR-SU need to be disabled temporarily
8019 * and enabled it again after dirty regions are stable to avoid video glitch.
8020 * PSR-SU will be enabled in vblank_control_worker() if user pause the video
8021 * during the PSR-SU was disabled.
8023 if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
8024 acrtc_attach->dm_irq_params.allow_psr_entry &&
8025 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
8026 !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
8028 dirty_rects_changed) {
8029 mutex_lock(&dm->dc_lock);
8030 acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns =
8032 if (acrtc_state->stream->link->psr_settings.psr_allow_active)
8033 amdgpu_dm_psr_disable(acrtc_state->stream);
8034 mutex_unlock(&dm->dc_lock);
8039 * Only allow immediate flips for fast updates that don't
8040 * change FB pitch, DCC state, rotation or mirroing.
8042 bundle->flip_addrs[planes_count].flip_immediate =
8043 crtc->state->async_flip &&
8044 acrtc_state->update_type == UPDATE_TYPE_FAST;
8046 timestamp_ns = ktime_get_ns();
8047 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000);
8048 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count];
8049 bundle->surface_updates[planes_count].surface = dc_plane;
8051 if (!bundle->surface_updates[planes_count].surface) {
8052 DRM_ERROR("No surface for CRTC: id=%d\n",
8053 acrtc_attach->crtc_id);
8057 if (plane == pcrtc->primary)
8058 update_freesync_state_on_stream(
8061 acrtc_state->stream,
8063 bundle->flip_addrs[planes_count].flip_timestamp_in_us);
8065 drm_dbg_state(state->dev, "%s Flipping to hi: 0x%x, low: 0x%x\n",
8067 bundle->flip_addrs[planes_count].address.grph.addr.high_part,
8068 bundle->flip_addrs[planes_count].address.grph.addr.low_part);
8074 if (pflip_present) {
8076 /* Use old throttling in non-vrr fixed refresh rate mode
8077 * to keep flip scheduling based on target vblank counts
8078 * working in a backwards compatible way, e.g., for
8079 * clients using the GLX_OML_sync_control extension or
8080 * DRI3/Present extension with defined target_msc.
8082 last_flip_vblank = amdgpu_get_vblank_counter_kms(pcrtc);
8085 /* For variable refresh rate mode only:
8086 * Get vblank of last completed flip to avoid > 1 vrr
8087 * flips per video frame by use of throttling, but allow
8088 * flip programming anywhere in the possibly large
8089 * variable vrr vblank interval for fine-grained flip
8090 * timing control and more opportunity to avoid stutter
8091 * on late submission of flips.
8093 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8094 last_flip_vblank = acrtc_attach->dm_irq_params.last_flip_vblank;
8095 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8098 target_vblank = last_flip_vblank + wait_for_vblank;
8101 * Wait until we're out of the vertical blank period before the one
8102 * targeted by the flip
8104 while ((acrtc_attach->enabled &&
8105 (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id,
8106 0, &vpos, &hpos, NULL,
8107 NULL, &pcrtc->hwmode)
8108 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
8109 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
8110 (int)(target_vblank -
8111 amdgpu_get_vblank_counter_kms(pcrtc)) > 0)) {
8112 usleep_range(1000, 1100);
8116 * Prepare the flip event for the pageflip interrupt to handle.
8118 * This only works in the case where we've already turned on the
8119 * appropriate hardware blocks (eg. HUBP) so in the transition case
8120 * from 0 -> n planes we have to skip a hardware generated event
8121 * and rely on sending it from software.
8123 if (acrtc_attach->base.state->event &&
8124 acrtc_state->active_planes > 0) {
8125 drm_crtc_vblank_get(pcrtc);
8127 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8129 WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE);
8130 prepare_flip_isr(acrtc_attach);
8132 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8135 if (acrtc_state->stream) {
8136 if (acrtc_state->freesync_vrr_info_changed)
8137 bundle->stream_update.vrr_infopacket =
8138 &acrtc_state->stream->vrr_infopacket;
8140 } else if (cursor_update && acrtc_state->active_planes > 0 &&
8141 acrtc_attach->base.state->event) {
8142 drm_crtc_vblank_get(pcrtc);
8144 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8146 acrtc_attach->event = acrtc_attach->base.state->event;
8147 acrtc_attach->base.state->event = NULL;
8149 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8152 /* Update the planes if changed or disable if we don't have any. */
8153 if ((planes_count || acrtc_state->active_planes == 0) &&
8154 acrtc_state->stream) {
8156 * If PSR or idle optimizations are enabled then flush out
8157 * any pending work before hardware programming.
8159 if (dm->vblank_control_workqueue)
8160 flush_workqueue(dm->vblank_control_workqueue);
8162 bundle->stream_update.stream = acrtc_state->stream;
8163 if (new_pcrtc_state->mode_changed) {
8164 bundle->stream_update.src = acrtc_state->stream->src;
8165 bundle->stream_update.dst = acrtc_state->stream->dst;
8168 if (new_pcrtc_state->color_mgmt_changed) {
8170 * TODO: This isn't fully correct since we've actually
8171 * already modified the stream in place.
8173 bundle->stream_update.gamut_remap =
8174 &acrtc_state->stream->gamut_remap_matrix;
8175 bundle->stream_update.output_csc_transform =
8176 &acrtc_state->stream->csc_color_matrix;
8177 bundle->stream_update.out_transfer_func =
8178 acrtc_state->stream->out_transfer_func;
8181 acrtc_state->stream->abm_level = acrtc_state->abm_level;
8182 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level)
8183 bundle->stream_update.abm_level = &acrtc_state->abm_level;
8186 * If FreeSync state on the stream has changed then we need to
8187 * re-adjust the min/max bounds now that DC doesn't handle this
8188 * as part of commit.
8190 if (is_dc_timing_adjust_needed(dm_old_crtc_state, acrtc_state)) {
8191 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8192 dc_stream_adjust_vmin_vmax(
8193 dm->dc, acrtc_state->stream,
8194 &acrtc_attach->dm_irq_params.vrr_params.adjust);
8195 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8197 mutex_lock(&dm->dc_lock);
8198 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
8199 acrtc_state->stream->link->psr_settings.psr_allow_active)
8200 amdgpu_dm_psr_disable(acrtc_state->stream);
8202 update_planes_and_stream_adapter(dm->dc,
8203 acrtc_state->update_type,
8205 acrtc_state->stream,
8206 &bundle->stream_update,
8207 bundle->surface_updates);
8210 * Enable or disable the interrupts on the backend.
8212 * Most pipes are put into power gating when unused.
8214 * When power gating is enabled on a pipe we lose the
8215 * interrupt enablement state when power gating is disabled.
8217 * So we need to update the IRQ control state in hardware
8218 * whenever the pipe turns on (since it could be previously
8219 * power gated) or off (since some pipes can't be power gated
8222 if (dm_old_crtc_state->active_planes != acrtc_state->active_planes)
8223 dm_update_pflip_irq_state(drm_to_adev(dev),
8226 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
8227 acrtc_state->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED &&
8228 !acrtc_state->stream->link->psr_settings.psr_feature_enabled)
8229 amdgpu_dm_link_setup_psr(acrtc_state->stream);
8231 /* Decrement skip count when PSR is enabled and we're doing fast updates. */
8232 if (acrtc_state->update_type == UPDATE_TYPE_FAST &&
8233 acrtc_state->stream->link->psr_settings.psr_feature_enabled) {
8234 struct amdgpu_dm_connector *aconn =
8235 (struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context;
8237 if (aconn->psr_skip_count > 0)
8238 aconn->psr_skip_count--;
8240 /* Allow PSR when skip count is 0. */
8241 acrtc_attach->dm_irq_params.allow_psr_entry = !aconn->psr_skip_count;
8244 * If sink supports PSR SU, there is no need to rely on
8245 * a vblank event disable request to enable PSR. PSR SU
8246 * can be enabled immediately once OS demonstrates an
8247 * adequate number of fast atomic commits to notify KMD
8248 * of update events. See `vblank_control_worker()`.
8250 if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
8251 acrtc_attach->dm_irq_params.allow_psr_entry &&
8252 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
8253 !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
8255 !acrtc_state->stream->link->psr_settings.psr_allow_active &&
8257 acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns) >
8259 amdgpu_dm_psr_enable(acrtc_state->stream);
8261 acrtc_attach->dm_irq_params.allow_psr_entry = false;
8264 mutex_unlock(&dm->dc_lock);
8268 * Update cursor state *after* programming all the planes.
8269 * This avoids redundant programming in the case where we're going
8270 * to be disabling a single plane - those pipes are being disabled.
8272 if (acrtc_state->active_planes)
8273 amdgpu_dm_commit_cursors(state);
8279 static void amdgpu_dm_commit_audio(struct drm_device *dev,
8280 struct drm_atomic_state *state)
8282 struct amdgpu_device *adev = drm_to_adev(dev);
8283 struct amdgpu_dm_connector *aconnector;
8284 struct drm_connector *connector;
8285 struct drm_connector_state *old_con_state, *new_con_state;
8286 struct drm_crtc_state *new_crtc_state;
8287 struct dm_crtc_state *new_dm_crtc_state;
8288 const struct dc_stream_status *status;
8291 /* Notify device removals. */
8292 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8293 if (old_con_state->crtc != new_con_state->crtc) {
8294 /* CRTC changes require notification. */
8298 if (!new_con_state->crtc)
8301 new_crtc_state = drm_atomic_get_new_crtc_state(
8302 state, new_con_state->crtc);
8304 if (!new_crtc_state)
8307 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8311 aconnector = to_amdgpu_dm_connector(connector);
8313 mutex_lock(&adev->dm.audio_lock);
8314 inst = aconnector->audio_inst;
8315 aconnector->audio_inst = -1;
8316 mutex_unlock(&adev->dm.audio_lock);
8318 amdgpu_dm_audio_eld_notify(adev, inst);
8321 /* Notify audio device additions. */
8322 for_each_new_connector_in_state(state, connector, new_con_state, i) {
8323 if (!new_con_state->crtc)
8326 new_crtc_state = drm_atomic_get_new_crtc_state(
8327 state, new_con_state->crtc);
8329 if (!new_crtc_state)
8332 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8335 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
8336 if (!new_dm_crtc_state->stream)
8339 status = dc_stream_get_status(new_dm_crtc_state->stream);
8343 aconnector = to_amdgpu_dm_connector(connector);
8345 mutex_lock(&adev->dm.audio_lock);
8346 inst = status->audio_inst;
8347 aconnector->audio_inst = inst;
8348 mutex_unlock(&adev->dm.audio_lock);
8350 amdgpu_dm_audio_eld_notify(adev, inst);
8355 * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
8356 * @crtc_state: the DRM CRTC state
8357 * @stream_state: the DC stream state.
8359 * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
8360 * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
8362 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
8363 struct dc_stream_state *stream_state)
8365 stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state);
8369 * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation.
8370 * @state: The atomic state to commit
8372 * This will tell DC to commit the constructed DC state from atomic_check,
8373 * programming the hardware. Any failures here implies a hardware failure, since
8374 * atomic check should have filtered anything non-kosher.
8376 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
8378 struct drm_device *dev = state->dev;
8379 struct amdgpu_device *adev = drm_to_adev(dev);
8380 struct amdgpu_display_manager *dm = &adev->dm;
8381 struct dm_atomic_state *dm_state;
8382 struct dc_state *dc_state = NULL, *dc_state_temp = NULL;
8384 struct drm_crtc *crtc;
8385 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
8386 unsigned long flags;
8387 bool wait_for_vblank = true;
8388 struct drm_connector *connector;
8389 struct drm_connector_state *old_con_state, *new_con_state;
8390 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
8391 int crtc_disable_count = 0;
8392 bool mode_set_reset_required = false;
8395 trace_amdgpu_dm_atomic_commit_tail_begin(state);
8397 r = drm_atomic_helper_wait_for_fences(dev, state, false);
8399 DRM_ERROR("Waiting for fences timed out!");
8401 drm_atomic_helper_update_legacy_modeset_state(dev, state);
8402 drm_dp_mst_atomic_wait_for_dependencies(state);
8404 dm_state = dm_atomic_get_new_state(state);
8405 if (dm_state && dm_state->context) {
8406 dc_state = dm_state->context;
8408 /* No state changes, retain current state. */
8409 dc_state_temp = dc_create_state(dm->dc);
8410 ASSERT(dc_state_temp);
8411 dc_state = dc_state_temp;
8412 dc_resource_state_copy_construct_current(dm->dc, dc_state);
8415 for_each_oldnew_crtc_in_state (state, crtc, old_crtc_state,
8416 new_crtc_state, i) {
8417 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8419 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8421 if (old_crtc_state->active &&
8422 (!new_crtc_state->active ||
8423 drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8424 manage_dm_interrupts(adev, acrtc, false);
8425 dc_stream_release(dm_old_crtc_state->stream);
8429 drm_atomic_helper_calc_timestamping_constants(state);
8431 /* update changed items */
8432 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
8433 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8435 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8436 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8438 drm_dbg_state(state->dev,
8439 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
8440 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
8441 "connectors_changed:%d\n",
8443 new_crtc_state->enable,
8444 new_crtc_state->active,
8445 new_crtc_state->planes_changed,
8446 new_crtc_state->mode_changed,
8447 new_crtc_state->active_changed,
8448 new_crtc_state->connectors_changed);
8450 /* Disable cursor if disabling crtc */
8451 if (old_crtc_state->active && !new_crtc_state->active) {
8452 struct dc_cursor_position position;
8454 memset(&position, 0, sizeof(position));
8455 mutex_lock(&dm->dc_lock);
8456 dc_stream_set_cursor_position(dm_old_crtc_state->stream, &position);
8457 mutex_unlock(&dm->dc_lock);
8460 /* Copy all transient state flags into dc state */
8461 if (dm_new_crtc_state->stream) {
8462 amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
8463 dm_new_crtc_state->stream);
8466 /* handles headless hotplug case, updating new_state and
8467 * aconnector as needed
8470 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
8472 DRM_DEBUG_ATOMIC("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
8474 if (!dm_new_crtc_state->stream) {
8476 * this could happen because of issues with
8477 * userspace notifications delivery.
8478 * In this case userspace tries to set mode on
8479 * display which is disconnected in fact.
8480 * dc_sink is NULL in this case on aconnector.
8481 * We expect reset mode will come soon.
8483 * This can also happen when unplug is done
8484 * during resume sequence ended
8486 * In this case, we want to pretend we still
8487 * have a sink to keep the pipe running so that
8488 * hw state is consistent with the sw state
8490 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
8491 __func__, acrtc->base.base.id);
8495 if (dm_old_crtc_state->stream)
8496 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
8498 pm_runtime_get_noresume(dev->dev);
8500 acrtc->enabled = true;
8501 acrtc->hw_mode = new_crtc_state->mode;
8502 crtc->hwmode = new_crtc_state->mode;
8503 mode_set_reset_required = true;
8504 } else if (modereset_required(new_crtc_state)) {
8505 DRM_DEBUG_ATOMIC("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
8506 /* i.e. reset mode */
8507 if (dm_old_crtc_state->stream)
8508 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
8510 mode_set_reset_required = true;
8512 } /* for_each_crtc_in_state() */
8515 /* if there mode set or reset, disable eDP PSR */
8516 if (mode_set_reset_required) {
8517 if (dm->vblank_control_workqueue)
8518 flush_workqueue(dm->vblank_control_workqueue);
8520 amdgpu_dm_psr_disable_all(dm);
8523 dm_enable_per_frame_crtc_master_sync(dc_state);
8524 mutex_lock(&dm->dc_lock);
8525 WARN_ON(!dc_commit_streams(dm->dc, dc_state->streams, dc_state->stream_count));
8527 /* Allow idle optimization when vblank count is 0 for display off */
8528 if (dm->active_vblank_irq_count == 0)
8529 dc_allow_idle_optimizations(dm->dc, true);
8530 mutex_unlock(&dm->dc_lock);
8533 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
8534 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8536 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8538 if (dm_new_crtc_state->stream != NULL) {
8539 const struct dc_stream_status *status =
8540 dc_stream_get_status(dm_new_crtc_state->stream);
8543 status = dc_stream_get_status_from_state(dc_state,
8544 dm_new_crtc_state->stream);
8546 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc);
8548 acrtc->otg_inst = status->primary_otg_inst;
8551 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8552 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8553 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8554 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8556 pr_debug("[HDCP_DM] -------------- i : %x ----------\n", i);
8561 pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n",
8562 connector->index, connector->status, connector->dpms);
8563 pr_debug("[HDCP_DM] state protection old: %x new: %x\n",
8564 old_con_state->content_protection, new_con_state->content_protection);
8566 if (aconnector->dc_sink) {
8567 if (aconnector->dc_sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&
8568 aconnector->dc_sink->sink_signal != SIGNAL_TYPE_NONE) {
8569 pr_debug("[HDCP_DM] pipe_ctx dispname=%s\n",
8570 aconnector->dc_sink->edid_caps.display_name);
8574 new_crtc_state = NULL;
8575 old_crtc_state = NULL;
8578 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8579 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8583 pr_debug("old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
8584 old_crtc_state->enable,
8585 old_crtc_state->active,
8586 old_crtc_state->mode_changed,
8587 old_crtc_state->active_changed,
8588 old_crtc_state->connectors_changed);
8591 pr_debug("NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
8592 new_crtc_state->enable,
8593 new_crtc_state->active,
8594 new_crtc_state->mode_changed,
8595 new_crtc_state->active_changed,
8596 new_crtc_state->connectors_changed);
8599 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8600 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8601 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8602 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8604 new_crtc_state = NULL;
8605 old_crtc_state = NULL;
8608 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8609 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8612 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8614 if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL &&
8615 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) {
8616 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
8617 new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
8618 dm_new_con_state->update_hdcp = true;
8622 if (is_content_protection_different(new_crtc_state, old_crtc_state, new_con_state,
8623 old_con_state, connector, adev->dm.hdcp_workqueue)) {
8624 /* when display is unplugged from mst hub, connctor will
8625 * be destroyed within dm_dp_mst_connector_destroy. connector
8626 * hdcp perperties, like type, undesired, desired, enabled,
8627 * will be lost. So, save hdcp properties into hdcp_work within
8628 * amdgpu_dm_atomic_commit_tail. if the same display is
8629 * plugged back with same display index, its hdcp properties
8630 * will be retrieved from hdcp_work within dm_dp_mst_get_modes
8633 bool enable_encryption = false;
8635 if (new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED)
8636 enable_encryption = true;
8638 if (aconnector->dc_link && aconnector->dc_sink &&
8639 aconnector->dc_link->type == dc_connection_mst_branch) {
8640 struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue;
8641 struct hdcp_workqueue *hdcp_w =
8642 &hdcp_work[aconnector->dc_link->link_index];
8644 hdcp_w->hdcp_content_type[connector->index] =
8645 new_con_state->hdcp_content_type;
8646 hdcp_w->content_protection[connector->index] =
8647 new_con_state->content_protection;
8650 if (new_crtc_state && new_crtc_state->mode_changed &&
8651 new_con_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED)
8652 enable_encryption = true;
8654 DRM_INFO("[HDCP_DM] hdcp_update_display enable_encryption = %x\n", enable_encryption);
8656 hdcp_update_display(
8657 adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector,
8658 new_con_state->hdcp_content_type, enable_encryption);
8662 /* Handle connector state changes */
8663 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8664 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8665 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
8666 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8667 struct dc_surface_update dummy_updates[MAX_SURFACES];
8668 struct dc_stream_update stream_update;
8669 struct dc_info_packet hdr_packet;
8670 struct dc_stream_status *status = NULL;
8671 bool abm_changed, hdr_changed, scaling_changed;
8673 memset(&dummy_updates, 0, sizeof(dummy_updates));
8674 memset(&stream_update, 0, sizeof(stream_update));
8677 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8678 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8681 /* Skip any modesets/resets */
8682 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
8685 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8686 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8688 scaling_changed = is_scaling_state_different(dm_new_con_state,
8691 abm_changed = dm_new_crtc_state->abm_level !=
8692 dm_old_crtc_state->abm_level;
8695 !drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state);
8697 if (!scaling_changed && !abm_changed && !hdr_changed)
8700 stream_update.stream = dm_new_crtc_state->stream;
8701 if (scaling_changed) {
8702 update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
8703 dm_new_con_state, dm_new_crtc_state->stream);
8705 stream_update.src = dm_new_crtc_state->stream->src;
8706 stream_update.dst = dm_new_crtc_state->stream->dst;
8710 dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level;
8712 stream_update.abm_level = &dm_new_crtc_state->abm_level;
8716 fill_hdr_info_packet(new_con_state, &hdr_packet);
8717 stream_update.hdr_static_metadata = &hdr_packet;
8720 status = dc_stream_get_status(dm_new_crtc_state->stream);
8722 if (WARN_ON(!status))
8725 WARN_ON(!status->plane_count);
8728 * TODO: DC refuses to perform stream updates without a dc_surface_update.
8729 * Here we create an empty update on each plane.
8730 * To fix this, DC should permit updating only stream properties.
8732 for (j = 0; j < status->plane_count; j++)
8733 dummy_updates[j].surface = status->plane_states[0];
8736 mutex_lock(&dm->dc_lock);
8737 dc_update_planes_and_stream(dm->dc,
8739 status->plane_count,
8740 dm_new_crtc_state->stream,
8742 mutex_unlock(&dm->dc_lock);
8746 * Enable interrupts for CRTCs that are newly enabled or went through
8747 * a modeset. It was intentionally deferred until after the front end
8748 * state was modified to wait until the OTG was on and so the IRQ
8749 * handlers didn't access stale or invalid state.
8751 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
8752 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8753 #ifdef CONFIG_DEBUG_FS
8754 enum amdgpu_dm_pipe_crc_source cur_crc_src;
8756 /* Count number of newly disabled CRTCs for dropping PM refs later. */
8757 if (old_crtc_state->active && !new_crtc_state->active)
8758 crtc_disable_count++;
8760 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8761 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8763 /* For freesync config update on crtc state and params for irq */
8764 update_stream_irq_parameters(dm, dm_new_crtc_state);
8766 #ifdef CONFIG_DEBUG_FS
8767 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8768 cur_crc_src = acrtc->dm_irq_params.crc_src;
8769 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8772 if (new_crtc_state->active &&
8773 (!old_crtc_state->active ||
8774 drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8775 dc_stream_retain(dm_new_crtc_state->stream);
8776 acrtc->dm_irq_params.stream = dm_new_crtc_state->stream;
8777 manage_dm_interrupts(adev, acrtc, true);
8779 /* Handle vrr on->off / off->on transitions */
8780 amdgpu_dm_handle_vrr_transition(dm_old_crtc_state, dm_new_crtc_state);
8782 #ifdef CONFIG_DEBUG_FS
8783 if (new_crtc_state->active &&
8784 (!old_crtc_state->active ||
8785 drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8787 * Frontend may have changed so reapply the CRC capture
8788 * settings for the stream.
8790 if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) {
8791 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
8792 if (amdgpu_dm_crc_window_is_activated(crtc)) {
8793 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8794 acrtc->dm_irq_params.window_param.update_win = true;
8797 * It takes 2 frames for HW to stably generate CRC when
8798 * resuming from suspend, so we set skip_frame_cnt 2.
8800 acrtc->dm_irq_params.window_param.skip_frame_cnt = 2;
8801 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8804 if (amdgpu_dm_crtc_configure_crc_source(
8805 crtc, dm_new_crtc_state, cur_crc_src))
8806 DRM_DEBUG_DRIVER("Failed to configure crc source");
8812 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j)
8813 if (new_crtc_state->async_flip)
8814 wait_for_vblank = false;
8816 /* update planes when needed per crtc*/
8817 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
8818 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8820 if (dm_new_crtc_state->stream)
8821 amdgpu_dm_commit_planes(state, dc_state, dev,
8822 dm, crtc, wait_for_vblank);
8825 /* Update audio instances for each connector. */
8826 amdgpu_dm_commit_audio(dev, state);
8828 /* restore the backlight level */
8829 for (i = 0; i < dm->num_of_edps; i++) {
8830 if (dm->backlight_dev[i] &&
8831 (dm->actual_brightness[i] != dm->brightness[i]))
8832 amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]);
8836 * send vblank event on all events not handled in flip and
8837 * mark consumed event for drm_atomic_helper_commit_hw_done
8839 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8840 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
8842 if (new_crtc_state->event)
8843 drm_send_event_locked(dev, &new_crtc_state->event->base);
8845 new_crtc_state->event = NULL;
8847 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8849 /* Signal HW programming completion */
8850 drm_atomic_helper_commit_hw_done(state);
8852 if (wait_for_vblank)
8853 drm_atomic_helper_wait_for_flip_done(dev, state);
8855 drm_atomic_helper_cleanup_planes(dev, state);
8857 /* return the stolen vga memory back to VRAM */
8858 if (!adev->mman.keep_stolen_vga_memory)
8859 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
8860 amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
8863 * Finally, drop a runtime PM reference for each newly disabled CRTC,
8864 * so we can put the GPU into runtime suspend if we're not driving any
8867 for (i = 0; i < crtc_disable_count; i++)
8868 pm_runtime_put_autosuspend(dev->dev);
8869 pm_runtime_mark_last_busy(dev->dev);
8872 dc_release_state(dc_state_temp);
8875 static int dm_force_atomic_commit(struct drm_connector *connector)
8878 struct drm_device *ddev = connector->dev;
8879 struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
8880 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
8881 struct drm_plane *plane = disconnected_acrtc->base.primary;
8882 struct drm_connector_state *conn_state;
8883 struct drm_crtc_state *crtc_state;
8884 struct drm_plane_state *plane_state;
8889 state->acquire_ctx = ddev->mode_config.acquire_ctx;
8891 /* Construct an atomic state to restore previous display setting */
8894 * Attach connectors to drm_atomic_state
8896 conn_state = drm_atomic_get_connector_state(state, connector);
8898 ret = PTR_ERR_OR_ZERO(conn_state);
8902 /* Attach crtc to drm_atomic_state*/
8903 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
8905 ret = PTR_ERR_OR_ZERO(crtc_state);
8909 /* force a restore */
8910 crtc_state->mode_changed = true;
8912 /* Attach plane to drm_atomic_state */
8913 plane_state = drm_atomic_get_plane_state(state, plane);
8915 ret = PTR_ERR_OR_ZERO(plane_state);
8919 /* Call commit internally with the state we just constructed */
8920 ret = drm_atomic_commit(state);
8923 drm_atomic_state_put(state);
8925 DRM_ERROR("Restoring old state failed with %i\n", ret);
8931 * This function handles all cases when set mode does not come upon hotplug.
8932 * This includes when a display is unplugged then plugged back into the
8933 * same port and when running without usermode desktop manager supprot
8935 void dm_restore_drm_connector_state(struct drm_device *dev,
8936 struct drm_connector *connector)
8938 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8939 struct amdgpu_crtc *disconnected_acrtc;
8940 struct dm_crtc_state *acrtc_state;
8942 if (!aconnector->dc_sink || !connector->state || !connector->encoder)
8945 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
8946 if (!disconnected_acrtc)
8949 acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
8950 if (!acrtc_state->stream)
8954 * If the previous sink is not released and different from the current,
8955 * we deduce we are in a state where we can not rely on usermode call
8956 * to turn on the display, so we do it here
8958 if (acrtc_state->stream->sink != aconnector->dc_sink)
8959 dm_force_atomic_commit(&aconnector->base);
8963 * Grabs all modesetting locks to serialize against any blocking commits,
8964 * Waits for completion of all non blocking commits.
8966 static int do_aquire_global_lock(struct drm_device *dev,
8967 struct drm_atomic_state *state)
8969 struct drm_crtc *crtc;
8970 struct drm_crtc_commit *commit;
8974 * Adding all modeset locks to aquire_ctx will
8975 * ensure that when the framework release it the
8976 * extra locks we are locking here will get released to
8978 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
8982 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8983 spin_lock(&crtc->commit_lock);
8984 commit = list_first_entry_or_null(&crtc->commit_list,
8985 struct drm_crtc_commit, commit_entry);
8987 drm_crtc_commit_get(commit);
8988 spin_unlock(&crtc->commit_lock);
8994 * Make sure all pending HW programming completed and
8997 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
9000 ret = wait_for_completion_interruptible_timeout(
9001 &commit->flip_done, 10*HZ);
9004 DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
9005 "timed out\n", crtc->base.id, crtc->name);
9007 drm_crtc_commit_put(commit);
9010 return ret < 0 ? ret : 0;
9013 static void get_freesync_config_for_crtc(
9014 struct dm_crtc_state *new_crtc_state,
9015 struct dm_connector_state *new_con_state)
9017 struct mod_freesync_config config = {0};
9018 struct amdgpu_dm_connector *aconnector =
9019 to_amdgpu_dm_connector(new_con_state->base.connector);
9020 struct drm_display_mode *mode = &new_crtc_state->base.mode;
9021 int vrefresh = drm_mode_vrefresh(mode);
9022 bool fs_vid_mode = false;
9024 new_crtc_state->vrr_supported = new_con_state->freesync_capable &&
9025 vrefresh >= aconnector->min_vfreq &&
9026 vrefresh <= aconnector->max_vfreq;
9028 if (new_crtc_state->vrr_supported) {
9029 new_crtc_state->stream->ignore_msa_timing_param = true;
9030 fs_vid_mode = new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
9032 config.min_refresh_in_uhz = aconnector->min_vfreq * 1000000;
9033 config.max_refresh_in_uhz = aconnector->max_vfreq * 1000000;
9034 config.vsif_supported = true;
9038 config.state = VRR_STATE_ACTIVE_FIXED;
9039 config.fixed_refresh_in_uhz = new_crtc_state->freesync_config.fixed_refresh_in_uhz;
9041 } else if (new_crtc_state->base.vrr_enabled) {
9042 config.state = VRR_STATE_ACTIVE_VARIABLE;
9044 config.state = VRR_STATE_INACTIVE;
9048 new_crtc_state->freesync_config = config;
9051 static void reset_freesync_config_for_crtc(
9052 struct dm_crtc_state *new_crtc_state)
9054 new_crtc_state->vrr_supported = false;
9056 memset(&new_crtc_state->vrr_infopacket, 0,
9057 sizeof(new_crtc_state->vrr_infopacket));
9061 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
9062 struct drm_crtc_state *new_crtc_state)
9064 const struct drm_display_mode *old_mode, *new_mode;
9066 if (!old_crtc_state || !new_crtc_state)
9069 old_mode = &old_crtc_state->mode;
9070 new_mode = &new_crtc_state->mode;
9072 if (old_mode->clock == new_mode->clock &&
9073 old_mode->hdisplay == new_mode->hdisplay &&
9074 old_mode->vdisplay == new_mode->vdisplay &&
9075 old_mode->htotal == new_mode->htotal &&
9076 old_mode->vtotal != new_mode->vtotal &&
9077 old_mode->hsync_start == new_mode->hsync_start &&
9078 old_mode->vsync_start != new_mode->vsync_start &&
9079 old_mode->hsync_end == new_mode->hsync_end &&
9080 old_mode->vsync_end != new_mode->vsync_end &&
9081 old_mode->hskew == new_mode->hskew &&
9082 old_mode->vscan == new_mode->vscan &&
9083 (old_mode->vsync_end - old_mode->vsync_start) ==
9084 (new_mode->vsync_end - new_mode->vsync_start))
9090 static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state) {
9092 struct drm_crtc_state *new_crtc_state = &dm_new_crtc_state->base;
9094 dm_new_crtc_state->freesync_config.state = VRR_STATE_ACTIVE_FIXED;
9096 num = (unsigned long long)new_crtc_state->mode.clock * 1000 * 1000000;
9097 den = (unsigned long long)new_crtc_state->mode.htotal *
9098 (unsigned long long)new_crtc_state->mode.vtotal;
9100 res = div_u64(num, den);
9101 dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = res;
9104 static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
9105 struct drm_atomic_state *state,
9106 struct drm_crtc *crtc,
9107 struct drm_crtc_state *old_crtc_state,
9108 struct drm_crtc_state *new_crtc_state,
9110 bool *lock_and_validation_needed)
9112 struct dm_atomic_state *dm_state = NULL;
9113 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
9114 struct dc_stream_state *new_stream;
9118 * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set
9119 * update changed items
9121 struct amdgpu_crtc *acrtc = NULL;
9122 struct amdgpu_dm_connector *aconnector = NULL;
9123 struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL;
9124 struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL;
9128 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9129 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9130 acrtc = to_amdgpu_crtc(crtc);
9131 aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
9133 /* TODO This hack should go away */
9134 if (aconnector && enable) {
9135 /* Make sure fake sink is created in plug-in scenario */
9136 drm_new_conn_state = drm_atomic_get_new_connector_state(state,
9138 drm_old_conn_state = drm_atomic_get_old_connector_state(state,
9141 if (IS_ERR(drm_new_conn_state)) {
9142 ret = PTR_ERR_OR_ZERO(drm_new_conn_state);
9146 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
9147 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state);
9149 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9152 new_stream = create_validate_stream_for_sink(aconnector,
9153 &new_crtc_state->mode,
9155 dm_old_crtc_state->stream);
9158 * we can have no stream on ACTION_SET if a display
9159 * was disconnected during S3, in this case it is not an
9160 * error, the OS will be updated after detection, and
9161 * will do the right thing on next atomic commit
9165 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
9166 __func__, acrtc->base.base.id);
9172 * TODO: Check VSDB bits to decide whether this should
9173 * be enabled or not.
9175 new_stream->triggered_crtc_reset.enabled =
9176 dm->force_timing_sync;
9178 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
9180 ret = fill_hdr_info_packet(drm_new_conn_state,
9181 &new_stream->hdr_static_metadata);
9186 * If we already removed the old stream from the context
9187 * (and set the new stream to NULL) then we can't reuse
9188 * the old stream even if the stream and scaling are unchanged.
9189 * We'll hit the BUG_ON and black screen.
9191 * TODO: Refactor this function to allow this check to work
9192 * in all conditions.
9194 if (amdgpu_freesync_vid_mode &&
9195 dm_new_crtc_state->stream &&
9196 is_timing_unchanged_for_freesync(new_crtc_state, old_crtc_state))
9199 if (dm_new_crtc_state->stream &&
9200 dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
9201 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
9202 new_crtc_state->mode_changed = false;
9203 DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
9204 new_crtc_state->mode_changed);
9208 /* mode_changed flag may get updated above, need to check again */
9209 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9212 drm_dbg_state(state->dev,
9213 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
9214 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
9215 "connectors_changed:%d\n",
9217 new_crtc_state->enable,
9218 new_crtc_state->active,
9219 new_crtc_state->planes_changed,
9220 new_crtc_state->mode_changed,
9221 new_crtc_state->active_changed,
9222 new_crtc_state->connectors_changed);
9224 /* Remove stream for any changed/disabled CRTC */
9227 if (!dm_old_crtc_state->stream)
9230 /* Unset freesync video if it was active before */
9231 if (dm_old_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) {
9232 dm_new_crtc_state->freesync_config.state = VRR_STATE_INACTIVE;
9233 dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = 0;
9236 /* Now check if we should set freesync video mode */
9237 if (amdgpu_freesync_vid_mode && dm_new_crtc_state->stream &&
9238 is_timing_unchanged_for_freesync(new_crtc_state,
9240 new_crtc_state->mode_changed = false;
9242 "Mode change not required for front porch change, "
9243 "setting mode_changed to %d",
9244 new_crtc_state->mode_changed);
9246 set_freesync_fixed_config(dm_new_crtc_state);
9249 } else if (amdgpu_freesync_vid_mode && aconnector &&
9250 is_freesync_video_mode(&new_crtc_state->mode,
9252 struct drm_display_mode *high_mode;
9254 high_mode = get_highest_refresh_rate_mode(aconnector, false);
9255 if (!drm_mode_equal(&new_crtc_state->mode, high_mode)) {
9256 set_freesync_fixed_config(dm_new_crtc_state);
9260 ret = dm_atomic_get_state(state, &dm_state);
9264 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
9267 /* i.e. reset mode */
9268 if (dc_remove_stream_from_ctx(
9271 dm_old_crtc_state->stream) != DC_OK) {
9276 dc_stream_release(dm_old_crtc_state->stream);
9277 dm_new_crtc_state->stream = NULL;
9279 reset_freesync_config_for_crtc(dm_new_crtc_state);
9281 *lock_and_validation_needed = true;
9283 } else {/* Add stream for any updated/enabled CRTC */
9285 * Quick fix to prevent NULL pointer on new_stream when
9286 * added MST connectors not found in existing crtc_state in the chained mode
9287 * TODO: need to dig out the root cause of that
9292 if (modereset_required(new_crtc_state))
9295 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, new_stream,
9296 dm_old_crtc_state->stream)) {
9298 WARN_ON(dm_new_crtc_state->stream);
9300 ret = dm_atomic_get_state(state, &dm_state);
9304 dm_new_crtc_state->stream = new_stream;
9306 dc_stream_retain(new_stream);
9308 DRM_DEBUG_ATOMIC("Enabling DRM crtc: %d\n",
9311 if (dc_add_stream_to_ctx(
9314 dm_new_crtc_state->stream) != DC_OK) {
9319 *lock_and_validation_needed = true;
9324 /* Release extra reference */
9326 dc_stream_release(new_stream);
9329 * We want to do dc stream updates that do not require a
9330 * full modeset below.
9332 if (!(enable && aconnector && new_crtc_state->active))
9335 * Given above conditions, the dc state cannot be NULL because:
9336 * 1. We're in the process of enabling CRTCs (just been added
9337 * to the dc context, or already is on the context)
9338 * 2. Has a valid connector attached, and
9339 * 3. Is currently active and enabled.
9340 * => The dc stream state currently exists.
9342 BUG_ON(dm_new_crtc_state->stream == NULL);
9344 /* Scaling or underscan settings */
9345 if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state) ||
9346 drm_atomic_crtc_needs_modeset(new_crtc_state))
9347 update_stream_scaling_settings(
9348 &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);
9351 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
9354 * Color management settings. We also update color properties
9355 * when a modeset is needed, to ensure it gets reprogrammed.
9357 if (dm_new_crtc_state->base.color_mgmt_changed ||
9358 drm_atomic_crtc_needs_modeset(new_crtc_state)) {
9359 ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state);
9364 /* Update Freesync settings. */
9365 get_freesync_config_for_crtc(dm_new_crtc_state,
9372 dc_stream_release(new_stream);
9376 static bool should_reset_plane(struct drm_atomic_state *state,
9377 struct drm_plane *plane,
9378 struct drm_plane_state *old_plane_state,
9379 struct drm_plane_state *new_plane_state)
9381 struct drm_plane *other;
9382 struct drm_plane_state *old_other_state, *new_other_state;
9383 struct drm_crtc_state *new_crtc_state;
9387 * TODO: Remove this hack once the checks below are sufficient
9388 * enough to determine when we need to reset all the planes on
9391 if (state->allow_modeset)
9394 /* Exit early if we know that we're adding or removing the plane. */
9395 if (old_plane_state->crtc != new_plane_state->crtc)
9398 /* old crtc == new_crtc == NULL, plane not in context. */
9399 if (!new_plane_state->crtc)
9403 drm_atomic_get_new_crtc_state(state, new_plane_state->crtc);
9405 if (!new_crtc_state)
9408 /* CRTC Degamma changes currently require us to recreate planes. */
9409 if (new_crtc_state->color_mgmt_changed)
9412 if (drm_atomic_crtc_needs_modeset(new_crtc_state))
9416 * If there are any new primary or overlay planes being added or
9417 * removed then the z-order can potentially change. To ensure
9418 * correct z-order and pipe acquisition the current DC architecture
9419 * requires us to remove and recreate all existing planes.
9421 * TODO: Come up with a more elegant solution for this.
9423 for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) {
9424 struct amdgpu_framebuffer *old_afb, *new_afb;
9425 if (other->type == DRM_PLANE_TYPE_CURSOR)
9428 if (old_other_state->crtc != new_plane_state->crtc &&
9429 new_other_state->crtc != new_plane_state->crtc)
9432 if (old_other_state->crtc != new_other_state->crtc)
9435 /* Src/dst size and scaling updates. */
9436 if (old_other_state->src_w != new_other_state->src_w ||
9437 old_other_state->src_h != new_other_state->src_h ||
9438 old_other_state->crtc_w != new_other_state->crtc_w ||
9439 old_other_state->crtc_h != new_other_state->crtc_h)
9442 /* Rotation / mirroring updates. */
9443 if (old_other_state->rotation != new_other_state->rotation)
9446 /* Blending updates. */
9447 if (old_other_state->pixel_blend_mode !=
9448 new_other_state->pixel_blend_mode)
9451 /* Alpha updates. */
9452 if (old_other_state->alpha != new_other_state->alpha)
9455 /* Colorspace changes. */
9456 if (old_other_state->color_range != new_other_state->color_range ||
9457 old_other_state->color_encoding != new_other_state->color_encoding)
9460 /* Framebuffer checks fall at the end. */
9461 if (!old_other_state->fb || !new_other_state->fb)
9464 /* Pixel format changes can require bandwidth updates. */
9465 if (old_other_state->fb->format != new_other_state->fb->format)
9468 old_afb = (struct amdgpu_framebuffer *)old_other_state->fb;
9469 new_afb = (struct amdgpu_framebuffer *)new_other_state->fb;
9471 /* Tiling and DCC changes also require bandwidth updates. */
9472 if (old_afb->tiling_flags != new_afb->tiling_flags ||
9473 old_afb->base.modifier != new_afb->base.modifier)
9480 static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc,
9481 struct drm_plane_state *new_plane_state,
9482 struct drm_framebuffer *fb)
9484 struct amdgpu_device *adev = drm_to_adev(new_acrtc->base.dev);
9485 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
9489 if (fb->width > new_acrtc->max_cursor_width ||
9490 fb->height > new_acrtc->max_cursor_height) {
9491 DRM_DEBUG_ATOMIC("Bad cursor FB size %dx%d\n",
9492 new_plane_state->fb->width,
9493 new_plane_state->fb->height);
9496 if (new_plane_state->src_w != fb->width << 16 ||
9497 new_plane_state->src_h != fb->height << 16) {
9498 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
9502 /* Pitch in pixels */
9503 pitch = fb->pitches[0] / fb->format->cpp[0];
9505 if (fb->width != pitch) {
9506 DRM_DEBUG_ATOMIC("Cursor FB width %d doesn't match pitch %d",
9515 /* FB pitch is supported by cursor plane */
9518 DRM_DEBUG_ATOMIC("Bad cursor FB pitch %d px\n", pitch);
9522 /* Core DRM takes care of checking FB modifiers, so we only need to
9523 * check tiling flags when the FB doesn't have a modifier. */
9524 if (!(fb->flags & DRM_MODE_FB_MODIFIERS)) {
9525 if (adev->family < AMDGPU_FAMILY_AI) {
9526 linear = AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_2D_TILED_THIN1 &&
9527 AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 &&
9528 AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE) == 0;
9530 linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0;
9533 DRM_DEBUG_ATOMIC("Cursor FB not linear");
9541 static int dm_update_plane_state(struct dc *dc,
9542 struct drm_atomic_state *state,
9543 struct drm_plane *plane,
9544 struct drm_plane_state *old_plane_state,
9545 struct drm_plane_state *new_plane_state,
9547 bool *lock_and_validation_needed,
9548 bool *is_top_most_overlay)
9551 struct dm_atomic_state *dm_state = NULL;
9552 struct drm_crtc *new_plane_crtc, *old_plane_crtc;
9553 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
9554 struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
9555 struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
9556 struct amdgpu_crtc *new_acrtc;
9561 new_plane_crtc = new_plane_state->crtc;
9562 old_plane_crtc = old_plane_state->crtc;
9563 dm_new_plane_state = to_dm_plane_state(new_plane_state);
9564 dm_old_plane_state = to_dm_plane_state(old_plane_state);
9566 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
9567 if (!enable || !new_plane_crtc ||
9568 drm_atomic_plane_disabling(plane->state, new_plane_state))
9571 new_acrtc = to_amdgpu_crtc(new_plane_crtc);
9573 if (new_plane_state->src_x != 0 || new_plane_state->src_y != 0) {
9574 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
9578 if (new_plane_state->fb) {
9579 ret = dm_check_cursor_fb(new_acrtc, new_plane_state,
9580 new_plane_state->fb);
9588 needs_reset = should_reset_plane(state, plane, old_plane_state,
9591 /* Remove any changed/removed planes */
9596 if (!old_plane_crtc)
9599 old_crtc_state = drm_atomic_get_old_crtc_state(
9600 state, old_plane_crtc);
9601 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9603 if (!dm_old_crtc_state->stream)
9606 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",
9607 plane->base.id, old_plane_crtc->base.id);
9609 ret = dm_atomic_get_state(state, &dm_state);
9613 if (!dc_remove_plane_from_context(
9615 dm_old_crtc_state->stream,
9616 dm_old_plane_state->dc_state,
9617 dm_state->context)) {
9623 dc_plane_state_release(dm_old_plane_state->dc_state);
9624 dm_new_plane_state->dc_state = NULL;
9626 *lock_and_validation_needed = true;
9628 } else { /* Add new planes */
9629 struct dc_plane_state *dc_new_plane_state;
9631 if (drm_atomic_plane_disabling(plane->state, new_plane_state))
9634 if (!new_plane_crtc)
9637 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
9638 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9640 if (!dm_new_crtc_state->stream)
9646 ret = amdgpu_dm_plane_helper_check_state(new_plane_state, new_crtc_state);
9650 WARN_ON(dm_new_plane_state->dc_state);
9652 dc_new_plane_state = dc_create_plane_state(dc);
9653 if (!dc_new_plane_state)
9656 /* Block top most plane from being a video plane */
9657 if (plane->type == DRM_PLANE_TYPE_OVERLAY) {
9658 if (is_video_format(new_plane_state->fb->format->format) && *is_top_most_overlay)
9661 *is_top_most_overlay = false;
9664 DRM_DEBUG_ATOMIC("Enabling DRM plane: %d on DRM crtc %d\n",
9665 plane->base.id, new_plane_crtc->base.id);
9667 ret = fill_dc_plane_attributes(
9668 drm_to_adev(new_plane_crtc->dev),
9673 dc_plane_state_release(dc_new_plane_state);
9677 ret = dm_atomic_get_state(state, &dm_state);
9679 dc_plane_state_release(dc_new_plane_state);
9684 * Any atomic check errors that occur after this will
9685 * not need a release. The plane state will be attached
9686 * to the stream, and therefore part of the atomic
9687 * state. It'll be released when the atomic state is
9690 if (!dc_add_plane_to_context(
9692 dm_new_crtc_state->stream,
9694 dm_state->context)) {
9696 dc_plane_state_release(dc_new_plane_state);
9700 dm_new_plane_state->dc_state = dc_new_plane_state;
9702 dm_new_crtc_state->mpo_requested |= (plane->type == DRM_PLANE_TYPE_OVERLAY);
9704 /* Tell DC to do a full surface update every time there
9705 * is a plane change. Inefficient, but works for now.
9707 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
9709 *lock_and_validation_needed = true;
9716 static void dm_get_oriented_plane_size(struct drm_plane_state *plane_state,
9717 int *src_w, int *src_h)
9719 switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
9720 case DRM_MODE_ROTATE_90:
9721 case DRM_MODE_ROTATE_270:
9722 *src_w = plane_state->src_h >> 16;
9723 *src_h = plane_state->src_w >> 16;
9725 case DRM_MODE_ROTATE_0:
9726 case DRM_MODE_ROTATE_180:
9728 *src_w = plane_state->src_w >> 16;
9729 *src_h = plane_state->src_h >> 16;
9734 static int dm_check_crtc_cursor(struct drm_atomic_state *state,
9735 struct drm_crtc *crtc,
9736 struct drm_crtc_state *new_crtc_state)
9738 struct drm_plane *cursor = crtc->cursor, *underlying;
9739 struct drm_plane_state *new_cursor_state, *new_underlying_state;
9741 int cursor_scale_w, cursor_scale_h, underlying_scale_w, underlying_scale_h;
9742 int cursor_src_w, cursor_src_h;
9743 int underlying_src_w, underlying_src_h;
9745 /* On DCE and DCN there is no dedicated hardware cursor plane. We get a
9746 * cursor per pipe but it's going to inherit the scaling and
9747 * positioning from the underlying pipe. Check the cursor plane's
9748 * blending properties match the underlying planes'. */
9750 new_cursor_state = drm_atomic_get_new_plane_state(state, cursor);
9751 if (!new_cursor_state || !new_cursor_state->fb) {
9755 dm_get_oriented_plane_size(new_cursor_state, &cursor_src_w, &cursor_src_h);
9756 cursor_scale_w = new_cursor_state->crtc_w * 1000 / cursor_src_w;
9757 cursor_scale_h = new_cursor_state->crtc_h * 1000 / cursor_src_h;
9759 for_each_new_plane_in_state_reverse(state, underlying, new_underlying_state, i) {
9760 /* Narrow down to non-cursor planes on the same CRTC as the cursor */
9761 if (new_underlying_state->crtc != crtc || underlying == crtc->cursor)
9764 /* Ignore disabled planes */
9765 if (!new_underlying_state->fb)
9768 dm_get_oriented_plane_size(new_underlying_state,
9769 &underlying_src_w, &underlying_src_h);
9770 underlying_scale_w = new_underlying_state->crtc_w * 1000 / underlying_src_w;
9771 underlying_scale_h = new_underlying_state->crtc_h * 1000 / underlying_src_h;
9773 if (cursor_scale_w != underlying_scale_w ||
9774 cursor_scale_h != underlying_scale_h) {
9775 drm_dbg_atomic(crtc->dev,
9776 "Cursor [PLANE:%d:%s] scaling doesn't match underlying [PLANE:%d:%s]\n",
9777 cursor->base.id, cursor->name, underlying->base.id, underlying->name);
9781 /* If this plane covers the whole CRTC, no need to check planes underneath */
9782 if (new_underlying_state->crtc_x <= 0 &&
9783 new_underlying_state->crtc_y <= 0 &&
9784 new_underlying_state->crtc_x + new_underlying_state->crtc_w >= new_crtc_state->mode.hdisplay &&
9785 new_underlying_state->crtc_y + new_underlying_state->crtc_h >= new_crtc_state->mode.vdisplay)
9792 static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc)
9794 struct drm_connector *connector;
9795 struct drm_connector_state *conn_state, *old_conn_state;
9796 struct amdgpu_dm_connector *aconnector = NULL;
9798 for_each_oldnew_connector_in_state(state, connector, old_conn_state, conn_state, i) {
9799 if (!conn_state->crtc)
9800 conn_state = old_conn_state;
9802 if (conn_state->crtc != crtc)
9805 aconnector = to_amdgpu_dm_connector(connector);
9806 if (!aconnector->mst_output_port || !aconnector->mst_root)
9815 return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_root->mst_mgr);
9819 * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.
9821 * @dev: The DRM device
9822 * @state: The atomic state to commit
9824 * Validate that the given atomic state is programmable by DC into hardware.
9825 * This involves constructing a &struct dc_state reflecting the new hardware
9826 * state we wish to commit, then querying DC to see if it is programmable. It's
9827 * important not to modify the existing DC state. Otherwise, atomic_check
9828 * may unexpectedly commit hardware changes.
9830 * When validating the DC state, it's important that the right locks are
9831 * acquired. For full updates case which removes/adds/updates streams on one
9832 * CRTC while flipping on another CRTC, acquiring global lock will guarantee
9833 * that any such full update commit will wait for completion of any outstanding
9834 * flip using DRMs synchronization events.
9836 * Note that DM adds the affected connectors for all CRTCs in state, when that
9837 * might not seem necessary. This is because DC stream creation requires the
9838 * DC sink, which is tied to the DRM connector state. Cleaning this up should
9839 * be possible but non-trivial - a possible TODO item.
9841 * Return: -Error code if validation failed.
9843 static int amdgpu_dm_atomic_check(struct drm_device *dev,
9844 struct drm_atomic_state *state)
9846 struct amdgpu_device *adev = drm_to_adev(dev);
9847 struct dm_atomic_state *dm_state = NULL;
9848 struct dc *dc = adev->dm.dc;
9849 struct drm_connector *connector;
9850 struct drm_connector_state *old_con_state, *new_con_state;
9851 struct drm_crtc *crtc;
9852 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
9853 struct drm_plane *plane;
9854 struct drm_plane_state *old_plane_state, *new_plane_state;
9855 enum dc_status status;
9857 bool lock_and_validation_needed = false;
9858 bool is_top_most_overlay = true;
9859 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
9860 struct drm_dp_mst_topology_mgr *mgr;
9861 struct drm_dp_mst_topology_state *mst_state;
9862 struct dsc_mst_fairness_vars vars[MAX_PIPES];
9864 trace_amdgpu_dm_atomic_check_begin(state);
9866 ret = drm_atomic_helper_check_modeset(dev, state);
9868 DRM_DEBUG_DRIVER("drm_atomic_helper_check_modeset() failed\n");
9872 /* Check connector changes */
9873 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
9874 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
9875 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
9877 /* Skip connectors that are disabled or part of modeset already. */
9878 if (!new_con_state->crtc)
9881 new_crtc_state = drm_atomic_get_crtc_state(state, new_con_state->crtc);
9882 if (IS_ERR(new_crtc_state)) {
9883 DRM_DEBUG_DRIVER("drm_atomic_get_crtc_state() failed\n");
9884 ret = PTR_ERR(new_crtc_state);
9888 if (dm_old_con_state->abm_level != dm_new_con_state->abm_level ||
9889 dm_old_con_state->scaling != dm_new_con_state->scaling)
9890 new_crtc_state->connectors_changed = true;
9893 if (dc_resource_is_dsc_encoding_supported(dc)) {
9894 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
9895 if (drm_atomic_crtc_needs_modeset(new_crtc_state)) {
9896 ret = add_affected_mst_dsc_crtcs(state, crtc);
9898 DRM_DEBUG_DRIVER("add_affected_mst_dsc_crtcs() failed\n");
9904 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
9905 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9907 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
9908 !new_crtc_state->color_mgmt_changed &&
9909 old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled &&
9910 dm_old_crtc_state->dsc_force_changed == false)
9913 ret = amdgpu_dm_verify_lut_sizes(new_crtc_state);
9915 DRM_DEBUG_DRIVER("amdgpu_dm_verify_lut_sizes() failed\n");
9919 if (!new_crtc_state->enable)
9922 ret = drm_atomic_add_affected_connectors(state, crtc);
9924 DRM_DEBUG_DRIVER("drm_atomic_add_affected_connectors() failed\n");
9928 ret = drm_atomic_add_affected_planes(state, crtc);
9930 DRM_DEBUG_DRIVER("drm_atomic_add_affected_planes() failed\n");
9934 if (dm_old_crtc_state->dsc_force_changed)
9935 new_crtc_state->mode_changed = true;
9939 * Add all primary and overlay planes on the CRTC to the state
9940 * whenever a plane is enabled to maintain correct z-ordering
9941 * and to enable fast surface updates.
9943 drm_for_each_crtc(crtc, dev) {
9944 bool modified = false;
9946 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
9947 if (plane->type == DRM_PLANE_TYPE_CURSOR)
9950 if (new_plane_state->crtc == crtc ||
9951 old_plane_state->crtc == crtc) {
9960 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) {
9961 if (plane->type == DRM_PLANE_TYPE_CURSOR)
9965 drm_atomic_get_plane_state(state, plane);
9967 if (IS_ERR(new_plane_state)) {
9968 ret = PTR_ERR(new_plane_state);
9969 DRM_DEBUG_DRIVER("new_plane_state is BAD\n");
9976 * DC consults the zpos (layer_index in DC terminology) to determine the
9977 * hw plane on which to enable the hw cursor (see
9978 * `dcn10_can_pipe_disable_cursor`). By now, all modified planes are in
9979 * atomic state, so call drm helper to normalize zpos.
9981 ret = drm_atomic_normalize_zpos(dev, state);
9983 drm_dbg(dev, "drm_atomic_normalize_zpos() failed\n");
9987 /* Remove exiting planes if they are modified */
9988 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
9989 ret = dm_update_plane_state(dc, state, plane,
9993 &lock_and_validation_needed,
9994 &is_top_most_overlay);
9996 DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n");
10001 /* Disable all crtcs which require disable */
10002 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10003 ret = dm_update_crtc_state(&adev->dm, state, crtc,
10007 &lock_and_validation_needed);
10009 DRM_DEBUG_DRIVER("DISABLE: dm_update_crtc_state() failed\n");
10014 /* Enable all crtcs which require enable */
10015 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10016 ret = dm_update_crtc_state(&adev->dm, state, crtc,
10020 &lock_and_validation_needed);
10022 DRM_DEBUG_DRIVER("ENABLE: dm_update_crtc_state() failed\n");
10027 /* Add new/modified planes */
10028 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
10029 ret = dm_update_plane_state(dc, state, plane,
10033 &lock_and_validation_needed,
10034 &is_top_most_overlay);
10036 DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n");
10041 if (dc_resource_is_dsc_encoding_supported(dc)) {
10042 ret = pre_validate_dsc(state, &dm_state, vars);
10047 /* Run this here since we want to validate the streams we created */
10048 ret = drm_atomic_helper_check_planes(dev, state);
10050 DRM_DEBUG_DRIVER("drm_atomic_helper_check_planes() failed\n");
10054 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10055 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
10056 if (dm_new_crtc_state->mpo_requested)
10057 DRM_DEBUG_DRIVER("MPO enablement requested on crtc:[%p]\n", crtc);
10060 /* Check cursor planes scaling */
10061 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10062 ret = dm_check_crtc_cursor(state, crtc, new_crtc_state);
10064 DRM_DEBUG_DRIVER("dm_check_crtc_cursor() failed\n");
10069 if (state->legacy_cursor_update) {
10071 * This is a fast cursor update coming from the plane update
10072 * helper, check if it can be done asynchronously for better
10075 state->async_update =
10076 !drm_atomic_helper_async_check(dev, state);
10079 * Skip the remaining global validation if this is an async
10080 * update. Cursor updates can be done without affecting
10081 * state or bandwidth calcs and this avoids the performance
10082 * penalty of locking the private state object and
10083 * allocating a new dc_state.
10085 if (state->async_update)
10089 /* Check scaling and underscan changes*/
10090 /* TODO Removed scaling changes validation due to inability to commit
10091 * new stream into context w\o causing full reset. Need to
10092 * decide how to handle.
10094 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
10095 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
10096 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
10097 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
10099 /* Skip any modesets/resets */
10100 if (!acrtc || drm_atomic_crtc_needs_modeset(
10101 drm_atomic_get_new_crtc_state(state, &acrtc->base)))
10104 /* Skip any thing not scale or underscan changes */
10105 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
10108 lock_and_validation_needed = true;
10111 /* set the slot info for each mst_state based on the link encoding format */
10112 for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) {
10113 struct amdgpu_dm_connector *aconnector;
10114 struct drm_connector *connector;
10115 struct drm_connector_list_iter iter;
10116 u8 link_coding_cap;
10118 drm_connector_list_iter_begin(dev, &iter);
10119 drm_for_each_connector_iter(connector, &iter) {
10120 if (connector->index == mst_state->mgr->conn_base_id) {
10121 aconnector = to_amdgpu_dm_connector(connector);
10122 link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link);
10123 drm_dp_mst_update_slots(mst_state, link_coding_cap);
10128 drm_connector_list_iter_end(&iter);
10132 * Streams and planes are reset when there are changes that affect
10133 * bandwidth. Anything that affects bandwidth needs to go through
10134 * DC global validation to ensure that the configuration can be applied
10137 * We have to currently stall out here in atomic_check for outstanding
10138 * commits to finish in this case because our IRQ handlers reference
10139 * DRM state directly - we can end up disabling interrupts too early
10142 * TODO: Remove this stall and drop DM state private objects.
10144 if (lock_and_validation_needed) {
10145 ret = dm_atomic_get_state(state, &dm_state);
10147 DRM_DEBUG_DRIVER("dm_atomic_get_state() failed\n");
10151 ret = do_aquire_global_lock(dev, state);
10153 DRM_DEBUG_DRIVER("do_aquire_global_lock() failed\n");
10157 ret = compute_mst_dsc_configs_for_state(state, dm_state->context, vars);
10159 DRM_DEBUG_DRIVER("compute_mst_dsc_configs_for_state() failed\n");
10163 ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context, vars);
10165 DRM_DEBUG_DRIVER("dm_update_mst_vcpi_slots_for_dsc() failed\n");
10170 * Perform validation of MST topology in the state:
10171 * We need to perform MST atomic check before calling
10172 * dc_validate_global_state(), or there is a chance
10173 * to get stuck in an infinite loop and hang eventually.
10175 ret = drm_dp_mst_atomic_check(state);
10177 DRM_DEBUG_DRIVER("drm_dp_mst_atomic_check() failed\n");
10180 status = dc_validate_global_state(dc, dm_state->context, true);
10181 if (status != DC_OK) {
10182 DRM_DEBUG_DRIVER("DC global validation failure: %s (%d)",
10183 dc_status_to_str(status), status);
10189 * The commit is a fast update. Fast updates shouldn't change
10190 * the DC context, affect global validation, and can have their
10191 * commit work done in parallel with other commits not touching
10192 * the same resource. If we have a new DC context as part of
10193 * the DM atomic state from validation we need to free it and
10194 * retain the existing one instead.
10196 * Furthermore, since the DM atomic state only contains the DC
10197 * context and can safely be annulled, we can free the state
10198 * and clear the associated private object now to free
10199 * some memory and avoid a possible use-after-free later.
10202 for (i = 0; i < state->num_private_objs; i++) {
10203 struct drm_private_obj *obj = state->private_objs[i].ptr;
10205 if (obj->funcs == adev->dm.atomic_obj.funcs) {
10206 int j = state->num_private_objs-1;
10208 dm_atomic_destroy_state(obj,
10209 state->private_objs[i].state);
10211 /* If i is not at the end of the array then the
10212 * last element needs to be moved to where i was
10213 * before the array can safely be truncated.
10216 state->private_objs[i] =
10217 state->private_objs[j];
10219 state->private_objs[j].ptr = NULL;
10220 state->private_objs[j].state = NULL;
10221 state->private_objs[j].old_state = NULL;
10222 state->private_objs[j].new_state = NULL;
10224 state->num_private_objs = j;
10230 /* Store the overall update type for use later in atomic check. */
10231 for_each_new_crtc_in_state (state, crtc, new_crtc_state, i) {
10232 struct dm_crtc_state *dm_new_crtc_state =
10233 to_dm_crtc_state(new_crtc_state);
10235 dm_new_crtc_state->update_type = lock_and_validation_needed ?
10240 /* Must be success */
10243 trace_amdgpu_dm_atomic_check_finish(state, ret);
10248 if (ret == -EDEADLK)
10249 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
10250 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
10251 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
10253 DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret);
10255 trace_amdgpu_dm_atomic_check_finish(state, ret);
10260 static bool is_dp_capable_without_timing_msa(struct dc *dc,
10261 struct amdgpu_dm_connector *amdgpu_dm_connector)
10264 bool capable = false;
10266 if (amdgpu_dm_connector->dc_link &&
10267 dm_helpers_dp_read_dpcd(
10269 amdgpu_dm_connector->dc_link,
10270 DP_DOWN_STREAM_PORT_COUNT,
10272 sizeof(dpcd_data))) {
10273 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
10279 static bool dm_edid_parser_send_cea(struct amdgpu_display_manager *dm,
10280 unsigned int offset,
10281 unsigned int total_length,
10283 unsigned int length,
10284 struct amdgpu_hdmi_vsdb_info *vsdb)
10287 union dmub_rb_cmd cmd;
10288 struct dmub_cmd_send_edid_cea *input;
10289 struct dmub_cmd_edid_cea_output *output;
10291 if (length > DMUB_EDID_CEA_DATA_CHUNK_BYTES)
10294 memset(&cmd, 0, sizeof(cmd));
10296 input = &cmd.edid_cea.data.input;
10298 cmd.edid_cea.header.type = DMUB_CMD__EDID_CEA;
10299 cmd.edid_cea.header.sub_type = 0;
10300 cmd.edid_cea.header.payload_bytes =
10301 sizeof(cmd.edid_cea) - sizeof(cmd.edid_cea.header);
10302 input->offset = offset;
10303 input->length = length;
10304 input->cea_total_length = total_length;
10305 memcpy(input->payload, data, length);
10307 res = dc_dmub_srv_cmd_with_reply_data(dm->dc->ctx->dmub_srv, &cmd);
10309 DRM_ERROR("EDID CEA parser failed\n");
10313 output = &cmd.edid_cea.data.output;
10315 if (output->type == DMUB_CMD__EDID_CEA_ACK) {
10316 if (!output->ack.success) {
10317 DRM_ERROR("EDID CEA ack failed at offset %d\n",
10318 output->ack.offset);
10320 } else if (output->type == DMUB_CMD__EDID_CEA_AMD_VSDB) {
10321 if (!output->amd_vsdb.vsdb_found)
10324 vsdb->freesync_supported = output->amd_vsdb.freesync_supported;
10325 vsdb->amd_vsdb_version = output->amd_vsdb.amd_vsdb_version;
10326 vsdb->min_refresh_rate_hz = output->amd_vsdb.min_frame_rate;
10327 vsdb->max_refresh_rate_hz = output->amd_vsdb.max_frame_rate;
10329 DRM_WARN("Unknown EDID CEA parser results\n");
10336 static bool parse_edid_cea_dmcu(struct amdgpu_display_manager *dm,
10337 u8 *edid_ext, int len,
10338 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10342 /* send extension block to DMCU for parsing */
10343 for (i = 0; i < len; i += 8) {
10347 /* send 8 bytes a time */
10348 if (!dc_edid_parser_send_cea(dm->dc, i, len, &edid_ext[i], 8))
10352 /* EDID block sent completed, expect result */
10353 int version, min_rate, max_rate;
10355 res = dc_edid_parser_recv_amd_vsdb(dm->dc, &version, &min_rate, &max_rate);
10357 /* amd vsdb found */
10358 vsdb_info->freesync_supported = 1;
10359 vsdb_info->amd_vsdb_version = version;
10360 vsdb_info->min_refresh_rate_hz = min_rate;
10361 vsdb_info->max_refresh_rate_hz = max_rate;
10369 res = dc_edid_parser_recv_cea_ack(dm->dc, &offset);
10377 static bool parse_edid_cea_dmub(struct amdgpu_display_manager *dm,
10378 u8 *edid_ext, int len,
10379 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10383 /* send extension block to DMCU for parsing */
10384 for (i = 0; i < len; i += 8) {
10385 /* send 8 bytes a time */
10386 if (!dm_edid_parser_send_cea(dm, i, len, &edid_ext[i], 8, vsdb_info))
10390 return vsdb_info->freesync_supported;
10393 static bool parse_edid_cea(struct amdgpu_dm_connector *aconnector,
10394 u8 *edid_ext, int len,
10395 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10397 struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev);
10400 mutex_lock(&adev->dm.dc_lock);
10401 if (adev->dm.dmub_srv)
10402 ret = parse_edid_cea_dmub(&adev->dm, edid_ext, len, vsdb_info);
10404 ret = parse_edid_cea_dmcu(&adev->dm, edid_ext, len, vsdb_info);
10405 mutex_unlock(&adev->dm.dc_lock);
10409 static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector,
10410 struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info)
10412 u8 *edid_ext = NULL;
10414 bool valid_vsdb_found = false;
10416 /*----- drm_find_cea_extension() -----*/
10417 /* No EDID or EDID extensions */
10418 if (edid == NULL || edid->extensions == 0)
10421 /* Find CEA extension */
10422 for (i = 0; i < edid->extensions; i++) {
10423 edid_ext = (uint8_t *)edid + EDID_LENGTH * (i + 1);
10424 if (edid_ext[0] == CEA_EXT)
10428 if (i == edid->extensions)
10431 /*----- cea_db_offsets() -----*/
10432 if (edid_ext[0] != CEA_EXT)
10435 valid_vsdb_found = parse_edid_cea(aconnector, edid_ext, EDID_LENGTH, vsdb_info);
10437 return valid_vsdb_found ? i : -ENODEV;
10441 * amdgpu_dm_update_freesync_caps - Update Freesync capabilities
10443 * @connector: Connector to query.
10444 * @edid: EDID from monitor
10446 * Amdgpu supports Freesync in DP and HDMI displays, and it is required to keep
10447 * track of some of the display information in the internal data struct used by
10448 * amdgpu_dm. This function checks which type of connector we need to set the
10449 * FreeSync parameters.
10451 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
10455 struct detailed_timing *timing;
10456 struct detailed_non_pixel *data;
10457 struct detailed_data_monitor_range *range;
10458 struct amdgpu_dm_connector *amdgpu_dm_connector =
10459 to_amdgpu_dm_connector(connector);
10460 struct dm_connector_state *dm_con_state = NULL;
10461 struct dc_sink *sink;
10463 struct drm_device *dev = connector->dev;
10464 struct amdgpu_device *adev = drm_to_adev(dev);
10465 struct amdgpu_hdmi_vsdb_info vsdb_info = {0};
10466 bool freesync_capable = false;
10467 enum adaptive_sync_type as_type = ADAPTIVE_SYNC_TYPE_NONE;
10469 if (!connector->state) {
10470 DRM_ERROR("%s - Connector has no state", __func__);
10474 sink = amdgpu_dm_connector->dc_sink ?
10475 amdgpu_dm_connector->dc_sink :
10476 amdgpu_dm_connector->dc_em_sink;
10478 if (!edid || !sink) {
10479 dm_con_state = to_dm_connector_state(connector->state);
10481 amdgpu_dm_connector->min_vfreq = 0;
10482 amdgpu_dm_connector->max_vfreq = 0;
10483 amdgpu_dm_connector->pixel_clock_mhz = 0;
10484 connector->display_info.monitor_range.min_vfreq = 0;
10485 connector->display_info.monitor_range.max_vfreq = 0;
10486 freesync_capable = false;
10491 dm_con_state = to_dm_connector_state(connector->state);
10493 if (!adev->dm.freesync_module)
10496 if (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
10497 || sink->sink_signal == SIGNAL_TYPE_EDP) {
10498 bool edid_check_required = false;
10501 edid_check_required = is_dp_capable_without_timing_msa(
10503 amdgpu_dm_connector);
10506 if (edid_check_required == true && (edid->version > 1 ||
10507 (edid->version == 1 && edid->revision > 1))) {
10508 for (i = 0; i < 4; i++) {
10510 timing = &edid->detailed_timings[i];
10511 data = &timing->data.other_data;
10512 range = &data->data.range;
10514 * Check if monitor has continuous frequency mode
10516 if (data->type != EDID_DETAIL_MONITOR_RANGE)
10519 * Check for flag range limits only. If flag == 1 then
10520 * no additional timing information provided.
10521 * Default GTF, GTF Secondary curve and CVT are not
10524 if (range->flags != 1)
10527 amdgpu_dm_connector->min_vfreq = range->min_vfreq;
10528 amdgpu_dm_connector->max_vfreq = range->max_vfreq;
10529 amdgpu_dm_connector->pixel_clock_mhz =
10530 range->pixel_clock_mhz * 10;
10532 connector->display_info.monitor_range.min_vfreq = range->min_vfreq;
10533 connector->display_info.monitor_range.max_vfreq = range->max_vfreq;
10538 if (amdgpu_dm_connector->max_vfreq -
10539 amdgpu_dm_connector->min_vfreq > 10) {
10541 freesync_capable = true;
10544 } else if (edid && sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) {
10545 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
10546 if (i >= 0 && vsdb_info.freesync_supported) {
10547 timing = &edid->detailed_timings[i];
10548 data = &timing->data.other_data;
10550 amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
10551 amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
10552 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
10553 freesync_capable = true;
10555 connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz;
10556 connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz;
10560 as_type = dm_get_adaptive_sync_support_type(amdgpu_dm_connector->dc_link);
10562 if (as_type == FREESYNC_TYPE_PCON_IN_WHITELIST) {
10563 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
10564 if (i >= 0 && vsdb_info.freesync_supported && vsdb_info.amd_vsdb_version > 0) {
10566 amdgpu_dm_connector->pack_sdp_v1_3 = true;
10567 amdgpu_dm_connector->as_type = as_type;
10568 amdgpu_dm_connector->vsdb_info = vsdb_info;
10570 amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
10571 amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
10572 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
10573 freesync_capable = true;
10575 connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz;
10576 connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz;
10582 dm_con_state->freesync_capable = freesync_capable;
10584 if (connector->vrr_capable_property)
10585 drm_connector_set_vrr_capable_property(connector,
10589 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev)
10591 struct amdgpu_device *adev = drm_to_adev(dev);
10592 struct dc *dc = adev->dm.dc;
10595 mutex_lock(&adev->dm.dc_lock);
10596 if (dc->current_state) {
10597 for (i = 0; i < dc->current_state->stream_count; ++i)
10598 dc->current_state->streams[i]
10599 ->triggered_crtc_reset.enabled =
10600 adev->dm.force_timing_sync;
10602 dm_enable_per_frame_crtc_master_sync(dc->current_state);
10603 dc_trigger_sync(dc, dc->current_state);
10605 mutex_unlock(&adev->dm.dc_lock);
10608 void dm_write_reg_func(const struct dc_context *ctx, uint32_t address,
10609 u32 value, const char *func_name)
10611 #ifdef DM_CHECK_ADDR_0
10612 if (address == 0) {
10613 DC_ERR("invalid register write. address = 0");
10617 cgs_write_register(ctx->cgs_device, address, value);
10618 trace_amdgpu_dc_wreg(&ctx->perf_trace->write_count, address, value);
10621 uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address,
10622 const char *func_name)
10625 #ifdef DM_CHECK_ADDR_0
10626 if (address == 0) {
10627 DC_ERR("invalid register read; address = 0\n");
10632 if (ctx->dmub_srv &&
10633 ctx->dmub_srv->reg_helper_offload.gather_in_progress &&
10634 !ctx->dmub_srv->reg_helper_offload.should_burst_write) {
10639 value = cgs_read_register(ctx->cgs_device, address);
10641 trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address, value);
10646 int amdgpu_dm_process_dmub_aux_transfer_sync(
10647 struct dc_context *ctx,
10648 unsigned int link_index,
10649 struct aux_payload *payload,
10650 enum aux_return_code_type *operation_result)
10652 struct amdgpu_device *adev = ctx->driver_context;
10653 struct dmub_notification *p_notify = adev->dm.dmub_notify;
10656 mutex_lock(&adev->dm.dpia_aux_lock);
10657 if (!dc_process_dmub_aux_transfer_async(ctx->dc, link_index, payload)) {
10658 *operation_result = AUX_RET_ERROR_ENGINE_ACQUIRE;
10662 if (!wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) {
10663 DRM_ERROR("wait_for_completion_timeout timeout!");
10664 *operation_result = AUX_RET_ERROR_TIMEOUT;
10668 if (p_notify->result != AUX_RET_SUCCESS) {
10670 * Transient states before tunneling is enabled could
10671 * lead to this error. We can ignore this for now.
10673 if (p_notify->result != AUX_RET_ERROR_PROTOCOL_ERROR) {
10674 DRM_WARN("DPIA AUX failed on 0x%x(%d), error %d\n",
10675 payload->address, payload->length,
10678 *operation_result = AUX_RET_ERROR_INVALID_REPLY;
10683 payload->reply[0] = adev->dm.dmub_notify->aux_reply.command;
10684 if (!payload->write && p_notify->aux_reply.length &&
10685 (payload->reply[0] == AUX_TRANSACTION_REPLY_AUX_ACK)) {
10687 if (payload->length != p_notify->aux_reply.length) {
10688 DRM_WARN("invalid read length %d from DPIA AUX 0x%x(%d)!\n",
10689 p_notify->aux_reply.length,
10690 payload->address, payload->length);
10691 *operation_result = AUX_RET_ERROR_INVALID_REPLY;
10695 memcpy(payload->data, p_notify->aux_reply.data,
10696 p_notify->aux_reply.length);
10700 ret = p_notify->aux_reply.length;
10701 *operation_result = p_notify->result;
10703 reinit_completion(&adev->dm.dmub_aux_transfer_done);
10704 mutex_unlock(&adev->dm.dpia_aux_lock);
10708 int amdgpu_dm_process_dmub_set_config_sync(
10709 struct dc_context *ctx,
10710 unsigned int link_index,
10711 struct set_config_cmd_payload *payload,
10712 enum set_config_status *operation_result)
10714 struct amdgpu_device *adev = ctx->driver_context;
10715 bool is_cmd_complete;
10718 mutex_lock(&adev->dm.dpia_aux_lock);
10719 is_cmd_complete = dc_process_dmub_set_config_async(ctx->dc,
10720 link_index, payload, adev->dm.dmub_notify);
10722 if (is_cmd_complete || wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) {
10724 *operation_result = adev->dm.dmub_notify->sc_status;
10726 DRM_ERROR("wait_for_completion_timeout timeout!");
10728 *operation_result = SET_CONFIG_UNKNOWN_ERROR;
10731 if (!is_cmd_complete)
10732 reinit_completion(&adev->dm.dmub_aux_transfer_done);
10733 mutex_unlock(&adev->dm.dpia_aux_lock);
10738 * Check whether seamless boot is supported.
10740 * So far we only support seamless boot on CHIP_VANGOGH.
10741 * If everything goes well, we may consider expanding
10742 * seamless boot to other ASICs.
10744 bool check_seamless_boot_capability(struct amdgpu_device *adev)
10746 switch (adev->ip_versions[DCE_HWIP][0]) {
10747 case IP_VERSION(3, 0, 1):
10748 if (!adev->mman.keep_stolen_vga_memory)