drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 /* The caprices of the preprocessor require that this be declared right here */
  27 #define CREATE_TRACE_POINTS
  28
  29 #include "dm_services_types.h"
  30 #include "dc.h"
  31 #include "dc/inc/core_types.h"
  32
  33 #include "vid.h"
  34 #include "amdgpu.h"
  35 #include "amdgpu_display.h"
  36 #include "amdgpu_ucode.h"
  37 #include "atom.h"
  38 #include "amdgpu_dm.h"
  39 #include "amdgpu_pm.h"
  40
  41 #include "amd_shared.h"
  42 #include "amdgpu_dm_irq.h"
  43 #include "dm_helpers.h"
  44 #include "amdgpu_dm_mst_types.h"
  45 #if defined(CONFIG_DEBUG_FS)
  46 #include "amdgpu_dm_debugfs.h"
  47 #endif
  48
  49 #include "ivsrcid/ivsrcid_vislands30.h"
  50
  51 #include <linux/module.h>
  52 #include <linux/moduleparam.h>
  53 #include <linux/version.h>
  54 #include <linux/types.h>
  55 #include <linux/pm_runtime.h>
  56 #include <linux/firmware.h>
  57
  58 #include <drm/drmP.h>
  59 #include <drm/drm_atomic.h>
  60 #include <drm/drm_atomic_uapi.h>
  61 #include <drm/drm_atomic_helper.h>
  62 #include <drm/drm_dp_mst_helper.h>
  63 #include <drm/drm_fb_helper.h>
  64 #include <drm/drm_edid.h>
  65
  66 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
  67 #include "ivsrcid/irqsrcs_dcn_1_0.h"
  68
  69 #include "dcn/dcn_1_0_offset.h"
  70 #include "dcn/dcn_1_0_sh_mask.h"
  71 #include "soc15_hw_ip.h"
  72 #include "vega10_ip_offset.h"
  73
  74 #include "soc15_common.h"
  75 #endif
  76
  77 #include "modules/inc/mod_freesync.h"
  78 #include "modules/power/power_helpers.h"
  79 #include "modules/inc/mod_info_packet.h"
  80
  81 #define FIRMWARE_RAVEN_DMCU             "amdgpu/raven_dmcu.bin"
  82 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
  83
  84 /**
  85  * DOC: overview
  86  *
  87  * The AMDgpu display manager, **amdgpu_dm** (or even simpler,
  88  * **dm**) sits between DRM and DC. It acts as a liason, converting DRM
  89  * requests into DC requests, and DC responses into DRM responses.
  90  *
  91  * The root control structure is &struct amdgpu_display_manager.
  92  */
  93
  94 /* basic init/fini API */
  95 static int amdgpu_dm_init(struct amdgpu_device *adev);
  96 static void amdgpu_dm_fini(struct amdgpu_device *adev);
  97
  98 /*
  99  * initializes drm_device display related structures, based on the information
 100  * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
 101  * drm_encoder, drm_mode_config
 102  *
 103  * Returns 0 on success
 104  */
 105 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
 106 /* removes and deallocates the drm structures, created by the above function */
 107 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
 108
 109 static void
 110 amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector);
 111
 112 static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
 113                                 struct drm_plane *plane,
 114                                 unsigned long possible_crtcs,
 115                                 const struct dc_plane_cap *plane_cap);
 116 static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
 117                                struct drm_plane *plane,
 118                                uint32_t link_index);
 119 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
 120                                     struct amdgpu_dm_connector *amdgpu_dm_connector,
 121                                     uint32_t link_index,
 122                                     struct amdgpu_encoder *amdgpu_encoder);
 123 static int amdgpu_dm_encoder_init(struct drm_device *dev,
 124                                   struct amdgpu_encoder *aencoder,
 125                                   uint32_t link_index);
 126
 127 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
 128
 129 static int amdgpu_dm_atomic_commit(struct drm_device *dev,
 130                                    struct drm_atomic_state *state,
 131                                    bool nonblock);
 132
 133 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
 134
 135 static int amdgpu_dm_atomic_check(struct drm_device *dev,
 136                                   struct drm_atomic_state *state);
 137
 138 static void handle_cursor_update(struct drm_plane *plane,
 139                                  struct drm_plane_state *old_plane_state);
 140
 141 /*
 142  * dm_vblank_get_counter
 143  *
 144  * @brief
 145  * Get counter for number of vertical blanks
 146  *
 147  * @param
 148  * struct amdgpu_device *adev - [in] desired amdgpu device
 149  * int disp_idx - [in] which CRTC to get the counter from
 150  *
 151  * @return
 152  * Counter for vertical blanks
 153  */
 154 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
 155 {
 156         if (crtc >= adev->mode_info.num_crtc)
 157                 return 0;
 158         else {
 159                 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
 160                 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
 161                                 acrtc->base.state);
 162
 163
 164                 if (acrtc_state->stream == NULL) {
 165                         DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
 166                                   crtc);
 167                         return 0;
 168                 }
 169
 170                 return dc_stream_get_vblank_counter(acrtc_state->stream);
 171         }
 172 }
 173
 174 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
 175                                   u32 *vbl, u32 *position)
 176 {
 177         uint32_t v_blank_start, v_blank_end, h_position, v_position;
 178
 179         if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
 180                 return -EINVAL;
 181         else {
 182                 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
 183                 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
 184                                                 acrtc->base.state);
 185
 186                 if (acrtc_state->stream ==  NULL) {
 187                         DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
 188                                   crtc);
 189                         return 0;
 190                 }
 191
 192                 /*
 193                  * TODO rework base driver to use values directly.
 194                  * for now parse it back into reg-format
 195                  */
 196                 dc_stream_get_scanoutpos(acrtc_state->stream,
 197                                          &v_blank_start,
 198                                          &v_blank_end,
 199                                          &h_position,
 200                                          &v_position);
 201
 202                 *position = v_position | (h_position << 16);
 203                 *vbl = v_blank_start | (v_blank_end << 16);
 204         }
 205
 206         return 0;
 207 }
 208
 209 static bool dm_is_idle(void *handle)
 210 {
 211         /* XXX todo */
 212         return true;
 213 }
 214
 215 static int dm_wait_for_idle(void *handle)
 216 {
 217         /* XXX todo */
 218         return 0;
 219 }
 220
 221 static bool dm_check_soft_reset(void *handle)
 222 {
 223         return false;
 224 }
 225
 226 static int dm_soft_reset(void *handle)
 227 {
 228         /* XXX todo */
 229         return 0;
 230 }
 231
 232 static struct amdgpu_crtc *
 233 get_crtc_by_otg_inst(struct amdgpu_device *adev,
 234                      int otg_inst)
 235 {
 236         struct drm_device *dev = adev->ddev;
 237         struct drm_crtc *crtc;
 238         struct amdgpu_crtc *amdgpu_crtc;
 239
 240         if (otg_inst == -1) {
 241                 WARN_ON(1);
 242                 return adev->mode_info.crtcs[0];
 243         }
 244
 245         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 246                 amdgpu_crtc = to_amdgpu_crtc(crtc);
 247
 248                 if (amdgpu_crtc->otg_inst == otg_inst)
 249                         return amdgpu_crtc;
 250         }
 251
 252         return NULL;
 253 }
 254
 255 static inline bool amdgpu_dm_vrr_active(struct dm_crtc_state *dm_state)
 256 {
 257         return dm_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE ||
 258                dm_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
 259 }
 260
 261 static void dm_pflip_high_irq(void *interrupt_params)
 262 {
 263         struct amdgpu_crtc *amdgpu_crtc;
 264         struct common_irq_params *irq_params = interrupt_params;
 265         struct amdgpu_device *adev = irq_params->adev;
 266         unsigned long flags;
 267         struct drm_pending_vblank_event *e;
 268         struct dm_crtc_state *acrtc_state;
 269         uint32_t vpos, hpos, v_blank_start, v_blank_end;
 270         bool vrr_active;
 271
 272         amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
 273
 274         /* IRQ could occur when in initial stage */
 275         /* TODO work and BO cleanup */
 276         if (amdgpu_crtc == NULL) {
 277                 DRM_DEBUG_DRIVER("CRTC is null, returning.\n");
 278                 return;
 279         }
 280
 281         spin_lock_irqsave(&adev->ddev->event_lock, flags);
 282
 283         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
 284                 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
 285                                                  amdgpu_crtc->pflip_status,
 286                                                  AMDGPU_FLIP_SUBMITTED,
 287                                                  amdgpu_crtc->crtc_id,
 288                                                  amdgpu_crtc);
 289                 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
 290                 return;
 291         }
 292
 293         /* page flip completed. */
 294         e = amdgpu_crtc->event;
 295         amdgpu_crtc->event = NULL;
 296
 297         if (!e)
 298                 WARN_ON(1);
 299
 300         acrtc_state = to_dm_crtc_state(amdgpu_crtc->base.state);
 301         vrr_active = amdgpu_dm_vrr_active(acrtc_state);
 302
 303         /* Fixed refresh rate, or VRR scanout position outside front-porch? */
 304         if (!vrr_active ||
 305             !dc_stream_get_scanoutpos(acrtc_state->stream, &v_blank_start,
 306                                       &v_blank_end, &hpos, &vpos) ||
 307             (vpos < v_blank_start)) {
 308                 /* Update to correct count and vblank timestamp if racing with
 309                  * vblank irq. This also updates to the correct vblank timestamp
 310                  * even in VRR mode, as scanout is past the front-porch atm.
 311                  */
 312                 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
 313
 314                 /* Wake up userspace by sending the pageflip event with proper
 315                  * count and timestamp of vblank of flip completion.
 316                  */
 317                 if (e) {
 318                         drm_crtc_send_vblank_event(&amdgpu_crtc->base, e);
 319
 320                         /* Event sent, so done with vblank for this flip */
 321                         drm_crtc_vblank_put(&amdgpu_crtc->base);
 322                 }
 323         } else if (e) {
 324                 /* VRR active and inside front-porch: vblank count and
 325                  * timestamp for pageflip event will only be up to date after
 326                  * drm_crtc_handle_vblank() has been executed from late vblank
 327                  * irq handler after start of back-porch (vline 0). We queue the
 328                  * pageflip event for send-out by drm_crtc_handle_vblank() with
 329                  * updated timestamp and count, once it runs after us.
 330                  *
 331                  * We need to open-code this instead of using the helper
 332                  * drm_crtc_arm_vblank_event(), as that helper would
 333                  * call drm_crtc_accurate_vblank_count(), which we must
 334                  * not call in VRR mode while we are in front-porch!
 335                  */
 336
 337                 /* sequence will be replaced by real count during send-out. */
 338                 e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base);
 339                 e->pipe = amdgpu_crtc->crtc_id;
 340
 341                 list_add_tail(&e->base.link, &adev->ddev->vblank_event_list);
 342                 e = NULL;
 343         }
 344
 345         /* Keep track of vblank of this flip for flip throttling. We use the
 346          * cooked hw counter, as that one incremented at start of this vblank
 347          * of pageflip completion, so last_flip_vblank is the forbidden count
 348          * for queueing new pageflips if vsync + VRR is enabled.
 349          */
 350         amdgpu_crtc->last_flip_vblank = amdgpu_get_vblank_counter_kms(adev->ddev,
 351                                                         amdgpu_crtc->crtc_id);
 352
 353         amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
 354         spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
 355
 356         DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n",
 357                          amdgpu_crtc->crtc_id, amdgpu_crtc,
 358                          vrr_active, (int) !e);
 359 }
 360
 361 static void dm_vupdate_high_irq(void *interrupt_params)
 362 {
 363         struct common_irq_params *irq_params = interrupt_params;
 364         struct amdgpu_device *adev = irq_params->adev;
 365         struct amdgpu_crtc *acrtc;
 366         struct dm_crtc_state *acrtc_state;
 367         unsigned long flags;
 368
 369         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE);
 370
 371         if (acrtc) {
 372                 acrtc_state = to_dm_crtc_state(acrtc->base.state);
 373
 374                 DRM_DEBUG_DRIVER("crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id,
 375                                  amdgpu_dm_vrr_active(acrtc_state));
 376
 377                 /* Core vblank handling is done here after end of front-porch in
 378                  * vrr mode, as vblank timestamping will give valid results
 379                  * while now done after front-porch. This will also deliver
 380                  * page-flip completion events that have been queued to us
 381                  * if a pageflip happened inside front-porch.
 382                  */
 383                 if (amdgpu_dm_vrr_active(acrtc_state)) {
 384                         drm_crtc_handle_vblank(&acrtc->base);
 385
 386                         /* BTR processing for pre-DCE12 ASICs */
 387                         if (acrtc_state->stream &&
 388                             adev->family < AMDGPU_FAMILY_AI) {
 389                                 spin_lock_irqsave(&adev->ddev->event_lock, flags);
 390                                 mod_freesync_handle_v_update(
 391                                     adev->dm.freesync_module,
 392                                     acrtc_state->stream,
 393                                     &acrtc_state->vrr_params);
 394
 395                                 dc_stream_adjust_vmin_vmax(
 396                                     adev->dm.dc,
 397                                     acrtc_state->stream,
 398                                     &acrtc_state->vrr_params.adjust);
 399                                 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
 400                         }
 401                 }
 402         }
 403 }
 404
 405 static void dm_crtc_high_irq(void *interrupt_params)
 406 {
 407         struct common_irq_params *irq_params = interrupt_params;
 408         struct amdgpu_device *adev = irq_params->adev;
 409         struct amdgpu_crtc *acrtc;
 410         struct dm_crtc_state *acrtc_state;
 411         unsigned long flags;
 412
 413         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
 414
 415         if (acrtc) {
 416                 acrtc_state = to_dm_crtc_state(acrtc->base.state);
 417
 418                 DRM_DEBUG_DRIVER("crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id,
 419                                  amdgpu_dm_vrr_active(acrtc_state));
 420
 421                 /* Core vblank handling at start of front-porch is only possible
 422                  * in non-vrr mode, as only there vblank timestamping will give
 423                  * valid results while done in front-porch. Otherwise defer it
 424                  * to dm_vupdate_high_irq after end of front-porch.
 425                  */
 426                 if (!amdgpu_dm_vrr_active(acrtc_state))
 427                         drm_crtc_handle_vblank(&acrtc->base);
 428
 429                 /* Following stuff must happen at start of vblank, for crc
 430                  * computation and below-the-range btr support in vrr mode.
 431                  */
 432                 amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
 433
 434                 if (acrtc_state->stream && adev->family >= AMDGPU_FAMILY_AI &&
 435                     acrtc_state->vrr_params.supported &&
 436                     acrtc_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE) {
 437                         spin_lock_irqsave(&adev->ddev->event_lock, flags);
 438                         mod_freesync_handle_v_update(
 439                                 adev->dm.freesync_module,
 440                                 acrtc_state->stream,
 441                                 &acrtc_state->vrr_params);
 442
 443                         dc_stream_adjust_vmin_vmax(
 444                                 adev->dm.dc,
 445                                 acrtc_state->stream,
 446                                 &acrtc_state->vrr_params.adjust);
 447                         spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
 448                 }
 449         }
 450 }
 451
 452 static int dm_set_clockgating_state(void *handle,
 453                   enum amd_clockgating_state state)
 454 {
 455         return 0;
 456 }
 457
 458 static int dm_set_powergating_state(void *handle,
 459                   enum amd_powergating_state state)
 460 {
 461         return 0;
 462 }
 463
 464 /* Prototypes of private functions */
 465 static int dm_early_init(void* handle);
 466
 467 /* Allocate memory for FBC compressed data  */
 468 static void amdgpu_dm_fbc_init(struct drm_connector *connector)
 469 {
 470         struct drm_device *dev = connector->dev;
 471         struct amdgpu_device *adev = dev->dev_private;
 472         struct dm_comressor_info *compressor = &adev->dm.compressor;
 473         struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
 474         struct drm_display_mode *mode;
 475         unsigned long max_size = 0;
 476
 477         if (adev->dm.dc->fbc_compressor == NULL)
 478                 return;
 479
 480         if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
 481                 return;
 482
 483         if (compressor->bo_ptr)
 484                 return;
 485
 486
 487         list_for_each_entry(mode, &connector->modes, head) {
 488                 if (max_size < mode->htotal * mode->vtotal)
 489                         max_size = mode->htotal * mode->vtotal;
 490         }
 491
 492         if (max_size) {
 493                 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,
 494                             AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr,
 495                             &compressor->gpu_addr, &compressor->cpu_addr);
 496
 497                 if (r)
 498                         DRM_ERROR("DM: Failed to initialize FBC\n");
 499                 else {
 500                         adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
 501                         DRM_INFO("DM: FBC alloc %lu\n", max_size*4);
 502                 }
 503
 504         }
 505
 506 }
 507
 508 static int amdgpu_dm_init(struct amdgpu_device *adev)
 509 {
 510         struct dc_init_data init_data;
 511         adev->dm.ddev = adev->ddev;
 512         adev->dm.adev = adev;
 513
 514         /* Zero all the fields */
 515         memset(&init_data, 0, sizeof(init_data));
 516
 517         mutex_init(&adev->dm.dc_lock);
 518
 519         if(amdgpu_dm_irq_init(adev)) {
 520                 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
 521                 goto error;
 522         }
 523
 524         init_data.asic_id.chip_family = adev->family;
 525
 526         init_data.asic_id.pci_revision_id = adev->rev_id;
 527         init_data.asic_id.hw_internal_rev = adev->external_rev_id;
 528
 529         init_data.asic_id.vram_width = adev->gmc.vram_width;
 530         /* TODO: initialize init_data.asic_id.vram_type here!!!! */
 531         init_data.asic_id.atombios_base_address =
 532                 adev->mode_info.atom_context->bios;
 533
 534         init_data.driver = adev;
 535
 536         adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
 537
 538         if (!adev->dm.cgs_device) {
 539                 DRM_ERROR("amdgpu: failed to create cgs device.\n");
 540                 goto error;
 541         }
 542
 543         init_data.cgs_device = adev->dm.cgs_device;
 544
 545         init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
 546
 547         /*
 548          * TODO debug why this doesn't work on Raven
 549          */
 550         if (adev->flags & AMD_IS_APU &&
 551             adev->asic_type >= CHIP_CARRIZO &&
 552             adev->asic_type < CHIP_RAVEN)
 553                 init_data.flags.gpu_vm_support = true;
 554
 555         if (amdgpu_dc_feature_mask & DC_FBC_MASK)
 556                 init_data.flags.fbc_support = true;
 557
 558         init_data.flags.power_down_display_on_boot = true;
 559
 560         /* Display Core create. */
 561         adev->dm.dc = dc_create(&init_data);
 562
 563         if (adev->dm.dc) {
 564                 DRM_INFO("Display Core initialized with v%s!\n", DC_VER);
 565         } else {
 566                 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER);
 567                 goto error;
 568         }
 569
 570         adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
 571         if (!adev->dm.freesync_module) {
 572                 DRM_ERROR(
 573                 "amdgpu: failed to initialize freesync_module.\n");
 574         } else
 575                 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
 576                                 adev->dm.freesync_module);
 577
 578         amdgpu_dm_init_color_mod();
 579
 580         if (amdgpu_dm_initialize_drm_device(adev)) {
 581                 DRM_ERROR(
 582                 "amdgpu: failed to initialize sw for display support.\n");
 583                 goto error;
 584         }
 585
 586         /* Update the actual used number of crtc */
 587         adev->mode_info.num_crtc = adev->dm.display_indexes_num;
 588
 589         /* TODO: Add_display_info? */
 590
 591         /* TODO use dynamic cursor width */
 592         adev->ddev->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
 593         adev->ddev->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
 594
 595         if (drm_vblank_init(adev->ddev, adev->dm.display_indexes_num)) {
 596                 DRM_ERROR(
 597                 "amdgpu: failed to initialize sw for display support.\n");
 598                 goto error;
 599         }
 600
 601 #if defined(CONFIG_DEBUG_FS)
 602         if (dtn_debugfs_init(adev))
 603                 DRM_ERROR("amdgpu: failed initialize dtn debugfs support.\n");
 604 #endif
 605
 606         DRM_DEBUG_DRIVER("KMS initialized.\n");
 607
 608         return 0;
 609 error:
 610         amdgpu_dm_fini(adev);
 611
 612         return -EINVAL;
 613 }
 614
 615 static void amdgpu_dm_fini(struct amdgpu_device *adev)
 616 {
 617         amdgpu_dm_destroy_drm_device(&adev->dm);
 618         /*
 619          * TODO: pageflip, vlank interrupt
 620          *
 621          * amdgpu_dm_irq_fini(adev);
 622          */
 623
 624         if (adev->dm.cgs_device) {
 625                 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
 626                 adev->dm.cgs_device = NULL;
 627         }
 628         if (adev->dm.freesync_module) {
 629                 mod_freesync_destroy(adev->dm.freesync_module);
 630                 adev->dm.freesync_module = NULL;
 631         }
 632         /* DC Destroy TODO: Replace destroy DAL */
 633         if (adev->dm.dc)
 634                 dc_destroy(&adev->dm.dc);
 635
 636         mutex_destroy(&adev->dm.dc_lock);
 637
 638         return;
 639 }
 640
 641 static int load_dmcu_fw(struct amdgpu_device *adev)
 642 {
 643         const char *fw_name_dmcu;
 644         int r;
 645         const struct dmcu_firmware_header_v1_0 *hdr;
 646
 647         switch(adev->asic_type) {
 648         case CHIP_BONAIRE:
 649         case CHIP_HAWAII:
 650         case CHIP_KAVERI:
 651         case CHIP_KABINI:
 652         case CHIP_MULLINS:
 653         case CHIP_TONGA:
 654         case CHIP_FIJI:
 655         case CHIP_CARRIZO:
 656         case CHIP_STONEY:
 657         case CHIP_POLARIS11:
 658         case CHIP_POLARIS10:
 659         case CHIP_POLARIS12:
 660         case CHIP_VEGAM:
 661         case CHIP_VEGA10:
 662         case CHIP_VEGA12:
 663         case CHIP_VEGA20:
 664                 return 0;
 665         case CHIP_RAVEN:
 666                 fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
 667                 break;
 668         default:
 669                 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
 670                 return -EINVAL;
 671         }
 672
 673         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
 674                 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n");
 675                 return 0;
 676         }
 677
 678         r = request_firmware_direct(&adev->dm.fw_dmcu, fw_name_dmcu, adev->dev);
 679         if (r == -ENOENT) {
 680                 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */
 681                 DRM_DEBUG_KMS("dm: DMCU firmware not found\n");
 682                 adev->dm.fw_dmcu = NULL;
 683                 return 0;
 684         }
 685         if (r) {
 686                 dev_err(adev->dev, "amdgpu_dm: Can't load firmware \"%s\"\n",
 687                         fw_name_dmcu);
 688                 return r;
 689         }
 690
 691         r = amdgpu_ucode_validate(adev->dm.fw_dmcu);
 692         if (r) {
 693                 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n",
 694                         fw_name_dmcu);
 695                 release_firmware(adev->dm.fw_dmcu);
 696                 adev->dm.fw_dmcu = NULL;
 697                 return r;
 698         }
 699
 700         hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data;
 701         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM;
 702         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu;
 703         adev->firmware.fw_size +=
 704                 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
 705
 706         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV;
 707         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu;
 708         adev->firmware.fw_size +=
 709                 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
 710
 711         adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version);
 712
 713         DRM_DEBUG_KMS("PSP loading DMCU firmware\n");
 714
 715         return 0;
 716 }
 717
 718 static int dm_sw_init(void *handle)
 719 {
 720         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 721
 722         return load_dmcu_fw(adev);
 723 }
 724
 725 static int dm_sw_fini(void *handle)
 726 {
 727         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 728
 729         if(adev->dm.fw_dmcu) {
 730                 release_firmware(adev->dm.fw_dmcu);
 731                 adev->dm.fw_dmcu = NULL;
 732         }
 733
 734         return 0;
 735 }
 736
 737 static int detect_mst_link_for_all_connectors(struct drm_device *dev)
 738 {
 739         struct amdgpu_dm_connector *aconnector;
 740         struct drm_connector *connector;
 741         int ret = 0;
 742
 743         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
 744
 745         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 746                 aconnector = to_amdgpu_dm_connector(connector);
 747                 if (aconnector->dc_link->type == dc_connection_mst_branch &&
 748                     aconnector->mst_mgr.aux) {
 749                         DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
 750                                         aconnector, aconnector->base.base.id);
 751
 752                         ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
 753                         if (ret < 0) {
 754                                 DRM_ERROR("DM_MST: Failed to start MST\n");
 755                                 ((struct dc_link *)aconnector->dc_link)->type = dc_connection_single;
 756                                 return ret;
 757                                 }
 758                         }
 759         }
 760
 761         drm_modeset_unlock(&dev->mode_config.connection_mutex);
 762         return ret;
 763 }
 764
 765 static int dm_late_init(void *handle)
 766 {
 767         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 768
 769         struct dmcu_iram_parameters params;
 770         unsigned int linear_lut[16];
 771         int i;
 772         struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
 773         bool ret;
 774
 775         for (i = 0; i < 16; i++)
 776                 linear_lut[i] = 0xFFFF * i / 15;
 777
 778         params.set = 0;
 779         params.backlight_ramping_start = 0xCCCC;
 780         params.backlight_ramping_reduction = 0xCCCCCCCC;
 781         params.backlight_lut_array_size = 16;
 782         params.backlight_lut_array = linear_lut;
 783
 784         ret = dmcu_load_iram(dmcu, params);
 785
 786         if (!ret)
 787                 return -EINVAL;
 788
 789         return detect_mst_link_for_all_connectors(adev->ddev);
 790 }
 791
 792 static void s3_handle_mst(struct drm_device *dev, bool suspend)
 793 {
 794         struct amdgpu_dm_connector *aconnector;
 795         struct drm_connector *connector;
 796         struct drm_dp_mst_topology_mgr *mgr;
 797         int ret;
 798         bool need_hotplug = false;
 799
 800         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
 801
 802         list_for_each_entry(connector, &dev->mode_config.connector_list,
 803                             head) {
 804                 aconnector = to_amdgpu_dm_connector(connector);
 805                 if (aconnector->dc_link->type != dc_connection_mst_branch ||
 806                     aconnector->mst_port)
 807                         continue;
 808
 809                 mgr = &aconnector->mst_mgr;
 810
 811                 if (suspend) {
 812                         drm_dp_mst_topology_mgr_suspend(mgr);
 813                 } else {
 814                         ret = drm_dp_mst_topology_mgr_resume(mgr);
 815                         if (ret < 0) {
 816                                 drm_dp_mst_topology_mgr_set_mst(mgr, false);
 817                                 need_hotplug = true;
 818                         }
 819                 }
 820         }
 821
 822         drm_modeset_unlock(&dev->mode_config.connection_mutex);
 823
 824         if (need_hotplug)
 825                 drm_kms_helper_hotplug_event(dev);
 826 }
 827
 828 /**
 829  * dm_hw_init() - Initialize DC device
 830  * @handle: The base driver device containing the amdpgu_dm device.
 831  *
 832  * Initialize the &struct amdgpu_display_manager device. This involves calling
 833  * the initializers of each DM component, then populating the struct with them.
 834  *
 835  * Although the function implies hardware initialization, both hardware and
 836  * software are initialized here. Splitting them out to their relevant init
 837  * hooks is a future TODO item.
 838  *
 839  * Some notable things that are initialized here:
 840  *
 841  * - Display Core, both software and hardware
 842  * - DC modules that we need (freesync and color management)
 843  * - DRM software states
 844  * - Interrupt sources and handlers
 845  * - Vblank support
 846  * - Debug FS entries, if enabled
 847  */
 848 static int dm_hw_init(void *handle)
 849 {
 850         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 851         /* Create DAL display manager */
 852         amdgpu_dm_init(adev);
 853         amdgpu_dm_hpd_init(adev);
 854
 855         return 0;
 856 }
 857
 858 /**
 859  * dm_hw_fini() - Teardown DC device
 860  * @handle: The base driver device containing the amdpgu_dm device.
 861  *
 862  * Teardown components within &struct amdgpu_display_manager that require
 863  * cleanup. This involves cleaning up the DRM device, DC, and any modules that
 864  * were loaded. Also flush IRQ workqueues and disable them.
 865  */
 866 static int dm_hw_fini(void *handle)
 867 {
 868         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 869
 870         amdgpu_dm_hpd_fini(adev);
 871
 872         amdgpu_dm_irq_fini(adev);
 873         amdgpu_dm_fini(adev);
 874         return 0;
 875 }
 876
 877 static int dm_suspend(void *handle)
 878 {
 879         struct amdgpu_device *adev = handle;
 880         struct amdgpu_display_manager *dm = &adev->dm;
 881         int ret = 0;
 882
 883         WARN_ON(adev->dm.cached_state);
 884         adev->dm.cached_state = drm_atomic_helper_suspend(adev->ddev);
 885
 886         s3_handle_mst(adev->ddev, true);
 887
 888         amdgpu_dm_irq_suspend(adev);
 889
 890
 891         dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
 892
 893         return ret;
 894 }
 895
 896 static struct amdgpu_dm_connector *
 897 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
 898                                              struct drm_crtc *crtc)
 899 {
 900         uint32_t i;
 901         struct drm_connector_state *new_con_state;
 902         struct drm_connector *connector;
 903         struct drm_crtc *crtc_from_state;
 904
 905         for_each_new_connector_in_state(state, connector, new_con_state, i) {
 906                 crtc_from_state = new_con_state->crtc;
 907
 908                 if (crtc_from_state == crtc)
 909                         return to_amdgpu_dm_connector(connector);
 910         }
 911
 912         return NULL;
 913 }
 914
 915 static void emulated_link_detect(struct dc_link *link)
 916 {
 917         struct dc_sink_init_data sink_init_data = { 0 };
 918         struct display_sink_capability sink_caps = { 0 };
 919         enum dc_edid_status edid_status;
 920         struct dc_context *dc_ctx = link->ctx;
 921         struct dc_sink *sink = NULL;
 922         struct dc_sink *prev_sink = NULL;
 923
 924         link->type = dc_connection_none;
 925         prev_sink = link->local_sink;
 926
 927         if (prev_sink != NULL)
 928                 dc_sink_retain(prev_sink);
 929
 930         switch (link->connector_signal) {
 931         case SIGNAL_TYPE_HDMI_TYPE_A: {
 932                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 933                 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
 934                 break;
 935         }
 936
 937         case SIGNAL_TYPE_DVI_SINGLE_LINK: {
 938                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 939                 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 940                 break;
 941         }
 942
 943         case SIGNAL_TYPE_DVI_DUAL_LINK: {
 944                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 945                 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
 946                 break;
 947         }
 948
 949         case SIGNAL_TYPE_LVDS: {
 950                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 951                 sink_caps.signal = SIGNAL_TYPE_LVDS;
 952                 break;
 953         }
 954
 955         case SIGNAL_TYPE_EDP: {
 956                 sink_caps.transaction_type =
 957                         DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 958                 sink_caps.signal = SIGNAL_TYPE_EDP;
 959                 break;
 960         }
 961
 962         case SIGNAL_TYPE_DISPLAY_PORT: {
 963                 sink_caps.transaction_type =
 964                         DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 965                 sink_caps.signal = SIGNAL_TYPE_VIRTUAL;
 966                 break;
 967         }
 968
 969         default:
 970                 DC_ERROR("Invalid connector type! signal:%d\n",
 971                         link->connector_signal);
 972                 return;
 973         }
 974
 975         sink_init_data.link = link;
 976         sink_init_data.sink_signal = sink_caps.signal;
 977
 978         sink = dc_sink_create(&sink_init_data);
 979         if (!sink) {
 980                 DC_ERROR("Failed to create sink!\n");
 981                 return;
 982         }
 983
 984         /* dc_sink_create returns a new reference */
 985         link->local_sink = sink;
 986
 987         edid_status = dm_helpers_read_local_edid(
 988                         link->ctx,
 989                         link,
 990                         sink);
 991
 992         if (edid_status != EDID_OK)
 993                 DC_ERROR("Failed to read EDID");
 994
 995 }
 996
 997 static int dm_resume(void *handle)
 998 {
 999         struct amdgpu_device *adev = handle;
1000         struct drm_device *ddev = adev->ddev;
1001         struct amdgpu_display_manager *dm = &adev->dm;
1002         struct amdgpu_dm_connector *aconnector;
1003         struct drm_connector *connector;
1004         struct drm_crtc *crtc;
1005         struct drm_crtc_state *new_crtc_state;
1006         struct dm_crtc_state *dm_new_crtc_state;
1007         struct drm_plane *plane;
1008         struct drm_plane_state *new_plane_state;
1009         struct dm_plane_state *dm_new_plane_state;
1010         struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state);
1011         enum dc_connection_type new_connection_type = dc_connection_none;
1012         int i;
1013
1014         /* Recreate dc_state - DC invalidates it when setting power state to S3. */
1015         dc_release_state(dm_state->context);
1016         dm_state->context = dc_create_state(dm->dc);
1017         /* TODO: Remove dc_state->dccg, use dc->dccg directly. */
1018         dc_resource_state_construct(dm->dc, dm_state->context);
1019
1020         /* power on hardware */
1021         dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
1022
1023         /* program HPD filter */
1024         dc_resume(dm->dc);
1025
1026         /* On resume we need to  rewrite the MSTM control bits to enamble MST*/
1027         s3_handle_mst(ddev, false);
1028
1029         /*
1030          * early enable HPD Rx IRQ, should be done before set mode as short
1031          * pulse interrupts are used for MST
1032          */
1033         amdgpu_dm_irq_resume_early(adev);
1034
1035         /* Do detection*/
1036         list_for_each_entry(connector, &ddev->mode_config.connector_list, head) {
1037                 aconnector = to_amdgpu_dm_connector(connector);
1038
1039                 /*
1040                  * this is the case when traversing through already created
1041                  * MST connectors, should be skipped
1042                  */
1043                 if (aconnector->mst_port)
1044                         continue;
1045
1046                 mutex_lock(&aconnector->hpd_lock);
1047                 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type))
1048                         DRM_ERROR("KMS: Failed to detect connector\n");
1049
1050                 if (aconnector->base.force && new_connection_type == dc_connection_none)
1051                         emulated_link_detect(aconnector->dc_link);
1052                 else
1053                         dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
1054
1055                 if (aconnector->fake_enable && aconnector->dc_link->local_sink)
1056                         aconnector->fake_enable = false;
1057
1058                 if (aconnector->dc_sink)
1059                         dc_sink_release(aconnector->dc_sink);
1060                 aconnector->dc_sink = NULL;
1061                 amdgpu_dm_update_connector_after_detect(aconnector);
1062                 mutex_unlock(&aconnector->hpd_lock);
1063         }
1064
1065         /* Force mode set in atomic commit */
1066         for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)
1067                 new_crtc_state->active_changed = true;
1068
1069         /*
1070          * atomic_check is expected to create the dc states. We need to release
1071          * them here, since they were duplicated as part of the suspend
1072          * procedure.
1073          */
1074         for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {
1075                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
1076                 if (dm_new_crtc_state->stream) {
1077                         WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
1078                         dc_stream_release(dm_new_crtc_state->stream);
1079                         dm_new_crtc_state->stream = NULL;
1080                 }
1081         }
1082
1083         for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) {
1084                 dm_new_plane_state = to_dm_plane_state(new_plane_state);
1085                 if (dm_new_plane_state->dc_state) {
1086                         WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
1087                         dc_plane_state_release(dm_new_plane_state->dc_state);
1088                         dm_new_plane_state->dc_state = NULL;
1089                 }
1090         }
1091
1092         drm_atomic_helper_resume(ddev, dm->cached_state);
1093
1094         dm->cached_state = NULL;
1095
1096         amdgpu_dm_irq_resume_late(adev);
1097
1098         return 0;
1099 }
1100
1101 /**
1102  * DOC: DM Lifecycle
1103  *
1104  * DM (and consequently DC) is registered in the amdgpu base driver as a IP
1105  * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to
1106  * the base driver's device list to be initialized and torn down accordingly.
1107  *
1108  * The functions to do so are provided as hooks in &struct amd_ip_funcs.
1109  */
1110
1111 static const struct amd_ip_funcs amdgpu_dm_funcs = {
1112         .name = "dm",
1113         .early_init = dm_early_init,
1114         .late_init = dm_late_init,
1115         .sw_init = dm_sw_init,
1116         .sw_fini = dm_sw_fini,
1117         .hw_init = dm_hw_init,
1118         .hw_fini = dm_hw_fini,
1119         .suspend = dm_suspend,
1120         .resume = dm_resume,
1121         .is_idle = dm_is_idle,
1122         .wait_for_idle = dm_wait_for_idle,
1123         .check_soft_reset = dm_check_soft_reset,
1124         .soft_reset = dm_soft_reset,
1125         .set_clockgating_state = dm_set_clockgating_state,
1126         .set_powergating_state = dm_set_powergating_state,
1127 };
1128
1129 const struct amdgpu_ip_block_version dm_ip_block =
1130 {
1131         .type = AMD_IP_BLOCK_TYPE_DCE,
1132         .major = 1,
1133         .minor = 0,
1134         .rev = 0,
1135         .funcs = &amdgpu_dm_funcs,
1136 };
1137
1138
1139 /**
1140  * DOC: atomic
1141  *
1142  * *WIP*
1143  */
1144
1145 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
1146         .fb_create = amdgpu_display_user_framebuffer_create,
1147         .output_poll_changed = drm_fb_helper_output_poll_changed,
1148         .atomic_check = amdgpu_dm_atomic_check,
1149         .atomic_commit = amdgpu_dm_atomic_commit,
1150 };
1151
1152 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
1153         .atomic_commit_tail = amdgpu_dm_atomic_commit_tail
1154 };
1155
1156 static void
1157 amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector)
1158 {
1159         struct drm_connector *connector = &aconnector->base;
1160         struct drm_device *dev = connector->dev;
1161         struct dc_sink *sink;
1162
1163         /* MST handled by drm_mst framework */
1164         if (aconnector->mst_mgr.mst_state == true)
1165                 return;
1166
1167
1168         sink = aconnector->dc_link->local_sink;
1169         if (sink)
1170                 dc_sink_retain(sink);
1171
1172         /*
1173          * Edid mgmt connector gets first update only in mode_valid hook and then
1174          * the connector sink is set to either fake or physical sink depends on link status.
1175          * Skip if already done during boot.
1176          */
1177         if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
1178                         && aconnector->dc_em_sink) {
1179
1180                 /*
1181                  * For S3 resume with headless use eml_sink to fake stream
1182                  * because on resume connector->sink is set to NULL
1183                  */
1184                 mutex_lock(&dev->mode_config.mutex);
1185
1186                 if (sink) {
1187                         if (aconnector->dc_sink) {
1188                                 amdgpu_dm_update_freesync_caps(connector, NULL);
1189                                 /*
1190                                  * retain and release below are used to
1191                                  * bump up refcount for sink because the link doesn't point
1192                                  * to it anymore after disconnect, so on next crtc to connector
1193                                  * reshuffle by UMD we will get into unwanted dc_sink release
1194                                  */
1195                                 dc_sink_release(aconnector->dc_sink);
1196                         }
1197                         aconnector->dc_sink = sink;
1198                         dc_sink_retain(aconnector->dc_sink);
1199                         amdgpu_dm_update_freesync_caps(connector,
1200                                         aconnector->edid);
1201                 } else {
1202                         amdgpu_dm_update_freesync_caps(connector, NULL);
1203                         if (!aconnector->dc_sink) {
1204                                 aconnector->dc_sink = aconnector->dc_em_sink;
1205                                 dc_sink_retain(aconnector->dc_sink);
1206                         }
1207                 }
1208
1209                 mutex_unlock(&dev->mode_config.mutex);
1210
1211                 if (sink)
1212                         dc_sink_release(sink);
1213                 return;
1214         }
1215
1216         /*
1217          * TODO: temporary guard to look for proper fix
1218          * if this sink is MST sink, we should not do anything
1219          */
1220         if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
1221                 dc_sink_release(sink);
1222                 return;
1223         }
1224
1225         if (aconnector->dc_sink == sink) {
1226                 /*
1227                  * We got a DP short pulse (Link Loss, DP CTS, etc...).
1228                  * Do nothing!!
1229                  */
1230                 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
1231                                 aconnector->connector_id);
1232                 if (sink)
1233                         dc_sink_release(sink);
1234                 return;
1235         }
1236
1237         DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
1238                 aconnector->connector_id, aconnector->dc_sink, sink);
1239
1240         mutex_lock(&dev->mode_config.mutex);
1241
1242         /*
1243          * 1. Update status of the drm connector
1244          * 2. Send an event and let userspace tell us what to do
1245          */
1246         if (sink) {
1247                 /*
1248                  * TODO: check if we still need the S3 mode update workaround.
1249                  * If yes, put it here.
1250                  */
1251                 if (aconnector->dc_sink)
1252                         amdgpu_dm_update_freesync_caps(connector, NULL);
1253
1254                 aconnector->dc_sink = sink;
1255                 dc_sink_retain(aconnector->dc_sink);
1256                 if (sink->dc_edid.length == 0) {
1257                         aconnector->edid = NULL;
1258                         drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
1259                 } else {
1260                         aconnector->edid =
1261                                 (struct edid *) sink->dc_edid.raw_edid;
1262
1263
1264                         drm_connector_update_edid_property(connector,
1265                                         aconnector->edid);
1266                         drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,
1267                                             aconnector->edid);
1268                 }
1269                 amdgpu_dm_update_freesync_caps(connector, aconnector->edid);
1270
1271         } else {
1272                 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
1273                 amdgpu_dm_update_freesync_caps(connector, NULL);
1274                 drm_connector_update_edid_property(connector, NULL);
1275                 aconnector->num_modes = 0;
1276                 dc_sink_release(aconnector->dc_sink);
1277                 aconnector->dc_sink = NULL;
1278                 aconnector->edid = NULL;
1279         }
1280
1281         mutex_unlock(&dev->mode_config.mutex);
1282
1283         if (sink)
1284                 dc_sink_release(sink);
1285 }
1286
1287 static void handle_hpd_irq(void *param)
1288 {
1289         struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
1290         struct drm_connector *connector = &aconnector->base;
1291         struct drm_device *dev = connector->dev;
1292         enum dc_connection_type new_connection_type = dc_connection_none;
1293
1294         /*
1295          * In case of failure or MST no need to update connector status or notify the OS
1296          * since (for MST case) MST does this in its own context.
1297          */
1298         mutex_lock(&aconnector->hpd_lock);
1299
1300         if (aconnector->fake_enable)
1301                 aconnector->fake_enable = false;
1302
1303         if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type))
1304                 DRM_ERROR("KMS: Failed to detect connector\n");
1305
1306         if (aconnector->base.force && new_connection_type == dc_connection_none) {
1307                 emulated_link_detect(aconnector->dc_link);
1308
1309
1310                 drm_modeset_lock_all(dev);
1311                 dm_restore_drm_connector_state(dev, connector);
1312                 drm_modeset_unlock_all(dev);
1313
1314                 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
1315                         drm_kms_helper_hotplug_event(dev);
1316
1317         } else if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) {
1318                 amdgpu_dm_update_connector_after_detect(aconnector);
1319
1320
1321                 drm_modeset_lock_all(dev);
1322                 dm_restore_drm_connector_state(dev, connector);
1323                 drm_modeset_unlock_all(dev);
1324
1325                 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
1326                         drm_kms_helper_hotplug_event(dev);
1327         }
1328         mutex_unlock(&aconnector->hpd_lock);
1329
1330 }
1331
1332 static void dm_handle_hpd_rx_irq(struct amdgpu_dm_connector *aconnector)
1333 {
1334         uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
1335         uint8_t dret;
1336         bool new_irq_handled = false;
1337         int dpcd_addr;
1338         int dpcd_bytes_to_read;
1339
1340         const int max_process_count = 30;
1341         int process_count = 0;
1342
1343         const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
1344
1345         if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
1346                 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
1347                 /* DPCD 0x200 - 0x201 for downstream IRQ */
1348                 dpcd_addr = DP_SINK_COUNT;
1349         } else {
1350                 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
1351                 /* DPCD 0x2002 - 0x2005 for downstream IRQ */
1352                 dpcd_addr = DP_SINK_COUNT_ESI;
1353         }
1354
1355         dret = drm_dp_dpcd_read(
1356                 &aconnector->dm_dp_aux.aux,
1357                 dpcd_addr,
1358                 esi,
1359                 dpcd_bytes_to_read);
1360
1361         while (dret == dpcd_bytes_to_read &&
1362                 process_count < max_process_count) {
1363                 uint8_t retry;
1364                 dret = 0;
1365
1366                 process_count++;
1367
1368                 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
1369                 /* handle HPD short pulse irq */
1370                 if (aconnector->mst_mgr.mst_state)
1371                         drm_dp_mst_hpd_irq(
1372                                 &aconnector->mst_mgr,
1373                                 esi,
1374                                 &new_irq_handled);
1375
1376                 if (new_irq_handled) {
1377                         /* ACK at DPCD to notify down stream */
1378                         const int ack_dpcd_bytes_to_write =
1379                                 dpcd_bytes_to_read - 1;
1380
1381                         for (retry = 0; retry < 3; retry++) {
1382                                 uint8_t wret;
1383
1384                                 wret = drm_dp_dpcd_write(
1385                                         &aconnector->dm_dp_aux.aux,
1386                                         dpcd_addr + 1,
1387                                         &esi[1],
1388                                         ack_dpcd_bytes_to_write);
1389                                 if (wret == ack_dpcd_bytes_to_write)
1390                                         break;
1391                         }
1392
1393                         /* check if there is new irq to be handled */
1394                         dret = drm_dp_dpcd_read(
1395                                 &aconnector->dm_dp_aux.aux,
1396                                 dpcd_addr,
1397                                 esi,
1398                                 dpcd_bytes_to_read);
1399
1400                         new_irq_handled = false;
1401                 } else {
1402                         break;
1403                 }
1404         }
1405
1406         if (process_count == max_process_count)
1407                 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
1408 }
1409
1410 static void handle_hpd_rx_irq(void *param)
1411 {
1412         struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
1413         struct drm_connector *connector = &aconnector->base;
1414         struct drm_device *dev = connector->dev;
1415         struct dc_link *dc_link = aconnector->dc_link;
1416         bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
1417         enum dc_connection_type new_connection_type = dc_connection_none;
1418
1419         /*
1420          * TODO:Temporary add mutex to protect hpd interrupt not have a gpio
1421          * conflict, after implement i2c helper, this mutex should be
1422          * retired.
1423          */
1424         if (dc_link->type != dc_connection_mst_branch)
1425                 mutex_lock(&aconnector->hpd_lock);
1426
1427         if (dc_link_handle_hpd_rx_irq(dc_link, NULL, NULL) &&
1428                         !is_mst_root_connector) {
1429                 /* Downstream Port status changed. */
1430                 if (!dc_link_detect_sink(dc_link, &new_connection_type))
1431                         DRM_ERROR("KMS: Failed to detect connector\n");
1432
1433                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
1434                         emulated_link_detect(dc_link);
1435
1436                         if (aconnector->fake_enable)
1437                                 aconnector->fake_enable = false;
1438
1439                         amdgpu_dm_update_connector_after_detect(aconnector);
1440
1441
1442                         drm_modeset_lock_all(dev);
1443                         dm_restore_drm_connector_state(dev, connector);
1444                         drm_modeset_unlock_all(dev);
1445
1446                         drm_kms_helper_hotplug_event(dev);
1447                 } else if (dc_link_detect(dc_link, DETECT_REASON_HPDRX)) {
1448
1449                         if (aconnector->fake_enable)
1450                                 aconnector->fake_enable = false;
1451
1452                         amdgpu_dm_update_connector_after_detect(aconnector);
1453
1454
1455                         drm_modeset_lock_all(dev);
1456                         dm_restore_drm_connector_state(dev, connector);
1457                         drm_modeset_unlock_all(dev);
1458
1459                         drm_kms_helper_hotplug_event(dev);
1460                 }
1461         }
1462         if ((dc_link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
1463             (dc_link->type == dc_connection_mst_branch))
1464                 dm_handle_hpd_rx_irq(aconnector);
1465
1466         if (dc_link->type != dc_connection_mst_branch) {
1467                 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux);
1468                 mutex_unlock(&aconnector->hpd_lock);
1469         }
1470 }
1471
1472 static void register_hpd_handlers(struct amdgpu_device *adev)
1473 {
1474         struct drm_device *dev = adev->ddev;
1475         struct drm_connector *connector;
1476         struct amdgpu_dm_connector *aconnector;
1477         const struct dc_link *dc_link;
1478         struct dc_interrupt_params int_params = {0};
1479
1480         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1481         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1482
1483         list_for_each_entry(connector,
1484                         &dev->mode_config.connector_list, head) {
1485
1486                 aconnector = to_amdgpu_dm_connector(connector);
1487                 dc_link = aconnector->dc_link;
1488
1489                 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
1490                         int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1491                         int_params.irq_source = dc_link->irq_source_hpd;
1492
1493                         amdgpu_dm_irq_register_interrupt(adev, &int_params,
1494                                         handle_hpd_irq,
1495                                         (void *) aconnector);
1496                 }
1497
1498                 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
1499
1500                         /* Also register for DP short pulse (hpd_rx). */
1501                         int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1502                         int_params.irq_source = dc_link->irq_source_hpd_rx;
1503
1504                         amdgpu_dm_irq_register_interrupt(adev, &int_params,
1505                                         handle_hpd_rx_irq,
1506                                         (void *) aconnector);
1507                 }
1508         }
1509 }
1510
1511 /* Register IRQ sources and initialize IRQ callbacks */
1512 static int dce110_register_irq_handlers(struct amdgpu_device *adev)
1513 {
1514         struct dc *dc = adev->dm.dc;
1515         struct common_irq_params *c_irq_params;
1516         struct dc_interrupt_params int_params = {0};
1517         int r;
1518         int i;
1519         unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
1520
1521         if (adev->asic_type == CHIP_VEGA10 ||
1522             adev->asic_type == CHIP_VEGA12 ||
1523             adev->asic_type == CHIP_VEGA20 ||
1524             adev->asic_type == CHIP_RAVEN)
1525                 client_id = SOC15_IH_CLIENTID_DCE;
1526
1527         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1528         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1529
1530         /*
1531          * Actions of amdgpu_irq_add_id():
1532          * 1. Register a set() function with base driver.
1533          *    Base driver will call set() function to enable/disable an
1534          *    interrupt in DC hardware.
1535          * 2. Register amdgpu_dm_irq_handler().
1536          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1537          *    coming from DC hardware.
1538          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1539          *    for acknowledging and handling. */
1540
1541         /* Use VBLANK interrupt */
1542         for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
1543                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
1544                 if (r) {
1545                         DRM_ERROR("Failed to add crtc irq id!\n");
1546                         return r;
1547                 }
1548
1549                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1550                 int_params.irq_source =
1551                         dc_interrupt_to_irq_source(dc, i, 0);
1552
1553                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
1554
1555                 c_irq_params->adev = adev;
1556                 c_irq_params->irq_src = int_params.irq_source;
1557
1558                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1559                                 dm_crtc_high_irq, c_irq_params);
1560         }
1561
1562         /* Use VUPDATE interrupt */
1563         for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) {
1564                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq);
1565                 if (r) {
1566                         DRM_ERROR("Failed to add vupdate irq id!\n");
1567                         return r;
1568                 }
1569
1570                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1571                 int_params.irq_source =
1572                         dc_interrupt_to_irq_source(dc, i, 0);
1573
1574                 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
1575
1576                 c_irq_params->adev = adev;
1577                 c_irq_params->irq_src = int_params.irq_source;
1578
1579                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1580                                 dm_vupdate_high_irq, c_irq_params);
1581         }
1582
1583         /* Use GRPH_PFLIP interrupt */
1584         for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
1585                         i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
1586                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
1587                 if (r) {
1588                         DRM_ERROR("Failed to add page flip irq id!\n");
1589                         return r;
1590                 }
1591
1592                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1593                 int_params.irq_source =
1594                         dc_interrupt_to_irq_source(dc, i, 0);
1595
1596                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1597
1598                 c_irq_params->adev = adev;
1599                 c_irq_params->irq_src = int_params.irq_source;
1600
1601                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1602                                 dm_pflip_high_irq, c_irq_params);
1603
1604         }
1605
1606         /* HPD */
1607         r = amdgpu_irq_add_id(adev, client_id,
1608                         VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
1609         if (r) {
1610                 DRM_ERROR("Failed to add hpd irq id!\n");
1611                 return r;
1612         }
1613
1614         register_hpd_handlers(adev);
1615
1616         return 0;
1617 }
1618
1619 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1620 /* Register IRQ sources and initialize IRQ callbacks */
1621 static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
1622 {
1623         struct dc *dc = adev->dm.dc;
1624         struct common_irq_params *c_irq_params;
1625         struct dc_interrupt_params int_params = {0};
1626         int r;
1627         int i;
1628
1629         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1630         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1631
1632         /*
1633          * Actions of amdgpu_irq_add_id():
1634          * 1. Register a set() function with base driver.
1635          *    Base driver will call set() function to enable/disable an
1636          *    interrupt in DC hardware.
1637          * 2. Register amdgpu_dm_irq_handler().
1638          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1639          *    coming from DC hardware.
1640          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1641          *    for acknowledging and handling.
1642          */
1643
1644         /* Use VSTARTUP interrupt */
1645         for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
1646                         i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
1647                         i++) {
1648                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);
1649
1650                 if (r) {
1651                         DRM_ERROR("Failed to add crtc irq id!\n");
1652                         return r;
1653                 }
1654
1655                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1656                 int_params.irq_source =
1657                         dc_interrupt_to_irq_source(dc, i, 0);
1658
1659                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
1660
1661                 c_irq_params->adev = adev;
1662                 c_irq_params->irq_src = int_params.irq_source;
1663
1664                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1665                                 dm_crtc_high_irq, c_irq_params);
1666         }
1667
1668         /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to
1669          * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx
1670          * to trigger at end of each vblank, regardless of state of the lock,
1671          * matching DCE behaviour.
1672          */
1673         for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT;
1674              i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1;
1675              i++) {
1676                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq);
1677
1678                 if (r) {
1679                         DRM_ERROR("Failed to add vupdate irq id!\n");
1680                         return r;
1681                 }
1682
1683                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1684                 int_params.irq_source =
1685                         dc_interrupt_to_irq_source(dc, i, 0);
1686
1687                 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
1688
1689                 c_irq_params->adev = adev;
1690                 c_irq_params->irq_src = int_params.irq_source;
1691
1692                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1693                                 dm_vupdate_high_irq, c_irq_params);
1694         }
1695
1696         /* Use GRPH_PFLIP interrupt */
1697         for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
1698                         i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1;
1699                         i++) {
1700                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
1701                 if (r) {
1702                         DRM_ERROR("Failed to add page flip irq id!\n");
1703                         return r;
1704                 }
1705
1706                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1707                 int_params.irq_source =
1708                         dc_interrupt_to_irq_source(dc, i, 0);
1709
1710                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1711
1712                 c_irq_params->adev = adev;
1713                 c_irq_params->irq_src = int_params.irq_source;
1714
1715                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1716                                 dm_pflip_high_irq, c_irq_params);
1717
1718         }
1719
1720         /* HPD */
1721         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
1722                         &adev->hpd_irq);
1723         if (r) {
1724                 DRM_ERROR("Failed to add hpd irq id!\n");
1725                 return r;
1726         }
1727
1728         register_hpd_handlers(adev);
1729
1730         return 0;
1731 }
1732 #endif
1733
1734 /*
1735  * Acquires the lock for the atomic state object and returns
1736  * the new atomic state.
1737  *
1738  * This should only be called during atomic check.
1739  */
1740 static int dm_atomic_get_state(struct drm_atomic_state *state,
1741                                struct dm_atomic_state **dm_state)
1742 {
1743         struct drm_device *dev = state->dev;
1744         struct amdgpu_device *adev = dev->dev_private;
1745         struct amdgpu_display_manager *dm = &adev->dm;
1746         struct drm_private_state *priv_state;
1747
1748         if (*dm_state)
1749                 return 0;
1750
1751         priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj);
1752         if (IS_ERR(priv_state))
1753                 return PTR_ERR(priv_state);
1754
1755         *dm_state = to_dm_atomic_state(priv_state);
1756
1757         return 0;
1758 }
1759
1760 struct dm_atomic_state *
1761 dm_atomic_get_new_state(struct drm_atomic_state *state)
1762 {
1763         struct drm_device *dev = state->dev;
1764         struct amdgpu_device *adev = dev->dev_private;
1765         struct amdgpu_display_manager *dm = &adev->dm;
1766         struct drm_private_obj *obj;
1767         struct drm_private_state *new_obj_state;
1768         int i;
1769
1770         for_each_new_private_obj_in_state(state, obj, new_obj_state, i) {
1771                 if (obj->funcs == dm->atomic_obj.funcs)
1772                         return to_dm_atomic_state(new_obj_state);
1773         }
1774
1775         return NULL;
1776 }
1777
1778 struct dm_atomic_state *
1779 dm_atomic_get_old_state(struct drm_atomic_state *state)
1780 {
1781         struct drm_device *dev = state->dev;
1782         struct amdgpu_device *adev = dev->dev_private;
1783         struct amdgpu_display_manager *dm = &adev->dm;
1784         struct drm_private_obj *obj;
1785         struct drm_private_state *old_obj_state;
1786         int i;
1787
1788         for_each_old_private_obj_in_state(state, obj, old_obj_state, i) {
1789                 if (obj->funcs == dm->atomic_obj.funcs)
1790                         return to_dm_atomic_state(old_obj_state);
1791         }
1792
1793         return NULL;
1794 }
1795
1796 static struct drm_private_state *
1797 dm_atomic_duplicate_state(struct drm_private_obj *obj)
1798 {
1799         struct dm_atomic_state *old_state, *new_state;
1800
1801         new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
1802         if (!new_state)
1803                 return NULL;
1804
1805         __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base);
1806
1807         old_state = to_dm_atomic_state(obj->state);
1808
1809         if (old_state && old_state->context)
1810                 new_state->context = dc_copy_state(old_state->context);
1811
1812         if (!new_state->context) {
1813                 kfree(new_state);
1814                 return NULL;
1815         }
1816
1817         return &new_state->base;
1818 }
1819
1820 static void dm_atomic_destroy_state(struct drm_private_obj *obj,
1821                                     struct drm_private_state *state)
1822 {
1823         struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
1824
1825         if (dm_state && dm_state->context)
1826                 dc_release_state(dm_state->context);
1827
1828         kfree(dm_state);
1829 }
1830
1831 static struct drm_private_state_funcs dm_atomic_state_funcs = {
1832         .atomic_duplicate_state = dm_atomic_duplicate_state,
1833         .atomic_destroy_state = dm_atomic_destroy_state,
1834 };
1835
1836 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
1837 {
1838         struct dm_atomic_state *state;
1839         int r;
1840
1841         adev->mode_info.mode_config_initialized = true;
1842
1843         adev->ddev->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
1844         adev->ddev->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
1845
1846         adev->ddev->mode_config.max_width = 16384;
1847         adev->ddev->mode_config.max_height = 16384;
1848
1849         adev->ddev->mode_config.preferred_depth = 24;
1850         adev->ddev->mode_config.prefer_shadow = 1;
1851         /* indicates support for immediate flip */
1852         adev->ddev->mode_config.async_page_flip = true;
1853
1854         adev->ddev->mode_config.fb_base = adev->gmc.aper_base;
1855
1856         state = kzalloc(sizeof(*state), GFP_KERNEL);
1857         if (!state)
1858                 return -ENOMEM;
1859
1860         state->context = dc_create_state(adev->dm.dc);
1861         if (!state->context) {
1862                 kfree(state);
1863                 return -ENOMEM;
1864         }
1865
1866         dc_resource_state_copy_construct_current(adev->dm.dc, state->context);
1867
1868         drm_atomic_private_obj_init(adev->ddev,
1869                                     &adev->dm.atomic_obj,
1870                                     &state->base,
1871                                     &dm_atomic_state_funcs);
1872
1873         r = amdgpu_display_modeset_create_props(adev);
1874         if (r)
1875                 return r;
1876
1877         return 0;
1878 }
1879
1880 #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12
1881 #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255
1882
1883 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
1884         defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
1885
1886 static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm)
1887 {
1888 #if defined(CONFIG_ACPI)
1889         struct amdgpu_dm_backlight_caps caps;
1890
1891         if (dm->backlight_caps.caps_valid)
1892                 return;
1893
1894         amdgpu_acpi_get_backlight_caps(dm->adev, &caps);
1895         if (caps.caps_valid) {
1896                 dm->backlight_caps.min_input_signal = caps.min_input_signal;
1897                 dm->backlight_caps.max_input_signal = caps.max_input_signal;
1898                 dm->backlight_caps.caps_valid = true;
1899         } else {
1900                 dm->backlight_caps.min_input_signal =
1901                                 AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
1902                 dm->backlight_caps.max_input_signal =
1903                                 AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
1904         }
1905 #else
1906         dm->backlight_caps.min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
1907         dm->backlight_caps.max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
1908 #endif
1909 }
1910
1911 static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
1912 {
1913         struct amdgpu_display_manager *dm = bl_get_data(bd);
1914         struct amdgpu_dm_backlight_caps caps;
1915         uint32_t brightness = bd->props.brightness;
1916
1917         amdgpu_dm_update_backlight_caps(dm);
1918         caps = dm->backlight_caps;
1919         /*
1920          * The brightness input is in the range 0-255
1921          * It needs to be rescaled to be between the
1922          * requested min and max input signal
1923          *
1924          * It also needs to be scaled up by 0x101 to
1925          * match the DC interface which has a range of
1926          * 0 to 0xffff
1927          */
1928         brightness =
1929                 brightness
1930                 * 0x101
1931                 * (caps.max_input_signal - caps.min_input_signal)
1932                 / AMDGPU_MAX_BL_LEVEL
1933                 + caps.min_input_signal * 0x101;
1934
1935         if (dc_link_set_backlight_level(dm->backlight_link,
1936                         brightness, 0))
1937                 return 0;
1938         else
1939                 return 1;
1940 }
1941
1942 static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
1943 {
1944         struct amdgpu_display_manager *dm = bl_get_data(bd);
1945         int ret = dc_link_get_backlight_level(dm->backlight_link);
1946
1947         if (ret == DC_ERROR_UNEXPECTED)
1948                 return bd->props.brightness;
1949         return ret;
1950 }
1951
1952 static const struct backlight_ops amdgpu_dm_backlight_ops = {
1953         .get_brightness = amdgpu_dm_backlight_get_brightness,
1954         .update_status  = amdgpu_dm_backlight_update_status,
1955 };
1956
1957 static void
1958 amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm)
1959 {
1960         char bl_name[16];
1961         struct backlight_properties props = { 0 };
1962
1963         amdgpu_dm_update_backlight_caps(dm);
1964
1965         props.max_brightness = AMDGPU_MAX_BL_LEVEL;
1966         props.brightness = AMDGPU_MAX_BL_LEVEL;
1967         props.type = BACKLIGHT_RAW;
1968
1969         snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
1970                         dm->adev->ddev->primary->index);
1971
1972         dm->backlight_dev = backlight_device_register(bl_name,
1973                         dm->adev->ddev->dev,
1974                         dm,
1975                         &amdgpu_dm_backlight_ops,
1976                         &props);
1977
1978         if (IS_ERR(dm->backlight_dev))
1979                 DRM_ERROR("DM: Backlight registration failed!\n");
1980         else
1981                 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
1982 }
1983
1984 #endif
1985
1986 static int initialize_plane(struct amdgpu_display_manager *dm,
1987                             struct amdgpu_mode_info *mode_info, int plane_id,
1988                             enum drm_plane_type plane_type,
1989                             const struct dc_plane_cap *plane_cap)
1990 {
1991         struct drm_plane *plane;
1992         unsigned long possible_crtcs;
1993         int ret = 0;
1994
1995         plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL);
1996         if (!plane) {
1997                 DRM_ERROR("KMS: Failed to allocate plane\n");
1998                 return -ENOMEM;
1999         }
2000         plane->type = plane_type;
2001
2002         /*
2003          * HACK: IGT tests expect that the primary plane for a CRTC
2004          * can only have one possible CRTC. Only expose support for
2005          * any CRTC if they're not going to be used as a primary plane
2006          * for a CRTC - like overlay or underlay planes.
2007          */
2008         possible_crtcs = 1 << plane_id;
2009         if (plane_id >= dm->dc->caps.max_streams)
2010                 possible_crtcs = 0xff;
2011
2012         ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap);
2013
2014         if (ret) {
2015                 DRM_ERROR("KMS: Failed to initialize plane\n");
2016                 kfree(plane);
2017                 return ret;
2018         }
2019
2020         if (mode_info)
2021                 mode_info->planes[plane_id] = plane;
2022
2023         return ret;
2024 }
2025
2026
2027 static void register_backlight_device(struct amdgpu_display_manager *dm,
2028                                       struct dc_link *link)
2029 {
2030 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
2031         defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
2032
2033         if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
2034             link->type != dc_connection_none) {
2035                 /*
2036                  * Event if registration failed, we should continue with
2037                  * DM initialization because not having a backlight control
2038                  * is better then a black screen.
2039                  */
2040                 amdgpu_dm_register_backlight_device(dm);
2041
2042                 if (dm->backlight_dev)
2043                         dm->backlight_link = link;
2044         }
2045 #endif
2046 }
2047
2048
2049 /*
2050  * In this architecture, the association
2051  * connector -> encoder -> crtc
2052  * id not really requried. The crtc and connector will hold the
2053  * display_index as an abstraction to use with DAL component
2054  *
2055  * Returns 0 on success
2056  */
2057 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
2058 {
2059         struct amdgpu_display_manager *dm = &adev->dm;
2060         int32_t i;
2061         struct amdgpu_dm_connector *aconnector = NULL;
2062         struct amdgpu_encoder *aencoder = NULL;
2063         struct amdgpu_mode_info *mode_info = &adev->mode_info;
2064         uint32_t link_cnt;
2065         int32_t primary_planes;
2066         enum dc_connection_type new_connection_type = dc_connection_none;
2067         const struct dc_plane_cap *plane;
2068
2069         link_cnt = dm->dc->caps.max_links;
2070         if (amdgpu_dm_mode_config_init(dm->adev)) {
2071                 DRM_ERROR("DM: Failed to initialize mode config\n");
2072                 return -EINVAL;
2073         }
2074
2075         /* There is one primary plane per CRTC */
2076         primary_planes = dm->dc->caps.max_streams;
2077         ASSERT(primary_planes <= AMDGPU_MAX_PLANES);
2078
2079         /*
2080          * Initialize primary planes, implicit planes for legacy IOCTLS.
2081          * Order is reversed to match iteration order in atomic check.
2082          */
2083         for (i = (primary_planes - 1); i >= 0; i--) {
2084                 plane = &dm->dc->caps.planes[i];
2085
2086                 if (initialize_plane(dm, mode_info, i,
2087                                      DRM_PLANE_TYPE_PRIMARY, plane)) {
2088                         DRM_ERROR("KMS: Failed to initialize primary plane\n");
2089                         goto fail;
2090                 }
2091         }
2092
2093         /*
2094          * Initialize overlay planes, index starting after primary planes.
2095          * These planes have a higher DRM index than the primary planes since
2096          * they should be considered as having a higher z-order.
2097          * Order is reversed to match iteration order in atomic check.
2098          *
2099          * Only support DCN for now, and only expose one so we don't encourage
2100          * userspace to use up all the pipes.
2101          */
2102         for (i = 0; i < dm->dc->caps.max_planes; ++i) {
2103                 struct dc_plane_cap *plane = &dm->dc->caps.planes[i];
2104
2105                 if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL)
2106                         continue;
2107
2108                 if (!plane->blends_with_above || !plane->blends_with_below)
2109                         continue;
2110
2111                 if (!plane->pixel_format_support.argb8888)
2112                         continue;
2113
2114                 if (initialize_plane(dm, NULL, primary_planes + i,
2115                                      DRM_PLANE_TYPE_OVERLAY, plane)) {
2116                         DRM_ERROR("KMS: Failed to initialize overlay plane\n");
2117                         goto fail;
2118                 }
2119
2120                 /* Only create one overlay plane. */
2121                 break;
2122         }
2123
2124         for (i = 0; i < dm->dc->caps.max_streams; i++)
2125                 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) {
2126                         DRM_ERROR("KMS: Failed to initialize crtc\n");
2127                         goto fail;
2128                 }
2129
2130         dm->display_indexes_num = dm->dc->caps.max_streams;
2131
2132         /* loops over all connectors on the board */
2133         for (i = 0; i < link_cnt; i++) {
2134                 struct dc_link *link = NULL;
2135
2136                 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
2137                         DRM_ERROR(
2138                                 "KMS: Cannot support more than %d display indexes\n",
2139                                         AMDGPU_DM_MAX_DISPLAY_INDEX);
2140                         continue;
2141                 }
2142
2143                 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
2144                 if (!aconnector)
2145                         goto fail;
2146
2147                 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
2148                 if (!aencoder)
2149                         goto fail;
2150
2151                 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
2152                         DRM_ERROR("KMS: Failed to initialize encoder\n");
2153                         goto fail;
2154                 }
2155
2156                 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
2157                         DRM_ERROR("KMS: Failed to initialize connector\n");
2158                         goto fail;
2159                 }
2160
2161                 link = dc_get_link_at_index(dm->dc, i);
2162
2163                 if (!dc_link_detect_sink(link, &new_connection_type))
2164                         DRM_ERROR("KMS: Failed to detect connector\n");
2165
2166                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
2167                         emulated_link_detect(link);
2168                         amdgpu_dm_update_connector_after_detect(aconnector);
2169
2170                 } else if (dc_link_detect(link, DETECT_REASON_BOOT)) {
2171                         amdgpu_dm_update_connector_after_detect(aconnector);
2172                         register_backlight_device(dm, link);
2173                 }
2174
2175
2176         }
2177
2178         /* Software is initialized. Now we can register interrupt handlers. */
2179         switch (adev->asic_type) {
2180         case CHIP_BONAIRE:
2181         case CHIP_HAWAII:
2182         case CHIP_KAVERI:
2183         case CHIP_KABINI:
2184         case CHIP_MULLINS:
2185         case CHIP_TONGA:
2186         case CHIP_FIJI:
2187         case CHIP_CARRIZO:
2188         case CHIP_STONEY:
2189         case CHIP_POLARIS11:
2190         case CHIP_POLARIS10:
2191         case CHIP_POLARIS12:
2192         case CHIP_VEGAM:
2193         case CHIP_VEGA10:
2194         case CHIP_VEGA12:
2195         case CHIP_VEGA20:
2196                 if (dce110_register_irq_handlers(dm->adev)) {
2197                         DRM_ERROR("DM: Failed to initialize IRQ\n");
2198                         goto fail;
2199                 }
2200                 break;
2201 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
2202         case CHIP_RAVEN:
2203                 if (dcn10_register_irq_handlers(dm->adev)) {
2204                         DRM_ERROR("DM: Failed to initialize IRQ\n");
2205                         goto fail;
2206                 }
2207                 break;
2208 #endif
2209         default:
2210                 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
2211                 goto fail;
2212         }
2213
2214         if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY)
2215                 dm->dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;
2216
2217         return 0;
2218 fail:
2219         kfree(aencoder);
2220         kfree(aconnector);
2221
2222         return -EINVAL;
2223 }
2224
2225 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
2226 {
2227         drm_mode_config_cleanup(dm->ddev);
2228         drm_atomic_private_obj_fini(&dm->atomic_obj);
2229         return;
2230 }
2231
2232 /******************************************************************************
2233  * amdgpu_display_funcs functions
2234  *****************************************************************************/
2235
2236 /*
2237  * dm_bandwidth_update - program display watermarks
2238  *
2239  * @adev: amdgpu_device pointer
2240  *
2241  * Calculate and program the display watermarks and line buffer allocation.
2242  */
2243 static void dm_bandwidth_update(struct amdgpu_device *adev)
2244 {
2245         /* TODO: implement later */
2246 }
2247
2248 static const struct amdgpu_display_funcs dm_display_funcs = {
2249         .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
2250         .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
2251         .backlight_set_level = NULL, /* never called for DC */
2252         .backlight_get_level = NULL, /* never called for DC */
2253         .hpd_sense = NULL,/* called unconditionally */
2254         .hpd_set_polarity = NULL, /* called unconditionally */
2255         .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
2256         .page_flip_get_scanoutpos =
2257                 dm_crtc_get_scanoutpos,/* called unconditionally */
2258         .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
2259         .add_connector = NULL, /* VBIOS parsing. DAL does it. */
2260 };
2261
2262 #if defined(CONFIG_DEBUG_KERNEL_DC)
2263
2264 static ssize_t s3_debug_store(struct device *device,
2265                               struct device_attribute *attr,
2266                               const char *buf,
2267                               size_t count)
2268 {
2269         int ret;
2270         int s3_state;
2271         struct pci_dev *pdev = to_pci_dev(device);
2272         struct drm_device *drm_dev = pci_get_drvdata(pdev);
2273         struct amdgpu_device *adev = drm_dev->dev_private;
2274
2275         ret = kstrtoint(buf, 0, &s3_state);
2276
2277         if (ret == 0) {
2278                 if (s3_state) {
2279                         dm_resume(adev);
2280                         drm_kms_helper_hotplug_event(adev->ddev);
2281                 } else
2282                         dm_suspend(adev);
2283         }
2284
2285         return ret == 0 ? count : 0;
2286 }
2287
2288 DEVICE_ATTR_WO(s3_debug);
2289
2290 #endif
2291
2292 static int dm_early_init(void *handle)
2293 {
2294         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2295
2296         switch (adev->asic_type) {
2297         case CHIP_BONAIRE:
2298         case CHIP_HAWAII:
2299                 adev->mode_info.num_crtc = 6;
2300                 adev->mode_info.num_hpd = 6;
2301                 adev->mode_info.num_dig = 6;
2302                 break;
2303         case CHIP_KAVERI:
2304                 adev->mode_info.num_crtc = 4;
2305                 adev->mode_info.num_hpd = 6;
2306                 adev->mode_info.num_dig = 7;
2307                 break;
2308         case CHIP_KABINI:
2309         case CHIP_MULLINS:
2310                 adev->mode_info.num_crtc = 2;
2311                 adev->mode_info.num_hpd = 6;
2312                 adev->mode_info.num_dig = 6;
2313                 break;
2314         case CHIP_FIJI:
2315         case CHIP_TONGA:
2316                 adev->mode_info.num_crtc = 6;
2317                 adev->mode_info.num_hpd = 6;
2318                 adev->mode_info.num_dig = 7;
2319                 break;
2320         case CHIP_CARRIZO:
2321                 adev->mode_info.num_crtc = 3;
2322                 adev->mode_info.num_hpd = 6;
2323                 adev->mode_info.num_dig = 9;
2324                 break;
2325         case CHIP_STONEY:
2326                 adev->mode_info.num_crtc = 2;
2327                 adev->mode_info.num_hpd = 6;
2328                 adev->mode_info.num_dig = 9;
2329                 break;
2330         case CHIP_POLARIS11:
2331         case CHIP_POLARIS12:
2332                 adev->mode_info.num_crtc = 5;
2333                 adev->mode_info.num_hpd = 5;
2334                 adev->mode_info.num_dig = 5;
2335                 break;
2336         case CHIP_POLARIS10:
2337         case CHIP_VEGAM:
2338                 adev->mode_info.num_crtc = 6;
2339                 adev->mode_info.num_hpd = 6;
2340                 adev->mode_info.num_dig = 6;
2341                 break;
2342         case CHIP_VEGA10:
2343         case CHIP_VEGA12:
2344         case CHIP_VEGA20:
2345                 adev->mode_info.num_crtc = 6;
2346                 adev->mode_info.num_hpd = 6;
2347                 adev->mode_info.num_dig = 6;
2348                 break;
2349 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
2350         case CHIP_RAVEN:
2351                 adev->mode_info.num_crtc = 4;
2352                 adev->mode_info.num_hpd = 4;
2353                 adev->mode_info.num_dig = 4;
2354                 break;
2355 #endif
2356         default:
2357                 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
2358                 return -EINVAL;
2359         }
2360
2361         amdgpu_dm_set_irq_funcs(adev);
2362
2363         if (adev->mode_info.funcs == NULL)
2364                 adev->mode_info.funcs = &dm_display_funcs;
2365
2366         /*
2367          * Note: Do NOT change adev->audio_endpt_rreg and
2368          * adev->audio_endpt_wreg because they are initialised in
2369          * amdgpu_device_init()
2370          */
2371 #if defined(CONFIG_DEBUG_KERNEL_DC)
2372         device_create_file(
2373                 adev->ddev->dev,
2374                 &dev_attr_s3_debug);
2375 #endif
2376
2377         return 0;
2378 }
2379
2380 static bool modeset_required(struct drm_crtc_state *crtc_state,
2381                              struct dc_stream_state *new_stream,
2382                              struct dc_stream_state *old_stream)
2383 {
2384         if (!drm_atomic_crtc_needs_modeset(crtc_state))
2385                 return false;
2386
2387         if (!crtc_state->enable)
2388                 return false;
2389
2390         return crtc_state->active;
2391 }
2392
2393 static bool modereset_required(struct drm_crtc_state *crtc_state)
2394 {
2395         if (!drm_atomic_crtc_needs_modeset(crtc_state))
2396                 return false;
2397
2398         return !crtc_state->enable || !crtc_state->active;
2399 }
2400
2401 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
2402 {
2403         drm_encoder_cleanup(encoder);
2404         kfree(encoder);
2405 }
2406
2407 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
2408         .destroy = amdgpu_dm_encoder_destroy,
2409 };
2410
2411
2412 static int fill_dc_scaling_info(const struct drm_plane_state *state,
2413                                 struct dc_scaling_info *scaling_info)
2414 {
2415         int scale_w, scale_h;
2416
2417         memset(scaling_info, 0, sizeof(*scaling_info));
2418
2419         /* Source is fixed 16.16 but we ignore mantissa for now... */
2420         scaling_info->src_rect.x = state->src_x >> 16;
2421         scaling_info->src_rect.y = state->src_y >> 16;
2422
2423         scaling_info->src_rect.width = state->src_w >> 16;
2424         if (scaling_info->src_rect.width == 0)
2425                 return -EINVAL;
2426
2427         scaling_info->src_rect.height = state->src_h >> 16;
2428         if (scaling_info->src_rect.height == 0)
2429                 return -EINVAL;
2430
2431         scaling_info->dst_rect.x = state->crtc_x;
2432         scaling_info->dst_rect.y = state->crtc_y;
2433
2434         if (state->crtc_w == 0)
2435                 return -EINVAL;
2436
2437         scaling_info->dst_rect.width = state->crtc_w;
2438
2439         if (state->crtc_h == 0)
2440                 return -EINVAL;
2441
2442         scaling_info->dst_rect.height = state->crtc_h;
2443
2444         /* DRM doesn't specify clipping on destination output. */
2445         scaling_info->clip_rect = scaling_info->dst_rect;
2446
2447         /* TODO: Validate scaling per-format with DC plane caps */
2448         scale_w = scaling_info->dst_rect.width * 1000 /
2449                   scaling_info->src_rect.width;
2450
2451         if (scale_w < 250 || scale_w > 16000)
2452                 return -EINVAL;
2453
2454         scale_h = scaling_info->dst_rect.height * 1000 /
2455                   scaling_info->src_rect.height;
2456
2457         if (scale_h < 250 || scale_h > 16000)
2458                 return -EINVAL;
2459
2460         /*
2461          * The "scaling_quality" can be ignored for now, quality = 0 has DC
2462          * assume reasonable defaults based on the format.
2463          */
2464
2465         return 0;
2466 }
2467
2468 static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,
2469                        uint64_t *tiling_flags)
2470 {
2471         struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]);
2472         int r = amdgpu_bo_reserve(rbo, false);
2473
2474         if (unlikely(r)) {
2475                 /* Don't show error message when returning -ERESTARTSYS */
2476                 if (r != -ERESTARTSYS)
2477                         DRM_ERROR("Unable to reserve buffer: %d\n", r);
2478                 return r;
2479         }
2480
2481         if (tiling_flags)
2482                 amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
2483
2484         amdgpu_bo_unreserve(rbo);
2485
2486         return r;
2487 }
2488
2489 static inline uint64_t get_dcc_address(uint64_t address, uint64_t tiling_flags)
2490 {
2491         uint32_t offset = AMDGPU_TILING_GET(tiling_flags, DCC_OFFSET_256B);
2492
2493         return offset ? (address + offset * 256) : 0;
2494 }
2495
2496 static int
2497 fill_plane_dcc_attributes(struct amdgpu_device *adev,
2498                           const struct amdgpu_framebuffer *afb,
2499                           const enum surface_pixel_format format,
2500                           const enum dc_rotation_angle rotation,
2501                           const union plane_size *plane_size,
2502                           const union dc_tiling_info *tiling_info,
2503                           const uint64_t info,
2504                           struct dc_plane_dcc_param *dcc,
2505                           struct dc_plane_address *address)
2506 {
2507         struct dc *dc = adev->dm.dc;
2508         struct dc_dcc_surface_param input;
2509         struct dc_surface_dcc_cap output;
2510         uint32_t offset = AMDGPU_TILING_GET(info, DCC_OFFSET_256B);
2511         uint32_t i64b = AMDGPU_TILING_GET(info, DCC_INDEPENDENT_64B) != 0;
2512         uint64_t dcc_address;
2513
2514         memset(&input, 0, sizeof(input));
2515         memset(&output, 0, sizeof(output));
2516
2517         if (!offset)
2518                 return 0;
2519
2520         if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
2521                 return 0;
2522
2523         if (!dc->cap_funcs.get_dcc_compression_cap)
2524                 return -EINVAL;
2525
2526         input.format = format;
2527         input.surface_size.width = plane_size->grph.surface_size.width;
2528         input.surface_size.height = plane_size->grph.surface_size.height;
2529         input.swizzle_mode = tiling_info->gfx9.swizzle;
2530
2531         if (rotation == ROTATION_ANGLE_0 || rotation == ROTATION_ANGLE_180)
2532                 input.scan = SCAN_DIRECTION_HORIZONTAL;
2533         else if (rotation == ROTATION_ANGLE_90 || rotation == ROTATION_ANGLE_270)
2534                 input.scan = SCAN_DIRECTION_VERTICAL;
2535
2536         if (!dc->cap_funcs.get_dcc_compression_cap(dc, &input, &output))
2537                 return -EINVAL;
2538
2539         if (!output.capable)
2540                 return -EINVAL;
2541
2542         if (i64b == 0 && output.grph.rgb.independent_64b_blks != 0)
2543                 return -EINVAL;
2544
2545         dcc->enable = 1;
2546         dcc->grph.meta_pitch =
2547                 AMDGPU_TILING_GET(info, DCC_PITCH_MAX) + 1;
2548         dcc->grph.independent_64b_blks = i64b;
2549
2550         dcc_address = get_dcc_address(afb->address, info);
2551         address->grph.meta_addr.low_part = lower_32_bits(dcc_address);
2552         address->grph.meta_addr.high_part = upper_32_bits(dcc_address);
2553
2554         return 0;
2555 }
2556
2557 static int
2558 fill_plane_buffer_attributes(struct amdgpu_device *adev,
2559                              const struct amdgpu_framebuffer *afb,
2560                              const enum surface_pixel_format format,
2561                              const enum dc_rotation_angle rotation,
2562                              const uint64_t tiling_flags,
2563                              union dc_tiling_info *tiling_info,
2564                              union plane_size *plane_size,
2565                              struct dc_plane_dcc_param *dcc,
2566                              struct dc_plane_address *address)
2567 {
2568         const struct drm_framebuffer *fb = &afb->base;
2569         int ret;
2570
2571         memset(tiling_info, 0, sizeof(*tiling_info));
2572         memset(plane_size, 0, sizeof(*plane_size));
2573         memset(dcc, 0, sizeof(*dcc));
2574         memset(address, 0, sizeof(*address));
2575
2576         if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
2577                 plane_size->grph.surface_size.x = 0;
2578                 plane_size->grph.surface_size.y = 0;
2579                 plane_size->grph.surface_size.width = fb->width;
2580                 plane_size->grph.surface_size.height = fb->height;
2581                 plane_size->grph.surface_pitch =
2582                         fb->pitches[0] / fb->format->cpp[0];
2583
2584                 address->type = PLN_ADDR_TYPE_GRAPHICS;
2585                 address->grph.addr.low_part = lower_32_bits(afb->address);
2586                 address->grph.addr.high_part = upper_32_bits(afb->address);
2587         } else {
2588                 uint64_t chroma_addr = afb->address + fb->offsets[1];
2589
2590                 plane_size->video.luma_size.x = 0;
2591                 plane_size->video.luma_size.y = 0;
2592                 plane_size->video.luma_size.width = fb->width;
2593                 plane_size->video.luma_size.height = fb->height;
2594                 plane_size->video.luma_pitch =
2595                         fb->pitches[0] / fb->format->cpp[0];
2596
2597                 plane_size->video.chroma_size.x = 0;
2598                 plane_size->video.chroma_size.y = 0;
2599                 /* TODO: set these based on surface format */
2600                 plane_size->video.chroma_size.width = fb->width / 2;
2601                 plane_size->video.chroma_size.height = fb->height / 2;
2602
2603                 plane_size->video.chroma_pitch =
2604                         fb->pitches[1] / fb->format->cpp[1];
2605
2606                 address->type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
2607                 address->video_progressive.luma_addr.low_part =
2608                         lower_32_bits(afb->address);
2609                 address->video_progressive.luma_addr.high_part =
2610                         upper_32_bits(afb->address);
2611                 address->video_progressive.chroma_addr.low_part =
2612                         lower_32_bits(chroma_addr);
2613                 address->video_progressive.chroma_addr.high_part =
2614                         upper_32_bits(chroma_addr);
2615         }
2616
2617         /* Fill GFX8 params */
2618         if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) {
2619                 unsigned int bankw, bankh, mtaspect, tile_split, num_banks;
2620
2621                 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2622                 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2623                 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2624                 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2625                 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2626
2627                 /* XXX fix me for VI */
2628                 tiling_info->gfx8.num_banks = num_banks;
2629                 tiling_info->gfx8.array_mode =
2630                                 DC_ARRAY_2D_TILED_THIN1;
2631                 tiling_info->gfx8.tile_split = tile_split;
2632                 tiling_info->gfx8.bank_width = bankw;
2633                 tiling_info->gfx8.bank_height = bankh;
2634                 tiling_info->gfx8.tile_aspect = mtaspect;
2635                 tiling_info->gfx8.tile_mode =
2636                                 DC_ADDR_SURF_MICRO_TILING_DISPLAY;
2637         } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)
2638                         == DC_ARRAY_1D_TILED_THIN1) {
2639                 tiling_info->gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1;
2640         }
2641
2642         tiling_info->gfx8.pipe_config =
2643                         AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2644
2645         if (adev->asic_type == CHIP_VEGA10 ||
2646             adev->asic_type == CHIP_VEGA12 ||
2647             adev->asic_type == CHIP_VEGA20 ||
2648             adev->asic_type == CHIP_RAVEN) {
2649                 /* Fill GFX9 params */
2650                 tiling_info->gfx9.num_pipes =
2651                         adev->gfx.config.gb_addr_config_fields.num_pipes;
2652                 tiling_info->gfx9.num_banks =
2653                         adev->gfx.config.gb_addr_config_fields.num_banks;
2654                 tiling_info->gfx9.pipe_interleave =
2655                         adev->gfx.config.gb_addr_config_fields.pipe_interleave_size;
2656                 tiling_info->gfx9.num_shader_engines =
2657                         adev->gfx.config.gb_addr_config_fields.num_se;
2658                 tiling_info->gfx9.max_compressed_frags =
2659                         adev->gfx.config.gb_addr_config_fields.max_compress_frags;
2660                 tiling_info->gfx9.num_rb_per_se =
2661                         adev->gfx.config.gb_addr_config_fields.num_rb_per_se;
2662                 tiling_info->gfx9.swizzle =
2663                         AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE);
2664                 tiling_info->gfx9.shaderEnable = 1;
2665
2666                 ret = fill_plane_dcc_attributes(adev, afb, format, rotation,
2667                                                 plane_size, tiling_info,
2668                                                 tiling_flags, dcc, address);
2669                 if (ret)
2670                         return ret;
2671         }
2672
2673         return 0;
2674 }
2675
2676 static void
2677 fill_blending_from_plane_state(const struct drm_plane_state *plane_state,
2678                                bool *per_pixel_alpha, bool *global_alpha,
2679                                int *global_alpha_value)
2680 {
2681         *per_pixel_alpha = false;
2682         *global_alpha = false;
2683         *global_alpha_value = 0xff;
2684
2685         if (plane_state->plane->type != DRM_PLANE_TYPE_OVERLAY)
2686                 return;
2687
2688         if (plane_state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) {
2689                 static const uint32_t alpha_formats[] = {
2690                         DRM_FORMAT_ARGB8888,
2691                         DRM_FORMAT_RGBA8888,
2692                         DRM_FORMAT_ABGR8888,
2693                 };
2694                 uint32_t format = plane_state->fb->format->format;
2695                 unsigned int i;
2696
2697                 for (i = 0; i < ARRAY_SIZE(alpha_formats); ++i) {
2698                         if (format == alpha_formats[i]) {
2699                                 *per_pixel_alpha = true;
2700                                 break;
2701                         }
2702                 }
2703         }
2704
2705         if (plane_state->alpha < 0xffff) {
2706                 *global_alpha = true;
2707                 *global_alpha_value = plane_state->alpha >> 8;
2708         }
2709 }
2710
2711 static int
2712 fill_plane_color_attributes(const struct drm_plane_state *plane_state,
2713                             const enum surface_pixel_format format,
2714                             enum dc_color_space *color_space)
2715 {
2716         bool full_range;
2717
2718         *color_space = COLOR_SPACE_SRGB;
2719
2720         /* DRM color properties only affect non-RGB formats. */
2721         if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
2722                 return 0;
2723
2724         full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE);
2725
2726         switch (plane_state->color_encoding) {
2727         case DRM_COLOR_YCBCR_BT601:
2728                 if (full_range)
2729                         *color_space = COLOR_SPACE_YCBCR601;
2730                 else
2731                         *color_space = COLOR_SPACE_YCBCR601_LIMITED;
2732                 break;
2733
2734         case DRM_COLOR_YCBCR_BT709:
2735                 if (full_range)
2736                         *color_space = COLOR_SPACE_YCBCR709;
2737                 else
2738                         *color_space = COLOR_SPACE_YCBCR709_LIMITED;
2739                 break;
2740
2741         case DRM_COLOR_YCBCR_BT2020:
2742                 if (full_range)
2743                         *color_space = COLOR_SPACE_2020_YCBCR;
2744                 else
2745                         return -EINVAL;
2746                 break;
2747
2748         default:
2749                 return -EINVAL;
2750         }
2751
2752         return 0;
2753 }
2754
2755 static int
2756 fill_dc_plane_info_and_addr(struct amdgpu_device *adev,
2757                             const struct drm_plane_state *plane_state,
2758                             const uint64_t tiling_flags,
2759                             struct dc_plane_info *plane_info,
2760                             struct dc_plane_address *address)
2761 {
2762         const struct drm_framebuffer *fb = plane_state->fb;
2763         const struct amdgpu_framebuffer *afb =
2764                 to_amdgpu_framebuffer(plane_state->fb);
2765         struct drm_format_name_buf format_name;
2766         int ret;
2767
2768         memset(plane_info, 0, sizeof(*plane_info));
2769
2770         switch (fb->format->format) {
2771         case DRM_FORMAT_C8:
2772                 plane_info->format =
2773                         SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
2774                 break;
2775         case DRM_FORMAT_RGB565:
2776                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
2777                 break;
2778         case DRM_FORMAT_XRGB8888:
2779         case DRM_FORMAT_ARGB8888:
2780                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
2781                 break;
2782         case DRM_FORMAT_XRGB2101010:
2783         case DRM_FORMAT_ARGB2101010:
2784                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
2785                 break;
2786         case DRM_FORMAT_XBGR2101010:
2787         case DRM_FORMAT_ABGR2101010:
2788                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
2789                 break;
2790         case DRM_FORMAT_XBGR8888:
2791         case DRM_FORMAT_ABGR8888:
2792                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888;
2793                 break;
2794         case DRM_FORMAT_NV21:
2795                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
2796                 break;
2797         case DRM_FORMAT_NV12:
2798                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
2799                 break;
2800         default:
2801                 DRM_ERROR(
2802                         "Unsupported screen format %s\n",
2803                         drm_get_format_name(fb->format->format, &format_name));
2804                 return -EINVAL;
2805         }
2806
2807         switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
2808         case DRM_MODE_ROTATE_0:
2809                 plane_info->rotation = ROTATION_ANGLE_0;
2810                 break;
2811         case DRM_MODE_ROTATE_90:
2812                 plane_info->rotation = ROTATION_ANGLE_90;
2813                 break;
2814         case DRM_MODE_ROTATE_180:
2815                 plane_info->rotation = ROTATION_ANGLE_180;
2816                 break;
2817         case DRM_MODE_ROTATE_270:
2818                 plane_info->rotation = ROTATION_ANGLE_270;
2819                 break;
2820         default:
2821                 plane_info->rotation = ROTATION_ANGLE_0;
2822                 break;
2823         }
2824
2825         plane_info->visible = true;
2826         plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE;
2827
2828         ret = fill_plane_color_attributes(plane_state, plane_info->format,
2829                                           &plane_info->color_space);
2830         if (ret)
2831                 return ret;
2832
2833         ret = fill_plane_buffer_attributes(adev, afb, plane_info->format,
2834                                            plane_info->rotation, tiling_flags,
2835                                            &plane_info->tiling_info,
2836                                            &plane_info->plane_size,
2837                                            &plane_info->dcc, address);
2838         if (ret)
2839                 return ret;
2840
2841         fill_blending_from_plane_state(
2842                 plane_state, &plane_info->per_pixel_alpha,
2843                 &plane_info->global_alpha, &plane_info->global_alpha_value);
2844
2845         return 0;
2846 }
2847
2848 static int fill_dc_plane_attributes(struct amdgpu_device *adev,
2849                                     struct dc_plane_state *dc_plane_state,
2850                                     struct drm_plane_state *plane_state,
2851                                     struct drm_crtc_state *crtc_state)
2852 {
2853         const struct amdgpu_framebuffer *amdgpu_fb =
2854                 to_amdgpu_framebuffer(plane_state->fb);
2855         struct dc_scaling_info scaling_info;
2856         struct dc_plane_info plane_info;
2857         uint64_t tiling_flags;
2858         int ret;
2859
2860         ret = fill_dc_scaling_info(plane_state, &scaling_info);
2861         if (ret)
2862                 return ret;
2863
2864         dc_plane_state->src_rect = scaling_info.src_rect;
2865         dc_plane_state->dst_rect = scaling_info.dst_rect;
2866         dc_plane_state->clip_rect = scaling_info.clip_rect;
2867         dc_plane_state->scaling_quality = scaling_info.scaling_quality;
2868
2869         ret = get_fb_info(amdgpu_fb, &tiling_flags);
2870         if (ret)
2871                 return ret;
2872
2873         ret = fill_dc_plane_info_and_addr(adev, plane_state, tiling_flags,
2874                                           &plane_info,
2875                                           &dc_plane_state->address);
2876         if (ret)
2877                 return ret;
2878
2879         dc_plane_state->format = plane_info.format;
2880         dc_plane_state->color_space = plane_info.color_space;
2881         dc_plane_state->format = plane_info.format;
2882         dc_plane_state->plane_size = plane_info.plane_size;
2883         dc_plane_state->rotation = plane_info.rotation;
2884         dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror;
2885         dc_plane_state->stereo_format = plane_info.stereo_format;
2886         dc_plane_state->tiling_info = plane_info.tiling_info;
2887         dc_plane_state->visible = plane_info.visible;
2888         dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha;
2889         dc_plane_state->global_alpha = plane_info.global_alpha;
2890         dc_plane_state->global_alpha_value = plane_info.global_alpha_value;
2891         dc_plane_state->dcc = plane_info.dcc;
2892
2893         /*
2894          * Always set input transfer function, since plane state is refreshed
2895          * every time.
2896          */
2897         ret = amdgpu_dm_set_degamma_lut(crtc_state, dc_plane_state);
2898         if (ret) {
2899                 dc_transfer_func_release(dc_plane_state->in_transfer_func);
2900                 dc_plane_state->in_transfer_func = NULL;
2901         }
2902
2903         return ret;
2904 }
2905
2906 static void update_stream_scaling_settings(const struct drm_display_mode *mode,
2907                                            const struct dm_connector_state *dm_state,
2908                                            struct dc_stream_state *stream)
2909 {
2910         enum amdgpu_rmx_type rmx_type;
2911
2912         struct rect src = { 0 }; /* viewport in composition space*/
2913         struct rect dst = { 0 }; /* stream addressable area */
2914
2915         /* no mode. nothing to be done */
2916         if (!mode)
2917                 return;
2918
2919         /* Full screen scaling by default */
2920         src.width = mode->hdisplay;
2921         src.height = mode->vdisplay;
2922         dst.width = stream->timing.h_addressable;
2923         dst.height = stream->timing.v_addressable;
2924
2925         if (dm_state) {
2926                 rmx_type = dm_state->scaling;
2927                 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
2928                         if (src.width * dst.height <
2929                                         src.height * dst.width) {
2930                                 /* height needs less upscaling/more downscaling */
2931                                 dst.width = src.width *
2932                                                 dst.height / src.height;
2933                         } else {
2934                                 /* width needs less upscaling/more downscaling */
2935                                 dst.height = src.height *
2936                                                 dst.width / src.width;
2937                         }
2938                 } else if (rmx_type == RMX_CENTER) {
2939                         dst = src;
2940                 }
2941
2942                 dst.x = (stream->timing.h_addressable - dst.width) / 2;
2943                 dst.y = (stream->timing.v_addressable - dst.height) / 2;
2944
2945                 if (dm_state->underscan_enable) {
2946                         dst.x += dm_state->underscan_hborder / 2;
2947                         dst.y += dm_state->underscan_vborder / 2;
2948                         dst.width -= dm_state->underscan_hborder;
2949                         dst.height -= dm_state->underscan_vborder;
2950                 }
2951         }
2952
2953         stream->src = src;
2954         stream->dst = dst;
2955
2956         DRM_DEBUG_DRIVER("Destination Rectangle x:%d  y:%d  width:%d  height:%d\n",
2957                         dst.x, dst.y, dst.width, dst.height);
2958
2959 }
2960
2961 static enum dc_color_depth
2962 convert_color_depth_from_display_info(const struct drm_connector *connector)
2963 {
2964         struct dm_connector_state *dm_conn_state =
2965                 to_dm_connector_state(connector->state);
2966         uint32_t bpc = connector->display_info.bpc;
2967
2968         /* TODO: Remove this when there's support for max_bpc in drm */
2969         if (dm_conn_state && bpc > dm_conn_state->max_bpc)
2970                 /* Round down to nearest even number. */
2971                 bpc = dm_conn_state->max_bpc - (dm_conn_state->max_bpc & 1);
2972
2973         switch (bpc) {
2974         case 0:
2975                 /*
2976                  * Temporary Work around, DRM doesn't parse color depth for
2977                  * EDID revision before 1.4
2978                  * TODO: Fix edid parsing
2979                  */
2980                 return COLOR_DEPTH_888;
2981         case 6:
2982                 return COLOR_DEPTH_666;
2983         case 8:
2984                 return COLOR_DEPTH_888;
2985         case 10:
2986                 return COLOR_DEPTH_101010;
2987         case 12:
2988                 return COLOR_DEPTH_121212;
2989         case 14:
2990                 return COLOR_DEPTH_141414;
2991         case 16:
2992                 return COLOR_DEPTH_161616;
2993         default:
2994                 return COLOR_DEPTH_UNDEFINED;
2995         }
2996 }
2997
2998 static enum dc_aspect_ratio
2999 get_aspect_ratio(const struct drm_display_mode *mode_in)
3000 {
3001         /* 1-1 mapping, since both enums follow the HDMI spec. */
3002         return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio;
3003 }
3004
3005 static enum dc_color_space
3006 get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
3007 {
3008         enum dc_color_space color_space = COLOR_SPACE_SRGB;
3009
3010         switch (dc_crtc_timing->pixel_encoding) {
3011         case PIXEL_ENCODING_YCBCR422:
3012         case PIXEL_ENCODING_YCBCR444:
3013         case PIXEL_ENCODING_YCBCR420:
3014         {
3015                 /*
3016                  * 27030khz is the separation point between HDTV and SDTV
3017                  * according to HDMI spec, we use YCbCr709 and YCbCr601
3018                  * respectively
3019                  */
3020                 if (dc_crtc_timing->pix_clk_100hz > 270300) {
3021                         if (dc_crtc_timing->flags.Y_ONLY)
3022                                 color_space =
3023                                         COLOR_SPACE_YCBCR709_LIMITED;
3024                         else
3025                                 color_space = COLOR_SPACE_YCBCR709;
3026                 } else {
3027                         if (dc_crtc_timing->flags.Y_ONLY)
3028                                 color_space =
3029                                         COLOR_SPACE_YCBCR601_LIMITED;
3030                         else
3031                                 color_space = COLOR_SPACE_YCBCR601;
3032                 }
3033
3034         }
3035         break;
3036         case PIXEL_ENCODING_RGB:
3037                 color_space = COLOR_SPACE_SRGB;
3038                 break;
3039
3040         default:
3041                 WARN_ON(1);
3042                 break;
3043         }
3044
3045         return color_space;
3046 }
3047
3048 static void reduce_mode_colour_depth(struct dc_crtc_timing *timing_out)
3049 {
3050         if (timing_out->display_color_depth <= COLOR_DEPTH_888)
3051                 return;
3052
3053         timing_out->display_color_depth--;
3054 }
3055
3056 static void adjust_colour_depth_from_display_info(struct dc_crtc_timing *timing_out,
3057                                                 const struct drm_display_info *info)
3058 {
3059         int normalized_clk;
3060         if (timing_out->display_color_depth <= COLOR_DEPTH_888)
3061                 return;
3062         do {
3063                 normalized_clk = timing_out->pix_clk_100hz / 10;
3064                 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */
3065                 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
3066                         normalized_clk /= 2;
3067                 /* Adjusting pix clock following on HDMI spec based on colour depth */
3068                 switch (timing_out->display_color_depth) {
3069                 case COLOR_DEPTH_101010:
3070                         normalized_clk = (normalized_clk * 30) / 24;
3071                         break;
3072                 case COLOR_DEPTH_121212:
3073                         normalized_clk = (normalized_clk * 36) / 24;
3074                         break;
3075                 case COLOR_DEPTH_161616:
3076                         normalized_clk = (normalized_clk * 48) / 24;
3077                         break;
3078                 default:
3079                         return;
3080                 }
3081                 if (normalized_clk <= info->max_tmds_clock)
3082                         return;
3083                 reduce_mode_colour_depth(timing_out);
3084
3085         } while (timing_out->display_color_depth > COLOR_DEPTH_888);
3086
3087 }
3088
3089 static void
3090 fill_stream_properties_from_drm_display_mode(struct dc_stream_state *stream,
3091                                              const struct drm_display_mode *mode_in,
3092                                              const struct drm_connector *connector,
3093                                              const struct dc_stream_state *old_stream)
3094 {
3095         struct dc_crtc_timing *timing_out = &stream->timing;
3096         const struct drm_display_info *info = &connector->display_info;
3097
3098         memset(timing_out, 0, sizeof(struct dc_crtc_timing));
3099
3100         timing_out->h_border_left = 0;
3101         timing_out->h_border_right = 0;
3102         timing_out->v_border_top = 0;
3103         timing_out->v_border_bottom = 0;
3104         /* TODO: un-hardcode */
3105         if (drm_mode_is_420_only(info, mode_in)
3106                         && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
3107                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
3108         else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444)
3109                         && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
3110                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
3111         else
3112                 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
3113
3114         timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
3115         timing_out->display_color_depth = convert_color_depth_from_display_info(
3116                         connector);
3117         timing_out->scan_type = SCANNING_TYPE_NODATA;
3118         timing_out->hdmi_vic = 0;
3119
3120         if(old_stream) {
3121                 timing_out->vic = old_stream->timing.vic;
3122                 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY;
3123                 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY;
3124         } else {
3125                 timing_out->vic = drm_match_cea_mode(mode_in);
3126                 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
3127                         timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
3128                 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
3129                         timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
3130         }
3131
3132         timing_out->h_addressable = mode_in->crtc_hdisplay;
3133         timing_out->h_total = mode_in->crtc_htotal;
3134         timing_out->h_sync_width =
3135                 mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
3136         timing_out->h_front_porch =
3137                 mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
3138         timing_out->v_total = mode_in->crtc_vtotal;
3139         timing_out->v_addressable = mode_in->crtc_vdisplay;
3140         timing_out->v_front_porch =
3141                 mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
3142         timing_out->v_sync_width =
3143                 mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
3144         timing_out->pix_clk_100hz = mode_in->crtc_clock * 10;
3145         timing_out->aspect_ratio = get_aspect_ratio(mode_in);
3146
3147         stream->output_color_space = get_output_color_space(timing_out);
3148
3149         stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
3150         stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
3151         if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
3152                 adjust_colour_depth_from_display_info(timing_out, info);
3153 }
3154
3155 static void fill_audio_info(struct audio_info *audio_info,
3156                             const struct drm_connector *drm_connector,
3157                             const struct dc_sink *dc_sink)
3158 {
3159         int i = 0;
3160         int cea_revision = 0;
3161         const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
3162
3163         audio_info->manufacture_id = edid_caps->manufacturer_id;
3164         audio_info->product_id = edid_caps->product_id;
3165
3166         cea_revision = drm_connector->display_info.cea_rev;
3167
3168         strscpy(audio_info->display_name,
3169                 edid_caps->display_name,
3170                 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
3171
3172         if (cea_revision >= 3) {
3173                 audio_info->mode_count = edid_caps->audio_mode_count;
3174
3175                 for (i = 0; i < audio_info->mode_count; ++i) {
3176                         audio_info->modes[i].format_code =
3177                                         (enum audio_format_code)
3178                                         (edid_caps->audio_modes[i].format_code);
3179                         audio_info->modes[i].channel_count =
3180                                         edid_caps->audio_modes[i].channel_count;
3181                         audio_info->modes[i].sample_rates.all =
3182                                         edid_caps->audio_modes[i].sample_rate;
3183                         audio_info->modes[i].sample_size =
3184                                         edid_caps->audio_modes[i].sample_size;
3185                 }
3186         }
3187
3188         audio_info->flags.all = edid_caps->speaker_flags;
3189
3190         /* TODO: We only check for the progressive mode, check for interlace mode too */
3191         if (drm_connector->latency_present[0]) {
3192                 audio_info->video_latency = drm_connector->video_latency[0];
3193                 audio_info->audio_latency = drm_connector->audio_latency[0];
3194         }
3195
3196         /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
3197
3198 }
3199
3200 static void
3201 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
3202                                       struct drm_display_mode *dst_mode)
3203 {
3204         dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
3205         dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
3206         dst_mode->crtc_clock = src_mode->crtc_clock;
3207         dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
3208         dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
3209         dst_mode->crtc_hsync_start =  src_mode->crtc_hsync_start;
3210         dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
3211         dst_mode->crtc_htotal = src_mode->crtc_htotal;
3212         dst_mode->crtc_hskew = src_mode->crtc_hskew;
3213         dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
3214         dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
3215         dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
3216         dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
3217         dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
3218 }
3219
3220 static void
3221 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
3222                                         const struct drm_display_mode *native_mode,
3223                                         bool scale_enabled)
3224 {
3225         if (scale_enabled) {
3226                 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
3227         } else if (native_mode->clock == drm_mode->clock &&
3228                         native_mode->htotal == drm_mode->htotal &&
3229                         native_mode->vtotal == drm_mode->vtotal) {
3230                 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
3231         } else {
3232                 /* no scaling nor amdgpu inserted, no need to patch */
3233         }
3234 }
3235
3236 static struct dc_sink *
3237 create_fake_sink(struct amdgpu_dm_connector *aconnector)
3238 {
3239         struct dc_sink_init_data sink_init_data = { 0 };
3240         struct dc_sink *sink = NULL;
3241         sink_init_data.link = aconnector->dc_link;
3242         sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
3243
3244         sink = dc_sink_create(&sink_init_data);
3245         if (!sink) {
3246                 DRM_ERROR("Failed to create sink!\n");
3247                 return NULL;
3248         }
3249         sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
3250
3251         return sink;
3252 }
3253
3254 static void set_multisync_trigger_params(
3255                 struct dc_stream_state *stream)
3256 {
3257         if (stream->triggered_crtc_reset.enabled) {
3258                 stream->triggered_crtc_reset.event = CRTC_EVENT_VSYNC_RISING;
3259                 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_LINE;
3260         }
3261 }
3262
3263 static void set_master_stream(struct dc_stream_state *stream_set[],
3264                               int stream_count)
3265 {
3266         int j, highest_rfr = 0, master_stream = 0;
3267
3268         for (j = 0;  j < stream_count; j++) {
3269                 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
3270                         int refresh_rate = 0;
3271
3272                         refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/
3273                                 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
3274                         if (refresh_rate > highest_rfr) {
3275                                 highest_rfr = refresh_rate;
3276                                 master_stream = j;
3277                         }
3278                 }
3279         }
3280         for (j = 0;  j < stream_count; j++) {
3281                 if (stream_set[j])
3282                         stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
3283         }
3284 }
3285
3286 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
3287 {
3288         int i = 0;
3289
3290         if (context->stream_count < 2)
3291                 return;
3292         for (i = 0; i < context->stream_count ; i++) {
3293                 if (!context->streams[i])
3294                         continue;
3295                 /*
3296                  * TODO: add a function to read AMD VSDB bits and set
3297                  * crtc_sync_master.multi_sync_enabled flag
3298                  * For now it's set to false
3299                  */
3300                 set_multisync_trigger_params(context->streams[i]);
3301         }
3302         set_master_stream(context->streams, context->stream_count);
3303 }
3304
3305 static struct dc_stream_state *
3306 create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
3307                        const struct drm_display_mode *drm_mode,
3308                        const struct dm_connector_state *dm_state,
3309                        const struct dc_stream_state *old_stream)
3310 {
3311         struct drm_display_mode *preferred_mode = NULL;
3312         struct drm_connector *drm_connector;
3313         struct dc_stream_state *stream = NULL;
3314         struct drm_display_mode mode = *drm_mode;
3315         bool native_mode_found = false;
3316         bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false;
3317         int mode_refresh;
3318         int preferred_refresh = 0;
3319
3320         struct dc_sink *sink = NULL;
3321         if (aconnector == NULL) {
3322                 DRM_ERROR("aconnector is NULL!\n");
3323                 return stream;
3324         }
3325
3326         drm_connector = &aconnector->base;
3327
3328         if (!aconnector->dc_sink) {
3329                 sink = create_fake_sink(aconnector);
3330                 if (!sink)
3331                         return stream;
3332         } else {
3333                 sink = aconnector->dc_sink;
3334                 dc_sink_retain(sink);
3335         }
3336
3337         stream = dc_create_stream_for_sink(sink);
3338
3339         if (stream == NULL) {
3340                 DRM_ERROR("Failed to create stream for sink!\n");
3341                 goto finish;
3342         }
3343
3344         stream->dm_stream_context = aconnector;
3345
3346         list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
3347                 /* Search for preferred mode */
3348                 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
3349                         native_mode_found = true;
3350                         break;
3351                 }
3352         }
3353         if (!native_mode_found)
3354                 preferred_mode = list_first_entry_or_null(
3355                                 &aconnector->base.modes,
3356                                 struct drm_display_mode,
3357                                 head);
3358
3359         mode_refresh = drm_mode_vrefresh(&mode);
3360
3361         if (preferred_mode == NULL) {
3362                 /*
3363                  * This may not be an error, the use case is when we have no
3364                  * usermode calls to reset and set mode upon hotplug. In this
3365                  * case, we call set mode ourselves to restore the previous mode
3366                  * and the modelist may not be filled in in time.
3367                  */
3368                 DRM_DEBUG_DRIVER("No preferred mode found\n");
3369         } else {
3370                 decide_crtc_timing_for_drm_display_mode(
3371                                 &mode, preferred_mode,
3372                                 dm_state ? (dm_state->scaling != RMX_OFF) : false);
3373                 preferred_refresh = drm_mode_vrefresh(preferred_mode);
3374         }
3375
3376         if (!dm_state)
3377                 drm_mode_set_crtcinfo(&mode, 0);
3378
3379         /*
3380         * If scaling is enabled and refresh rate didn't change
3381         * we copy the vic and polarities of the old timings
3382         */
3383         if (!scale || mode_refresh != preferred_refresh)
3384                 fill_stream_properties_from_drm_display_mode(stream,
3385                         &mode, &aconnector->base, NULL);
3386         else
3387                 fill_stream_properties_from_drm_display_mode(stream,
3388                         &mode, &aconnector->base, old_stream);
3389
3390         update_stream_scaling_settings(&mode, dm_state, stream);
3391
3392         fill_audio_info(
3393                 &stream->audio_info,
3394                 drm_connector,
3395                 sink);
3396
3397         update_stream_signal(stream, sink);
3398
3399 finish:
3400         dc_sink_release(sink);
3401
3402         return stream;
3403 }
3404
3405 static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
3406 {
3407         drm_crtc_cleanup(crtc);
3408         kfree(crtc);
3409 }
3410
3411 static void dm_crtc_destroy_state(struct drm_crtc *crtc,
3412                                   struct drm_crtc_state *state)
3413 {
3414         struct dm_crtc_state *cur = to_dm_crtc_state(state);
3415
3416         /* TODO Destroy dc_stream objects are stream object is flattened */
3417         if (cur->stream)
3418                 dc_stream_release(cur->stream);
3419
3420
3421         __drm_atomic_helper_crtc_destroy_state(state);
3422
3423
3424         kfree(state);
3425 }
3426
3427 static void dm_crtc_reset_state(struct drm_crtc *crtc)
3428 {
3429         struct dm_crtc_state *state;
3430
3431         if (crtc->state)
3432                 dm_crtc_destroy_state(crtc, crtc->state);
3433
3434         state = kzalloc(sizeof(*state), GFP_KERNEL);
3435         if (WARN_ON(!state))
3436                 return;
3437
3438         crtc->state = &state->base;
3439         crtc->state->crtc = crtc;
3440
3441 }
3442
3443 static struct drm_crtc_state *
3444 dm_crtc_duplicate_state(struct drm_crtc *crtc)
3445 {
3446         struct dm_crtc_state *state, *cur;
3447
3448         cur = to_dm_crtc_state(crtc->state);
3449
3450         if (WARN_ON(!crtc->state))
3451                 return NULL;
3452
3453         state = kzalloc(sizeof(*state), GFP_KERNEL);
3454         if (!state)
3455                 return NULL;
3456
3457         __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
3458
3459         if (cur->stream) {
3460                 state->stream = cur->stream;
3461                 dc_stream_retain(state->stream);
3462         }
3463
3464         state->active_planes = cur->active_planes;
3465         state->interrupts_enabled = cur->interrupts_enabled;
3466         state->vrr_params = cur->vrr_params;
3467         state->vrr_infopacket = cur->vrr_infopacket;
3468         state->abm_level = cur->abm_level;
3469         state->vrr_supported = cur->vrr_supported;
3470         state->freesync_config = cur->freesync_config;
3471         state->crc_enabled = cur->crc_enabled;
3472
3473         /* TODO Duplicate dc_stream after objects are stream object is flattened */
3474
3475         return &state->base;
3476 }
3477
3478 static inline int dm_set_vupdate_irq(struct drm_crtc *crtc, bool enable)
3479 {
3480         enum dc_irq_source irq_source;
3481         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3482         struct amdgpu_device *adev = crtc->dev->dev_private;
3483         int rc;
3484
3485         irq_source = IRQ_TYPE_VUPDATE + acrtc->otg_inst;
3486
3487         rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
3488
3489         DRM_DEBUG_DRIVER("crtc %d - vupdate irq %sabling: r=%d\n",
3490                          acrtc->crtc_id, enable ? "en" : "dis", rc);
3491         return rc;
3492 }
3493
3494 static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable)
3495 {
3496         enum dc_irq_source irq_source;
3497         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3498         struct amdgpu_device *adev = crtc->dev->dev_private;
3499         struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
3500         int rc = 0;
3501
3502         if (enable) {
3503                 /* vblank irq on -> Only need vupdate irq in vrr mode */
3504                 if (amdgpu_dm_vrr_active(acrtc_state))
3505                         rc = dm_set_vupdate_irq(crtc, true);
3506         } else {
3507                 /* vblank irq off -> vupdate irq off */
3508                 rc = dm_set_vupdate_irq(crtc, false);
3509         }
3510
3511         if (rc)
3512                 return rc;
3513
3514         irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst;
3515         return dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
3516 }
3517
3518 static int dm_enable_vblank(struct drm_crtc *crtc)
3519 {
3520         return dm_set_vblank(crtc, true);
3521 }
3522
3523 static void dm_disable_vblank(struct drm_crtc *crtc)
3524 {
3525         dm_set_vblank(crtc, false);
3526 }
3527
3528 /* Implemented only the options currently availible for the driver */
3529 static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
3530         .reset = dm_crtc_reset_state,
3531         .destroy = amdgpu_dm_crtc_destroy,
3532         .gamma_set = drm_atomic_helper_legacy_gamma_set,
3533         .set_config = drm_atomic_helper_set_config,
3534         .page_flip = drm_atomic_helper_page_flip,
3535         .atomic_duplicate_state = dm_crtc_duplicate_state,
3536         .atomic_destroy_state = dm_crtc_destroy_state,
3537         .set_crc_source = amdgpu_dm_crtc_set_crc_source,
3538         .verify_crc_source = amdgpu_dm_crtc_verify_crc_source,
3539         .enable_vblank = dm_enable_vblank,
3540         .disable_vblank = dm_disable_vblank,
3541 };
3542
3543 static enum drm_connector_status
3544 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
3545 {
3546         bool connected;
3547         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
3548
3549         /*
3550          * Notes:
3551          * 1. This interface is NOT called in context of HPD irq.
3552          * 2. This interface *is called* in context of user-mode ioctl. Which
3553          * makes it a bad place for *any* MST-related activity.
3554          */
3555
3556         if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
3557             !aconnector->fake_enable)
3558                 connected = (aconnector->dc_sink != NULL);
3559         else
3560                 connected = (aconnector->base.force == DRM_FORCE_ON);
3561
3562         return (connected ? connector_status_connected :
3563                         connector_status_disconnected);
3564 }
3565
3566 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
3567                                             struct drm_connector_state *connector_state,
3568                                             struct drm_property *property,
3569                                             uint64_t val)
3570 {
3571         struct drm_device *dev = connector->dev;
3572         struct amdgpu_device *adev = dev->dev_private;
3573         struct dm_connector_state *dm_old_state =
3574                 to_dm_connector_state(connector->state);
3575         struct dm_connector_state *dm_new_state =
3576                 to_dm_connector_state(connector_state);
3577
3578         int ret = -EINVAL;
3579
3580         if (property == dev->mode_config.scaling_mode_property) {
3581                 enum amdgpu_rmx_type rmx_type;
3582
3583                 switch (val) {
3584                 case DRM_MODE_SCALE_CENTER:
3585                         rmx_type = RMX_CENTER;
3586                         break;
3587                 case DRM_MODE_SCALE_ASPECT:
3588                         rmx_type = RMX_ASPECT;
3589                         break;
3590                 case DRM_MODE_SCALE_FULLSCREEN:
3591                         rmx_type = RMX_FULL;
3592                         break;
3593                 case DRM_MODE_SCALE_NONE:
3594                 default:
3595                         rmx_type = RMX_OFF;
3596                         break;
3597                 }
3598
3599                 if (dm_old_state->scaling == rmx_type)
3600                         return 0;
3601
3602                 dm_new_state->scaling = rmx_type;
3603                 ret = 0;
3604         } else if (property == adev->mode_info.underscan_hborder_property) {
3605                 dm_new_state->underscan_hborder = val;
3606                 ret = 0;
3607         } else if (property == adev->mode_info.underscan_vborder_property) {
3608                 dm_new_state->underscan_vborder = val;
3609                 ret = 0;
3610         } else if (property == adev->mode_info.underscan_property) {
3611                 dm_new_state->underscan_enable = val;
3612                 ret = 0;
3613         } else if (property == adev->mode_info.max_bpc_property) {
3614                 dm_new_state->max_bpc = val;
3615                 ret = 0;
3616         } else if (property == adev->mode_info.abm_level_property) {
3617                 dm_new_state->abm_level = val;
3618                 ret = 0;
3619         }
3620
3621         return ret;
3622 }
3623
3624 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
3625                                             const struct drm_connector_state *state,
3626                                             struct drm_property *property,
3627                                             uint64_t *val)
3628 {
3629         struct drm_device *dev = connector->dev;
3630         struct amdgpu_device *adev = dev->dev_private;
3631         struct dm_connector_state *dm_state =
3632                 to_dm_connector_state(state);
3633         int ret = -EINVAL;
3634
3635         if (property == dev->mode_config.scaling_mode_property) {
3636                 switch (dm_state->scaling) {
3637                 case RMX_CENTER:
3638                         *val = DRM_MODE_SCALE_CENTER;
3639                         break;
3640                 case RMX_ASPECT:
3641                         *val = DRM_MODE_SCALE_ASPECT;
3642                         break;
3643                 case RMX_FULL:
3644                         *val = DRM_MODE_SCALE_FULLSCREEN;
3645                         break;
3646                 case RMX_OFF:
3647                 default:
3648                         *val = DRM_MODE_SCALE_NONE;
3649                         break;
3650                 }
3651                 ret = 0;
3652         } else if (property == adev->mode_info.underscan_hborder_property) {
3653                 *val = dm_state->underscan_hborder;
3654                 ret = 0;
3655         } else if (property == adev->mode_info.underscan_vborder_property) {
3656                 *val = dm_state->underscan_vborder;
3657                 ret = 0;
3658         } else if (property == adev->mode_info.underscan_property) {
3659                 *val = dm_state->underscan_enable;
3660                 ret = 0;
3661         } else if (property == adev->mode_info.max_bpc_property) {
3662                 *val = dm_state->max_bpc;
3663                 ret = 0;
3664         } else if (property == adev->mode_info.abm_level_property) {
3665                 *val = dm_state->abm_level;
3666                 ret = 0;
3667         }
3668
3669         return ret;
3670 }
3671
3672 static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
3673 {
3674         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
3675         const struct dc_link *link = aconnector->dc_link;
3676         struct amdgpu_device *adev = connector->dev->dev_private;
3677         struct amdgpu_display_manager *dm = &adev->dm;
3678
3679 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
3680         defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
3681
3682         if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
3683             link->type != dc_connection_none &&
3684             dm->backlight_dev) {
3685                 backlight_device_unregister(dm->backlight_dev);
3686                 dm->backlight_dev = NULL;
3687         }
3688 #endif
3689
3690         if (aconnector->dc_em_sink)
3691                 dc_sink_release(aconnector->dc_em_sink);
3692         aconnector->dc_em_sink = NULL;
3693         if (aconnector->dc_sink)
3694                 dc_sink_release(aconnector->dc_sink);
3695         aconnector->dc_sink = NULL;
3696
3697         drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux);
3698         drm_connector_unregister(connector);
3699         drm_connector_cleanup(connector);
3700         kfree(connector);
3701 }
3702
3703 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
3704 {
3705         struct dm_connector_state *state =
3706                 to_dm_connector_state(connector->state);
3707
3708         if (connector->state)
3709                 __drm_atomic_helper_connector_destroy_state(connector->state);
3710
3711         kfree(state);
3712
3713         state = kzalloc(sizeof(*state), GFP_KERNEL);
3714
3715         if (state) {
3716                 state->scaling = RMX_OFF;
3717                 state->underscan_enable = false;
3718                 state->underscan_hborder = 0;
3719                 state->underscan_vborder = 0;
3720                 state->max_bpc = 8;
3721
3722                 __drm_atomic_helper_connector_reset(connector, &state->base);
3723         }
3724 }
3725
3726 struct drm_connector_state *
3727 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
3728 {
3729         struct dm_connector_state *state =
3730                 to_dm_connector_state(connector->state);
3731
3732         struct dm_connector_state *new_state =
3733                         kmemdup(state, sizeof(*state), GFP_KERNEL);
3734
3735         if (!new_state)
3736                 return NULL;
3737
3738         __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
3739
3740         new_state->freesync_capable = state->freesync_capable;
3741         new_state->abm_level = state->abm_level;
3742         new_state->scaling = state->scaling;
3743         new_state->underscan_enable = state->underscan_enable;
3744         new_state->underscan_hborder = state->underscan_hborder;
3745         new_state->underscan_vborder = state->underscan_vborder;
3746         new_state->max_bpc = state->max_bpc;
3747
3748         return &new_state->base;
3749 }
3750
3751 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
3752         .reset = amdgpu_dm_connector_funcs_reset,
3753         .detect = amdgpu_dm_connector_detect,
3754         .fill_modes = drm_helper_probe_single_connector_modes,
3755         .destroy = amdgpu_dm_connector_destroy,
3756         .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
3757         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
3758         .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
3759         .atomic_get_property = amdgpu_dm_connector_atomic_get_property
3760 };
3761
3762 static int get_modes(struct drm_connector *connector)
3763 {
3764         return amdgpu_dm_connector_get_modes(connector);
3765 }
3766
3767 static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
3768 {
3769         struct dc_sink_init_data init_params = {
3770                         .link = aconnector->dc_link,
3771                         .sink_signal = SIGNAL_TYPE_VIRTUAL
3772         };
3773         struct edid *edid;
3774
3775         if (!aconnector->base.edid_blob_ptr) {
3776                 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
3777                                 aconnector->base.name);
3778
3779                 aconnector->base.force = DRM_FORCE_OFF;
3780                 aconnector->base.override_edid = false;
3781                 return;
3782         }
3783
3784         edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
3785
3786         aconnector->edid = edid;
3787
3788         aconnector->dc_em_sink = dc_link_add_remote_sink(
3789                 aconnector->dc_link,
3790                 (uint8_t *)edid,
3791                 (edid->extensions + 1) * EDID_LENGTH,
3792                 &init_params);
3793
3794         if (aconnector->base.force == DRM_FORCE_ON) {
3795                 aconnector->dc_sink = aconnector->dc_link->local_sink ?
3796                 aconnector->dc_link->local_sink :
3797                 aconnector->dc_em_sink;
3798                 dc_sink_retain(aconnector->dc_sink);
3799         }
3800 }
3801
3802 static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
3803 {
3804         struct dc_link *link = (struct dc_link *)aconnector->dc_link;
3805
3806         /*
3807          * In case of headless boot with force on for DP managed connector
3808          * Those settings have to be != 0 to get initial modeset
3809          */
3810         if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
3811                 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
3812                 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
3813         }
3814
3815
3816         aconnector->base.override_edid = true;
3817         create_eml_sink(aconnector);
3818 }
3819
3820 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
3821                                    struct drm_display_mode *mode)
3822 {
3823         int result = MODE_ERROR;
3824         struct dc_sink *dc_sink;
3825         struct amdgpu_device *adev = connector->dev->dev_private;
3826         /* TODO: Unhardcode stream count */
3827         struct dc_stream_state *stream;
3828         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
3829         enum dc_status dc_result = DC_OK;
3830
3831         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
3832                         (mode->flags & DRM_MODE_FLAG_DBLSCAN))
3833                 return result;
3834
3835         /*
3836          * Only run this the first time mode_valid is called to initilialize
3837          * EDID mgmt
3838          */
3839         if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
3840                 !aconnector->dc_em_sink)
3841                 handle_edid_mgmt(aconnector);
3842
3843         dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
3844
3845         if (dc_sink == NULL) {
3846                 DRM_ERROR("dc_sink is NULL!\n");
3847                 goto fail;
3848         }
3849
3850         stream = create_stream_for_sink(aconnector, mode, NULL, NULL);
3851         if (stream == NULL) {
3852                 DRM_ERROR("Failed to create stream for sink!\n");
3853                 goto fail;
3854         }
3855
3856         dc_result = dc_validate_stream(adev->dm.dc, stream);
3857
3858         if (dc_result == DC_OK)
3859                 result = MODE_OK;
3860         else
3861                 DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d\n",
3862                               mode->vdisplay,
3863                               mode->hdisplay,
3864                               mode->clock,
3865                               dc_result);
3866
3867         dc_stream_release(stream);
3868
3869 fail:
3870         /* TODO: error handling*/
3871         return result;
3872 }
3873
3874 static const struct drm_connector_helper_funcs
3875 amdgpu_dm_connector_helper_funcs = {
3876         /*
3877          * If hotplugging a second bigger display in FB Con mode, bigger resolution
3878          * modes will be filtered by drm_mode_validate_size(), and those modes
3879          * are missing after user start lightdm. So we need to renew modes list.
3880          * in get_modes call back, not just return the modes count
3881          */
3882         .get_modes = get_modes,
3883         .mode_valid = amdgpu_dm_connector_mode_valid,
3884 };
3885
3886 static void dm_crtc_helper_disable(struct drm_crtc *crtc)
3887 {
3888 }
3889
3890 static bool does_crtc_have_active_cursor(struct drm_crtc_state *new_crtc_state)
3891 {
3892         struct drm_device *dev = new_crtc_state->crtc->dev;
3893         struct drm_plane *plane;
3894
3895         drm_for_each_plane_mask(plane, dev, new_crtc_state->plane_mask) {
3896                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
3897                         return true;
3898         }
3899
3900         return false;
3901 }
3902
3903 static int count_crtc_active_planes(struct drm_crtc_state *new_crtc_state)
3904 {
3905         struct drm_atomic_state *state = new_crtc_state->state;
3906         struct drm_plane *plane;
3907         int num_active = 0;
3908
3909         drm_for_each_plane_mask(plane, state->dev, new_crtc_state->plane_mask) {
3910                 struct drm_plane_state *new_plane_state;
3911
3912                 /* Cursor planes are "fake". */
3913                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
3914                         continue;
3915
3916                 new_plane_state = drm_atomic_get_new_plane_state(state, plane);
3917
3918                 if (!new_plane_state) {
3919                         /*
3920                          * The plane is enable on the CRTC and hasn't changed
3921                          * state. This means that it previously passed
3922                          * validation and is therefore enabled.
3923                          */
3924                         num_active += 1;
3925                         continue;
3926                 }
3927
3928                 /* We need a framebuffer to be considered enabled. */
3929                 num_active += (new_plane_state->fb != NULL);
3930         }
3931
3932         return num_active;
3933 }
3934
3935 /*
3936  * Sets whether interrupts should be enabled on a specific CRTC.
3937  * We require that the stream be enabled and that there exist active
3938  * DC planes on the stream.
3939  */
3940 static void
3941 dm_update_crtc_interrupt_state(struct drm_crtc *crtc,
3942                                struct drm_crtc_state *new_crtc_state)
3943 {
3944         struct dm_crtc_state *dm_new_crtc_state =
3945                 to_dm_crtc_state(new_crtc_state);
3946
3947         dm_new_crtc_state->active_planes = 0;
3948         dm_new_crtc_state->interrupts_enabled = false;
3949
3950         if (!dm_new_crtc_state->stream)
3951                 return;
3952
3953         dm_new_crtc_state->active_planes =
3954                 count_crtc_active_planes(new_crtc_state);
3955
3956         dm_new_crtc_state->interrupts_enabled =
3957                 dm_new_crtc_state->active_planes > 0;
3958 }
3959
3960 static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc,
3961                                        struct drm_crtc_state *state)
3962 {
3963         struct amdgpu_device *adev = crtc->dev->dev_private;
3964         struct dc *dc = adev->dm.dc;
3965         struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(state);
3966         int ret = -EINVAL;
3967
3968         /*
3969          * Update interrupt state for the CRTC. This needs to happen whenever
3970          * the CRTC has changed or whenever any of its planes have changed.
3971          * Atomic check satisfies both of these requirements since the CRTC
3972          * is added to the state by DRM during drm_atomic_helper_check_planes.
3973          */
3974         dm_update_crtc_interrupt_state(crtc, state);
3975
3976         if (unlikely(!dm_crtc_state->stream &&
3977                      modeset_required(state, NULL, dm_crtc_state->stream))) {
3978                 WARN_ON(1);
3979                 return ret;
3980         }
3981
3982         /* In some use cases, like reset, no stream is attached */
3983         if (!dm_crtc_state->stream)
3984                 return 0;
3985
3986         /*
3987          * We want at least one hardware plane enabled to use
3988          * the stream with a cursor enabled.
3989          */
3990         if (state->enable && state->active &&
3991             does_crtc_have_active_cursor(state) &&
3992             dm_crtc_state->active_planes == 0)
3993                 return -EINVAL;
3994
3995         if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK)
3996                 return 0;
3997
3998         return ret;
3999 }
4000
4001 static bool dm_crtc_helper_mode_fixup(struct drm_crtc *crtc,
4002                                       const struct drm_display_mode *mode,
4003                                       struct drm_display_mode *adjusted_mode)
4004 {
4005         return true;
4006 }
4007
4008 static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = {
4009         .disable = dm_crtc_helper_disable,
4010         .atomic_check = dm_crtc_helper_atomic_check,
4011         .mode_fixup = dm_crtc_helper_mode_fixup
4012 };
4013
4014 static void dm_encoder_helper_disable(struct drm_encoder *encoder)
4015 {
4016
4017 }
4018
4019 static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
4020                                           struct drm_crtc_state *crtc_state,
4021                                           struct drm_connector_state *conn_state)
4022 {
4023         return 0;
4024 }
4025
4026 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
4027         .disable = dm_encoder_helper_disable,
4028         .atomic_check = dm_encoder_helper_atomic_check
4029 };
4030
4031 static void dm_drm_plane_reset(struct drm_plane *plane)
4032 {
4033         struct dm_plane_state *amdgpu_state = NULL;
4034
4035         if (plane->state)
4036                 plane->funcs->atomic_destroy_state(plane, plane->state);
4037
4038         amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL);
4039         WARN_ON(amdgpu_state == NULL);
4040
4041         if (amdgpu_state)
4042                 __drm_atomic_helper_plane_reset(plane, &amdgpu_state->base);
4043 }
4044
4045 static struct drm_plane_state *
4046 dm_drm_plane_duplicate_state(struct drm_plane *plane)
4047 {
4048         struct dm_plane_state *dm_plane_state, *old_dm_plane_state;
4049
4050         old_dm_plane_state = to_dm_plane_state(plane->state);
4051         dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL);
4052         if (!dm_plane_state)
4053                 return NULL;
4054
4055         __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base);
4056
4057         if (old_dm_plane_state->dc_state) {
4058                 dm_plane_state->dc_state = old_dm_plane_state->dc_state;
4059                 dc_plane_state_retain(dm_plane_state->dc_state);
4060         }
4061
4062         return &dm_plane_state->base;
4063 }
4064
4065 void dm_drm_plane_destroy_state(struct drm_plane *plane,
4066                                 struct drm_plane_state *state)
4067 {
4068         struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
4069
4070         if (dm_plane_state->dc_state)
4071                 dc_plane_state_release(dm_plane_state->dc_state);
4072
4073         drm_atomic_helper_plane_destroy_state(plane, state);
4074 }
4075
4076 static const struct drm_plane_funcs dm_plane_funcs = {
4077         .update_plane   = drm_atomic_helper_update_plane,
4078         .disable_plane  = drm_atomic_helper_disable_plane,
4079         .destroy        = drm_primary_helper_destroy,
4080         .reset = dm_drm_plane_reset,
4081         .atomic_duplicate_state = dm_drm_plane_duplicate_state,
4082         .atomic_destroy_state = dm_drm_plane_destroy_state,
4083 };
4084
4085 static int dm_plane_helper_prepare_fb(struct drm_plane *plane,
4086                                       struct drm_plane_state *new_state)
4087 {
4088         struct amdgpu_framebuffer *afb;
4089         struct drm_gem_object *obj;
4090         struct amdgpu_device *adev;
4091         struct amdgpu_bo *rbo;
4092         struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old;
4093         uint64_t tiling_flags;
4094         uint32_t domain;
4095         int r;
4096
4097         dm_plane_state_old = to_dm_plane_state(plane->state);
4098         dm_plane_state_new = to_dm_plane_state(new_state);
4099
4100         if (!new_state->fb) {
4101                 DRM_DEBUG_DRIVER("No FB bound\n");
4102                 return 0;
4103         }
4104
4105         afb = to_amdgpu_framebuffer(new_state->fb);
4106         obj = new_state->fb->obj[0];
4107         rbo = gem_to_amdgpu_bo(obj);
4108         adev = amdgpu_ttm_adev(rbo->tbo.bdev);
4109         r = amdgpu_bo_reserve(rbo, false);
4110         if (unlikely(r != 0))
4111                 return r;
4112
4113         if (plane->type != DRM_PLANE_TYPE_CURSOR)
4114                 domain = amdgpu_display_supported_domains(adev);
4115         else
4116                 domain = AMDGPU_GEM_DOMAIN_VRAM;
4117
4118         r = amdgpu_bo_pin(rbo, domain);
4119         if (unlikely(r != 0)) {
4120                 if (r != -ERESTARTSYS)
4121                         DRM_ERROR("Failed to pin framebuffer with error %d\n", r);
4122                 amdgpu_bo_unreserve(rbo);
4123                 return r;
4124         }
4125
4126         r = amdgpu_ttm_alloc_gart(&rbo->tbo);
4127         if (unlikely(r != 0)) {
4128                 amdgpu_bo_unpin(rbo);
4129                 amdgpu_bo_unreserve(rbo);
4130                 DRM_ERROR("%p bind failed\n", rbo);
4131                 return r;
4132         }
4133
4134         amdgpu_bo_get_tiling_flags(rbo, &tiling_flags);
4135
4136         amdgpu_bo_unreserve(rbo);
4137
4138         afb->address = amdgpu_bo_gpu_offset(rbo);
4139
4140         amdgpu_bo_ref(rbo);
4141
4142         if (dm_plane_state_new->dc_state &&
4143                         dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) {
4144                 struct dc_plane_state *plane_state = dm_plane_state_new->dc_state;
4145
4146                 fill_plane_buffer_attributes(
4147                         adev, afb, plane_state->format, plane_state->rotation,
4148                         tiling_flags, &plane_state->tiling_info,
4149                         &plane_state->plane_size, &plane_state->dcc,
4150                         &plane_state->address);
4151         }
4152
4153         return 0;
4154 }
4155
4156 static void dm_plane_helper_cleanup_fb(struct drm_plane *plane,
4157                                        struct drm_plane_state *old_state)
4158 {
4159         struct amdgpu_bo *rbo;
4160         int r;
4161
4162         if (!old_state->fb)
4163                 return;
4164
4165         rbo = gem_to_amdgpu_bo(old_state->fb->obj[0]);
4166         r = amdgpu_bo_reserve(rbo, false);
4167         if (unlikely(r)) {
4168                 DRM_ERROR("failed to reserve rbo before unpin\n");
4169                 return;
4170         }
4171
4172         amdgpu_bo_unpin(rbo);
4173         amdgpu_bo_unreserve(rbo);
4174         amdgpu_bo_unref(&rbo);
4175 }
4176
4177 static int dm_plane_atomic_check(struct drm_plane *plane,
4178                                  struct drm_plane_state *state)
4179 {
4180         struct amdgpu_device *adev = plane->dev->dev_private;
4181         struct dc *dc = adev->dm.dc;
4182         struct dm_plane_state *dm_plane_state;
4183         struct dc_scaling_info scaling_info;
4184         int ret;
4185
4186         dm_plane_state = to_dm_plane_state(state);
4187
4188         if (!dm_plane_state->dc_state)
4189                 return 0;
4190
4191         ret = fill_dc_scaling_info(state, &scaling_info);
4192         if (ret)
4193                 return ret;
4194
4195         if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK)
4196                 return 0;
4197
4198         return -EINVAL;
4199 }
4200
4201 static int dm_plane_atomic_async_check(struct drm_plane *plane,
4202                                        struct drm_plane_state *new_plane_state)
4203 {
4204         struct drm_plane_state *old_plane_state =
4205                 drm_atomic_get_old_plane_state(new_plane_state->state, plane);
4206
4207         /* Only support async updates on cursor planes. */
4208         if (plane->type != DRM_PLANE_TYPE_CURSOR)
4209                 return -EINVAL;
4210
4211         /*
4212          * DRM calls prepare_fb and cleanup_fb on new_plane_state for
4213          * async commits so don't allow fb changes.
4214          */
4215         if (old_plane_state->fb != new_plane_state->fb)
4216                 return -EINVAL;
4217
4218         return 0;
4219 }
4220
4221 static void dm_plane_atomic_async_update(struct drm_plane *plane,
4222                                          struct drm_plane_state *new_state)
4223 {
4224         struct drm_plane_state *old_state =
4225                 drm_atomic_get_old_plane_state(new_state->state, plane);
4226
4227         if (plane->state->fb != new_state->fb)
4228                 drm_atomic_set_fb_for_plane(plane->state, new_state->fb);
4229
4230         plane->state->src_x = new_state->src_x;
4231         plane->state->src_y = new_state->src_y;
4232         plane->state->src_w = new_state->src_w;
4233         plane->state->src_h = new_state->src_h;
4234         plane->state->crtc_x = new_state->crtc_x;
4235         plane->state->crtc_y = new_state->crtc_y;
4236         plane->state->crtc_w = new_state->crtc_w;
4237         plane->state->crtc_h = new_state->crtc_h;
4238
4239         handle_cursor_update(plane, old_state);
4240 }
4241
4242 static const struct drm_plane_helper_funcs dm_plane_helper_funcs = {
4243         .prepare_fb = dm_plane_helper_prepare_fb,
4244         .cleanup_fb = dm_plane_helper_cleanup_fb,
4245         .atomic_check = dm_plane_atomic_check,
4246         .atomic_async_check = dm_plane_atomic_async_check,
4247         .atomic_async_update = dm_plane_atomic_async_update
4248 };
4249
4250 /*
4251  * TODO: these are currently initialized to rgb formats only.
4252  * For future use cases we should either initialize them dynamically based on
4253  * plane capabilities, or initialize this array to all formats, so internal drm
4254  * check will succeed, and let DC implement proper check
4255  */
4256 static const uint32_t rgb_formats[] = {
4257         DRM_FORMAT_XRGB8888,
4258         DRM_FORMAT_ARGB8888,
4259         DRM_FORMAT_RGBA8888,
4260         DRM_FORMAT_XRGB2101010,
4261         DRM_FORMAT_XBGR2101010,
4262         DRM_FORMAT_ARGB2101010,
4263         DRM_FORMAT_ABGR2101010,
4264         DRM_FORMAT_XBGR8888,
4265         DRM_FORMAT_ABGR8888,
4266         DRM_FORMAT_RGB565,
4267 };
4268
4269 static const uint32_t overlay_formats[] = {
4270         DRM_FORMAT_XRGB8888,
4271         DRM_FORMAT_ARGB8888,
4272         DRM_FORMAT_RGBA8888,
4273         DRM_FORMAT_XBGR8888,
4274         DRM_FORMAT_ABGR8888,
4275         DRM_FORMAT_RGB565
4276 };
4277
4278 static const u32 cursor_formats[] = {
4279         DRM_FORMAT_ARGB8888
4280 };
4281
4282 static int get_plane_formats(const struct drm_plane *plane,
4283                              const struct dc_plane_cap *plane_cap,
4284                              uint32_t *formats, int max_formats)
4285 {
4286         int i, num_formats = 0;
4287
4288         /*
4289          * TODO: Query support for each group of formats directly from
4290          * DC plane caps. This will require adding more formats to the
4291          * caps list.
4292          */
4293
4294         switch (plane->type) {
4295         case DRM_PLANE_TYPE_PRIMARY:
4296                 for (i = 0; i < ARRAY_SIZE(rgb_formats); ++i) {
4297                         if (num_formats >= max_formats)
4298                                 break;
4299
4300                         formats[num_formats++] = rgb_formats[i];
4301                 }
4302
4303                 if (plane_cap && plane_cap->pixel_format_support.nv12)
4304                         formats[num_formats++] = DRM_FORMAT_NV12;
4305                 break;
4306
4307         case DRM_PLANE_TYPE_OVERLAY:
4308                 for (i = 0; i < ARRAY_SIZE(overlay_formats); ++i) {
4309                         if (num_formats >= max_formats)
4310                                 break;
4311
4312                         formats[num_formats++] = overlay_formats[i];
4313                 }
4314                 break;
4315
4316         case DRM_PLANE_TYPE_CURSOR:
4317                 for (i = 0; i < ARRAY_SIZE(cursor_formats); ++i) {
4318                         if (num_formats >= max_formats)
4319                                 break;
4320
4321                         formats[num_formats++] = cursor_formats[i];
4322                 }
4323                 break;
4324         }
4325
4326         return num_formats;
4327 }
4328
4329 static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
4330                                 struct drm_plane *plane,
4331                                 unsigned long possible_crtcs,
4332                                 const struct dc_plane_cap *plane_cap)
4333 {
4334         uint32_t formats[32];
4335         int num_formats;
4336         int res = -EPERM;
4337
4338         num_formats = get_plane_formats(plane, plane_cap, formats,
4339                                         ARRAY_SIZE(formats));
4340
4341         res = drm_universal_plane_init(dm->adev->ddev, plane, possible_crtcs,
4342                                        &dm_plane_funcs, formats, num_formats,
4343                                        NULL, plane->type, NULL);
4344         if (res)
4345                 return res;
4346
4347         if (plane->type == DRM_PLANE_TYPE_OVERLAY &&
4348             plane_cap && plane_cap->per_pixel_alpha) {
4349                 unsigned int blend_caps = BIT(DRM_MODE_BLEND_PIXEL_NONE) |
4350                                           BIT(DRM_MODE_BLEND_PREMULTI);
4351
4352                 drm_plane_create_alpha_property(plane);
4353                 drm_plane_create_blend_mode_property(plane, blend_caps);
4354         }
4355
4356         if (plane->type == DRM_PLANE_TYPE_PRIMARY &&
4357             plane_cap && plane_cap->pixel_format_support.nv12) {
4358                 /* This only affects YUV formats. */
4359                 drm_plane_create_color_properties(
4360                         plane,
4361                         BIT(DRM_COLOR_YCBCR_BT601) |
4362                         BIT(DRM_COLOR_YCBCR_BT709),
4363                         BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
4364                         BIT(DRM_COLOR_YCBCR_FULL_RANGE),
4365                         DRM_COLOR_YCBCR_BT709, DRM_COLOR_YCBCR_LIMITED_RANGE);
4366         }
4367
4368         drm_plane_helper_add(plane, &dm_plane_helper_funcs);
4369
4370         /* Create (reset) the plane state */
4371         if (plane->funcs->reset)
4372                 plane->funcs->reset(plane);
4373
4374         return 0;
4375 }
4376
4377 static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
4378                                struct drm_plane *plane,
4379                                uint32_t crtc_index)
4380 {
4381         struct amdgpu_crtc *acrtc = NULL;
4382         struct drm_plane *cursor_plane;
4383
4384         int res = -ENOMEM;
4385
4386         cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL);
4387         if (!cursor_plane)
4388                 goto fail;
4389
4390         cursor_plane->type = DRM_PLANE_TYPE_CURSOR;
4391         res = amdgpu_dm_plane_init(dm, cursor_plane, 0, NULL);
4392
4393         acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
4394         if (!acrtc)
4395                 goto fail;
4396
4397         res = drm_crtc_init_with_planes(
4398                         dm->ddev,
4399                         &acrtc->base,
4400                         plane,
4401                         cursor_plane,
4402                         &amdgpu_dm_crtc_funcs, NULL);
4403
4404         if (res)
4405                 goto fail;
4406
4407         drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs);
4408
4409         /* Create (reset) the plane state */
4410         if (acrtc->base.funcs->reset)
4411                 acrtc->base.funcs->reset(&acrtc->base);
4412
4413         acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;
4414         acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;
4415
4416         acrtc->crtc_id = crtc_index;
4417         acrtc->base.enabled = false;
4418         acrtc->otg_inst = -1;
4419
4420         dm->adev->mode_info.crtcs[crtc_index] = acrtc;
4421         drm_crtc_enable_color_mgmt(&acrtc->base, MAX_COLOR_LUT_ENTRIES,
4422                                    true, MAX_COLOR_LUT_ENTRIES);
4423         drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES);
4424
4425         return 0;
4426
4427 fail:
4428         kfree(acrtc);
4429         kfree(cursor_plane);
4430         return res;
4431 }
4432
4433
4434 static int to_drm_connector_type(enum signal_type st)
4435 {
4436         switch (st) {
4437         case SIGNAL_TYPE_HDMI_TYPE_A:
4438                 return DRM_MODE_CONNECTOR_HDMIA;
4439         case SIGNAL_TYPE_EDP:
4440                 return DRM_MODE_CONNECTOR_eDP;
4441         case SIGNAL_TYPE_LVDS:
4442                 return DRM_MODE_CONNECTOR_LVDS;
4443         case SIGNAL_TYPE_RGB:
4444                 return DRM_MODE_CONNECTOR_VGA;
4445         case SIGNAL_TYPE_DISPLAY_PORT:
4446         case SIGNAL_TYPE_DISPLAY_PORT_MST:
4447                 return DRM_MODE_CONNECTOR_DisplayPort;
4448         case SIGNAL_TYPE_DVI_DUAL_LINK:
4449         case SIGNAL_TYPE_DVI_SINGLE_LINK:
4450                 return DRM_MODE_CONNECTOR_DVID;
4451         case SIGNAL_TYPE_VIRTUAL:
4452                 return DRM_MODE_CONNECTOR_VIRTUAL;
4453
4454         default:
4455                 return DRM_MODE_CONNECTOR_Unknown;
4456         }
4457 }
4458
4459 static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector)
4460 {
4461         return drm_encoder_find(connector->dev, NULL, connector->encoder_ids[0]);
4462 }
4463
4464 static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
4465 {
4466         struct drm_encoder *encoder;
4467         struct amdgpu_encoder *amdgpu_encoder;
4468
4469         encoder = amdgpu_dm_connector_to_encoder(connector);
4470
4471         if (encoder == NULL)
4472                 return;
4473
4474         amdgpu_encoder = to_amdgpu_encoder(encoder);
4475
4476         amdgpu_encoder->native_mode.clock = 0;
4477
4478         if (!list_empty(&connector->probed_modes)) {
4479                 struct drm_display_mode *preferred_mode = NULL;
4480
4481                 list_for_each_entry(preferred_mode,
4482                                     &connector->probed_modes,
4483                                     head) {
4484                         if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
4485                                 amdgpu_encoder->native_mode = *preferred_mode;
4486
4487                         break;
4488                 }
4489
4490         }
4491 }
4492
4493 static struct drm_display_mode *
4494 amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
4495                              char *name,
4496                              int hdisplay, int vdisplay)
4497 {
4498         struct drm_device *dev = encoder->dev;
4499         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
4500         struct drm_display_mode *mode = NULL;
4501         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
4502
4503         mode = drm_mode_duplicate(dev, native_mode);
4504
4505         if (mode == NULL)
4506                 return NULL;
4507
4508         mode->hdisplay = hdisplay;
4509         mode->vdisplay = vdisplay;
4510         mode->type &= ~DRM_MODE_TYPE_PREFERRED;
4511         strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
4512
4513         return mode;
4514
4515 }
4516
4517 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
4518                                                  struct drm_connector *connector)
4519 {
4520         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
4521         struct drm_display_mode *mode = NULL;
4522         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
4523         struct amdgpu_dm_connector *amdgpu_dm_connector =
4524                                 to_amdgpu_dm_connector(connector);
4525         int i;
4526         int n;
4527         struct mode_size {
4528                 char name[DRM_DISPLAY_MODE_LEN];
4529                 int w;
4530                 int h;
4531         } common_modes[] = {
4532                 {  "640x480",  640,  480},
4533                 {  "800x600",  800,  600},
4534                 { "1024x768", 1024,  768},
4535                 { "1280x720", 1280,  720},
4536                 { "1280x800", 1280,  800},
4537                 {"1280x1024", 1280, 1024},
4538                 { "1440x900", 1440,  900},
4539                 {"1680x1050", 1680, 1050},
4540                 {"1600x1200", 1600, 1200},
4541                 {"1920x1080", 1920, 1080},
4542                 {"1920x1200", 1920, 1200}
4543         };
4544
4545         n = ARRAY_SIZE(common_modes);
4546
4547         for (i = 0; i < n; i++) {
4548                 struct drm_display_mode *curmode = NULL;
4549                 bool mode_existed = false;
4550
4551                 if (common_modes[i].w > native_mode->hdisplay ||
4552                     common_modes[i].h > native_mode->vdisplay ||
4553                    (common_modes[i].w == native_mode->hdisplay &&
4554                     common_modes[i].h == native_mode->vdisplay))
4555                         continue;
4556
4557                 list_for_each_entry(curmode, &connector->probed_modes, head) {
4558                         if (common_modes[i].w == curmode->hdisplay &&
4559                             common_modes[i].h == curmode->vdisplay) {
4560                                 mode_existed = true;
4561                                 break;
4562                         }
4563                 }
4564
4565                 if (mode_existed)
4566                         continue;
4567
4568                 mode = amdgpu_dm_create_common_mode(encoder,
4569                                 common_modes[i].name, common_modes[i].w,
4570                                 common_modes[i].h);
4571                 drm_mode_probed_add(connector, mode);
4572                 amdgpu_dm_connector->num_modes++;
4573         }
4574 }
4575
4576 static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
4577                                               struct edid *edid)
4578 {
4579         struct amdgpu_dm_connector *amdgpu_dm_connector =
4580                         to_amdgpu_dm_connector(connector);
4581
4582         if (edid) {
4583                 /* empty probed_modes */
4584                 INIT_LIST_HEAD(&connector->probed_modes);
4585                 amdgpu_dm_connector->num_modes =
4586                                 drm_add_edid_modes(connector, edid);
4587
4588                 amdgpu_dm_get_native_mode(connector);
4589         } else {
4590                 amdgpu_dm_connector->num_modes = 0;
4591         }
4592 }
4593
4594 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
4595 {
4596         struct amdgpu_dm_connector *amdgpu_dm_connector =
4597                         to_amdgpu_dm_connector(connector);
4598         struct drm_encoder *encoder;
4599         struct edid *edid = amdgpu_dm_connector->edid;
4600
4601         encoder = amdgpu_dm_connector_to_encoder(connector);
4602
4603         if (!edid || !drm_edid_is_valid(edid)) {
4604                 amdgpu_dm_connector->num_modes =
4605                                 drm_add_modes_noedid(connector, 640, 480);
4606         } else {
4607                 amdgpu_dm_connector_ddc_get_modes(connector, edid);
4608                 amdgpu_dm_connector_add_common_modes(encoder, connector);
4609         }
4610         amdgpu_dm_fbc_init(connector);
4611
4612         return amdgpu_dm_connector->num_modes;
4613 }
4614
4615 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
4616                                      struct amdgpu_dm_connector *aconnector,
4617                                      int connector_type,
4618                                      struct dc_link *link,
4619                                      int link_index)
4620 {
4621         struct amdgpu_device *adev = dm->ddev->dev_private;
4622
4623         aconnector->connector_id = link_index;
4624         aconnector->dc_link = link;
4625         aconnector->base.interlace_allowed = false;
4626         aconnector->base.doublescan_allowed = false;
4627         aconnector->base.stereo_allowed = false;
4628         aconnector->base.dpms = DRM_MODE_DPMS_OFF;
4629         aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
4630         mutex_init(&aconnector->hpd_lock);
4631
4632         /*
4633          * configure support HPD hot plug connector_>polled default value is 0
4634          * which means HPD hot plug not supported
4635          */
4636         switch (connector_type) {
4637         case DRM_MODE_CONNECTOR_HDMIA:
4638                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
4639                 aconnector->base.ycbcr_420_allowed =
4640                         link->link_enc->features.hdmi_ycbcr420_supported ? true : false;
4641                 break;
4642         case DRM_MODE_CONNECTOR_DisplayPort:
4643                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
4644                 aconnector->base.ycbcr_420_allowed =
4645                         link->link_enc->features.dp_ycbcr420_supported ? true : false;
4646                 break;
4647         case DRM_MODE_CONNECTOR_DVID:
4648                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
4649                 break;
4650         default:
4651                 break;
4652         }
4653
4654         drm_object_attach_property(&aconnector->base.base,
4655                                 dm->ddev->mode_config.scaling_mode_property,
4656                                 DRM_MODE_SCALE_NONE);
4657
4658         drm_object_attach_property(&aconnector->base.base,
4659                                 adev->mode_info.underscan_property,
4660                                 UNDERSCAN_OFF);
4661         drm_object_attach_property(&aconnector->base.base,
4662                                 adev->mode_info.underscan_hborder_property,
4663                                 0);
4664         drm_object_attach_property(&aconnector->base.base,
4665                                 adev->mode_info.underscan_vborder_property,
4666                                 0);
4667         drm_object_attach_property(&aconnector->base.base,
4668                                 adev->mode_info.max_bpc_property,
4669                                 0);
4670
4671         if (connector_type == DRM_MODE_CONNECTOR_eDP &&
4672             dc_is_dmcu_initialized(adev->dm.dc)) {
4673                 drm_object_attach_property(&aconnector->base.base,
4674                                 adev->mode_info.abm_level_property, 0);
4675         }
4676
4677         if (connector_type == DRM_MODE_CONNECTOR_HDMIA ||
4678             connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
4679             connector_type == DRM_MODE_CONNECTOR_eDP) {
4680                 drm_connector_attach_vrr_capable_property(
4681                         &aconnector->base);
4682         }
4683 }
4684
4685 static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
4686                               struct i2c_msg *msgs, int num)
4687 {
4688         struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
4689         struct ddc_service *ddc_service = i2c->ddc_service;
4690         struct i2c_command cmd;
4691         int i;
4692         int result = -EIO;
4693
4694         cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
4695
4696         if (!cmd.payloads)
4697                 return result;
4698
4699         cmd.number_of_payloads = num;
4700         cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
4701         cmd.speed = 100;
4702
4703         for (i = 0; i < num; i++) {
4704                 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
4705                 cmd.payloads[i].address = msgs[i].addr;
4706                 cmd.payloads[i].length = msgs[i].len;
4707                 cmd.payloads[i].data = msgs[i].buf;
4708         }
4709
4710         if (dc_submit_i2c(
4711                         ddc_service->ctx->dc,
4712                         ddc_service->ddc_pin->hw_info.ddc_channel,
4713                         &cmd))
4714                 result = num;
4715
4716         kfree(cmd.payloads);
4717         return result;
4718 }
4719
4720 static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
4721 {
4722         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
4723 }
4724
4725 static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
4726         .master_xfer = amdgpu_dm_i2c_xfer,
4727         .functionality = amdgpu_dm_i2c_func,
4728 };
4729
4730 static struct amdgpu_i2c_adapter *
4731 create_i2c(struct ddc_service *ddc_service,
4732            int link_index,
4733            int *res)
4734 {
4735         struct amdgpu_device *adev = ddc_service->ctx->driver_context;
4736         struct amdgpu_i2c_adapter *i2c;
4737
4738         i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
4739         if (!i2c)
4740                 return NULL;
4741         i2c->base.owner = THIS_MODULE;
4742         i2c->base.class = I2C_CLASS_DDC;
4743         i2c->base.dev.parent = &adev->pdev->dev;
4744         i2c->base.algo = &amdgpu_dm_i2c_algo;
4745         snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
4746         i2c_set_adapdata(&i2c->base, i2c);
4747         i2c->ddc_service = ddc_service;
4748         i2c->ddc_service->ddc_pin->hw_info.ddc_channel = link_index;
4749
4750         return i2c;
4751 }
4752
4753
4754 /*
4755  * Note: this function assumes that dc_link_detect() was called for the
4756  * dc_link which will be represented by this aconnector.
4757  */
4758 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
4759                                     struct amdgpu_dm_connector *aconnector,
4760                                     uint32_t link_index,
4761                                     struct amdgpu_encoder *aencoder)
4762 {
4763         int res = 0;
4764         int connector_type;
4765         struct dc *dc = dm->dc;
4766         struct dc_link *link = dc_get_link_at_index(dc, link_index);
4767         struct amdgpu_i2c_adapter *i2c;
4768
4769         link->priv = aconnector;
4770
4771         DRM_DEBUG_DRIVER("%s()\n", __func__);
4772
4773         i2c = create_i2c(link->ddc, link->link_index, &res);
4774         if (!i2c) {
4775                 DRM_ERROR("Failed to create i2c adapter data\n");
4776                 return -ENOMEM;
4777         }
4778
4779         aconnector->i2c = i2c;
4780         res = i2c_add_adapter(&i2c->base);
4781
4782         if (res) {
4783                 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
4784                 goto out_free;
4785         }
4786
4787         connector_type = to_drm_connector_type(link->connector_signal);
4788
4789         res = drm_connector_init(
4790                         dm->ddev,
4791                         &aconnector->base,
4792                         &amdgpu_dm_connector_funcs,
4793                         connector_type);
4794
4795         if (res) {
4796                 DRM_ERROR("connector_init failed\n");
4797                 aconnector->connector_id = -1;
4798                 goto out_free;
4799         }
4800
4801         drm_connector_helper_add(
4802                         &aconnector->base,
4803                         &amdgpu_dm_connector_helper_funcs);
4804
4805         if (aconnector->base.funcs->reset)
4806                 aconnector->base.funcs->reset(&aconnector->base);
4807
4808         amdgpu_dm_connector_init_helper(
4809                 dm,
4810                 aconnector,
4811                 connector_type,
4812                 link,
4813                 link_index);
4814
4815         drm_connector_attach_encoder(
4816                 &aconnector->base, &aencoder->base);
4817
4818         drm_connector_register(&aconnector->base);
4819 #if defined(CONFIG_DEBUG_FS)
4820         res = connector_debugfs_init(aconnector);
4821         if (res) {
4822                 DRM_ERROR("Failed to create debugfs for connector");
4823                 goto out_free;
4824         }
4825         aconnector->debugfs_dpcd_address = 0;
4826         aconnector->debugfs_dpcd_size = 0;
4827 #endif
4828
4829         if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
4830                 || connector_type == DRM_MODE_CONNECTOR_eDP)
4831                 amdgpu_dm_initialize_dp_connector(dm, aconnector);
4832
4833 out_free:
4834         if (res) {
4835                 kfree(i2c);
4836                 aconnector->i2c = NULL;
4837         }
4838         return res;
4839 }
4840
4841 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
4842 {
4843         switch (adev->mode_info.num_crtc) {
4844         case 1:
4845                 return 0x1;
4846         case 2:
4847                 return 0x3;
4848         case 3:
4849                 return 0x7;
4850         case 4:
4851                 return 0xf;
4852         case 5:
4853                 return 0x1f;
4854         case 6:
4855         default:
4856                 return 0x3f;
4857         }
4858 }
4859
4860 static int amdgpu_dm_encoder_init(struct drm_device *dev,
4861                                   struct amdgpu_encoder *aencoder,
4862                                   uint32_t link_index)
4863 {
4864         struct amdgpu_device *adev = dev->dev_private;
4865
4866         int res = drm_encoder_init(dev,
4867                                    &aencoder->base,
4868                                    &amdgpu_dm_encoder_funcs,
4869                                    DRM_MODE_ENCODER_TMDS,
4870                                    NULL);
4871
4872         aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
4873
4874         if (!res)
4875                 aencoder->encoder_id = link_index;
4876         else
4877                 aencoder->encoder_id = -1;
4878
4879         drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
4880
4881         return res;
4882 }
4883
4884 static void manage_dm_interrupts(struct amdgpu_device *adev,
4885                                  struct amdgpu_crtc *acrtc,
4886                                  bool enable)
4887 {
4888         /*
4889          * this is not correct translation but will work as soon as VBLANK
4890          * constant is the same as PFLIP
4891          */
4892         int irq_type =
4893                 amdgpu_display_crtc_idx_to_irq_type(
4894                         adev,
4895                         acrtc->crtc_id);
4896
4897         if (enable) {
4898                 drm_crtc_vblank_on(&acrtc->base);
4899                 amdgpu_irq_get(
4900                         adev,
4901                         &adev->pageflip_irq,
4902                         irq_type);
4903         } else {
4904
4905                 amdgpu_irq_put(
4906                         adev,
4907                         &adev->pageflip_irq,
4908                         irq_type);
4909                 drm_crtc_vblank_off(&acrtc->base);
4910         }
4911 }
4912
4913 static bool
4914 is_scaling_state_different(const struct dm_connector_state *dm_state,
4915                            const struct dm_connector_state *old_dm_state)
4916 {
4917         if (dm_state->scaling != old_dm_state->scaling)
4918                 return true;
4919         if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
4920                 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
4921                         return true;
4922         } else  if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
4923                 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
4924                         return true;
4925         } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
4926                    dm_state->underscan_vborder != old_dm_state->underscan_vborder)
4927                 return true;
4928         return false;
4929 }
4930
4931 static void remove_stream(struct amdgpu_device *adev,
4932                           struct amdgpu_crtc *acrtc,
4933                           struct dc_stream_state *stream)
4934 {
4935         /* this is the update mode case */
4936
4937         acrtc->otg_inst = -1;
4938         acrtc->enabled = false;
4939 }
4940
4941 static int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc,
4942                                struct dc_cursor_position *position)
4943 {
4944         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
4945         int x, y;
4946         int xorigin = 0, yorigin = 0;
4947
4948         if (!crtc || !plane->state->fb) {
4949                 position->enable = false;
4950                 position->x = 0;
4951                 position->y = 0;
4952                 return 0;
4953         }
4954
4955         if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) ||
4956             (plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) {
4957                 DRM_ERROR("%s: bad cursor width or height %d x %d\n",
4958                           __func__,
4959                           plane->state->crtc_w,
4960                           plane->state->crtc_h);
4961                 return -EINVAL;
4962         }
4963
4964         x = plane->state->crtc_x;
4965         y = plane->state->crtc_y;
4966
4967         if (crtc->primary->state) {
4968                 /* avivo cursor are offset into the total surface */
4969                 x += crtc->primary->state->src_x >> 16;
4970                 y += crtc->primary->state->src_y >> 16;
4971         }
4972
4973         if (x < 0) {
4974                 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
4975                 x = 0;
4976         }
4977         if (y < 0) {
4978                 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
4979                 y = 0;
4980         }
4981         position->enable = true;
4982         position->x = x;
4983         position->y = y;
4984         position->x_hotspot = xorigin;
4985         position->y_hotspot = yorigin;
4986
4987         return 0;
4988 }
4989
4990 static void handle_cursor_update(struct drm_plane *plane,
4991                                  struct drm_plane_state *old_plane_state)
4992 {
4993         struct amdgpu_device *adev = plane->dev->dev_private;
4994         struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb);
4995         struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc;
4996         struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL;
4997         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
4998         uint64_t address = afb ? afb->address : 0;
4999         struct dc_cursor_position position;
5000         struct dc_cursor_attributes attributes;
5001         int ret;
5002
5003         if (!plane->state->fb && !old_plane_state->fb)
5004                 return;
5005
5006         DRM_DEBUG_DRIVER("%s: crtc_id=%d with size %d to %d\n",
5007                          __func__,
5008                          amdgpu_crtc->crtc_id,
5009                          plane->state->crtc_w,
5010                          plane->state->crtc_h);
5011
5012         ret = get_cursor_position(plane, crtc, &position);
5013         if (ret)
5014                 return;
5015
5016         if (!position.enable) {
5017                 /* turn off cursor */
5018                 if (crtc_state && crtc_state->stream) {
5019                         mutex_lock(&adev->dm.dc_lock);
5020                         dc_stream_set_cursor_position(crtc_state->stream,
5021                                                       &position);
5022                         mutex_unlock(&adev->dm.dc_lock);
5023                 }
5024                 return;
5025         }
5026
5027         amdgpu_crtc->cursor_width = plane->state->crtc_w;
5028         amdgpu_crtc->cursor_height = plane->state->crtc_h;
5029
5030         memset(&attributes, 0, sizeof(attributes));
5031         attributes.address.high_part = upper_32_bits(address);
5032         attributes.address.low_part  = lower_32_bits(address);
5033         attributes.width             = plane->state->crtc_w;
5034         attributes.height            = plane->state->crtc_h;
5035         attributes.color_format      = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA;
5036         attributes.rotation_angle    = 0;
5037         attributes.attribute_flags.value = 0;
5038
5039         attributes.pitch = attributes.width;
5040
5041         if (crtc_state->stream) {
5042                 mutex_lock(&adev->dm.dc_lock);
5043                 if (!dc_stream_set_cursor_attributes(crtc_state->stream,
5044                                                          &attributes))
5045                         DRM_ERROR("DC failed to set cursor attributes\n");
5046
5047                 if (!dc_stream_set_cursor_position(crtc_state->stream,
5048                                                    &position))
5049                         DRM_ERROR("DC failed to set cursor position\n");
5050                 mutex_unlock(&adev->dm.dc_lock);
5051         }
5052 }
5053
5054 static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
5055 {
5056
5057         assert_spin_locked(&acrtc->base.dev->event_lock);
5058         WARN_ON(acrtc->event);
5059
5060         acrtc->event = acrtc->base.state->event;
5061
5062         /* Set the flip status */
5063         acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
5064
5065         /* Mark this event as consumed */
5066         acrtc->base.state->event = NULL;
5067
5068         DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
5069                                                  acrtc->crtc_id);
5070 }
5071
5072 static void update_freesync_state_on_stream(
5073         struct amdgpu_display_manager *dm,
5074         struct dm_crtc_state *new_crtc_state,
5075         struct dc_stream_state *new_stream,
5076         struct dc_plane_state *surface,
5077         u32 flip_timestamp_in_us)
5078 {
5079         struct mod_vrr_params vrr_params;
5080         struct dc_info_packet vrr_infopacket = {0};
5081         struct amdgpu_device *adev = dm->adev;
5082         unsigned long flags;
5083
5084         if (!new_stream)
5085                 return;
5086
5087         /*
5088          * TODO: Determine why min/max totals and vrefresh can be 0 here.
5089          * For now it's sufficient to just guard against these conditions.
5090          */
5091
5092         if (!new_stream->timing.h_total || !new_stream->timing.v_total)
5093                 return;
5094
5095         spin_lock_irqsave(&adev->ddev->event_lock, flags);
5096         vrr_params = new_crtc_state->vrr_params;
5097
5098         if (surface) {
5099                 mod_freesync_handle_preflip(
5100                         dm->freesync_module,
5101                         surface,
5102                         new_stream,
5103                         flip_timestamp_in_us,
5104                         &vrr_params);
5105
5106                 if (adev->family < AMDGPU_FAMILY_AI &&
5107                     amdgpu_dm_vrr_active(new_crtc_state)) {
5108                         mod_freesync_handle_v_update(dm->freesync_module,
5109                                                      new_stream, &vrr_params);
5110                 }
5111         }
5112
5113         mod_freesync_build_vrr_infopacket(
5114                 dm->freesync_module,
5115                 new_stream,
5116                 &vrr_params,
5117                 PACKET_TYPE_VRR,
5118                 TRANSFER_FUNC_UNKNOWN,
5119                 &vrr_infopacket);
5120
5121         new_crtc_state->freesync_timing_changed |=
5122                 (memcmp(&new_crtc_state->vrr_params.adjust,
5123                         &vrr_params.adjust,
5124                         sizeof(vrr_params.adjust)) != 0);
5125
5126         new_crtc_state->freesync_vrr_info_changed |=
5127                 (memcmp(&new_crtc_state->vrr_infopacket,
5128                         &vrr_infopacket,
5129                         sizeof(vrr_infopacket)) != 0);
5130
5131         new_crtc_state->vrr_params = vrr_params;
5132         new_crtc_state->vrr_infopacket = vrr_infopacket;
5133
5134         new_stream->adjust = new_crtc_state->vrr_params.adjust;
5135         new_stream->vrr_infopacket = vrr_infopacket;
5136
5137         if (new_crtc_state->freesync_vrr_info_changed)
5138                 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d",
5139                               new_crtc_state->base.crtc->base.id,
5140                               (int)new_crtc_state->base.vrr_enabled,
5141                               (int)vrr_params.state);
5142
5143         spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
5144 }
5145
5146 static void pre_update_freesync_state_on_stream(
5147         struct amdgpu_display_manager *dm,
5148         struct dm_crtc_state *new_crtc_state)
5149 {
5150         struct dc_stream_state *new_stream = new_crtc_state->stream;
5151         struct mod_vrr_params vrr_params;
5152         struct mod_freesync_config config = new_crtc_state->freesync_config;
5153         struct amdgpu_device *adev = dm->adev;
5154         unsigned long flags;
5155
5156         if (!new_stream)
5157                 return;
5158
5159         /*
5160          * TODO: Determine why min/max totals and vrefresh can be 0 here.
5161          * For now it's sufficient to just guard against these conditions.
5162          */
5163         if (!new_stream->timing.h_total || !new_stream->timing.v_total)
5164                 return;
5165
5166         spin_lock_irqsave(&adev->ddev->event_lock, flags);
5167         vrr_params = new_crtc_state->vrr_params;
5168
5169         if (new_crtc_state->vrr_supported &&
5170             config.min_refresh_in_uhz &&
5171             config.max_refresh_in_uhz) {
5172                 config.state = new_crtc_state->base.vrr_enabled ?
5173                         VRR_STATE_ACTIVE_VARIABLE :
5174                         VRR_STATE_INACTIVE;
5175         } else {
5176                 config.state = VRR_STATE_UNSUPPORTED;
5177         }
5178
5179         mod_freesync_build_vrr_params(dm->freesync_module,
5180                                       new_stream,
5181                                       &config, &vrr_params);
5182
5183         new_crtc_state->freesync_timing_changed |=
5184                 (memcmp(&new_crtc_state->vrr_params.adjust,
5185                         &vrr_params.adjust,
5186                         sizeof(vrr_params.adjust)) != 0);
5187
5188         new_crtc_state->vrr_params = vrr_params;
5189         spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
5190 }
5191
5192 static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state,
5193                                             struct dm_crtc_state *new_state)
5194 {
5195         bool old_vrr_active = amdgpu_dm_vrr_active(old_state);
5196         bool new_vrr_active = amdgpu_dm_vrr_active(new_state);
5197
5198         if (!old_vrr_active && new_vrr_active) {
5199                 /* Transition VRR inactive -> active:
5200                  * While VRR is active, we must not disable vblank irq, as a
5201                  * reenable after disable would compute bogus vblank/pflip
5202                  * timestamps if it likely happened inside display front-porch.
5203                  *
5204                  * We also need vupdate irq for the actual core vblank handling
5205                  * at end of vblank.
5206                  */
5207                 dm_set_vupdate_irq(new_state->base.crtc, true);
5208                 drm_crtc_vblank_get(new_state->base.crtc);
5209                 DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n",
5210                                  __func__, new_state->base.crtc->base.id);
5211         } else if (old_vrr_active && !new_vrr_active) {
5212                 /* Transition VRR active -> inactive:
5213                  * Allow vblank irq disable again for fixed refresh rate.
5214                  */
5215                 dm_set_vupdate_irq(new_state->base.crtc, false);
5216                 drm_crtc_vblank_put(new_state->base.crtc);
5217                 DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n",
5218                                  __func__, new_state->base.crtc->base.id);
5219         }
5220 }
5221
5222 static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state)
5223 {
5224         struct drm_plane *plane;
5225         struct drm_plane_state *old_plane_state, *new_plane_state;
5226         int i;
5227
5228         /*
5229          * TODO: Make this per-stream so we don't issue redundant updates for
5230          * commits with multiple streams.
5231          */
5232         for_each_oldnew_plane_in_state(state, plane, old_plane_state,
5233                                        new_plane_state, i)
5234                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
5235                         handle_cursor_update(plane, old_plane_state);
5236 }
5237
5238 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
5239                                     struct dc_state *dc_state,
5240                                     struct drm_device *dev,
5241                                     struct amdgpu_display_manager *dm,
5242                                     struct drm_crtc *pcrtc,
5243                                     bool wait_for_vblank)
5244 {
5245         uint32_t i;
5246         uint64_t timestamp_ns;
5247         struct drm_plane *plane;
5248         struct drm_plane_state *old_plane_state, *new_plane_state;
5249         struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
5250         struct drm_crtc_state *new_pcrtc_state =
5251                         drm_atomic_get_new_crtc_state(state, pcrtc);
5252         struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
5253         struct dm_crtc_state *dm_old_crtc_state =
5254                         to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
5255         int planes_count = 0, vpos, hpos;
5256         long r;
5257         unsigned long flags;
5258         struct amdgpu_bo *abo;
5259         uint64_t tiling_flags;
5260         uint32_t target_vblank, last_flip_vblank;
5261         bool vrr_active = amdgpu_dm_vrr_active(acrtc_state);
5262         bool pflip_present = false;
5263         struct {
5264                 struct dc_surface_update surface_updates[MAX_SURFACES];
5265                 struct dc_plane_info plane_infos[MAX_SURFACES];
5266                 struct dc_scaling_info scaling_infos[MAX_SURFACES];
5267                 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
5268                 struct dc_stream_update stream_update;
5269         } *bundle;
5270
5271         bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
5272
5273         if (!bundle) {
5274                 dm_error("Failed to allocate update bundle\n");
5275                 goto cleanup;
5276         }
5277
5278         /*
5279          * Disable the cursor first if we're disabling all the planes.
5280          * It'll remain on the screen after the planes are re-enabled
5281          * if we don't.
5282          */
5283         if (acrtc_state->active_planes == 0)
5284                 amdgpu_dm_commit_cursors(state);
5285
5286         /* update planes when needed */
5287         for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
5288                 struct drm_crtc *crtc = new_plane_state->crtc;
5289                 struct drm_crtc_state *new_crtc_state;
5290                 struct drm_framebuffer *fb = new_plane_state->fb;
5291                 bool plane_needs_flip;
5292                 struct dc_plane_state *dc_plane;
5293                 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
5294
5295                 /* Cursor plane is handled after stream updates */
5296                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
5297                         continue;
5298
5299                 if (!fb || !crtc || pcrtc != crtc)
5300                         continue;
5301
5302                 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
5303                 if (!new_crtc_state->active)
5304                         continue;
5305
5306                 dc_plane = dm_new_plane_state->dc_state;
5307
5308                 bundle->surface_updates[planes_count].surface = dc_plane;
5309                 if (new_pcrtc_state->color_mgmt_changed) {
5310                         bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction;
5311                         bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func;
5312                 }
5313
5314                 fill_dc_scaling_info(new_plane_state,
5315                                      &bundle->scaling_infos[planes_count]);
5316
5317                 bundle->surface_updates[planes_count].scaling_info =
5318                         &bundle->scaling_infos[planes_count];
5319
5320                 plane_needs_flip = old_plane_state->fb && new_plane_state->fb;
5321
5322                 pflip_present = pflip_present || plane_needs_flip;
5323
5324                 if (!plane_needs_flip) {
5325                         planes_count += 1;
5326                         continue;
5327                 }
5328
5329                 abo = gem_to_amdgpu_bo(fb->obj[0]);
5330
5331                 /*
5332                  * Wait for all fences on this FB. Do limited wait to avoid
5333                  * deadlock during GPU reset when this fence will not signal
5334                  * but we hold reservation lock for the BO.
5335                  */
5336                 r = reservation_object_wait_timeout_rcu(abo->tbo.resv, true,
5337                                                         false,
5338                                                         msecs_to_jiffies(5000));
5339                 if (unlikely(r <= 0))
5340                         DRM_ERROR("Waiting for fences timed out or interrupted!");
5341
5342                 /*
5343                  * TODO This might fail and hence better not used, wait
5344                  * explicitly on fences instead
5345                  * and in general should be called for
5346                  * blocking commit to as per framework helpers
5347                  */
5348                 r = amdgpu_bo_reserve(abo, true);
5349                 if (unlikely(r != 0))
5350                         DRM_ERROR("failed to reserve buffer before flip\n");
5351
5352                 amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
5353
5354                 amdgpu_bo_unreserve(abo);
5355
5356                 fill_dc_plane_info_and_addr(
5357                         dm->adev, new_plane_state, tiling_flags,
5358                         &bundle->plane_infos[planes_count],
5359                         &bundle->flip_addrs[planes_count].address);
5360
5361                 bundle->surface_updates[planes_count].plane_info =
5362                         &bundle->plane_infos[planes_count];
5363
5364                 bundle->flip_addrs[planes_count].flip_immediate =
5365                                 (crtc->state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
5366
5367                 timestamp_ns = ktime_get_ns();
5368                 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000);
5369                 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count];
5370                 bundle->surface_updates[planes_count].surface = dc_plane;
5371
5372                 if (!bundle->surface_updates[planes_count].surface) {
5373                         DRM_ERROR("No surface for CRTC: id=%d\n",
5374                                         acrtc_attach->crtc_id);
5375                         continue;
5376                 }
5377
5378                 if (plane == pcrtc->primary)
5379                         update_freesync_state_on_stream(
5380                                 dm,
5381                                 acrtc_state,
5382                                 acrtc_state->stream,
5383                                 dc_plane,
5384                                 bundle->flip_addrs[planes_count].flip_timestamp_in_us);
5385
5386                 DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x\n",
5387                                  __func__,
5388                                  bundle->flip_addrs[planes_count].address.grph.addr.high_part,
5389                                  bundle->flip_addrs[planes_count].address.grph.addr.low_part);
5390
5391                 planes_count += 1;
5392
5393         }
5394
5395         if (pflip_present) {
5396                 if (!vrr_active) {
5397                         /* Use old throttling in non-vrr fixed refresh rate mode
5398                          * to keep flip scheduling based on target vblank counts
5399                          * working in a backwards compatible way, e.g., for
5400                          * clients using the GLX_OML_sync_control extension or
5401                          * DRI3/Present extension with defined target_msc.
5402                          */
5403                         last_flip_vblank = amdgpu_get_vblank_counter_kms(dm->ddev, acrtc_attach->crtc_id);
5404                 }
5405                 else {
5406                         /* For variable refresh rate mode only:
5407                          * Get vblank of last completed flip to avoid > 1 vrr
5408                          * flips per video frame by use of throttling, but allow
5409                          * flip programming anywhere in the possibly large
5410                          * variable vrr vblank interval for fine-grained flip
5411                          * timing control and more opportunity to avoid stutter
5412                          * on late submission of flips.
5413                          */
5414                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
5415                         last_flip_vblank = acrtc_attach->last_flip_vblank;
5416                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
5417                 }
5418
5419                 target_vblank = last_flip_vblank + wait_for_vblank;
5420
5421                 /*
5422                  * Wait until we're out of the vertical blank period before the one
5423                  * targeted by the flip
5424                  */
5425                 while ((acrtc_attach->enabled &&
5426                         (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id,
5427                                                             0, &vpos, &hpos, NULL,
5428                                                             NULL, &pcrtc->hwmode)
5429                          & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
5430                         (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
5431                         (int)(target_vblank -
5432                           amdgpu_get_vblank_counter_kms(dm->ddev, acrtc_attach->crtc_id)) > 0)) {
5433                         usleep_range(1000, 1100);
5434                 }
5435
5436                 if (acrtc_attach->base.state->event) {
5437                         drm_crtc_vblank_get(pcrtc);
5438
5439                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
5440
5441                         WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE);
5442                         prepare_flip_isr(acrtc_attach);
5443
5444                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
5445                 }
5446
5447                 if (acrtc_state->stream) {
5448
5449                         if (acrtc_state->freesync_timing_changed)
5450                                 bundle->stream_update.adjust =
5451                                         &acrtc_state->stream->adjust;
5452
5453                         if (acrtc_state->freesync_vrr_info_changed)
5454                                 bundle->stream_update.vrr_infopacket =
5455                                         &acrtc_state->stream->vrr_infopacket;
5456                 }
5457         }
5458
5459         /* Update the planes if changed or disable if we don't have any. */
5460         if (planes_count || acrtc_state->active_planes == 0) {
5461                 if (new_pcrtc_state->mode_changed) {
5462                         bundle->stream_update.src = acrtc_state->stream->src;
5463                         bundle->stream_update.dst = acrtc_state->stream->dst;
5464                 }
5465
5466                 if (new_pcrtc_state->color_mgmt_changed)
5467                         bundle->stream_update.out_transfer_func = acrtc_state->stream->out_transfer_func;
5468
5469                 acrtc_state->stream->abm_level = acrtc_state->abm_level;
5470                 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level)
5471                         bundle->stream_update.abm_level = &acrtc_state->abm_level;
5472
5473                 mutex_lock(&dm->dc_lock);
5474                 dc_commit_updates_for_stream(dm->dc,
5475                                                      bundle->surface_updates,
5476                                                      planes_count,
5477                                                      acrtc_state->stream,
5478                                                      &bundle->stream_update,
5479                                                      dc_state);
5480                 mutex_unlock(&dm->dc_lock);
5481         }
5482
5483         /*
5484          * Update cursor state *after* programming all the planes.
5485          * This avoids redundant programming in the case where we're going
5486          * to be disabling a single plane - those pipes are being disabled.
5487          */
5488         if (acrtc_state->active_planes)
5489                 amdgpu_dm_commit_cursors(state);
5490
5491 cleanup:
5492         kfree(bundle);
5493 }
5494
5495 /*
5496  * Enable interrupts on CRTCs that are newly active, undergone
5497  * a modeset, or have active planes again.
5498  *
5499  * Done in two passes, based on the for_modeset flag:
5500  * Pass 1: For CRTCs going through modeset
5501  * Pass 2: For CRTCs going from 0 to n active planes
5502  *
5503  * Interrupts can only be enabled after the planes are programmed,
5504  * so this requires a two-pass approach since we don't want to
5505  * just defer the interrupts until after commit planes every time.
5506  */
5507 static void amdgpu_dm_enable_crtc_interrupts(struct drm_device *dev,
5508                                              struct drm_atomic_state *state,
5509                                              bool for_modeset)
5510 {
5511         struct amdgpu_device *adev = dev->dev_private;
5512         struct drm_crtc *crtc;
5513         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
5514         int i;
5515
5516         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
5517                                       new_crtc_state, i) {
5518                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
5519                 struct dm_crtc_state *dm_new_crtc_state =
5520                         to_dm_crtc_state(new_crtc_state);
5521                 struct dm_crtc_state *dm_old_crtc_state =
5522                         to_dm_crtc_state(old_crtc_state);
5523                 bool modeset = drm_atomic_crtc_needs_modeset(new_crtc_state);
5524                 bool run_pass;
5525
5526                 run_pass = (for_modeset && modeset) ||
5527                            (!for_modeset && !modeset &&
5528                             !dm_old_crtc_state->interrupts_enabled);
5529
5530                 if (!run_pass)
5531                         continue;
5532
5533                 if (!dm_new_crtc_state->interrupts_enabled)
5534                         continue;
5535
5536                 manage_dm_interrupts(adev, acrtc, true);
5537
5538 #ifdef CONFIG_DEBUG_FS
5539                 /* The stream has changed so CRC capture needs to re-enabled. */
5540                 if (dm_new_crtc_state->crc_enabled) {
5541                         dm_new_crtc_state->crc_enabled = false;
5542                         amdgpu_dm_crtc_set_crc_source(crtc, "auto");
5543                 }
5544 #endif
5545         }
5546 }
5547
5548 /*
5549  * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
5550  * @crtc_state: the DRM CRTC state
5551  * @stream_state: the DC stream state.
5552  *
5553  * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
5554  * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
5555  */
5556 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
5557                                                 struct dc_stream_state *stream_state)
5558 {
5559         stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state);
5560 }
5561
5562 static int amdgpu_dm_atomic_commit(struct drm_device *dev,
5563                                    struct drm_atomic_state *state,
5564                                    bool nonblock)
5565 {
5566         struct drm_crtc *crtc;
5567         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
5568         struct amdgpu_device *adev = dev->dev_private;
5569         int i;
5570
5571         /*
5572          * We evade vblank and pflip interrupts on CRTCs that are undergoing
5573          * a modeset, being disabled, or have no active planes.
5574          *
5575          * It's done in atomic commit rather than commit tail for now since
5576          * some of these interrupt handlers access the current CRTC state and
5577          * potentially the stream pointer itself.
5578          *
5579          * Since the atomic state is swapped within atomic commit and not within
5580          * commit tail this would leave to new state (that hasn't been committed yet)
5581          * being accesssed from within the handlers.
5582          *
5583          * TODO: Fix this so we can do this in commit tail and not have to block
5584          * in atomic check.
5585          */
5586         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
5587                 struct dm_crtc_state *dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
5588                 struct dm_crtc_state *dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
5589                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
5590
5591                 if (dm_old_crtc_state->interrupts_enabled &&
5592                     (!dm_new_crtc_state->interrupts_enabled ||
5593                      drm_atomic_crtc_needs_modeset(new_crtc_state))) {
5594                         /*
5595                          * Drop the extra vblank reference added by CRC
5596                          * capture if applicable.
5597                          */
5598                         if (dm_new_crtc_state->crc_enabled)
5599                                 drm_crtc_vblank_put(crtc);
5600
5601                         /*
5602                          * Only keep CRC capture enabled if there's
5603                          * still a stream for the CRTC.
5604                          */
5605                         if (!dm_new_crtc_state->stream)
5606                                 dm_new_crtc_state->crc_enabled = false;
5607
5608                         manage_dm_interrupts(adev, acrtc, false);
5609                 }
5610         }
5611         /*
5612          * Add check here for SoC's that support hardware cursor plane, to
5613          * unset legacy_cursor_update
5614          */
5615
5616         return drm_atomic_helper_commit(dev, state, nonblock);
5617
5618         /*TODO Handle EINTR, reenable IRQ*/
5619 }
5620
5621 /**
5622  * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation.
5623  * @state: The atomic state to commit
5624  *
5625  * This will tell DC to commit the constructed DC state from atomic_check,
5626  * programming the hardware. Any failures here implies a hardware failure, since
5627  * atomic check should have filtered anything non-kosher.
5628  */
5629 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
5630 {
5631         struct drm_device *dev = state->dev;
5632         struct amdgpu_device *adev = dev->dev_private;
5633         struct amdgpu_display_manager *dm = &adev->dm;
5634         struct dm_atomic_state *dm_state;
5635         struct dc_state *dc_state = NULL, *dc_state_temp = NULL;
5636         uint32_t i, j;
5637         struct drm_crtc *crtc;
5638         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
5639         unsigned long flags;
5640         bool wait_for_vblank = true;
5641         struct drm_connector *connector;
5642         struct drm_connector_state *old_con_state, *new_con_state;
5643         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
5644         int crtc_disable_count = 0;
5645
5646         drm_atomic_helper_update_legacy_modeset_state(dev, state);
5647
5648         dm_state = dm_atomic_get_new_state(state);
5649         if (dm_state && dm_state->context) {
5650                 dc_state = dm_state->context;
5651         } else {
5652                 /* No state changes, retain current state. */
5653                 dc_state_temp = dc_create_state(dm->dc);
5654                 ASSERT(dc_state_temp);
5655                 dc_state = dc_state_temp;
5656                 dc_resource_state_copy_construct_current(dm->dc, dc_state);
5657         }
5658
5659         /* update changed items */
5660         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
5661                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
5662
5663                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
5664                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
5665
5666                 DRM_DEBUG_DRIVER(
5667                         "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
5668                         "planes_changed:%d, mode_changed:%d,active_changed:%d,"
5669                         "connectors_changed:%d\n",
5670                         acrtc->crtc_id,
5671                         new_crtc_state->enable,
5672                         new_crtc_state->active,
5673                         new_crtc_state->planes_changed,
5674                         new_crtc_state->mode_changed,
5675                         new_crtc_state->active_changed,
5676                         new_crtc_state->connectors_changed);
5677
5678                 /* Copy all transient state flags into dc state */
5679                 if (dm_new_crtc_state->stream) {
5680                         amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
5681                                                             dm_new_crtc_state->stream);
5682                 }
5683
5684                 /* handles headless hotplug case, updating new_state and
5685                  * aconnector as needed
5686                  */
5687
5688                 if (modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
5689
5690                         DRM_DEBUG_DRIVER("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
5691
5692                         if (!dm_new_crtc_state->stream) {
5693                                 /*
5694                                  * this could happen because of issues with
5695                                  * userspace notifications delivery.
5696                                  * In this case userspace tries to set mode on
5697                                  * display which is disconnected in fact.
5698                                  * dc_sink is NULL in this case on aconnector.
5699                                  * We expect reset mode will come soon.
5700                                  *
5701                                  * This can also happen when unplug is done
5702                                  * during resume sequence ended
5703                                  *
5704                                  * In this case, we want to pretend we still
5705                                  * have a sink to keep the pipe running so that
5706                                  * hw state is consistent with the sw state
5707                                  */
5708                                 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
5709                                                 __func__, acrtc->base.base.id);
5710                                 continue;
5711                         }
5712
5713                         if (dm_old_crtc_state->stream)
5714                                 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
5715
5716                         pm_runtime_get_noresume(dev->dev);
5717
5718                         acrtc->enabled = true;
5719                         acrtc->hw_mode = new_crtc_state->mode;
5720                         crtc->hwmode = new_crtc_state->mode;
5721                 } else if (modereset_required(new_crtc_state)) {
5722                         DRM_DEBUG_DRIVER("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
5723
5724                         /* i.e. reset mode */
5725                         if (dm_old_crtc_state->stream)
5726                                 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
5727                 }
5728         } /* for_each_crtc_in_state() */
5729
5730         if (dc_state) {
5731                 dm_enable_per_frame_crtc_master_sync(dc_state);
5732                 mutex_lock(&dm->dc_lock);
5733                 WARN_ON(!dc_commit_state(dm->dc, dc_state));
5734                 mutex_unlock(&dm->dc_lock);
5735         }
5736
5737         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
5738                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
5739
5740                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
5741
5742                 if (dm_new_crtc_state->stream != NULL) {
5743                         const struct dc_stream_status *status =
5744                                         dc_stream_get_status(dm_new_crtc_state->stream);
5745
5746                         if (!status)
5747                                 status = dc_stream_get_status_from_state(dc_state,
5748                                                                          dm_new_crtc_state->stream);
5749
5750                         if (!status)
5751                                 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc);
5752                         else
5753                                 acrtc->otg_inst = status->primary_otg_inst;
5754                 }
5755         }
5756
5757         /* Handle connector state changes */
5758         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
5759                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
5760                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
5761                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
5762                 struct dc_surface_update dummy_updates[MAX_SURFACES];
5763                 struct dc_stream_update stream_update;
5764                 struct dc_stream_status *status = NULL;
5765
5766                 memset(&dummy_updates, 0, sizeof(dummy_updates));
5767                 memset(&stream_update, 0, sizeof(stream_update));
5768
5769                 if (acrtc) {
5770                         new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
5771                         old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
5772                 }
5773
5774                 /* Skip any modesets/resets */
5775                 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
5776                         continue;
5777
5778                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
5779                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
5780
5781                 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state) &&
5782                                 (dm_new_crtc_state->abm_level == dm_old_crtc_state->abm_level))
5783                         continue;
5784
5785                 if (is_scaling_state_different(dm_new_con_state, dm_old_con_state)) {
5786                         update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
5787                                         dm_new_con_state, (struct dc_stream_state *)dm_new_crtc_state->stream);
5788
5789                         stream_update.src = dm_new_crtc_state->stream->src;
5790                         stream_update.dst = dm_new_crtc_state->stream->dst;
5791                 }
5792
5793                 if (dm_new_crtc_state->abm_level != dm_old_crtc_state->abm_level) {
5794                         dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level;
5795
5796                         stream_update.abm_level = &dm_new_crtc_state->abm_level;
5797                 }
5798
5799                 status = dc_stream_get_status(dm_new_crtc_state->stream);
5800                 WARN_ON(!status);
5801                 WARN_ON(!status->plane_count);
5802
5803                 /*
5804                  * TODO: DC refuses to perform stream updates without a dc_surface_update.
5805                  * Here we create an empty update on each plane.
5806                  * To fix this, DC should permit updating only stream properties.
5807                  */
5808                 for (j = 0; j < status->plane_count; j++)
5809                         dummy_updates[j].surface = status->plane_states[0];
5810
5811
5812                 mutex_lock(&dm->dc_lock);
5813                 dc_commit_updates_for_stream(dm->dc,
5814                                                      dummy_updates,
5815                                                      status->plane_count,
5816                                                      dm_new_crtc_state->stream,
5817                                                      &stream_update,
5818                                                      dc_state);
5819                 mutex_unlock(&dm->dc_lock);
5820         }
5821
5822         /* Count number of newly disabled CRTCs for dropping PM refs later. */
5823         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
5824                                       new_crtc_state, i) {
5825                 if (old_crtc_state->active && !new_crtc_state->active)
5826                         crtc_disable_count++;
5827
5828                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
5829                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
5830
5831                 /* Update freesync active state. */
5832                 pre_update_freesync_state_on_stream(dm, dm_new_crtc_state);
5833
5834                 /* Handle vrr on->off / off->on transitions */
5835                 amdgpu_dm_handle_vrr_transition(dm_old_crtc_state,
5836                                                 dm_new_crtc_state);
5837         }
5838
5839         /* Enable interrupts for CRTCs going through a modeset. */
5840         amdgpu_dm_enable_crtc_interrupts(dev, state, true);
5841
5842         for_each_new_crtc_in_state(state, crtc, new_crtc_state, j)
5843                 if (new_crtc_state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC)
5844                         wait_for_vblank = false;
5845
5846         /* update planes when needed per crtc*/
5847         for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
5848                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
5849
5850                 if (dm_new_crtc_state->stream)
5851                         amdgpu_dm_commit_planes(state, dc_state, dev,
5852                                                 dm, crtc, wait_for_vblank);
5853         }
5854
5855         /* Enable interrupts for CRTCs going from 0 to n active planes. */
5856         amdgpu_dm_enable_crtc_interrupts(dev, state, false);
5857
5858         /*
5859          * send vblank event on all events not handled in flip and
5860          * mark consumed event for drm_atomic_helper_commit_hw_done
5861          */
5862         spin_lock_irqsave(&adev->ddev->event_lock, flags);
5863         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
5864
5865                 if (new_crtc_state->event)
5866                         drm_send_event_locked(dev, &new_crtc_state->event->base);
5867
5868                 new_crtc_state->event = NULL;
5869         }
5870         spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
5871
5872         /* Signal HW programming completion */
5873         drm_atomic_helper_commit_hw_done(state);
5874
5875         if (wait_for_vblank)
5876                 drm_atomic_helper_wait_for_flip_done(dev, state);
5877
5878         drm_atomic_helper_cleanup_planes(dev, state);
5879
5880         /*
5881          * Finally, drop a runtime PM reference for each newly disabled CRTC,
5882          * so we can put the GPU into runtime suspend if we're not driving any
5883          * displays anymore
5884          */
5885         for (i = 0; i < crtc_disable_count; i++)
5886                 pm_runtime_put_autosuspend(dev->dev);
5887         pm_runtime_mark_last_busy(dev->dev);
5888
5889         if (dc_state_temp)
5890                 dc_release_state(dc_state_temp);
5891 }
5892
5893
5894 static int dm_force_atomic_commit(struct drm_connector *connector)
5895 {
5896         int ret = 0;
5897         struct drm_device *ddev = connector->dev;
5898         struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
5899         struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
5900         struct drm_plane *plane = disconnected_acrtc->base.primary;
5901         struct drm_connector_state *conn_state;
5902         struct drm_crtc_state *crtc_state;
5903         struct drm_plane_state *plane_state;
5904
5905         if (!state)
5906                 return -ENOMEM;
5907
5908         state->acquire_ctx = ddev->mode_config.acquire_ctx;
5909
5910         /* Construct an atomic state to restore previous display setting */
5911
5912         /*
5913          * Attach connectors to drm_atomic_state
5914          */
5915         conn_state = drm_atomic_get_connector_state(state, connector);
5916
5917         ret = PTR_ERR_OR_ZERO(conn_state);
5918         if (ret)
5919                 goto err;
5920
5921         /* Attach crtc to drm_atomic_state*/
5922         crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
5923
5924         ret = PTR_ERR_OR_ZERO(crtc_state);
5925         if (ret)
5926                 goto err;
5927
5928         /* force a restore */
5929         crtc_state->mode_changed = true;
5930
5931         /* Attach plane to drm_atomic_state */
5932         plane_state = drm_atomic_get_plane_state(state, plane);
5933
5934         ret = PTR_ERR_OR_ZERO(plane_state);
5935         if (ret)
5936                 goto err;
5937
5938
5939         /* Call commit internally with the state we just constructed */
5940         ret = drm_atomic_commit(state);
5941         if (!ret)
5942                 return 0;
5943
5944 err:
5945         DRM_ERROR("Restoring old state failed with %i\n", ret);
5946         drm_atomic_state_put(state);
5947
5948         return ret;
5949 }
5950
5951 /*
5952  * This function handles all cases when set mode does not come upon hotplug.
5953  * This includes when a display is unplugged then plugged back into the
5954  * same port and when running without usermode desktop manager supprot
5955  */
5956 void dm_restore_drm_connector_state(struct drm_device *dev,
5957                                     struct drm_connector *connector)
5958 {
5959         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
5960         struct amdgpu_crtc *disconnected_acrtc;
5961         struct dm_crtc_state *acrtc_state;
5962
5963         if (!aconnector->dc_sink || !connector->state || !connector->encoder)
5964                 return;
5965
5966         disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
5967         if (!disconnected_acrtc)
5968                 return;
5969
5970         acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
5971         if (!acrtc_state->stream)
5972                 return;
5973
5974         /*
5975          * If the previous sink is not released and different from the current,
5976          * we deduce we are in a state where we can not rely on usermode call
5977          * to turn on the display, so we do it here
5978          */
5979         if (acrtc_state->stream->sink != aconnector->dc_sink)
5980                 dm_force_atomic_commit(&aconnector->base);
5981 }
5982
5983 /*
5984  * Grabs all modesetting locks to serialize against any blocking commits,
5985  * Waits for completion of all non blocking commits.
5986  */
5987 static int do_aquire_global_lock(struct drm_device *dev,
5988                                  struct drm_atomic_state *state)
5989 {
5990         struct drm_crtc *crtc;
5991         struct drm_crtc_commit *commit;
5992         long ret;
5993
5994         /*
5995          * Adding all modeset locks to aquire_ctx will
5996          * ensure that when the framework release it the
5997          * extra locks we are locking here will get released to
5998          */
5999         ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
6000         if (ret)
6001                 return ret;
6002
6003         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6004                 spin_lock(&crtc->commit_lock);
6005                 commit = list_first_entry_or_null(&crtc->commit_list,
6006                                 struct drm_crtc_commit, commit_entry);
6007                 if (commit)
6008                         drm_crtc_commit_get(commit);
6009                 spin_unlock(&crtc->commit_lock);
6010
6011                 if (!commit)
6012                         continue;
6013
6014                 /*
6015                  * Make sure all pending HW programming completed and
6016                  * page flips done
6017                  */
6018                 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
6019
6020                 if (ret > 0)
6021                         ret = wait_for_completion_interruptible_timeout(
6022                                         &commit->flip_done, 10*HZ);
6023
6024                 if (ret == 0)
6025                         DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
6026                                   "timed out\n", crtc->base.id, crtc->name);
6027
6028                 drm_crtc_commit_put(commit);
6029         }
6030
6031         return ret < 0 ? ret : 0;
6032 }
6033
6034 static void get_freesync_config_for_crtc(
6035         struct dm_crtc_state *new_crtc_state,
6036         struct dm_connector_state *new_con_state)
6037 {
6038         struct mod_freesync_config config = {0};
6039         struct amdgpu_dm_connector *aconnector =
6040                         to_amdgpu_dm_connector(new_con_state->base.connector);
6041         struct drm_display_mode *mode = &new_crtc_state->base.mode;
6042         int vrefresh = drm_mode_vrefresh(mode);
6043
6044         new_crtc_state->vrr_supported = new_con_state->freesync_capable &&
6045                                         vrefresh >= aconnector->min_vfreq &&
6046                                         vrefresh <= aconnector->max_vfreq;
6047
6048         if (new_crtc_state->vrr_supported) {
6049                 new_crtc_state->stream->ignore_msa_timing_param = true;
6050                 config.state = new_crtc_state->base.vrr_enabled ?
6051                                 VRR_STATE_ACTIVE_VARIABLE :
6052                                 VRR_STATE_INACTIVE;
6053                 config.min_refresh_in_uhz =
6054                                 aconnector->min_vfreq * 1000000;
6055                 config.max_refresh_in_uhz =
6056                                 aconnector->max_vfreq * 1000000;
6057                 config.vsif_supported = true;
6058                 config.btr = true;
6059         }
6060
6061         new_crtc_state->freesync_config = config;
6062 }
6063
6064 static void reset_freesync_config_for_crtc(
6065         struct dm_crtc_state *new_crtc_state)
6066 {
6067         new_crtc_state->vrr_supported = false;
6068
6069         memset(&new_crtc_state->vrr_params, 0,
6070                sizeof(new_crtc_state->vrr_params));
6071         memset(&new_crtc_state->vrr_infopacket, 0,
6072                sizeof(new_crtc_state->vrr_infopacket));
6073 }
6074
6075 static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
6076                                 struct drm_atomic_state *state,
6077                                 struct drm_crtc *crtc,
6078                                 struct drm_crtc_state *old_crtc_state,
6079                                 struct drm_crtc_state *new_crtc_state,
6080                                 bool enable,
6081                                 bool *lock_and_validation_needed)
6082 {
6083         struct dm_atomic_state *dm_state = NULL;
6084         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
6085         struct dc_stream_state *new_stream;
6086         int ret = 0;
6087
6088         /*
6089          * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set
6090          * update changed items
6091          */
6092         struct amdgpu_crtc *acrtc = NULL;
6093         struct amdgpu_dm_connector *aconnector = NULL;
6094         struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL;
6095         struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL;
6096
6097         new_stream = NULL;
6098
6099         dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
6100         dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
6101         acrtc = to_amdgpu_crtc(crtc);
6102         aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
6103
6104         /* TODO This hack should go away */
6105         if (aconnector && enable) {
6106                 /* Make sure fake sink is created in plug-in scenario */
6107                 drm_new_conn_state = drm_atomic_get_new_connector_state(state,
6108                                                             &aconnector->base);
6109                 drm_old_conn_state = drm_atomic_get_old_connector_state(state,
6110                                                             &aconnector->base);
6111
6112                 if (IS_ERR(drm_new_conn_state)) {
6113                         ret = PTR_ERR_OR_ZERO(drm_new_conn_state);
6114                         goto fail;
6115                 }
6116
6117                 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
6118                 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state);
6119
6120                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
6121                         goto skip_modeset;
6122
6123                 new_stream = create_stream_for_sink(aconnector,
6124                                                      &new_crtc_state->mode,
6125                                                     dm_new_conn_state,
6126                                                     dm_old_crtc_state->stream);
6127
6128                 /*
6129                  * we can have no stream on ACTION_SET if a display
6130                  * was disconnected during S3, in this case it is not an
6131                  * error, the OS will be updated after detection, and
6132                  * will do the right thing on next atomic commit
6133                  */
6134
6135                 if (!new_stream) {
6136                         DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
6137                                         __func__, acrtc->base.base.id);
6138                         ret = -ENOMEM;
6139                         goto fail;
6140                 }
6141
6142                 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
6143
6144                 if (dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
6145                     dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
6146                         new_crtc_state->mode_changed = false;
6147                         DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
6148                                          new_crtc_state->mode_changed);
6149                 }
6150         }
6151
6152         /* mode_changed flag may get updated above, need to check again */
6153         if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
6154                 goto skip_modeset;
6155
6156         DRM_DEBUG_DRIVER(
6157                 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
6158                 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
6159                 "connectors_changed:%d\n",
6160                 acrtc->crtc_id,
6161                 new_crtc_state->enable,
6162                 new_crtc_state->active,
6163                 new_crtc_state->planes_changed,
6164                 new_crtc_state->mode_changed,
6165                 new_crtc_state->active_changed,
6166                 new_crtc_state->connectors_changed);
6167
6168         /* Remove stream for any changed/disabled CRTC */
6169         if (!enable) {
6170
6171                 if (!dm_old_crtc_state->stream)
6172                         goto skip_modeset;
6173
6174                 ret = dm_atomic_get_state(state, &dm_state);
6175                 if (ret)
6176                         goto fail;
6177
6178                 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
6179                                 crtc->base.id);
6180
6181                 /* i.e. reset mode */
6182                 if (dc_remove_stream_from_ctx(
6183                                 dm->dc,
6184                                 dm_state->context,
6185                                 dm_old_crtc_state->stream) != DC_OK) {
6186                         ret = -EINVAL;
6187                         goto fail;
6188                 }
6189
6190                 dc_stream_release(dm_old_crtc_state->stream);
6191                 dm_new_crtc_state->stream = NULL;
6192
6193                 reset_freesync_config_for_crtc(dm_new_crtc_state);
6194
6195                 *lock_and_validation_needed = true;
6196
6197         } else {/* Add stream for any updated/enabled CRTC */
6198                 /*
6199                  * Quick fix to prevent NULL pointer on new_stream when
6200                  * added MST connectors not found in existing crtc_state in the chained mode
6201                  * TODO: need to dig out the root cause of that
6202                  */
6203                 if (!aconnector || (!aconnector->dc_sink && aconnector->mst_port))
6204                         goto skip_modeset;
6205
6206                 if (modereset_required(new_crtc_state))
6207                         goto skip_modeset;
6208
6209                 if (modeset_required(new_crtc_state, new_stream,
6210                                      dm_old_crtc_state->stream)) {
6211
6212                         WARN_ON(dm_new_crtc_state->stream);
6213
6214                         ret = dm_atomic_get_state(state, &dm_state);
6215                         if (ret)
6216                                 goto fail;
6217
6218                         dm_new_crtc_state->stream = new_stream;
6219
6220                         dc_stream_retain(new_stream);
6221
6222                         DRM_DEBUG_DRIVER("Enabling DRM crtc: %d\n",
6223                                                 crtc->base.id);
6224
6225                         if (dc_add_stream_to_ctx(
6226                                         dm->dc,
6227                                         dm_state->context,
6228                                         dm_new_crtc_state->stream) != DC_OK) {
6229                                 ret = -EINVAL;
6230                                 goto fail;
6231                         }
6232
6233                         *lock_and_validation_needed = true;
6234                 }
6235         }
6236
6237 skip_modeset:
6238         /* Release extra reference */
6239         if (new_stream)
6240                  dc_stream_release(new_stream);
6241
6242         /*
6243          * We want to do dc stream updates that do not require a
6244          * full modeset below.
6245          */
6246         if (!(enable && aconnector && new_crtc_state->enable &&
6247               new_crtc_state->active))
6248                 return 0;
6249         /*
6250          * Given above conditions, the dc state cannot be NULL because:
6251          * 1. We're in the process of enabling CRTCs (just been added
6252          *    to the dc context, or already is on the context)
6253          * 2. Has a valid connector attached, and
6254          * 3. Is currently active and enabled.
6255          * => The dc stream state currently exists.
6256          */
6257         BUG_ON(dm_new_crtc_state->stream == NULL);
6258
6259         /* Scaling or underscan settings */
6260         if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state))
6261                 update_stream_scaling_settings(
6262                         &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);
6263
6264         /* ABM settings */
6265         dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
6266
6267         /*
6268          * Color management settings. We also update color properties
6269          * when a modeset is needed, to ensure it gets reprogrammed.
6270          */
6271         if (dm_new_crtc_state->base.color_mgmt_changed ||
6272             drm_atomic_crtc_needs_modeset(new_crtc_state)) {
6273                 ret = amdgpu_dm_set_regamma_lut(dm_new_crtc_state);
6274                 if (ret)
6275                         goto fail;
6276                 amdgpu_dm_set_ctm(dm_new_crtc_state);
6277         }
6278
6279         /* Update Freesync settings. */
6280         get_freesync_config_for_crtc(dm_new_crtc_state,
6281                                      dm_new_conn_state);
6282
6283         return ret;
6284
6285 fail:
6286         if (new_stream)
6287                 dc_stream_release(new_stream);
6288         return ret;
6289 }
6290
6291 static bool should_reset_plane(struct drm_atomic_state *state,
6292                                struct drm_plane *plane,
6293                                struct drm_plane_state *old_plane_state,
6294                                struct drm_plane_state *new_plane_state)
6295 {
6296         struct drm_plane *other;
6297         struct drm_plane_state *old_other_state, *new_other_state;
6298         struct drm_crtc_state *new_crtc_state;
6299         int i;
6300
6301         /*
6302          * TODO: Remove this hack once the checks below are sufficient
6303          * enough to determine when we need to reset all the planes on
6304          * the stream.
6305          */
6306         if (state->allow_modeset)
6307                 return true;
6308
6309         /* Exit early if we know that we're adding or removing the plane. */
6310         if (old_plane_state->crtc != new_plane_state->crtc)
6311                 return true;
6312
6313         /* old crtc == new_crtc == NULL, plane not in context. */
6314         if (!new_plane_state->crtc)
6315                 return false;
6316
6317         new_crtc_state =
6318                 drm_atomic_get_new_crtc_state(state, new_plane_state->crtc);
6319
6320         if (!new_crtc_state)
6321                 return true;
6322
6323         if (drm_atomic_crtc_needs_modeset(new_crtc_state))
6324                 return true;
6325
6326         /*
6327          * If there are any new primary or overlay planes being added or
6328          * removed then the z-order can potentially change. To ensure
6329          * correct z-order and pipe acquisition the current DC architecture
6330          * requires us to remove and recreate all existing planes.
6331          *
6332          * TODO: Come up with a more elegant solution for this.
6333          */
6334         for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) {
6335                 if (other->type == DRM_PLANE_TYPE_CURSOR)
6336                         continue;
6337
6338                 if (old_other_state->crtc != new_plane_state->crtc &&
6339                     new_other_state->crtc != new_plane_state->crtc)
6340                         continue;
6341
6342                 if (old_other_state->crtc != new_other_state->crtc)
6343                         return true;
6344
6345                 /* TODO: Remove this once we can handle fast format changes. */
6346                 if (old_other_state->fb && new_other_state->fb &&
6347                     old_other_state->fb->format != new_other_state->fb->format)
6348                         return true;
6349         }
6350
6351         return false;
6352 }
6353
6354 static int dm_update_plane_state(struct dc *dc,
6355                                  struct drm_atomic_state *state,
6356                                  struct drm_plane *plane,
6357                                  struct drm_plane_state *old_plane_state,
6358                                  struct drm_plane_state *new_plane_state,
6359                                  bool enable,
6360                                  bool *lock_and_validation_needed)
6361 {
6362
6363         struct dm_atomic_state *dm_state = NULL;
6364         struct drm_crtc *new_plane_crtc, *old_plane_crtc;
6365         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
6366         struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
6367         struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
6368         bool needs_reset;
6369         int ret = 0;
6370
6371
6372         new_plane_crtc = new_plane_state->crtc;
6373         old_plane_crtc = old_plane_state->crtc;
6374         dm_new_plane_state = to_dm_plane_state(new_plane_state);
6375         dm_old_plane_state = to_dm_plane_state(old_plane_state);
6376
6377         /*TODO Implement atomic check for cursor plane */
6378         if (plane->type == DRM_PLANE_TYPE_CURSOR)
6379                 return 0;
6380
6381         needs_reset = should_reset_plane(state, plane, old_plane_state,
6382                                          new_plane_state);
6383
6384         /* Remove any changed/removed planes */
6385         if (!enable) {
6386                 if (!needs_reset)
6387                         return 0;
6388
6389                 if (!old_plane_crtc)
6390                         return 0;
6391
6392                 old_crtc_state = drm_atomic_get_old_crtc_state(
6393                                 state, old_plane_crtc);
6394                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
6395
6396                 if (!dm_old_crtc_state->stream)
6397                         return 0;
6398
6399                 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",
6400                                 plane->base.id, old_plane_crtc->base.id);
6401
6402                 ret = dm_atomic_get_state(state, &dm_state);
6403                 if (ret)
6404                         return ret;
6405
6406                 if (!dc_remove_plane_from_context(
6407                                 dc,
6408                                 dm_old_crtc_state->stream,
6409                                 dm_old_plane_state->dc_state,
6410                                 dm_state->context)) {
6411
6412                         ret = EINVAL;
6413                         return ret;
6414                 }
6415
6416
6417                 dc_plane_state_release(dm_old_plane_state->dc_state);
6418                 dm_new_plane_state->dc_state = NULL;
6419
6420                 *lock_and_validation_needed = true;
6421
6422         } else { /* Add new planes */
6423                 struct dc_plane_state *dc_new_plane_state;
6424
6425                 if (drm_atomic_plane_disabling(plane->state, new_plane_state))
6426                         return 0;
6427
6428                 if (!new_plane_crtc)
6429                         return 0;
6430
6431                 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
6432                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
6433
6434                 if (!dm_new_crtc_state->stream)
6435                         return 0;
6436
6437                 if (!needs_reset)
6438                         return 0;
6439
6440                 WARN_ON(dm_new_plane_state->dc_state);
6441
6442                 dc_new_plane_state = dc_create_plane_state(dc);
6443                 if (!dc_new_plane_state)
6444                         return -ENOMEM;
6445
6446                 DRM_DEBUG_DRIVER("Enabling DRM plane: %d on DRM crtc %d\n",
6447                                 plane->base.id, new_plane_crtc->base.id);
6448
6449                 ret = fill_dc_plane_attributes(
6450                         new_plane_crtc->dev->dev_private,
6451                         dc_new_plane_state,
6452                         new_plane_state,
6453                         new_crtc_state);
6454                 if (ret) {
6455                         dc_plane_state_release(dc_new_plane_state);
6456                         return ret;
6457                 }
6458
6459                 ret = dm_atomic_get_state(state, &dm_state);
6460                 if (ret) {
6461                         dc_plane_state_release(dc_new_plane_state);
6462                         return ret;
6463                 }
6464
6465                 /*
6466                  * Any atomic check errors that occur after this will
6467                  * not need a release. The plane state will be attached
6468                  * to the stream, and therefore part of the atomic
6469                  * state. It'll be released when the atomic state is
6470                  * cleaned.
6471                  */
6472                 if (!dc_add_plane_to_context(
6473                                 dc,
6474                                 dm_new_crtc_state->stream,
6475                                 dc_new_plane_state,
6476                                 dm_state->context)) {
6477
6478                         dc_plane_state_release(dc_new_plane_state);
6479                         return -EINVAL;
6480                 }
6481
6482                 dm_new_plane_state->dc_state = dc_new_plane_state;
6483
6484                 /* Tell DC to do a full surface update every time there
6485                  * is a plane change. Inefficient, but works for now.
6486                  */
6487                 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
6488
6489                 *lock_and_validation_needed = true;
6490         }
6491
6492
6493         return ret;
6494 }
6495
6496 static int
6497 dm_determine_update_type_for_commit(struct amdgpu_display_manager *dm,
6498                                     struct drm_atomic_state *state,
6499                                     enum surface_update_type *out_type)
6500 {
6501         struct dc *dc = dm->dc;
6502         struct dm_atomic_state *dm_state = NULL, *old_dm_state = NULL;
6503         int i, j, num_plane, ret = 0;
6504         struct drm_plane_state *old_plane_state, *new_plane_state;
6505         struct dm_plane_state *new_dm_plane_state, *old_dm_plane_state;
6506         struct drm_crtc *new_plane_crtc, *old_plane_crtc;
6507         struct drm_plane *plane;
6508
6509         struct drm_crtc *crtc;
6510         struct drm_crtc_state *new_crtc_state, *old_crtc_state;
6511         struct dm_crtc_state *new_dm_crtc_state, *old_dm_crtc_state;
6512         struct dc_stream_status *status = NULL;
6513
6514         struct dc_surface_update *updates;
6515         enum surface_update_type update_type = UPDATE_TYPE_FAST;
6516
6517         updates = kcalloc(MAX_SURFACES, sizeof(*updates), GFP_KERNEL);
6518
6519         if (!updates) {
6520                 DRM_ERROR("Failed to allocate plane updates\n");
6521                 /* Set type to FULL to avoid crashing in DC*/
6522                 update_type = UPDATE_TYPE_FULL;
6523                 goto cleanup;
6524         }
6525
6526         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
6527                 struct dc_scaling_info scaling_info;
6528                 struct dc_stream_update stream_update;
6529
6530                 memset(&stream_update, 0, sizeof(stream_update));
6531
6532                 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
6533                 old_dm_crtc_state = to_dm_crtc_state(old_crtc_state);
6534                 num_plane = 0;
6535
6536                 if (new_dm_crtc_state->stream != old_dm_crtc_state->stream) {
6537                         update_type = UPDATE_TYPE_FULL;
6538                         goto cleanup;
6539                 }
6540
6541                 if (!new_dm_crtc_state->stream)
6542                         continue;
6543
6544                 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, j) {
6545                         new_plane_crtc = new_plane_state->crtc;
6546                         old_plane_crtc = old_plane_state->crtc;
6547                         new_dm_plane_state = to_dm_plane_state(new_plane_state);
6548                         old_dm_plane_state = to_dm_plane_state(old_plane_state);
6549
6550                         if (plane->type == DRM_PLANE_TYPE_CURSOR)
6551                                 continue;
6552
6553                         if (new_dm_plane_state->dc_state != old_dm_plane_state->dc_state) {
6554                                 update_type = UPDATE_TYPE_FULL;
6555                                 goto cleanup;
6556                         }
6557
6558                         if (crtc != new_plane_crtc)
6559                                 continue;
6560
6561                         updates[num_plane].surface = new_dm_plane_state->dc_state;
6562
6563                         if (new_crtc_state->mode_changed) {
6564                                 stream_update.dst = new_dm_crtc_state->stream->dst;
6565                                 stream_update.src = new_dm_crtc_state->stream->src;
6566                         }
6567
6568                         if (new_crtc_state->color_mgmt_changed) {
6569                                 updates[num_plane].gamma =
6570                                                 new_dm_plane_state->dc_state->gamma_correction;
6571                                 updates[num_plane].in_transfer_func =
6572                                                 new_dm_plane_state->dc_state->in_transfer_func;
6573                                 stream_update.gamut_remap =
6574                                                 &new_dm_crtc_state->stream->gamut_remap_matrix;
6575                                 stream_update.out_transfer_func =
6576                                                 new_dm_crtc_state->stream->out_transfer_func;
6577                         }
6578
6579                         ret = fill_dc_scaling_info(new_plane_state,
6580                                                    &scaling_info);
6581                         if (ret)
6582                                 goto cleanup;
6583
6584                         updates[num_plane].scaling_info = &scaling_info;
6585
6586                         num_plane++;
6587                 }
6588
6589                 if (num_plane == 0)
6590                         continue;
6591
6592                 ret = dm_atomic_get_state(state, &dm_state);
6593                 if (ret)
6594                         goto cleanup;
6595
6596                 old_dm_state = dm_atomic_get_old_state(state);
6597                 if (!old_dm_state) {
6598                         ret = -EINVAL;
6599                         goto cleanup;
6600                 }
6601
6602                 status = dc_stream_get_status_from_state(old_dm_state->context,
6603                                                          new_dm_crtc_state->stream);
6604
6605                 /*
6606                  * TODO: DC modifies the surface during this call so we need
6607                  * to lock here - find a way to do this without locking.
6608                  */
6609                 mutex_lock(&dm->dc_lock);
6610                 update_type = dc_check_update_surfaces_for_stream(dc, updates, num_plane,
6611                                                                   &stream_update, status);
6612                 mutex_unlock(&dm->dc_lock);
6613
6614                 if (update_type > UPDATE_TYPE_MED) {
6615                         update_type = UPDATE_TYPE_FULL;
6616                         goto cleanup;
6617                 }
6618         }
6619
6620 cleanup:
6621         kfree(updates);
6622
6623         *out_type = update_type;
6624         return ret;
6625 }
6626
6627 /**
6628  * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.
6629  * @dev: The DRM device
6630  * @state: The atomic state to commit
6631  *
6632  * Validate that the given atomic state is programmable by DC into hardware.
6633  * This involves constructing a &struct dc_state reflecting the new hardware
6634  * state we wish to commit, then querying DC to see if it is programmable. It's
6635  * important not to modify the existing DC state. Otherwise, atomic_check
6636  * may unexpectedly commit hardware changes.
6637  *
6638  * When validating the DC state, it's important that the right locks are
6639  * acquired. For full updates case which removes/adds/updates streams on one
6640  * CRTC while flipping on another CRTC, acquiring global lock will guarantee
6641  * that any such full update commit will wait for completion of any outstanding
6642  * flip using DRMs synchronization events. See
6643  * dm_determine_update_type_for_commit()
6644  *
6645  * Note that DM adds the affected connectors for all CRTCs in state, when that
6646  * might not seem necessary. This is because DC stream creation requires the
6647  * DC sink, which is tied to the DRM connector state. Cleaning this up should
6648  * be possible but non-trivial - a possible TODO item.
6649  *
6650  * Return: -Error code if validation failed.
6651  */
6652 static int amdgpu_dm_atomic_check(struct drm_device *dev,
6653                                   struct drm_atomic_state *state)
6654 {
6655         struct amdgpu_device *adev = dev->dev_private;
6656         struct dm_atomic_state *dm_state = NULL;
6657         struct dc *dc = adev->dm.dc;
6658         struct drm_connector *connector;
6659         struct drm_connector_state *old_con_state, *new_con_state;
6660         struct drm_crtc *crtc;
6661         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
6662         struct drm_plane *plane;
6663         struct drm_plane_state *old_plane_state, *new_plane_state;
6664         enum surface_update_type update_type = UPDATE_TYPE_FAST;
6665         enum surface_update_type overall_update_type = UPDATE_TYPE_FAST;
6666
6667         int ret, i;
6668
6669         /*
6670          * This bool will be set for true for any modeset/reset
6671          * or plane update which implies non fast surface update.
6672          */
6673         bool lock_and_validation_needed = false;
6674
6675         ret = drm_atomic_helper_check_modeset(dev, state);
6676         if (ret)
6677                 goto fail;
6678
6679         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
6680                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
6681                     !new_crtc_state->color_mgmt_changed &&
6682                     old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled)
6683                         continue;
6684
6685                 if (!new_crtc_state->enable)
6686                         continue;
6687
6688                 ret = drm_atomic_add_affected_connectors(state, crtc);
6689                 if (ret)
6690                         return ret;
6691
6692                 ret = drm_atomic_add_affected_planes(state, crtc);
6693                 if (ret)
6694                         goto fail;
6695         }
6696
6697         /*
6698          * Add all primary and overlay planes on the CRTC to the state
6699          * whenever a plane is enabled to maintain correct z-ordering
6700          * and to enable fast surface updates.
6701          */
6702         drm_for_each_crtc(crtc, dev) {
6703                 bool modified = false;
6704
6705                 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
6706                         if (plane->type == DRM_PLANE_TYPE_CURSOR)
6707                                 continue;
6708
6709                         if (new_plane_state->crtc == crtc ||
6710                             old_plane_state->crtc == crtc) {
6711                                 modified = true;
6712                                 break;
6713                         }
6714                 }
6715
6716                 if (!modified)
6717                         continue;
6718
6719                 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) {
6720                         if (plane->type == DRM_PLANE_TYPE_CURSOR)
6721                                 continue;
6722
6723                         new_plane_state =
6724                                 drm_atomic_get_plane_state(state, plane);
6725
6726                         if (IS_ERR(new_plane_state)) {
6727                                 ret = PTR_ERR(new_plane_state);
6728                                 goto fail;
6729                         }
6730                 }
6731         }
6732
6733         /* Remove exiting planes if they are modified */
6734         for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
6735                 ret = dm_update_plane_state(dc, state, plane,
6736                                             old_plane_state,
6737                                             new_plane_state,
6738                                             false,
6739                                             &lock_and_validation_needed);
6740                 if (ret)
6741                         goto fail;
6742         }
6743
6744         /* Disable all crtcs which require disable */
6745         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
6746                 ret = dm_update_crtc_state(&adev->dm, state, crtc,
6747                                            old_crtc_state,
6748                                            new_crtc_state,
6749                                            false,
6750                                            &lock_and_validation_needed);
6751                 if (ret)
6752                         goto fail;
6753         }
6754
6755         /* Enable all crtcs which require enable */
6756         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
6757                 ret = dm_update_crtc_state(&adev->dm, state, crtc,
6758                                            old_crtc_state,
6759                                            new_crtc_state,
6760                                            true,
6761                                            &lock_and_validation_needed);
6762                 if (ret)
6763                         goto fail;
6764         }
6765
6766         /* Add new/modified planes */
6767         for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
6768                 ret = dm_update_plane_state(dc, state, plane,
6769                                             old_plane_state,
6770                                             new_plane_state,
6771                                             true,
6772                                             &lock_and_validation_needed);
6773                 if (ret)
6774                         goto fail;
6775         }
6776
6777         /* Run this here since we want to validate the streams we created */
6778         ret = drm_atomic_helper_check_planes(dev, state);
6779         if (ret)
6780                 goto fail;
6781
6782         /* Check scaling and underscan changes*/
6783         /* TODO Removed scaling changes validation due to inability to commit
6784          * new stream into context w\o causing full reset. Need to
6785          * decide how to handle.
6786          */
6787         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
6788                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
6789                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
6790                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
6791
6792                 /* Skip any modesets/resets */
6793                 if (!acrtc || drm_atomic_crtc_needs_modeset(
6794                                 drm_atomic_get_new_crtc_state(state, &acrtc->base)))
6795                         continue;
6796
6797                 /* Skip any thing not scale or underscan changes */
6798                 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
6799                         continue;
6800
6801                 overall_update_type = UPDATE_TYPE_FULL;
6802                 lock_and_validation_needed = true;
6803         }
6804
6805         ret = dm_determine_update_type_for_commit(&adev->dm, state, &update_type);
6806         if (ret)
6807                 goto fail;
6808
6809         if (overall_update_type < update_type)
6810                 overall_update_type = update_type;
6811
6812         /*
6813          * lock_and_validation_needed was an old way to determine if we need to set
6814          * the global lock. Leaving it in to check if we broke any corner cases
6815          * lock_and_validation_needed true = UPDATE_TYPE_FULL or UPDATE_TYPE_MED
6816          * lock_and_validation_needed false = UPDATE_TYPE_FAST
6817          */
6818         if (lock_and_validation_needed && overall_update_type <= UPDATE_TYPE_FAST)
6819                 WARN(1, "Global lock should be Set, overall_update_type should be UPDATE_TYPE_MED or UPDATE_TYPE_FULL");
6820
6821         if (overall_update_type > UPDATE_TYPE_FAST) {
6822                 ret = dm_atomic_get_state(state, &dm_state);
6823                 if (ret)
6824                         goto fail;
6825
6826                 ret = do_aquire_global_lock(dev, state);
6827                 if (ret)
6828                         goto fail;
6829
6830                 if (dc_validate_global_state(dc, dm_state->context, false) != DC_OK) {
6831                         ret = -EINVAL;
6832                         goto fail;
6833                 }
6834         } else if (state->legacy_cursor_update) {
6835                 /*
6836                  * This is a fast cursor update coming from the plane update
6837                  * helper, check if it can be done asynchronously for better
6838                  * performance.
6839                  */
6840                 state->async_update = !drm_atomic_helper_async_check(dev, state);
6841         }
6842
6843         /* Must be success */
6844         WARN_ON(ret);
6845         return ret;
6846
6847 fail:
6848         if (ret == -EDEADLK)
6849                 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
6850         else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
6851                 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
6852         else
6853                 DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret);
6854
6855         return ret;
6856 }
6857
6858 static bool is_dp_capable_without_timing_msa(struct dc *dc,
6859                                              struct amdgpu_dm_connector *amdgpu_dm_connector)
6860 {
6861         uint8_t dpcd_data;
6862         bool capable = false;
6863
6864         if (amdgpu_dm_connector->dc_link &&
6865                 dm_helpers_dp_read_dpcd(
6866                                 NULL,
6867                                 amdgpu_dm_connector->dc_link,
6868                                 DP_DOWN_STREAM_PORT_COUNT,
6869                                 &dpcd_data,
6870                                 sizeof(dpcd_data))) {
6871                 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
6872         }
6873
6874         return capable;
6875 }
6876 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
6877                                         struct edid *edid)
6878 {
6879         int i;
6880         bool edid_check_required;
6881         struct detailed_timing *timing;
6882         struct detailed_non_pixel *data;
6883         struct detailed_data_monitor_range *range;
6884         struct amdgpu_dm_connector *amdgpu_dm_connector =
6885                         to_amdgpu_dm_connector(connector);
6886         struct dm_connector_state *dm_con_state = NULL;
6887
6888         struct drm_device *dev = connector->dev;
6889         struct amdgpu_device *adev = dev->dev_private;
6890         bool freesync_capable = false;
6891
6892         if (!connector->state) {
6893                 DRM_ERROR("%s - Connector has no state", __func__);
6894                 goto update;
6895         }
6896
6897         if (!edid) {
6898                 dm_con_state = to_dm_connector_state(connector->state);
6899
6900                 amdgpu_dm_connector->min_vfreq = 0;
6901                 amdgpu_dm_connector->max_vfreq = 0;
6902                 amdgpu_dm_connector->pixel_clock_mhz = 0;
6903
6904                 goto update;
6905         }
6906
6907         dm_con_state = to_dm_connector_state(connector->state);
6908
6909         edid_check_required = false;
6910         if (!amdgpu_dm_connector->dc_sink) {
6911                 DRM_ERROR("dc_sink NULL, could not add free_sync module.\n");
6912                 goto update;
6913         }
6914         if (!adev->dm.freesync_module)
6915                 goto update;
6916         /*
6917          * if edid non zero restrict freesync only for dp and edp
6918          */
6919         if (edid) {
6920                 if (amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
6921                         || amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) {
6922                         edid_check_required = is_dp_capable_without_timing_msa(
6923                                                 adev->dm.dc,
6924                                                 amdgpu_dm_connector);
6925                 }
6926         }
6927         if (edid_check_required == true && (edid->version > 1 ||
6928            (edid->version == 1 && edid->revision > 1))) {
6929                 for (i = 0; i < 4; i++) {
6930
6931                         timing  = &edid->detailed_timings[i];
6932                         data    = &timing->data.other_data;
6933                         range   = &data->data.range;
6934                         /*
6935                          * Check if monitor has continuous frequency mode
6936                          */
6937                         if (data->type != EDID_DETAIL_MONITOR_RANGE)
6938                                 continue;
6939                         /*
6940                          * Check for flag range limits only. If flag == 1 then
6941                          * no additional timing information provided.
6942                          * Default GTF, GTF Secondary curve and CVT are not
6943                          * supported
6944                          */
6945                         if (range->flags != 1)
6946                                 continue;
6947
6948                         amdgpu_dm_connector->min_vfreq = range->min_vfreq;
6949                         amdgpu_dm_connector->max_vfreq = range->max_vfreq;
6950                         amdgpu_dm_connector->pixel_clock_mhz =
6951                                 range->pixel_clock_mhz * 10;
6952                         break;
6953                 }
6954
6955                 if (amdgpu_dm_connector->max_vfreq -
6956                     amdgpu_dm_connector->min_vfreq > 10) {
6957
6958                         freesync_capable = true;
6959                 }
6960         }
6961
6962 update:
6963         if (dm_con_state)
6964                 dm_con_state->freesync_capable = freesync_capable;
6965
6966         if (connector->vrr_capable_property)
6967                 drm_connector_set_vrr_capable_property(connector,
6968                                                        freesync_capable);
6969 }
6970