drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 /* The caprices of the preprocessor require that this be declared right here */
  27 #define CREATE_TRACE_POINTS
  28
  29 #include "dm_services_types.h"
  30 #include "dc.h"
  31 #include "link_enc_cfg.h"
  32 #include "dc/inc/core_types.h"
  33 #include "dal_asic_id.h"
  34 #include "dmub/dmub_srv.h"
  35 #include "dc/inc/hw/dmcu.h"
  36 #include "dc/inc/hw/abm.h"
  37 #include "dc/dc_dmub_srv.h"
  38 #include "dc/dc_edid_parser.h"
  39 #include "dc/dc_stat.h"
  40 #include "amdgpu_dm_trace.h"
  41 #include "dpcd_defs.h"
  42 #include "link/protocols/link_dpcd.h"
  43 #include "link_service_types.h"
  44 #include "link/protocols/link_dp_capability.h"
  45 #include "link/protocols/link_ddc.h"
  46
  47 #include "vid.h"
  48 #include "amdgpu.h"
  49 #include "amdgpu_display.h"
  50 #include "amdgpu_ucode.h"
  51 #include "atom.h"
  52 #include "amdgpu_dm.h"
  53 #include "amdgpu_dm_plane.h"
  54 #include "amdgpu_dm_crtc.h"
  55 #include "amdgpu_dm_hdcp.h"
  56 #include <drm/display/drm_hdcp_helper.h>
  57 #include "amdgpu_pm.h"
  58 #include "amdgpu_atombios.h"
  59
  60 #include "amd_shared.h"
  61 #include "amdgpu_dm_irq.h"
  62 #include "dm_helpers.h"
  63 #include "amdgpu_dm_mst_types.h"
  64 #if defined(CONFIG_DEBUG_FS)
  65 #include "amdgpu_dm_debugfs.h"
  66 #endif
  67 #include "amdgpu_dm_psr.h"
  68
  69 #include "ivsrcid/ivsrcid_vislands30.h"
  70
  71 #include <linux/backlight.h>
  72 #include <linux/module.h>
  73 #include <linux/moduleparam.h>
  74 #include <linux/types.h>
  75 #include <linux/pm_runtime.h>
  76 #include <linux/pci.h>
  77 #include <linux/firmware.h>
  78 #include <linux/component.h>
  79 #include <linux/dmi.h>
  80
  81 #include <drm/display/drm_dp_mst_helper.h>
  82 #include <drm/display/drm_hdmi_helper.h>
  83 #include <drm/drm_atomic.h>
  84 #include <drm/drm_atomic_uapi.h>
  85 #include <drm/drm_atomic_helper.h>
  86 #include <drm/drm_blend.h>
  87 #include <drm/drm_fourcc.h>
  88 #include <drm/drm_edid.h>
  89 #include <drm/drm_vblank.h>
  90 #include <drm/drm_audio_component.h>
  91 #include <drm/drm_gem_atomic_helper.h>
  92 #include <drm/drm_plane_helper.h>
  93
  94 #include <acpi/video.h>
  95
  96 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
  97
  98 #include "dcn/dcn_1_0_offset.h"
  99 #include "dcn/dcn_1_0_sh_mask.h"
 100 #include "soc15_hw_ip.h"
 101 #include "soc15_common.h"
 102 #include "vega10_ip_offset.h"
 103
 104 #include "gc/gc_11_0_0_offset.h"
 105 #include "gc/gc_11_0_0_sh_mask.h"
 106
 107 #include "modules/inc/mod_freesync.h"
 108 #include "modules/power/power_helpers.h"
 109
 110 #define FIRMWARE_RENOIR_DMUB "amdgpu/renoir_dmcub.bin"
 111 MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB);
 112 #define FIRMWARE_SIENNA_CICHLID_DMUB "amdgpu/sienna_cichlid_dmcub.bin"
 113 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID_DMUB);
 114 #define FIRMWARE_NAVY_FLOUNDER_DMUB "amdgpu/navy_flounder_dmcub.bin"
 115 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER_DMUB);
 116 #define FIRMWARE_GREEN_SARDINE_DMUB "amdgpu/green_sardine_dmcub.bin"
 117 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE_DMUB);
 118 #define FIRMWARE_VANGOGH_DMUB "amdgpu/vangogh_dmcub.bin"
 119 MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB);
 120 #define FIRMWARE_DIMGREY_CAVEFISH_DMUB "amdgpu/dimgrey_cavefish_dmcub.bin"
 121 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH_DMUB);
 122 #define FIRMWARE_BEIGE_GOBY_DMUB "amdgpu/beige_goby_dmcub.bin"
 123 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY_DMUB);
 124 #define FIRMWARE_YELLOW_CARP_DMUB "amdgpu/yellow_carp_dmcub.bin"
 125 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP_DMUB);
 126 #define FIRMWARE_DCN_314_DMUB "amdgpu/dcn_3_1_4_dmcub.bin"
 127 MODULE_FIRMWARE(FIRMWARE_DCN_314_DMUB);
 128 #define FIRMWARE_DCN_315_DMUB "amdgpu/dcn_3_1_5_dmcub.bin"
 129 MODULE_FIRMWARE(FIRMWARE_DCN_315_DMUB);
 130 #define FIRMWARE_DCN316_DMUB "amdgpu/dcn_3_1_6_dmcub.bin"
 131 MODULE_FIRMWARE(FIRMWARE_DCN316_DMUB);
 132
 133 #define FIRMWARE_DCN_V3_2_0_DMCUB "amdgpu/dcn_3_2_0_dmcub.bin"
 134 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_0_DMCUB);
 135 #define FIRMWARE_DCN_V3_2_1_DMCUB "amdgpu/dcn_3_2_1_dmcub.bin"
 136 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_1_DMCUB);
 137
 138 #define FIRMWARE_RAVEN_DMCU             "amdgpu/raven_dmcu.bin"
 139 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
 140
 141 #define FIRMWARE_NAVI12_DMCU            "amdgpu/navi12_dmcu.bin"
 142 MODULE_FIRMWARE(FIRMWARE_NAVI12_DMCU);
 143
 144 /* Number of bytes in PSP header for firmware. */
 145 #define PSP_HEADER_BYTES 0x100
 146
 147 /* Number of bytes in PSP footer for firmware. */
 148 #define PSP_FOOTER_BYTES 0x100
 149
 150 /**
 151  * DOC: overview
 152  *
 153  * The AMDgpu display manager, **amdgpu_dm** (or even simpler,
 154  * **dm**) sits between DRM and DC. It acts as a liaison, converting DRM
 155  * requests into DC requests, and DC responses into DRM responses.
 156  *
 157  * The root control structure is &struct amdgpu_display_manager.
 158  */
 159
 160 /* basic init/fini API */
 161 static int amdgpu_dm_init(struct amdgpu_device *adev);
 162 static void amdgpu_dm_fini(struct amdgpu_device *adev);
 163 static bool is_freesync_video_mode(const struct drm_display_mode *mode, struct amdgpu_dm_connector *aconnector);
 164
 165 static enum drm_mode_subconnector get_subconnector_type(struct dc_link *link)
 166 {
 167         switch (link->dpcd_caps.dongle_type) {
 168         case DISPLAY_DONGLE_NONE:
 169                 return DRM_MODE_SUBCONNECTOR_Native;
 170         case DISPLAY_DONGLE_DP_VGA_CONVERTER:
 171                 return DRM_MODE_SUBCONNECTOR_VGA;
 172         case DISPLAY_DONGLE_DP_DVI_CONVERTER:
 173         case DISPLAY_DONGLE_DP_DVI_DONGLE:
 174                 return DRM_MODE_SUBCONNECTOR_DVID;
 175         case DISPLAY_DONGLE_DP_HDMI_CONVERTER:
 176         case DISPLAY_DONGLE_DP_HDMI_DONGLE:
 177                 return DRM_MODE_SUBCONNECTOR_HDMIA;
 178         case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
 179         default:
 180                 return DRM_MODE_SUBCONNECTOR_Unknown;
 181         }
 182 }
 183
 184 static void update_subconnector_property(struct amdgpu_dm_connector *aconnector)
 185 {
 186         struct dc_link *link = aconnector->dc_link;
 187         struct drm_connector *connector = &aconnector->base;
 188         enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
 189
 190         if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
 191                 return;
 192
 193         if (aconnector->dc_sink)
 194                 subconnector = get_subconnector_type(link);
 195
 196         drm_object_property_set_value(&connector->base,
 197                         connector->dev->mode_config.dp_subconnector_property,
 198                         subconnector);
 199 }
 200
 201 /*
 202  * initializes drm_device display related structures, based on the information
 203  * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
 204  * drm_encoder, drm_mode_config
 205  *
 206  * Returns 0 on success
 207  */
 208 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
 209 /* removes and deallocates the drm structures, created by the above function */
 210 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
 211
 212 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
 213                                     struct amdgpu_dm_connector *amdgpu_dm_connector,
 214                                     u32 link_index,
 215                                     struct amdgpu_encoder *amdgpu_encoder);
 216 static int amdgpu_dm_encoder_init(struct drm_device *dev,
 217                                   struct amdgpu_encoder *aencoder,
 218                                   uint32_t link_index);
 219
 220 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
 221
 222 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
 223
 224 static int amdgpu_dm_atomic_check(struct drm_device *dev,
 225                                   struct drm_atomic_state *state);
 226
 227 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector);
 228 static void handle_hpd_rx_irq(void *param);
 229
 230 static bool
 231 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
 232                                  struct drm_crtc_state *new_crtc_state);
 233 /*
 234  * dm_vblank_get_counter
 235  *
 236  * @brief
 237  * Get counter for number of vertical blanks
 238  *
 239  * @param
 240  * struct amdgpu_device *adev - [in] desired amdgpu device
 241  * int disp_idx - [in] which CRTC to get the counter from
 242  *
 243  * @return
 244  * Counter for vertical blanks
 245  */
 246 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
 247 {
 248         if (crtc >= adev->mode_info.num_crtc)
 249                 return 0;
 250         else {
 251                 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
 252
 253                 if (acrtc->dm_irq_params.stream == NULL) {
 254                         DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
 255                                   crtc);
 256                         return 0;
 257                 }
 258
 259                 return dc_stream_get_vblank_counter(acrtc->dm_irq_params.stream);
 260         }
 261 }
 262
 263 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
 264                                   u32 *vbl, u32 *position)
 265 {
 266         u32 v_blank_start, v_blank_end, h_position, v_position;
 267
 268         if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
 269                 return -EINVAL;
 270         else {
 271                 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
 272
 273                 if (acrtc->dm_irq_params.stream ==  NULL) {
 274                         DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
 275                                   crtc);
 276                         return 0;
 277                 }
 278
 279                 /*
 280                  * TODO rework base driver to use values directly.
 281                  * for now parse it back into reg-format
 282                  */
 283                 dc_stream_get_scanoutpos(acrtc->dm_irq_params.stream,
 284                                          &v_blank_start,
 285                                          &v_blank_end,
 286                                          &h_position,
 287                                          &v_position);
 288
 289                 *position = v_position | (h_position << 16);
 290                 *vbl = v_blank_start | (v_blank_end << 16);
 291         }
 292
 293         return 0;
 294 }
 295
 296 static bool dm_is_idle(void *handle)
 297 {
 298         /* XXX todo */
 299         return true;
 300 }
 301
 302 static int dm_wait_for_idle(void *handle)
 303 {
 304         /* XXX todo */
 305         return 0;
 306 }
 307
 308 static bool dm_check_soft_reset(void *handle)
 309 {
 310         return false;
 311 }
 312
 313 static int dm_soft_reset(void *handle)
 314 {
 315         /* XXX todo */
 316         return 0;
 317 }
 318
 319 static struct amdgpu_crtc *
 320 get_crtc_by_otg_inst(struct amdgpu_device *adev,
 321                      int otg_inst)
 322 {
 323         struct drm_device *dev = adev_to_drm(adev);
 324         struct drm_crtc *crtc;
 325         struct amdgpu_crtc *amdgpu_crtc;
 326
 327         if (WARN_ON(otg_inst == -1))
 328                 return adev->mode_info.crtcs[0];
 329
 330         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 331                 amdgpu_crtc = to_amdgpu_crtc(crtc);
 332
 333                 if (amdgpu_crtc->otg_inst == otg_inst)
 334                         return amdgpu_crtc;
 335         }
 336
 337         return NULL;
 338 }
 339
 340 static inline bool is_dc_timing_adjust_needed(struct dm_crtc_state *old_state,
 341                                               struct dm_crtc_state *new_state)
 342 {
 343         if (new_state->freesync_config.state ==  VRR_STATE_ACTIVE_FIXED)
 344                 return true;
 345         else if (amdgpu_dm_crtc_vrr_active(old_state) != amdgpu_dm_crtc_vrr_active(new_state))
 346                 return true;
 347         else
 348                 return false;
 349 }
 350
 351 static inline void reverse_planes_order(struct dc_surface_update *array_of_surface_update,
 352                                         int planes_count)
 353 {
 354         int i, j;
 355
 356         for (i = 0, j = planes_count - 1; i < j; i++, j--)
 357                 swap(array_of_surface_update[i], array_of_surface_update[j]);
 358 }
 359
 360 /**
 361  * update_planes_and_stream_adapter() - Send planes to be updated in DC
 362  *
 363  * DC has a generic way to update planes and stream via
 364  * dc_update_planes_and_stream function; however, DM might need some
 365  * adjustments and preparation before calling it. This function is a wrapper
 366  * for the dc_update_planes_and_stream that does any required configuration
 367  * before passing control to DC.
 368  */
 369 static inline bool update_planes_and_stream_adapter(struct dc *dc,
 370                                                     int update_type,
 371                                                     int planes_count,
 372                                                     struct dc_stream_state *stream,
 373                                                     struct dc_stream_update *stream_update,
 374                                                     struct dc_surface_update *array_of_surface_update)
 375 {
 376         reverse_planes_order(array_of_surface_update, planes_count);
 377
 378         /*
 379          * Previous frame finished and HW is ready for optimization.
 380          */
 381         if (update_type == UPDATE_TYPE_FAST)
 382                 dc_post_update_surfaces_to_stream(dc);
 383
 384         return dc_update_planes_and_stream(dc,
 385                                            array_of_surface_update,
 386                                            planes_count,
 387                                            stream,
 388                                            stream_update);
 389 }
 390
 391 /**
 392  * dm_pflip_high_irq() - Handle pageflip interrupt
 393  * @interrupt_params: ignored
 394  *
 395  * Handles the pageflip interrupt by notifying all interested parties
 396  * that the pageflip has been completed.
 397  */
 398 static void dm_pflip_high_irq(void *interrupt_params)
 399 {
 400         struct amdgpu_crtc *amdgpu_crtc;
 401         struct common_irq_params *irq_params = interrupt_params;
 402         struct amdgpu_device *adev = irq_params->adev;
 403         unsigned long flags;
 404         struct drm_pending_vblank_event *e;
 405         u32 vpos, hpos, v_blank_start, v_blank_end;
 406         bool vrr_active;
 407
 408         amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
 409
 410         /* IRQ could occur when in initial stage */
 411         /* TODO work and BO cleanup */
 412         if (amdgpu_crtc == NULL) {
 413                 DC_LOG_PFLIP("CRTC is null, returning.\n");
 414                 return;
 415         }
 416
 417         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
 418
 419         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
 420                 DC_LOG_PFLIP("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
 421                                                  amdgpu_crtc->pflip_status,
 422                                                  AMDGPU_FLIP_SUBMITTED,
 423                                                  amdgpu_crtc->crtc_id,
 424                                                  amdgpu_crtc);
 425                 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 426                 return;
 427         }
 428
 429         /* page flip completed. */
 430         e = amdgpu_crtc->event;
 431         amdgpu_crtc->event = NULL;
 432
 433         WARN_ON(!e);
 434
 435         vrr_active = amdgpu_dm_crtc_vrr_active_irq(amdgpu_crtc);
 436
 437         /* Fixed refresh rate, or VRR scanout position outside front-porch? */
 438         if (!vrr_active ||
 439             !dc_stream_get_scanoutpos(amdgpu_crtc->dm_irq_params.stream, &v_blank_start,
 440                                       &v_blank_end, &hpos, &vpos) ||
 441             (vpos < v_blank_start)) {
 442                 /* Update to correct count and vblank timestamp if racing with
 443                  * vblank irq. This also updates to the correct vblank timestamp
 444                  * even in VRR mode, as scanout is past the front-porch atm.
 445                  */
 446                 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
 447
 448                 /* Wake up userspace by sending the pageflip event with proper
 449                  * count and timestamp of vblank of flip completion.
 450                  */
 451                 if (e) {
 452                         drm_crtc_send_vblank_event(&amdgpu_crtc->base, e);
 453
 454                         /* Event sent, so done with vblank for this flip */
 455                         drm_crtc_vblank_put(&amdgpu_crtc->base);
 456                 }
 457         } else if (e) {
 458                 /* VRR active and inside front-porch: vblank count and
 459                  * timestamp for pageflip event will only be up to date after
 460                  * drm_crtc_handle_vblank() has been executed from late vblank
 461                  * irq handler after start of back-porch (vline 0). We queue the
 462                  * pageflip event for send-out by drm_crtc_handle_vblank() with
 463                  * updated timestamp and count, once it runs after us.
 464                  *
 465                  * We need to open-code this instead of using the helper
 466                  * drm_crtc_arm_vblank_event(), as that helper would
 467                  * call drm_crtc_accurate_vblank_count(), which we must
 468                  * not call in VRR mode while we are in front-porch!
 469                  */
 470
 471                 /* sequence will be replaced by real count during send-out. */
 472                 e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base);
 473                 e->pipe = amdgpu_crtc->crtc_id;
 474
 475                 list_add_tail(&e->base.link, &adev_to_drm(adev)->vblank_event_list);
 476                 e = NULL;
 477         }
 478
 479         /* Keep track of vblank of this flip for flip throttling. We use the
 480          * cooked hw counter, as that one incremented at start of this vblank
 481          * of pageflip completion, so last_flip_vblank is the forbidden count
 482          * for queueing new pageflips if vsync + VRR is enabled.
 483          */
 484         amdgpu_crtc->dm_irq_params.last_flip_vblank =
 485                 amdgpu_get_vblank_counter_kms(&amdgpu_crtc->base);
 486
 487         amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
 488         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 489
 490         DC_LOG_PFLIP("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n",
 491                      amdgpu_crtc->crtc_id, amdgpu_crtc,
 492                      vrr_active, (int) !e);
 493 }
 494
 495 static void dm_vupdate_high_irq(void *interrupt_params)
 496 {
 497         struct common_irq_params *irq_params = interrupt_params;
 498         struct amdgpu_device *adev = irq_params->adev;
 499         struct amdgpu_crtc *acrtc;
 500         struct drm_device *drm_dev;
 501         struct drm_vblank_crtc *vblank;
 502         ktime_t frame_duration_ns, previous_timestamp;
 503         unsigned long flags;
 504         int vrr_active;
 505
 506         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE);
 507
 508         if (acrtc) {
 509                 vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc);
 510                 drm_dev = acrtc->base.dev;
 511                 vblank = &drm_dev->vblank[acrtc->base.index];
 512                 previous_timestamp = atomic64_read(&irq_params->previous_timestamp);
 513                 frame_duration_ns = vblank->time - previous_timestamp;
 514
 515                 if (frame_duration_ns > 0) {
 516                         trace_amdgpu_refresh_rate_track(acrtc->base.index,
 517                                                 frame_duration_ns,
 518                                                 ktime_divns(NSEC_PER_SEC, frame_duration_ns));
 519                         atomic64_set(&irq_params->previous_timestamp, vblank->time);
 520                 }
 521
 522                 DC_LOG_VBLANK("crtc:%d, vupdate-vrr:%d\n",
 523                               acrtc->crtc_id,
 524                               vrr_active);
 525
 526                 /* Core vblank handling is done here after end of front-porch in
 527                  * vrr mode, as vblank timestamping will give valid results
 528                  * while now done after front-porch. This will also deliver
 529                  * page-flip completion events that have been queued to us
 530                  * if a pageflip happened inside front-porch.
 531                  */
 532                 if (vrr_active) {
 533                         amdgpu_dm_crtc_handle_vblank(acrtc);
 534
 535                         /* BTR processing for pre-DCE12 ASICs */
 536                         if (acrtc->dm_irq_params.stream &&
 537                             adev->family < AMDGPU_FAMILY_AI) {
 538                                 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
 539                                 mod_freesync_handle_v_update(
 540                                     adev->dm.freesync_module,
 541                                     acrtc->dm_irq_params.stream,
 542                                     &acrtc->dm_irq_params.vrr_params);
 543
 544                                 dc_stream_adjust_vmin_vmax(
 545                                     adev->dm.dc,
 546                                     acrtc->dm_irq_params.stream,
 547                                     &acrtc->dm_irq_params.vrr_params.adjust);
 548                                 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 549                         }
 550                 }
 551         }
 552 }
 553
 554 /**
 555  * dm_crtc_high_irq() - Handles CRTC interrupt
 556  * @interrupt_params: used for determining the CRTC instance
 557  *
 558  * Handles the CRTC/VSYNC interrupt by notfying DRM's VBLANK
 559  * event handler.
 560  */
 561 static void dm_crtc_high_irq(void *interrupt_params)
 562 {
 563         struct common_irq_params *irq_params = interrupt_params;
 564         struct amdgpu_device *adev = irq_params->adev;
 565         struct amdgpu_crtc *acrtc;
 566         unsigned long flags;
 567         int vrr_active;
 568
 569         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
 570         if (!acrtc)
 571                 return;
 572
 573         vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc);
 574
 575         DC_LOG_VBLANK("crtc:%d, vupdate-vrr:%d, planes:%d\n", acrtc->crtc_id,
 576                       vrr_active, acrtc->dm_irq_params.active_planes);
 577
 578         /**
 579          * Core vblank handling at start of front-porch is only possible
 580          * in non-vrr mode, as only there vblank timestamping will give
 581          * valid results while done in front-porch. Otherwise defer it
 582          * to dm_vupdate_high_irq after end of front-porch.
 583          */
 584         if (!vrr_active)
 585                 amdgpu_dm_crtc_handle_vblank(acrtc);
 586
 587         /**
 588          * Following stuff must happen at start of vblank, for crc
 589          * computation and below-the-range btr support in vrr mode.
 590          */
 591         amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
 592
 593         /* BTR updates need to happen before VUPDATE on Vega and above. */
 594         if (adev->family < AMDGPU_FAMILY_AI)
 595                 return;
 596
 597         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
 598
 599         if (acrtc->dm_irq_params.stream &&
 600             acrtc->dm_irq_params.vrr_params.supported &&
 601             acrtc->dm_irq_params.freesync_config.state ==
 602                     VRR_STATE_ACTIVE_VARIABLE) {
 603                 mod_freesync_handle_v_update(adev->dm.freesync_module,
 604                                              acrtc->dm_irq_params.stream,
 605                                              &acrtc->dm_irq_params.vrr_params);
 606
 607                 dc_stream_adjust_vmin_vmax(adev->dm.dc, acrtc->dm_irq_params.stream,
 608                                            &acrtc->dm_irq_params.vrr_params.adjust);
 609         }
 610
 611         /*
 612          * If there aren't any active_planes then DCH HUBP may be clock-gated.
 613          * In that case, pageflip completion interrupts won't fire and pageflip
 614          * completion events won't get delivered. Prevent this by sending
 615          * pending pageflip events from here if a flip is still pending.
 616          *
 617          * If any planes are enabled, use dm_pflip_high_irq() instead, to
 618          * avoid race conditions between flip programming and completion,
 619          * which could cause too early flip completion events.
 620          */
 621         if (adev->family >= AMDGPU_FAMILY_RV &&
 622             acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED &&
 623             acrtc->dm_irq_params.active_planes == 0) {
 624                 if (acrtc->event) {
 625                         drm_crtc_send_vblank_event(&acrtc->base, acrtc->event);
 626                         acrtc->event = NULL;
 627                         drm_crtc_vblank_put(&acrtc->base);
 628                 }
 629                 acrtc->pflip_status = AMDGPU_FLIP_NONE;
 630         }
 631
 632         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 633 }
 634
 635 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
 636 /**
 637  * dm_dcn_vertical_interrupt0_high_irq() - Handles OTG Vertical interrupt0 for
 638  * DCN generation ASICs
 639  * @interrupt_params: interrupt parameters
 640  *
 641  * Used to set crc window/read out crc value at vertical line 0 position
 642  */
 643 static void dm_dcn_vertical_interrupt0_high_irq(void *interrupt_params)
 644 {
 645         struct common_irq_params *irq_params = interrupt_params;
 646         struct amdgpu_device *adev = irq_params->adev;
 647         struct amdgpu_crtc *acrtc;
 648
 649         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VLINE0);
 650
 651         if (!acrtc)
 652                 return;
 653
 654         amdgpu_dm_crtc_handle_crc_window_irq(&acrtc->base);
 655 }
 656 #endif /* CONFIG_DRM_AMD_SECURE_DISPLAY */
 657
 658 /**
 659  * dmub_aux_setconfig_callback - Callback for AUX or SET_CONFIG command.
 660  * @adev: amdgpu_device pointer
 661  * @notify: dmub notification structure
 662  *
 663  * Dmub AUX or SET_CONFIG command completion processing callback
 664  * Copies dmub notification to DM which is to be read by AUX command.
 665  * issuing thread and also signals the event to wake up the thread.
 666  */
 667 static void dmub_aux_setconfig_callback(struct amdgpu_device *adev,
 668                                         struct dmub_notification *notify)
 669 {
 670         if (adev->dm.dmub_notify)
 671                 memcpy(adev->dm.dmub_notify, notify, sizeof(struct dmub_notification));
 672         if (notify->type == DMUB_NOTIFICATION_AUX_REPLY)
 673                 complete(&adev->dm.dmub_aux_transfer_done);
 674 }
 675
 676 /**
 677  * dmub_hpd_callback - DMUB HPD interrupt processing callback.
 678  * @adev: amdgpu_device pointer
 679  * @notify: dmub notification structure
 680  *
 681  * Dmub Hpd interrupt processing callback. Gets displayindex through the
 682  * ink index and calls helper to do the processing.
 683  */
 684 static void dmub_hpd_callback(struct amdgpu_device *adev,
 685                               struct dmub_notification *notify)
 686 {
 687         struct amdgpu_dm_connector *aconnector;
 688         struct amdgpu_dm_connector *hpd_aconnector = NULL;
 689         struct drm_connector *connector;
 690         struct drm_connector_list_iter iter;
 691         struct dc_link *link;
 692         u8 link_index = 0;
 693         struct drm_device *dev;
 694
 695         if (adev == NULL)
 696                 return;
 697
 698         if (notify == NULL) {
 699                 DRM_ERROR("DMUB HPD callback notification was NULL");
 700                 return;
 701         }
 702
 703         if (notify->link_index > adev->dm.dc->link_count) {
 704                 DRM_ERROR("DMUB HPD index (%u)is abnormal", notify->link_index);
 705                 return;
 706         }
 707
 708         link_index = notify->link_index;
 709         link = adev->dm.dc->links[link_index];
 710         dev = adev->dm.ddev;
 711
 712         drm_connector_list_iter_begin(dev, &iter);
 713         drm_for_each_connector_iter(connector, &iter) {
 714                 aconnector = to_amdgpu_dm_connector(connector);
 715                 if (link && aconnector->dc_link == link) {
 716                         if (notify->type == DMUB_NOTIFICATION_HPD)
 717                                 DRM_INFO("DMUB HPD callback: link_index=%u\n", link_index);
 718                         else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ)
 719                                 DRM_INFO("DMUB HPD IRQ callback: link_index=%u\n", link_index);
 720                         else
 721                                 DRM_WARN("DMUB Unknown HPD callback type %d, link_index=%u\n",
 722                                                 notify->type, link_index);
 723
 724                         hpd_aconnector = aconnector;
 725                         break;
 726                 }
 727         }
 728         drm_connector_list_iter_end(&iter);
 729
 730         if (hpd_aconnector) {
 731                 if (notify->type == DMUB_NOTIFICATION_HPD)
 732                         handle_hpd_irq_helper(hpd_aconnector);
 733                 else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ)
 734                         handle_hpd_rx_irq(hpd_aconnector);
 735         }
 736 }
 737
 738 /**
 739  * register_dmub_notify_callback - Sets callback for DMUB notify
 740  * @adev: amdgpu_device pointer
 741  * @type: Type of dmub notification
 742  * @callback: Dmub interrupt callback function
 743  * @dmub_int_thread_offload: offload indicator
 744  *
 745  * API to register a dmub callback handler for a dmub notification
 746  * Also sets indicator whether callback processing to be offloaded.
 747  * to dmub interrupt handling thread
 748  * Return: true if successfully registered, false if there is existing registration
 749  */
 750 static bool register_dmub_notify_callback(struct amdgpu_device *adev,
 751                                           enum dmub_notification_type type,
 752                                           dmub_notify_interrupt_callback_t callback,
 753                                           bool dmub_int_thread_offload)
 754 {
 755         if (callback != NULL && type < ARRAY_SIZE(adev->dm.dmub_thread_offload)) {
 756                 adev->dm.dmub_callback[type] = callback;
 757                 adev->dm.dmub_thread_offload[type] = dmub_int_thread_offload;
 758         } else
 759                 return false;
 760
 761         return true;
 762 }
 763
 764 static void dm_handle_hpd_work(struct work_struct *work)
 765 {
 766         struct dmub_hpd_work *dmub_hpd_wrk;
 767
 768         dmub_hpd_wrk = container_of(work, struct dmub_hpd_work, handle_hpd_work);
 769
 770         if (!dmub_hpd_wrk->dmub_notify) {
 771                 DRM_ERROR("dmub_hpd_wrk dmub_notify is NULL");
 772                 return;
 773         }
 774
 775         if (dmub_hpd_wrk->dmub_notify->type < ARRAY_SIZE(dmub_hpd_wrk->adev->dm.dmub_callback)) {
 776                 dmub_hpd_wrk->adev->dm.dmub_callback[dmub_hpd_wrk->dmub_notify->type](dmub_hpd_wrk->adev,
 777                 dmub_hpd_wrk->dmub_notify);
 778         }
 779
 780         kfree(dmub_hpd_wrk->dmub_notify);
 781         kfree(dmub_hpd_wrk);
 782
 783 }
 784
 785 #define DMUB_TRACE_MAX_READ 64
 786 /**
 787  * dm_dmub_outbox1_low_irq() - Handles Outbox interrupt
 788  * @interrupt_params: used for determining the Outbox instance
 789  *
 790  * Handles the Outbox Interrupt
 791  * event handler.
 792  */
 793 static void dm_dmub_outbox1_low_irq(void *interrupt_params)
 794 {
 795         struct dmub_notification notify;
 796         struct common_irq_params *irq_params = interrupt_params;
 797         struct amdgpu_device *adev = irq_params->adev;
 798         struct amdgpu_display_manager *dm = &adev->dm;
 799         struct dmcub_trace_buf_entry entry = { 0 };
 800         u32 count = 0;
 801         struct dmub_hpd_work *dmub_hpd_wrk;
 802         struct dc_link *plink = NULL;
 803
 804         if (dc_enable_dmub_notifications(adev->dm.dc) &&
 805                 irq_params->irq_src == DC_IRQ_SOURCE_DMCUB_OUTBOX) {
 806
 807                 do {
 808                         dc_stat_get_dmub_notification(adev->dm.dc, &notify);
 809                         if (notify.type >= ARRAY_SIZE(dm->dmub_thread_offload)) {
 810                                 DRM_ERROR("DM: notify type %d invalid!", notify.type);
 811                                 continue;
 812                         }
 813                         if (!dm->dmub_callback[notify.type]) {
 814                                 DRM_DEBUG_DRIVER("DMUB notification skipped, no handler: type=%d\n", notify.type);
 815                                 continue;
 816                         }
 817                         if (dm->dmub_thread_offload[notify.type] == true) {
 818                                 dmub_hpd_wrk = kzalloc(sizeof(*dmub_hpd_wrk), GFP_ATOMIC);
 819                                 if (!dmub_hpd_wrk) {
 820                                         DRM_ERROR("Failed to allocate dmub_hpd_wrk");
 821                                         return;
 822                                 }
 823                                 dmub_hpd_wrk->dmub_notify = kzalloc(sizeof(struct dmub_notification), GFP_ATOMIC);
 824                                 if (!dmub_hpd_wrk->dmub_notify) {
 825                                         kfree(dmub_hpd_wrk);
 826                                         DRM_ERROR("Failed to allocate dmub_hpd_wrk->dmub_notify");
 827                                         return;
 828                                 }
 829                                 INIT_WORK(&dmub_hpd_wrk->handle_hpd_work, dm_handle_hpd_work);
 830                                 if (dmub_hpd_wrk->dmub_notify)
 831                                         memcpy(dmub_hpd_wrk->dmub_notify, &notify, sizeof(struct dmub_notification));
 832                                 dmub_hpd_wrk->adev = adev;
 833                                 if (notify.type == DMUB_NOTIFICATION_HPD) {
 834                                         plink = adev->dm.dc->links[notify.link_index];
 835                                         if (plink) {
 836                                                 plink->hpd_status =
 837                                                         notify.hpd_status == DP_HPD_PLUG;
 838                                         }
 839                                 }
 840                                 queue_work(adev->dm.delayed_hpd_wq, &dmub_hpd_wrk->handle_hpd_work);
 841                         } else {
 842                                 dm->dmub_callback[notify.type](adev, &notify);
 843                         }
 844                 } while (notify.pending_notification);
 845         }
 846
 847
 848         do {
 849                 if (dc_dmub_srv_get_dmub_outbox0_msg(dm->dc, &entry)) {
 850                         trace_amdgpu_dmub_trace_high_irq(entry.trace_code, entry.tick_count,
 851                                                         entry.param0, entry.param1);
 852
 853                         DRM_DEBUG_DRIVER("trace_code:%u, tick_count:%u, param0:%u, param1:%u\n",
 854                                  entry.trace_code, entry.tick_count, entry.param0, entry.param1);
 855                 } else
 856                         break;
 857
 858                 count++;
 859
 860         } while (count <= DMUB_TRACE_MAX_READ);
 861
 862         if (count > DMUB_TRACE_MAX_READ)
 863                 DRM_DEBUG_DRIVER("Warning : count > DMUB_TRACE_MAX_READ");
 864 }
 865
 866 static int dm_set_clockgating_state(void *handle,
 867                   enum amd_clockgating_state state)
 868 {
 869         return 0;
 870 }
 871
 872 static int dm_set_powergating_state(void *handle,
 873                   enum amd_powergating_state state)
 874 {
 875         return 0;
 876 }
 877
 878 /* Prototypes of private functions */
 879 static int dm_early_init(void* handle);
 880
 881 /* Allocate memory for FBC compressed data  */
 882 static void amdgpu_dm_fbc_init(struct drm_connector *connector)
 883 {
 884         struct drm_device *dev = connector->dev;
 885         struct amdgpu_device *adev = drm_to_adev(dev);
 886         struct dm_compressor_info *compressor = &adev->dm.compressor;
 887         struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
 888         struct drm_display_mode *mode;
 889         unsigned long max_size = 0;
 890
 891         if (adev->dm.dc->fbc_compressor == NULL)
 892                 return;
 893
 894         if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
 895                 return;
 896
 897         if (compressor->bo_ptr)
 898                 return;
 899
 900
 901         list_for_each_entry(mode, &connector->modes, head) {
 902                 if (max_size < mode->htotal * mode->vtotal)
 903                         max_size = mode->htotal * mode->vtotal;
 904         }
 905
 906         if (max_size) {
 907                 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,
 908                             AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr,
 909                             &compressor->gpu_addr, &compressor->cpu_addr);
 910
 911                 if (r)
 912                         DRM_ERROR("DM: Failed to initialize FBC\n");
 913                 else {
 914                         adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
 915                         DRM_INFO("DM: FBC alloc %lu\n", max_size*4);
 916                 }
 917
 918         }
 919
 920 }
 921
 922 static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port,
 923                                           int pipe, bool *enabled,
 924                                           unsigned char *buf, int max_bytes)
 925 {
 926         struct drm_device *dev = dev_get_drvdata(kdev);
 927         struct amdgpu_device *adev = drm_to_adev(dev);
 928         struct drm_connector *connector;
 929         struct drm_connector_list_iter conn_iter;
 930         struct amdgpu_dm_connector *aconnector;
 931         int ret = 0;
 932
 933         *enabled = false;
 934
 935         mutex_lock(&adev->dm.audio_lock);
 936
 937         drm_connector_list_iter_begin(dev, &conn_iter);
 938         drm_for_each_connector_iter(connector, &conn_iter) {
 939                 aconnector = to_amdgpu_dm_connector(connector);
 940                 if (aconnector->audio_inst != port)
 941                         continue;
 942
 943                 *enabled = true;
 944                 ret = drm_eld_size(connector->eld);
 945                 memcpy(buf, connector->eld, min(max_bytes, ret));
 946
 947                 break;
 948         }
 949         drm_connector_list_iter_end(&conn_iter);
 950
 951         mutex_unlock(&adev->dm.audio_lock);
 952
 953         DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled);
 954
 955         return ret;
 956 }
 957
 958 static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = {
 959         .get_eld = amdgpu_dm_audio_component_get_eld,
 960 };
 961
 962 static int amdgpu_dm_audio_component_bind(struct device *kdev,
 963                                        struct device *hda_kdev, void *data)
 964 {
 965         struct drm_device *dev = dev_get_drvdata(kdev);
 966         struct amdgpu_device *adev = drm_to_adev(dev);
 967         struct drm_audio_component *acomp = data;
 968
 969         acomp->ops = &amdgpu_dm_audio_component_ops;
 970         acomp->dev = kdev;
 971         adev->dm.audio_component = acomp;
 972
 973         return 0;
 974 }
 975
 976 static void amdgpu_dm_audio_component_unbind(struct device *kdev,
 977                                           struct device *hda_kdev, void *data)
 978 {
 979         struct drm_device *dev = dev_get_drvdata(kdev);
 980         struct amdgpu_device *adev = drm_to_adev(dev);
 981         struct drm_audio_component *acomp = data;
 982
 983         acomp->ops = NULL;
 984         acomp->dev = NULL;
 985         adev->dm.audio_component = NULL;
 986 }
 987
 988 static const struct component_ops amdgpu_dm_audio_component_bind_ops = {
 989         .bind   = amdgpu_dm_audio_component_bind,
 990         .unbind = amdgpu_dm_audio_component_unbind,
 991 };
 992
 993 static int amdgpu_dm_audio_init(struct amdgpu_device *adev)
 994 {
 995         int i, ret;
 996
 997         if (!amdgpu_audio)
 998                 return 0;
 999
1000         adev->mode_info.audio.enabled = true;
1001
1002         adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count;
1003
1004         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1005                 adev->mode_info.audio.pin[i].channels = -1;
1006                 adev->mode_info.audio.pin[i].rate = -1;
1007                 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1008                 adev->mode_info.audio.pin[i].status_bits = 0;
1009                 adev->mode_info.audio.pin[i].category_code = 0;
1010                 adev->mode_info.audio.pin[i].connected = false;
1011                 adev->mode_info.audio.pin[i].id =
1012                         adev->dm.dc->res_pool->audios[i]->inst;
1013                 adev->mode_info.audio.pin[i].offset = 0;
1014         }
1015
1016         ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops);
1017         if (ret < 0)
1018                 return ret;
1019
1020         adev->dm.audio_registered = true;
1021
1022         return 0;
1023 }
1024
1025 static void amdgpu_dm_audio_fini(struct amdgpu_device *adev)
1026 {
1027         if (!amdgpu_audio)
1028                 return;
1029
1030         if (!adev->mode_info.audio.enabled)
1031                 return;
1032
1033         if (adev->dm.audio_registered) {
1034                 component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops);
1035                 adev->dm.audio_registered = false;
1036         }
1037
1038         /* TODO: Disable audio? */
1039
1040         adev->mode_info.audio.enabled = false;
1041 }
1042
1043 static  void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin)
1044 {
1045         struct drm_audio_component *acomp = adev->dm.audio_component;
1046
1047         if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) {
1048                 DRM_DEBUG_KMS("Notify ELD: %d\n", pin);
1049
1050                 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
1051                                                  pin, -1);
1052         }
1053 }
1054
1055 static int dm_dmub_hw_init(struct amdgpu_device *adev)
1056 {
1057         const struct dmcub_firmware_header_v1_0 *hdr;
1058         struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
1059         struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
1060         const struct firmware *dmub_fw = adev->dm.dmub_fw;
1061         struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
1062         struct abm *abm = adev->dm.dc->res_pool->abm;
1063         struct dmub_srv_hw_params hw_params;
1064         enum dmub_status status;
1065         const unsigned char *fw_inst_const, *fw_bss_data;
1066         u32 i, fw_inst_const_size, fw_bss_data_size;
1067         bool has_hw_support;
1068
1069         if (!dmub_srv)
1070                 /* DMUB isn't supported on the ASIC. */
1071                 return 0;
1072
1073         if (!fb_info) {
1074                 DRM_ERROR("No framebuffer info for DMUB service.\n");
1075                 return -EINVAL;
1076         }
1077
1078         if (!dmub_fw) {
1079                 /* Firmware required for DMUB support. */
1080                 DRM_ERROR("No firmware provided for DMUB.\n");
1081                 return -EINVAL;
1082         }
1083
1084         status = dmub_srv_has_hw_support(dmub_srv, &has_hw_support);
1085         if (status != DMUB_STATUS_OK) {
1086                 DRM_ERROR("Error checking HW support for DMUB: %d\n", status);
1087                 return -EINVAL;
1088         }
1089
1090         if (!has_hw_support) {
1091                 DRM_INFO("DMUB unsupported on ASIC\n");
1092                 return 0;
1093         }
1094
1095         /* Reset DMCUB if it was previously running - before we overwrite its memory. */
1096         status = dmub_srv_hw_reset(dmub_srv);
1097         if (status != DMUB_STATUS_OK)
1098                 DRM_WARN("Error resetting DMUB HW: %d\n", status);
1099
1100         hdr = (const struct dmcub_firmware_header_v1_0 *)dmub_fw->data;
1101
1102         fw_inst_const = dmub_fw->data +
1103                         le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1104                         PSP_HEADER_BYTES;
1105
1106         fw_bss_data = dmub_fw->data +
1107                       le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1108                       le32_to_cpu(hdr->inst_const_bytes);
1109
1110         /* Copy firmware and bios info into FB memory. */
1111         fw_inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
1112                              PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
1113
1114         fw_bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
1115
1116         /* if adev->firmware.load_type == AMDGPU_FW_LOAD_PSP,
1117          * amdgpu_ucode_init_single_fw will load dmub firmware
1118          * fw_inst_const part to cw0; otherwise, the firmware back door load
1119          * will be done by dm_dmub_hw_init
1120          */
1121         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1122                 memcpy(fb_info->fb[DMUB_WINDOW_0_INST_CONST].cpu_addr, fw_inst_const,
1123                                 fw_inst_const_size);
1124         }
1125
1126         if (fw_bss_data_size)
1127                 memcpy(fb_info->fb[DMUB_WINDOW_2_BSS_DATA].cpu_addr,
1128                        fw_bss_data, fw_bss_data_size);
1129
1130         /* Copy firmware bios info into FB memory. */
1131         memcpy(fb_info->fb[DMUB_WINDOW_3_VBIOS].cpu_addr, adev->bios,
1132                adev->bios_size);
1133
1134         /* Reset regions that need to be reset. */
1135         memset(fb_info->fb[DMUB_WINDOW_4_MAILBOX].cpu_addr, 0,
1136         fb_info->fb[DMUB_WINDOW_4_MAILBOX].size);
1137
1138         memset(fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr, 0,
1139                fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size);
1140
1141         memset(fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr, 0,
1142                fb_info->fb[DMUB_WINDOW_6_FW_STATE].size);
1143
1144         /* Initialize hardware. */
1145         memset(&hw_params, 0, sizeof(hw_params));
1146         hw_params.fb_base = adev->gmc.fb_start;
1147         hw_params.fb_offset = adev->vm_manager.vram_base_offset;
1148
1149         /* backdoor load firmware and trigger dmub running */
1150         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
1151                 hw_params.load_inst_const = true;
1152
1153         if (dmcu)
1154                 hw_params.psp_version = dmcu->psp_version;
1155
1156         for (i = 0; i < fb_info->num_fb; ++i)
1157                 hw_params.fb[i] = &fb_info->fb[i];
1158
1159         switch (adev->ip_versions[DCE_HWIP][0]) {
1160         case IP_VERSION(3, 1, 3):
1161         case IP_VERSION(3, 1, 4):
1162                 hw_params.dpia_supported = true;
1163                 hw_params.disable_dpia = adev->dm.dc->debug.dpia_debug.bits.disable_dpia;
1164                 break;
1165         default:
1166                 break;
1167         }
1168
1169         status = dmub_srv_hw_init(dmub_srv, &hw_params);
1170         if (status != DMUB_STATUS_OK) {
1171                 DRM_ERROR("Error initializing DMUB HW: %d\n", status);
1172                 return -EINVAL;
1173         }
1174
1175         /* Wait for firmware load to finish. */
1176         status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
1177         if (status != DMUB_STATUS_OK)
1178                 DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
1179
1180         /* Init DMCU and ABM if available. */
1181         if (dmcu && abm) {
1182                 dmcu->funcs->dmcu_init(dmcu);
1183                 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
1184         }
1185
1186         if (!adev->dm.dc->ctx->dmub_srv)
1187                 adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv);
1188         if (!adev->dm.dc->ctx->dmub_srv) {
1189                 DRM_ERROR("Couldn't allocate DC DMUB server!\n");
1190                 return -ENOMEM;
1191         }
1192
1193         DRM_INFO("DMUB hardware initialized: version=0x%08X\n",
1194                  adev->dm.dmcub_fw_version);
1195
1196         return 0;
1197 }
1198
1199 static void dm_dmub_hw_resume(struct amdgpu_device *adev)
1200 {
1201         struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
1202         enum dmub_status status;
1203         bool init;
1204
1205         if (!dmub_srv) {
1206                 /* DMUB isn't supported on the ASIC. */
1207                 return;
1208         }
1209
1210         status = dmub_srv_is_hw_init(dmub_srv, &init);
1211         if (status != DMUB_STATUS_OK)
1212                 DRM_WARN("DMUB hardware init check failed: %d\n", status);
1213
1214         if (status == DMUB_STATUS_OK && init) {
1215                 /* Wait for firmware load to finish. */
1216                 status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
1217                 if (status != DMUB_STATUS_OK)
1218                         DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
1219         } else {
1220                 /* Perform the full hardware initialization. */
1221                 dm_dmub_hw_init(adev);
1222         }
1223 }
1224
1225 static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_addr_space_config *pa_config)
1226 {
1227         u64 pt_base;
1228         u32 logical_addr_low;
1229         u32 logical_addr_high;
1230         u32 agp_base, agp_bot, agp_top;
1231         PHYSICAL_ADDRESS_LOC page_table_start, page_table_end, page_table_base;
1232
1233         memset(pa_config, 0, sizeof(*pa_config));
1234
1235         agp_base = 0;
1236         agp_bot = adev->gmc.agp_start >> 24;
1237         agp_top = adev->gmc.agp_end >> 24;
1238
1239         /* AGP aperture is disabled */
1240         if (agp_bot == agp_top) {
1241                 logical_addr_low = adev->gmc.fb_start >> 18;
1242                 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1243                         /*
1244                          * Raven2 has a HW issue that it is unable to use the vram which
1245                          * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
1246                          * workaround that increase system aperture high address (add 1)
1247                          * to get rid of the VM fault and hardware hang.
1248                          */
1249                         logical_addr_high = (adev->gmc.fb_end >> 18) + 0x1;
1250                 else
1251                         logical_addr_high = adev->gmc.fb_end >> 18;
1252         } else {
1253                 logical_addr_low = min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18;
1254                 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1255                         /*
1256                          * Raven2 has a HW issue that it is unable to use the vram which
1257                          * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
1258                          * workaround that increase system aperture high address (add 1)
1259                          * to get rid of the VM fault and hardware hang.
1260                          */
1261                         logical_addr_high = max((adev->gmc.fb_end >> 18) + 0x1, adev->gmc.agp_end >> 18);
1262                 else
1263                         logical_addr_high = max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18;
1264         }
1265
1266         pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
1267
1268         page_table_start.high_part = (u32)(adev->gmc.gart_start >> 44) & 0xF;
1269         page_table_start.low_part = (u32)(adev->gmc.gart_start >> 12);
1270         page_table_end.high_part = (u32)(adev->gmc.gart_end >> 44) & 0xF;
1271         page_table_end.low_part = (u32)(adev->gmc.gart_end >> 12);
1272         page_table_base.high_part = upper_32_bits(pt_base) & 0xF;
1273         page_table_base.low_part = lower_32_bits(pt_base);
1274
1275         pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18;
1276         pa_config->system_aperture.end_addr = (uint64_t)logical_addr_high << 18;
1277
1278         pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24 ;
1279         pa_config->system_aperture.agp_bot = (uint64_t)agp_bot << 24;
1280         pa_config->system_aperture.agp_top = (uint64_t)agp_top << 24;
1281
1282         pa_config->system_aperture.fb_base = adev->gmc.fb_start;
1283         pa_config->system_aperture.fb_offset = adev->vm_manager.vram_base_offset;
1284         pa_config->system_aperture.fb_top = adev->gmc.fb_end;
1285
1286         pa_config->gart_config.page_table_start_addr = page_table_start.quad_part << 12;
1287         pa_config->gart_config.page_table_end_addr = page_table_end.quad_part << 12;
1288         pa_config->gart_config.page_table_base_addr = page_table_base.quad_part;
1289
1290         pa_config->is_hvm_enabled = adev->mode_info.gpu_vm_support;
1291
1292 }
1293
1294 static void force_connector_state(
1295         struct amdgpu_dm_connector *aconnector,
1296         enum drm_connector_force force_state)
1297 {
1298         struct drm_connector *connector = &aconnector->base;
1299
1300         mutex_lock(&connector->dev->mode_config.mutex);
1301         aconnector->base.force = force_state;
1302         mutex_unlock(&connector->dev->mode_config.mutex);
1303
1304         mutex_lock(&aconnector->hpd_lock);
1305         drm_kms_helper_connector_hotplug_event(connector);
1306         mutex_unlock(&aconnector->hpd_lock);
1307 }
1308
1309 static void dm_handle_hpd_rx_offload_work(struct work_struct *work)
1310 {
1311         struct hpd_rx_irq_offload_work *offload_work;
1312         struct amdgpu_dm_connector *aconnector;
1313         struct dc_link *dc_link;
1314         struct amdgpu_device *adev;
1315         enum dc_connection_type new_connection_type = dc_connection_none;
1316         unsigned long flags;
1317         union test_response test_response;
1318
1319         memset(&test_response, 0, sizeof(test_response));
1320
1321         offload_work = container_of(work, struct hpd_rx_irq_offload_work, work);
1322         aconnector = offload_work->offload_wq->aconnector;
1323
1324         if (!aconnector) {
1325                 DRM_ERROR("Can't retrieve aconnector in hpd_rx_irq_offload_work");
1326                 goto skip;
1327         }
1328
1329         adev = drm_to_adev(aconnector->base.dev);
1330         dc_link = aconnector->dc_link;
1331
1332         mutex_lock(&aconnector->hpd_lock);
1333         if (!dc_link_detect_connection_type(dc_link, &new_connection_type))
1334                 DRM_ERROR("KMS: Failed to detect connector\n");
1335         mutex_unlock(&aconnector->hpd_lock);
1336
1337         if (new_connection_type == dc_connection_none)
1338                 goto skip;
1339
1340         if (amdgpu_in_reset(adev))
1341                 goto skip;
1342
1343         mutex_lock(&adev->dm.dc_lock);
1344         if (offload_work->data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
1345                 dc_link_dp_handle_automated_test(dc_link);
1346
1347                 if (aconnector->timing_changed) {
1348                         /* force connector disconnect and reconnect */
1349                         force_connector_state(aconnector, DRM_FORCE_OFF);
1350                         msleep(100);
1351                         force_connector_state(aconnector, DRM_FORCE_UNSPECIFIED);
1352                 }
1353
1354                 test_response.bits.ACK = 1;
1355
1356                 core_link_write_dpcd(
1357                 dc_link,
1358                 DP_TEST_RESPONSE,
1359                 &test_response.raw,
1360                 sizeof(test_response));
1361         }
1362         else if ((dc_link->connector_signal != SIGNAL_TYPE_EDP) &&
1363                         dc_link_check_link_loss_status(dc_link, &offload_work->data) &&
1364                         dc_link_dp_allow_hpd_rx_irq(dc_link)) {
1365                 /* offload_work->data is from handle_hpd_rx_irq->
1366                  * schedule_hpd_rx_offload_work.this is defer handle
1367                  * for hpd short pulse. upon here, link status may be
1368                  * changed, need get latest link status from dpcd
1369                  * registers. if link status is good, skip run link
1370                  * training again.
1371                  */
1372                 union hpd_irq_data irq_data;
1373
1374                 memset(&irq_data, 0, sizeof(irq_data));
1375
1376                 /* before dc_link_dp_handle_link_loss, allow new link lost handle
1377                  * request be added to work queue if link lost at end of dc_link_
1378                  * dp_handle_link_loss
1379                  */
1380                 spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags);
1381                 offload_work->offload_wq->is_handling_link_loss = false;
1382                 spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags);
1383
1384                 if ((dc_link_dp_read_hpd_rx_irq_data(dc_link, &irq_data) == DC_OK) &&
1385                         dc_link_check_link_loss_status(dc_link, &irq_data))
1386                         dc_link_dp_handle_link_loss(dc_link);
1387         }
1388         mutex_unlock(&adev->dm.dc_lock);
1389
1390 skip:
1391         kfree(offload_work);
1392
1393 }
1394
1395 static struct hpd_rx_irq_offload_work_queue *hpd_rx_irq_create_workqueue(struct dc *dc)
1396 {
1397         int max_caps = dc->caps.max_links;
1398         int i = 0;
1399         struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq = NULL;
1400
1401         hpd_rx_offload_wq = kcalloc(max_caps, sizeof(*hpd_rx_offload_wq), GFP_KERNEL);
1402
1403         if (!hpd_rx_offload_wq)
1404                 return NULL;
1405
1406
1407         for (i = 0; i < max_caps; i++) {
1408                 hpd_rx_offload_wq[i].wq =
1409                                     create_singlethread_workqueue("amdgpu_dm_hpd_rx_offload_wq");
1410
1411                 if (hpd_rx_offload_wq[i].wq == NULL) {
1412                         DRM_ERROR("create amdgpu_dm_hpd_rx_offload_wq fail!");
1413                         goto out_err;
1414                 }
1415
1416                 spin_lock_init(&hpd_rx_offload_wq[i].offload_lock);
1417         }
1418
1419         return hpd_rx_offload_wq;
1420
1421 out_err:
1422         for (i = 0; i < max_caps; i++) {
1423                 if (hpd_rx_offload_wq[i].wq)
1424                         destroy_workqueue(hpd_rx_offload_wq[i].wq);
1425         }
1426         kfree(hpd_rx_offload_wq);
1427         return NULL;
1428 }
1429
1430 struct amdgpu_stutter_quirk {
1431         u16 chip_vendor;
1432         u16 chip_device;
1433         u16 subsys_vendor;
1434         u16 subsys_device;
1435         u8 revision;
1436 };
1437
1438 static const struct amdgpu_stutter_quirk amdgpu_stutter_quirk_list[] = {
1439         /* https://bugzilla.kernel.org/show_bug.cgi?id=214417 */
1440         { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 },
1441         { 0, 0, 0, 0, 0 },
1442 };
1443
1444 static bool dm_should_disable_stutter(struct pci_dev *pdev)
1445 {
1446         const struct amdgpu_stutter_quirk *p = amdgpu_stutter_quirk_list;
1447
1448         while (p && p->chip_device != 0) {
1449                 if (pdev->vendor == p->chip_vendor &&
1450                     pdev->device == p->chip_device &&
1451                     pdev->subsystem_vendor == p->subsys_vendor &&
1452                     pdev->subsystem_device == p->subsys_device &&
1453                     pdev->revision == p->revision) {
1454                         return true;
1455                 }
1456                 ++p;
1457         }
1458         return false;
1459 }
1460
1461 static const struct dmi_system_id hpd_disconnect_quirk_table[] = {
1462         {
1463                 .matches = {
1464                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1465                         DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3660"),
1466                 },
1467         },
1468         {
1469                 .matches = {
1470                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1471                         DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3260"),
1472                 },
1473         },
1474         {
1475                 .matches = {
1476                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1477                         DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3460"),
1478                 },
1479         },
1480         {
1481                 .matches = {
1482                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1483                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower Plus 7010"),
1484                 },
1485         },
1486         {
1487                 .matches = {
1488                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1489                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower 7010"),
1490                 },
1491         },
1492         {
1493                 .matches = {
1494                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1495                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF Plus 7010"),
1496                 },
1497         },
1498         {
1499                 .matches = {
1500                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1501                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF 7010"),
1502                 },
1503         },
1504         {
1505                 .matches = {
1506                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1507                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro Plus 7010"),
1508                 },
1509         },
1510         {
1511                 .matches = {
1512                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1513                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro 7010"),
1514                 },
1515         },
1516         {}
1517         /* TODO: refactor this from a fixed table to a dynamic option */
1518 };
1519
1520 static void retrieve_dmi_info(struct amdgpu_display_manager *dm)
1521 {
1522         const struct dmi_system_id *dmi_id;
1523
1524         dm->aux_hpd_discon_quirk = false;
1525
1526         dmi_id = dmi_first_match(hpd_disconnect_quirk_table);
1527         if (dmi_id) {
1528                 dm->aux_hpd_discon_quirk = true;
1529                 DRM_INFO("aux_hpd_discon_quirk attached\n");
1530         }
1531 }
1532
1533 static int amdgpu_dm_init(struct amdgpu_device *adev)
1534 {
1535         struct dc_init_data init_data;
1536         struct dc_callback_init init_params;
1537         int r;
1538
1539         adev->dm.ddev = adev_to_drm(adev);
1540         adev->dm.adev = adev;
1541
1542         /* Zero all the fields */
1543         memset(&init_data, 0, sizeof(init_data));
1544         memset(&init_params, 0, sizeof(init_params));
1545
1546         mutex_init(&adev->dm.dpia_aux_lock);
1547         mutex_init(&adev->dm.dc_lock);
1548         mutex_init(&adev->dm.audio_lock);
1549
1550         if(amdgpu_dm_irq_init(adev)) {
1551                 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
1552                 goto error;
1553         }
1554
1555         init_data.asic_id.chip_family = adev->family;
1556
1557         init_data.asic_id.pci_revision_id = adev->pdev->revision;
1558         init_data.asic_id.hw_internal_rev = adev->external_rev_id;
1559         init_data.asic_id.chip_id = adev->pdev->device;
1560
1561         init_data.asic_id.vram_width = adev->gmc.vram_width;
1562         /* TODO: initialize init_data.asic_id.vram_type here!!!! */
1563         init_data.asic_id.atombios_base_address =
1564                 adev->mode_info.atom_context->bios;
1565
1566         init_data.driver = adev;
1567
1568         adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
1569
1570         if (!adev->dm.cgs_device) {
1571                 DRM_ERROR("amdgpu: failed to create cgs device.\n");
1572                 goto error;
1573         }
1574
1575         init_data.cgs_device = adev->dm.cgs_device;
1576
1577         init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
1578
1579         switch (adev->ip_versions[DCE_HWIP][0]) {
1580         case IP_VERSION(2, 1, 0):
1581                 switch (adev->dm.dmcub_fw_version) {
1582                 case 0: /* development */
1583                 case 0x1: /* linux-firmware.git hash 6d9f399 */
1584                 case 0x01000000: /* linux-firmware.git hash 9a0b0f4 */
1585                         init_data.flags.disable_dmcu = false;
1586                         break;
1587                 default:
1588                         init_data.flags.disable_dmcu = true;
1589                 }
1590                 break;
1591         case IP_VERSION(2, 0, 3):
1592                 init_data.flags.disable_dmcu = true;
1593                 break;
1594         default:
1595                 break;
1596         }
1597
1598         switch (adev->asic_type) {
1599         case CHIP_CARRIZO:
1600         case CHIP_STONEY:
1601                 init_data.flags.gpu_vm_support = true;
1602                 break;
1603         default:
1604                 switch (adev->ip_versions[DCE_HWIP][0]) {
1605                 case IP_VERSION(1, 0, 0):
1606                 case IP_VERSION(1, 0, 1):
1607                         /* enable S/G on PCO and RV2 */
1608                         if ((adev->apu_flags & AMD_APU_IS_RAVEN2) ||
1609                             (adev->apu_flags & AMD_APU_IS_PICASSO))
1610                                 init_data.flags.gpu_vm_support = true;
1611                         break;
1612                 case IP_VERSION(2, 1, 0):
1613                 case IP_VERSION(3, 0, 1):
1614                 case IP_VERSION(3, 1, 2):
1615                 case IP_VERSION(3, 1, 3):
1616                 case IP_VERSION(3, 1, 4):
1617                 case IP_VERSION(3, 1, 5):
1618                 case IP_VERSION(3, 1, 6):
1619                         init_data.flags.gpu_vm_support = true;
1620                         break;
1621                 default:
1622                         break;
1623                 }
1624                 break;
1625         }
1626         if (init_data.flags.gpu_vm_support &&
1627             (amdgpu_sg_display == 0))
1628                 init_data.flags.gpu_vm_support = false;
1629
1630         if (init_data.flags.gpu_vm_support)
1631                 adev->mode_info.gpu_vm_support = true;
1632
1633         if (amdgpu_dc_feature_mask & DC_FBC_MASK)
1634                 init_data.flags.fbc_support = true;
1635
1636         if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK)
1637                 init_data.flags.multi_mon_pp_mclk_switch = true;
1638
1639         if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK)
1640                 init_data.flags.disable_fractional_pwm = true;
1641
1642         if (amdgpu_dc_feature_mask & DC_EDP_NO_POWER_SEQUENCING)
1643                 init_data.flags.edp_no_power_sequencing = true;
1644
1645         if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP1_4A)
1646                 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP1_4A = true;
1647         if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP2_0)
1648                 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP2_0 = true;
1649
1650         /* Disable SubVP + DRR config by default */
1651         init_data.flags.disable_subvp_drr = true;
1652         if (amdgpu_dc_feature_mask & DC_ENABLE_SUBVP_DRR)
1653                 init_data.flags.disable_subvp_drr = false;
1654
1655         init_data.flags.seamless_boot_edp_requested = false;
1656
1657         if (check_seamless_boot_capability(adev)) {
1658                 init_data.flags.seamless_boot_edp_requested = true;
1659                 init_data.flags.allow_seamless_boot_optimization = true;
1660                 DRM_INFO("Seamless boot condition check passed\n");
1661         }
1662
1663         init_data.flags.enable_mipi_converter_optimization = true;
1664
1665         init_data.dcn_reg_offsets = adev->reg_offset[DCE_HWIP][0];
1666         init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0];
1667
1668         INIT_LIST_HEAD(&adev->dm.da_list);
1669
1670         retrieve_dmi_info(&adev->dm);
1671
1672         /* Display Core create. */
1673         adev->dm.dc = dc_create(&init_data);
1674
1675         if (adev->dm.dc) {
1676                 DRM_INFO("Display Core initialized with v%s!\n", DC_VER);
1677         } else {
1678                 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER);
1679                 goto error;
1680         }
1681
1682         if (amdgpu_dc_debug_mask & DC_DISABLE_PIPE_SPLIT) {
1683                 adev->dm.dc->debug.force_single_disp_pipe_split = false;
1684                 adev->dm.dc->debug.pipe_split_policy = MPC_SPLIT_AVOID;
1685         }
1686
1687         if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY)
1688                 adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;
1689         if (dm_should_disable_stutter(adev->pdev))
1690                 adev->dm.dc->debug.disable_stutter = true;
1691
1692         if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER)
1693                 adev->dm.dc->debug.disable_stutter = true;
1694
1695         if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) {
1696                 adev->dm.dc->debug.disable_dsc = true;
1697         }
1698
1699         if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING)
1700                 adev->dm.dc->debug.disable_clock_gate = true;
1701
1702         if (amdgpu_dc_debug_mask & DC_FORCE_SUBVP_MCLK_SWITCH)
1703                 adev->dm.dc->debug.force_subvp_mclk_switch = true;
1704
1705         adev->dm.dc->debug.visual_confirm = amdgpu_dc_visual_confirm;
1706
1707         /* TODO: Remove after DP2 receiver gets proper support of Cable ID feature */
1708         adev->dm.dc->debug.ignore_cable_id = true;
1709
1710         /* TODO: There is a new drm mst change where the freedom of
1711          * vc_next_start_slot update is revoked/moved into drm, instead of in
1712          * driver. This forces us to make sure to get vc_next_start_slot updated
1713          * in drm function each time without considering if mst_state is active
1714          * or not. Otherwise, next time hotplug will give wrong start_slot
1715          * number. We are implementing a temporary solution to even notify drm
1716          * mst deallocation when link is no longer of MST type when uncommitting
1717          * the stream so we will have more time to work on a proper solution.
1718          * Ideally when dm_helpers_dp_mst_stop_top_mgr message is triggered, we
1719          * should notify drm to do a complete "reset" of its states and stop
1720          * calling further drm mst functions when link is no longer of an MST
1721          * type. This could happen when we unplug an MST hubs/displays. When
1722          * uncommit stream comes later after unplug, we should just reset
1723          * hardware states only.
1724          */
1725         adev->dm.dc->debug.temp_mst_deallocation_sequence = true;
1726
1727         if (adev->dm.dc->caps.dp_hdmi21_pcon_support)
1728                 DRM_INFO("DP-HDMI FRL PCON supported\n");
1729
1730         r = dm_dmub_hw_init(adev);
1731         if (r) {
1732                 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
1733                 goto error;
1734         }
1735
1736         dc_hardware_init(adev->dm.dc);
1737
1738         adev->dm.hpd_rx_offload_wq = hpd_rx_irq_create_workqueue(adev->dm.dc);
1739         if (!adev->dm.hpd_rx_offload_wq) {
1740                 DRM_ERROR("amdgpu: failed to create hpd rx offload workqueue.\n");
1741                 goto error;
1742         }
1743
1744         if ((adev->flags & AMD_IS_APU) && (adev->asic_type >= CHIP_CARRIZO)) {
1745                 struct dc_phy_addr_space_config pa_config;
1746
1747                 mmhub_read_system_context(adev, &pa_config);
1748
1749                 // Call the DC init_memory func
1750                 dc_setup_system_context(adev->dm.dc, &pa_config);
1751         }
1752
1753         adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
1754         if (!adev->dm.freesync_module) {
1755                 DRM_ERROR(
1756                 "amdgpu: failed to initialize freesync_module.\n");
1757         } else
1758                 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
1759                                 adev->dm.freesync_module);
1760
1761         amdgpu_dm_init_color_mod();
1762
1763         if (adev->dm.dc->caps.max_links > 0) {
1764                 adev->dm.vblank_control_workqueue =
1765                         create_singlethread_workqueue("dm_vblank_control_workqueue");
1766                 if (!adev->dm.vblank_control_workqueue)
1767                         DRM_ERROR("amdgpu: failed to initialize vblank_workqueue.\n");
1768         }
1769
1770         if (adev->dm.dc->caps.max_links > 0 && adev->family >= AMDGPU_FAMILY_RV) {
1771                 adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc);
1772
1773                 if (!adev->dm.hdcp_workqueue)
1774                         DRM_ERROR("amdgpu: failed to initialize hdcp_workqueue.\n");
1775                 else
1776                         DRM_DEBUG_DRIVER("amdgpu: hdcp_workqueue init done %p.\n", adev->dm.hdcp_workqueue);
1777
1778                 dc_init_callbacks(adev->dm.dc, &init_params);
1779         }
1780 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
1781         adev->dm.secure_display_ctxs = amdgpu_dm_crtc_secure_display_create_contexts(adev);
1782         if (!adev->dm.secure_display_ctxs) {
1783                 DRM_ERROR("amdgpu: failed to initialize secure_display_ctxs.\n");
1784         }
1785 #endif
1786         if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
1787                 init_completion(&adev->dm.dmub_aux_transfer_done);
1788                 adev->dm.dmub_notify = kzalloc(sizeof(struct dmub_notification), GFP_KERNEL);
1789                 if (!adev->dm.dmub_notify) {
1790                         DRM_INFO("amdgpu: fail to allocate adev->dm.dmub_notify");
1791                         goto error;
1792                 }
1793
1794                 adev->dm.delayed_hpd_wq = create_singlethread_workqueue("amdgpu_dm_hpd_wq");
1795                 if (!adev->dm.delayed_hpd_wq) {
1796                         DRM_ERROR("amdgpu: failed to create hpd offload workqueue.\n");
1797                         goto error;
1798                 }
1799
1800                 amdgpu_dm_outbox_init(adev);
1801                 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_AUX_REPLY,
1802                         dmub_aux_setconfig_callback, false)) {
1803                         DRM_ERROR("amdgpu: fail to register dmub aux callback");
1804                         goto error;
1805                 }
1806                 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD, dmub_hpd_callback, true)) {
1807                         DRM_ERROR("amdgpu: fail to register dmub hpd callback");
1808                         goto error;
1809                 }
1810                 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD_IRQ, dmub_hpd_callback, true)) {
1811                         DRM_ERROR("amdgpu: fail to register dmub hpd callback");
1812                         goto error;
1813                 }
1814         }
1815
1816         /* Enable outbox notification only after IRQ handlers are registered and DMUB is alive.
1817          * It is expected that DMUB will resend any pending notifications at this point, for
1818          * example HPD from DPIA.
1819          */
1820         if (dc_is_dmub_outbox_supported(adev->dm.dc))
1821                 dc_enable_dmub_outbox(adev->dm.dc);
1822
1823         if (amdgpu_dm_initialize_drm_device(adev)) {
1824                 DRM_ERROR(
1825                 "amdgpu: failed to initialize sw for display support.\n");
1826                 goto error;
1827         }
1828
1829         /* create fake encoders for MST */
1830         dm_dp_create_fake_mst_encoders(adev);
1831
1832         /* TODO: Add_display_info? */
1833
1834         /* TODO use dynamic cursor width */
1835         adev_to_drm(adev)->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
1836         adev_to_drm(adev)->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
1837
1838         if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) {
1839                 DRM_ERROR(
1840                 "amdgpu: failed to initialize sw for display support.\n");
1841                 goto error;
1842         }
1843
1844
1845         DRM_DEBUG_DRIVER("KMS initialized.\n");
1846
1847         return 0;
1848 error:
1849         amdgpu_dm_fini(adev);
1850
1851         return -EINVAL;
1852 }
1853
1854 static int amdgpu_dm_early_fini(void *handle)
1855 {
1856         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1857
1858         amdgpu_dm_audio_fini(adev);
1859
1860         return 0;
1861 }
1862
1863 static void amdgpu_dm_fini(struct amdgpu_device *adev)
1864 {
1865         int i;
1866
1867         if (adev->dm.vblank_control_workqueue) {
1868                 destroy_workqueue(adev->dm.vblank_control_workqueue);
1869                 adev->dm.vblank_control_workqueue = NULL;
1870         }
1871
1872         amdgpu_dm_destroy_drm_device(&adev->dm);
1873
1874 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
1875         if (adev->dm.secure_display_ctxs) {
1876                 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1877                         if (adev->dm.secure_display_ctxs[i].crtc) {
1878                                 flush_work(&adev->dm.secure_display_ctxs[i].notify_ta_work);
1879                                 flush_work(&adev->dm.secure_display_ctxs[i].forward_roi_work);
1880                         }
1881                 }
1882                 kfree(adev->dm.secure_display_ctxs);
1883                 adev->dm.secure_display_ctxs = NULL;
1884         }
1885 #endif
1886         if (adev->dm.hdcp_workqueue) {
1887                 hdcp_destroy(&adev->dev->kobj, adev->dm.hdcp_workqueue);
1888                 adev->dm.hdcp_workqueue = NULL;
1889         }
1890
1891         if (adev->dm.dc)
1892                 dc_deinit_callbacks(adev->dm.dc);
1893
1894         dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv);
1895
1896         if (dc_enable_dmub_notifications(adev->dm.dc)) {
1897                 kfree(adev->dm.dmub_notify);
1898                 adev->dm.dmub_notify = NULL;
1899                 destroy_workqueue(adev->dm.delayed_hpd_wq);
1900                 adev->dm.delayed_hpd_wq = NULL;
1901         }
1902
1903         if (adev->dm.dmub_bo)
1904                 amdgpu_bo_free_kernel(&adev->dm.dmub_bo,
1905                                       &adev->dm.dmub_bo_gpu_addr,
1906                                       &adev->dm.dmub_bo_cpu_addr);
1907
1908         if (adev->dm.hpd_rx_offload_wq) {
1909                 for (i = 0; i < adev->dm.dc->caps.max_links; i++) {
1910                         if (adev->dm.hpd_rx_offload_wq[i].wq) {
1911                                 destroy_workqueue(adev->dm.hpd_rx_offload_wq[i].wq);
1912                                 adev->dm.hpd_rx_offload_wq[i].wq = NULL;
1913                         }
1914                 }
1915
1916                 kfree(adev->dm.hpd_rx_offload_wq);
1917                 adev->dm.hpd_rx_offload_wq = NULL;
1918         }
1919
1920         /* DC Destroy TODO: Replace destroy DAL */
1921         if (adev->dm.dc)
1922                 dc_destroy(&adev->dm.dc);
1923         /*
1924          * TODO: pageflip, vlank interrupt
1925          *
1926          * amdgpu_dm_irq_fini(adev);
1927          */
1928
1929         if (adev->dm.cgs_device) {
1930                 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
1931                 adev->dm.cgs_device = NULL;
1932         }
1933         if (adev->dm.freesync_module) {
1934                 mod_freesync_destroy(adev->dm.freesync_module);
1935                 adev->dm.freesync_module = NULL;
1936         }
1937
1938         mutex_destroy(&adev->dm.audio_lock);
1939         mutex_destroy(&adev->dm.dc_lock);
1940         mutex_destroy(&adev->dm.dpia_aux_lock);
1941
1942         return;
1943 }
1944
1945 static int load_dmcu_fw(struct amdgpu_device *adev)
1946 {
1947         const char *fw_name_dmcu = NULL;
1948         int r;
1949         const struct dmcu_firmware_header_v1_0 *hdr;
1950
1951         switch(adev->asic_type) {
1952 #if defined(CONFIG_DRM_AMD_DC_SI)
1953         case CHIP_TAHITI:
1954         case CHIP_PITCAIRN:
1955         case CHIP_VERDE:
1956         case CHIP_OLAND:
1957 #endif
1958         case CHIP_BONAIRE:
1959         case CHIP_HAWAII:
1960         case CHIP_KAVERI:
1961         case CHIP_KABINI:
1962         case CHIP_MULLINS:
1963         case CHIP_TONGA:
1964         case CHIP_FIJI:
1965         case CHIP_CARRIZO:
1966         case CHIP_STONEY:
1967         case CHIP_POLARIS11:
1968         case CHIP_POLARIS10:
1969         case CHIP_POLARIS12:
1970         case CHIP_VEGAM:
1971         case CHIP_VEGA10:
1972         case CHIP_VEGA12:
1973         case CHIP_VEGA20:
1974                 return 0;
1975         case CHIP_NAVI12:
1976                 fw_name_dmcu = FIRMWARE_NAVI12_DMCU;
1977                 break;
1978         case CHIP_RAVEN:
1979                 if (ASICREV_IS_PICASSO(adev->external_rev_id))
1980                         fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
1981                 else if (ASICREV_IS_RAVEN2(adev->external_rev_id))
1982                         fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
1983                 else
1984                         return 0;
1985                 break;
1986         default:
1987                 switch (adev->ip_versions[DCE_HWIP][0]) {
1988                 case IP_VERSION(2, 0, 2):
1989                 case IP_VERSION(2, 0, 3):
1990                 case IP_VERSION(2, 0, 0):
1991                 case IP_VERSION(2, 1, 0):
1992                 case IP_VERSION(3, 0, 0):
1993                 case IP_VERSION(3, 0, 2):
1994                 case IP_VERSION(3, 0, 3):
1995                 case IP_VERSION(3, 0, 1):
1996                 case IP_VERSION(3, 1, 2):
1997                 case IP_VERSION(3, 1, 3):
1998                 case IP_VERSION(3, 1, 4):
1999                 case IP_VERSION(3, 1, 5):
2000                 case IP_VERSION(3, 1, 6):
2001                 case IP_VERSION(3, 2, 0):
2002                 case IP_VERSION(3, 2, 1):
2003                         return 0;
2004                 default:
2005                         break;
2006                 }
2007                 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
2008                 return -EINVAL;
2009         }
2010
2011         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
2012                 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n");
2013                 return 0;
2014         }
2015
2016         r = amdgpu_ucode_request(adev, &adev->dm.fw_dmcu, fw_name_dmcu);
2017         if (r == -ENODEV) {
2018                 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */
2019                 DRM_DEBUG_KMS("dm: DMCU firmware not found\n");
2020                 adev->dm.fw_dmcu = NULL;
2021                 return 0;
2022         }
2023         if (r) {
2024                 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n",
2025                         fw_name_dmcu);
2026                 amdgpu_ucode_release(&adev->dm.fw_dmcu);
2027                 return r;
2028         }
2029
2030         hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data;
2031         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM;
2032         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu;
2033         adev->firmware.fw_size +=
2034                 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
2035
2036         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV;
2037         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu;
2038         adev->firmware.fw_size +=
2039                 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
2040
2041         adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version);
2042
2043         DRM_DEBUG_KMS("PSP loading DMCU firmware\n");
2044
2045         return 0;
2046 }
2047
2048 static uint32_t amdgpu_dm_dmub_reg_read(void *ctx, uint32_t address)
2049 {
2050         struct amdgpu_device *adev = ctx;
2051
2052         return dm_read_reg(adev->dm.dc->ctx, address);
2053 }
2054
2055 static void amdgpu_dm_dmub_reg_write(void *ctx, uint32_t address,
2056                                      uint32_t value)
2057 {
2058         struct amdgpu_device *adev = ctx;
2059
2060         return dm_write_reg(adev->dm.dc->ctx, address, value);
2061 }
2062
2063 static int dm_dmub_sw_init(struct amdgpu_device *adev)
2064 {
2065         struct dmub_srv_create_params create_params;
2066         struct dmub_srv_region_params region_params;
2067         struct dmub_srv_region_info region_info;
2068         struct dmub_srv_fb_params fb_params;
2069         struct dmub_srv_fb_info *fb_info;
2070         struct dmub_srv *dmub_srv;
2071         const struct dmcub_firmware_header_v1_0 *hdr;
2072         enum dmub_asic dmub_asic;
2073         enum dmub_status status;
2074         int r;
2075
2076         switch (adev->ip_versions[DCE_HWIP][0]) {
2077         case IP_VERSION(2, 1, 0):
2078                 dmub_asic = DMUB_ASIC_DCN21;
2079                 break;
2080         case IP_VERSION(3, 0, 0):
2081                 dmub_asic = DMUB_ASIC_DCN30;
2082                 break;
2083         case IP_VERSION(3, 0, 1):
2084                 dmub_asic = DMUB_ASIC_DCN301;
2085                 break;
2086         case IP_VERSION(3, 0, 2):
2087                 dmub_asic = DMUB_ASIC_DCN302;
2088                 break;
2089         case IP_VERSION(3, 0, 3):
2090                 dmub_asic = DMUB_ASIC_DCN303;
2091                 break;
2092         case IP_VERSION(3, 1, 2):
2093         case IP_VERSION(3, 1, 3):
2094                 dmub_asic = (adev->external_rev_id == YELLOW_CARP_B0) ? DMUB_ASIC_DCN31B : DMUB_ASIC_DCN31;
2095                 break;
2096         case IP_VERSION(3, 1, 4):
2097                 dmub_asic = DMUB_ASIC_DCN314;
2098                 break;
2099         case IP_VERSION(3, 1, 5):
2100                 dmub_asic = DMUB_ASIC_DCN315;
2101                 break;
2102         case IP_VERSION(3, 1, 6):
2103                 dmub_asic = DMUB_ASIC_DCN316;
2104                 break;
2105         case IP_VERSION(3, 2, 0):
2106                 dmub_asic = DMUB_ASIC_DCN32;
2107                 break;
2108         case IP_VERSION(3, 2, 1):
2109                 dmub_asic = DMUB_ASIC_DCN321;
2110                 break;
2111         default:
2112                 /* ASIC doesn't support DMUB. */
2113                 return 0;
2114         }
2115
2116         hdr = (const struct dmcub_firmware_header_v1_0 *)adev->dm.dmub_fw->data;
2117         adev->dm.dmcub_fw_version = le32_to_cpu(hdr->header.ucode_version);
2118
2119         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
2120                 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].ucode_id =
2121                         AMDGPU_UCODE_ID_DMCUB;
2122                 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].fw =
2123                         adev->dm.dmub_fw;
2124                 adev->firmware.fw_size +=
2125                         ALIGN(le32_to_cpu(hdr->inst_const_bytes), PAGE_SIZE);
2126
2127                 DRM_INFO("Loading DMUB firmware via PSP: version=0x%08X\n",
2128                          adev->dm.dmcub_fw_version);
2129         }
2130
2131
2132         adev->dm.dmub_srv = kzalloc(sizeof(*adev->dm.dmub_srv), GFP_KERNEL);
2133         dmub_srv = adev->dm.dmub_srv;
2134
2135         if (!dmub_srv) {
2136                 DRM_ERROR("Failed to allocate DMUB service!\n");
2137                 return -ENOMEM;
2138         }
2139
2140         memset(&create_params, 0, sizeof(create_params));
2141         create_params.user_ctx = adev;
2142         create_params.funcs.reg_read = amdgpu_dm_dmub_reg_read;
2143         create_params.funcs.reg_write = amdgpu_dm_dmub_reg_write;
2144         create_params.asic = dmub_asic;
2145
2146         /* Create the DMUB service. */
2147         status = dmub_srv_create(dmub_srv, &create_params);
2148         if (status != DMUB_STATUS_OK) {
2149                 DRM_ERROR("Error creating DMUB service: %d\n", status);
2150                 return -EINVAL;
2151         }
2152
2153         /* Calculate the size of all the regions for the DMUB service. */
2154         memset(&region_params, 0, sizeof(region_params));
2155
2156         region_params.inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
2157                                         PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
2158         region_params.bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
2159         region_params.vbios_size = adev->bios_size;
2160         region_params.fw_bss_data = region_params.bss_data_size ?
2161                 adev->dm.dmub_fw->data +
2162                 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
2163                 le32_to_cpu(hdr->inst_const_bytes) : NULL;
2164         region_params.fw_inst_const =
2165                 adev->dm.dmub_fw->data +
2166                 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
2167                 PSP_HEADER_BYTES;
2168
2169         status = dmub_srv_calc_region_info(dmub_srv, &region_params,
2170                                            &region_info);
2171
2172         if (status != DMUB_STATUS_OK) {
2173                 DRM_ERROR("Error calculating DMUB region info: %d\n", status);
2174                 return -EINVAL;
2175         }
2176
2177         /*
2178          * Allocate a framebuffer based on the total size of all the regions.
2179          * TODO: Move this into GART.
2180          */
2181         r = amdgpu_bo_create_kernel(adev, region_info.fb_size, PAGE_SIZE,
2182                                     AMDGPU_GEM_DOMAIN_VRAM |
2183                                     AMDGPU_GEM_DOMAIN_GTT,
2184                                     &adev->dm.dmub_bo,
2185                                     &adev->dm.dmub_bo_gpu_addr,
2186                                     &adev->dm.dmub_bo_cpu_addr);
2187         if (r)
2188                 return r;
2189
2190         /* Rebase the regions on the framebuffer address. */
2191         memset(&fb_params, 0, sizeof(fb_params));
2192         fb_params.cpu_addr = adev->dm.dmub_bo_cpu_addr;
2193         fb_params.gpu_addr = adev->dm.dmub_bo_gpu_addr;
2194         fb_params.region_info = &region_info;
2195
2196         adev->dm.dmub_fb_info =
2197                 kzalloc(sizeof(*adev->dm.dmub_fb_info), GFP_KERNEL);
2198         fb_info = adev->dm.dmub_fb_info;
2199
2200         if (!fb_info) {
2201                 DRM_ERROR(
2202                         "Failed to allocate framebuffer info for DMUB service!\n");
2203                 return -ENOMEM;
2204         }
2205
2206         status = dmub_srv_calc_fb_info(dmub_srv, &fb_params, fb_info);
2207         if (status != DMUB_STATUS_OK) {
2208                 DRM_ERROR("Error calculating DMUB FB info: %d\n", status);
2209                 return -EINVAL;
2210         }
2211
2212         return 0;
2213 }
2214
2215 static int dm_sw_init(void *handle)
2216 {
2217         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2218         int r;
2219
2220         r = dm_dmub_sw_init(adev);
2221         if (r)
2222                 return r;
2223
2224         return load_dmcu_fw(adev);
2225 }
2226
2227 static int dm_sw_fini(void *handle)
2228 {
2229         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2230
2231         kfree(adev->dm.dmub_fb_info);
2232         adev->dm.dmub_fb_info = NULL;
2233
2234         if (adev->dm.dmub_srv) {
2235                 dmub_srv_destroy(adev->dm.dmub_srv);
2236                 adev->dm.dmub_srv = NULL;
2237         }
2238
2239         amdgpu_ucode_release(&adev->dm.dmub_fw);
2240         amdgpu_ucode_release(&adev->dm.fw_dmcu);
2241
2242         return 0;
2243 }
2244
2245 static int detect_mst_link_for_all_connectors(struct drm_device *dev)
2246 {
2247         struct amdgpu_dm_connector *aconnector;
2248         struct drm_connector *connector;
2249         struct drm_connector_list_iter iter;
2250         int ret = 0;
2251
2252         drm_connector_list_iter_begin(dev, &iter);
2253         drm_for_each_connector_iter(connector, &iter) {
2254                 aconnector = to_amdgpu_dm_connector(connector);
2255                 if (aconnector->dc_link->type == dc_connection_mst_branch &&
2256                     aconnector->mst_mgr.aux) {
2257                         DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
2258                                          aconnector,
2259                                          aconnector->base.base.id);
2260
2261                         ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
2262                         if (ret < 0) {
2263                                 DRM_ERROR("DM_MST: Failed to start MST\n");
2264                                 aconnector->dc_link->type =
2265                                         dc_connection_single;
2266                                 ret = dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,
2267                                                                      aconnector->dc_link);
2268                                 break;
2269                         }
2270                 }
2271         }
2272         drm_connector_list_iter_end(&iter);
2273
2274         return ret;
2275 }
2276
2277 static int dm_late_init(void *handle)
2278 {
2279         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2280
2281         struct dmcu_iram_parameters params;
2282         unsigned int linear_lut[16];
2283         int i;
2284         struct dmcu *dmcu = NULL;
2285
2286         dmcu = adev->dm.dc->res_pool->dmcu;
2287
2288         for (i = 0; i < 16; i++)
2289                 linear_lut[i] = 0xFFFF * i / 15;
2290
2291         params.set = 0;
2292         params.backlight_ramping_override = false;
2293         params.backlight_ramping_start = 0xCCCC;
2294         params.backlight_ramping_reduction = 0xCCCCCCCC;
2295         params.backlight_lut_array_size = 16;
2296         params.backlight_lut_array = linear_lut;
2297
2298         /* Min backlight level after ABM reduction,  Don't allow below 1%
2299          * 0xFFFF x 0.01 = 0x28F
2300          */
2301         params.min_abm_backlight = 0x28F;
2302         /* In the case where abm is implemented on dmcub,
2303         * dmcu object will be null.
2304         * ABM 2.4 and up are implemented on dmcub.
2305         */
2306         if (dmcu) {
2307                 if (!dmcu_load_iram(dmcu, params))
2308                         return -EINVAL;
2309         } else if (adev->dm.dc->ctx->dmub_srv) {
2310                 struct dc_link *edp_links[MAX_NUM_EDP];
2311                 int edp_num;
2312
2313                 dc_get_edp_links(adev->dm.dc, edp_links, &edp_num);
2314                 for (i = 0; i < edp_num; i++) {
2315                         if (!dmub_init_abm_config(adev->dm.dc->res_pool, params, i))
2316                                 return -EINVAL;
2317                 }
2318         }
2319
2320         return detect_mst_link_for_all_connectors(adev_to_drm(adev));
2321 }
2322
2323 static void s3_handle_mst(struct drm_device *dev, bool suspend)
2324 {
2325         struct amdgpu_dm_connector *aconnector;
2326         struct drm_connector *connector;
2327         struct drm_connector_list_iter iter;
2328         struct drm_dp_mst_topology_mgr *mgr;
2329         int ret;
2330         bool need_hotplug = false;
2331
2332         drm_connector_list_iter_begin(dev, &iter);
2333         drm_for_each_connector_iter(connector, &iter) {
2334                 aconnector = to_amdgpu_dm_connector(connector);
2335                 if (aconnector->dc_link->type != dc_connection_mst_branch ||
2336                     aconnector->mst_root)
2337                         continue;
2338
2339                 mgr = &aconnector->mst_mgr;
2340
2341                 if (suspend) {
2342                         drm_dp_mst_topology_mgr_suspend(mgr);
2343                 } else {
2344                         /* if extended timeout is supported in hardware,
2345                          * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer
2346                          * CTS 4.2.1.1 regression introduced by CTS specs requirement update.
2347                          */
2348                         try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD);
2349                         if (!dp_is_lttpr_present(aconnector->dc_link))
2350                                 try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
2351
2352                         ret = drm_dp_mst_topology_mgr_resume(mgr, true);
2353                         if (ret < 0) {
2354                                 dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,
2355                                         aconnector->dc_link);
2356                                 need_hotplug = true;
2357                         }
2358                 }
2359         }
2360         drm_connector_list_iter_end(&iter);
2361
2362         if (need_hotplug)
2363                 drm_kms_helper_hotplug_event(dev);
2364 }
2365
2366 static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev)
2367 {
2368         int ret = 0;
2369
2370         /* This interface is for dGPU Navi1x.Linux dc-pplib interface depends
2371          * on window driver dc implementation.
2372          * For Navi1x, clock settings of dcn watermarks are fixed. the settings
2373          * should be passed to smu during boot up and resume from s3.
2374          * boot up: dc calculate dcn watermark clock settings within dc_create,
2375          * dcn20_resource_construct
2376          * then call pplib functions below to pass the settings to smu:
2377          * smu_set_watermarks_for_clock_ranges
2378          * smu_set_watermarks_table
2379          * navi10_set_watermarks_table
2380          * smu_write_watermarks_table
2381          *
2382          * For Renoir, clock settings of dcn watermark are also fixed values.
2383          * dc has implemented different flow for window driver:
2384          * dc_hardware_init / dc_set_power_state
2385          * dcn10_init_hw
2386          * notify_wm_ranges
2387          * set_wm_ranges
2388          * -- Linux
2389          * smu_set_watermarks_for_clock_ranges
2390          * renoir_set_watermarks_table
2391          * smu_write_watermarks_table
2392          *
2393          * For Linux,
2394          * dc_hardware_init -> amdgpu_dm_init
2395          * dc_set_power_state --> dm_resume
2396          *
2397          * therefore, this function apply to navi10/12/14 but not Renoir
2398          * *
2399          */
2400         switch (adev->ip_versions[DCE_HWIP][0]) {
2401         case IP_VERSION(2, 0, 2):
2402         case IP_VERSION(2, 0, 0):
2403                 break;
2404         default:
2405                 return 0;
2406         }
2407
2408         ret = amdgpu_dpm_write_watermarks_table(adev);
2409         if (ret) {
2410                 DRM_ERROR("Failed to update WMTABLE!\n");
2411                 return ret;
2412         }
2413
2414         return 0;
2415 }
2416
2417 /**
2418  * dm_hw_init() - Initialize DC device
2419  * @handle: The base driver device containing the amdgpu_dm device.
2420  *
2421  * Initialize the &struct amdgpu_display_manager device. This involves calling
2422  * the initializers of each DM component, then populating the struct with them.
2423  *
2424  * Although the function implies hardware initialization, both hardware and
2425  * software are initialized here. Splitting them out to their relevant init
2426  * hooks is a future TODO item.
2427  *
2428  * Some notable things that are initialized here:
2429  *
2430  * - Display Core, both software and hardware
2431  * - DC modules that we need (freesync and color management)
2432  * - DRM software states
2433  * - Interrupt sources and handlers
2434  * - Vblank support
2435  * - Debug FS entries, if enabled
2436  */
2437 static int dm_hw_init(void *handle)
2438 {
2439         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2440         /* Create DAL display manager */
2441         amdgpu_dm_init(adev);
2442         amdgpu_dm_hpd_init(adev);
2443
2444         return 0;
2445 }
2446
2447 /**
2448  * dm_hw_fini() - Teardown DC device
2449  * @handle: The base driver device containing the amdgpu_dm device.
2450  *
2451  * Teardown components within &struct amdgpu_display_manager that require
2452  * cleanup. This involves cleaning up the DRM device, DC, and any modules that
2453  * were loaded. Also flush IRQ workqueues and disable them.
2454  */
2455 static int dm_hw_fini(void *handle)
2456 {
2457         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2458
2459         amdgpu_dm_hpd_fini(adev);
2460
2461         amdgpu_dm_irq_fini(adev);
2462         amdgpu_dm_fini(adev);
2463         return 0;
2464 }
2465
2466
2467 static void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev,
2468                                  struct dc_state *state, bool enable)
2469 {
2470         enum dc_irq_source irq_source;
2471         struct amdgpu_crtc *acrtc;
2472         int rc = -EBUSY;
2473         int i = 0;
2474
2475         for (i = 0; i < state->stream_count; i++) {
2476                 acrtc = get_crtc_by_otg_inst(
2477                                 adev, state->stream_status[i].primary_otg_inst);
2478
2479                 if (acrtc && state->stream_status[i].plane_count != 0) {
2480                         irq_source = IRQ_TYPE_PFLIP + acrtc->otg_inst;
2481                         rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
2482                         DRM_DEBUG_VBL("crtc %d - vupdate irq %sabling: r=%d\n",
2483                                       acrtc->crtc_id, enable ? "en" : "dis", rc);
2484                         if (rc)
2485                                 DRM_WARN("Failed to %s pflip interrupts\n",
2486                                          enable ? "enable" : "disable");
2487
2488                         if (enable) {
2489                                 rc = amdgpu_dm_crtc_enable_vblank(&acrtc->base);
2490                                 if (rc)
2491                                         DRM_WARN("Failed to enable vblank interrupts\n");
2492                         } else {
2493                                 amdgpu_dm_crtc_disable_vblank(&acrtc->base);
2494                         }
2495
2496                 }
2497         }
2498
2499 }
2500
2501 static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc)
2502 {
2503         struct dc_state *context = NULL;
2504         enum dc_status res = DC_ERROR_UNEXPECTED;
2505         int i;
2506         struct dc_stream_state *del_streams[MAX_PIPES];
2507         int del_streams_count = 0;
2508
2509         memset(del_streams, 0, sizeof(del_streams));
2510
2511         context = dc_create_state(dc);
2512         if (context == NULL)
2513                 goto context_alloc_fail;
2514
2515         dc_resource_state_copy_construct_current(dc, context);
2516
2517         /* First remove from context all streams */
2518         for (i = 0; i < context->stream_count; i++) {
2519                 struct dc_stream_state *stream = context->streams[i];
2520
2521                 del_streams[del_streams_count++] = stream;
2522         }
2523
2524         /* Remove all planes for removed streams and then remove the streams */
2525         for (i = 0; i < del_streams_count; i++) {
2526                 if (!dc_rem_all_planes_for_stream(dc, del_streams[i], context)) {
2527                         res = DC_FAIL_DETACH_SURFACES;
2528                         goto fail;
2529                 }
2530
2531                 res = dc_remove_stream_from_ctx(dc, context, del_streams[i]);
2532                 if (res != DC_OK)
2533                         goto fail;
2534         }
2535
2536         res = dc_commit_streams(dc, context->streams, context->stream_count);
2537
2538 fail:
2539         dc_release_state(context);
2540
2541 context_alloc_fail:
2542         return res;
2543 }
2544
2545 static void hpd_rx_irq_work_suspend(struct amdgpu_display_manager *dm)
2546 {
2547         int i;
2548
2549         if (dm->hpd_rx_offload_wq) {
2550                 for (i = 0; i < dm->dc->caps.max_links; i++)
2551                         flush_workqueue(dm->hpd_rx_offload_wq[i].wq);
2552         }
2553 }
2554
2555 static int dm_suspend(void *handle)
2556 {
2557         struct amdgpu_device *adev = handle;
2558         struct amdgpu_display_manager *dm = &adev->dm;
2559         int ret = 0;
2560
2561         if (amdgpu_in_reset(adev)) {
2562                 mutex_lock(&dm->dc_lock);
2563
2564                 dc_allow_idle_optimizations(adev->dm.dc, false);
2565
2566                 dm->cached_dc_state = dc_copy_state(dm->dc->current_state);
2567
2568                 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false);
2569
2570                 amdgpu_dm_commit_zero_streams(dm->dc);
2571
2572                 amdgpu_dm_irq_suspend(adev);
2573
2574                 hpd_rx_irq_work_suspend(dm);
2575
2576                 return ret;
2577         }
2578
2579         WARN_ON(adev->dm.cached_state);
2580         adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev));
2581
2582         s3_handle_mst(adev_to_drm(adev), true);
2583
2584         amdgpu_dm_irq_suspend(adev);
2585
2586         hpd_rx_irq_work_suspend(dm);
2587
2588         dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
2589
2590         return 0;
2591 }
2592
2593 struct amdgpu_dm_connector *
2594 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
2595                                              struct drm_crtc *crtc)
2596 {
2597         u32 i;
2598         struct drm_connector_state *new_con_state;
2599         struct drm_connector *connector;
2600         struct drm_crtc *crtc_from_state;
2601
2602         for_each_new_connector_in_state(state, connector, new_con_state, i) {
2603                 crtc_from_state = new_con_state->crtc;
2604
2605                 if (crtc_from_state == crtc)
2606                         return to_amdgpu_dm_connector(connector);
2607         }
2608
2609         return NULL;
2610 }
2611
2612 static void emulated_link_detect(struct dc_link *link)
2613 {
2614         struct dc_sink_init_data sink_init_data = { 0 };
2615         struct display_sink_capability sink_caps = { 0 };
2616         enum dc_edid_status edid_status;
2617         struct dc_context *dc_ctx = link->ctx;
2618         struct dc_sink *sink = NULL;
2619         struct dc_sink *prev_sink = NULL;
2620
2621         link->type = dc_connection_none;
2622         prev_sink = link->local_sink;
2623
2624         if (prev_sink)
2625                 dc_sink_release(prev_sink);
2626
2627         switch (link->connector_signal) {
2628         case SIGNAL_TYPE_HDMI_TYPE_A: {
2629                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2630                 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
2631                 break;
2632         }
2633
2634         case SIGNAL_TYPE_DVI_SINGLE_LINK: {
2635                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2636                 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
2637                 break;
2638         }
2639
2640         case SIGNAL_TYPE_DVI_DUAL_LINK: {
2641                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2642                 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
2643                 break;
2644         }
2645
2646         case SIGNAL_TYPE_LVDS: {
2647                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2648                 sink_caps.signal = SIGNAL_TYPE_LVDS;
2649                 break;
2650         }
2651
2652         case SIGNAL_TYPE_EDP: {
2653                 sink_caps.transaction_type =
2654                         DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
2655                 sink_caps.signal = SIGNAL_TYPE_EDP;
2656                 break;
2657         }
2658
2659         case SIGNAL_TYPE_DISPLAY_PORT: {
2660                 sink_caps.transaction_type =
2661                         DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
2662                 sink_caps.signal = SIGNAL_TYPE_VIRTUAL;
2663                 break;
2664         }
2665
2666         default:
2667                 DC_ERROR("Invalid connector type! signal:%d\n",
2668                         link->connector_signal);
2669                 return;
2670         }
2671
2672         sink_init_data.link = link;
2673         sink_init_data.sink_signal = sink_caps.signal;
2674
2675         sink = dc_sink_create(&sink_init_data);
2676         if (!sink) {
2677                 DC_ERROR("Failed to create sink!\n");
2678                 return;
2679         }
2680
2681         /* dc_sink_create returns a new reference */
2682         link->local_sink = sink;
2683
2684         edid_status = dm_helpers_read_local_edid(
2685                         link->ctx,
2686                         link,
2687                         sink);
2688
2689         if (edid_status != EDID_OK)
2690                 DC_ERROR("Failed to read EDID");
2691
2692 }
2693
2694 static void dm_gpureset_commit_state(struct dc_state *dc_state,
2695                                      struct amdgpu_display_manager *dm)
2696 {
2697         struct {
2698                 struct dc_surface_update surface_updates[MAX_SURFACES];
2699                 struct dc_plane_info plane_infos[MAX_SURFACES];
2700                 struct dc_scaling_info scaling_infos[MAX_SURFACES];
2701                 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
2702                 struct dc_stream_update stream_update;
2703         } * bundle;
2704         int k, m;
2705
2706         bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
2707
2708         if (!bundle) {
2709                 dm_error("Failed to allocate update bundle\n");
2710                 goto cleanup;
2711         }
2712
2713         for (k = 0; k < dc_state->stream_count; k++) {
2714                 bundle->stream_update.stream = dc_state->streams[k];
2715
2716                 for (m = 0; m < dc_state->stream_status->plane_count; m++) {
2717                         bundle->surface_updates[m].surface =
2718                                 dc_state->stream_status->plane_states[m];
2719                         bundle->surface_updates[m].surface->force_full_update =
2720                                 true;
2721                 }
2722
2723                 update_planes_and_stream_adapter(dm->dc,
2724                                          UPDATE_TYPE_FULL,
2725                                          dc_state->stream_status->plane_count,
2726                                          dc_state->streams[k],
2727                                          &bundle->stream_update,
2728                                          bundle->surface_updates);
2729         }
2730
2731 cleanup:
2732         kfree(bundle);
2733
2734         return;
2735 }
2736
2737 static int dm_resume(void *handle)
2738 {
2739         struct amdgpu_device *adev = handle;
2740         struct drm_device *ddev = adev_to_drm(adev);
2741         struct amdgpu_display_manager *dm = &adev->dm;
2742         struct amdgpu_dm_connector *aconnector;
2743         struct drm_connector *connector;
2744         struct drm_connector_list_iter iter;
2745         struct drm_crtc *crtc;
2746         struct drm_crtc_state *new_crtc_state;
2747         struct dm_crtc_state *dm_new_crtc_state;
2748         struct drm_plane *plane;
2749         struct drm_plane_state *new_plane_state;
2750         struct dm_plane_state *dm_new_plane_state;
2751         struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state);
2752         enum dc_connection_type new_connection_type = dc_connection_none;
2753         struct dc_state *dc_state;
2754         int i, r, j;
2755
2756         if (amdgpu_in_reset(adev)) {
2757                 dc_state = dm->cached_dc_state;
2758
2759                 /*
2760                  * The dc->current_state is backed up into dm->cached_dc_state
2761                  * before we commit 0 streams.
2762                  *
2763                  * DC will clear link encoder assignments on the real state
2764                  * but the changes won't propagate over to the copy we made
2765                  * before the 0 streams commit.
2766                  *
2767                  * DC expects that link encoder assignments are *not* valid
2768                  * when committing a state, so as a workaround we can copy
2769                  * off of the current state.
2770                  *
2771                  * We lose the previous assignments, but we had already
2772                  * commit 0 streams anyway.
2773                  */
2774                 link_enc_cfg_copy(adev->dm.dc->current_state, dc_state);
2775
2776                 r = dm_dmub_hw_init(adev);
2777                 if (r)
2778                         DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
2779
2780                 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
2781                 dc_resume(dm->dc);
2782
2783                 amdgpu_dm_irq_resume_early(adev);
2784
2785                 for (i = 0; i < dc_state->stream_count; i++) {
2786                         dc_state->streams[i]->mode_changed = true;
2787                         for (j = 0; j < dc_state->stream_status[i].plane_count; j++) {
2788                                 dc_state->stream_status[i].plane_states[j]->update_flags.raw
2789                                         = 0xffffffff;
2790                         }
2791                 }
2792
2793                 if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
2794                         amdgpu_dm_outbox_init(adev);
2795                         dc_enable_dmub_outbox(adev->dm.dc);
2796                 }
2797
2798                 WARN_ON(!dc_commit_streams(dm->dc, dc_state->streams, dc_state->stream_count));
2799
2800                 dm_gpureset_commit_state(dm->cached_dc_state, dm);
2801
2802                 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, true);
2803
2804                 dc_release_state(dm->cached_dc_state);
2805                 dm->cached_dc_state = NULL;
2806
2807                 amdgpu_dm_irq_resume_late(adev);
2808
2809                 mutex_unlock(&dm->dc_lock);
2810
2811                 return 0;
2812         }
2813         /* Recreate dc_state - DC invalidates it when setting power state to S3. */
2814         dc_release_state(dm_state->context);
2815         dm_state->context = dc_create_state(dm->dc);
2816         /* TODO: Remove dc_state->dccg, use dc->dccg directly. */
2817         dc_resource_state_construct(dm->dc, dm_state->context);
2818
2819         /* Before powering on DC we need to re-initialize DMUB. */
2820         dm_dmub_hw_resume(adev);
2821
2822         /* Re-enable outbox interrupts for DPIA. */
2823         if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
2824                 amdgpu_dm_outbox_init(adev);
2825                 dc_enable_dmub_outbox(adev->dm.dc);
2826         }
2827
2828         /* power on hardware */
2829         dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
2830
2831         /* program HPD filter */
2832         dc_resume(dm->dc);
2833
2834         /*
2835          * early enable HPD Rx IRQ, should be done before set mode as short
2836          * pulse interrupts are used for MST
2837          */
2838         amdgpu_dm_irq_resume_early(adev);
2839
2840         /* On resume we need to rewrite the MSTM control bits to enable MST*/
2841         s3_handle_mst(ddev, false);
2842
2843         /* Do detection*/
2844         drm_connector_list_iter_begin(ddev, &iter);
2845         drm_for_each_connector_iter(connector, &iter) {
2846                 aconnector = to_amdgpu_dm_connector(connector);
2847
2848                 if (!aconnector->dc_link)
2849                         continue;
2850
2851                 /*
2852                  * this is the case when traversing through already created
2853                  * MST connectors, should be skipped
2854                  */
2855                 if (aconnector->dc_link->type == dc_connection_mst_branch)
2856                         continue;
2857
2858                 mutex_lock(&aconnector->hpd_lock);
2859                 if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type))
2860                         DRM_ERROR("KMS: Failed to detect connector\n");
2861
2862                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
2863                         emulated_link_detect(aconnector->dc_link);
2864                 } else {
2865                         mutex_lock(&dm->dc_lock);
2866                         dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
2867                         mutex_unlock(&dm->dc_lock);
2868                 }
2869
2870                 if (aconnector->fake_enable && aconnector->dc_link->local_sink)
2871                         aconnector->fake_enable = false;
2872
2873                 if (aconnector->dc_sink)
2874                         dc_sink_release(aconnector->dc_sink);
2875                 aconnector->dc_sink = NULL;
2876                 amdgpu_dm_update_connector_after_detect(aconnector);
2877                 mutex_unlock(&aconnector->hpd_lock);
2878         }
2879         drm_connector_list_iter_end(&iter);
2880
2881         /* Force mode set in atomic commit */
2882         for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)
2883                 new_crtc_state->active_changed = true;
2884
2885         /*
2886          * atomic_check is expected to create the dc states. We need to release
2887          * them here, since they were duplicated as part of the suspend
2888          * procedure.
2889          */
2890         for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {
2891                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
2892                 if (dm_new_crtc_state->stream) {
2893                         WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
2894                         dc_stream_release(dm_new_crtc_state->stream);
2895                         dm_new_crtc_state->stream = NULL;
2896                 }
2897         }
2898
2899         for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) {
2900                 dm_new_plane_state = to_dm_plane_state(new_plane_state);
2901                 if (dm_new_plane_state->dc_state) {
2902                         WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
2903                         dc_plane_state_release(dm_new_plane_state->dc_state);
2904                         dm_new_plane_state->dc_state = NULL;
2905                 }
2906         }
2907
2908         drm_atomic_helper_resume(ddev, dm->cached_state);
2909
2910         dm->cached_state = NULL;
2911
2912         amdgpu_dm_irq_resume_late(adev);
2913
2914         amdgpu_dm_smu_write_watermarks_table(adev);
2915
2916         return 0;
2917 }
2918
2919 /**
2920  * DOC: DM Lifecycle
2921  *
2922  * DM (and consequently DC) is registered in the amdgpu base driver as a IP
2923  * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to
2924  * the base driver's device list to be initialized and torn down accordingly.
2925  *
2926  * The functions to do so are provided as hooks in &struct amd_ip_funcs.
2927  */
2928
2929 static const struct amd_ip_funcs amdgpu_dm_funcs = {
2930         .name = "dm",
2931         .early_init = dm_early_init,
2932         .late_init = dm_late_init,
2933         .sw_init = dm_sw_init,
2934         .sw_fini = dm_sw_fini,
2935         .early_fini = amdgpu_dm_early_fini,
2936         .hw_init = dm_hw_init,
2937         .hw_fini = dm_hw_fini,
2938         .suspend = dm_suspend,
2939         .resume = dm_resume,
2940         .is_idle = dm_is_idle,
2941         .wait_for_idle = dm_wait_for_idle,
2942         .check_soft_reset = dm_check_soft_reset,
2943         .soft_reset = dm_soft_reset,
2944         .set_clockgating_state = dm_set_clockgating_state,
2945         .set_powergating_state = dm_set_powergating_state,
2946 };
2947
2948 const struct amdgpu_ip_block_version dm_ip_block =
2949 {
2950         .type = AMD_IP_BLOCK_TYPE_DCE,
2951         .major = 1,
2952         .minor = 0,
2953         .rev = 0,
2954         .funcs = &amdgpu_dm_funcs,
2955 };
2956
2957
2958 /**
2959  * DOC: atomic
2960  *
2961  * *WIP*
2962  */
2963
2964 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
2965         .fb_create = amdgpu_display_user_framebuffer_create,
2966         .get_format_info = amdgpu_dm_plane_get_format_info,
2967         .atomic_check = amdgpu_dm_atomic_check,
2968         .atomic_commit = drm_atomic_helper_commit,
2969 };
2970
2971 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
2972         .atomic_commit_tail = amdgpu_dm_atomic_commit_tail,
2973         .atomic_commit_setup = drm_dp_mst_atomic_setup_commit,
2974 };
2975
2976 static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector)
2977 {
2978         struct amdgpu_dm_backlight_caps *caps;
2979         struct amdgpu_display_manager *dm;
2980         struct drm_connector *conn_base;
2981         struct amdgpu_device *adev;
2982         struct dc_link *link = NULL;
2983         struct drm_luminance_range_info *luminance_range;
2984         int i;
2985
2986         if (!aconnector || !aconnector->dc_link)
2987                 return;
2988
2989         link = aconnector->dc_link;
2990         if (link->connector_signal != SIGNAL_TYPE_EDP)
2991                 return;
2992
2993         conn_base = &aconnector->base;
2994         adev = drm_to_adev(conn_base->dev);
2995         dm = &adev->dm;
2996         for (i = 0; i < dm->num_of_edps; i++) {
2997                 if (link == dm->backlight_link[i])
2998                         break;
2999         }
3000         if (i >= dm->num_of_edps)
3001                 return;
3002         caps = &dm->backlight_caps[i];
3003         caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps;
3004         caps->aux_support = false;
3005
3006         if (caps->ext_caps->bits.oled == 1 /*||
3007             caps->ext_caps->bits.sdr_aux_backlight_control == 1 ||
3008             caps->ext_caps->bits.hdr_aux_backlight_control == 1*/)
3009                 caps->aux_support = true;
3010
3011         if (amdgpu_backlight == 0)
3012                 caps->aux_support = false;
3013         else if (amdgpu_backlight == 1)
3014                 caps->aux_support = true;
3015
3016         luminance_range = &conn_base->display_info.luminance_range;
3017
3018         if (luminance_range->max_luminance) {
3019                 caps->aux_min_input_signal = luminance_range->min_luminance;
3020                 caps->aux_max_input_signal = luminance_range->max_luminance;
3021         } else {
3022                 caps->aux_min_input_signal = 0;
3023                 caps->aux_max_input_signal = 512;
3024         }
3025 }
3026
3027 void amdgpu_dm_update_connector_after_detect(
3028                 struct amdgpu_dm_connector *aconnector)
3029 {
3030         struct drm_connector *connector = &aconnector->base;
3031         struct drm_device *dev = connector->dev;
3032         struct dc_sink *sink;
3033
3034         /* MST handled by drm_mst framework */
3035         if (aconnector->mst_mgr.mst_state == true)
3036                 return;
3037
3038         sink = aconnector->dc_link->local_sink;
3039         if (sink)
3040                 dc_sink_retain(sink);
3041
3042         /*
3043          * Edid mgmt connector gets first update only in mode_valid hook and then
3044          * the connector sink is set to either fake or physical sink depends on link status.
3045          * Skip if already done during boot.
3046          */
3047         if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
3048                         && aconnector->dc_em_sink) {
3049
3050                 /*
3051                  * For S3 resume with headless use eml_sink to fake stream
3052                  * because on resume connector->sink is set to NULL
3053                  */
3054                 mutex_lock(&dev->mode_config.mutex);
3055
3056                 if (sink) {
3057                         if (aconnector->dc_sink) {
3058                                 amdgpu_dm_update_freesync_caps(connector, NULL);
3059                                 /*
3060                                  * retain and release below are used to
3061                                  * bump up refcount for sink because the link doesn't point
3062                                  * to it anymore after disconnect, so on next crtc to connector
3063                                  * reshuffle by UMD we will get into unwanted dc_sink release
3064                                  */
3065                                 dc_sink_release(aconnector->dc_sink);
3066                         }
3067                         aconnector->dc_sink = sink;
3068                         dc_sink_retain(aconnector->dc_sink);
3069                         amdgpu_dm_update_freesync_caps(connector,
3070                                         aconnector->edid);
3071                 } else {
3072                         amdgpu_dm_update_freesync_caps(connector, NULL);
3073                         if (!aconnector->dc_sink) {
3074                                 aconnector->dc_sink = aconnector->dc_em_sink;
3075                                 dc_sink_retain(aconnector->dc_sink);
3076                         }
3077                 }
3078
3079                 mutex_unlock(&dev->mode_config.mutex);
3080
3081                 if (sink)
3082                         dc_sink_release(sink);
3083                 return;
3084         }
3085
3086         /*
3087          * TODO: temporary guard to look for proper fix
3088          * if this sink is MST sink, we should not do anything
3089          */
3090         if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
3091                 dc_sink_release(sink);
3092                 return;
3093         }
3094
3095         if (aconnector->dc_sink == sink) {
3096                 /*
3097                  * We got a DP short pulse (Link Loss, DP CTS, etc...).
3098                  * Do nothing!!
3099                  */
3100                 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
3101                                 aconnector->connector_id);
3102                 if (sink)
3103                         dc_sink_release(sink);
3104                 return;
3105         }
3106
3107         DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
3108                 aconnector->connector_id, aconnector->dc_sink, sink);
3109
3110         mutex_lock(&dev->mode_config.mutex);
3111
3112         /*
3113          * 1. Update status of the drm connector
3114          * 2. Send an event and let userspace tell us what to do
3115          */
3116         if (sink) {
3117                 /*
3118                  * TODO: check if we still need the S3 mode update workaround.
3119                  * If yes, put it here.
3120                  */
3121                 if (aconnector->dc_sink) {
3122                         amdgpu_dm_update_freesync_caps(connector, NULL);
3123                         dc_sink_release(aconnector->dc_sink);
3124                 }
3125
3126                 aconnector->dc_sink = sink;
3127                 dc_sink_retain(aconnector->dc_sink);
3128                 if (sink->dc_edid.length == 0) {
3129                         aconnector->edid = NULL;
3130                         if (aconnector->dc_link->aux_mode) {
3131                                 drm_dp_cec_unset_edid(
3132                                         &aconnector->dm_dp_aux.aux);
3133                         }
3134                 } else {
3135                         aconnector->edid =
3136                                 (struct edid *)sink->dc_edid.raw_edid;
3137
3138                         if (aconnector->dc_link->aux_mode)
3139                                 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,
3140                                                     aconnector->edid);
3141                 }
3142
3143                 aconnector->timing_requested = kzalloc(sizeof(struct dc_crtc_timing), GFP_KERNEL);
3144                 if (!aconnector->timing_requested)
3145                         dm_error("%s: failed to create aconnector->requested_timing\n", __func__);
3146
3147                 drm_connector_update_edid_property(connector, aconnector->edid);
3148                 amdgpu_dm_update_freesync_caps(connector, aconnector->edid);
3149                 update_connector_ext_caps(aconnector);
3150         } else {
3151                 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
3152                 amdgpu_dm_update_freesync_caps(connector, NULL);
3153                 drm_connector_update_edid_property(connector, NULL);
3154                 aconnector->num_modes = 0;
3155                 dc_sink_release(aconnector->dc_sink);
3156                 aconnector->dc_sink = NULL;
3157                 aconnector->edid = NULL;
3158                 kfree(aconnector->timing_requested);
3159                 aconnector->timing_requested = NULL;
3160                 /* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */
3161                 if (connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
3162                         connector->state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
3163         }
3164
3165         mutex_unlock(&dev->mode_config.mutex);
3166
3167         update_subconnector_property(aconnector);
3168
3169         if (sink)
3170                 dc_sink_release(sink);
3171 }
3172
3173 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector)
3174 {
3175         struct drm_connector *connector = &aconnector->base;
3176         struct drm_device *dev = connector->dev;
3177         enum dc_connection_type new_connection_type = dc_connection_none;
3178         struct amdgpu_device *adev = drm_to_adev(dev);
3179         struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
3180         bool ret = false;
3181
3182         if (adev->dm.disable_hpd_irq)
3183                 return;
3184
3185         /*
3186          * In case of failure or MST no need to update connector status or notify the OS
3187          * since (for MST case) MST does this in its own context.
3188          */
3189         mutex_lock(&aconnector->hpd_lock);
3190
3191         if (adev->dm.hdcp_workqueue) {
3192                 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
3193                 dm_con_state->update_hdcp = true;
3194         }
3195         if (aconnector->fake_enable)
3196                 aconnector->fake_enable = false;
3197
3198         aconnector->timing_changed = false;
3199
3200         if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type))
3201                 DRM_ERROR("KMS: Failed to detect connector\n");
3202
3203         if (aconnector->base.force && new_connection_type == dc_connection_none) {
3204                 emulated_link_detect(aconnector->dc_link);
3205
3206                 drm_modeset_lock_all(dev);
3207                 dm_restore_drm_connector_state(dev, connector);
3208                 drm_modeset_unlock_all(dev);
3209
3210                 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
3211                         drm_kms_helper_connector_hotplug_event(connector);
3212         } else {
3213                 mutex_lock(&adev->dm.dc_lock);
3214                 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
3215                 mutex_unlock(&adev->dm.dc_lock);
3216                 if (ret) {
3217                         amdgpu_dm_update_connector_after_detect(aconnector);
3218
3219                         drm_modeset_lock_all(dev);
3220                         dm_restore_drm_connector_state(dev, connector);
3221                         drm_modeset_unlock_all(dev);
3222
3223                         if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
3224                                 drm_kms_helper_connector_hotplug_event(connector);
3225                 }
3226         }
3227         mutex_unlock(&aconnector->hpd_lock);
3228
3229 }
3230
3231 static void handle_hpd_irq(void *param)
3232 {
3233         struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
3234
3235         handle_hpd_irq_helper(aconnector);
3236
3237 }
3238
3239 static void dm_handle_mst_sideband_msg(struct amdgpu_dm_connector *aconnector)
3240 {
3241         u8 esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
3242         u8 dret;
3243         bool new_irq_handled = false;
3244         int dpcd_addr;
3245         int dpcd_bytes_to_read;
3246
3247         const int max_process_count = 30;
3248         int process_count = 0;
3249
3250         const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
3251
3252         if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
3253                 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
3254                 /* DPCD 0x200 - 0x201 for downstream IRQ */
3255                 dpcd_addr = DP_SINK_COUNT;
3256         } else {
3257                 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
3258                 /* DPCD 0x2002 - 0x2005 for downstream IRQ */
3259                 dpcd_addr = DP_SINK_COUNT_ESI;
3260         }
3261
3262         dret = drm_dp_dpcd_read(
3263                 &aconnector->dm_dp_aux.aux,
3264                 dpcd_addr,
3265                 esi,
3266                 dpcd_bytes_to_read);
3267
3268         while (dret == dpcd_bytes_to_read &&
3269                 process_count < max_process_count) {
3270                 u8 retry;
3271                 dret = 0;
3272
3273                 process_count++;
3274
3275                 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3276                 /* handle HPD short pulse irq */
3277                 if (aconnector->mst_mgr.mst_state)
3278                         drm_dp_mst_hpd_irq(
3279                                 &aconnector->mst_mgr,
3280                                 esi,
3281                                 &new_irq_handled);
3282
3283                 if (new_irq_handled) {
3284                         /* ACK at DPCD to notify down stream */
3285                         const int ack_dpcd_bytes_to_write =
3286                                 dpcd_bytes_to_read - 1;
3287
3288                         for (retry = 0; retry < 3; retry++) {
3289                                 u8 wret;
3290
3291                                 wret = drm_dp_dpcd_write(
3292                                         &aconnector->dm_dp_aux.aux,
3293                                         dpcd_addr + 1,
3294                                         &esi[1],
3295                                         ack_dpcd_bytes_to_write);
3296                                 if (wret == ack_dpcd_bytes_to_write)
3297                                         break;
3298                         }
3299
3300                         /* check if there is new irq to be handled */
3301                         dret = drm_dp_dpcd_read(
3302                                 &aconnector->dm_dp_aux.aux,
3303                                 dpcd_addr,
3304                                 esi,
3305                                 dpcd_bytes_to_read);
3306
3307                         new_irq_handled = false;
3308                 } else {
3309                         break;
3310                 }
3311         }
3312
3313         if (process_count == max_process_count)
3314                 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
3315 }
3316
3317 static void schedule_hpd_rx_offload_work(struct hpd_rx_irq_offload_work_queue *offload_wq,
3318                                                         union hpd_irq_data hpd_irq_data)
3319 {
3320         struct hpd_rx_irq_offload_work *offload_work =
3321                                 kzalloc(sizeof(*offload_work), GFP_KERNEL);
3322
3323         if (!offload_work) {
3324                 DRM_ERROR("Failed to allocate hpd_rx_irq_offload_work.\n");
3325                 return;
3326         }
3327
3328         INIT_WORK(&offload_work->work, dm_handle_hpd_rx_offload_work);
3329         offload_work->data = hpd_irq_data;
3330         offload_work->offload_wq = offload_wq;
3331
3332         queue_work(offload_wq->wq, &offload_work->work);
3333         DRM_DEBUG_KMS("queue work to handle hpd_rx offload work");
3334 }
3335
3336 static void handle_hpd_rx_irq(void *param)
3337 {
3338         struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
3339         struct drm_connector *connector = &aconnector->base;
3340         struct drm_device *dev = connector->dev;
3341         struct dc_link *dc_link = aconnector->dc_link;
3342         bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
3343         bool result = false;
3344         enum dc_connection_type new_connection_type = dc_connection_none;
3345         struct amdgpu_device *adev = drm_to_adev(dev);
3346         union hpd_irq_data hpd_irq_data;
3347         bool link_loss = false;
3348         bool has_left_work = false;
3349         int idx = dc_link->link_index;
3350         struct hpd_rx_irq_offload_work_queue *offload_wq = &adev->dm.hpd_rx_offload_wq[idx];
3351
3352         memset(&hpd_irq_data, 0, sizeof(hpd_irq_data));
3353
3354         if (adev->dm.disable_hpd_irq)
3355                 return;
3356
3357         /*
3358          * TODO:Temporary add mutex to protect hpd interrupt not have a gpio
3359          * conflict, after implement i2c helper, this mutex should be
3360          * retired.
3361          */
3362         mutex_lock(&aconnector->hpd_lock);
3363
3364         result = dc_link_handle_hpd_rx_irq(dc_link, &hpd_irq_data,
3365                                                 &link_loss, true, &has_left_work);
3366
3367         if (!has_left_work)
3368                 goto out;
3369
3370         if (hpd_irq_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
3371                 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3372                 goto out;
3373         }
3374
3375         if (dc_link_dp_allow_hpd_rx_irq(dc_link)) {
3376                 if (hpd_irq_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY ||
3377                         hpd_irq_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) {
3378                         dm_handle_mst_sideband_msg(aconnector);
3379                         goto out;
3380                 }
3381
3382                 if (link_loss) {
3383                         bool skip = false;
3384
3385                         spin_lock(&offload_wq->offload_lock);
3386                         skip = offload_wq->is_handling_link_loss;
3387
3388                         if (!skip)
3389                                 offload_wq->is_handling_link_loss = true;
3390
3391                         spin_unlock(&offload_wq->offload_lock);
3392
3393                         if (!skip)
3394                                 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3395
3396                         goto out;
3397                 }
3398         }
3399
3400 out:
3401         if (result && !is_mst_root_connector) {
3402                 /* Downstream Port status changed. */
3403                 if (!dc_link_detect_connection_type(dc_link, &new_connection_type))
3404                         DRM_ERROR("KMS: Failed to detect connector\n");
3405
3406                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
3407                         emulated_link_detect(dc_link);
3408
3409                         if (aconnector->fake_enable)
3410                                 aconnector->fake_enable = false;
3411
3412                         amdgpu_dm_update_connector_after_detect(aconnector);
3413
3414
3415                         drm_modeset_lock_all(dev);
3416                         dm_restore_drm_connector_state(dev, connector);
3417                         drm_modeset_unlock_all(dev);
3418
3419                         drm_kms_helper_connector_hotplug_event(connector);
3420                 } else {
3421                         bool ret = false;
3422
3423                         mutex_lock(&adev->dm.dc_lock);
3424                         ret = dc_link_detect(dc_link, DETECT_REASON_HPDRX);
3425                         mutex_unlock(&adev->dm.dc_lock);
3426
3427                         if (ret) {
3428                                 if (aconnector->fake_enable)
3429                                         aconnector->fake_enable = false;
3430
3431                                 amdgpu_dm_update_connector_after_detect(aconnector);
3432
3433                                 drm_modeset_lock_all(dev);
3434                                 dm_restore_drm_connector_state(dev, connector);
3435                                 drm_modeset_unlock_all(dev);
3436
3437                                 drm_kms_helper_connector_hotplug_event(connector);
3438                         }
3439                 }
3440         }
3441         if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ) {
3442                 if (adev->dm.hdcp_workqueue)
3443                         hdcp_handle_cpirq(adev->dm.hdcp_workqueue,  aconnector->base.index);
3444         }
3445
3446         if (dc_link->type != dc_connection_mst_branch)
3447                 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux);
3448
3449         mutex_unlock(&aconnector->hpd_lock);
3450 }
3451
3452 static void register_hpd_handlers(struct amdgpu_device *adev)
3453 {
3454         struct drm_device *dev = adev_to_drm(adev);
3455         struct drm_connector *connector;
3456         struct amdgpu_dm_connector *aconnector;
3457         const struct dc_link *dc_link;
3458         struct dc_interrupt_params int_params = {0};
3459
3460         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3461         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3462
3463         list_for_each_entry(connector,
3464                         &dev->mode_config.connector_list, head) {
3465
3466                 aconnector = to_amdgpu_dm_connector(connector);
3467                 dc_link = aconnector->dc_link;
3468
3469                 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
3470                         int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3471                         int_params.irq_source = dc_link->irq_source_hpd;
3472
3473                         amdgpu_dm_irq_register_interrupt(adev, &int_params,
3474                                         handle_hpd_irq,
3475                                         (void *) aconnector);
3476                 }
3477
3478                 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
3479
3480                         /* Also register for DP short pulse (hpd_rx). */
3481                         int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3482                         int_params.irq_source = dc_link->irq_source_hpd_rx;
3483
3484                         amdgpu_dm_irq_register_interrupt(adev, &int_params,
3485                                         handle_hpd_rx_irq,
3486                                         (void *) aconnector);
3487
3488                         if (adev->dm.hpd_rx_offload_wq)
3489                                 adev->dm.hpd_rx_offload_wq[dc_link->link_index].aconnector =
3490                                         aconnector;
3491                 }
3492         }
3493 }
3494
3495 #if defined(CONFIG_DRM_AMD_DC_SI)
3496 /* Register IRQ sources and initialize IRQ callbacks */
3497 static int dce60_register_irq_handlers(struct amdgpu_device *adev)
3498 {
3499         struct dc *dc = adev->dm.dc;
3500         struct common_irq_params *c_irq_params;
3501         struct dc_interrupt_params int_params = {0};
3502         int r;
3503         int i;
3504         unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
3505
3506         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3507         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3508
3509         /*
3510          * Actions of amdgpu_irq_add_id():
3511          * 1. Register a set() function with base driver.
3512          *    Base driver will call set() function to enable/disable an
3513          *    interrupt in DC hardware.
3514          * 2. Register amdgpu_dm_irq_handler().
3515          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3516          *    coming from DC hardware.
3517          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3518          *    for acknowledging and handling. */
3519
3520         /* Use VBLANK interrupt */
3521         for (i = 0; i < adev->mode_info.num_crtc; i++) {
3522                 r = amdgpu_irq_add_id(adev, client_id, i+1 , &adev->crtc_irq);
3523                 if (r) {
3524                         DRM_ERROR("Failed to add crtc irq id!\n");
3525                         return r;
3526                 }
3527
3528                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3529                 int_params.irq_source =
3530                         dc_interrupt_to_irq_source(dc, i+1 , 0);
3531
3532                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3533
3534                 c_irq_params->adev = adev;
3535                 c_irq_params->irq_src = int_params.irq_source;
3536
3537                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3538                                 dm_crtc_high_irq, c_irq_params);
3539         }
3540
3541         /* Use GRPH_PFLIP interrupt */
3542         for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
3543                         i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
3544                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
3545                 if (r) {
3546                         DRM_ERROR("Failed to add page flip irq id!\n");
3547                         return r;
3548                 }
3549
3550                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3551                 int_params.irq_source =
3552                         dc_interrupt_to_irq_source(dc, i, 0);
3553
3554                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3555
3556                 c_irq_params->adev = adev;
3557                 c_irq_params->irq_src = int_params.irq_source;
3558
3559                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3560                                 dm_pflip_high_irq, c_irq_params);
3561
3562         }
3563
3564         /* HPD */
3565         r = amdgpu_irq_add_id(adev, client_id,
3566                         VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
3567         if (r) {
3568                 DRM_ERROR("Failed to add hpd irq id!\n");
3569                 return r;
3570         }
3571
3572         register_hpd_handlers(adev);
3573
3574         return 0;
3575 }
3576 #endif
3577
3578 /* Register IRQ sources and initialize IRQ callbacks */
3579 static int dce110_register_irq_handlers(struct amdgpu_device *adev)
3580 {
3581         struct dc *dc = adev->dm.dc;
3582         struct common_irq_params *c_irq_params;
3583         struct dc_interrupt_params int_params = {0};
3584         int r;
3585         int i;
3586         unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
3587
3588         if (adev->family >= AMDGPU_FAMILY_AI)
3589                 client_id = SOC15_IH_CLIENTID_DCE;
3590
3591         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3592         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3593
3594         /*
3595          * Actions of amdgpu_irq_add_id():
3596          * 1. Register a set() function with base driver.
3597          *    Base driver will call set() function to enable/disable an
3598          *    interrupt in DC hardware.
3599          * 2. Register amdgpu_dm_irq_handler().
3600          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3601          *    coming from DC hardware.
3602          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3603          *    for acknowledging and handling. */
3604
3605         /* Use VBLANK interrupt */
3606         for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
3607                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
3608                 if (r) {
3609                         DRM_ERROR("Failed to add crtc irq id!\n");
3610                         return r;
3611                 }
3612
3613                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3614                 int_params.irq_source =
3615                         dc_interrupt_to_irq_source(dc, i, 0);
3616
3617                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3618
3619                 c_irq_params->adev = adev;
3620                 c_irq_params->irq_src = int_params.irq_source;
3621
3622                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3623                                 dm_crtc_high_irq, c_irq_params);
3624         }
3625
3626         /* Use VUPDATE interrupt */
3627         for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) {
3628                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq);
3629                 if (r) {
3630                         DRM_ERROR("Failed to add vupdate irq id!\n");
3631                         return r;
3632                 }
3633
3634                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3635                 int_params.irq_source =
3636                         dc_interrupt_to_irq_source(dc, i, 0);
3637
3638                 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
3639
3640                 c_irq_params->adev = adev;
3641                 c_irq_params->irq_src = int_params.irq_source;
3642
3643                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3644                                 dm_vupdate_high_irq, c_irq_params);
3645         }
3646
3647         /* Use GRPH_PFLIP interrupt */
3648         for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
3649                         i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
3650                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
3651                 if (r) {
3652                         DRM_ERROR("Failed to add page flip irq id!\n");
3653                         return r;
3654                 }
3655
3656                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3657                 int_params.irq_source =
3658                         dc_interrupt_to_irq_source(dc, i, 0);
3659
3660                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3661
3662                 c_irq_params->adev = adev;
3663                 c_irq_params->irq_src = int_params.irq_source;
3664
3665                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3666                                 dm_pflip_high_irq, c_irq_params);
3667
3668         }
3669
3670         /* HPD */
3671         r = amdgpu_irq_add_id(adev, client_id,
3672                         VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
3673         if (r) {
3674                 DRM_ERROR("Failed to add hpd irq id!\n");
3675                 return r;
3676         }
3677
3678         register_hpd_handlers(adev);
3679
3680         return 0;
3681 }
3682
3683 /* Register IRQ sources and initialize IRQ callbacks */
3684 static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
3685 {
3686         struct dc *dc = adev->dm.dc;
3687         struct common_irq_params *c_irq_params;
3688         struct dc_interrupt_params int_params = {0};
3689         int r;
3690         int i;
3691 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
3692         static const unsigned int vrtl_int_srcid[] = {
3693                 DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL,
3694                 DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL,
3695                 DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL,
3696                 DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL,
3697                 DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL,
3698                 DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL
3699         };
3700 #endif
3701
3702         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3703         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3704
3705         /*
3706          * Actions of amdgpu_irq_add_id():
3707          * 1. Register a set() function with base driver.
3708          *    Base driver will call set() function to enable/disable an
3709          *    interrupt in DC hardware.
3710          * 2. Register amdgpu_dm_irq_handler().
3711          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3712          *    coming from DC hardware.
3713          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3714          *    for acknowledging and handling.
3715          */
3716
3717         /* Use VSTARTUP interrupt */
3718         for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
3719                         i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
3720                         i++) {
3721                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);
3722
3723                 if (r) {
3724                         DRM_ERROR("Failed to add crtc irq id!\n");
3725                         return r;
3726                 }
3727
3728                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3729                 int_params.irq_source =
3730                         dc_interrupt_to_irq_source(dc, i, 0);
3731
3732                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3733
3734                 c_irq_params->adev = adev;
3735                 c_irq_params->irq_src = int_params.irq_source;
3736
3737                 amdgpu_dm_irq_register_interrupt(
3738                         adev, &int_params, dm_crtc_high_irq, c_irq_params);
3739         }
3740
3741         /* Use otg vertical line interrupt */
3742 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
3743         for (i = 0; i <= adev->mode_info.num_crtc - 1; i++) {
3744                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE,
3745                                 vrtl_int_srcid[i], &adev->vline0_irq);
3746
3747                 if (r) {
3748                         DRM_ERROR("Failed to add vline0 irq id!\n");
3749                         return r;
3750                 }
3751
3752                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3753                 int_params.irq_source =
3754                         dc_interrupt_to_irq_source(dc, vrtl_int_srcid[i], 0);
3755
3756                 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID) {
3757                         DRM_ERROR("Failed to register vline0 irq %d!\n", vrtl_int_srcid[i]);
3758                         break;
3759                 }
3760
3761                 c_irq_params = &adev->dm.vline0_params[int_params.irq_source
3762                                         - DC_IRQ_SOURCE_DC1_VLINE0];
3763
3764                 c_irq_params->adev = adev;
3765                 c_irq_params->irq_src = int_params.irq_source;
3766
3767                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3768                                 dm_dcn_vertical_interrupt0_high_irq, c_irq_params);
3769         }
3770 #endif
3771
3772         /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to
3773          * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx
3774          * to trigger at end of each vblank, regardless of state of the lock,
3775          * matching DCE behaviour.
3776          */
3777         for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT;
3778              i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1;
3779              i++) {
3780                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq);
3781
3782                 if (r) {
3783                         DRM_ERROR("Failed to add vupdate irq id!\n");
3784                         return r;
3785                 }
3786
3787                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3788                 int_params.irq_source =
3789                         dc_interrupt_to_irq_source(dc, i, 0);
3790
3791                 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
3792
3793                 c_irq_params->adev = adev;
3794                 c_irq_params->irq_src = int_params.irq_source;
3795
3796                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3797                                 dm_vupdate_high_irq, c_irq_params);
3798         }
3799
3800         /* Use GRPH_PFLIP interrupt */
3801         for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
3802                         i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + dc->caps.max_otg_num - 1;
3803                         i++) {
3804                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
3805                 if (r) {
3806                         DRM_ERROR("Failed to add page flip irq id!\n");
3807                         return r;
3808                 }
3809
3810                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3811                 int_params.irq_source =
3812                         dc_interrupt_to_irq_source(dc, i, 0);
3813
3814                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3815
3816                 c_irq_params->adev = adev;
3817                 c_irq_params->irq_src = int_params.irq_source;
3818
3819                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3820                                 dm_pflip_high_irq, c_irq_params);
3821
3822         }
3823
3824         /* HPD */
3825         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
3826                         &adev->hpd_irq);
3827         if (r) {
3828                 DRM_ERROR("Failed to add hpd irq id!\n");
3829                 return r;
3830         }
3831
3832         register_hpd_handlers(adev);
3833
3834         return 0;
3835 }
3836 /* Register Outbox IRQ sources and initialize IRQ callbacks */
3837 static int register_outbox_irq_handlers(struct amdgpu_device *adev)
3838 {
3839         struct dc *dc = adev->dm.dc;
3840         struct common_irq_params *c_irq_params;
3841         struct dc_interrupt_params int_params = {0};
3842         int r, i;
3843
3844         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3845         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3846
3847         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT,
3848                         &adev->dmub_outbox_irq);
3849         if (r) {
3850                 DRM_ERROR("Failed to add outbox irq id!\n");
3851                 return r;
3852         }
3853
3854         if (dc->ctx->dmub_srv) {
3855                 i = DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT;
3856                 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3857                 int_params.irq_source =
3858                 dc_interrupt_to_irq_source(dc, i, 0);
3859
3860                 c_irq_params = &adev->dm.dmub_outbox_params[0];
3861
3862                 c_irq_params->adev = adev;
3863                 c_irq_params->irq_src = int_params.irq_source;
3864
3865                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3866                                 dm_dmub_outbox1_low_irq, c_irq_params);
3867         }
3868
3869         return 0;
3870 }
3871
3872 /*
3873  * Acquires the lock for the atomic state object and returns
3874  * the new atomic state.
3875  *
3876  * This should only be called during atomic check.
3877  */
3878 int dm_atomic_get_state(struct drm_atomic_state *state,
3879                         struct dm_atomic_state **dm_state)
3880 {
3881         struct drm_device *dev = state->dev;
3882         struct amdgpu_device *adev = drm_to_adev(dev);
3883         struct amdgpu_display_manager *dm = &adev->dm;
3884         struct drm_private_state *priv_state;
3885
3886         if (*dm_state)
3887                 return 0;
3888
3889         priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj);
3890         if (IS_ERR(priv_state))
3891                 return PTR_ERR(priv_state);
3892
3893         *dm_state = to_dm_atomic_state(priv_state);
3894
3895         return 0;
3896 }
3897
3898 static struct dm_atomic_state *
3899 dm_atomic_get_new_state(struct drm_atomic_state *state)
3900 {
3901         struct drm_device *dev = state->dev;
3902         struct amdgpu_device *adev = drm_to_adev(dev);
3903         struct amdgpu_display_manager *dm = &adev->dm;
3904         struct drm_private_obj *obj;
3905         struct drm_private_state *new_obj_state;
3906         int i;
3907
3908         for_each_new_private_obj_in_state(state, obj, new_obj_state, i) {
3909                 if (obj->funcs == dm->atomic_obj.funcs)
3910                         return to_dm_atomic_state(new_obj_state);
3911         }
3912
3913         return NULL;
3914 }
3915
3916 static struct drm_private_state *
3917 dm_atomic_duplicate_state(struct drm_private_obj *obj)
3918 {
3919         struct dm_atomic_state *old_state, *new_state;
3920
3921         new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
3922         if (!new_state)
3923                 return NULL;
3924
3925         __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base);
3926
3927         old_state = to_dm_atomic_state(obj->state);
3928
3929         if (old_state && old_state->context)
3930                 new_state->context = dc_copy_state(old_state->context);
3931
3932         if (!new_state->context) {
3933                 kfree(new_state);
3934                 return NULL;
3935         }
3936
3937         return &new_state->base;
3938 }
3939
3940 static void dm_atomic_destroy_state(struct drm_private_obj *obj,
3941                                     struct drm_private_state *state)
3942 {
3943         struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
3944
3945         if (dm_state && dm_state->context)
3946                 dc_release_state(dm_state->context);
3947
3948         kfree(dm_state);
3949 }
3950
3951 static struct drm_private_state_funcs dm_atomic_state_funcs = {
3952         .atomic_duplicate_state = dm_atomic_duplicate_state,
3953         .atomic_destroy_state = dm_atomic_destroy_state,
3954 };
3955
3956 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
3957 {
3958         struct dm_atomic_state *state;
3959         int r;
3960
3961         adev->mode_info.mode_config_initialized = true;
3962
3963         adev_to_drm(adev)->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
3964         adev_to_drm(adev)->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
3965
3966         adev_to_drm(adev)->mode_config.max_width = 16384;
3967         adev_to_drm(adev)->mode_config.max_height = 16384;
3968
3969         adev_to_drm(adev)->mode_config.preferred_depth = 24;
3970         if (adev->asic_type == CHIP_HAWAII)
3971                 /* disable prefer shadow for now due to hibernation issues */
3972                 adev_to_drm(adev)->mode_config.prefer_shadow = 0;
3973         else
3974                 adev_to_drm(adev)->mode_config.prefer_shadow = 1;
3975         /* indicates support for immediate flip */
3976         adev_to_drm(adev)->mode_config.async_page_flip = true;
3977
3978         state = kzalloc(sizeof(*state), GFP_KERNEL);
3979         if (!state)
3980                 return -ENOMEM;
3981
3982         state->context = dc_create_state(adev->dm.dc);
3983         if (!state->context) {
3984                 kfree(state);
3985                 return -ENOMEM;
3986         }
3987
3988         dc_resource_state_copy_construct_current(adev->dm.dc, state->context);
3989
3990         drm_atomic_private_obj_init(adev_to_drm(adev),
3991                                     &adev->dm.atomic_obj,
3992                                     &state->base,
3993                                     &dm_atomic_state_funcs);
3994
3995         r = amdgpu_display_modeset_create_props(adev);
3996         if (r) {
3997                 dc_release_state(state->context);
3998                 kfree(state);
3999                 return r;
4000         }
4001
4002         r = amdgpu_dm_audio_init(adev);
4003         if (r) {
4004                 dc_release_state(state->context);
4005                 kfree(state);
4006                 return r;
4007         }
4008
4009         return 0;
4010 }
4011
4012 #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12
4013 #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255
4014 #define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50
4015
4016 static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm,
4017                                             int bl_idx)
4018 {
4019 #if defined(CONFIG_ACPI)
4020         struct amdgpu_dm_backlight_caps caps;
4021
4022         memset(&caps, 0, sizeof(caps));
4023
4024         if (dm->backlight_caps[bl_idx].caps_valid)
4025                 return;
4026
4027         amdgpu_acpi_get_backlight_caps(&caps);
4028         if (caps.caps_valid) {
4029                 dm->backlight_caps[bl_idx].caps_valid = true;
4030                 if (caps.aux_support)
4031                         return;
4032                 dm->backlight_caps[bl_idx].min_input_signal = caps.min_input_signal;
4033                 dm->backlight_caps[bl_idx].max_input_signal = caps.max_input_signal;
4034         } else {
4035                 dm->backlight_caps[bl_idx].min_input_signal =
4036                                 AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
4037                 dm->backlight_caps[bl_idx].max_input_signal =
4038                                 AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
4039         }
4040 #else
4041         if (dm->backlight_caps[bl_idx].aux_support)
4042                 return;
4043
4044         dm->backlight_caps[bl_idx].min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
4045         dm->backlight_caps[bl_idx].max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
4046 #endif
4047 }
4048
4049 static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps,
4050                                 unsigned *min, unsigned *max)
4051 {
4052         if (!caps)
4053                 return 0;
4054
4055         if (caps->aux_support) {
4056                 // Firmware limits are in nits, DC API wants millinits.
4057                 *max = 1000 * caps->aux_max_input_signal;
4058                 *min = 1000 * caps->aux_min_input_signal;
4059         } else {
4060                 // Firmware limits are 8-bit, PWM control is 16-bit.
4061                 *max = 0x101 * caps->max_input_signal;
4062                 *min = 0x101 * caps->min_input_signal;
4063         }
4064         return 1;
4065 }
4066
4067 static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *caps,
4068                                         uint32_t brightness)
4069 {
4070         unsigned min, max;
4071
4072         if (!get_brightness_range(caps, &min, &max))
4073                 return brightness;
4074
4075         // Rescale 0..255 to min..max
4076         return min + DIV_ROUND_CLOSEST((max - min) * brightness,
4077                                        AMDGPU_MAX_BL_LEVEL);
4078 }
4079
4080 static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *caps,
4081                                       uint32_t brightness)
4082 {
4083         unsigned min, max;
4084
4085         if (!get_brightness_range(caps, &min, &max))
4086                 return brightness;
4087
4088         if (brightness < min)
4089                 return 0;
4090         // Rescale min..max to 0..255
4091         return DIV_ROUND_CLOSEST(AMDGPU_MAX_BL_LEVEL * (brightness - min),
4092                                  max - min);
4093 }
4094
4095 static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm,
4096                                          int bl_idx,
4097                                          u32 user_brightness)
4098 {
4099         struct amdgpu_dm_backlight_caps caps;
4100         struct dc_link *link;
4101         u32 brightness;
4102         bool rc;
4103
4104         amdgpu_dm_update_backlight_caps(dm, bl_idx);
4105         caps = dm->backlight_caps[bl_idx];
4106
4107         dm->brightness[bl_idx] = user_brightness;
4108         /* update scratch register */
4109         if (bl_idx == 0)
4110                 amdgpu_atombios_scratch_regs_set_backlight_level(dm->adev, dm->brightness[bl_idx]);
4111         brightness = convert_brightness_from_user(&caps, dm->brightness[bl_idx]);
4112         link = (struct dc_link *)dm->backlight_link[bl_idx];
4113
4114         /* Change brightness based on AUX property */
4115         if (caps.aux_support) {
4116                 rc = dc_link_set_backlight_level_nits(link, true, brightness,
4117                                                       AUX_BL_DEFAULT_TRANSITION_TIME_MS);
4118                 if (!rc)
4119                         DRM_DEBUG("DM: Failed to update backlight via AUX on eDP[%d]\n", bl_idx);
4120         } else {
4121                 rc = dc_link_set_backlight_level(link, brightness, 0);
4122                 if (!rc)
4123                         DRM_DEBUG("DM: Failed to update backlight on eDP[%d]\n", bl_idx);
4124         }
4125
4126         if (rc)
4127                 dm->actual_brightness[bl_idx] = user_brightness;
4128 }
4129
4130 static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
4131 {
4132         struct amdgpu_display_manager *dm = bl_get_data(bd);
4133         int i;
4134
4135         for (i = 0; i < dm->num_of_edps; i++) {
4136                 if (bd == dm->backlight_dev[i])
4137                         break;
4138         }
4139         if (i >= AMDGPU_DM_MAX_NUM_EDP)
4140                 i = 0;
4141         amdgpu_dm_backlight_set_level(dm, i, bd->props.brightness);
4142
4143         return 0;
4144 }
4145
4146 static u32 amdgpu_dm_backlight_get_level(struct amdgpu_display_manager *dm,
4147                                          int bl_idx)
4148 {
4149         struct amdgpu_dm_backlight_caps caps;
4150         struct dc_link *link = (struct dc_link *)dm->backlight_link[bl_idx];
4151
4152         amdgpu_dm_update_backlight_caps(dm, bl_idx);
4153         caps = dm->backlight_caps[bl_idx];
4154
4155         if (caps.aux_support) {
4156                 u32 avg, peak;
4157                 bool rc;
4158
4159                 rc = dc_link_get_backlight_level_nits(link, &avg, &peak);
4160                 if (!rc)
4161                         return dm->brightness[bl_idx];
4162                 return convert_brightness_to_user(&caps, avg);
4163         } else {
4164                 int ret = dc_link_get_backlight_level(link);
4165
4166                 if (ret == DC_ERROR_UNEXPECTED)
4167                         return dm->brightness[bl_idx];
4168                 return convert_brightness_to_user(&caps, ret);
4169         }
4170 }
4171
4172 static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
4173 {
4174         struct amdgpu_display_manager *dm = bl_get_data(bd);
4175         int i;
4176
4177         for (i = 0; i < dm->num_of_edps; i++) {
4178                 if (bd == dm->backlight_dev[i])
4179                         break;
4180         }
4181         if (i >= AMDGPU_DM_MAX_NUM_EDP)
4182                 i = 0;
4183         return amdgpu_dm_backlight_get_level(dm, i);
4184 }
4185
4186 static const struct backlight_ops amdgpu_dm_backlight_ops = {
4187         .options = BL_CORE_SUSPENDRESUME,
4188         .get_brightness = amdgpu_dm_backlight_get_brightness,
4189         .update_status  = amdgpu_dm_backlight_update_status,
4190 };
4191
4192 static void
4193 amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm)
4194 {
4195         char bl_name[16];
4196         struct backlight_properties props = { 0 };
4197
4198         amdgpu_dm_update_backlight_caps(dm, dm->num_of_edps);
4199         dm->brightness[dm->num_of_edps] = AMDGPU_MAX_BL_LEVEL;
4200
4201         if (!acpi_video_backlight_use_native()) {
4202                 drm_info(adev_to_drm(dm->adev), "Skipping amdgpu DM backlight registration\n");
4203                 /* Try registering an ACPI video backlight device instead. */
4204                 acpi_video_register_backlight();
4205                 return;
4206         }
4207
4208         props.max_brightness = AMDGPU_MAX_BL_LEVEL;
4209         props.brightness = AMDGPU_MAX_BL_LEVEL;
4210         props.type = BACKLIGHT_RAW;
4211
4212         snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
4213                  adev_to_drm(dm->adev)->primary->index + dm->num_of_edps);
4214
4215         dm->backlight_dev[dm->num_of_edps] = backlight_device_register(bl_name,
4216                                                                        adev_to_drm(dm->adev)->dev,
4217                                                                        dm,
4218                                                                        &amdgpu_dm_backlight_ops,
4219                                                                        &props);
4220
4221         if (IS_ERR(dm->backlight_dev[dm->num_of_edps])) {
4222                 DRM_ERROR("DM: Backlight registration failed!\n");
4223                 dm->backlight_dev[dm->num_of_edps] = NULL;
4224         } else
4225                 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
4226 }
4227
4228 static int initialize_plane(struct amdgpu_display_manager *dm,
4229                             struct amdgpu_mode_info *mode_info, int plane_id,
4230                             enum drm_plane_type plane_type,
4231                             const struct dc_plane_cap *plane_cap)
4232 {
4233         struct drm_plane *plane;
4234         unsigned long possible_crtcs;
4235         int ret = 0;
4236
4237         plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL);
4238         if (!plane) {
4239                 DRM_ERROR("KMS: Failed to allocate plane\n");
4240                 return -ENOMEM;
4241         }
4242         plane->type = plane_type;
4243
4244         /*
4245          * HACK: IGT tests expect that the primary plane for a CRTC
4246          * can only have one possible CRTC. Only expose support for
4247          * any CRTC if they're not going to be used as a primary plane
4248          * for a CRTC - like overlay or underlay planes.
4249          */
4250         possible_crtcs = 1 << plane_id;
4251         if (plane_id >= dm->dc->caps.max_streams)
4252                 possible_crtcs = 0xff;
4253
4254         ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap);
4255
4256         if (ret) {
4257                 DRM_ERROR("KMS: Failed to initialize plane\n");
4258                 kfree(plane);
4259                 return ret;
4260         }
4261
4262         if (mode_info)
4263                 mode_info->planes[plane_id] = plane;
4264
4265         return ret;
4266 }
4267
4268
4269 static void register_backlight_device(struct amdgpu_display_manager *dm,
4270                                       struct dc_link *link)
4271 {
4272         if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
4273             link->type != dc_connection_none) {
4274                 /*
4275                  * Event if registration failed, we should continue with
4276                  * DM initialization because not having a backlight control
4277                  * is better then a black screen.
4278                  */
4279                 if (!dm->backlight_dev[dm->num_of_edps])
4280                         amdgpu_dm_register_backlight_device(dm);
4281
4282                 if (dm->backlight_dev[dm->num_of_edps]) {
4283                         dm->backlight_link[dm->num_of_edps] = link;
4284                         dm->num_of_edps++;
4285                 }
4286         }
4287 }
4288
4289 static void amdgpu_set_panel_orientation(struct drm_connector *connector);
4290
4291 /*
4292  * In this architecture, the association
4293  * connector -> encoder -> crtc
4294  * id not really requried. The crtc and connector will hold the
4295  * display_index as an abstraction to use with DAL component
4296  *
4297  * Returns 0 on success
4298  */
4299 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
4300 {
4301         struct amdgpu_display_manager *dm = &adev->dm;
4302         s32 i;
4303         struct amdgpu_dm_connector *aconnector = NULL;
4304         struct amdgpu_encoder *aencoder = NULL;
4305         struct amdgpu_mode_info *mode_info = &adev->mode_info;
4306         u32 link_cnt;
4307         s32 primary_planes;
4308         enum dc_connection_type new_connection_type = dc_connection_none;
4309         const struct dc_plane_cap *plane;
4310         bool psr_feature_enabled = false;
4311         int max_overlay = dm->dc->caps.max_slave_planes;
4312
4313         dm->display_indexes_num = dm->dc->caps.max_streams;
4314         /* Update the actual used number of crtc */
4315         adev->mode_info.num_crtc = adev->dm.display_indexes_num;
4316
4317         amdgpu_dm_set_irq_funcs(adev);
4318
4319         link_cnt = dm->dc->caps.max_links;
4320         if (amdgpu_dm_mode_config_init(dm->adev)) {
4321                 DRM_ERROR("DM: Failed to initialize mode config\n");
4322                 return -EINVAL;
4323         }
4324
4325         /* There is one primary plane per CRTC */
4326         primary_planes = dm->dc->caps.max_streams;
4327         ASSERT(primary_planes <= AMDGPU_MAX_PLANES);
4328
4329         /*
4330          * Initialize primary planes, implicit planes for legacy IOCTLS.
4331          * Order is reversed to match iteration order in atomic check.
4332          */
4333         for (i = (primary_planes - 1); i >= 0; i--) {
4334                 plane = &dm->dc->caps.planes[i];
4335
4336                 if (initialize_plane(dm, mode_info, i,
4337                                      DRM_PLANE_TYPE_PRIMARY, plane)) {
4338                         DRM_ERROR("KMS: Failed to initialize primary plane\n");
4339                         goto fail;
4340                 }
4341         }
4342
4343         /*
4344          * Initialize overlay planes, index starting after primary planes.
4345          * These planes have a higher DRM index than the primary planes since
4346          * they should be considered as having a higher z-order.
4347          * Order is reversed to match iteration order in atomic check.
4348          *
4349          * Only support DCN for now, and only expose one so we don't encourage
4350          * userspace to use up all the pipes.
4351          */
4352         for (i = 0; i < dm->dc->caps.max_planes; ++i) {
4353                 struct dc_plane_cap *plane = &dm->dc->caps.planes[i];
4354
4355                 /* Do not create overlay if MPO disabled */
4356                 if (amdgpu_dc_debug_mask & DC_DISABLE_MPO)
4357                         break;
4358
4359                 if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL)
4360                         continue;
4361
4362                 if (!plane->pixel_format_support.argb8888)
4363                         continue;
4364
4365                 if (max_overlay-- == 0)
4366                         break;
4367
4368                 if (initialize_plane(dm, NULL, primary_planes + i,
4369                                      DRM_PLANE_TYPE_OVERLAY, plane)) {
4370                         DRM_ERROR("KMS: Failed to initialize overlay plane\n");
4371                         goto fail;
4372                 }
4373         }
4374
4375         for (i = 0; i < dm->dc->caps.max_streams; i++)
4376                 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) {
4377                         DRM_ERROR("KMS: Failed to initialize crtc\n");
4378                         goto fail;
4379                 }
4380
4381         /* Use Outbox interrupt */
4382         switch (adev->ip_versions[DCE_HWIP][0]) {
4383         case IP_VERSION(3, 0, 0):
4384         case IP_VERSION(3, 1, 2):
4385         case IP_VERSION(3, 1, 3):
4386         case IP_VERSION(3, 1, 4):
4387         case IP_VERSION(3, 1, 5):
4388         case IP_VERSION(3, 1, 6):
4389         case IP_VERSION(3, 2, 0):
4390         case IP_VERSION(3, 2, 1):
4391         case IP_VERSION(2, 1, 0):
4392                 if (register_outbox_irq_handlers(dm->adev)) {
4393                         DRM_ERROR("DM: Failed to initialize IRQ\n");
4394                         goto fail;
4395                 }
4396                 break;
4397         default:
4398                 DRM_DEBUG_KMS("Unsupported DCN IP version for outbox: 0x%X\n",
4399                               adev->ip_versions[DCE_HWIP][0]);
4400         }
4401
4402         /* Determine whether to enable PSR support by default. */
4403         if (!(amdgpu_dc_debug_mask & DC_DISABLE_PSR)) {
4404                 switch (adev->ip_versions[DCE_HWIP][0]) {
4405                 case IP_VERSION(3, 1, 2):
4406                 case IP_VERSION(3, 1, 3):
4407                 case IP_VERSION(3, 1, 4):
4408                 case IP_VERSION(3, 1, 5):
4409                 case IP_VERSION(3, 1, 6):
4410                 case IP_VERSION(3, 2, 0):
4411                 case IP_VERSION(3, 2, 1):
4412                         psr_feature_enabled = true;
4413                         break;
4414                 default:
4415                         psr_feature_enabled = amdgpu_dc_feature_mask & DC_PSR_MASK;
4416                         break;
4417                 }
4418         }
4419
4420         /* loops over all connectors on the board */
4421         for (i = 0; i < link_cnt; i++) {
4422                 struct dc_link *link = NULL;
4423
4424                 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
4425                         DRM_ERROR(
4426                                 "KMS: Cannot support more than %d display indexes\n",
4427                                         AMDGPU_DM_MAX_DISPLAY_INDEX);
4428                         continue;
4429                 }
4430
4431                 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
4432                 if (!aconnector)
4433                         goto fail;
4434
4435                 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
4436                 if (!aencoder)
4437                         goto fail;
4438
4439                 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
4440                         DRM_ERROR("KMS: Failed to initialize encoder\n");
4441                         goto fail;
4442                 }
4443
4444                 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
4445                         DRM_ERROR("KMS: Failed to initialize connector\n");
4446                         goto fail;
4447                 }
4448
4449                 link = dc_get_link_at_index(dm->dc, i);
4450
4451                 if (!dc_link_detect_connection_type(link, &new_connection_type))
4452                         DRM_ERROR("KMS: Failed to detect connector\n");
4453
4454                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
4455                         emulated_link_detect(link);
4456                         amdgpu_dm_update_connector_after_detect(aconnector);
4457                 } else {
4458                         bool ret = false;
4459
4460                         mutex_lock(&dm->dc_lock);
4461                         ret = dc_link_detect(link, DETECT_REASON_BOOT);
4462                         mutex_unlock(&dm->dc_lock);
4463
4464                         if (ret) {
4465                                 amdgpu_dm_update_connector_after_detect(aconnector);
4466                                 register_backlight_device(dm, link);
4467
4468                                 if (dm->num_of_edps)
4469                                         update_connector_ext_caps(aconnector);
4470
4471                                 if (psr_feature_enabled)
4472                                         amdgpu_dm_set_psr_caps(link);
4473
4474                                 /* TODO: Fix vblank control helpers to delay PSR entry to allow this when
4475                                  * PSR is also supported.
4476                                  */
4477                                 if (link->psr_settings.psr_feature_enabled)
4478                                         adev_to_drm(adev)->vblank_disable_immediate = false;
4479                         }
4480                 }
4481                 amdgpu_set_panel_orientation(&aconnector->base);
4482         }
4483
4484         /* If we didn't find a panel, notify the acpi video detection */
4485         if (dm->adev->flags & AMD_IS_APU && dm->num_of_edps == 0)
4486                 acpi_video_report_nolcd();
4487
4488         /* Software is initialized. Now we can register interrupt handlers. */
4489         switch (adev->asic_type) {
4490 #if defined(CONFIG_DRM_AMD_DC_SI)
4491         case CHIP_TAHITI:
4492         case CHIP_PITCAIRN:
4493         case CHIP_VERDE:
4494         case CHIP_OLAND:
4495                 if (dce60_register_irq_handlers(dm->adev)) {
4496                         DRM_ERROR("DM: Failed to initialize IRQ\n");
4497                         goto fail;
4498                 }
4499                 break;
4500 #endif
4501         case CHIP_BONAIRE:
4502         case CHIP_HAWAII:
4503         case CHIP_KAVERI:
4504         case CHIP_KABINI:
4505         case CHIP_MULLINS:
4506         case CHIP_TONGA:
4507         case CHIP_FIJI:
4508         case CHIP_CARRIZO:
4509         case CHIP_STONEY:
4510         case CHIP_POLARIS11:
4511         case CHIP_POLARIS10:
4512         case CHIP_POLARIS12:
4513         case CHIP_VEGAM:
4514         case CHIP_VEGA10:
4515         case CHIP_VEGA12:
4516         case CHIP_VEGA20:
4517                 if (dce110_register_irq_handlers(dm->adev)) {
4518                         DRM_ERROR("DM: Failed to initialize IRQ\n");
4519                         goto fail;
4520                 }
4521                 break;
4522         default:
4523                 switch (adev->ip_versions[DCE_HWIP][0]) {
4524                 case IP_VERSION(1, 0, 0):
4525                 case IP_VERSION(1, 0, 1):
4526                 case IP_VERSION(2, 0, 2):
4527                 case IP_VERSION(2, 0, 3):
4528                 case IP_VERSION(2, 0, 0):
4529                 case IP_VERSION(2, 1, 0):
4530                 case IP_VERSION(3, 0, 0):
4531                 case IP_VERSION(3, 0, 2):
4532                 case IP_VERSION(3, 0, 3):
4533                 case IP_VERSION(3, 0, 1):
4534                 case IP_VERSION(3, 1, 2):
4535                 case IP_VERSION(3, 1, 3):
4536                 case IP_VERSION(3, 1, 4):
4537                 case IP_VERSION(3, 1, 5):
4538                 case IP_VERSION(3, 1, 6):
4539                 case IP_VERSION(3, 2, 0):
4540                 case IP_VERSION(3, 2, 1):
4541                         if (dcn10_register_irq_handlers(dm->adev)) {
4542                                 DRM_ERROR("DM: Failed to initialize IRQ\n");
4543                                 goto fail;
4544                         }
4545                         break;
4546                 default:
4547                         DRM_ERROR("Unsupported DCE IP versions: 0x%X\n",
4548                                         adev->ip_versions[DCE_HWIP][0]);
4549                         goto fail;
4550                 }
4551                 break;
4552         }
4553
4554         return 0;
4555 fail:
4556         kfree(aencoder);
4557         kfree(aconnector);
4558
4559         return -EINVAL;
4560 }
4561
4562 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
4563 {
4564         drm_atomic_private_obj_fini(&dm->atomic_obj);
4565         return;
4566 }
4567
4568 /******************************************************************************
4569  * amdgpu_display_funcs functions
4570  *****************************************************************************/
4571
4572 /*
4573  * dm_bandwidth_update - program display watermarks
4574  *
4575  * @adev: amdgpu_device pointer
4576  *
4577  * Calculate and program the display watermarks and line buffer allocation.
4578  */
4579 static void dm_bandwidth_update(struct amdgpu_device *adev)
4580 {
4581         /* TODO: implement later */
4582 }
4583
4584 static const struct amdgpu_display_funcs dm_display_funcs = {
4585         .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
4586         .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
4587         .backlight_set_level = NULL, /* never called for DC */
4588         .backlight_get_level = NULL, /* never called for DC */
4589         .hpd_sense = NULL,/* called unconditionally */
4590         .hpd_set_polarity = NULL, /* called unconditionally */
4591         .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
4592         .page_flip_get_scanoutpos =
4593                 dm_crtc_get_scanoutpos,/* called unconditionally */
4594         .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
4595         .add_connector = NULL, /* VBIOS parsing. DAL does it. */
4596 };
4597
4598 #if defined(CONFIG_DEBUG_KERNEL_DC)
4599
4600 static ssize_t s3_debug_store(struct device *device,
4601                               struct device_attribute *attr,
4602                               const char *buf,
4603                               size_t count)
4604 {
4605         int ret;
4606         int s3_state;
4607         struct drm_device *drm_dev = dev_get_drvdata(device);
4608         struct amdgpu_device *adev = drm_to_adev(drm_dev);
4609
4610         ret = kstrtoint(buf, 0, &s3_state);
4611
4612         if (ret == 0) {
4613                 if (s3_state) {
4614                         dm_resume(adev);
4615                         drm_kms_helper_hotplug_event(adev_to_drm(adev));
4616                 } else
4617                         dm_suspend(adev);
4618         }
4619
4620         return ret == 0 ? count : 0;
4621 }
4622
4623 DEVICE_ATTR_WO(s3_debug);
4624
4625 #endif
4626
4627 static int dm_init_microcode(struct amdgpu_device *adev)
4628 {
4629         char *fw_name_dmub;
4630         int r;
4631
4632         switch (adev->ip_versions[DCE_HWIP][0]) {
4633         case IP_VERSION(2, 1, 0):
4634                 fw_name_dmub = FIRMWARE_RENOIR_DMUB;
4635                 if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
4636                         fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB;
4637                 break;
4638         case IP_VERSION(3, 0, 0):
4639                 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0))
4640                         fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB;
4641                 else
4642                         fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB;
4643                 break;
4644         case IP_VERSION(3, 0, 1):
4645                 fw_name_dmub = FIRMWARE_VANGOGH_DMUB;
4646                 break;
4647         case IP_VERSION(3, 0, 2):
4648                 fw_name_dmub = FIRMWARE_DIMGREY_CAVEFISH_DMUB;
4649                 break;
4650         case IP_VERSION(3, 0, 3):
4651                 fw_name_dmub = FIRMWARE_BEIGE_GOBY_DMUB;
4652                 break;
4653         case IP_VERSION(3, 1, 2):
4654         case IP_VERSION(3, 1, 3):
4655                 fw_name_dmub = FIRMWARE_YELLOW_CARP_DMUB;
4656                 break;
4657         case IP_VERSION(3, 1, 4):
4658                 fw_name_dmub = FIRMWARE_DCN_314_DMUB;
4659                 break;
4660         case IP_VERSION(3, 1, 5):
4661                 fw_name_dmub = FIRMWARE_DCN_315_DMUB;
4662                 break;
4663         case IP_VERSION(3, 1, 6):
4664                 fw_name_dmub = FIRMWARE_DCN316_DMUB;
4665                 break;
4666         case IP_VERSION(3, 2, 0):
4667                 fw_name_dmub = FIRMWARE_DCN_V3_2_0_DMCUB;
4668                 break;
4669         case IP_VERSION(3, 2, 1):
4670                 fw_name_dmub = FIRMWARE_DCN_V3_2_1_DMCUB;
4671                 break;
4672         default:
4673                 /* ASIC doesn't support DMUB. */
4674                 return 0;
4675         }
4676         r = amdgpu_ucode_request(adev, &adev->dm.dmub_fw, fw_name_dmub);
4677         if (r)
4678                 DRM_ERROR("DMUB firmware loading failed: %d\n", r);
4679         return r;
4680 }
4681
4682 static int dm_early_init(void *handle)
4683 {
4684         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4685         struct amdgpu_mode_info *mode_info = &adev->mode_info;
4686         struct atom_context *ctx = mode_info->atom_context;
4687         int index = GetIndexIntoMasterTable(DATA, Object_Header);
4688         u16 data_offset;
4689
4690         /* if there is no object header, skip DM */
4691         if (!amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) {
4692                 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
4693                 dev_info(adev->dev, "No object header, skipping DM\n");
4694                 return -ENOENT;
4695         }
4696
4697         switch (adev->asic_type) {
4698 #if defined(CONFIG_DRM_AMD_DC_SI)
4699         case CHIP_TAHITI:
4700         case CHIP_PITCAIRN:
4701         case CHIP_VERDE:
4702                 adev->mode_info.num_crtc = 6;
4703                 adev->mode_info.num_hpd = 6;
4704                 adev->mode_info.num_dig = 6;
4705                 break;
4706         case CHIP_OLAND:
4707                 adev->mode_info.num_crtc = 2;
4708                 adev->mode_info.num_hpd = 2;
4709                 adev->mode_info.num_dig = 2;
4710                 break;
4711 #endif
4712         case CHIP_BONAIRE:
4713         case CHIP_HAWAII:
4714                 adev->mode_info.num_crtc = 6;
4715                 adev->mode_info.num_hpd = 6;
4716                 adev->mode_info.num_dig = 6;
4717                 break;
4718         case CHIP_KAVERI:
4719                 adev->mode_info.num_crtc = 4;
4720                 adev->mode_info.num_hpd = 6;
4721                 adev->mode_info.num_dig = 7;
4722                 break;
4723         case CHIP_KABINI:
4724         case CHIP_MULLINS:
4725                 adev->mode_info.num_crtc = 2;
4726                 adev->mode_info.num_hpd = 6;
4727                 adev->mode_info.num_dig = 6;
4728                 break;
4729         case CHIP_FIJI:
4730         case CHIP_TONGA:
4731                 adev->mode_info.num_crtc = 6;
4732                 adev->mode_info.num_hpd = 6;
4733                 adev->mode_info.num_dig = 7;
4734                 break;
4735         case CHIP_CARRIZO:
4736                 adev->mode_info.num_crtc = 3;
4737                 adev->mode_info.num_hpd = 6;
4738                 adev->mode_info.num_dig = 9;
4739                 break;
4740         case CHIP_STONEY:
4741                 adev->mode_info.num_crtc = 2;
4742                 adev->mode_info.num_hpd = 6;
4743                 adev->mode_info.num_dig = 9;
4744                 break;
4745         case CHIP_POLARIS11:
4746         case CHIP_POLARIS12:
4747                 adev->mode_info.num_crtc = 5;
4748                 adev->mode_info.num_hpd = 5;
4749                 adev->mode_info.num_dig = 5;
4750                 break;
4751         case CHIP_POLARIS10:
4752         case CHIP_VEGAM:
4753                 adev->mode_info.num_crtc = 6;
4754                 adev->mode_info.num_hpd = 6;
4755                 adev->mode_info.num_dig = 6;
4756                 break;
4757         case CHIP_VEGA10:
4758         case CHIP_VEGA12:
4759         case CHIP_VEGA20:
4760                 adev->mode_info.num_crtc = 6;
4761                 adev->mode_info.num_hpd = 6;
4762                 adev->mode_info.num_dig = 6;
4763                 break;
4764         default:
4765
4766                 switch (adev->ip_versions[DCE_HWIP][0]) {
4767                 case IP_VERSION(2, 0, 2):
4768                 case IP_VERSION(3, 0, 0):
4769                         adev->mode_info.num_crtc = 6;
4770                         adev->mode_info.num_hpd = 6;
4771                         adev->mode_info.num_dig = 6;
4772                         break;
4773                 case IP_VERSION(2, 0, 0):
4774                 case IP_VERSION(3, 0, 2):
4775                         adev->mode_info.num_crtc = 5;
4776                         adev->mode_info.num_hpd = 5;
4777                         adev->mode_info.num_dig = 5;
4778                         break;
4779                 case IP_VERSION(2, 0, 3):
4780                 case IP_VERSION(3, 0, 3):
4781                         adev->mode_info.num_crtc = 2;
4782                         adev->mode_info.num_hpd = 2;
4783                         adev->mode_info.num_dig = 2;
4784                         break;
4785                 case IP_VERSION(1, 0, 0):
4786                 case IP_VERSION(1, 0, 1):
4787                 case IP_VERSION(3, 0, 1):
4788                 case IP_VERSION(2, 1, 0):
4789                 case IP_VERSION(3, 1, 2):
4790                 case IP_VERSION(3, 1, 3):
4791                 case IP_VERSION(3, 1, 4):
4792                 case IP_VERSION(3, 1, 5):
4793                 case IP_VERSION(3, 1, 6):
4794                 case IP_VERSION(3, 2, 0):
4795                 case IP_VERSION(3, 2, 1):
4796                         adev->mode_info.num_crtc = 4;
4797                         adev->mode_info.num_hpd = 4;
4798                         adev->mode_info.num_dig = 4;
4799                         break;
4800                 default:
4801                         DRM_ERROR("Unsupported DCE IP versions: 0x%x\n",
4802                                         adev->ip_versions[DCE_HWIP][0]);
4803                         return -EINVAL;
4804                 }
4805                 break;
4806         }
4807
4808         if (adev->mode_info.funcs == NULL)
4809                 adev->mode_info.funcs = &dm_display_funcs;
4810
4811         /*
4812          * Note: Do NOT change adev->audio_endpt_rreg and
4813          * adev->audio_endpt_wreg because they are initialised in
4814          * amdgpu_device_init()
4815          */
4816 #if defined(CONFIG_DEBUG_KERNEL_DC)
4817         device_create_file(
4818                 adev_to_drm(adev)->dev,
4819                 &dev_attr_s3_debug);
4820 #endif
4821         adev->dc_enabled = true;
4822
4823         return dm_init_microcode(adev);
4824 }
4825
4826 static bool modereset_required(struct drm_crtc_state *crtc_state)
4827 {
4828         return !crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state);
4829 }
4830
4831 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
4832 {
4833         drm_encoder_cleanup(encoder);
4834         kfree(encoder);
4835 }
4836
4837 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
4838         .destroy = amdgpu_dm_encoder_destroy,
4839 };
4840
4841 static int
4842 fill_plane_color_attributes(const struct drm_plane_state *plane_state,
4843                             const enum surface_pixel_format format,
4844                             enum dc_color_space *color_space)
4845 {
4846         bool full_range;
4847
4848         *color_space = COLOR_SPACE_SRGB;
4849
4850         /* DRM color properties only affect non-RGB formats. */
4851         if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
4852                 return 0;
4853
4854         full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE);
4855
4856         switch (plane_state->color_encoding) {
4857         case DRM_COLOR_YCBCR_BT601:
4858                 if (full_range)
4859                         *color_space = COLOR_SPACE_YCBCR601;
4860                 else
4861                         *color_space = COLOR_SPACE_YCBCR601_LIMITED;
4862                 break;
4863
4864         case DRM_COLOR_YCBCR_BT709:
4865                 if (full_range)
4866                         *color_space = COLOR_SPACE_YCBCR709;
4867                 else
4868                         *color_space = COLOR_SPACE_YCBCR709_LIMITED;
4869                 break;
4870
4871         case DRM_COLOR_YCBCR_BT2020:
4872                 if (full_range)
4873                         *color_space = COLOR_SPACE_2020_YCBCR;
4874                 else
4875                         return -EINVAL;
4876                 break;
4877
4878         default:
4879                 return -EINVAL;
4880         }
4881
4882         return 0;
4883 }
4884
4885 static int
4886 fill_dc_plane_info_and_addr(struct amdgpu_device *adev,
4887                             const struct drm_plane_state *plane_state,
4888                             const u64 tiling_flags,
4889                             struct dc_plane_info *plane_info,
4890                             struct dc_plane_address *address,
4891                             bool tmz_surface,
4892                             bool force_disable_dcc)
4893 {
4894         const struct drm_framebuffer *fb = plane_state->fb;
4895         const struct amdgpu_framebuffer *afb =
4896                 to_amdgpu_framebuffer(plane_state->fb);
4897         int ret;
4898
4899         memset(plane_info, 0, sizeof(*plane_info));
4900
4901         switch (fb->format->format) {
4902         case DRM_FORMAT_C8:
4903                 plane_info->format =
4904                         SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
4905                 break;
4906         case DRM_FORMAT_RGB565:
4907                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
4908                 break;
4909         case DRM_FORMAT_XRGB8888:
4910         case DRM_FORMAT_ARGB8888:
4911                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
4912                 break;
4913         case DRM_FORMAT_XRGB2101010:
4914         case DRM_FORMAT_ARGB2101010:
4915                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
4916                 break;
4917         case DRM_FORMAT_XBGR2101010:
4918         case DRM_FORMAT_ABGR2101010:
4919                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
4920                 break;
4921         case DRM_FORMAT_XBGR8888:
4922         case DRM_FORMAT_ABGR8888:
4923                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888;
4924                 break;
4925         case DRM_FORMAT_NV21:
4926                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
4927                 break;
4928         case DRM_FORMAT_NV12:
4929                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
4930                 break;
4931         case DRM_FORMAT_P010:
4932                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb;
4933                 break;
4934         case DRM_FORMAT_XRGB16161616F:
4935         case DRM_FORMAT_ARGB16161616F:
4936                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F;
4937                 break;
4938         case DRM_FORMAT_XBGR16161616F:
4939         case DRM_FORMAT_ABGR16161616F:
4940                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F;
4941                 break;
4942         case DRM_FORMAT_XRGB16161616:
4943         case DRM_FORMAT_ARGB16161616:
4944                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616;
4945                 break;
4946         case DRM_FORMAT_XBGR16161616:
4947         case DRM_FORMAT_ABGR16161616:
4948                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616;
4949                 break;
4950         default:
4951                 DRM_ERROR(
4952                         "Unsupported screen format %p4cc\n",
4953                         &fb->format->format);
4954                 return -EINVAL;
4955         }
4956
4957         switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
4958         case DRM_MODE_ROTATE_0:
4959                 plane_info->rotation = ROTATION_ANGLE_0;
4960                 break;
4961         case DRM_MODE_ROTATE_90:
4962                 plane_info->rotation = ROTATION_ANGLE_90;
4963                 break;
4964         case DRM_MODE_ROTATE_180:
4965                 plane_info->rotation = ROTATION_ANGLE_180;
4966                 break;
4967         case DRM_MODE_ROTATE_270:
4968                 plane_info->rotation = ROTATION_ANGLE_270;
4969                 break;
4970         default:
4971                 plane_info->rotation = ROTATION_ANGLE_0;
4972                 break;
4973         }
4974
4975
4976         plane_info->visible = true;
4977         plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE;
4978
4979         plane_info->layer_index = plane_state->normalized_zpos;
4980
4981         ret = fill_plane_color_attributes(plane_state, plane_info->format,
4982                                           &plane_info->color_space);
4983         if (ret)
4984                 return ret;
4985
4986         ret = amdgpu_dm_plane_fill_plane_buffer_attributes(adev, afb, plane_info->format,
4987                                            plane_info->rotation, tiling_flags,
4988                                            &plane_info->tiling_info,
4989                                            &plane_info->plane_size,
4990                                            &plane_info->dcc, address,
4991                                            tmz_surface, force_disable_dcc);
4992         if (ret)
4993                 return ret;
4994
4995         amdgpu_dm_plane_fill_blending_from_plane_state(
4996                 plane_state, &plane_info->per_pixel_alpha, &plane_info->pre_multiplied_alpha,
4997                 &plane_info->global_alpha, &plane_info->global_alpha_value);
4998
4999         return 0;
5000 }
5001
5002 static int fill_dc_plane_attributes(struct amdgpu_device *adev,
5003                                     struct dc_plane_state *dc_plane_state,
5004                                     struct drm_plane_state *plane_state,
5005                                     struct drm_crtc_state *crtc_state)
5006 {
5007         struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
5008         struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)plane_state->fb;
5009         struct dc_scaling_info scaling_info;
5010         struct dc_plane_info plane_info;
5011         int ret;
5012         bool force_disable_dcc = false;
5013
5014         ret = amdgpu_dm_plane_fill_dc_scaling_info(adev, plane_state, &scaling_info);
5015         if (ret)
5016                 return ret;
5017
5018         dc_plane_state->src_rect = scaling_info.src_rect;
5019         dc_plane_state->dst_rect = scaling_info.dst_rect;
5020         dc_plane_state->clip_rect = scaling_info.clip_rect;
5021         dc_plane_state->scaling_quality = scaling_info.scaling_quality;
5022
5023         force_disable_dcc = adev->asic_type == CHIP_RAVEN && adev->in_suspend;
5024         ret = fill_dc_plane_info_and_addr(adev, plane_state,
5025                                           afb->tiling_flags,
5026                                           &plane_info,
5027                                           &dc_plane_state->address,
5028                                           afb->tmz_surface,
5029                                           force_disable_dcc);
5030         if (ret)
5031                 return ret;
5032
5033         dc_plane_state->format = plane_info.format;
5034         dc_plane_state->color_space = plane_info.color_space;
5035         dc_plane_state->format = plane_info.format;
5036         dc_plane_state->plane_size = plane_info.plane_size;
5037         dc_plane_state->rotation = plane_info.rotation;
5038         dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror;
5039         dc_plane_state->stereo_format = plane_info.stereo_format;
5040         dc_plane_state->tiling_info = plane_info.tiling_info;
5041         dc_plane_state->visible = plane_info.visible;
5042         dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha;
5043         dc_plane_state->pre_multiplied_alpha = plane_info.pre_multiplied_alpha;
5044         dc_plane_state->global_alpha = plane_info.global_alpha;
5045         dc_plane_state->global_alpha_value = plane_info.global_alpha_value;
5046         dc_plane_state->dcc = plane_info.dcc;
5047         dc_plane_state->layer_index = plane_info.layer_index;
5048         dc_plane_state->flip_int_enabled = true;
5049
5050         /*
5051          * Always set input transfer function, since plane state is refreshed
5052          * every time.
5053          */
5054         ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dc_plane_state);
5055         if (ret)
5056                 return ret;
5057
5058         return 0;
5059 }
5060
5061 static inline void fill_dc_dirty_rect(struct drm_plane *plane,
5062                                       struct rect *dirty_rect, int32_t x,
5063                                       s32 y, s32 width, s32 height,
5064                                       int *i, bool ffu)
5065 {
5066         if (*i > DC_MAX_DIRTY_RECTS)
5067                 return;
5068
5069         if (*i == DC_MAX_DIRTY_RECTS)
5070                 goto out;
5071
5072         dirty_rect->x = x;
5073         dirty_rect->y = y;
5074         dirty_rect->width = width;
5075         dirty_rect->height = height;
5076
5077         if (ffu)
5078                 drm_dbg(plane->dev,
5079                         "[PLANE:%d] PSR FFU dirty rect size (%d, %d)\n",
5080                         plane->base.id, width, height);
5081         else
5082                 drm_dbg(plane->dev,
5083                         "[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)",
5084                         plane->base.id, x, y, width, height);
5085
5086 out:
5087         (*i)++;
5088 }
5089
5090 /**
5091  * fill_dc_dirty_rects() - Fill DC dirty regions for PSR selective updates
5092  *
5093  * @plane: DRM plane containing dirty regions that need to be flushed to the eDP
5094  *         remote fb
5095  * @old_plane_state: Old state of @plane
5096  * @new_plane_state: New state of @plane
5097  * @crtc_state: New state of CRTC connected to the @plane
5098  * @flip_addrs: DC flip tracking struct, which also tracts dirty rects
5099  * @dirty_regions_changed: dirty regions changed
5100  *
5101  * For PSR SU, DC informs the DMUB uController of dirty rectangle regions
5102  * (referred to as "damage clips" in DRM nomenclature) that require updating on
5103  * the eDP remote buffer. The responsibility of specifying the dirty regions is
5104  * amdgpu_dm's.
5105  *
5106  * A damage-aware DRM client should fill the FB_DAMAGE_CLIPS property on the
5107  * plane with regions that require flushing to the eDP remote buffer. In
5108  * addition, certain use cases - such as cursor and multi-plane overlay (MPO) -
5109  * implicitly provide damage clips without any client support via the plane
5110  * bounds.
5111  */
5112 static void fill_dc_dirty_rects(struct drm_plane *plane,
5113                                 struct drm_plane_state *old_plane_state,
5114                                 struct drm_plane_state *new_plane_state,
5115                                 struct drm_crtc_state *crtc_state,
5116                                 struct dc_flip_addrs *flip_addrs,
5117                                 bool *dirty_regions_changed)
5118 {
5119         struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
5120         struct rect *dirty_rects = flip_addrs->dirty_rects;
5121         u32 num_clips;
5122         struct drm_mode_rect *clips;
5123         bool bb_changed;
5124         bool fb_changed;
5125         u32 i = 0;
5126         *dirty_regions_changed = false;
5127
5128         /*
5129          * Cursor plane has it's own dirty rect update interface. See
5130          * dcn10_dmub_update_cursor_data and dmub_cmd_update_cursor_info_data
5131          */
5132         if (plane->type == DRM_PLANE_TYPE_CURSOR)
5133                 return;
5134
5135         num_clips = drm_plane_get_damage_clips_count(new_plane_state);
5136         clips = drm_plane_get_damage_clips(new_plane_state);
5137
5138         if (!dm_crtc_state->mpo_requested) {
5139                 if (!num_clips || num_clips > DC_MAX_DIRTY_RECTS)
5140                         goto ffu;
5141
5142                 for (; flip_addrs->dirty_rect_count < num_clips; clips++)
5143                         fill_dc_dirty_rect(new_plane_state->plane,
5144                                            &dirty_rects[flip_addrs->dirty_rect_count],
5145                                            clips->x1, clips->y1,
5146                                            clips->x2 - clips->x1, clips->y2 - clips->y1,
5147                                            &flip_addrs->dirty_rect_count,
5148                                            false);
5149                 return;
5150         }
5151
5152         /*
5153          * MPO is requested. Add entire plane bounding box to dirty rects if
5154          * flipped to or damaged.
5155          *
5156          * If plane is moved or resized, also add old bounding box to dirty
5157          * rects.
5158          */
5159         fb_changed = old_plane_state->fb->base.id !=
5160                      new_plane_state->fb->base.id;
5161         bb_changed = (old_plane_state->crtc_x != new_plane_state->crtc_x ||
5162                       old_plane_state->crtc_y != new_plane_state->crtc_y ||
5163                       old_plane_state->crtc_w != new_plane_state->crtc_w ||
5164                       old_plane_state->crtc_h != new_plane_state->crtc_h);
5165
5166         drm_dbg(plane->dev,
5167                 "[PLANE:%d] PSR bb_changed:%d fb_changed:%d num_clips:%d\n",
5168                 new_plane_state->plane->base.id,
5169                 bb_changed, fb_changed, num_clips);
5170
5171         *dirty_regions_changed = bb_changed;
5172
5173         if (bb_changed) {
5174                 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5175                                    new_plane_state->crtc_x,
5176                                    new_plane_state->crtc_y,
5177                                    new_plane_state->crtc_w,
5178                                    new_plane_state->crtc_h, &i, false);
5179
5180                 /* Add old plane bounding-box if plane is moved or resized */
5181                 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5182                                    old_plane_state->crtc_x,
5183                                    old_plane_state->crtc_y,
5184                                    old_plane_state->crtc_w,
5185                                    old_plane_state->crtc_h, &i, false);
5186         }
5187
5188         if (num_clips) {
5189                 for (; i < num_clips; clips++)
5190                         fill_dc_dirty_rect(new_plane_state->plane,
5191                                            &dirty_rects[i], clips->x1,
5192                                            clips->y1, clips->x2 - clips->x1,
5193                                            clips->y2 - clips->y1, &i, false);
5194         } else if (fb_changed && !bb_changed) {
5195                 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5196                                    new_plane_state->crtc_x,
5197                                    new_plane_state->crtc_y,
5198                                    new_plane_state->crtc_w,
5199                                    new_plane_state->crtc_h, &i, false);
5200         }
5201
5202         if (i > DC_MAX_DIRTY_RECTS)
5203                 goto ffu;
5204
5205         flip_addrs->dirty_rect_count = i;
5206         return;
5207
5208 ffu:
5209         fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[0], 0, 0,
5210                            dm_crtc_state->base.mode.crtc_hdisplay,
5211                            dm_crtc_state->base.mode.crtc_vdisplay,
5212                            &flip_addrs->dirty_rect_count, true);
5213 }
5214
5215 static void update_stream_scaling_settings(const struct drm_display_mode *mode,
5216                                            const struct dm_connector_state *dm_state,
5217                                            struct dc_stream_state *stream)
5218 {
5219         enum amdgpu_rmx_type rmx_type;
5220
5221         struct rect src = { 0 }; /* viewport in composition space*/
5222         struct rect dst = { 0 }; /* stream addressable area */
5223
5224         /* no mode. nothing to be done */
5225         if (!mode)
5226                 return;
5227
5228         /* Full screen scaling by default */
5229         src.width = mode->hdisplay;
5230         src.height = mode->vdisplay;
5231         dst.width = stream->timing.h_addressable;
5232         dst.height = stream->timing.v_addressable;
5233
5234         if (dm_state) {
5235                 rmx_type = dm_state->scaling;
5236                 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
5237                         if (src.width * dst.height <
5238                                         src.height * dst.width) {
5239                                 /* height needs less upscaling/more downscaling */
5240                                 dst.width = src.width *
5241                                                 dst.height / src.height;
5242                         } else {
5243                                 /* width needs less upscaling/more downscaling */
5244                                 dst.height = src.height *
5245                                                 dst.width / src.width;
5246                         }
5247                 } else if (rmx_type == RMX_CENTER) {
5248                         dst = src;
5249                 }
5250
5251                 dst.x = (stream->timing.h_addressable - dst.width) / 2;
5252                 dst.y = (stream->timing.v_addressable - dst.height) / 2;
5253
5254                 if (dm_state->underscan_enable) {
5255                         dst.x += dm_state->underscan_hborder / 2;
5256                         dst.y += dm_state->underscan_vborder / 2;
5257                         dst.width -= dm_state->underscan_hborder;
5258                         dst.height -= dm_state->underscan_vborder;
5259                 }
5260         }
5261
5262         stream->src = src;
5263         stream->dst = dst;
5264
5265         DRM_DEBUG_KMS("Destination Rectangle x:%d  y:%d  width:%d  height:%d\n",
5266                       dst.x, dst.y, dst.width, dst.height);
5267
5268 }
5269
5270 static enum dc_color_depth
5271 convert_color_depth_from_display_info(const struct drm_connector *connector,
5272                                       bool is_y420, int requested_bpc)
5273 {
5274         u8 bpc;
5275
5276         if (is_y420) {
5277                 bpc = 8;
5278
5279                 /* Cap display bpc based on HDMI 2.0 HF-VSDB */
5280                 if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48)
5281                         bpc = 16;
5282                 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36)
5283                         bpc = 12;
5284                 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30)
5285                         bpc = 10;
5286         } else {
5287                 bpc = (uint8_t)connector->display_info.bpc;
5288                 /* Assume 8 bpc by default if no bpc is specified. */
5289                 bpc = bpc ? bpc : 8;
5290         }
5291
5292         if (requested_bpc > 0) {
5293                 /*
5294                  * Cap display bpc based on the user requested value.
5295                  *
5296                  * The value for state->max_bpc may not correctly updated
5297                  * depending on when the connector gets added to the state
5298                  * or if this was called outside of atomic check, so it
5299                  * can't be used directly.
5300                  */
5301                 bpc = min_t(u8, bpc, requested_bpc);
5302
5303                 /* Round down to the nearest even number. */
5304                 bpc = bpc - (bpc & 1);
5305         }
5306
5307         switch (bpc) {
5308         case 0:
5309                 /*
5310                  * Temporary Work around, DRM doesn't parse color depth for
5311                  * EDID revision before 1.4
5312                  * TODO: Fix edid parsing
5313                  */
5314                 return COLOR_DEPTH_888;
5315         case 6:
5316                 return COLOR_DEPTH_666;
5317         case 8:
5318                 return COLOR_DEPTH_888;
5319         case 10:
5320                 return COLOR_DEPTH_101010;
5321         case 12:
5322                 return COLOR_DEPTH_121212;
5323         case 14:
5324                 return COLOR_DEPTH_141414;
5325         case 16:
5326                 return COLOR_DEPTH_161616;
5327         default:
5328                 return COLOR_DEPTH_UNDEFINED;
5329         }
5330 }
5331
5332 static enum dc_aspect_ratio
5333 get_aspect_ratio(const struct drm_display_mode *mode_in)
5334 {
5335         /* 1-1 mapping, since both enums follow the HDMI spec. */
5336         return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio;
5337 }
5338
5339 static enum dc_color_space
5340 get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
5341 {
5342         enum dc_color_space color_space = COLOR_SPACE_SRGB;
5343
5344         switch (dc_crtc_timing->pixel_encoding) {
5345         case PIXEL_ENCODING_YCBCR422:
5346         case PIXEL_ENCODING_YCBCR444:
5347         case PIXEL_ENCODING_YCBCR420:
5348         {
5349                 /*
5350                  * 27030khz is the separation point between HDTV and SDTV
5351                  * according to HDMI spec, we use YCbCr709 and YCbCr601
5352                  * respectively
5353                  */
5354                 if (dc_crtc_timing->pix_clk_100hz > 270300) {
5355                         if (dc_crtc_timing->flags.Y_ONLY)
5356                                 color_space =
5357                                         COLOR_SPACE_YCBCR709_LIMITED;
5358                         else
5359                                 color_space = COLOR_SPACE_YCBCR709;
5360                 } else {
5361                         if (dc_crtc_timing->flags.Y_ONLY)
5362                                 color_space =
5363                                         COLOR_SPACE_YCBCR601_LIMITED;
5364                         else
5365                                 color_space = COLOR_SPACE_YCBCR601;
5366                 }
5367
5368         }
5369         break;
5370         case PIXEL_ENCODING_RGB:
5371                 color_space = COLOR_SPACE_SRGB;
5372                 break;
5373
5374         default:
5375                 WARN_ON(1);
5376                 break;
5377         }
5378
5379         return color_space;
5380 }
5381
5382 static bool adjust_colour_depth_from_display_info(
5383         struct dc_crtc_timing *timing_out,
5384         const struct drm_display_info *info)
5385 {
5386         enum dc_color_depth depth = timing_out->display_color_depth;
5387         int normalized_clk;
5388         do {
5389                 normalized_clk = timing_out->pix_clk_100hz / 10;
5390                 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */
5391                 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
5392                         normalized_clk /= 2;
5393                 /* Adjusting pix clock following on HDMI spec based on colour depth */
5394                 switch (depth) {
5395                 case COLOR_DEPTH_888:
5396                         break;
5397                 case COLOR_DEPTH_101010:
5398                         normalized_clk = (normalized_clk * 30) / 24;
5399                         break;
5400                 case COLOR_DEPTH_121212:
5401                         normalized_clk = (normalized_clk * 36) / 24;
5402                         break;
5403                 case COLOR_DEPTH_161616:
5404                         normalized_clk = (normalized_clk * 48) / 24;
5405                         break;
5406                 default:
5407                         /* The above depths are the only ones valid for HDMI. */
5408                         return false;
5409                 }
5410                 if (normalized_clk <= info->max_tmds_clock) {
5411                         timing_out->display_color_depth = depth;
5412                         return true;
5413                 }
5414         } while (--depth > COLOR_DEPTH_666);
5415         return false;
5416 }
5417
5418 static void fill_stream_properties_from_drm_display_mode(
5419         struct dc_stream_state *stream,
5420         const struct drm_display_mode *mode_in,
5421         const struct drm_connector *connector,
5422         const struct drm_connector_state *connector_state,
5423         const struct dc_stream_state *old_stream,
5424         int requested_bpc)
5425 {
5426         struct dc_crtc_timing *timing_out = &stream->timing;
5427         const struct drm_display_info *info = &connector->display_info;
5428         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
5429         struct hdmi_vendor_infoframe hv_frame;
5430         struct hdmi_avi_infoframe avi_frame;
5431
5432         memset(&hv_frame, 0, sizeof(hv_frame));
5433         memset(&avi_frame, 0, sizeof(avi_frame));
5434
5435         timing_out->h_border_left = 0;
5436         timing_out->h_border_right = 0;
5437         timing_out->v_border_top = 0;
5438         timing_out->v_border_bottom = 0;
5439         /* TODO: un-hardcode */
5440         if (drm_mode_is_420_only(info, mode_in)
5441                         && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5442                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5443         else if (drm_mode_is_420_also(info, mode_in)
5444                         && aconnector->force_yuv420_output)
5445                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5446         else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR444)
5447                         && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5448                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
5449         else
5450                 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
5451
5452         timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
5453         timing_out->display_color_depth = convert_color_depth_from_display_info(
5454                 connector,
5455                 (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420),
5456                 requested_bpc);
5457         timing_out->scan_type = SCANNING_TYPE_NODATA;
5458         timing_out->hdmi_vic = 0;
5459
5460         if (old_stream) {
5461                 timing_out->vic = old_stream->timing.vic;
5462                 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY;
5463                 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY;
5464         } else {
5465                 timing_out->vic = drm_match_cea_mode(mode_in);
5466                 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
5467                         timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
5468                 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
5469                         timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
5470         }
5471
5472         if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
5473                 drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, (struct drm_connector *)connector, mode_in);
5474                 timing_out->vic = avi_frame.video_code;
5475                 drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, (struct drm_connector *)connector, mode_in);
5476                 timing_out->hdmi_vic = hv_frame.vic;
5477         }
5478
5479         if (is_freesync_video_mode(mode_in, aconnector)) {
5480                 timing_out->h_addressable = mode_in->hdisplay;
5481                 timing_out->h_total = mode_in->htotal;
5482                 timing_out->h_sync_width = mode_in->hsync_end - mode_in->hsync_start;
5483                 timing_out->h_front_porch = mode_in->hsync_start - mode_in->hdisplay;
5484                 timing_out->v_total = mode_in->vtotal;
5485                 timing_out->v_addressable = mode_in->vdisplay;
5486                 timing_out->v_front_porch = mode_in->vsync_start - mode_in->vdisplay;
5487                 timing_out->v_sync_width = mode_in->vsync_end - mode_in->vsync_start;
5488                 timing_out->pix_clk_100hz = mode_in->clock * 10;
5489         } else {
5490                 timing_out->h_addressable = mode_in->crtc_hdisplay;
5491                 timing_out->h_total = mode_in->crtc_htotal;
5492                 timing_out->h_sync_width = mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
5493                 timing_out->h_front_porch = mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
5494                 timing_out->v_total = mode_in->crtc_vtotal;
5495                 timing_out->v_addressable = mode_in->crtc_vdisplay;
5496                 timing_out->v_front_porch = mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
5497                 timing_out->v_sync_width = mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
5498                 timing_out->pix_clk_100hz = mode_in->crtc_clock * 10;
5499         }
5500
5501         timing_out->aspect_ratio = get_aspect_ratio(mode_in);
5502
5503         stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
5504         stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
5505         if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
5506                 if (!adjust_colour_depth_from_display_info(timing_out, info) &&
5507                     drm_mode_is_420_also(info, mode_in) &&
5508                     timing_out->pixel_encoding != PIXEL_ENCODING_YCBCR420) {
5509                         timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5510                         adjust_colour_depth_from_display_info(timing_out, info);
5511                 }
5512         }
5513
5514         stream->output_color_space = get_output_color_space(timing_out);
5515 }
5516
5517 static void fill_audio_info(struct audio_info *audio_info,
5518                             const struct drm_connector *drm_connector,
5519                             const struct dc_sink *dc_sink)
5520 {
5521         int i = 0;
5522         int cea_revision = 0;
5523         const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
5524
5525         audio_info->manufacture_id = edid_caps->manufacturer_id;
5526         audio_info->product_id = edid_caps->product_id;
5527
5528         cea_revision = drm_connector->display_info.cea_rev;
5529
5530         strscpy(audio_info->display_name,
5531                 edid_caps->display_name,
5532                 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
5533
5534         if (cea_revision >= 3) {
5535                 audio_info->mode_count = edid_caps->audio_mode_count;
5536
5537                 for (i = 0; i < audio_info->mode_count; ++i) {
5538                         audio_info->modes[i].format_code =
5539                                         (enum audio_format_code)
5540                                         (edid_caps->audio_modes[i].format_code);
5541                         audio_info->modes[i].channel_count =
5542                                         edid_caps->audio_modes[i].channel_count;
5543                         audio_info->modes[i].sample_rates.all =
5544                                         edid_caps->audio_modes[i].sample_rate;
5545                         audio_info->modes[i].sample_size =
5546                                         edid_caps->audio_modes[i].sample_size;
5547                 }
5548         }
5549
5550         audio_info->flags.all = edid_caps->speaker_flags;
5551
5552         /* TODO: We only check for the progressive mode, check for interlace mode too */
5553         if (drm_connector->latency_present[0]) {
5554                 audio_info->video_latency = drm_connector->video_latency[0];
5555                 audio_info->audio_latency = drm_connector->audio_latency[0];
5556         }
5557
5558         /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
5559
5560 }
5561
5562 static void
5563 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
5564                                       struct drm_display_mode *dst_mode)
5565 {
5566         dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
5567         dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
5568         dst_mode->crtc_clock = src_mode->crtc_clock;
5569         dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
5570         dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
5571         dst_mode->crtc_hsync_start =  src_mode->crtc_hsync_start;
5572         dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
5573         dst_mode->crtc_htotal = src_mode->crtc_htotal;
5574         dst_mode->crtc_hskew = src_mode->crtc_hskew;
5575         dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
5576         dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
5577         dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
5578         dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
5579         dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
5580 }
5581
5582 static void
5583 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
5584                                         const struct drm_display_mode *native_mode,
5585                                         bool scale_enabled)
5586 {
5587         if (scale_enabled) {
5588                 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
5589         } else if (native_mode->clock == drm_mode->clock &&
5590                         native_mode->htotal == drm_mode->htotal &&
5591                         native_mode->vtotal == drm_mode->vtotal) {
5592                 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
5593         } else {
5594                 /* no scaling nor amdgpu inserted, no need to patch */
5595         }
5596 }
5597
5598 static struct dc_sink *
5599 create_fake_sink(struct amdgpu_dm_connector *aconnector)
5600 {
5601         struct dc_sink_init_data sink_init_data = { 0 };
5602         struct dc_sink *sink = NULL;
5603         sink_init_data.link = aconnector->dc_link;
5604         sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
5605
5606         sink = dc_sink_create(&sink_init_data);
5607         if (!sink) {
5608                 DRM_ERROR("Failed to create sink!\n");
5609                 return NULL;
5610         }
5611         sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
5612
5613         return sink;
5614 }
5615
5616 static void set_multisync_trigger_params(
5617                 struct dc_stream_state *stream)
5618 {
5619         struct dc_stream_state *master = NULL;
5620
5621         if (stream->triggered_crtc_reset.enabled) {
5622                 master = stream->triggered_crtc_reset.event_source;
5623                 stream->triggered_crtc_reset.event =
5624                         master->timing.flags.VSYNC_POSITIVE_POLARITY ?
5625                         CRTC_EVENT_VSYNC_RISING : CRTC_EVENT_VSYNC_FALLING;
5626                 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_PIXEL;
5627         }
5628 }
5629
5630 static void set_master_stream(struct dc_stream_state *stream_set[],
5631                               int stream_count)
5632 {
5633         int j, highest_rfr = 0, master_stream = 0;
5634
5635         for (j = 0;  j < stream_count; j++) {
5636                 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
5637                         int refresh_rate = 0;
5638
5639                         refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/
5640                                 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
5641                         if (refresh_rate > highest_rfr) {
5642                                 highest_rfr = refresh_rate;
5643                                 master_stream = j;
5644                         }
5645                 }
5646         }
5647         for (j = 0;  j < stream_count; j++) {
5648                 if (stream_set[j])
5649                         stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
5650         }
5651 }
5652
5653 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
5654 {
5655         int i = 0;
5656         struct dc_stream_state *stream;
5657
5658         if (context->stream_count < 2)
5659                 return;
5660         for (i = 0; i < context->stream_count ; i++) {
5661                 if (!context->streams[i])
5662                         continue;
5663                 /*
5664                  * TODO: add a function to read AMD VSDB bits and set
5665                  * crtc_sync_master.multi_sync_enabled flag
5666                  * For now it's set to false
5667                  */
5668         }
5669
5670         set_master_stream(context->streams, context->stream_count);
5671
5672         for (i = 0; i < context->stream_count ; i++) {
5673                 stream = context->streams[i];
5674
5675                 if (!stream)
5676                         continue;
5677
5678                 set_multisync_trigger_params(stream);
5679         }
5680 }
5681
5682 /**
5683  * DOC: FreeSync Video
5684  *
5685  * When a userspace application wants to play a video, the content follows a
5686  * standard format definition that usually specifies the FPS for that format.
5687  * The below list illustrates some video format and the expected FPS,
5688  * respectively:
5689  *
5690  * - TV/NTSC (23.976 FPS)
5691  * - Cinema (24 FPS)
5692  * - TV/PAL (25 FPS)
5693  * - TV/NTSC (29.97 FPS)
5694  * - TV/NTSC (30 FPS)
5695  * - Cinema HFR (48 FPS)
5696  * - TV/PAL (50 FPS)
5697  * - Commonly used (60 FPS)
5698  * - Multiples of 24 (48,72,96 FPS)
5699  *
5700  * The list of standards video format is not huge and can be added to the
5701  * connector modeset list beforehand. With that, userspace can leverage
5702  * FreeSync to extends the front porch in order to attain the target refresh
5703  * rate. Such a switch will happen seamlessly, without screen blanking or
5704  * reprogramming of the output in any other way. If the userspace requests a
5705  * modesetting change compatible with FreeSync modes that only differ in the
5706  * refresh rate, DC will skip the full update and avoid blink during the
5707  * transition. For example, the video player can change the modesetting from
5708  * 60Hz to 30Hz for playing TV/NTSC content when it goes full screen without
5709  * causing any display blink. This same concept can be applied to a mode
5710  * setting change.
5711  */
5712 static struct drm_display_mode *
5713 get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector,
5714                 bool use_probed_modes)
5715 {
5716         struct drm_display_mode *m, *m_pref = NULL;
5717         u16 current_refresh, highest_refresh;
5718         struct list_head *list_head = use_probed_modes ?
5719                 &aconnector->base.probed_modes :
5720                 &aconnector->base.modes;
5721
5722         if (aconnector->freesync_vid_base.clock != 0)
5723                 return &aconnector->freesync_vid_base;
5724
5725         /* Find the preferred mode */
5726         list_for_each_entry (m, list_head, head) {
5727                 if (m->type & DRM_MODE_TYPE_PREFERRED) {
5728                         m_pref = m;
5729                         break;
5730                 }
5731         }
5732
5733         if (!m_pref) {
5734                 /* Probably an EDID with no preferred mode. Fallback to first entry */
5735                 m_pref = list_first_entry_or_null(
5736                                 &aconnector->base.modes, struct drm_display_mode, head);
5737                 if (!m_pref) {
5738                         DRM_DEBUG_DRIVER("No preferred mode found in EDID\n");
5739                         return NULL;
5740                 }
5741         }
5742
5743         highest_refresh = drm_mode_vrefresh(m_pref);
5744
5745         /*
5746          * Find the mode with highest refresh rate with same resolution.
5747          * For some monitors, preferred mode is not the mode with highest
5748          * supported refresh rate.
5749          */
5750         list_for_each_entry (m, list_head, head) {
5751                 current_refresh  = drm_mode_vrefresh(m);
5752
5753                 if (m->hdisplay == m_pref->hdisplay &&
5754                     m->vdisplay == m_pref->vdisplay &&
5755                     highest_refresh < current_refresh) {
5756                         highest_refresh = current_refresh;
5757                         m_pref = m;
5758                 }
5759         }
5760
5761         drm_mode_copy(&aconnector->freesync_vid_base, m_pref);
5762         return m_pref;
5763 }
5764
5765 static bool is_freesync_video_mode(const struct drm_display_mode *mode,
5766                 struct amdgpu_dm_connector *aconnector)
5767 {
5768         struct drm_display_mode *high_mode;
5769         int timing_diff;
5770
5771         high_mode = get_highest_refresh_rate_mode(aconnector, false);
5772         if (!high_mode || !mode)
5773                 return false;
5774
5775         timing_diff = high_mode->vtotal - mode->vtotal;
5776
5777         if (high_mode->clock == 0 || high_mode->clock != mode->clock ||
5778             high_mode->hdisplay != mode->hdisplay ||
5779             high_mode->vdisplay != mode->vdisplay ||
5780             high_mode->hsync_start != mode->hsync_start ||
5781             high_mode->hsync_end != mode->hsync_end ||
5782             high_mode->htotal != mode->htotal ||
5783             high_mode->hskew != mode->hskew ||
5784             high_mode->vscan != mode->vscan ||
5785             high_mode->vsync_start - mode->vsync_start != timing_diff ||
5786             high_mode->vsync_end - mode->vsync_end != timing_diff)
5787                 return false;
5788         else
5789                 return true;
5790 }
5791
5792 static void update_dsc_caps(struct amdgpu_dm_connector *aconnector,
5793                             struct dc_sink *sink, struct dc_stream_state *stream,
5794                             struct dsc_dec_dpcd_caps *dsc_caps)
5795 {
5796         stream->timing.flags.DSC = 0;
5797         dsc_caps->is_dsc_supported = false;
5798
5799         if (aconnector->dc_link && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT ||
5800             sink->sink_signal == SIGNAL_TYPE_EDP)) {
5801                 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE ||
5802                         sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER)
5803                         dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
5804                                 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
5805                                 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
5806                                 dsc_caps);
5807         }
5808 }
5809
5810
5811 static void apply_dsc_policy_for_edp(struct amdgpu_dm_connector *aconnector,
5812                                     struct dc_sink *sink, struct dc_stream_state *stream,
5813                                     struct dsc_dec_dpcd_caps *dsc_caps,
5814                                     uint32_t max_dsc_target_bpp_limit_override)
5815 {
5816         const struct dc_link_settings *verified_link_cap = NULL;
5817         u32 link_bw_in_kbps;
5818         u32 edp_min_bpp_x16, edp_max_bpp_x16;
5819         struct dc *dc = sink->ctx->dc;
5820         struct dc_dsc_bw_range bw_range = {0};
5821         struct dc_dsc_config dsc_cfg = {0};
5822         struct dc_dsc_config_options dsc_options = {0};
5823
5824         dc_dsc_get_default_config_option(dc, &dsc_options);
5825         dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16;
5826
5827         verified_link_cap = dc_link_get_link_cap(stream->link);
5828         link_bw_in_kbps = dc_link_bandwidth_kbps(stream->link, verified_link_cap);
5829         edp_min_bpp_x16 = 8 * 16;
5830         edp_max_bpp_x16 = 8 * 16;
5831
5832         if (edp_max_bpp_x16 > dsc_caps->edp_max_bits_per_pixel)
5833                 edp_max_bpp_x16 = dsc_caps->edp_max_bits_per_pixel;
5834
5835         if (edp_max_bpp_x16 < edp_min_bpp_x16)
5836                 edp_min_bpp_x16 = edp_max_bpp_x16;
5837
5838         if (dc_dsc_compute_bandwidth_range(dc->res_pool->dscs[0],
5839                                 dc->debug.dsc_min_slice_height_override,
5840                                 edp_min_bpp_x16, edp_max_bpp_x16,
5841                                 dsc_caps,
5842                                 &stream->timing,
5843                                 &bw_range)) {
5844
5845                 if (bw_range.max_kbps < link_bw_in_kbps) {
5846                         if (dc_dsc_compute_config(dc->res_pool->dscs[0],
5847                                         dsc_caps,
5848                                         &dsc_options,
5849                                         0,
5850                                         &stream->timing,
5851                                         &dsc_cfg)) {
5852                                 stream->timing.dsc_cfg = dsc_cfg;
5853                                 stream->timing.flags.DSC = 1;
5854                                 stream->timing.dsc_cfg.bits_per_pixel = edp_max_bpp_x16;
5855                         }
5856                         return;
5857                 }
5858         }
5859
5860         if (dc_dsc_compute_config(dc->res_pool->dscs[0],
5861                                 dsc_caps,
5862                                 &dsc_options,
5863                                 link_bw_in_kbps,
5864                                 &stream->timing,
5865                                 &dsc_cfg)) {
5866                 stream->timing.dsc_cfg = dsc_cfg;
5867                 stream->timing.flags.DSC = 1;
5868         }
5869 }
5870
5871
5872 static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector,
5873                                         struct dc_sink *sink, struct dc_stream_state *stream,
5874                                         struct dsc_dec_dpcd_caps *dsc_caps)
5875 {
5876         struct drm_connector *drm_connector = &aconnector->base;
5877         u32 link_bandwidth_kbps;
5878         struct dc *dc = sink->ctx->dc;
5879         u32 max_supported_bw_in_kbps, timing_bw_in_kbps;
5880         u32 dsc_max_supported_bw_in_kbps;
5881         u32 max_dsc_target_bpp_limit_override =
5882                 drm_connector->display_info.max_dsc_bpp;
5883         struct dc_dsc_config_options dsc_options = {0};
5884
5885         dc_dsc_get_default_config_option(dc, &dsc_options);
5886         dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16;
5887
5888         link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
5889                                                         dc_link_get_link_cap(aconnector->dc_link));
5890
5891         /* Set DSC policy according to dsc_clock_en */
5892         dc_dsc_policy_set_enable_dsc_when_not_needed(
5893                 aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE);
5894
5895         if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_EDP &&
5896             !aconnector->dc_link->panel_config.dsc.disable_dsc_edp &&
5897             dc->caps.edp_dsc_support && aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE) {
5898
5899                 apply_dsc_policy_for_edp(aconnector, sink, stream, dsc_caps, max_dsc_target_bpp_limit_override);
5900
5901         } else if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) {
5902                 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) {
5903                         if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
5904                                                 dsc_caps,
5905                                                 &dsc_options,
5906                                                 link_bandwidth_kbps,
5907                                                 &stream->timing,
5908                                                 &stream->timing.dsc_cfg)) {
5909                                 stream->timing.flags.DSC = 1;
5910                                 DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from SST RX\n", __func__, drm_connector->name);
5911                         }
5912                 } else if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) {
5913                         timing_bw_in_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing);
5914                         max_supported_bw_in_kbps = link_bandwidth_kbps;
5915                         dsc_max_supported_bw_in_kbps = link_bandwidth_kbps;
5916
5917                         if (timing_bw_in_kbps > max_supported_bw_in_kbps &&
5918                                         max_supported_bw_in_kbps > 0 &&
5919                                         dsc_max_supported_bw_in_kbps > 0)
5920                                 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
5921                                                 dsc_caps,
5922                                                 &dsc_options,
5923                                                 dsc_max_supported_bw_in_kbps,
5924                                                 &stream->timing,
5925                                                 &stream->timing.dsc_cfg)) {
5926                                         stream->timing.flags.DSC = 1;
5927                                         DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from DP-HDMI PCON\n",
5928                                                                          __func__, drm_connector->name);
5929                                 }
5930                 }
5931         }
5932
5933         /* Overwrite the stream flag if DSC is enabled through debugfs */
5934         if (aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE)
5935                 stream->timing.flags.DSC = 1;
5936
5937         if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_h)
5938                 stream->timing.dsc_cfg.num_slices_h = aconnector->dsc_settings.dsc_num_slices_h;
5939
5940         if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_v)
5941                 stream->timing.dsc_cfg.num_slices_v = aconnector->dsc_settings.dsc_num_slices_v;
5942
5943         if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_bits_per_pixel)
5944                 stream->timing.dsc_cfg.bits_per_pixel = aconnector->dsc_settings.dsc_bits_per_pixel;
5945 }
5946
5947 static struct dc_stream_state *
5948 create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
5949                        const struct drm_display_mode *drm_mode,
5950                        const struct dm_connector_state *dm_state,
5951                        const struct dc_stream_state *old_stream,
5952                        int requested_bpc)
5953 {
5954         struct drm_display_mode *preferred_mode = NULL;
5955         struct drm_connector *drm_connector;
5956         const struct drm_connector_state *con_state =
5957                 dm_state ? &dm_state->base : NULL;
5958         struct dc_stream_state *stream = NULL;
5959         struct drm_display_mode mode;
5960         struct drm_display_mode saved_mode;
5961         struct drm_display_mode *freesync_mode = NULL;
5962         bool native_mode_found = false;
5963         bool recalculate_timing = false;
5964         bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false;
5965         int mode_refresh;
5966         int preferred_refresh = 0;
5967         enum color_transfer_func tf = TRANSFER_FUNC_UNKNOWN;
5968         struct dsc_dec_dpcd_caps dsc_caps;
5969
5970         struct dc_sink *sink = NULL;
5971
5972         drm_mode_init(&mode, drm_mode);
5973         memset(&saved_mode, 0, sizeof(saved_mode));
5974
5975         if (aconnector == NULL) {
5976                 DRM_ERROR("aconnector is NULL!\n");
5977                 return stream;
5978         }
5979
5980         drm_connector = &aconnector->base;
5981
5982         if (!aconnector->dc_sink) {
5983                 sink = create_fake_sink(aconnector);
5984                 if (!sink)
5985                         return stream;
5986         } else {
5987                 sink = aconnector->dc_sink;
5988                 dc_sink_retain(sink);
5989         }
5990
5991         stream = dc_create_stream_for_sink(sink);
5992
5993         if (stream == NULL) {
5994                 DRM_ERROR("Failed to create stream for sink!\n");
5995                 goto finish;
5996         }
5997
5998         stream->dm_stream_context = aconnector;
5999
6000         stream->timing.flags.LTE_340MCSC_SCRAMBLE =
6001                 drm_connector->display_info.hdmi.scdc.scrambling.low_rates;
6002
6003         list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
6004                 /* Search for preferred mode */
6005                 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
6006                         native_mode_found = true;
6007                         break;
6008                 }
6009         }
6010         if (!native_mode_found)
6011                 preferred_mode = list_first_entry_or_null(
6012                                 &aconnector->base.modes,
6013                                 struct drm_display_mode,
6014                                 head);
6015
6016         mode_refresh = drm_mode_vrefresh(&mode);
6017
6018         if (preferred_mode == NULL) {
6019                 /*
6020                  * This may not be an error, the use case is when we have no
6021                  * usermode calls to reset and set mode upon hotplug. In this
6022                  * case, we call set mode ourselves to restore the previous mode
6023                  * and the modelist may not be filled in in time.
6024                  */
6025                 DRM_DEBUG_DRIVER("No preferred mode found\n");
6026         } else {
6027                 recalculate_timing = amdgpu_freesync_vid_mode &&
6028                                  is_freesync_video_mode(&mode, aconnector);
6029                 if (recalculate_timing) {
6030                         freesync_mode = get_highest_refresh_rate_mode(aconnector, false);
6031                         drm_mode_copy(&saved_mode, &mode);
6032                         drm_mode_copy(&mode, freesync_mode);
6033                 } else {
6034                         decide_crtc_timing_for_drm_display_mode(
6035                                         &mode, preferred_mode, scale);
6036
6037                         preferred_refresh = drm_mode_vrefresh(preferred_mode);
6038                 }
6039         }
6040
6041         if (recalculate_timing)
6042                 drm_mode_set_crtcinfo(&saved_mode, 0);
6043         else if (!dm_state)
6044                 drm_mode_set_crtcinfo(&mode, 0);
6045
6046         /*
6047         * If scaling is enabled and refresh rate didn't change
6048         * we copy the vic and polarities of the old timings
6049         */
6050         if (!scale || mode_refresh != preferred_refresh)
6051                 fill_stream_properties_from_drm_display_mode(
6052                         stream, &mode, &aconnector->base, con_state, NULL,
6053                         requested_bpc);
6054         else
6055                 fill_stream_properties_from_drm_display_mode(
6056                         stream, &mode, &aconnector->base, con_state, old_stream,
6057                         requested_bpc);
6058
6059         if (aconnector->timing_changed) {
6060                 DC_LOG_DEBUG("%s: overriding timing for automated test, bpc %d, changing to %d\n",
6061                                 __func__,
6062                                 stream->timing.display_color_depth,
6063                                 aconnector->timing_requested->display_color_depth);
6064                 stream->timing = *aconnector->timing_requested;
6065         }
6066
6067         /* SST DSC determination policy */
6068         update_dsc_caps(aconnector, sink, stream, &dsc_caps);
6069         if (aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE && dsc_caps.is_dsc_supported)
6070                 apply_dsc_policy_for_stream(aconnector, sink, stream, &dsc_caps);
6071
6072         update_stream_scaling_settings(&mode, dm_state, stream);
6073
6074         fill_audio_info(
6075                 &stream->audio_info,
6076                 drm_connector,
6077                 sink);
6078
6079         update_stream_signal(stream, sink);
6080
6081         if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
6082                 mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket);
6083
6084         if (stream->link->psr_settings.psr_feature_enabled) {
6085                 //
6086                 // should decide stream support vsc sdp colorimetry capability
6087                 // before building vsc info packet
6088                 //
6089                 stream->use_vsc_sdp_for_colorimetry = false;
6090                 if (aconnector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
6091                         stream->use_vsc_sdp_for_colorimetry =
6092                                 aconnector->dc_sink->is_vsc_sdp_colorimetry_supported;
6093                 } else {
6094                         if (stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED)
6095                                 stream->use_vsc_sdp_for_colorimetry = true;
6096                 }
6097                 if (stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22)
6098                         tf = TRANSFER_FUNC_GAMMA_22;
6099                 mod_build_vsc_infopacket(stream, &stream->vsc_infopacket, stream->output_color_space, tf);
6100                 aconnector->psr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY;
6101
6102         }
6103 finish:
6104         dc_sink_release(sink);
6105
6106         return stream;
6107 }
6108
6109 static enum drm_connector_status
6110 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
6111 {
6112         bool connected;
6113         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6114
6115         /*
6116          * Notes:
6117          * 1. This interface is NOT called in context of HPD irq.
6118          * 2. This interface *is called* in context of user-mode ioctl. Which
6119          * makes it a bad place for *any* MST-related activity.
6120          */
6121
6122         if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
6123             !aconnector->fake_enable)
6124                 connected = (aconnector->dc_sink != NULL);
6125         else
6126                 connected = (aconnector->base.force == DRM_FORCE_ON ||
6127                                 aconnector->base.force == DRM_FORCE_ON_DIGITAL);
6128
6129         update_subconnector_property(aconnector);
6130
6131         return (connected ? connector_status_connected :
6132                         connector_status_disconnected);
6133 }
6134
6135 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
6136                                             struct drm_connector_state *connector_state,
6137                                             struct drm_property *property,
6138                                             uint64_t val)
6139 {
6140         struct drm_device *dev = connector->dev;
6141         struct amdgpu_device *adev = drm_to_adev(dev);
6142         struct dm_connector_state *dm_old_state =
6143                 to_dm_connector_state(connector->state);
6144         struct dm_connector_state *dm_new_state =
6145                 to_dm_connector_state(connector_state);
6146
6147         int ret = -EINVAL;
6148
6149         if (property == dev->mode_config.scaling_mode_property) {
6150                 enum amdgpu_rmx_type rmx_type;
6151
6152                 switch (val) {
6153                 case DRM_MODE_SCALE_CENTER:
6154                         rmx_type = RMX_CENTER;
6155                         break;
6156                 case DRM_MODE_SCALE_ASPECT:
6157                         rmx_type = RMX_ASPECT;
6158                         break;
6159                 case DRM_MODE_SCALE_FULLSCREEN:
6160                         rmx_type = RMX_FULL;
6161                         break;
6162                 case DRM_MODE_SCALE_NONE:
6163                 default:
6164                         rmx_type = RMX_OFF;
6165                         break;
6166                 }
6167
6168                 if (dm_old_state->scaling == rmx_type)
6169                         return 0;
6170
6171                 dm_new_state->scaling = rmx_type;
6172                 ret = 0;
6173         } else if (property == adev->mode_info.underscan_hborder_property) {
6174                 dm_new_state->underscan_hborder = val;
6175                 ret = 0;
6176         } else if (property == adev->mode_info.underscan_vborder_property) {
6177                 dm_new_state->underscan_vborder = val;
6178                 ret = 0;
6179         } else if (property == adev->mode_info.underscan_property) {
6180                 dm_new_state->underscan_enable = val;
6181                 ret = 0;
6182         } else if (property == adev->mode_info.abm_level_property) {
6183                 dm_new_state->abm_level = val;
6184                 ret = 0;
6185         }
6186
6187         return ret;
6188 }
6189
6190 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
6191                                             const struct drm_connector_state *state,
6192                                             struct drm_property *property,
6193                                             uint64_t *val)
6194 {
6195         struct drm_device *dev = connector->dev;
6196         struct amdgpu_device *adev = drm_to_adev(dev);
6197         struct dm_connector_state *dm_state =
6198                 to_dm_connector_state(state);
6199         int ret = -EINVAL;
6200
6201         if (property == dev->mode_config.scaling_mode_property) {
6202                 switch (dm_state->scaling) {
6203                 case RMX_CENTER:
6204                         *val = DRM_MODE_SCALE_CENTER;
6205                         break;
6206                 case RMX_ASPECT:
6207                         *val = DRM_MODE_SCALE_ASPECT;
6208                         break;
6209                 case RMX_FULL:
6210                         *val = DRM_MODE_SCALE_FULLSCREEN;
6211                         break;
6212                 case RMX_OFF:
6213                 default:
6214                         *val = DRM_MODE_SCALE_NONE;
6215                         break;
6216                 }
6217                 ret = 0;
6218         } else if (property == adev->mode_info.underscan_hborder_property) {
6219                 *val = dm_state->underscan_hborder;
6220                 ret = 0;
6221         } else if (property == adev->mode_info.underscan_vborder_property) {
6222                 *val = dm_state->underscan_vborder;
6223                 ret = 0;
6224         } else if (property == adev->mode_info.underscan_property) {
6225                 *val = dm_state->underscan_enable;
6226                 ret = 0;
6227         } else if (property == adev->mode_info.abm_level_property) {
6228                 *val = dm_state->abm_level;
6229                 ret = 0;
6230         }
6231
6232         return ret;
6233 }
6234
6235 static void amdgpu_dm_connector_unregister(struct drm_connector *connector)
6236 {
6237         struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector);
6238
6239         drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux);
6240 }
6241
6242 static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
6243 {
6244         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6245         const struct dc_link *link = aconnector->dc_link;
6246         struct amdgpu_device *adev = drm_to_adev(connector->dev);
6247         struct amdgpu_display_manager *dm = &adev->dm;
6248         int i;
6249
6250         /*
6251          * Call only if mst_mgr was initialized before since it's not done
6252          * for all connector types.
6253          */
6254         if (aconnector->mst_mgr.dev)
6255                 drm_dp_mst_topology_mgr_destroy(&aconnector->mst_mgr);
6256
6257         for (i = 0; i < dm->num_of_edps; i++) {
6258                 if ((link == dm->backlight_link[i]) && dm->backlight_dev[i]) {
6259                         backlight_device_unregister(dm->backlight_dev[i]);
6260                         dm->backlight_dev[i] = NULL;
6261                 }
6262         }
6263
6264         if (aconnector->dc_em_sink)
6265                 dc_sink_release(aconnector->dc_em_sink);
6266         aconnector->dc_em_sink = NULL;
6267         if (aconnector->dc_sink)
6268                 dc_sink_release(aconnector->dc_sink);
6269         aconnector->dc_sink = NULL;
6270
6271         drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux);
6272         drm_connector_unregister(connector);
6273         drm_connector_cleanup(connector);
6274         if (aconnector->i2c) {
6275                 i2c_del_adapter(&aconnector->i2c->base);
6276                 kfree(aconnector->i2c);
6277         }
6278         kfree(aconnector->dm_dp_aux.aux.name);
6279
6280         kfree(connector);
6281 }
6282
6283 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
6284 {
6285         struct dm_connector_state *state =
6286                 to_dm_connector_state(connector->state);
6287
6288         if (connector->state)
6289                 __drm_atomic_helper_connector_destroy_state(connector->state);
6290
6291         kfree(state);
6292
6293         state = kzalloc(sizeof(*state), GFP_KERNEL);
6294
6295         if (state) {
6296                 state->scaling = RMX_OFF;
6297                 state->underscan_enable = false;
6298                 state->underscan_hborder = 0;
6299                 state->underscan_vborder = 0;
6300                 state->base.max_requested_bpc = 8;
6301                 state->vcpi_slots = 0;
6302                 state->pbn = 0;
6303
6304                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
6305                         state->abm_level = amdgpu_dm_abm_level;
6306
6307                 __drm_atomic_helper_connector_reset(connector, &state->base);
6308         }
6309 }
6310
6311 struct drm_connector_state *
6312 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
6313 {
6314         struct dm_connector_state *state =
6315                 to_dm_connector_state(connector->state);
6316
6317         struct dm_connector_state *new_state =
6318                         kmemdup(state, sizeof(*state), GFP_KERNEL);
6319
6320         if (!new_state)
6321                 return NULL;
6322
6323         __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
6324
6325         new_state->freesync_capable = state->freesync_capable;
6326         new_state->abm_level = state->abm_level;
6327         new_state->scaling = state->scaling;
6328         new_state->underscan_enable = state->underscan_enable;
6329         new_state->underscan_hborder = state->underscan_hborder;
6330         new_state->underscan_vborder = state->underscan_vborder;
6331         new_state->vcpi_slots = state->vcpi_slots;
6332         new_state->pbn = state->pbn;
6333         return &new_state->base;
6334 }
6335
6336 static int
6337 amdgpu_dm_connector_late_register(struct drm_connector *connector)
6338 {
6339         struct amdgpu_dm_connector *amdgpu_dm_connector =
6340                 to_amdgpu_dm_connector(connector);
6341         int r;
6342
6343         if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
6344             (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
6345                 amdgpu_dm_connector->dm_dp_aux.aux.dev = connector->kdev;
6346                 r = drm_dp_aux_register(&amdgpu_dm_connector->dm_dp_aux.aux);
6347                 if (r)
6348                         return r;
6349         }
6350
6351 #if defined(CONFIG_DEBUG_FS)
6352         connector_debugfs_init(amdgpu_dm_connector);
6353 #endif
6354
6355         return 0;
6356 }
6357
6358 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
6359         .reset = amdgpu_dm_connector_funcs_reset,
6360         .detect = amdgpu_dm_connector_detect,
6361         .fill_modes = drm_helper_probe_single_connector_modes,
6362         .destroy = amdgpu_dm_connector_destroy,
6363         .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
6364         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
6365         .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
6366         .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
6367         .late_register = amdgpu_dm_connector_late_register,
6368         .early_unregister = amdgpu_dm_connector_unregister
6369 };
6370
6371 static int get_modes(struct drm_connector *connector)
6372 {
6373         return amdgpu_dm_connector_get_modes(connector);
6374 }
6375
6376 static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
6377 {
6378         struct dc_sink_init_data init_params = {
6379                         .link = aconnector->dc_link,
6380                         .sink_signal = SIGNAL_TYPE_VIRTUAL
6381         };
6382         struct edid *edid;
6383
6384         if (!aconnector->base.edid_blob_ptr) {
6385                 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
6386                                 aconnector->base.name);
6387
6388                 aconnector->base.force = DRM_FORCE_OFF;
6389                 return;
6390         }
6391
6392         edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
6393
6394         aconnector->edid = edid;
6395
6396         aconnector->dc_em_sink = dc_link_add_remote_sink(
6397                 aconnector->dc_link,
6398                 (uint8_t *)edid,
6399                 (edid->extensions + 1) * EDID_LENGTH,
6400                 &init_params);
6401
6402         if (aconnector->base.force == DRM_FORCE_ON) {
6403                 aconnector->dc_sink = aconnector->dc_link->local_sink ?
6404                 aconnector->dc_link->local_sink :
6405                 aconnector->dc_em_sink;
6406                 dc_sink_retain(aconnector->dc_sink);
6407         }
6408 }
6409
6410 static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
6411 {
6412         struct dc_link *link = (struct dc_link *)aconnector->dc_link;
6413
6414         /*
6415          * In case of headless boot with force on for DP managed connector
6416          * Those settings have to be != 0 to get initial modeset
6417          */
6418         if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
6419                 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
6420                 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
6421         }
6422
6423         create_eml_sink(aconnector);
6424 }
6425
6426 static enum dc_status dm_validate_stream_and_context(struct dc *dc,
6427                                                 struct dc_stream_state *stream)
6428 {
6429         enum dc_status dc_result = DC_ERROR_UNEXPECTED;
6430         struct dc_plane_state *dc_plane_state = NULL;
6431         struct dc_state *dc_state = NULL;
6432
6433         if (!stream)
6434                 goto cleanup;
6435
6436         dc_plane_state = dc_create_plane_state(dc);
6437         if (!dc_plane_state)
6438                 goto cleanup;
6439
6440         dc_state = dc_create_state(dc);
6441         if (!dc_state)
6442                 goto cleanup;
6443
6444         /* populate stream to plane */
6445         dc_plane_state->src_rect.height  = stream->src.height;
6446         dc_plane_state->src_rect.width   = stream->src.width;
6447         dc_plane_state->dst_rect.height  = stream->src.height;
6448         dc_plane_state->dst_rect.width   = stream->src.width;
6449         dc_plane_state->clip_rect.height = stream->src.height;
6450         dc_plane_state->clip_rect.width  = stream->src.width;
6451         dc_plane_state->plane_size.surface_pitch = ((stream->src.width + 255) / 256) * 256;
6452         dc_plane_state->plane_size.surface_size.height = stream->src.height;
6453         dc_plane_state->plane_size.surface_size.width  = stream->src.width;
6454         dc_plane_state->plane_size.chroma_size.height  = stream->src.height;
6455         dc_plane_state->plane_size.chroma_size.width   = stream->src.width;
6456         dc_plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
6457         dc_plane_state->tiling_info.gfx9.swizzle = DC_SW_UNKNOWN;
6458         dc_plane_state->rotation = ROTATION_ANGLE_0;
6459         dc_plane_state->is_tiling_rotated = false;
6460         dc_plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_LINEAR_GENERAL;
6461
6462         dc_result = dc_validate_stream(dc, stream);
6463         if (dc_result == DC_OK)
6464                 dc_result = dc_validate_plane(dc, dc_plane_state);
6465
6466         if (dc_result == DC_OK)
6467                 dc_result = dc_add_stream_to_ctx(dc, dc_state, stream);
6468
6469         if (dc_result == DC_OK && !dc_add_plane_to_context(
6470                                                 dc,
6471                                                 stream,
6472                                                 dc_plane_state,
6473                                                 dc_state))
6474                 dc_result = DC_FAIL_ATTACH_SURFACES;
6475
6476         if (dc_result == DC_OK)
6477                 dc_result = dc_validate_global_state(dc, dc_state, true);
6478
6479 cleanup:
6480         if (dc_state)
6481                 dc_release_state(dc_state);
6482
6483         if (dc_plane_state)
6484                 dc_plane_state_release(dc_plane_state);
6485
6486         return dc_result;
6487 }
6488
6489 struct dc_stream_state *
6490 create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector,
6491                                 const struct drm_display_mode *drm_mode,
6492                                 const struct dm_connector_state *dm_state,
6493                                 const struct dc_stream_state *old_stream)
6494 {
6495         struct drm_connector *connector = &aconnector->base;
6496         struct amdgpu_device *adev = drm_to_adev(connector->dev);
6497         struct dc_stream_state *stream;
6498         const struct drm_connector_state *drm_state = dm_state ? &dm_state->base : NULL;
6499         int requested_bpc = drm_state ? drm_state->max_requested_bpc : 8;
6500         enum dc_status dc_result = DC_OK;
6501
6502         do {
6503                 stream = create_stream_for_sink(aconnector, drm_mode,
6504                                                 dm_state, old_stream,
6505                                                 requested_bpc);
6506                 if (stream == NULL) {
6507                         DRM_ERROR("Failed to create stream for sink!\n");
6508                         break;
6509                 }
6510
6511                 dc_result = dc_validate_stream(adev->dm.dc, stream);
6512                 if (dc_result == DC_OK && stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
6513                         dc_result = dm_dp_mst_is_port_support_mode(aconnector, stream);
6514
6515                 if (dc_result == DC_OK)
6516                         dc_result = dm_validate_stream_and_context(adev->dm.dc, stream);
6517
6518                 if (dc_result != DC_OK) {
6519                         DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n",
6520                                       drm_mode->hdisplay,
6521                                       drm_mode->vdisplay,
6522                                       drm_mode->clock,
6523                                       dc_result,
6524                                       dc_status_to_str(dc_result));
6525
6526                         dc_stream_release(stream);
6527                         stream = NULL;
6528                         requested_bpc -= 2; /* lower bpc to retry validation */
6529                 }
6530
6531         } while (stream == NULL && requested_bpc >= 6);
6532
6533         if (dc_result == DC_FAIL_ENC_VALIDATE && !aconnector->force_yuv420_output) {
6534                 DRM_DEBUG_KMS("Retry forcing YCbCr420 encoding\n");
6535
6536                 aconnector->force_yuv420_output = true;
6537                 stream = create_validate_stream_for_sink(aconnector, drm_mode,
6538                                                 dm_state, old_stream);
6539                 aconnector->force_yuv420_output = false;
6540         }
6541
6542         return stream;
6543 }
6544
6545 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
6546                                    struct drm_display_mode *mode)
6547 {
6548         int result = MODE_ERROR;
6549         struct dc_sink *dc_sink;
6550         /* TODO: Unhardcode stream count */
6551         struct dc_stream_state *stream;
6552         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6553
6554         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
6555                         (mode->flags & DRM_MODE_FLAG_DBLSCAN))
6556                 return result;
6557
6558         /*
6559          * Only run this the first time mode_valid is called to initilialize
6560          * EDID mgmt
6561          */
6562         if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
6563                 !aconnector->dc_em_sink)
6564                 handle_edid_mgmt(aconnector);
6565
6566         dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
6567
6568         if (dc_sink == NULL && aconnector->base.force != DRM_FORCE_ON_DIGITAL &&
6569                                 aconnector->base.force != DRM_FORCE_ON) {
6570                 DRM_ERROR("dc_sink is NULL!\n");
6571                 goto fail;
6572         }
6573
6574         stream = create_validate_stream_for_sink(aconnector, mode, NULL, NULL);
6575         if (stream) {
6576                 dc_stream_release(stream);
6577                 result = MODE_OK;
6578         }
6579
6580 fail:
6581         /* TODO: error handling*/
6582         return result;
6583 }
6584
6585 static int fill_hdr_info_packet(const struct drm_connector_state *state,
6586                                 struct dc_info_packet *out)
6587 {
6588         struct hdmi_drm_infoframe frame;
6589         unsigned char buf[30]; /* 26 + 4 */
6590         ssize_t len;
6591         int ret, i;
6592
6593         memset(out, 0, sizeof(*out));
6594
6595         if (!state->hdr_output_metadata)
6596                 return 0;
6597
6598         ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state);
6599         if (ret)
6600                 return ret;
6601
6602         len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf));
6603         if (len < 0)
6604                 return (int)len;
6605
6606         /* Static metadata is a fixed 26 bytes + 4 byte header. */
6607         if (len != 30)
6608                 return -EINVAL;
6609
6610         /* Prepare the infopacket for DC. */
6611         switch (state->connector->connector_type) {
6612         case DRM_MODE_CONNECTOR_HDMIA:
6613                 out->hb0 = 0x87; /* type */
6614                 out->hb1 = 0x01; /* version */
6615                 out->hb2 = 0x1A; /* length */
6616                 out->sb[0] = buf[3]; /* checksum */
6617                 i = 1;
6618                 break;
6619
6620         case DRM_MODE_CONNECTOR_DisplayPort:
6621         case DRM_MODE_CONNECTOR_eDP:
6622                 out->hb0 = 0x00; /* sdp id, zero */
6623                 out->hb1 = 0x87; /* type */
6624                 out->hb2 = 0x1D; /* payload len - 1 */
6625                 out->hb3 = (0x13 << 2); /* sdp version */
6626                 out->sb[0] = 0x01; /* version */
6627                 out->sb[1] = 0x1A; /* length */
6628                 i = 2;
6629                 break;
6630
6631         default:
6632                 return -EINVAL;
6633         }
6634
6635         memcpy(&out->sb[i], &buf[4], 26);
6636         out->valid = true;
6637
6638         print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb,
6639                        sizeof(out->sb), false);
6640
6641         return 0;
6642 }
6643
6644 static int
6645 amdgpu_dm_connector_atomic_check(struct drm_connector *conn,
6646                                  struct drm_atomic_state *state)
6647 {
6648         struct drm_connector_state *new_con_state =
6649                 drm_atomic_get_new_connector_state(state, conn);
6650         struct drm_connector_state *old_con_state =
6651                 drm_atomic_get_old_connector_state(state, conn);
6652         struct drm_crtc *crtc = new_con_state->crtc;
6653         struct drm_crtc_state *new_crtc_state;
6654         struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(conn);
6655         int ret;
6656
6657         trace_amdgpu_dm_connector_atomic_check(new_con_state);
6658
6659         if (conn->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
6660                 ret = drm_dp_mst_root_conn_atomic_check(new_con_state, &aconn->mst_mgr);
6661                 if (ret < 0)
6662                         return ret;
6663         }
6664
6665         if (!crtc)
6666                 return 0;
6667
6668         if (!drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state)) {
6669                 struct dc_info_packet hdr_infopacket;
6670
6671                 ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket);
6672                 if (ret)
6673                         return ret;
6674
6675                 new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
6676                 if (IS_ERR(new_crtc_state))
6677                         return PTR_ERR(new_crtc_state);
6678
6679                 /*
6680                  * DC considers the stream backends changed if the
6681                  * static metadata changes. Forcing the modeset also
6682                  * gives a simple way for userspace to switch from
6683                  * 8bpc to 10bpc when setting the metadata to enter
6684                  * or exit HDR.
6685                  *
6686                  * Changing the static metadata after it's been
6687                  * set is permissible, however. So only force a
6688                  * modeset if we're entering or exiting HDR.
6689                  */
6690                 new_crtc_state->mode_changed =
6691                         !old_con_state->hdr_output_metadata ||
6692                         !new_con_state->hdr_output_metadata;
6693         }
6694
6695         return 0;
6696 }
6697
6698 static const struct drm_connector_helper_funcs
6699 amdgpu_dm_connector_helper_funcs = {
6700         /*
6701          * If hotplugging a second bigger display in FB Con mode, bigger resolution
6702          * modes will be filtered by drm_mode_validate_size(), and those modes
6703          * are missing after user start lightdm. So we need to renew modes list.
6704          * in get_modes call back, not just return the modes count
6705          */
6706         .get_modes = get_modes,
6707         .mode_valid = amdgpu_dm_connector_mode_valid,
6708         .atomic_check = amdgpu_dm_connector_atomic_check,
6709 };
6710
6711 static void dm_encoder_helper_disable(struct drm_encoder *encoder)
6712 {
6713
6714 }
6715
6716 int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth)
6717 {
6718         switch (display_color_depth) {
6719         case COLOR_DEPTH_666:
6720                 return 6;
6721         case COLOR_DEPTH_888:
6722                 return 8;
6723         case COLOR_DEPTH_101010:
6724                 return 10;
6725         case COLOR_DEPTH_121212:
6726                 return 12;
6727         case COLOR_DEPTH_141414:
6728                 return 14;
6729         case COLOR_DEPTH_161616:
6730                 return 16;
6731         default:
6732                 break;
6733         }
6734         return 0;
6735 }
6736
6737 static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
6738                                           struct drm_crtc_state *crtc_state,
6739                                           struct drm_connector_state *conn_state)
6740 {
6741         struct drm_atomic_state *state = crtc_state->state;
6742         struct drm_connector *connector = conn_state->connector;
6743         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6744         struct dm_connector_state *dm_new_connector_state = to_dm_connector_state(conn_state);
6745         const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
6746         struct drm_dp_mst_topology_mgr *mst_mgr;
6747         struct drm_dp_mst_port *mst_port;
6748         struct drm_dp_mst_topology_state *mst_state;
6749         enum dc_color_depth color_depth;
6750         int clock, bpp = 0;
6751         bool is_y420 = false;
6752
6753         if (!aconnector->mst_output_port || !aconnector->dc_sink)
6754                 return 0;
6755
6756         mst_port = aconnector->mst_output_port;
6757         mst_mgr = &aconnector->mst_root->mst_mgr;
6758
6759         if (!crtc_state->connectors_changed && !crtc_state->mode_changed)
6760                 return 0;
6761
6762         mst_state = drm_atomic_get_mst_topology_state(state, mst_mgr);
6763         if (IS_ERR(mst_state))
6764                 return PTR_ERR(mst_state);
6765
6766         if (!mst_state->pbn_div)
6767                 mst_state->pbn_div = dm_mst_get_pbn_divider(aconnector->mst_root->dc_link);
6768
6769         if (!state->duplicated) {
6770                 int max_bpc = conn_state->max_requested_bpc;
6771                 is_y420 = drm_mode_is_420_also(&connector->display_info, adjusted_mode) &&
6772                           aconnector->force_yuv420_output;
6773                 color_depth = convert_color_depth_from_display_info(connector,
6774                                                                     is_y420,
6775                                                                     max_bpc);
6776                 bpp = convert_dc_color_depth_into_bpc(color_depth) * 3;
6777                 clock = adjusted_mode->clock;
6778                 dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp, false);
6779         }
6780
6781         dm_new_connector_state->vcpi_slots =
6782                 drm_dp_atomic_find_time_slots(state, mst_mgr, mst_port,
6783                                               dm_new_connector_state->pbn);
6784         if (dm_new_connector_state->vcpi_slots < 0) {
6785                 DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots);
6786                 return dm_new_connector_state->vcpi_slots;
6787         }
6788         return 0;
6789 }
6790
6791 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
6792         .disable = dm_encoder_helper_disable,
6793         .atomic_check = dm_encoder_helper_atomic_check
6794 };
6795
6796 static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state,
6797                                             struct dc_state *dc_state,
6798                                             struct dsc_mst_fairness_vars *vars)
6799 {
6800         struct dc_stream_state *stream = NULL;
6801         struct drm_connector *connector;
6802         struct drm_connector_state *new_con_state;
6803         struct amdgpu_dm_connector *aconnector;
6804         struct dm_connector_state *dm_conn_state;
6805         int i, j, ret;
6806         int vcpi, pbn_div, pbn, slot_num = 0;
6807
6808         for_each_new_connector_in_state(state, connector, new_con_state, i) {
6809
6810                 aconnector = to_amdgpu_dm_connector(connector);
6811
6812                 if (!aconnector->mst_output_port)
6813                         continue;
6814
6815                 if (!new_con_state || !new_con_state->crtc)
6816                         continue;
6817
6818                 dm_conn_state = to_dm_connector_state(new_con_state);
6819
6820                 for (j = 0; j < dc_state->stream_count; j++) {
6821                         stream = dc_state->streams[j];
6822                         if (!stream)
6823                                 continue;
6824
6825                         if ((struct amdgpu_dm_connector *)stream->dm_stream_context == aconnector)
6826                                 break;
6827
6828                         stream = NULL;
6829                 }
6830
6831                 if (!stream)
6832                         continue;
6833
6834                 pbn_div = dm_mst_get_pbn_divider(stream->link);
6835                 /* pbn is calculated by compute_mst_dsc_configs_for_state*/
6836                 for (j = 0; j < dc_state->stream_count; j++) {
6837                         if (vars[j].aconnector == aconnector) {
6838                                 pbn = vars[j].pbn;
6839                                 break;
6840                         }
6841                 }
6842
6843                 if (j == dc_state->stream_count)
6844                         continue;
6845
6846                 slot_num = DIV_ROUND_UP(pbn, pbn_div);
6847
6848                 if (stream->timing.flags.DSC != 1) {
6849                         dm_conn_state->pbn = pbn;
6850                         dm_conn_state->vcpi_slots = slot_num;
6851
6852                         ret = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port,
6853                                                            dm_conn_state->pbn, false);
6854                         if (ret < 0)
6855                                 return ret;
6856
6857                         continue;
6858                 }
6859
6860                 vcpi = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, pbn, true);
6861                 if (vcpi < 0)
6862                         return vcpi;
6863
6864                 dm_conn_state->pbn = pbn;
6865                 dm_conn_state->vcpi_slots = vcpi;
6866         }
6867         return 0;
6868 }
6869
6870 static int to_drm_connector_type(enum signal_type st)
6871 {
6872         switch (st) {
6873         case SIGNAL_TYPE_HDMI_TYPE_A:
6874                 return DRM_MODE_CONNECTOR_HDMIA;
6875         case SIGNAL_TYPE_EDP:
6876                 return DRM_MODE_CONNECTOR_eDP;
6877         case SIGNAL_TYPE_LVDS:
6878                 return DRM_MODE_CONNECTOR_LVDS;
6879         case SIGNAL_TYPE_RGB:
6880                 return DRM_MODE_CONNECTOR_VGA;
6881         case SIGNAL_TYPE_DISPLAY_PORT:
6882         case SIGNAL_TYPE_DISPLAY_PORT_MST:
6883                 return DRM_MODE_CONNECTOR_DisplayPort;
6884         case SIGNAL_TYPE_DVI_DUAL_LINK:
6885         case SIGNAL_TYPE_DVI_SINGLE_LINK:
6886                 return DRM_MODE_CONNECTOR_DVID;
6887         case SIGNAL_TYPE_VIRTUAL:
6888                 return DRM_MODE_CONNECTOR_VIRTUAL;
6889
6890         default:
6891                 return DRM_MODE_CONNECTOR_Unknown;
6892         }
6893 }
6894
6895 static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector)
6896 {
6897         struct drm_encoder *encoder;
6898
6899         /* There is only one encoder per connector */
6900         drm_connector_for_each_possible_encoder(connector, encoder)
6901                 return encoder;
6902
6903         return NULL;
6904 }
6905
6906 static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
6907 {
6908         struct drm_encoder *encoder;
6909         struct amdgpu_encoder *amdgpu_encoder;
6910
6911         encoder = amdgpu_dm_connector_to_encoder(connector);
6912
6913         if (encoder == NULL)
6914                 return;
6915
6916         amdgpu_encoder = to_amdgpu_encoder(encoder);
6917
6918         amdgpu_encoder->native_mode.clock = 0;
6919
6920         if (!list_empty(&connector->probed_modes)) {
6921                 struct drm_display_mode *preferred_mode = NULL;
6922
6923                 list_for_each_entry(preferred_mode,
6924                                     &connector->probed_modes,
6925                                     head) {
6926                         if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
6927                                 amdgpu_encoder->native_mode = *preferred_mode;
6928
6929                         break;
6930                 }
6931
6932         }
6933 }
6934
6935 static struct drm_display_mode *
6936 amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
6937                              char *name,
6938                              int hdisplay, int vdisplay)
6939 {
6940         struct drm_device *dev = encoder->dev;
6941         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
6942         struct drm_display_mode *mode = NULL;
6943         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
6944
6945         mode = drm_mode_duplicate(dev, native_mode);
6946
6947         if (mode == NULL)
6948                 return NULL;
6949
6950         mode->hdisplay = hdisplay;
6951         mode->vdisplay = vdisplay;
6952         mode->type &= ~DRM_MODE_TYPE_PREFERRED;
6953         strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
6954
6955         return mode;
6956
6957 }
6958
6959 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
6960                                                  struct drm_connector *connector)
6961 {
6962         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
6963         struct drm_display_mode *mode = NULL;
6964         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
6965         struct amdgpu_dm_connector *amdgpu_dm_connector =
6966                                 to_amdgpu_dm_connector(connector);
6967         int i;
6968         int n;
6969         struct mode_size {
6970                 char name[DRM_DISPLAY_MODE_LEN];
6971                 int w;
6972                 int h;
6973         } common_modes[] = {
6974                 {  "640x480",  640,  480},
6975                 {  "800x600",  800,  600},
6976                 { "1024x768", 1024,  768},
6977                 { "1280x720", 1280,  720},
6978                 { "1280x800", 1280,  800},
6979                 {"1280x1024", 1280, 1024},
6980                 { "1440x900", 1440,  900},
6981                 {"1680x1050", 1680, 1050},
6982                 {"1600x1200", 1600, 1200},
6983                 {"1920x1080", 1920, 1080},
6984                 {"1920x1200", 1920, 1200}
6985         };
6986
6987         n = ARRAY_SIZE(common_modes);
6988
6989         for (i = 0; i < n; i++) {
6990                 struct drm_display_mode *curmode = NULL;
6991                 bool mode_existed = false;
6992
6993                 if (common_modes[i].w > native_mode->hdisplay ||
6994                     common_modes[i].h > native_mode->vdisplay ||
6995                    (common_modes[i].w == native_mode->hdisplay &&
6996                     common_modes[i].h == native_mode->vdisplay))
6997                         continue;
6998
6999                 list_for_each_entry(curmode, &connector->probed_modes, head) {
7000                         if (common_modes[i].w == curmode->hdisplay &&
7001                             common_modes[i].h == curmode->vdisplay) {
7002                                 mode_existed = true;
7003                                 break;
7004                         }
7005                 }
7006
7007                 if (mode_existed)
7008                         continue;
7009
7010                 mode = amdgpu_dm_create_common_mode(encoder,
7011                                 common_modes[i].name, common_modes[i].w,
7012                                 common_modes[i].h);
7013                 if (!mode)
7014                         continue;
7015
7016                 drm_mode_probed_add(connector, mode);
7017                 amdgpu_dm_connector->num_modes++;
7018         }
7019 }
7020
7021 static void amdgpu_set_panel_orientation(struct drm_connector *connector)
7022 {
7023         struct drm_encoder *encoder;
7024         struct amdgpu_encoder *amdgpu_encoder;
7025         const struct drm_display_mode *native_mode;
7026
7027         if (connector->connector_type != DRM_MODE_CONNECTOR_eDP &&
7028             connector->connector_type != DRM_MODE_CONNECTOR_LVDS)
7029                 return;
7030
7031         mutex_lock(&connector->dev->mode_config.mutex);
7032         amdgpu_dm_connector_get_modes(connector);
7033         mutex_unlock(&connector->dev->mode_config.mutex);
7034
7035         encoder = amdgpu_dm_connector_to_encoder(connector);
7036         if (!encoder)
7037                 return;
7038
7039         amdgpu_encoder = to_amdgpu_encoder(encoder);
7040
7041         native_mode = &amdgpu_encoder->native_mode;
7042         if (native_mode->hdisplay == 0 || native_mode->vdisplay == 0)
7043                 return;
7044
7045         drm_connector_set_panel_orientation_with_quirk(connector,
7046                                                        DRM_MODE_PANEL_ORIENTATION_UNKNOWN,
7047                                                        native_mode->hdisplay,
7048                                                        native_mode->vdisplay);
7049 }
7050
7051 static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
7052                                               struct edid *edid)
7053 {
7054         struct amdgpu_dm_connector *amdgpu_dm_connector =
7055                         to_amdgpu_dm_connector(connector);
7056
7057         if (edid) {
7058                 /* empty probed_modes */
7059                 INIT_LIST_HEAD(&connector->probed_modes);
7060                 amdgpu_dm_connector->num_modes =
7061                                 drm_add_edid_modes(connector, edid);
7062
7063                 /* sorting the probed modes before calling function
7064                  * amdgpu_dm_get_native_mode() since EDID can have
7065                  * more than one preferred mode. The modes that are
7066                  * later in the probed mode list could be of higher
7067                  * and preferred resolution. For example, 3840x2160
7068                  * resolution in base EDID preferred timing and 4096x2160
7069                  * preferred resolution in DID extension block later.
7070                  */
7071                 drm_mode_sort(&connector->probed_modes);
7072                 amdgpu_dm_get_native_mode(connector);
7073
7074                 /* Freesync capabilities are reset by calling
7075                  * drm_add_edid_modes() and need to be
7076                  * restored here.
7077                  */
7078                 amdgpu_dm_update_freesync_caps(connector, edid);
7079         } else {
7080                 amdgpu_dm_connector->num_modes = 0;
7081         }
7082 }
7083
7084 static bool is_duplicate_mode(struct amdgpu_dm_connector *aconnector,
7085                               struct drm_display_mode *mode)
7086 {
7087         struct drm_display_mode *m;
7088
7089         list_for_each_entry (m, &aconnector->base.probed_modes, head) {
7090                 if (drm_mode_equal(m, mode))
7091                         return true;
7092         }
7093
7094         return false;
7095 }
7096
7097 static uint add_fs_modes(struct amdgpu_dm_connector *aconnector)
7098 {
7099         const struct drm_display_mode *m;
7100         struct drm_display_mode *new_mode;
7101         uint i;
7102         u32 new_modes_count = 0;
7103
7104         /* Standard FPS values
7105          *
7106          * 23.976       - TV/NTSC
7107          * 24           - Cinema
7108          * 25           - TV/PAL
7109          * 29.97        - TV/NTSC
7110          * 30           - TV/NTSC
7111          * 48           - Cinema HFR
7112          * 50           - TV/PAL
7113          * 60           - Commonly used
7114          * 48,72,96,120 - Multiples of 24
7115          */
7116         static const u32 common_rates[] = {
7117                 23976, 24000, 25000, 29970, 30000,
7118                 48000, 50000, 60000, 72000, 96000, 120000
7119         };
7120
7121         /*
7122          * Find mode with highest refresh rate with the same resolution
7123          * as the preferred mode. Some monitors report a preferred mode
7124          * with lower resolution than the highest refresh rate supported.
7125          */
7126
7127         m = get_highest_refresh_rate_mode(aconnector, true);
7128         if (!m)
7129                 return 0;
7130
7131         for (i = 0; i < ARRAY_SIZE(common_rates); i++) {
7132                 u64 target_vtotal, target_vtotal_diff;
7133                 u64 num, den;
7134
7135                 if (drm_mode_vrefresh(m) * 1000 < common_rates[i])
7136                         continue;
7137
7138                 if (common_rates[i] < aconnector->min_vfreq * 1000 ||
7139                     common_rates[i] > aconnector->max_vfreq * 1000)
7140                         continue;
7141
7142                 num = (unsigned long long)m->clock * 1000 * 1000;
7143                 den = common_rates[i] * (unsigned long long)m->htotal;
7144                 target_vtotal = div_u64(num, den);
7145                 target_vtotal_diff = target_vtotal - m->vtotal;
7146
7147                 /* Check for illegal modes */
7148                 if (m->vsync_start + target_vtotal_diff < m->vdisplay ||
7149                     m->vsync_end + target_vtotal_diff < m->vsync_start ||
7150                     m->vtotal + target_vtotal_diff < m->vsync_end)
7151                         continue;
7152
7153                 new_mode = drm_mode_duplicate(aconnector->base.dev, m);
7154                 if (!new_mode)
7155                         goto out;
7156
7157                 new_mode->vtotal += (u16)target_vtotal_diff;
7158                 new_mode->vsync_start += (u16)target_vtotal_diff;
7159                 new_mode->vsync_end += (u16)target_vtotal_diff;
7160                 new_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
7161                 new_mode->type |= DRM_MODE_TYPE_DRIVER;
7162
7163                 if (!is_duplicate_mode(aconnector, new_mode)) {
7164                         drm_mode_probed_add(&aconnector->base, new_mode);
7165                         new_modes_count += 1;
7166                 } else
7167                         drm_mode_destroy(aconnector->base.dev, new_mode);
7168         }
7169  out:
7170         return new_modes_count;
7171 }
7172
7173 static void amdgpu_dm_connector_add_freesync_modes(struct drm_connector *connector,
7174                                                    struct edid *edid)
7175 {
7176         struct amdgpu_dm_connector *amdgpu_dm_connector =
7177                 to_amdgpu_dm_connector(connector);
7178
7179         if (!(amdgpu_freesync_vid_mode && edid))
7180                 return;
7181
7182         if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
7183                 amdgpu_dm_connector->num_modes +=
7184                         add_fs_modes(amdgpu_dm_connector);
7185 }
7186
7187 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
7188 {
7189         struct amdgpu_dm_connector *amdgpu_dm_connector =
7190                         to_amdgpu_dm_connector(connector);
7191         struct drm_encoder *encoder;
7192         struct edid *edid = amdgpu_dm_connector->edid;
7193         struct dc_link_settings *verified_link_cap =
7194                         &amdgpu_dm_connector->dc_link->verified_link_cap;
7195         const struct dc *dc = amdgpu_dm_connector->dc_link->dc;
7196
7197         encoder = amdgpu_dm_connector_to_encoder(connector);
7198
7199         if (!drm_edid_is_valid(edid)) {
7200                 amdgpu_dm_connector->num_modes =
7201                                 drm_add_modes_noedid(connector, 640, 480);
7202                 if (dc->link_srv->dp_get_encoding_format(verified_link_cap) == DP_128b_132b_ENCODING)
7203                         amdgpu_dm_connector->num_modes +=
7204                                 drm_add_modes_noedid(connector, 1920, 1080);
7205         } else {
7206                 amdgpu_dm_connector_ddc_get_modes(connector, edid);
7207                 amdgpu_dm_connector_add_common_modes(encoder, connector);
7208                 amdgpu_dm_connector_add_freesync_modes(connector, edid);
7209         }
7210         amdgpu_dm_fbc_init(connector);
7211
7212         return amdgpu_dm_connector->num_modes;
7213 }
7214
7215 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
7216                                      struct amdgpu_dm_connector *aconnector,
7217                                      int connector_type,
7218                                      struct dc_link *link,
7219                                      int link_index)
7220 {
7221         struct amdgpu_device *adev = drm_to_adev(dm->ddev);
7222
7223         /*
7224          * Some of the properties below require access to state, like bpc.
7225          * Allocate some default initial connector state with our reset helper.
7226          */
7227         if (aconnector->base.funcs->reset)
7228                 aconnector->base.funcs->reset(&aconnector->base);
7229
7230         aconnector->connector_id = link_index;
7231         aconnector->dc_link = link;
7232         aconnector->base.interlace_allowed = false;
7233         aconnector->base.doublescan_allowed = false;
7234         aconnector->base.stereo_allowed = false;
7235         aconnector->base.dpms = DRM_MODE_DPMS_OFF;
7236         aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
7237         aconnector->audio_inst = -1;
7238         aconnector->pack_sdp_v1_3 = false;
7239         aconnector->as_type = ADAPTIVE_SYNC_TYPE_NONE;
7240         memset(&aconnector->vsdb_info, 0, sizeof(aconnector->vsdb_info));
7241         mutex_init(&aconnector->hpd_lock);
7242
7243         /*
7244          * configure support HPD hot plug connector_>polled default value is 0
7245          * which means HPD hot plug not supported
7246          */
7247         switch (connector_type) {
7248         case DRM_MODE_CONNECTOR_HDMIA:
7249                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7250                 aconnector->base.ycbcr_420_allowed =
7251                         link->link_enc->features.hdmi_ycbcr420_supported ? true : false;
7252                 break;
7253         case DRM_MODE_CONNECTOR_DisplayPort:
7254                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7255                 link->link_enc = link_enc_cfg_get_link_enc(link);
7256                 ASSERT(link->link_enc);
7257                 if (link->link_enc)
7258                         aconnector->base.ycbcr_420_allowed =
7259                         link->link_enc->features.dp_ycbcr420_supported ? true : false;
7260                 break;
7261         case DRM_MODE_CONNECTOR_DVID:
7262                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7263                 break;
7264         default:
7265                 break;
7266         }
7267
7268         drm_object_attach_property(&aconnector->base.base,
7269                                 dm->ddev->mode_config.scaling_mode_property,
7270                                 DRM_MODE_SCALE_NONE);
7271
7272         drm_object_attach_property(&aconnector->base.base,
7273                                 adev->mode_info.underscan_property,
7274                                 UNDERSCAN_OFF);
7275         drm_object_attach_property(&aconnector->base.base,
7276                                 adev->mode_info.underscan_hborder_property,
7277                                 0);
7278         drm_object_attach_property(&aconnector->base.base,
7279                                 adev->mode_info.underscan_vborder_property,
7280                                 0);
7281
7282         if (!aconnector->mst_root)
7283                 drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16);
7284
7285         /* This defaults to the max in the range, but we want 8bpc for non-edp. */
7286         aconnector->base.state->max_bpc = 16;
7287         aconnector->base.state->max_requested_bpc = aconnector->base.state->max_bpc;
7288
7289         if (connector_type == DRM_MODE_CONNECTOR_eDP &&
7290             (dc_is_dmcu_initialized(adev->dm.dc) || adev->dm.dc->ctx->dmub_srv)) {
7291                 drm_object_attach_property(&aconnector->base.base,
7292                                 adev->mode_info.abm_level_property, 0);
7293         }
7294
7295         if (connector_type == DRM_MODE_CONNECTOR_HDMIA ||
7296             connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
7297             connector_type == DRM_MODE_CONNECTOR_eDP) {
7298                 drm_connector_attach_hdr_output_metadata_property(&aconnector->base);
7299
7300                 if (!aconnector->mst_root)
7301                         drm_connector_attach_vrr_capable_property(&aconnector->base);
7302
7303                 if (adev->dm.hdcp_workqueue)
7304                         drm_connector_attach_content_protection_property(&aconnector->base, true);
7305         }
7306 }
7307
7308 static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
7309                               struct i2c_msg *msgs, int num)
7310 {
7311         struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
7312         struct ddc_service *ddc_service = i2c->ddc_service;
7313         struct i2c_command cmd;
7314         int i;
7315         int result = -EIO;
7316
7317         cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
7318
7319         if (!cmd.payloads)
7320                 return result;
7321
7322         cmd.number_of_payloads = num;
7323         cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
7324         cmd.speed = 100;
7325
7326         for (i = 0; i < num; i++) {
7327                 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
7328                 cmd.payloads[i].address = msgs[i].addr;
7329                 cmd.payloads[i].length = msgs[i].len;
7330                 cmd.payloads[i].data = msgs[i].buf;
7331         }
7332
7333         if (dc_submit_i2c(
7334                         ddc_service->ctx->dc,
7335                         ddc_service->link->link_index,
7336                         &cmd))
7337                 result = num;
7338
7339         kfree(cmd.payloads);
7340         return result;
7341 }
7342
7343 static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
7344 {
7345         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
7346 }
7347
7348 static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
7349         .master_xfer = amdgpu_dm_i2c_xfer,
7350         .functionality = amdgpu_dm_i2c_func,
7351 };
7352
7353 static struct amdgpu_i2c_adapter *
7354 create_i2c(struct ddc_service *ddc_service,
7355            int link_index,
7356            int *res)
7357 {
7358         struct amdgpu_device *adev = ddc_service->ctx->driver_context;
7359         struct amdgpu_i2c_adapter *i2c;
7360
7361         i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
7362         if (!i2c)
7363                 return NULL;
7364         i2c->base.owner = THIS_MODULE;
7365         i2c->base.class = I2C_CLASS_DDC;
7366         i2c->base.dev.parent = &adev->pdev->dev;
7367         i2c->base.algo = &amdgpu_dm_i2c_algo;
7368         snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
7369         i2c_set_adapdata(&i2c->base, i2c);
7370         i2c->ddc_service = ddc_service;
7371
7372         return i2c;
7373 }
7374
7375
7376 /*
7377  * Note: this function assumes that dc_link_detect() was called for the
7378  * dc_link which will be represented by this aconnector.
7379  */
7380 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
7381                                     struct amdgpu_dm_connector *aconnector,
7382                                     u32 link_index,
7383                                     struct amdgpu_encoder *aencoder)
7384 {
7385         int res = 0;
7386         int connector_type;
7387         struct dc *dc = dm->dc;
7388         struct dc_link *link = dc_get_link_at_index(dc, link_index);
7389         struct amdgpu_i2c_adapter *i2c;
7390
7391         link->priv = aconnector;
7392
7393         DRM_DEBUG_DRIVER("%s()\n", __func__);
7394
7395         i2c = create_i2c(link->ddc, link->link_index, &res);
7396         if (!i2c) {
7397                 DRM_ERROR("Failed to create i2c adapter data\n");
7398                 return -ENOMEM;
7399         }
7400
7401         aconnector->i2c = i2c;
7402         res = i2c_add_adapter(&i2c->base);
7403
7404         if (res) {
7405                 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
7406                 goto out_free;
7407         }
7408
7409         connector_type = to_drm_connector_type(link->connector_signal);
7410
7411         res = drm_connector_init_with_ddc(
7412                         dm->ddev,
7413                         &aconnector->base,
7414                         &amdgpu_dm_connector_funcs,
7415                         connector_type,
7416                         &i2c->base);
7417
7418         if (res) {
7419                 DRM_ERROR("connector_init failed\n");
7420                 aconnector->connector_id = -1;
7421                 goto out_free;
7422         }
7423
7424         drm_connector_helper_add(
7425                         &aconnector->base,
7426                         &amdgpu_dm_connector_helper_funcs);
7427
7428         amdgpu_dm_connector_init_helper(
7429                 dm,
7430                 aconnector,
7431                 connector_type,
7432                 link,
7433                 link_index);
7434
7435         drm_connector_attach_encoder(
7436                 &aconnector->base, &aencoder->base);
7437
7438         if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
7439                 || connector_type == DRM_MODE_CONNECTOR_eDP)
7440                 amdgpu_dm_initialize_dp_connector(dm, aconnector, link->link_index);
7441
7442 out_free:
7443         if (res) {
7444                 kfree(i2c);
7445                 aconnector->i2c = NULL;
7446         }
7447         return res;
7448 }
7449
7450 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
7451 {
7452         switch (adev->mode_info.num_crtc) {
7453         case 1:
7454                 return 0x1;
7455         case 2:
7456                 return 0x3;
7457         case 3:
7458                 return 0x7;
7459         case 4:
7460                 return 0xf;
7461         case 5:
7462                 return 0x1f;
7463         case 6:
7464         default:
7465                 return 0x3f;
7466         }
7467 }
7468
7469 static int amdgpu_dm_encoder_init(struct drm_device *dev,
7470                                   struct amdgpu_encoder *aencoder,
7471                                   uint32_t link_index)
7472 {
7473         struct amdgpu_device *adev = drm_to_adev(dev);
7474
7475         int res = drm_encoder_init(dev,
7476                                    &aencoder->base,
7477                                    &amdgpu_dm_encoder_funcs,
7478                                    DRM_MODE_ENCODER_TMDS,
7479                                    NULL);
7480
7481         aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
7482
7483         if (!res)
7484                 aencoder->encoder_id = link_index;
7485         else
7486                 aencoder->encoder_id = -1;
7487
7488         drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
7489
7490         return res;
7491 }
7492
7493 static void manage_dm_interrupts(struct amdgpu_device *adev,
7494                                  struct amdgpu_crtc *acrtc,
7495                                  bool enable)
7496 {
7497         /*
7498          * We have no guarantee that the frontend index maps to the same
7499          * backend index - some even map to more than one.
7500          *
7501          * TODO: Use a different interrupt or check DC itself for the mapping.
7502          */
7503         int irq_type =
7504                 amdgpu_display_crtc_idx_to_irq_type(
7505                         adev,
7506                         acrtc->crtc_id);
7507
7508         if (enable) {
7509                 drm_crtc_vblank_on(&acrtc->base);
7510                 amdgpu_irq_get(
7511                         adev,
7512                         &adev->pageflip_irq,
7513                         irq_type);
7514 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
7515                 amdgpu_irq_get(
7516                         adev,
7517                         &adev->vline0_irq,
7518                         irq_type);
7519 #endif
7520         } else {
7521 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
7522                 amdgpu_irq_put(
7523                         adev,
7524                         &adev->vline0_irq,
7525                         irq_type);
7526 #endif
7527                 amdgpu_irq_put(
7528                         adev,
7529                         &adev->pageflip_irq,
7530                         irq_type);
7531                 drm_crtc_vblank_off(&acrtc->base);
7532         }
7533 }
7534
7535 static void dm_update_pflip_irq_state(struct amdgpu_device *adev,
7536                                       struct amdgpu_crtc *acrtc)
7537 {
7538         int irq_type =
7539                 amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id);
7540
7541         /**
7542          * This reads the current state for the IRQ and force reapplies
7543          * the setting to hardware.
7544          */
7545         amdgpu_irq_update(adev, &adev->pageflip_irq, irq_type);
7546 }
7547
7548 static bool
7549 is_scaling_state_different(const struct dm_connector_state *dm_state,
7550                            const struct dm_connector_state *old_dm_state)
7551 {
7552         if (dm_state->scaling != old_dm_state->scaling)
7553                 return true;
7554         if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
7555                 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
7556                         return true;
7557         } else  if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
7558                 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
7559                         return true;
7560         } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
7561                    dm_state->underscan_vborder != old_dm_state->underscan_vborder)
7562                 return true;
7563         return false;
7564 }
7565
7566 static bool is_content_protection_different(struct drm_crtc_state *new_crtc_state,
7567                                             struct drm_crtc_state *old_crtc_state,
7568                                             struct drm_connector_state *new_conn_state,
7569                                             struct drm_connector_state *old_conn_state,
7570                                             const struct drm_connector *connector,
7571                                             struct hdcp_workqueue *hdcp_w)
7572 {
7573         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
7574         struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
7575
7576         pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n",
7577                 connector->index, connector->status, connector->dpms);
7578         pr_debug("[HDCP_DM] state protection old: %x new: %x\n",
7579                 old_conn_state->content_protection, new_conn_state->content_protection);
7580
7581         if (old_crtc_state)
7582                 pr_debug("[HDCP_DM] old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
7583                 old_crtc_state->enable,
7584                 old_crtc_state->active,
7585                 old_crtc_state->mode_changed,
7586                 old_crtc_state->active_changed,
7587                 old_crtc_state->connectors_changed);
7588
7589         if (new_crtc_state)
7590                 pr_debug("[HDCP_DM] NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
7591                 new_crtc_state->enable,
7592                 new_crtc_state->active,
7593                 new_crtc_state->mode_changed,
7594                 new_crtc_state->active_changed,
7595                 new_crtc_state->connectors_changed);
7596
7597         /* hdcp content type change */
7598         if (old_conn_state->hdcp_content_type != new_conn_state->hdcp_content_type &&
7599             new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
7600                 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7601                 pr_debug("[HDCP_DM] Type0/1 change %s :true\n", __func__);
7602                 return true;
7603         }
7604
7605         /* CP is being re enabled, ignore this */
7606         if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED &&
7607             new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7608                 if (new_crtc_state && new_crtc_state->mode_changed) {
7609                         new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7610                         pr_debug("[HDCP_DM] ENABLED->DESIRED & mode_changed %s :true\n", __func__);
7611                         return true;
7612                 }
7613                 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED;
7614                 pr_debug("[HDCP_DM] ENABLED -> DESIRED %s :false\n", __func__);
7615                 return false;
7616         }
7617
7618         /* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED
7619          *
7620          * Handles:     UNDESIRED -> ENABLED
7621          */
7622         if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED &&
7623             new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
7624                 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7625
7626         /* Stream removed and re-enabled
7627          *
7628          * Can sometimes overlap with the HPD case,
7629          * thus set update_hdcp to false to avoid
7630          * setting HDCP multiple times.
7631          *
7632          * Handles:     DESIRED -> DESIRED (Special case)
7633          */
7634         if (!(old_conn_state->crtc && old_conn_state->crtc->enabled) &&
7635                 new_conn_state->crtc && new_conn_state->crtc->enabled &&
7636                 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7637                 dm_con_state->update_hdcp = false;
7638                 pr_debug("[HDCP_DM] DESIRED->DESIRED (Stream removed and re-enabled) %s :true\n",
7639                         __func__);
7640                 return true;
7641         }
7642
7643         /* Hot-plug, headless s3, dpms
7644          *
7645          * Only start HDCP if the display is connected/enabled.
7646          * update_hdcp flag will be set to false until the next
7647          * HPD comes in.
7648          *
7649          * Handles:     DESIRED -> DESIRED (Special case)
7650          */
7651         if (dm_con_state->update_hdcp &&
7652         new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED &&
7653         connector->dpms == DRM_MODE_DPMS_ON && aconnector->dc_sink != NULL) {
7654                 dm_con_state->update_hdcp = false;
7655                 pr_debug("[HDCP_DM] DESIRED->DESIRED (Hot-plug, headless s3, dpms) %s :true\n",
7656                         __func__);
7657                 return true;
7658         }
7659
7660         if (old_conn_state->content_protection == new_conn_state->content_protection) {
7661                 if (new_conn_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7662                         if (new_crtc_state && new_crtc_state->mode_changed) {
7663                                 pr_debug("[HDCP_DM] DESIRED->DESIRED or ENABLE->ENABLE mode_change %s :true\n",
7664                                         __func__);
7665                                 return true;
7666                         }
7667                         pr_debug("[HDCP_DM] DESIRED->DESIRED & ENABLE->ENABLE %s :false\n",
7668                                 __func__);
7669                         return false;
7670                 }
7671
7672                 pr_debug("[HDCP_DM] UNDESIRED->UNDESIRED %s :false\n", __func__);
7673                 return false;
7674         }
7675
7676         if (new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_ENABLED) {
7677                 pr_debug("[HDCP_DM] UNDESIRED->DESIRED or DESIRED->UNDESIRED or ENABLED->UNDESIRED %s :true\n",
7678                         __func__);
7679                 return true;
7680         }
7681
7682         pr_debug("[HDCP_DM] DESIRED->ENABLED %s :false\n", __func__);
7683         return false;
7684 }
7685
7686 static void remove_stream(struct amdgpu_device *adev,
7687                           struct amdgpu_crtc *acrtc,
7688                           struct dc_stream_state *stream)
7689 {
7690         /* this is the update mode case */
7691
7692         acrtc->otg_inst = -1;
7693         acrtc->enabled = false;
7694 }
7695
7696 static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
7697 {
7698
7699         assert_spin_locked(&acrtc->base.dev->event_lock);
7700         WARN_ON(acrtc->event);
7701
7702         acrtc->event = acrtc->base.state->event;
7703
7704         /* Set the flip status */
7705         acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
7706
7707         /* Mark this event as consumed */
7708         acrtc->base.state->event = NULL;
7709
7710         DC_LOG_PFLIP("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
7711                      acrtc->crtc_id);
7712 }
7713
7714 static void update_freesync_state_on_stream(
7715         struct amdgpu_display_manager *dm,
7716         struct dm_crtc_state *new_crtc_state,
7717         struct dc_stream_state *new_stream,
7718         struct dc_plane_state *surface,
7719         u32 flip_timestamp_in_us)
7720 {
7721         struct mod_vrr_params vrr_params;
7722         struct dc_info_packet vrr_infopacket = {0};
7723         struct amdgpu_device *adev = dm->adev;
7724         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
7725         unsigned long flags;
7726         bool pack_sdp_v1_3 = false;
7727         struct amdgpu_dm_connector *aconn;
7728         enum vrr_packet_type packet_type = PACKET_TYPE_VRR;
7729
7730         if (!new_stream)
7731                 return;
7732
7733         /*
7734          * TODO: Determine why min/max totals and vrefresh can be 0 here.
7735          * For now it's sufficient to just guard against these conditions.
7736          */
7737
7738         if (!new_stream->timing.h_total || !new_stream->timing.v_total)
7739                 return;
7740
7741         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
7742         vrr_params = acrtc->dm_irq_params.vrr_params;
7743
7744         if (surface) {
7745                 mod_freesync_handle_preflip(
7746                         dm->freesync_module,
7747                         surface,
7748                         new_stream,
7749                         flip_timestamp_in_us,
7750                         &vrr_params);
7751
7752                 if (adev->family < AMDGPU_FAMILY_AI &&
7753                     amdgpu_dm_crtc_vrr_active(new_crtc_state)) {
7754                         mod_freesync_handle_v_update(dm->freesync_module,
7755                                                      new_stream, &vrr_params);
7756
7757                         /* Need to call this before the frame ends. */
7758                         dc_stream_adjust_vmin_vmax(dm->dc,
7759                                                    new_crtc_state->stream,
7760                                                    &vrr_params.adjust);
7761                 }
7762         }
7763
7764         aconn = (struct amdgpu_dm_connector *)new_stream->dm_stream_context;
7765
7766         if (aconn && aconn->as_type == FREESYNC_TYPE_PCON_IN_WHITELIST) {
7767                 pack_sdp_v1_3 = aconn->pack_sdp_v1_3;
7768
7769                 if (aconn->vsdb_info.amd_vsdb_version == 1)
7770                         packet_type = PACKET_TYPE_FS_V1;
7771                 else if (aconn->vsdb_info.amd_vsdb_version == 2)
7772                         packet_type = PACKET_TYPE_FS_V2;
7773                 else if (aconn->vsdb_info.amd_vsdb_version == 3)
7774                         packet_type = PACKET_TYPE_FS_V3;
7775
7776                 mod_build_adaptive_sync_infopacket(new_stream, aconn->as_type, NULL,
7777                                         &new_stream->adaptive_sync_infopacket);
7778         }
7779
7780         mod_freesync_build_vrr_infopacket(
7781                 dm->freesync_module,
7782                 new_stream,
7783                 &vrr_params,
7784                 packet_type,
7785                 TRANSFER_FUNC_UNKNOWN,
7786                 &vrr_infopacket,
7787                 pack_sdp_v1_3);
7788
7789         new_crtc_state->freesync_vrr_info_changed |=
7790                 (memcmp(&new_crtc_state->vrr_infopacket,
7791                         &vrr_infopacket,
7792                         sizeof(vrr_infopacket)) != 0);
7793
7794         acrtc->dm_irq_params.vrr_params = vrr_params;
7795         new_crtc_state->vrr_infopacket = vrr_infopacket;
7796
7797         new_stream->vrr_infopacket = vrr_infopacket;
7798         new_stream->allow_freesync = mod_freesync_get_freesync_enabled(&vrr_params);
7799
7800         if (new_crtc_state->freesync_vrr_info_changed)
7801                 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d",
7802                               new_crtc_state->base.crtc->base.id,
7803                               (int)new_crtc_state->base.vrr_enabled,
7804                               (int)vrr_params.state);
7805
7806         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
7807 }
7808
7809 static void update_stream_irq_parameters(
7810         struct amdgpu_display_manager *dm,
7811         struct dm_crtc_state *new_crtc_state)
7812 {
7813         struct dc_stream_state *new_stream = new_crtc_state->stream;
7814         struct mod_vrr_params vrr_params;
7815         struct mod_freesync_config config = new_crtc_state->freesync_config;
7816         struct amdgpu_device *adev = dm->adev;
7817         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
7818         unsigned long flags;
7819
7820         if (!new_stream)
7821                 return;
7822
7823         /*
7824          * TODO: Determine why min/max totals and vrefresh can be 0 here.
7825          * For now it's sufficient to just guard against these conditions.
7826          */
7827         if (!new_stream->timing.h_total || !new_stream->timing.v_total)
7828                 return;
7829
7830         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
7831         vrr_params = acrtc->dm_irq_params.vrr_params;
7832
7833         if (new_crtc_state->vrr_supported &&
7834             config.min_refresh_in_uhz &&
7835             config.max_refresh_in_uhz) {
7836                 /*
7837                  * if freesync compatible mode was set, config.state will be set
7838                  * in atomic check
7839                  */
7840                 if (config.state == VRR_STATE_ACTIVE_FIXED && config.fixed_refresh_in_uhz &&
7841                     (!drm_atomic_crtc_needs_modeset(&new_crtc_state->base) ||
7842                      new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)) {
7843                         vrr_params.max_refresh_in_uhz = config.max_refresh_in_uhz;
7844                         vrr_params.min_refresh_in_uhz = config.min_refresh_in_uhz;
7845                         vrr_params.fixed_refresh_in_uhz = config.fixed_refresh_in_uhz;
7846                         vrr_params.state = VRR_STATE_ACTIVE_FIXED;
7847                 } else {
7848                         config.state = new_crtc_state->base.vrr_enabled ?
7849                                                      VRR_STATE_ACTIVE_VARIABLE :
7850                                                      VRR_STATE_INACTIVE;
7851                 }
7852         } else {
7853                 config.state = VRR_STATE_UNSUPPORTED;
7854         }
7855
7856         mod_freesync_build_vrr_params(dm->freesync_module,
7857                                       new_stream,
7858                                       &config, &vrr_params);
7859
7860         new_crtc_state->freesync_config = config;
7861         /* Copy state for access from DM IRQ handler */
7862         acrtc->dm_irq_params.freesync_config = config;
7863         acrtc->dm_irq_params.active_planes = new_crtc_state->active_planes;
7864         acrtc->dm_irq_params.vrr_params = vrr_params;
7865         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
7866 }
7867
7868 static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state,
7869                                             struct dm_crtc_state *new_state)
7870 {
7871         bool old_vrr_active = amdgpu_dm_crtc_vrr_active(old_state);
7872         bool new_vrr_active = amdgpu_dm_crtc_vrr_active(new_state);
7873
7874         if (!old_vrr_active && new_vrr_active) {
7875                 /* Transition VRR inactive -> active:
7876                  * While VRR is active, we must not disable vblank irq, as a
7877                  * reenable after disable would compute bogus vblank/pflip
7878                  * timestamps if it likely happened inside display front-porch.
7879                  *
7880                  * We also need vupdate irq for the actual core vblank handling
7881                  * at end of vblank.
7882                  */
7883                 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, true) != 0);
7884                 WARN_ON(drm_crtc_vblank_get(new_state->base.crtc) != 0);
7885                 DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n",
7886                                  __func__, new_state->base.crtc->base.id);
7887         } else if (old_vrr_active && !new_vrr_active) {
7888                 /* Transition VRR active -> inactive:
7889                  * Allow vblank irq disable again for fixed refresh rate.
7890                  */
7891                 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, false) != 0);
7892                 drm_crtc_vblank_put(new_state->base.crtc);
7893                 DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n",
7894                                  __func__, new_state->base.crtc->base.id);
7895         }
7896 }
7897
7898 static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state)
7899 {
7900         struct drm_plane *plane;
7901         struct drm_plane_state *old_plane_state;
7902         int i;
7903
7904         /*
7905          * TODO: Make this per-stream so we don't issue redundant updates for
7906          * commits with multiple streams.
7907          */
7908         for_each_old_plane_in_state(state, plane, old_plane_state, i)
7909                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
7910                         amdgpu_dm_plane_handle_cursor_update(plane, old_plane_state);
7911 }
7912
7913 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
7914                                     struct dc_state *dc_state,
7915                                     struct drm_device *dev,
7916                                     struct amdgpu_display_manager *dm,
7917                                     struct drm_crtc *pcrtc,
7918                                     bool wait_for_vblank)
7919 {
7920         u32 i;
7921         u64 timestamp_ns = ktime_get_ns();
7922         struct drm_plane *plane;
7923         struct drm_plane_state *old_plane_state, *new_plane_state;
7924         struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
7925         struct drm_crtc_state *new_pcrtc_state =
7926                         drm_atomic_get_new_crtc_state(state, pcrtc);
7927         struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
7928         struct dm_crtc_state *dm_old_crtc_state =
7929                         to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
7930         int planes_count = 0, vpos, hpos;
7931         unsigned long flags;
7932         u32 target_vblank, last_flip_vblank;
7933         bool vrr_active = amdgpu_dm_crtc_vrr_active(acrtc_state);
7934         bool cursor_update = false;
7935         bool pflip_present = false;
7936         bool dirty_rects_changed = false;
7937         struct {
7938                 struct dc_surface_update surface_updates[MAX_SURFACES];
7939                 struct dc_plane_info plane_infos[MAX_SURFACES];
7940                 struct dc_scaling_info scaling_infos[MAX_SURFACES];
7941                 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
7942                 struct dc_stream_update stream_update;
7943         } *bundle;
7944
7945         bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
7946
7947         if (!bundle) {
7948                 dm_error("Failed to allocate update bundle\n");
7949                 goto cleanup;
7950         }
7951
7952         /*
7953          * Disable the cursor first if we're disabling all the planes.
7954          * It'll remain on the screen after the planes are re-enabled
7955          * if we don't.
7956          */
7957         if (acrtc_state->active_planes == 0)
7958                 amdgpu_dm_commit_cursors(state);
7959
7960         /* update planes when needed */
7961         for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
7962                 struct drm_crtc *crtc = new_plane_state->crtc;
7963                 struct drm_crtc_state *new_crtc_state;
7964                 struct drm_framebuffer *fb = new_plane_state->fb;
7965                 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)fb;
7966                 bool plane_needs_flip;
7967                 struct dc_plane_state *dc_plane;
7968                 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
7969
7970                 /* Cursor plane is handled after stream updates */
7971                 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
7972                         if ((fb && crtc == pcrtc) ||
7973                             (old_plane_state->fb && old_plane_state->crtc == pcrtc))
7974                                 cursor_update = true;
7975
7976                         continue;
7977                 }
7978
7979                 if (!fb || !crtc || pcrtc != crtc)
7980                         continue;
7981
7982                 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
7983                 if (!new_crtc_state->active)
7984                         continue;
7985
7986                 dc_plane = dm_new_plane_state->dc_state;
7987
7988                 bundle->surface_updates[planes_count].surface = dc_plane;
7989                 if (new_pcrtc_state->color_mgmt_changed) {
7990                         bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction;
7991                         bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func;
7992                         bundle->surface_updates[planes_count].gamut_remap_matrix = &dc_plane->gamut_remap_matrix;
7993                 }
7994
7995                 amdgpu_dm_plane_fill_dc_scaling_info(dm->adev, new_plane_state,
7996                                      &bundle->scaling_infos[planes_count]);
7997
7998                 bundle->surface_updates[planes_count].scaling_info =
7999                         &bundle->scaling_infos[planes_count];
8000
8001                 plane_needs_flip = old_plane_state->fb && new_plane_state->fb;
8002
8003                 pflip_present = pflip_present || plane_needs_flip;
8004
8005                 if (!plane_needs_flip) {
8006                         planes_count += 1;
8007                         continue;
8008                 }
8009
8010                 fill_dc_plane_info_and_addr(
8011                         dm->adev, new_plane_state,
8012                         afb->tiling_flags,
8013                         &bundle->plane_infos[planes_count],
8014                         &bundle->flip_addrs[planes_count].address,
8015                         afb->tmz_surface, false);
8016
8017                 drm_dbg_state(state->dev, "plane: id=%d dcc_en=%d\n",
8018                                  new_plane_state->plane->index,
8019                                  bundle->plane_infos[planes_count].dcc.enable);
8020
8021                 bundle->surface_updates[planes_count].plane_info =
8022                         &bundle->plane_infos[planes_count];
8023
8024                 if (acrtc_state->stream->link->psr_settings.psr_feature_enabled) {
8025                         fill_dc_dirty_rects(plane, old_plane_state,
8026                                             new_plane_state, new_crtc_state,
8027                                             &bundle->flip_addrs[planes_count],
8028                                             &dirty_rects_changed);
8029
8030                         /*
8031                          * If the dirty regions changed, PSR-SU need to be disabled temporarily
8032                          * and enabled it again after dirty regions are stable to avoid video glitch.
8033                          * PSR-SU will be enabled in vblank_control_worker() if user pause the video
8034                          * during the PSR-SU was disabled.
8035                          */
8036                         if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
8037                             acrtc_attach->dm_irq_params.allow_psr_entry &&
8038 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
8039                             !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
8040 #endif
8041                             dirty_rects_changed) {
8042                                 mutex_lock(&dm->dc_lock);
8043                                 acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns =
8044                                 timestamp_ns;
8045                                 if (acrtc_state->stream->link->psr_settings.psr_allow_active)
8046                                         amdgpu_dm_psr_disable(acrtc_state->stream);
8047                                 mutex_unlock(&dm->dc_lock);
8048                         }
8049                 }
8050
8051                 /*
8052                  * Only allow immediate flips for fast updates that don't
8053                  * change FB pitch, DCC state, rotation or mirroing.
8054                  */
8055                 bundle->flip_addrs[planes_count].flip_immediate =
8056                         crtc->state->async_flip &&
8057                         acrtc_state->update_type == UPDATE_TYPE_FAST;
8058
8059                 timestamp_ns = ktime_get_ns();
8060                 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000);
8061                 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count];
8062                 bundle->surface_updates[planes_count].surface = dc_plane;
8063
8064                 if (!bundle->surface_updates[planes_count].surface) {
8065                         DRM_ERROR("No surface for CRTC: id=%d\n",
8066                                         acrtc_attach->crtc_id);
8067                         continue;
8068                 }
8069
8070                 if (plane == pcrtc->primary)
8071                         update_freesync_state_on_stream(
8072                                 dm,
8073                                 acrtc_state,
8074                                 acrtc_state->stream,
8075                                 dc_plane,
8076                                 bundle->flip_addrs[planes_count].flip_timestamp_in_us);
8077
8078                 drm_dbg_state(state->dev, "%s Flipping to hi: 0x%x, low: 0x%x\n",
8079                                  __func__,
8080                                  bundle->flip_addrs[planes_count].address.grph.addr.high_part,
8081                                  bundle->flip_addrs[planes_count].address.grph.addr.low_part);
8082
8083                 planes_count += 1;
8084
8085         }
8086
8087         if (pflip_present) {
8088                 if (!vrr_active) {
8089                         /* Use old throttling in non-vrr fixed refresh rate mode
8090                          * to keep flip scheduling based on target vblank counts
8091                          * working in a backwards compatible way, e.g., for
8092                          * clients using the GLX_OML_sync_control extension or
8093                          * DRI3/Present extension with defined target_msc.
8094                          */
8095                         last_flip_vblank = amdgpu_get_vblank_counter_kms(pcrtc);
8096                 }
8097                 else {
8098                         /* For variable refresh rate mode only:
8099                          * Get vblank of last completed flip to avoid > 1 vrr
8100                          * flips per video frame by use of throttling, but allow
8101                          * flip programming anywhere in the possibly large
8102                          * variable vrr vblank interval for fine-grained flip
8103                          * timing control and more opportunity to avoid stutter
8104                          * on late submission of flips.
8105                          */
8106                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8107                         last_flip_vblank = acrtc_attach->dm_irq_params.last_flip_vblank;
8108                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8109                 }
8110
8111                 target_vblank = last_flip_vblank + wait_for_vblank;
8112
8113                 /*
8114                  * Wait until we're out of the vertical blank period before the one
8115                  * targeted by the flip
8116                  */
8117                 while ((acrtc_attach->enabled &&
8118                         (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id,
8119                                                             0, &vpos, &hpos, NULL,
8120                                                             NULL, &pcrtc->hwmode)
8121                          & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
8122                         (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
8123                         (int)(target_vblank -
8124                           amdgpu_get_vblank_counter_kms(pcrtc)) > 0)) {
8125                         usleep_range(1000, 1100);
8126                 }
8127
8128                 /**
8129                  * Prepare the flip event for the pageflip interrupt to handle.
8130                  *
8131                  * This only works in the case where we've already turned on the
8132                  * appropriate hardware blocks (eg. HUBP) so in the transition case
8133                  * from 0 -> n planes we have to skip a hardware generated event
8134                  * and rely on sending it from software.
8135                  */
8136                 if (acrtc_attach->base.state->event &&
8137                     acrtc_state->active_planes > 0) {
8138                         drm_crtc_vblank_get(pcrtc);
8139
8140                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8141
8142                         WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE);
8143                         prepare_flip_isr(acrtc_attach);
8144
8145                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8146                 }
8147
8148                 if (acrtc_state->stream) {
8149                         if (acrtc_state->freesync_vrr_info_changed)
8150                                 bundle->stream_update.vrr_infopacket =
8151                                         &acrtc_state->stream->vrr_infopacket;
8152                 }
8153         } else if (cursor_update && acrtc_state->active_planes > 0 &&
8154                    acrtc_attach->base.state->event) {
8155                 drm_crtc_vblank_get(pcrtc);
8156
8157                 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8158
8159                 acrtc_attach->event = acrtc_attach->base.state->event;
8160                 acrtc_attach->base.state->event = NULL;
8161
8162                 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8163         }
8164
8165         /* Update the planes if changed or disable if we don't have any. */
8166         if ((planes_count || acrtc_state->active_planes == 0) &&
8167                 acrtc_state->stream) {
8168                 /*
8169                  * If PSR or idle optimizations are enabled then flush out
8170                  * any pending work before hardware programming.
8171                  */
8172                 if (dm->vblank_control_workqueue)
8173                         flush_workqueue(dm->vblank_control_workqueue);
8174
8175                 bundle->stream_update.stream = acrtc_state->stream;
8176                 if (new_pcrtc_state->mode_changed) {
8177                         bundle->stream_update.src = acrtc_state->stream->src;
8178                         bundle->stream_update.dst = acrtc_state->stream->dst;
8179                 }
8180
8181                 if (new_pcrtc_state->color_mgmt_changed) {
8182                         /*
8183                          * TODO: This isn't fully correct since we've actually
8184                          * already modified the stream in place.
8185                          */
8186                         bundle->stream_update.gamut_remap =
8187                                 &acrtc_state->stream->gamut_remap_matrix;
8188                         bundle->stream_update.output_csc_transform =
8189                                 &acrtc_state->stream->csc_color_matrix;
8190                         bundle->stream_update.out_transfer_func =
8191                                 acrtc_state->stream->out_transfer_func;
8192                 }
8193
8194                 acrtc_state->stream->abm_level = acrtc_state->abm_level;
8195                 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level)
8196                         bundle->stream_update.abm_level = &acrtc_state->abm_level;
8197
8198                 /*
8199                  * If FreeSync state on the stream has changed then we need to
8200                  * re-adjust the min/max bounds now that DC doesn't handle this
8201                  * as part of commit.
8202                  */
8203                 if (is_dc_timing_adjust_needed(dm_old_crtc_state, acrtc_state)) {
8204                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8205                         dc_stream_adjust_vmin_vmax(
8206                                 dm->dc, acrtc_state->stream,
8207                                 &acrtc_attach->dm_irq_params.vrr_params.adjust);
8208                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8209                 }
8210                 mutex_lock(&dm->dc_lock);
8211                 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
8212                                 acrtc_state->stream->link->psr_settings.psr_allow_active)
8213                         amdgpu_dm_psr_disable(acrtc_state->stream);
8214
8215                 update_planes_and_stream_adapter(dm->dc,
8216                                          acrtc_state->update_type,
8217                                          planes_count,
8218                                          acrtc_state->stream,
8219                                          &bundle->stream_update,
8220                                          bundle->surface_updates);
8221
8222                 /**
8223                  * Enable or disable the interrupts on the backend.
8224                  *
8225                  * Most pipes are put into power gating when unused.
8226                  *
8227                  * When power gating is enabled on a pipe we lose the
8228                  * interrupt enablement state when power gating is disabled.
8229                  *
8230                  * So we need to update the IRQ control state in hardware
8231                  * whenever the pipe turns on (since it could be previously
8232                  * power gated) or off (since some pipes can't be power gated
8233                  * on some ASICs).
8234                  */
8235                 if (dm_old_crtc_state->active_planes != acrtc_state->active_planes)
8236                         dm_update_pflip_irq_state(drm_to_adev(dev),
8237                                                   acrtc_attach);
8238
8239                 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
8240                                 acrtc_state->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED &&
8241                                 !acrtc_state->stream->link->psr_settings.psr_feature_enabled)
8242                         amdgpu_dm_link_setup_psr(acrtc_state->stream);
8243
8244                 /* Decrement skip count when PSR is enabled and we're doing fast updates. */
8245                 if (acrtc_state->update_type == UPDATE_TYPE_FAST &&
8246                     acrtc_state->stream->link->psr_settings.psr_feature_enabled) {
8247                         struct amdgpu_dm_connector *aconn =
8248                                 (struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context;
8249
8250                         if (aconn->psr_skip_count > 0)
8251                                 aconn->psr_skip_count--;
8252
8253                         /* Allow PSR when skip count is 0. */
8254                         acrtc_attach->dm_irq_params.allow_psr_entry = !aconn->psr_skip_count;
8255
8256                         /*
8257                          * If sink supports PSR SU, there is no need to rely on
8258                          * a vblank event disable request to enable PSR. PSR SU
8259                          * can be enabled immediately once OS demonstrates an
8260                          * adequate number of fast atomic commits to notify KMD
8261                          * of update events. See `vblank_control_worker()`.
8262                          */
8263                         if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
8264                             acrtc_attach->dm_irq_params.allow_psr_entry &&
8265 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
8266                             !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
8267 #endif
8268                             !acrtc_state->stream->link->psr_settings.psr_allow_active &&
8269                             (timestamp_ns -
8270                             acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns) >
8271                             500000000)
8272                                 amdgpu_dm_psr_enable(acrtc_state->stream);
8273                 } else {
8274                         acrtc_attach->dm_irq_params.allow_psr_entry = false;
8275                 }
8276
8277                 mutex_unlock(&dm->dc_lock);
8278         }
8279
8280         /*
8281          * Update cursor state *after* programming all the planes.
8282          * This avoids redundant programming in the case where we're going
8283          * to be disabling a single plane - those pipes are being disabled.
8284          */
8285         if (acrtc_state->active_planes)
8286                 amdgpu_dm_commit_cursors(state);
8287
8288 cleanup:
8289         kfree(bundle);
8290 }
8291
8292 static void amdgpu_dm_commit_audio(struct drm_device *dev,
8293                                    struct drm_atomic_state *state)
8294 {
8295         struct amdgpu_device *adev = drm_to_adev(dev);
8296         struct amdgpu_dm_connector *aconnector;
8297         struct drm_connector *connector;
8298         struct drm_connector_state *old_con_state, *new_con_state;
8299         struct drm_crtc_state *new_crtc_state;
8300         struct dm_crtc_state *new_dm_crtc_state;
8301         const struct dc_stream_status *status;
8302         int i, inst;
8303
8304         /* Notify device removals. */
8305         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8306                 if (old_con_state->crtc != new_con_state->crtc) {
8307                         /* CRTC changes require notification. */
8308                         goto notify;
8309                 }
8310
8311                 if (!new_con_state->crtc)
8312                         continue;
8313
8314                 new_crtc_state = drm_atomic_get_new_crtc_state(
8315                         state, new_con_state->crtc);
8316
8317                 if (!new_crtc_state)
8318                         continue;
8319
8320                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8321                         continue;
8322
8323         notify:
8324                 aconnector = to_amdgpu_dm_connector(connector);
8325
8326                 mutex_lock(&adev->dm.audio_lock);
8327                 inst = aconnector->audio_inst;
8328                 aconnector->audio_inst = -1;
8329                 mutex_unlock(&adev->dm.audio_lock);
8330
8331                 amdgpu_dm_audio_eld_notify(adev, inst);
8332         }
8333
8334         /* Notify audio device additions. */
8335         for_each_new_connector_in_state(state, connector, new_con_state, i) {
8336                 if (!new_con_state->crtc)
8337                         continue;
8338
8339                 new_crtc_state = drm_atomic_get_new_crtc_state(
8340                         state, new_con_state->crtc);
8341
8342                 if (!new_crtc_state)
8343                         continue;
8344
8345                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8346                         continue;
8347
8348                 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
8349                 if (!new_dm_crtc_state->stream)
8350                         continue;
8351
8352                 status = dc_stream_get_status(new_dm_crtc_state->stream);
8353                 if (!status)
8354                         continue;
8355
8356                 aconnector = to_amdgpu_dm_connector(connector);
8357
8358                 mutex_lock(&adev->dm.audio_lock);
8359                 inst = status->audio_inst;
8360                 aconnector->audio_inst = inst;
8361                 mutex_unlock(&adev->dm.audio_lock);
8362
8363                 amdgpu_dm_audio_eld_notify(adev, inst);
8364         }
8365 }
8366
8367 /*
8368  * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
8369  * @crtc_state: the DRM CRTC state
8370  * @stream_state: the DC stream state.
8371  *
8372  * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
8373  * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
8374  */
8375 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
8376                                                 struct dc_stream_state *stream_state)
8377 {
8378         stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state);
8379 }
8380
8381 /**
8382  * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation.
8383  * @state: The atomic state to commit
8384  *
8385  * This will tell DC to commit the constructed DC state from atomic_check,
8386  * programming the hardware. Any failures here implies a hardware failure, since
8387  * atomic check should have filtered anything non-kosher.
8388  */
8389 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
8390 {
8391         struct drm_device *dev = state->dev;
8392         struct amdgpu_device *adev = drm_to_adev(dev);
8393         struct amdgpu_display_manager *dm = &adev->dm;
8394         struct dm_atomic_state *dm_state;
8395         struct dc_state *dc_state = NULL, *dc_state_temp = NULL;
8396         u32 i, j;
8397         struct drm_crtc *crtc;
8398         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
8399         unsigned long flags;
8400         bool wait_for_vblank = true;
8401         struct drm_connector *connector;
8402         struct drm_connector_state *old_con_state, *new_con_state;
8403         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
8404         int crtc_disable_count = 0;
8405         bool mode_set_reset_required = false;
8406         int r;
8407
8408         trace_amdgpu_dm_atomic_commit_tail_begin(state);
8409
8410         r = drm_atomic_helper_wait_for_fences(dev, state, false);
8411         if (unlikely(r))
8412                 DRM_ERROR("Waiting for fences timed out!");
8413
8414         drm_atomic_helper_update_legacy_modeset_state(dev, state);
8415         drm_dp_mst_atomic_wait_for_dependencies(state);
8416
8417         dm_state = dm_atomic_get_new_state(state);
8418         if (dm_state && dm_state->context) {
8419                 dc_state = dm_state->context;
8420         } else {
8421                 /* No state changes, retain current state. */
8422                 dc_state_temp = dc_create_state(dm->dc);
8423                 ASSERT(dc_state_temp);
8424                 dc_state = dc_state_temp;
8425                 dc_resource_state_copy_construct_current(dm->dc, dc_state);
8426         }
8427
8428         for_each_oldnew_crtc_in_state (state, crtc, old_crtc_state,
8429                                        new_crtc_state, i) {
8430                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8431
8432                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8433
8434                 if (old_crtc_state->active &&
8435                     (!new_crtc_state->active ||
8436                      drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8437                         manage_dm_interrupts(adev, acrtc, false);
8438                         dc_stream_release(dm_old_crtc_state->stream);
8439                 }
8440         }
8441
8442         drm_atomic_helper_calc_timestamping_constants(state);
8443
8444         /* update changed items */
8445         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
8446                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8447
8448                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8449                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8450
8451                 drm_dbg_state(state->dev,
8452                         "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
8453                         "planes_changed:%d, mode_changed:%d,active_changed:%d,"
8454                         "connectors_changed:%d\n",
8455                         acrtc->crtc_id,
8456                         new_crtc_state->enable,
8457                         new_crtc_state->active,
8458                         new_crtc_state->planes_changed,
8459                         new_crtc_state->mode_changed,
8460                         new_crtc_state->active_changed,
8461                         new_crtc_state->connectors_changed);
8462
8463                 /* Disable cursor if disabling crtc */
8464                 if (old_crtc_state->active && !new_crtc_state->active) {
8465                         struct dc_cursor_position position;
8466
8467                         memset(&position, 0, sizeof(position));
8468                         mutex_lock(&dm->dc_lock);
8469                         dc_stream_set_cursor_position(dm_old_crtc_state->stream, &position);
8470                         mutex_unlock(&dm->dc_lock);
8471                 }
8472
8473                 /* Copy all transient state flags into dc state */
8474                 if (dm_new_crtc_state->stream) {
8475                         amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
8476                                                             dm_new_crtc_state->stream);
8477                 }
8478
8479                 /* handles headless hotplug case, updating new_state and
8480                  * aconnector as needed
8481                  */
8482
8483                 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
8484
8485                         DRM_DEBUG_ATOMIC("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
8486
8487                         if (!dm_new_crtc_state->stream) {
8488                                 /*
8489                                  * this could happen because of issues with
8490                                  * userspace notifications delivery.
8491                                  * In this case userspace tries to set mode on
8492                                  * display which is disconnected in fact.
8493                                  * dc_sink is NULL in this case on aconnector.
8494                                  * We expect reset mode will come soon.
8495                                  *
8496                                  * This can also happen when unplug is done
8497                                  * during resume sequence ended
8498                                  *
8499                                  * In this case, we want to pretend we still
8500                                  * have a sink to keep the pipe running so that
8501                                  * hw state is consistent with the sw state
8502                                  */
8503                                 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
8504                                                 __func__, acrtc->base.base.id);
8505                                 continue;
8506                         }
8507
8508                         if (dm_old_crtc_state->stream)
8509                                 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
8510
8511                         pm_runtime_get_noresume(dev->dev);
8512
8513                         acrtc->enabled = true;
8514                         acrtc->hw_mode = new_crtc_state->mode;
8515                         crtc->hwmode = new_crtc_state->mode;
8516                         mode_set_reset_required = true;
8517                 } else if (modereset_required(new_crtc_state)) {
8518                         DRM_DEBUG_ATOMIC("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
8519                         /* i.e. reset mode */
8520                         if (dm_old_crtc_state->stream)
8521                                 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
8522
8523                         mode_set_reset_required = true;
8524                 }
8525         } /* for_each_crtc_in_state() */
8526
8527         if (dc_state) {
8528                 /* if there mode set or reset, disable eDP PSR */
8529                 if (mode_set_reset_required) {
8530                         if (dm->vblank_control_workqueue)
8531                                 flush_workqueue(dm->vblank_control_workqueue);
8532
8533                         amdgpu_dm_psr_disable_all(dm);
8534                 }
8535
8536                 dm_enable_per_frame_crtc_master_sync(dc_state);
8537                 mutex_lock(&dm->dc_lock);
8538                 WARN_ON(!dc_commit_streams(dm->dc, dc_state->streams, dc_state->stream_count));
8539
8540                 /* Allow idle optimization when vblank count is 0 for display off */
8541                 if (dm->active_vblank_irq_count == 0)
8542                         dc_allow_idle_optimizations(dm->dc, true);
8543                 mutex_unlock(&dm->dc_lock);
8544         }
8545
8546         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
8547                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8548
8549                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8550
8551                 if (dm_new_crtc_state->stream != NULL) {
8552                         const struct dc_stream_status *status =
8553                                         dc_stream_get_status(dm_new_crtc_state->stream);
8554
8555                         if (!status)
8556                                 status = dc_stream_get_status_from_state(dc_state,
8557                                                                          dm_new_crtc_state->stream);
8558                         if (!status)
8559                                 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc);
8560                         else
8561                                 acrtc->otg_inst = status->primary_otg_inst;
8562                 }
8563         }
8564         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8565                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8566                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8567                 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8568
8569                 pr_debug("[HDCP_DM] -------------- i : %x ----------\n", i);
8570
8571                 if (!connector)
8572                         continue;
8573
8574                 pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n",
8575                         connector->index, connector->status, connector->dpms);
8576                 pr_debug("[HDCP_DM] state protection old: %x new: %x\n",
8577                         old_con_state->content_protection, new_con_state->content_protection);
8578
8579                 if (aconnector->dc_sink) {
8580                         if (aconnector->dc_sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&
8581                                 aconnector->dc_sink->sink_signal != SIGNAL_TYPE_NONE) {
8582                                 pr_debug("[HDCP_DM] pipe_ctx dispname=%s\n",
8583                                 aconnector->dc_sink->edid_caps.display_name);
8584                         }
8585                 }
8586
8587                 new_crtc_state = NULL;
8588                 old_crtc_state = NULL;
8589
8590                 if (acrtc) {
8591                         new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8592                         old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8593                 }
8594
8595                 if (old_crtc_state)
8596                         pr_debug("old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
8597                         old_crtc_state->enable,
8598                         old_crtc_state->active,
8599                         old_crtc_state->mode_changed,
8600                         old_crtc_state->active_changed,
8601                         old_crtc_state->connectors_changed);
8602
8603                 if (new_crtc_state)
8604                         pr_debug("NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
8605                         new_crtc_state->enable,
8606                         new_crtc_state->active,
8607                         new_crtc_state->mode_changed,
8608                         new_crtc_state->active_changed,
8609                         new_crtc_state->connectors_changed);
8610         }
8611
8612         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8613                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8614                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8615                 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8616
8617                 new_crtc_state = NULL;
8618                 old_crtc_state = NULL;
8619
8620                 if (acrtc) {
8621                         new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8622                         old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8623                 }
8624
8625                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8626
8627                 if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL &&
8628                     connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) {
8629                         hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
8630                         new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
8631                         dm_new_con_state->update_hdcp = true;
8632                         continue;
8633                 }
8634
8635                 if (is_content_protection_different(new_crtc_state, old_crtc_state, new_con_state,
8636                                                                                         old_con_state, connector, adev->dm.hdcp_workqueue)) {
8637                         /* when display is unplugged from mst hub, connctor will
8638                          * be destroyed within dm_dp_mst_connector_destroy. connector
8639                          * hdcp perperties, like type, undesired, desired, enabled,
8640                          * will be lost. So, save hdcp properties into hdcp_work within
8641                          * amdgpu_dm_atomic_commit_tail. if the same display is
8642                          * plugged back with same display index, its hdcp properties
8643                          * will be retrieved from hdcp_work within dm_dp_mst_get_modes
8644                          */
8645
8646                         bool enable_encryption = false;
8647
8648                         if (new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED)
8649                                 enable_encryption = true;
8650
8651                         if (aconnector->dc_link && aconnector->dc_sink &&
8652                                 aconnector->dc_link->type == dc_connection_mst_branch) {
8653                                 struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue;
8654                                 struct hdcp_workqueue *hdcp_w =
8655                                         &hdcp_work[aconnector->dc_link->link_index];
8656
8657                                 hdcp_w->hdcp_content_type[connector->index] =
8658                                         new_con_state->hdcp_content_type;
8659                                 hdcp_w->content_protection[connector->index] =
8660                                         new_con_state->content_protection;
8661                         }
8662
8663                         if (new_crtc_state && new_crtc_state->mode_changed &&
8664                                 new_con_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED)
8665                                 enable_encryption = true;
8666
8667                         DRM_INFO("[HDCP_DM] hdcp_update_display enable_encryption = %x\n", enable_encryption);
8668
8669                         hdcp_update_display(
8670                                 adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector,
8671                                 new_con_state->hdcp_content_type, enable_encryption);
8672                 }
8673         }
8674
8675         /* Handle connector state changes */
8676         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8677                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8678                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
8679                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8680                 struct dc_surface_update dummy_updates[MAX_SURFACES];
8681                 struct dc_stream_update stream_update;
8682                 struct dc_info_packet hdr_packet;
8683                 struct dc_stream_status *status = NULL;
8684                 bool abm_changed, hdr_changed, scaling_changed;
8685
8686                 memset(&dummy_updates, 0, sizeof(dummy_updates));
8687                 memset(&stream_update, 0, sizeof(stream_update));
8688
8689                 if (acrtc) {
8690                         new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8691                         old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8692                 }
8693
8694                 /* Skip any modesets/resets */
8695                 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
8696                         continue;
8697
8698                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8699                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8700
8701                 scaling_changed = is_scaling_state_different(dm_new_con_state,
8702                                                              dm_old_con_state);
8703
8704                 abm_changed = dm_new_crtc_state->abm_level !=
8705                               dm_old_crtc_state->abm_level;
8706
8707                 hdr_changed =
8708                         !drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state);
8709
8710                 if (!scaling_changed && !abm_changed && !hdr_changed)
8711                         continue;
8712
8713                 stream_update.stream = dm_new_crtc_state->stream;
8714                 if (scaling_changed) {
8715                         update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
8716                                         dm_new_con_state, dm_new_crtc_state->stream);
8717
8718                         stream_update.src = dm_new_crtc_state->stream->src;
8719                         stream_update.dst = dm_new_crtc_state->stream->dst;
8720                 }
8721
8722                 if (abm_changed) {
8723                         dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level;
8724
8725                         stream_update.abm_level = &dm_new_crtc_state->abm_level;
8726                 }
8727
8728                 if (hdr_changed) {
8729                         fill_hdr_info_packet(new_con_state, &hdr_packet);
8730                         stream_update.hdr_static_metadata = &hdr_packet;
8731                 }
8732
8733                 status = dc_stream_get_status(dm_new_crtc_state->stream);
8734
8735                 if (WARN_ON(!status))
8736                         continue;
8737
8738                 WARN_ON(!status->plane_count);
8739
8740                 /*
8741                  * TODO: DC refuses to perform stream updates without a dc_surface_update.
8742                  * Here we create an empty update on each plane.
8743                  * To fix this, DC should permit updating only stream properties.
8744                  */
8745                 for (j = 0; j < status->plane_count; j++)
8746                         dummy_updates[j].surface = status->plane_states[0];
8747
8748
8749                 mutex_lock(&dm->dc_lock);
8750                 dc_update_planes_and_stream(dm->dc,
8751                                             dummy_updates,
8752                                             status->plane_count,
8753                                             dm_new_crtc_state->stream,
8754                                             &stream_update);
8755                 mutex_unlock(&dm->dc_lock);
8756         }
8757
8758         /**
8759          * Enable interrupts for CRTCs that are newly enabled or went through
8760          * a modeset. It was intentionally deferred until after the front end
8761          * state was modified to wait until the OTG was on and so the IRQ
8762          * handlers didn't access stale or invalid state.
8763          */
8764         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
8765                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8766 #ifdef CONFIG_DEBUG_FS
8767                 enum amdgpu_dm_pipe_crc_source cur_crc_src;
8768 #endif
8769                 /* Count number of newly disabled CRTCs for dropping PM refs later. */
8770                 if (old_crtc_state->active && !new_crtc_state->active)
8771                         crtc_disable_count++;
8772
8773                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8774                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8775
8776                 /* For freesync config update on crtc state and params for irq */
8777                 update_stream_irq_parameters(dm, dm_new_crtc_state);
8778
8779 #ifdef CONFIG_DEBUG_FS
8780                 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8781                 cur_crc_src = acrtc->dm_irq_params.crc_src;
8782                 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8783 #endif
8784
8785                 if (new_crtc_state->active &&
8786                     (!old_crtc_state->active ||
8787                      drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8788                         dc_stream_retain(dm_new_crtc_state->stream);
8789                         acrtc->dm_irq_params.stream = dm_new_crtc_state->stream;
8790                         manage_dm_interrupts(adev, acrtc, true);
8791                 }
8792                 /* Handle vrr on->off / off->on transitions */
8793                 amdgpu_dm_handle_vrr_transition(dm_old_crtc_state, dm_new_crtc_state);
8794
8795 #ifdef CONFIG_DEBUG_FS
8796                 if (new_crtc_state->active &&
8797                     (!old_crtc_state->active ||
8798                      drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8799                         /**
8800                          * Frontend may have changed so reapply the CRC capture
8801                          * settings for the stream.
8802                          */
8803                         if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) {
8804 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
8805                                 if (amdgpu_dm_crc_window_is_activated(crtc)) {
8806                                         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8807                                         acrtc->dm_irq_params.window_param.update_win = true;
8808
8809                                         /**
8810                                          * It takes 2 frames for HW to stably generate CRC when
8811                                          * resuming from suspend, so we set skip_frame_cnt 2.
8812                                          */
8813                                         acrtc->dm_irq_params.window_param.skip_frame_cnt = 2;
8814                                         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8815                                 }
8816 #endif
8817                                 if (amdgpu_dm_crtc_configure_crc_source(
8818                                         crtc, dm_new_crtc_state, cur_crc_src))
8819                                         DRM_DEBUG_DRIVER("Failed to configure crc source");
8820                         }
8821                 }
8822 #endif
8823         }
8824
8825         for_each_new_crtc_in_state(state, crtc, new_crtc_state, j)
8826                 if (new_crtc_state->async_flip)
8827                         wait_for_vblank = false;
8828
8829         /* update planes when needed per crtc*/
8830         for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
8831                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8832
8833                 if (dm_new_crtc_state->stream)
8834                         amdgpu_dm_commit_planes(state, dc_state, dev,
8835                                                 dm, crtc, wait_for_vblank);
8836         }
8837
8838         /* Update audio instances for each connector. */
8839         amdgpu_dm_commit_audio(dev, state);
8840
8841         /* restore the backlight level */
8842         for (i = 0; i < dm->num_of_edps; i++) {
8843                 if (dm->backlight_dev[i] &&
8844                     (dm->actual_brightness[i] != dm->brightness[i]))
8845                         amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]);
8846         }
8847
8848         /*
8849          * send vblank event on all events not handled in flip and
8850          * mark consumed event for drm_atomic_helper_commit_hw_done
8851          */
8852         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8853         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
8854
8855                 if (new_crtc_state->event)
8856                         drm_send_event_locked(dev, &new_crtc_state->event->base);
8857
8858                 new_crtc_state->event = NULL;
8859         }
8860         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8861
8862         /* Signal HW programming completion */
8863         drm_atomic_helper_commit_hw_done(state);
8864
8865         if (wait_for_vblank)
8866                 drm_atomic_helper_wait_for_flip_done(dev, state);
8867
8868         drm_atomic_helper_cleanup_planes(dev, state);
8869
8870         /* return the stolen vga memory back to VRAM */
8871         if (!adev->mman.keep_stolen_vga_memory)
8872                 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
8873         amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
8874
8875         /*
8876          * Finally, drop a runtime PM reference for each newly disabled CRTC,
8877          * so we can put the GPU into runtime suspend if we're not driving any
8878          * displays anymore
8879          */
8880         for (i = 0; i < crtc_disable_count; i++)
8881                 pm_runtime_put_autosuspend(dev->dev);
8882         pm_runtime_mark_last_busy(dev->dev);
8883
8884         if (dc_state_temp)
8885                 dc_release_state(dc_state_temp);
8886 }
8887
8888 static int dm_force_atomic_commit(struct drm_connector *connector)
8889 {
8890         int ret = 0;
8891         struct drm_device *ddev = connector->dev;
8892         struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
8893         struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
8894         struct drm_plane *plane = disconnected_acrtc->base.primary;
8895         struct drm_connector_state *conn_state;
8896         struct drm_crtc_state *crtc_state;
8897         struct drm_plane_state *plane_state;
8898
8899         if (!state)
8900                 return -ENOMEM;
8901
8902         state->acquire_ctx = ddev->mode_config.acquire_ctx;
8903
8904         /* Construct an atomic state to restore previous display setting */
8905
8906         /*
8907          * Attach connectors to drm_atomic_state
8908          */
8909         conn_state = drm_atomic_get_connector_state(state, connector);
8910
8911         ret = PTR_ERR_OR_ZERO(conn_state);
8912         if (ret)
8913                 goto out;
8914
8915         /* Attach crtc to drm_atomic_state*/
8916         crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
8917
8918         ret = PTR_ERR_OR_ZERO(crtc_state);
8919         if (ret)
8920                 goto out;
8921
8922         /* force a restore */
8923         crtc_state->mode_changed = true;
8924
8925         /* Attach plane to drm_atomic_state */
8926         plane_state = drm_atomic_get_plane_state(state, plane);
8927
8928         ret = PTR_ERR_OR_ZERO(plane_state);
8929         if (ret)
8930                 goto out;
8931
8932         /* Call commit internally with the state we just constructed */
8933         ret = drm_atomic_commit(state);
8934
8935 out:
8936         drm_atomic_state_put(state);
8937         if (ret)
8938                 DRM_ERROR("Restoring old state failed with %i\n", ret);
8939
8940         return ret;
8941 }
8942
8943 /*
8944  * This function handles all cases when set mode does not come upon hotplug.
8945  * This includes when a display is unplugged then plugged back into the
8946  * same port and when running without usermode desktop manager supprot
8947  */
8948 void dm_restore_drm_connector_state(struct drm_device *dev,
8949                                     struct drm_connector *connector)
8950 {
8951         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8952         struct amdgpu_crtc *disconnected_acrtc;
8953         struct dm_crtc_state *acrtc_state;
8954
8955         if (!aconnector->dc_sink || !connector->state || !connector->encoder)
8956                 return;
8957
8958         disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
8959         if (!disconnected_acrtc)
8960                 return;
8961
8962         acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
8963         if (!acrtc_state->stream)
8964                 return;
8965
8966         /*
8967          * If the previous sink is not released and different from the current,
8968          * we deduce we are in a state where we can not rely on usermode call
8969          * to turn on the display, so we do it here
8970          */
8971         if (acrtc_state->stream->sink != aconnector->dc_sink)
8972                 dm_force_atomic_commit(&aconnector->base);
8973 }
8974
8975 /*
8976  * Grabs all modesetting locks to serialize against any blocking commits,
8977  * Waits for completion of all non blocking commits.
8978  */
8979 static int do_aquire_global_lock(struct drm_device *dev,
8980                                  struct drm_atomic_state *state)
8981 {
8982         struct drm_crtc *crtc;
8983         struct drm_crtc_commit *commit;
8984         long ret;
8985
8986         /*
8987          * Adding all modeset locks to aquire_ctx will
8988          * ensure that when the framework release it the
8989          * extra locks we are locking here will get released to
8990          */
8991         ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
8992         if (ret)
8993                 return ret;
8994
8995         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8996                 spin_lock(&crtc->commit_lock);
8997                 commit = list_first_entry_or_null(&crtc->commit_list,
8998                                 struct drm_crtc_commit, commit_entry);
8999                 if (commit)
9000                         drm_crtc_commit_get(commit);
9001                 spin_unlock(&crtc->commit_lock);
9002
9003                 if (!commit)
9004                         continue;
9005
9006                 /*
9007                  * Make sure all pending HW programming completed and
9008                  * page flips done
9009                  */
9010                 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
9011
9012                 if (ret > 0)
9013                         ret = wait_for_completion_interruptible_timeout(
9014                                         &commit->flip_done, 10*HZ);
9015
9016                 if (ret == 0)
9017                         DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
9018                                   "timed out\n", crtc->base.id, crtc->name);
9019
9020                 drm_crtc_commit_put(commit);
9021         }
9022
9023         return ret < 0 ? ret : 0;
9024 }
9025
9026 static void get_freesync_config_for_crtc(
9027         struct dm_crtc_state *new_crtc_state,
9028         struct dm_connector_state *new_con_state)
9029 {
9030         struct mod_freesync_config config = {0};
9031         struct amdgpu_dm_connector *aconnector =
9032                         to_amdgpu_dm_connector(new_con_state->base.connector);
9033         struct drm_display_mode *mode = &new_crtc_state->base.mode;
9034         int vrefresh = drm_mode_vrefresh(mode);
9035         bool fs_vid_mode = false;
9036
9037         new_crtc_state->vrr_supported = new_con_state->freesync_capable &&
9038                                         vrefresh >= aconnector->min_vfreq &&
9039                                         vrefresh <= aconnector->max_vfreq;
9040
9041         if (new_crtc_state->vrr_supported) {
9042                 new_crtc_state->stream->ignore_msa_timing_param = true;
9043                 fs_vid_mode = new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
9044
9045                 config.min_refresh_in_uhz = aconnector->min_vfreq * 1000000;
9046                 config.max_refresh_in_uhz = aconnector->max_vfreq * 1000000;
9047                 config.vsif_supported = true;
9048                 config.btr = true;
9049
9050                 if (fs_vid_mode) {
9051                         config.state = VRR_STATE_ACTIVE_FIXED;
9052                         config.fixed_refresh_in_uhz = new_crtc_state->freesync_config.fixed_refresh_in_uhz;
9053                         goto out;
9054                 } else if (new_crtc_state->base.vrr_enabled) {
9055                         config.state = VRR_STATE_ACTIVE_VARIABLE;
9056                 } else {
9057                         config.state = VRR_STATE_INACTIVE;
9058                 }
9059         }
9060 out:
9061         new_crtc_state->freesync_config = config;
9062 }
9063
9064 static void reset_freesync_config_for_crtc(
9065         struct dm_crtc_state *new_crtc_state)
9066 {
9067         new_crtc_state->vrr_supported = false;
9068
9069         memset(&new_crtc_state->vrr_infopacket, 0,
9070                sizeof(new_crtc_state->vrr_infopacket));
9071 }
9072
9073 static bool
9074 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
9075                                  struct drm_crtc_state *new_crtc_state)
9076 {
9077         const struct drm_display_mode *old_mode, *new_mode;
9078
9079         if (!old_crtc_state || !new_crtc_state)
9080                 return false;
9081
9082         old_mode = &old_crtc_state->mode;
9083         new_mode = &new_crtc_state->mode;
9084
9085         if (old_mode->clock       == new_mode->clock &&
9086             old_mode->hdisplay    == new_mode->hdisplay &&
9087             old_mode->vdisplay    == new_mode->vdisplay &&
9088             old_mode->htotal      == new_mode->htotal &&
9089             old_mode->vtotal      != new_mode->vtotal &&
9090             old_mode->hsync_start == new_mode->hsync_start &&
9091             old_mode->vsync_start != new_mode->vsync_start &&
9092             old_mode->hsync_end   == new_mode->hsync_end &&
9093             old_mode->vsync_end   != new_mode->vsync_end &&
9094             old_mode->hskew       == new_mode->hskew &&
9095             old_mode->vscan       == new_mode->vscan &&
9096             (old_mode->vsync_end - old_mode->vsync_start) ==
9097             (new_mode->vsync_end - new_mode->vsync_start))
9098                 return true;
9099
9100         return false;
9101 }
9102
9103 static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state) {
9104         u64 num, den, res;
9105         struct drm_crtc_state *new_crtc_state = &dm_new_crtc_state->base;
9106
9107         dm_new_crtc_state->freesync_config.state = VRR_STATE_ACTIVE_FIXED;
9108
9109         num = (unsigned long long)new_crtc_state->mode.clock * 1000 * 1000000;
9110         den = (unsigned long long)new_crtc_state->mode.htotal *
9111               (unsigned long long)new_crtc_state->mode.vtotal;
9112
9113         res = div_u64(num, den);
9114         dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = res;
9115 }
9116
9117 static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
9118                          struct drm_atomic_state *state,
9119                          struct drm_crtc *crtc,
9120                          struct drm_crtc_state *old_crtc_state,
9121                          struct drm_crtc_state *new_crtc_state,
9122                          bool enable,
9123                          bool *lock_and_validation_needed)
9124 {
9125         struct dm_atomic_state *dm_state = NULL;
9126         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
9127         struct dc_stream_state *new_stream;
9128         int ret = 0;
9129
9130         /*
9131          * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set
9132          * update changed items
9133          */
9134         struct amdgpu_crtc *acrtc = NULL;
9135         struct amdgpu_dm_connector *aconnector = NULL;
9136         struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL;
9137         struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL;
9138
9139         new_stream = NULL;
9140
9141         dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9142         dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9143         acrtc = to_amdgpu_crtc(crtc);
9144         aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
9145
9146         /* TODO This hack should go away */
9147         if (aconnector && enable) {
9148                 /* Make sure fake sink is created in plug-in scenario */
9149                 drm_new_conn_state = drm_atomic_get_new_connector_state(state,
9150                                                             &aconnector->base);
9151                 drm_old_conn_state = drm_atomic_get_old_connector_state(state,
9152                                                             &aconnector->base);
9153
9154                 if (IS_ERR(drm_new_conn_state)) {
9155                         ret = PTR_ERR_OR_ZERO(drm_new_conn_state);
9156                         goto fail;
9157                 }
9158
9159                 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
9160                 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state);
9161
9162                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9163                         goto skip_modeset;
9164
9165                 new_stream = create_validate_stream_for_sink(aconnector,
9166                                                              &new_crtc_state->mode,
9167                                                              dm_new_conn_state,
9168                                                              dm_old_crtc_state->stream);
9169
9170                 /*
9171                  * we can have no stream on ACTION_SET if a display
9172                  * was disconnected during S3, in this case it is not an
9173                  * error, the OS will be updated after detection, and
9174                  * will do the right thing on next atomic commit
9175                  */
9176
9177                 if (!new_stream) {
9178                         DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
9179                                         __func__, acrtc->base.base.id);
9180                         ret = -ENOMEM;
9181                         goto fail;
9182                 }
9183
9184                 /*
9185                  * TODO: Check VSDB bits to decide whether this should
9186                  * be enabled or not.
9187                  */
9188                 new_stream->triggered_crtc_reset.enabled =
9189                         dm->force_timing_sync;
9190
9191                 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
9192
9193                 ret = fill_hdr_info_packet(drm_new_conn_state,
9194                                            &new_stream->hdr_static_metadata);
9195                 if (ret)
9196                         goto fail;
9197
9198                 /*
9199                  * If we already removed the old stream from the context
9200                  * (and set the new stream to NULL) then we can't reuse
9201                  * the old stream even if the stream and scaling are unchanged.
9202                  * We'll hit the BUG_ON and black screen.
9203                  *
9204                  * TODO: Refactor this function to allow this check to work
9205                  * in all conditions.
9206                  */
9207                 if (amdgpu_freesync_vid_mode &&
9208                     dm_new_crtc_state->stream &&
9209                     is_timing_unchanged_for_freesync(new_crtc_state, old_crtc_state))
9210                         goto skip_modeset;
9211
9212                 if (dm_new_crtc_state->stream &&
9213                     dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
9214                     dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
9215                         new_crtc_state->mode_changed = false;
9216                         DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
9217                                          new_crtc_state->mode_changed);
9218                 }
9219         }
9220
9221         /* mode_changed flag may get updated above, need to check again */
9222         if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9223                 goto skip_modeset;
9224
9225         drm_dbg_state(state->dev,
9226                 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
9227                 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
9228                 "connectors_changed:%d\n",
9229                 acrtc->crtc_id,
9230                 new_crtc_state->enable,
9231                 new_crtc_state->active,
9232                 new_crtc_state->planes_changed,
9233                 new_crtc_state->mode_changed,
9234                 new_crtc_state->active_changed,
9235                 new_crtc_state->connectors_changed);
9236
9237         /* Remove stream for any changed/disabled CRTC */
9238         if (!enable) {
9239
9240                 if (!dm_old_crtc_state->stream)
9241                         goto skip_modeset;
9242
9243                 /* Unset freesync video if it was active before */
9244                 if (dm_old_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) {
9245                         dm_new_crtc_state->freesync_config.state = VRR_STATE_INACTIVE;
9246                         dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = 0;
9247                 }
9248
9249                 /* Now check if we should set freesync video mode */
9250                 if (amdgpu_freesync_vid_mode && dm_new_crtc_state->stream &&
9251                     is_timing_unchanged_for_freesync(new_crtc_state,
9252                                                      old_crtc_state)) {
9253                         new_crtc_state->mode_changed = false;
9254                         DRM_DEBUG_DRIVER(
9255                                 "Mode change not required for front porch change, "
9256                                 "setting mode_changed to %d",
9257                                 new_crtc_state->mode_changed);
9258
9259                         set_freesync_fixed_config(dm_new_crtc_state);
9260
9261                         goto skip_modeset;
9262                 } else if (amdgpu_freesync_vid_mode && aconnector &&
9263                            is_freesync_video_mode(&new_crtc_state->mode,
9264                                                   aconnector)) {
9265                         struct drm_display_mode *high_mode;
9266
9267                         high_mode = get_highest_refresh_rate_mode(aconnector, false);
9268                         if (!drm_mode_equal(&new_crtc_state->mode, high_mode)) {
9269                                 set_freesync_fixed_config(dm_new_crtc_state);
9270                         }
9271                 }
9272
9273                 ret = dm_atomic_get_state(state, &dm_state);
9274                 if (ret)
9275                         goto fail;
9276
9277                 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
9278                                 crtc->base.id);
9279
9280                 /* i.e. reset mode */
9281                 if (dc_remove_stream_from_ctx(
9282                                 dm->dc,
9283                                 dm_state->context,
9284                                 dm_old_crtc_state->stream) != DC_OK) {
9285                         ret = -EINVAL;
9286                         goto fail;
9287                 }
9288
9289                 dc_stream_release(dm_old_crtc_state->stream);
9290                 dm_new_crtc_state->stream = NULL;
9291
9292                 reset_freesync_config_for_crtc(dm_new_crtc_state);
9293
9294                 *lock_and_validation_needed = true;
9295
9296         } else {/* Add stream for any updated/enabled CRTC */
9297                 /*
9298                  * Quick fix to prevent NULL pointer on new_stream when
9299                  * added MST connectors not found in existing crtc_state in the chained mode
9300                  * TODO: need to dig out the root cause of that
9301                  */
9302                 if (!aconnector)
9303                         goto skip_modeset;
9304
9305                 if (modereset_required(new_crtc_state))
9306                         goto skip_modeset;
9307
9308                 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, new_stream,
9309                                      dm_old_crtc_state->stream)) {
9310
9311                         WARN_ON(dm_new_crtc_state->stream);
9312
9313                         ret = dm_atomic_get_state(state, &dm_state);
9314                         if (ret)
9315                                 goto fail;
9316
9317                         dm_new_crtc_state->stream = new_stream;
9318
9319                         dc_stream_retain(new_stream);
9320
9321                         DRM_DEBUG_ATOMIC("Enabling DRM crtc: %d\n",
9322                                          crtc->base.id);
9323
9324                         if (dc_add_stream_to_ctx(
9325                                         dm->dc,
9326                                         dm_state->context,
9327                                         dm_new_crtc_state->stream) != DC_OK) {
9328                                 ret = -EINVAL;
9329                                 goto fail;
9330                         }
9331
9332                         *lock_and_validation_needed = true;
9333                 }
9334         }
9335
9336 skip_modeset:
9337         /* Release extra reference */
9338         if (new_stream)
9339                  dc_stream_release(new_stream);
9340
9341         /*
9342          * We want to do dc stream updates that do not require a
9343          * full modeset below.
9344          */
9345         if (!(enable && aconnector && new_crtc_state->active))
9346                 return 0;
9347         /*
9348          * Given above conditions, the dc state cannot be NULL because:
9349          * 1. We're in the process of enabling CRTCs (just been added
9350          *    to the dc context, or already is on the context)
9351          * 2. Has a valid connector attached, and
9352          * 3. Is currently active and enabled.
9353          * => The dc stream state currently exists.
9354          */
9355         BUG_ON(dm_new_crtc_state->stream == NULL);
9356
9357         /* Scaling or underscan settings */
9358         if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state) ||
9359                                 drm_atomic_crtc_needs_modeset(new_crtc_state))
9360                 update_stream_scaling_settings(
9361                         &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);
9362
9363         /* ABM settings */
9364         dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
9365
9366         /*
9367          * Color management settings. We also update color properties
9368          * when a modeset is needed, to ensure it gets reprogrammed.
9369          */
9370         if (dm_new_crtc_state->base.color_mgmt_changed ||
9371             drm_atomic_crtc_needs_modeset(new_crtc_state)) {
9372                 ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state);
9373                 if (ret)
9374                         goto fail;
9375         }
9376
9377         /* Update Freesync settings. */
9378         get_freesync_config_for_crtc(dm_new_crtc_state,
9379                                      dm_new_conn_state);
9380
9381         return ret;
9382
9383 fail:
9384         if (new_stream)
9385                 dc_stream_release(new_stream);
9386         return ret;
9387 }
9388
9389 static bool should_reset_plane(struct drm_atomic_state *state,
9390                                struct drm_plane *plane,
9391                                struct drm_plane_state *old_plane_state,
9392                                struct drm_plane_state *new_plane_state)
9393 {
9394         struct drm_plane *other;
9395         struct drm_plane_state *old_other_state, *new_other_state;
9396         struct drm_crtc_state *new_crtc_state;
9397         int i;
9398
9399         /*
9400          * TODO: Remove this hack once the checks below are sufficient
9401          * enough to determine when we need to reset all the planes on
9402          * the stream.
9403          */
9404         if (state->allow_modeset)
9405                 return true;
9406
9407         /* Exit early if we know that we're adding or removing the plane. */
9408         if (old_plane_state->crtc != new_plane_state->crtc)
9409                 return true;
9410
9411         /* old crtc == new_crtc == NULL, plane not in context. */
9412         if (!new_plane_state->crtc)
9413                 return false;
9414
9415         new_crtc_state =
9416                 drm_atomic_get_new_crtc_state(state, new_plane_state->crtc);
9417
9418         if (!new_crtc_state)
9419                 return true;
9420
9421         /* CRTC Degamma changes currently require us to recreate planes. */
9422         if (new_crtc_state->color_mgmt_changed)
9423                 return true;
9424
9425         if (drm_atomic_crtc_needs_modeset(new_crtc_state))
9426                 return true;
9427
9428         /*
9429          * If there are any new primary or overlay planes being added or
9430          * removed then the z-order can potentially change. To ensure
9431          * correct z-order and pipe acquisition the current DC architecture
9432          * requires us to remove and recreate all existing planes.
9433          *
9434          * TODO: Come up with a more elegant solution for this.
9435          */
9436         for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) {
9437                 struct amdgpu_framebuffer *old_afb, *new_afb;
9438                 if (other->type == DRM_PLANE_TYPE_CURSOR)
9439                         continue;
9440
9441                 if (old_other_state->crtc != new_plane_state->crtc &&
9442                     new_other_state->crtc != new_plane_state->crtc)
9443                         continue;
9444
9445                 if (old_other_state->crtc != new_other_state->crtc)
9446                         return true;
9447
9448                 /* Src/dst size and scaling updates. */
9449                 if (old_other_state->src_w != new_other_state->src_w ||
9450                     old_other_state->src_h != new_other_state->src_h ||
9451                     old_other_state->crtc_w != new_other_state->crtc_w ||
9452                     old_other_state->crtc_h != new_other_state->crtc_h)
9453                         return true;
9454
9455                 /* Rotation / mirroring updates. */
9456                 if (old_other_state->rotation != new_other_state->rotation)
9457                         return true;
9458
9459                 /* Blending updates. */
9460                 if (old_other_state->pixel_blend_mode !=
9461                     new_other_state->pixel_blend_mode)
9462                         return true;
9463
9464                 /* Alpha updates. */
9465                 if (old_other_state->alpha != new_other_state->alpha)
9466                         return true;
9467
9468                 /* Colorspace changes. */
9469                 if (old_other_state->color_range != new_other_state->color_range ||
9470                     old_other_state->color_encoding != new_other_state->color_encoding)
9471                         return true;
9472
9473                 /* Framebuffer checks fall at the end. */
9474                 if (!old_other_state->fb || !new_other_state->fb)
9475                         continue;
9476
9477                 /* Pixel format changes can require bandwidth updates. */
9478                 if (old_other_state->fb->format != new_other_state->fb->format)
9479                         return true;
9480
9481                 old_afb = (struct amdgpu_framebuffer *)old_other_state->fb;
9482                 new_afb = (struct amdgpu_framebuffer *)new_other_state->fb;
9483
9484                 /* Tiling and DCC changes also require bandwidth updates. */
9485                 if (old_afb->tiling_flags != new_afb->tiling_flags ||
9486                     old_afb->base.modifier != new_afb->base.modifier)
9487                         return true;
9488         }
9489
9490         return false;
9491 }
9492
9493 static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc,
9494                               struct drm_plane_state *new_plane_state,
9495                               struct drm_framebuffer *fb)
9496 {
9497         struct amdgpu_device *adev = drm_to_adev(new_acrtc->base.dev);
9498         struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
9499         unsigned int pitch;
9500         bool linear;
9501
9502         if (fb->width > new_acrtc->max_cursor_width ||
9503             fb->height > new_acrtc->max_cursor_height) {
9504                 DRM_DEBUG_ATOMIC("Bad cursor FB size %dx%d\n",
9505                                  new_plane_state->fb->width,
9506                                  new_plane_state->fb->height);
9507                 return -EINVAL;
9508         }
9509         if (new_plane_state->src_w != fb->width << 16 ||
9510             new_plane_state->src_h != fb->height << 16) {
9511                 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
9512                 return -EINVAL;
9513         }
9514
9515         /* Pitch in pixels */
9516         pitch = fb->pitches[0] / fb->format->cpp[0];
9517
9518         if (fb->width != pitch) {
9519                 DRM_DEBUG_ATOMIC("Cursor FB width %d doesn't match pitch %d",
9520                                  fb->width, pitch);
9521                 return -EINVAL;
9522         }
9523
9524         switch (pitch) {
9525         case 64:
9526         case 128:
9527         case 256:
9528                 /* FB pitch is supported by cursor plane */
9529                 break;
9530         default:
9531                 DRM_DEBUG_ATOMIC("Bad cursor FB pitch %d px\n", pitch);
9532                 return -EINVAL;
9533         }
9534
9535         /* Core DRM takes care of checking FB modifiers, so we only need to
9536          * check tiling flags when the FB doesn't have a modifier. */
9537         if (!(fb->flags & DRM_MODE_FB_MODIFIERS)) {
9538                 if (adev->family < AMDGPU_FAMILY_AI) {
9539                         linear = AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_2D_TILED_THIN1 &&
9540                                  AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 &&
9541                                  AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE) == 0;
9542                 } else {
9543                         linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0;
9544                 }
9545                 if (!linear) {
9546                         DRM_DEBUG_ATOMIC("Cursor FB not linear");
9547                         return -EINVAL;
9548                 }
9549         }
9550
9551         return 0;
9552 }
9553
9554 static int dm_update_plane_state(struct dc *dc,
9555                                  struct drm_atomic_state *state,
9556                                  struct drm_plane *plane,
9557                                  struct drm_plane_state *old_plane_state,
9558                                  struct drm_plane_state *new_plane_state,
9559                                  bool enable,
9560                                  bool *lock_and_validation_needed,
9561                                  bool *is_top_most_overlay)
9562 {
9563
9564         struct dm_atomic_state *dm_state = NULL;
9565         struct drm_crtc *new_plane_crtc, *old_plane_crtc;
9566         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
9567         struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
9568         struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
9569         struct amdgpu_crtc *new_acrtc;
9570         bool needs_reset;
9571         int ret = 0;
9572
9573
9574         new_plane_crtc = new_plane_state->crtc;
9575         old_plane_crtc = old_plane_state->crtc;
9576         dm_new_plane_state = to_dm_plane_state(new_plane_state);
9577         dm_old_plane_state = to_dm_plane_state(old_plane_state);
9578
9579         if (plane->type == DRM_PLANE_TYPE_CURSOR) {
9580                 if (!enable || !new_plane_crtc ||
9581                         drm_atomic_plane_disabling(plane->state, new_plane_state))
9582                         return 0;
9583
9584                 new_acrtc = to_amdgpu_crtc(new_plane_crtc);
9585
9586                 if (new_plane_state->src_x != 0 || new_plane_state->src_y != 0) {
9587                         DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
9588                         return -EINVAL;
9589                 }
9590
9591                 if (new_plane_state->fb) {
9592                         ret = dm_check_cursor_fb(new_acrtc, new_plane_state,
9593                                                  new_plane_state->fb);
9594                         if (ret)
9595                                 return ret;
9596                 }
9597
9598                 return 0;
9599         }
9600
9601         needs_reset = should_reset_plane(state, plane, old_plane_state,
9602                                          new_plane_state);
9603
9604         /* Remove any changed/removed planes */
9605         if (!enable) {
9606                 if (!needs_reset)
9607                         return 0;
9608
9609                 if (!old_plane_crtc)
9610                         return 0;
9611
9612                 old_crtc_state = drm_atomic_get_old_crtc_state(
9613                                 state, old_plane_crtc);
9614                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9615
9616                 if (!dm_old_crtc_state->stream)
9617                         return 0;
9618
9619                 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",
9620                                 plane->base.id, old_plane_crtc->base.id);
9621
9622                 ret = dm_atomic_get_state(state, &dm_state);
9623                 if (ret)
9624                         return ret;
9625
9626                 if (!dc_remove_plane_from_context(
9627                                 dc,
9628                                 dm_old_crtc_state->stream,
9629                                 dm_old_plane_state->dc_state,
9630                                 dm_state->context)) {
9631
9632                         return -EINVAL;
9633                 }
9634
9635
9636                 dc_plane_state_release(dm_old_plane_state->dc_state);
9637                 dm_new_plane_state->dc_state = NULL;
9638
9639                 *lock_and_validation_needed = true;
9640
9641         } else { /* Add new planes */
9642                 struct dc_plane_state *dc_new_plane_state;
9643
9644                 if (drm_atomic_plane_disabling(plane->state, new_plane_state))
9645                         return 0;
9646
9647                 if (!new_plane_crtc)
9648                         return 0;
9649
9650                 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
9651                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9652
9653                 if (!dm_new_crtc_state->stream)
9654                         return 0;
9655
9656                 if (!needs_reset)
9657                         return 0;
9658
9659                 ret = amdgpu_dm_plane_helper_check_state(new_plane_state, new_crtc_state);
9660                 if (ret)
9661                         return ret;
9662
9663                 WARN_ON(dm_new_plane_state->dc_state);
9664
9665                 dc_new_plane_state = dc_create_plane_state(dc);
9666                 if (!dc_new_plane_state)
9667                         return -ENOMEM;
9668
9669                 /* Block top most plane from being a video plane */
9670                 if (plane->type == DRM_PLANE_TYPE_OVERLAY) {
9671                         if (is_video_format(new_plane_state->fb->format->format) && *is_top_most_overlay)
9672                                 return -EINVAL;
9673                         else
9674                                 *is_top_most_overlay = false;
9675                 }
9676
9677                 DRM_DEBUG_ATOMIC("Enabling DRM plane: %d on DRM crtc %d\n",
9678                                  plane->base.id, new_plane_crtc->base.id);
9679
9680                 ret = fill_dc_plane_attributes(
9681                         drm_to_adev(new_plane_crtc->dev),
9682                         dc_new_plane_state,
9683                         new_plane_state,
9684                         new_crtc_state);
9685                 if (ret) {
9686                         dc_plane_state_release(dc_new_plane_state);
9687                         return ret;
9688                 }
9689
9690                 ret = dm_atomic_get_state(state, &dm_state);
9691                 if (ret) {
9692                         dc_plane_state_release(dc_new_plane_state);
9693                         return ret;
9694                 }
9695
9696                 /*
9697                  * Any atomic check errors that occur after this will
9698                  * not need a release. The plane state will be attached
9699                  * to the stream, and therefore part of the atomic
9700                  * state. It'll be released when the atomic state is
9701                  * cleaned.
9702                  */
9703                 if (!dc_add_plane_to_context(
9704                                 dc,
9705                                 dm_new_crtc_state->stream,
9706                                 dc_new_plane_state,
9707                                 dm_state->context)) {
9708
9709                         dc_plane_state_release(dc_new_plane_state);
9710                         return -EINVAL;
9711                 }
9712
9713                 dm_new_plane_state->dc_state = dc_new_plane_state;
9714
9715                 dm_new_crtc_state->mpo_requested |= (plane->type == DRM_PLANE_TYPE_OVERLAY);
9716
9717                 /* Tell DC to do a full surface update every time there
9718                  * is a plane change. Inefficient, but works for now.
9719                  */
9720                 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
9721
9722                 *lock_and_validation_needed = true;
9723         }
9724
9725
9726         return ret;
9727 }
9728
9729 static void dm_get_oriented_plane_size(struct drm_plane_state *plane_state,
9730                                        int *src_w, int *src_h)
9731 {
9732         switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
9733         case DRM_MODE_ROTATE_90:
9734         case DRM_MODE_ROTATE_270:
9735                 *src_w = plane_state->src_h >> 16;
9736                 *src_h = plane_state->src_w >> 16;
9737                 break;
9738         case DRM_MODE_ROTATE_0:
9739         case DRM_MODE_ROTATE_180:
9740         default:
9741                 *src_w = plane_state->src_w >> 16;
9742                 *src_h = plane_state->src_h >> 16;
9743                 break;
9744         }
9745 }
9746
9747 static int dm_check_crtc_cursor(struct drm_atomic_state *state,
9748                                 struct drm_crtc *crtc,
9749                                 struct drm_crtc_state *new_crtc_state)
9750 {
9751         struct drm_plane *cursor = crtc->cursor, *underlying;
9752         struct drm_plane_state *new_cursor_state, *new_underlying_state;
9753         int i;
9754         int cursor_scale_w, cursor_scale_h, underlying_scale_w, underlying_scale_h;
9755         int cursor_src_w, cursor_src_h;
9756         int underlying_src_w, underlying_src_h;
9757
9758         /* On DCE and DCN there is no dedicated hardware cursor plane. We get a
9759          * cursor per pipe but it's going to inherit the scaling and
9760          * positioning from the underlying pipe. Check the cursor plane's
9761          * blending properties match the underlying planes'. */
9762
9763         new_cursor_state = drm_atomic_get_new_plane_state(state, cursor);
9764         if (!new_cursor_state || !new_cursor_state->fb) {
9765                 return 0;
9766         }
9767
9768         dm_get_oriented_plane_size(new_cursor_state, &cursor_src_w, &cursor_src_h);
9769         cursor_scale_w = new_cursor_state->crtc_w * 1000 / cursor_src_w;
9770         cursor_scale_h = new_cursor_state->crtc_h * 1000 / cursor_src_h;
9771
9772         for_each_new_plane_in_state_reverse(state, underlying, new_underlying_state, i) {
9773                 /* Narrow down to non-cursor planes on the same CRTC as the cursor */
9774                 if (new_underlying_state->crtc != crtc || underlying == crtc->cursor)
9775                         continue;
9776
9777                 /* Ignore disabled planes */
9778                 if (!new_underlying_state->fb)
9779                         continue;
9780
9781                 dm_get_oriented_plane_size(new_underlying_state,
9782                                            &underlying_src_w, &underlying_src_h);
9783                 underlying_scale_w = new_underlying_state->crtc_w * 1000 / underlying_src_w;
9784                 underlying_scale_h = new_underlying_state->crtc_h * 1000 / underlying_src_h;
9785
9786                 if (cursor_scale_w != underlying_scale_w ||
9787                     cursor_scale_h != underlying_scale_h) {
9788                         drm_dbg_atomic(crtc->dev,
9789                                        "Cursor [PLANE:%d:%s] scaling doesn't match underlying [PLANE:%d:%s]\n",
9790                                        cursor->base.id, cursor->name, underlying->base.id, underlying->name);
9791                         return -EINVAL;
9792                 }
9793
9794                 /* If this plane covers the whole CRTC, no need to check planes underneath */
9795                 if (new_underlying_state->crtc_x <= 0 &&
9796                     new_underlying_state->crtc_y <= 0 &&
9797                     new_underlying_state->crtc_x + new_underlying_state->crtc_w >= new_crtc_state->mode.hdisplay &&
9798                     new_underlying_state->crtc_y + new_underlying_state->crtc_h >= new_crtc_state->mode.vdisplay)
9799                         break;
9800         }
9801
9802         return 0;
9803 }
9804
9805 static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc)
9806 {
9807         struct drm_connector *connector;
9808         struct drm_connector_state *conn_state, *old_conn_state;
9809         struct amdgpu_dm_connector *aconnector = NULL;
9810         int i;
9811         for_each_oldnew_connector_in_state(state, connector, old_conn_state, conn_state, i) {
9812                 if (!conn_state->crtc)
9813                         conn_state = old_conn_state;
9814
9815                 if (conn_state->crtc != crtc)
9816                         continue;
9817
9818                 aconnector = to_amdgpu_dm_connector(connector);
9819                 if (!aconnector->mst_output_port || !aconnector->mst_root)
9820                         aconnector = NULL;
9821                 else
9822                         break;
9823         }
9824
9825         if (!aconnector)
9826                 return 0;
9827
9828         return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_root->mst_mgr);
9829 }
9830
9831 /**
9832  * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.
9833  *
9834  * @dev: The DRM device
9835  * @state: The atomic state to commit
9836  *
9837  * Validate that the given atomic state is programmable by DC into hardware.
9838  * This involves constructing a &struct dc_state reflecting the new hardware
9839  * state we wish to commit, then querying DC to see if it is programmable. It's
9840  * important not to modify the existing DC state. Otherwise, atomic_check
9841  * may unexpectedly commit hardware changes.
9842  *
9843  * When validating the DC state, it's important that the right locks are
9844  * acquired. For full updates case which removes/adds/updates streams on one
9845  * CRTC while flipping on another CRTC, acquiring global lock will guarantee
9846  * that any such full update commit will wait for completion of any outstanding
9847  * flip using DRMs synchronization events.
9848  *
9849  * Note that DM adds the affected connectors for all CRTCs in state, when that
9850  * might not seem necessary. This is because DC stream creation requires the
9851  * DC sink, which is tied to the DRM connector state. Cleaning this up should
9852  * be possible but non-trivial - a possible TODO item.
9853  *
9854  * Return: -Error code if validation failed.
9855  */
9856 static int amdgpu_dm_atomic_check(struct drm_device *dev,
9857                                   struct drm_atomic_state *state)
9858 {
9859         struct amdgpu_device *adev = drm_to_adev(dev);
9860         struct dm_atomic_state *dm_state = NULL;
9861         struct dc *dc = adev->dm.dc;
9862         struct drm_connector *connector;
9863         struct drm_connector_state *old_con_state, *new_con_state;
9864         struct drm_crtc *crtc;
9865         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
9866         struct drm_plane *plane;
9867         struct drm_plane_state *old_plane_state, *new_plane_state;
9868         enum dc_status status;
9869         int ret, i;
9870         bool lock_and_validation_needed = false;
9871         bool is_top_most_overlay = true;
9872         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
9873         struct drm_dp_mst_topology_mgr *mgr;
9874         struct drm_dp_mst_topology_state *mst_state;
9875         struct dsc_mst_fairness_vars vars[MAX_PIPES];
9876
9877         trace_amdgpu_dm_atomic_check_begin(state);
9878
9879         ret = drm_atomic_helper_check_modeset(dev, state);
9880         if (ret) {
9881                 DRM_DEBUG_DRIVER("drm_atomic_helper_check_modeset() failed\n");
9882                 goto fail;
9883         }
9884
9885         /* Check connector changes */
9886         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
9887                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
9888                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
9889
9890                 /* Skip connectors that are disabled or part of modeset already. */
9891                 if (!new_con_state->crtc)
9892                         continue;
9893
9894                 new_crtc_state = drm_atomic_get_crtc_state(state, new_con_state->crtc);
9895                 if (IS_ERR(new_crtc_state)) {
9896                         DRM_DEBUG_DRIVER("drm_atomic_get_crtc_state() failed\n");
9897                         ret = PTR_ERR(new_crtc_state);
9898                         goto fail;
9899                 }
9900
9901                 if (dm_old_con_state->abm_level != dm_new_con_state->abm_level ||
9902                     dm_old_con_state->scaling != dm_new_con_state->scaling)
9903                         new_crtc_state->connectors_changed = true;
9904         }
9905
9906         if (dc_resource_is_dsc_encoding_supported(dc)) {
9907                 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
9908                         if (drm_atomic_crtc_needs_modeset(new_crtc_state)) {
9909                                 ret = add_affected_mst_dsc_crtcs(state, crtc);
9910                                 if (ret) {
9911                                         DRM_DEBUG_DRIVER("add_affected_mst_dsc_crtcs() failed\n");
9912                                         goto fail;
9913                                 }
9914                         }
9915                 }
9916         }
9917         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
9918                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9919
9920                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
9921                     !new_crtc_state->color_mgmt_changed &&
9922                     old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled &&
9923                         dm_old_crtc_state->dsc_force_changed == false)
9924                         continue;
9925
9926                 ret = amdgpu_dm_verify_lut_sizes(new_crtc_state);
9927                 if (ret) {
9928                         DRM_DEBUG_DRIVER("amdgpu_dm_verify_lut_sizes() failed\n");
9929                         goto fail;
9930                 }
9931
9932                 if (!new_crtc_state->enable)
9933                         continue;
9934
9935                 ret = drm_atomic_add_affected_connectors(state, crtc);
9936                 if (ret) {
9937                         DRM_DEBUG_DRIVER("drm_atomic_add_affected_connectors() failed\n");
9938                         goto fail;
9939                 }
9940
9941                 ret = drm_atomic_add_affected_planes(state, crtc);
9942                 if (ret) {
9943                         DRM_DEBUG_DRIVER("drm_atomic_add_affected_planes() failed\n");
9944                         goto fail;
9945                 }
9946
9947                 if (dm_old_crtc_state->dsc_force_changed)
9948                         new_crtc_state->mode_changed = true;
9949         }
9950
9951         /*
9952          * Add all primary and overlay planes on the CRTC to the state
9953          * whenever a plane is enabled to maintain correct z-ordering
9954          * and to enable fast surface updates.
9955          */
9956         drm_for_each_crtc(crtc, dev) {
9957                 bool modified = false;
9958
9959                 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
9960                         if (plane->type == DRM_PLANE_TYPE_CURSOR)
9961                                 continue;
9962
9963                         if (new_plane_state->crtc == crtc ||
9964                             old_plane_state->crtc == crtc) {
9965                                 modified = true;
9966                                 break;
9967                         }
9968                 }
9969
9970                 if (!modified)
9971                         continue;
9972
9973                 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) {
9974                         if (plane->type == DRM_PLANE_TYPE_CURSOR)
9975                                 continue;
9976
9977                         new_plane_state =
9978                                 drm_atomic_get_plane_state(state, plane);
9979
9980                         if (IS_ERR(new_plane_state)) {
9981                                 ret = PTR_ERR(new_plane_state);
9982                                 DRM_DEBUG_DRIVER("new_plane_state is BAD\n");
9983                                 goto fail;
9984                         }
9985                 }
9986         }
9987
9988         /*
9989          * DC consults the zpos (layer_index in DC terminology) to determine the
9990          * hw plane on which to enable the hw cursor (see
9991          * `dcn10_can_pipe_disable_cursor`). By now, all modified planes are in
9992          * atomic state, so call drm helper to normalize zpos.
9993          */
9994         ret = drm_atomic_normalize_zpos(dev, state);
9995         if (ret) {
9996                 drm_dbg(dev, "drm_atomic_normalize_zpos() failed\n");
9997                 goto fail;
9998         }
9999
10000         /* Remove exiting planes if they are modified */
10001         for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
10002                 ret = dm_update_plane_state(dc, state, plane,
10003                                             old_plane_state,
10004                                             new_plane_state,
10005                                             false,
10006                                             &lock_and_validation_needed,
10007                                             &is_top_most_overlay);
10008                 if (ret) {
10009                         DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n");
10010                         goto fail;
10011                 }
10012         }
10013
10014         /* Disable all crtcs which require disable */
10015         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10016                 ret = dm_update_crtc_state(&adev->dm, state, crtc,
10017                                            old_crtc_state,
10018                                            new_crtc_state,
10019                                            false,
10020                                            &lock_and_validation_needed);
10021                 if (ret) {
10022                         DRM_DEBUG_DRIVER("DISABLE: dm_update_crtc_state() failed\n");
10023                         goto fail;
10024                 }
10025         }
10026
10027         /* Enable all crtcs which require enable */
10028         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10029                 ret = dm_update_crtc_state(&adev->dm, state, crtc,
10030                                            old_crtc_state,
10031                                            new_crtc_state,
10032                                            true,
10033                                            &lock_and_validation_needed);
10034                 if (ret) {
10035                         DRM_DEBUG_DRIVER("ENABLE: dm_update_crtc_state() failed\n");
10036                         goto fail;
10037                 }
10038         }
10039
10040         /* Add new/modified planes */
10041         for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
10042                 ret = dm_update_plane_state(dc, state, plane,
10043                                             old_plane_state,
10044                                             new_plane_state,
10045                                             true,
10046                                             &lock_and_validation_needed,
10047                                             &is_top_most_overlay);
10048                 if (ret) {
10049                         DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n");
10050                         goto fail;
10051                 }
10052         }
10053
10054         if (dc_resource_is_dsc_encoding_supported(dc)) {
10055                 ret = pre_validate_dsc(state, &dm_state, vars);
10056                 if (ret != 0)
10057                         goto fail;
10058         }
10059
10060         /* Run this here since we want to validate the streams we created */
10061         ret = drm_atomic_helper_check_planes(dev, state);
10062         if (ret) {
10063                 DRM_DEBUG_DRIVER("drm_atomic_helper_check_planes() failed\n");
10064                 goto fail;
10065         }
10066
10067         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10068                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
10069                 if (dm_new_crtc_state->mpo_requested)
10070                         DRM_DEBUG_DRIVER("MPO enablement requested on crtc:[%p]\n", crtc);
10071         }
10072
10073         /* Check cursor planes scaling */
10074         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10075                 ret = dm_check_crtc_cursor(state, crtc, new_crtc_state);
10076                 if (ret) {
10077                         DRM_DEBUG_DRIVER("dm_check_crtc_cursor() failed\n");
10078                         goto fail;
10079                 }
10080         }
10081
10082         if (state->legacy_cursor_update) {
10083                 /*
10084                  * This is a fast cursor update coming from the plane update
10085                  * helper, check if it can be done asynchronously for better
10086                  * performance.
10087                  */
10088                 state->async_update =
10089                         !drm_atomic_helper_async_check(dev, state);
10090
10091                 /*
10092                  * Skip the remaining global validation if this is an async
10093                  * update. Cursor updates can be done without affecting
10094                  * state or bandwidth calcs and this avoids the performance
10095                  * penalty of locking the private state object and
10096                  * allocating a new dc_state.
10097                  */
10098                 if (state->async_update)
10099                         return 0;
10100         }
10101
10102         /* Check scaling and underscan changes*/
10103         /* TODO Removed scaling changes validation due to inability to commit
10104          * new stream into context w\o causing full reset. Need to
10105          * decide how to handle.
10106          */
10107         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
10108                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
10109                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
10110                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
10111
10112                 /* Skip any modesets/resets */
10113                 if (!acrtc || drm_atomic_crtc_needs_modeset(
10114                                 drm_atomic_get_new_crtc_state(state, &acrtc->base)))
10115                         continue;
10116
10117                 /* Skip any thing not scale or underscan changes */
10118                 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
10119                         continue;
10120
10121                 lock_and_validation_needed = true;
10122         }
10123
10124         /* set the slot info for each mst_state based on the link encoding format */
10125         for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) {
10126                 struct amdgpu_dm_connector *aconnector;
10127                 struct drm_connector *connector;
10128                 struct drm_connector_list_iter iter;
10129                 u8 link_coding_cap;
10130
10131                 drm_connector_list_iter_begin(dev, &iter);
10132                 drm_for_each_connector_iter(connector, &iter) {
10133                         if (connector->index == mst_state->mgr->conn_base_id) {
10134                                 aconnector = to_amdgpu_dm_connector(connector);
10135                                 link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link);
10136                                 drm_dp_mst_update_slots(mst_state, link_coding_cap);
10137
10138                                 break;
10139                         }
10140                 }
10141                 drm_connector_list_iter_end(&iter);
10142         }
10143
10144         /**
10145          * Streams and planes are reset when there are changes that affect
10146          * bandwidth. Anything that affects bandwidth needs to go through
10147          * DC global validation to ensure that the configuration can be applied
10148          * to hardware.
10149          *
10150          * We have to currently stall out here in atomic_check for outstanding
10151          * commits to finish in this case because our IRQ handlers reference
10152          * DRM state directly - we can end up disabling interrupts too early
10153          * if we don't.
10154          *
10155          * TODO: Remove this stall and drop DM state private objects.
10156          */
10157         if (lock_and_validation_needed) {
10158                 ret = dm_atomic_get_state(state, &dm_state);
10159                 if (ret) {
10160                         DRM_DEBUG_DRIVER("dm_atomic_get_state() failed\n");
10161                         goto fail;
10162                 }
10163
10164                 ret = do_aquire_global_lock(dev, state);
10165                 if (ret) {
10166                         DRM_DEBUG_DRIVER("do_aquire_global_lock() failed\n");
10167                         goto fail;
10168                 }
10169
10170                 ret = compute_mst_dsc_configs_for_state(state, dm_state->context, vars);
10171                 if (ret) {
10172                         DRM_DEBUG_DRIVER("compute_mst_dsc_configs_for_state() failed\n");
10173                         goto fail;
10174                 }
10175
10176                 ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context, vars);
10177                 if (ret) {
10178                         DRM_DEBUG_DRIVER("dm_update_mst_vcpi_slots_for_dsc() failed\n");
10179                         goto fail;
10180                 }
10181
10182                 /*
10183                  * Perform validation of MST topology in the state:
10184                  * We need to perform MST atomic check before calling
10185                  * dc_validate_global_state(), or there is a chance
10186                  * to get stuck in an infinite loop and hang eventually.
10187                  */
10188                 ret = drm_dp_mst_atomic_check(state);
10189                 if (ret) {
10190                         DRM_DEBUG_DRIVER("drm_dp_mst_atomic_check() failed\n");
10191                         goto fail;
10192                 }
10193                 status = dc_validate_global_state(dc, dm_state->context, true);
10194                 if (status != DC_OK) {
10195                         DRM_DEBUG_DRIVER("DC global validation failure: %s (%d)",
10196                                        dc_status_to_str(status), status);
10197                         ret = -EINVAL;
10198                         goto fail;
10199                 }
10200         } else {
10201                 /*
10202                  * The commit is a fast update. Fast updates shouldn't change
10203                  * the DC context, affect global validation, and can have their
10204                  * commit work done in parallel with other commits not touching
10205                  * the same resource. If we have a new DC context as part of
10206                  * the DM atomic state from validation we need to free it and
10207                  * retain the existing one instead.
10208                  *
10209                  * Furthermore, since the DM atomic state only contains the DC
10210                  * context and can safely be annulled, we can free the state
10211                  * and clear the associated private object now to free
10212                  * some memory and avoid a possible use-after-free later.
10213                  */
10214
10215                 for (i = 0; i < state->num_private_objs; i++) {
10216                         struct drm_private_obj *obj = state->private_objs[i].ptr;
10217
10218                         if (obj->funcs == adev->dm.atomic_obj.funcs) {
10219                                 int j = state->num_private_objs-1;
10220
10221                                 dm_atomic_destroy_state(obj,
10222                                                 state->private_objs[i].state);
10223
10224                                 /* If i is not at the end of the array then the
10225                                  * last element needs to be moved to where i was
10226                                  * before the array can safely be truncated.
10227                                  */
10228                                 if (i != j)
10229                                         state->private_objs[i] =
10230                                                 state->private_objs[j];
10231
10232                                 state->private_objs[j].ptr = NULL;
10233                                 state->private_objs[j].state = NULL;
10234                                 state->private_objs[j].old_state = NULL;
10235                                 state->private_objs[j].new_state = NULL;
10236
10237                                 state->num_private_objs = j;
10238                                 break;
10239                         }
10240                 }
10241         }
10242
10243         /* Store the overall update type for use later in atomic check. */
10244         for_each_new_crtc_in_state (state, crtc, new_crtc_state, i) {
10245                 struct dm_crtc_state *dm_new_crtc_state =
10246                         to_dm_crtc_state(new_crtc_state);
10247
10248                 dm_new_crtc_state->update_type = lock_and_validation_needed ?
10249                                                          UPDATE_TYPE_FULL :
10250                                                          UPDATE_TYPE_FAST;
10251         }
10252
10253         /* Must be success */
10254         WARN_ON(ret);
10255
10256         trace_amdgpu_dm_atomic_check_finish(state, ret);
10257
10258         return ret;
10259
10260 fail:
10261         if (ret == -EDEADLK)
10262                 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
10263         else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
10264                 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
10265         else
10266                 DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret);
10267
10268         trace_amdgpu_dm_atomic_check_finish(state, ret);
10269
10270         return ret;
10271 }
10272
10273 static bool is_dp_capable_without_timing_msa(struct dc *dc,
10274                                              struct amdgpu_dm_connector *amdgpu_dm_connector)
10275 {
10276         u8 dpcd_data;
10277         bool capable = false;
10278
10279         if (amdgpu_dm_connector->dc_link &&
10280                 dm_helpers_dp_read_dpcd(
10281                                 NULL,
10282                                 amdgpu_dm_connector->dc_link,
10283                                 DP_DOWN_STREAM_PORT_COUNT,
10284                                 &dpcd_data,
10285                                 sizeof(dpcd_data))) {
10286                 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
10287         }
10288
10289         return capable;
10290 }
10291
10292 static bool dm_edid_parser_send_cea(struct amdgpu_display_manager *dm,
10293                 unsigned int offset,
10294                 unsigned int total_length,
10295                 u8 *data,
10296                 unsigned int length,
10297                 struct amdgpu_hdmi_vsdb_info *vsdb)
10298 {
10299         bool res;
10300         union dmub_rb_cmd cmd;
10301         struct dmub_cmd_send_edid_cea *input;
10302         struct dmub_cmd_edid_cea_output *output;
10303
10304         if (length > DMUB_EDID_CEA_DATA_CHUNK_BYTES)
10305                 return false;
10306
10307         memset(&cmd, 0, sizeof(cmd));
10308
10309         input = &cmd.edid_cea.data.input;
10310
10311         cmd.edid_cea.header.type = DMUB_CMD__EDID_CEA;
10312         cmd.edid_cea.header.sub_type = 0;
10313         cmd.edid_cea.header.payload_bytes =
10314                 sizeof(cmd.edid_cea) - sizeof(cmd.edid_cea.header);
10315         input->offset = offset;
10316         input->length = length;
10317         input->cea_total_length = total_length;
10318         memcpy(input->payload, data, length);
10319
10320         res = dc_dmub_srv_cmd_with_reply_data(dm->dc->ctx->dmub_srv, &cmd);
10321         if (!res) {
10322                 DRM_ERROR("EDID CEA parser failed\n");
10323                 return false;
10324         }
10325
10326         output = &cmd.edid_cea.data.output;
10327
10328         if (output->type == DMUB_CMD__EDID_CEA_ACK) {
10329                 if (!output->ack.success) {
10330                         DRM_ERROR("EDID CEA ack failed at offset %d\n",
10331                                         output->ack.offset);
10332                 }
10333         } else if (output->type == DMUB_CMD__EDID_CEA_AMD_VSDB) {
10334                 if (!output->amd_vsdb.vsdb_found)
10335                         return false;
10336
10337                 vsdb->freesync_supported = output->amd_vsdb.freesync_supported;
10338                 vsdb->amd_vsdb_version = output->amd_vsdb.amd_vsdb_version;
10339                 vsdb->min_refresh_rate_hz = output->amd_vsdb.min_frame_rate;
10340                 vsdb->max_refresh_rate_hz = output->amd_vsdb.max_frame_rate;
10341         } else {
10342                 DRM_WARN("Unknown EDID CEA parser results\n");
10343                 return false;
10344         }
10345
10346         return true;
10347 }
10348
10349 static bool parse_edid_cea_dmcu(struct amdgpu_display_manager *dm,
10350                 u8 *edid_ext, int len,
10351                 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10352 {
10353         int i;
10354
10355         /* send extension block to DMCU for parsing */
10356         for (i = 0; i < len; i += 8) {
10357                 bool res;
10358                 int offset;
10359
10360                 /* send 8 bytes a time */
10361                 if (!dc_edid_parser_send_cea(dm->dc, i, len, &edid_ext[i], 8))
10362                         return false;
10363
10364                 if (i+8 == len) {
10365                         /* EDID block sent completed, expect result */
10366                         int version, min_rate, max_rate;
10367
10368                         res = dc_edid_parser_recv_amd_vsdb(dm->dc, &version, &min_rate, &max_rate);
10369                         if (res) {
10370                                 /* amd vsdb found */
10371                                 vsdb_info->freesync_supported = 1;
10372                                 vsdb_info->amd_vsdb_version = version;
10373                                 vsdb_info->min_refresh_rate_hz = min_rate;
10374                                 vsdb_info->max_refresh_rate_hz = max_rate;
10375                                 return true;
10376                         }
10377                         /* not amd vsdb */
10378                         return false;
10379                 }
10380
10381                 /* check for ack*/
10382                 res = dc_edid_parser_recv_cea_ack(dm->dc, &offset);
10383                 if (!res)
10384                         return false;
10385         }
10386
10387         return false;
10388 }
10389
10390 static bool parse_edid_cea_dmub(struct amdgpu_display_manager *dm,
10391                 u8 *edid_ext, int len,
10392                 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10393 {
10394         int i;
10395
10396         /* send extension block to DMCU for parsing */
10397         for (i = 0; i < len; i += 8) {
10398                 /* send 8 bytes a time */
10399                 if (!dm_edid_parser_send_cea(dm, i, len, &edid_ext[i], 8, vsdb_info))
10400                         return false;
10401         }
10402
10403         return vsdb_info->freesync_supported;
10404 }
10405
10406 static bool parse_edid_cea(struct amdgpu_dm_connector *aconnector,
10407                 u8 *edid_ext, int len,
10408                 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10409 {
10410         struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev);
10411         bool ret;
10412
10413         mutex_lock(&adev->dm.dc_lock);
10414         if (adev->dm.dmub_srv)
10415                 ret = parse_edid_cea_dmub(&adev->dm, edid_ext, len, vsdb_info);
10416         else
10417                 ret = parse_edid_cea_dmcu(&adev->dm, edid_ext, len, vsdb_info);
10418         mutex_unlock(&adev->dm.dc_lock);
10419         return ret;
10420 }
10421
10422 static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector,
10423                 struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info)
10424 {
10425         u8 *edid_ext = NULL;
10426         int i;
10427         bool valid_vsdb_found = false;
10428
10429         /*----- drm_find_cea_extension() -----*/
10430         /* No EDID or EDID extensions */
10431         if (edid == NULL || edid->extensions == 0)
10432                 return -ENODEV;
10433
10434         /* Find CEA extension */
10435         for (i = 0; i < edid->extensions; i++) {
10436                 edid_ext = (uint8_t *)edid + EDID_LENGTH * (i + 1);
10437                 if (edid_ext[0] == CEA_EXT)
10438                         break;
10439         }
10440
10441         if (i == edid->extensions)
10442                 return -ENODEV;
10443
10444         /*----- cea_db_offsets() -----*/
10445         if (edid_ext[0] != CEA_EXT)
10446                 return -ENODEV;
10447
10448         valid_vsdb_found = parse_edid_cea(aconnector, edid_ext, EDID_LENGTH, vsdb_info);
10449
10450         return valid_vsdb_found ? i : -ENODEV;
10451 }
10452
10453 /**
10454  * amdgpu_dm_update_freesync_caps - Update Freesync capabilities
10455  *
10456  * @connector: Connector to query.
10457  * @edid: EDID from monitor
10458  *
10459  * Amdgpu supports Freesync in DP and HDMI displays, and it is required to keep
10460  * track of some of the display information in the internal data struct used by
10461  * amdgpu_dm. This function checks which type of connector we need to set the
10462  * FreeSync parameters.
10463  */
10464 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
10465                                     struct edid *edid)
10466 {
10467         int i = 0;
10468         struct detailed_timing *timing;
10469         struct detailed_non_pixel *data;
10470         struct detailed_data_monitor_range *range;
10471         struct amdgpu_dm_connector *amdgpu_dm_connector =
10472                         to_amdgpu_dm_connector(connector);
10473         struct dm_connector_state *dm_con_state = NULL;
10474         struct dc_sink *sink;
10475
10476         struct drm_device *dev = connector->dev;
10477         struct amdgpu_device *adev = drm_to_adev(dev);
10478         struct amdgpu_hdmi_vsdb_info vsdb_info = {0};
10479         bool freesync_capable = false;
10480         enum adaptive_sync_type as_type = ADAPTIVE_SYNC_TYPE_NONE;
10481
10482         if (!connector->state) {
10483                 DRM_ERROR("%s - Connector has no state", __func__);
10484                 goto update;
10485         }
10486
10487         sink = amdgpu_dm_connector->dc_sink ?
10488                 amdgpu_dm_connector->dc_sink :
10489                 amdgpu_dm_connector->dc_em_sink;
10490
10491         if (!edid || !sink) {
10492                 dm_con_state = to_dm_connector_state(connector->state);
10493
10494                 amdgpu_dm_connector->min_vfreq = 0;
10495                 amdgpu_dm_connector->max_vfreq = 0;
10496                 amdgpu_dm_connector->pixel_clock_mhz = 0;
10497                 connector->display_info.monitor_range.min_vfreq = 0;
10498                 connector->display_info.monitor_range.max_vfreq = 0;
10499                 freesync_capable = false;
10500
10501                 goto update;
10502         }
10503
10504         dm_con_state = to_dm_connector_state(connector->state);
10505
10506         if (!adev->dm.freesync_module)
10507                 goto update;
10508
10509         if (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
10510                 || sink->sink_signal == SIGNAL_TYPE_EDP) {
10511                 bool edid_check_required = false;
10512
10513                 if (edid) {
10514                         edid_check_required = is_dp_capable_without_timing_msa(
10515                                                 adev->dm.dc,
10516                                                 amdgpu_dm_connector);
10517                 }
10518
10519                 if (edid_check_required == true && (edid->version > 1 ||
10520                    (edid->version == 1 && edid->revision > 1))) {
10521                         for (i = 0; i < 4; i++) {
10522
10523                                 timing  = &edid->detailed_timings[i];
10524                                 data    = &timing->data.other_data;
10525                                 range   = &data->data.range;
10526                                 /*
10527                                  * Check if monitor has continuous frequency mode
10528                                  */
10529                                 if (data->type != EDID_DETAIL_MONITOR_RANGE)
10530                                         continue;
10531                                 /*
10532                                  * Check for flag range limits only. If flag == 1 then
10533                                  * no additional timing information provided.
10534                                  * Default GTF, GTF Secondary curve and CVT are not
10535                                  * supported
10536                                  */
10537                                 if (range->flags != 1)
10538                                         continue;
10539
10540                                 amdgpu_dm_connector->min_vfreq = range->min_vfreq;
10541                                 amdgpu_dm_connector->max_vfreq = range->max_vfreq;
10542                                 amdgpu_dm_connector->pixel_clock_mhz =
10543                                         range->pixel_clock_mhz * 10;
10544
10545                                 connector->display_info.monitor_range.min_vfreq = range->min_vfreq;
10546                                 connector->display_info.monitor_range.max_vfreq = range->max_vfreq;
10547
10548                                 break;
10549                         }
10550
10551                         if (amdgpu_dm_connector->max_vfreq -
10552                             amdgpu_dm_connector->min_vfreq > 10) {
10553
10554                                 freesync_capable = true;
10555                         }
10556                 }
10557         } else if (edid && sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) {
10558                 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
10559                 if (i >= 0 && vsdb_info.freesync_supported) {
10560                         timing  = &edid->detailed_timings[i];
10561                         data    = &timing->data.other_data;
10562
10563                         amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
10564                         amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
10565                         if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
10566                                 freesync_capable = true;
10567
10568                         connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz;
10569                         connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz;
10570                 }
10571         }
10572
10573         as_type = dm_get_adaptive_sync_support_type(amdgpu_dm_connector->dc_link);
10574
10575         if (as_type == FREESYNC_TYPE_PCON_IN_WHITELIST) {
10576                 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
10577                 if (i >= 0 && vsdb_info.freesync_supported && vsdb_info.amd_vsdb_version > 0) {
10578
10579                         amdgpu_dm_connector->pack_sdp_v1_3 = true;
10580                         amdgpu_dm_connector->as_type = as_type;
10581                         amdgpu_dm_connector->vsdb_info = vsdb_info;
10582
10583                         amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
10584                         amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
10585                         if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
10586                                 freesync_capable = true;
10587
10588                         connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz;
10589                         connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz;
10590                 }
10591         }
10592
10593 update:
10594         if (dm_con_state)
10595                 dm_con_state->freesync_capable = freesync_capable;
10596
10597         if (connector->vrr_capable_property)
10598                 drm_connector_set_vrr_capable_property(connector,
10599                                                        freesync_capable);
10600 }
10601
10602 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev)
10603 {
10604         struct amdgpu_device *adev = drm_to_adev(dev);
10605         struct dc *dc = adev->dm.dc;
10606         int i;
10607
10608         mutex_lock(&adev->dm.dc_lock);
10609         if (dc->current_state) {
10610                 for (i = 0; i < dc->current_state->stream_count; ++i)
10611                         dc->current_state->streams[i]
10612                                 ->triggered_crtc_reset.enabled =
10613                                 adev->dm.force_timing_sync;
10614
10615                 dm_enable_per_frame_crtc_master_sync(dc->current_state);
10616                 dc_trigger_sync(dc, dc->current_state);
10617         }
10618         mutex_unlock(&adev->dm.dc_lock);
10619 }
10620
10621 void dm_write_reg_func(const struct dc_context *ctx, uint32_t address,
10622                        u32 value, const char *func_name)
10623 {
10624 #ifdef DM_CHECK_ADDR_0
10625         if (address == 0) {
10626                 DC_ERR("invalid register write. address = 0");
10627                 return;
10628         }
10629 #endif
10630         cgs_write_register(ctx->cgs_device, address, value);
10631         trace_amdgpu_dc_wreg(&ctx->perf_trace->write_count, address, value);
10632 }
10633
10634 uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address,
10635                           const char *func_name)
10636 {
10637         u32 value;
10638 #ifdef DM_CHECK_ADDR_0
10639         if (address == 0) {
10640                 DC_ERR("invalid register read; address = 0\n");
10641                 return 0;
10642         }
10643 #endif
10644
10645         if (ctx->dmub_srv &&
10646             ctx->dmub_srv->reg_helper_offload.gather_in_progress &&
10647             !ctx->dmub_srv->reg_helper_offload.should_burst_write) {
10648                 ASSERT(false);
10649                 return 0;
10650         }
10651
10652         value = cgs_read_register(ctx->cgs_device, address);
10653
10654         trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address, value);
10655
10656         return value;
10657 }
10658
10659 int amdgpu_dm_process_dmub_aux_transfer_sync(
10660                 struct dc_context *ctx,
10661                 unsigned int link_index,
10662                 struct aux_payload *payload,
10663                 enum aux_return_code_type *operation_result)
10664 {
10665         struct amdgpu_device *adev = ctx->driver_context;
10666         struct dmub_notification *p_notify = adev->dm.dmub_notify;
10667         int ret = -1;
10668
10669         mutex_lock(&adev->dm.dpia_aux_lock);
10670         if (!dc_process_dmub_aux_transfer_async(ctx->dc, link_index, payload)) {
10671                 *operation_result = AUX_RET_ERROR_ENGINE_ACQUIRE;
10672                 goto out;
10673         }
10674
10675         if (!wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) {
10676                 DRM_ERROR("wait_for_completion_timeout timeout!");
10677                 *operation_result = AUX_RET_ERROR_TIMEOUT;
10678                 goto out;
10679         }
10680
10681         if (p_notify->result != AUX_RET_SUCCESS) {
10682                 /*
10683                  * Transient states before tunneling is enabled could
10684                  * lead to this error. We can ignore this for now.
10685                  */
10686                 if (p_notify->result != AUX_RET_ERROR_PROTOCOL_ERROR) {
10687                         DRM_WARN("DPIA AUX failed on 0x%x(%d), error %d\n",
10688                                         payload->address, payload->length,
10689                                         p_notify->result);
10690                 }
10691                 *operation_result = AUX_RET_ERROR_INVALID_REPLY;
10692                 goto out;
10693         }
10694
10695
10696         payload->reply[0] = adev->dm.dmub_notify->aux_reply.command;
10697         if (!payload->write && p_notify->aux_reply.length &&
10698                         (payload->reply[0] == AUX_TRANSACTION_REPLY_AUX_ACK)) {
10699
10700                 if (payload->length != p_notify->aux_reply.length) {
10701                         DRM_WARN("invalid read length %d from DPIA AUX 0x%x(%d)!\n",
10702                                 p_notify->aux_reply.length,
10703                                         payload->address, payload->length);
10704                         *operation_result = AUX_RET_ERROR_INVALID_REPLY;
10705                         goto out;
10706                 }
10707
10708                 memcpy(payload->data, p_notify->aux_reply.data,
10709                                 p_notify->aux_reply.length);
10710         }
10711
10712         /* success */
10713         ret = p_notify->aux_reply.length;
10714         *operation_result = p_notify->result;
10715 out:
10716         reinit_completion(&adev->dm.dmub_aux_transfer_done);
10717         mutex_unlock(&adev->dm.dpia_aux_lock);
10718         return ret;
10719 }
10720
10721 int amdgpu_dm_process_dmub_set_config_sync(
10722                 struct dc_context *ctx,
10723                 unsigned int link_index,
10724                 struct set_config_cmd_payload *payload,
10725                 enum set_config_status *operation_result)
10726 {
10727         struct amdgpu_device *adev = ctx->driver_context;
10728         bool is_cmd_complete;
10729         int ret;
10730
10731         mutex_lock(&adev->dm.dpia_aux_lock);
10732         is_cmd_complete = dc_process_dmub_set_config_async(ctx->dc,
10733                         link_index, payload, adev->dm.dmub_notify);
10734
10735         if (is_cmd_complete || wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) {
10736                 ret = 0;
10737                 *operation_result = adev->dm.dmub_notify->sc_status;
10738         } else {
10739                 DRM_ERROR("wait_for_completion_timeout timeout!");
10740                 ret = -1;
10741                 *operation_result = SET_CONFIG_UNKNOWN_ERROR;
10742         }
10743
10744         if (!is_cmd_complete)
10745                 reinit_completion(&adev->dm.dmub_aux_transfer_done);
10746         mutex_unlock(&adev->dm.dpia_aux_lock);
10747         return ret;
10748 }
10749
10750 /*
10751  * Check whether seamless boot is supported.
10752  *
10753  * So far we only support seamless boot on CHIP_VANGOGH.
10754  * If everything goes well, we may consider expanding
10755  * seamless boot to other ASICs.
10756  */
10757 bool check_seamless_boot_capability(struct amdgpu_device *adev)
10758 {
10759         switch (adev->ip_versions[DCE_HWIP][0]) {
10760         case IP_VERSION(3, 0, 1):
10761                 if (!adev->mman.keep_stolen_vga_memory)
10762                         return true;
10763                 break;
10764         default:
10765                 break;
10766         }
10767
10768         return false;
10769 }