2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 /* The caprices of the preprocessor require that this be declared right here */
27 #define CREATE_TRACE_POINTS
29 #include "dm_services_types.h"
31 #include "link_enc_cfg.h"
32 #include "dc/inc/core_types.h"
33 #include "dal_asic_id.h"
34 #include "dmub/dmub_srv.h"
35 #include "dc/inc/hw/dmcu.h"
36 #include "dc/inc/hw/abm.h"
37 #include "dc/dc_dmub_srv.h"
38 #include "dc/dc_edid_parser.h"
39 #include "dc/dc_stat.h"
40 #include "amdgpu_dm_trace.h"
41 #include "dpcd_defs.h"
42 #include "link/protocols/link_dpcd.h"
43 #include "link_service_types.h"
44 #include "link/protocols/link_dp_capability.h"
45 #include "link/protocols/link_ddc.h"
49 #include "amdgpu_display.h"
50 #include "amdgpu_ucode.h"
52 #include "amdgpu_dm.h"
53 #include "amdgpu_dm_plane.h"
54 #include "amdgpu_dm_crtc.h"
55 #include "amdgpu_dm_hdcp.h"
56 #include <drm/display/drm_hdcp_helper.h>
57 #include "amdgpu_pm.h"
58 #include "amdgpu_atombios.h"
60 #include "amd_shared.h"
61 #include "amdgpu_dm_irq.h"
62 #include "dm_helpers.h"
63 #include "amdgpu_dm_mst_types.h"
64 #if defined(CONFIG_DEBUG_FS)
65 #include "amdgpu_dm_debugfs.h"
67 #include "amdgpu_dm_psr.h"
69 #include "ivsrcid/ivsrcid_vislands30.h"
71 #include <linux/backlight.h>
72 #include <linux/module.h>
73 #include <linux/moduleparam.h>
74 #include <linux/types.h>
75 #include <linux/pm_runtime.h>
76 #include <linux/pci.h>
77 #include <linux/firmware.h>
78 #include <linux/component.h>
79 #include <linux/dmi.h>
81 #include <drm/display/drm_dp_mst_helper.h>
82 #include <drm/display/drm_hdmi_helper.h>
83 #include <drm/drm_atomic.h>
84 #include <drm/drm_atomic_uapi.h>
85 #include <drm/drm_atomic_helper.h>
86 #include <drm/drm_blend.h>
87 #include <drm/drm_fourcc.h>
88 #include <drm/drm_edid.h>
89 #include <drm/drm_vblank.h>
90 #include <drm/drm_audio_component.h>
91 #include <drm/drm_gem_atomic_helper.h>
92 #include <drm/drm_plane_helper.h>
94 #include <acpi/video.h>
96 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
98 #include "dcn/dcn_1_0_offset.h"
99 #include "dcn/dcn_1_0_sh_mask.h"
100 #include "soc15_hw_ip.h"
101 #include "soc15_common.h"
102 #include "vega10_ip_offset.h"
104 #include "gc/gc_11_0_0_offset.h"
105 #include "gc/gc_11_0_0_sh_mask.h"
107 #include "modules/inc/mod_freesync.h"
108 #include "modules/power/power_helpers.h"
110 #define FIRMWARE_RENOIR_DMUB "amdgpu/renoir_dmcub.bin"
111 MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB);
112 #define FIRMWARE_SIENNA_CICHLID_DMUB "amdgpu/sienna_cichlid_dmcub.bin"
113 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID_DMUB);
114 #define FIRMWARE_NAVY_FLOUNDER_DMUB "amdgpu/navy_flounder_dmcub.bin"
115 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER_DMUB);
116 #define FIRMWARE_GREEN_SARDINE_DMUB "amdgpu/green_sardine_dmcub.bin"
117 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE_DMUB);
118 #define FIRMWARE_VANGOGH_DMUB "amdgpu/vangogh_dmcub.bin"
119 MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB);
120 #define FIRMWARE_DIMGREY_CAVEFISH_DMUB "amdgpu/dimgrey_cavefish_dmcub.bin"
121 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH_DMUB);
122 #define FIRMWARE_BEIGE_GOBY_DMUB "amdgpu/beige_goby_dmcub.bin"
123 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY_DMUB);
124 #define FIRMWARE_YELLOW_CARP_DMUB "amdgpu/yellow_carp_dmcub.bin"
125 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP_DMUB);
126 #define FIRMWARE_DCN_314_DMUB "amdgpu/dcn_3_1_4_dmcub.bin"
127 MODULE_FIRMWARE(FIRMWARE_DCN_314_DMUB);
128 #define FIRMWARE_DCN_315_DMUB "amdgpu/dcn_3_1_5_dmcub.bin"
129 MODULE_FIRMWARE(FIRMWARE_DCN_315_DMUB);
130 #define FIRMWARE_DCN316_DMUB "amdgpu/dcn_3_1_6_dmcub.bin"
131 MODULE_FIRMWARE(FIRMWARE_DCN316_DMUB);
133 #define FIRMWARE_DCN_V3_2_0_DMCUB "amdgpu/dcn_3_2_0_dmcub.bin"
134 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_0_DMCUB);
135 #define FIRMWARE_DCN_V3_2_1_DMCUB "amdgpu/dcn_3_2_1_dmcub.bin"
136 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_1_DMCUB);
138 #define FIRMWARE_RAVEN_DMCU "amdgpu/raven_dmcu.bin"
139 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
141 #define FIRMWARE_NAVI12_DMCU "amdgpu/navi12_dmcu.bin"
142 MODULE_FIRMWARE(FIRMWARE_NAVI12_DMCU);
144 /* Number of bytes in PSP header for firmware. */
145 #define PSP_HEADER_BYTES 0x100
147 /* Number of bytes in PSP footer for firmware. */
148 #define PSP_FOOTER_BYTES 0x100
153 * The AMDgpu display manager, **amdgpu_dm** (or even simpler,
154 * **dm**) sits between DRM and DC. It acts as a liaison, converting DRM
155 * requests into DC requests, and DC responses into DRM responses.
157 * The root control structure is &struct amdgpu_display_manager.
160 /* basic init/fini API */
161 static int amdgpu_dm_init(struct amdgpu_device *adev);
162 static void amdgpu_dm_fini(struct amdgpu_device *adev);
163 static bool is_freesync_video_mode(const struct drm_display_mode *mode, struct amdgpu_dm_connector *aconnector);
165 static enum drm_mode_subconnector get_subconnector_type(struct dc_link *link)
167 switch (link->dpcd_caps.dongle_type) {
168 case DISPLAY_DONGLE_NONE:
169 return DRM_MODE_SUBCONNECTOR_Native;
170 case DISPLAY_DONGLE_DP_VGA_CONVERTER:
171 return DRM_MODE_SUBCONNECTOR_VGA;
172 case DISPLAY_DONGLE_DP_DVI_CONVERTER:
173 case DISPLAY_DONGLE_DP_DVI_DONGLE:
174 return DRM_MODE_SUBCONNECTOR_DVID;
175 case DISPLAY_DONGLE_DP_HDMI_CONVERTER:
176 case DISPLAY_DONGLE_DP_HDMI_DONGLE:
177 return DRM_MODE_SUBCONNECTOR_HDMIA;
178 case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
180 return DRM_MODE_SUBCONNECTOR_Unknown;
184 static void update_subconnector_property(struct amdgpu_dm_connector *aconnector)
186 struct dc_link *link = aconnector->dc_link;
187 struct drm_connector *connector = &aconnector->base;
188 enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
190 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
193 if (aconnector->dc_sink)
194 subconnector = get_subconnector_type(link);
196 drm_object_property_set_value(&connector->base,
197 connector->dev->mode_config.dp_subconnector_property,
202 * initializes drm_device display related structures, based on the information
203 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
204 * drm_encoder, drm_mode_config
206 * Returns 0 on success
208 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
209 /* removes and deallocates the drm structures, created by the above function */
210 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
212 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
213 struct amdgpu_dm_connector *amdgpu_dm_connector,
215 struct amdgpu_encoder *amdgpu_encoder);
216 static int amdgpu_dm_encoder_init(struct drm_device *dev,
217 struct amdgpu_encoder *aencoder,
218 uint32_t link_index);
220 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
222 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
224 static int amdgpu_dm_atomic_check(struct drm_device *dev,
225 struct drm_atomic_state *state);
227 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector);
228 static void handle_hpd_rx_irq(void *param);
231 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
232 struct drm_crtc_state *new_crtc_state);
234 * dm_vblank_get_counter
237 * Get counter for number of vertical blanks
240 * struct amdgpu_device *adev - [in] desired amdgpu device
241 * int disp_idx - [in] which CRTC to get the counter from
244 * Counter for vertical blanks
246 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
248 if (crtc >= adev->mode_info.num_crtc)
251 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
253 if (acrtc->dm_irq_params.stream == NULL) {
254 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
259 return dc_stream_get_vblank_counter(acrtc->dm_irq_params.stream);
263 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
264 u32 *vbl, u32 *position)
266 u32 v_blank_start, v_blank_end, h_position, v_position;
268 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
271 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
273 if (acrtc->dm_irq_params.stream == NULL) {
274 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
280 * TODO rework base driver to use values directly.
281 * for now parse it back into reg-format
283 dc_stream_get_scanoutpos(acrtc->dm_irq_params.stream,
289 *position = v_position | (h_position << 16);
290 *vbl = v_blank_start | (v_blank_end << 16);
296 static bool dm_is_idle(void *handle)
302 static int dm_wait_for_idle(void *handle)
308 static bool dm_check_soft_reset(void *handle)
313 static int dm_soft_reset(void *handle)
319 static struct amdgpu_crtc *
320 get_crtc_by_otg_inst(struct amdgpu_device *adev,
323 struct drm_device *dev = adev_to_drm(adev);
324 struct drm_crtc *crtc;
325 struct amdgpu_crtc *amdgpu_crtc;
327 if (WARN_ON(otg_inst == -1))
328 return adev->mode_info.crtcs[0];
330 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
331 amdgpu_crtc = to_amdgpu_crtc(crtc);
333 if (amdgpu_crtc->otg_inst == otg_inst)
340 static inline bool is_dc_timing_adjust_needed(struct dm_crtc_state *old_state,
341 struct dm_crtc_state *new_state)
343 if (new_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)
345 else if (amdgpu_dm_crtc_vrr_active(old_state) != amdgpu_dm_crtc_vrr_active(new_state))
351 static inline void reverse_planes_order(struct dc_surface_update *array_of_surface_update,
356 for (i = 0, j = planes_count - 1; i < j; i++, j--)
357 swap(array_of_surface_update[i], array_of_surface_update[j]);
361 * update_planes_and_stream_adapter() - Send planes to be updated in DC
363 * DC has a generic way to update planes and stream via
364 * dc_update_planes_and_stream function; however, DM might need some
365 * adjustments and preparation before calling it. This function is a wrapper
366 * for the dc_update_planes_and_stream that does any required configuration
367 * before passing control to DC.
369 static inline bool update_planes_and_stream_adapter(struct dc *dc,
372 struct dc_stream_state *stream,
373 struct dc_stream_update *stream_update,
374 struct dc_surface_update *array_of_surface_update)
376 reverse_planes_order(array_of_surface_update, planes_count);
379 * Previous frame finished and HW is ready for optimization.
381 if (update_type == UPDATE_TYPE_FAST)
382 dc_post_update_surfaces_to_stream(dc);
384 return dc_update_planes_and_stream(dc,
385 array_of_surface_update,
392 * dm_pflip_high_irq() - Handle pageflip interrupt
393 * @interrupt_params: ignored
395 * Handles the pageflip interrupt by notifying all interested parties
396 * that the pageflip has been completed.
398 static void dm_pflip_high_irq(void *interrupt_params)
400 struct amdgpu_crtc *amdgpu_crtc;
401 struct common_irq_params *irq_params = interrupt_params;
402 struct amdgpu_device *adev = irq_params->adev;
404 struct drm_pending_vblank_event *e;
405 u32 vpos, hpos, v_blank_start, v_blank_end;
408 amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
410 /* IRQ could occur when in initial stage */
411 /* TODO work and BO cleanup */
412 if (amdgpu_crtc == NULL) {
413 DC_LOG_PFLIP("CRTC is null, returning.\n");
417 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
419 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
420 DC_LOG_PFLIP("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
421 amdgpu_crtc->pflip_status,
422 AMDGPU_FLIP_SUBMITTED,
423 amdgpu_crtc->crtc_id,
425 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
429 /* page flip completed. */
430 e = amdgpu_crtc->event;
431 amdgpu_crtc->event = NULL;
435 vrr_active = amdgpu_dm_crtc_vrr_active_irq(amdgpu_crtc);
437 /* Fixed refresh rate, or VRR scanout position outside front-porch? */
439 !dc_stream_get_scanoutpos(amdgpu_crtc->dm_irq_params.stream, &v_blank_start,
440 &v_blank_end, &hpos, &vpos) ||
441 (vpos < v_blank_start)) {
442 /* Update to correct count and vblank timestamp if racing with
443 * vblank irq. This also updates to the correct vblank timestamp
444 * even in VRR mode, as scanout is past the front-porch atm.
446 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
448 /* Wake up userspace by sending the pageflip event with proper
449 * count and timestamp of vblank of flip completion.
452 drm_crtc_send_vblank_event(&amdgpu_crtc->base, e);
454 /* Event sent, so done with vblank for this flip */
455 drm_crtc_vblank_put(&amdgpu_crtc->base);
458 /* VRR active and inside front-porch: vblank count and
459 * timestamp for pageflip event will only be up to date after
460 * drm_crtc_handle_vblank() has been executed from late vblank
461 * irq handler after start of back-porch (vline 0). We queue the
462 * pageflip event for send-out by drm_crtc_handle_vblank() with
463 * updated timestamp and count, once it runs after us.
465 * We need to open-code this instead of using the helper
466 * drm_crtc_arm_vblank_event(), as that helper would
467 * call drm_crtc_accurate_vblank_count(), which we must
468 * not call in VRR mode while we are in front-porch!
471 /* sequence will be replaced by real count during send-out. */
472 e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base);
473 e->pipe = amdgpu_crtc->crtc_id;
475 list_add_tail(&e->base.link, &adev_to_drm(adev)->vblank_event_list);
479 /* Keep track of vblank of this flip for flip throttling. We use the
480 * cooked hw counter, as that one incremented at start of this vblank
481 * of pageflip completion, so last_flip_vblank is the forbidden count
482 * for queueing new pageflips if vsync + VRR is enabled.
484 amdgpu_crtc->dm_irq_params.last_flip_vblank =
485 amdgpu_get_vblank_counter_kms(&amdgpu_crtc->base);
487 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
488 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
490 DC_LOG_PFLIP("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n",
491 amdgpu_crtc->crtc_id, amdgpu_crtc,
492 vrr_active, (int) !e);
495 static void dm_vupdate_high_irq(void *interrupt_params)
497 struct common_irq_params *irq_params = interrupt_params;
498 struct amdgpu_device *adev = irq_params->adev;
499 struct amdgpu_crtc *acrtc;
500 struct drm_device *drm_dev;
501 struct drm_vblank_crtc *vblank;
502 ktime_t frame_duration_ns, previous_timestamp;
506 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE);
509 vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc);
510 drm_dev = acrtc->base.dev;
511 vblank = &drm_dev->vblank[acrtc->base.index];
512 previous_timestamp = atomic64_read(&irq_params->previous_timestamp);
513 frame_duration_ns = vblank->time - previous_timestamp;
515 if (frame_duration_ns > 0) {
516 trace_amdgpu_refresh_rate_track(acrtc->base.index,
518 ktime_divns(NSEC_PER_SEC, frame_duration_ns));
519 atomic64_set(&irq_params->previous_timestamp, vblank->time);
522 DC_LOG_VBLANK("crtc:%d, vupdate-vrr:%d\n",
526 /* Core vblank handling is done here after end of front-porch in
527 * vrr mode, as vblank timestamping will give valid results
528 * while now done after front-porch. This will also deliver
529 * page-flip completion events that have been queued to us
530 * if a pageflip happened inside front-porch.
533 amdgpu_dm_crtc_handle_vblank(acrtc);
535 /* BTR processing for pre-DCE12 ASICs */
536 if (acrtc->dm_irq_params.stream &&
537 adev->family < AMDGPU_FAMILY_AI) {
538 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
539 mod_freesync_handle_v_update(
540 adev->dm.freesync_module,
541 acrtc->dm_irq_params.stream,
542 &acrtc->dm_irq_params.vrr_params);
544 dc_stream_adjust_vmin_vmax(
546 acrtc->dm_irq_params.stream,
547 &acrtc->dm_irq_params.vrr_params.adjust);
548 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
555 * dm_crtc_high_irq() - Handles CRTC interrupt
556 * @interrupt_params: used for determining the CRTC instance
558 * Handles the CRTC/VSYNC interrupt by notfying DRM's VBLANK
561 static void dm_crtc_high_irq(void *interrupt_params)
563 struct common_irq_params *irq_params = interrupt_params;
564 struct amdgpu_device *adev = irq_params->adev;
565 struct amdgpu_crtc *acrtc;
569 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
573 vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc);
575 DC_LOG_VBLANK("crtc:%d, vupdate-vrr:%d, planes:%d\n", acrtc->crtc_id,
576 vrr_active, acrtc->dm_irq_params.active_planes);
579 * Core vblank handling at start of front-porch is only possible
580 * in non-vrr mode, as only there vblank timestamping will give
581 * valid results while done in front-porch. Otherwise defer it
582 * to dm_vupdate_high_irq after end of front-porch.
585 amdgpu_dm_crtc_handle_vblank(acrtc);
588 * Following stuff must happen at start of vblank, for crc
589 * computation and below-the-range btr support in vrr mode.
591 amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
593 /* BTR updates need to happen before VUPDATE on Vega and above. */
594 if (adev->family < AMDGPU_FAMILY_AI)
597 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
599 if (acrtc->dm_irq_params.stream &&
600 acrtc->dm_irq_params.vrr_params.supported &&
601 acrtc->dm_irq_params.freesync_config.state ==
602 VRR_STATE_ACTIVE_VARIABLE) {
603 mod_freesync_handle_v_update(adev->dm.freesync_module,
604 acrtc->dm_irq_params.stream,
605 &acrtc->dm_irq_params.vrr_params);
607 dc_stream_adjust_vmin_vmax(adev->dm.dc, acrtc->dm_irq_params.stream,
608 &acrtc->dm_irq_params.vrr_params.adjust);
612 * If there aren't any active_planes then DCH HUBP may be clock-gated.
613 * In that case, pageflip completion interrupts won't fire and pageflip
614 * completion events won't get delivered. Prevent this by sending
615 * pending pageflip events from here if a flip is still pending.
617 * If any planes are enabled, use dm_pflip_high_irq() instead, to
618 * avoid race conditions between flip programming and completion,
619 * which could cause too early flip completion events.
621 if (adev->family >= AMDGPU_FAMILY_RV &&
622 acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED &&
623 acrtc->dm_irq_params.active_planes == 0) {
625 drm_crtc_send_vblank_event(&acrtc->base, acrtc->event);
627 drm_crtc_vblank_put(&acrtc->base);
629 acrtc->pflip_status = AMDGPU_FLIP_NONE;
632 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
635 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
637 * dm_dcn_vertical_interrupt0_high_irq() - Handles OTG Vertical interrupt0 for
638 * DCN generation ASICs
639 * @interrupt_params: interrupt parameters
641 * Used to set crc window/read out crc value at vertical line 0 position
643 static void dm_dcn_vertical_interrupt0_high_irq(void *interrupt_params)
645 struct common_irq_params *irq_params = interrupt_params;
646 struct amdgpu_device *adev = irq_params->adev;
647 struct amdgpu_crtc *acrtc;
649 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VLINE0);
654 amdgpu_dm_crtc_handle_crc_window_irq(&acrtc->base);
656 #endif /* CONFIG_DRM_AMD_SECURE_DISPLAY */
659 * dmub_aux_setconfig_callback - Callback for AUX or SET_CONFIG command.
660 * @adev: amdgpu_device pointer
661 * @notify: dmub notification structure
663 * Dmub AUX or SET_CONFIG command completion processing callback
664 * Copies dmub notification to DM which is to be read by AUX command.
665 * issuing thread and also signals the event to wake up the thread.
667 static void dmub_aux_setconfig_callback(struct amdgpu_device *adev,
668 struct dmub_notification *notify)
670 if (adev->dm.dmub_notify)
671 memcpy(adev->dm.dmub_notify, notify, sizeof(struct dmub_notification));
672 if (notify->type == DMUB_NOTIFICATION_AUX_REPLY)
673 complete(&adev->dm.dmub_aux_transfer_done);
677 * dmub_hpd_callback - DMUB HPD interrupt processing callback.
678 * @adev: amdgpu_device pointer
679 * @notify: dmub notification structure
681 * Dmub Hpd interrupt processing callback. Gets displayindex through the
682 * ink index and calls helper to do the processing.
684 static void dmub_hpd_callback(struct amdgpu_device *adev,
685 struct dmub_notification *notify)
687 struct amdgpu_dm_connector *aconnector;
688 struct amdgpu_dm_connector *hpd_aconnector = NULL;
689 struct drm_connector *connector;
690 struct drm_connector_list_iter iter;
691 struct dc_link *link;
693 struct drm_device *dev;
698 if (notify == NULL) {
699 DRM_ERROR("DMUB HPD callback notification was NULL");
703 if (notify->link_index > adev->dm.dc->link_count) {
704 DRM_ERROR("DMUB HPD index (%u)is abnormal", notify->link_index);
708 link_index = notify->link_index;
709 link = adev->dm.dc->links[link_index];
712 drm_connector_list_iter_begin(dev, &iter);
713 drm_for_each_connector_iter(connector, &iter) {
714 aconnector = to_amdgpu_dm_connector(connector);
715 if (link && aconnector->dc_link == link) {
716 if (notify->type == DMUB_NOTIFICATION_HPD)
717 DRM_INFO("DMUB HPD callback: link_index=%u\n", link_index);
718 else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ)
719 DRM_INFO("DMUB HPD IRQ callback: link_index=%u\n", link_index);
721 DRM_WARN("DMUB Unknown HPD callback type %d, link_index=%u\n",
722 notify->type, link_index);
724 hpd_aconnector = aconnector;
728 drm_connector_list_iter_end(&iter);
730 if (hpd_aconnector) {
731 if (notify->type == DMUB_NOTIFICATION_HPD)
732 handle_hpd_irq_helper(hpd_aconnector);
733 else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ)
734 handle_hpd_rx_irq(hpd_aconnector);
739 * register_dmub_notify_callback - Sets callback for DMUB notify
740 * @adev: amdgpu_device pointer
741 * @type: Type of dmub notification
742 * @callback: Dmub interrupt callback function
743 * @dmub_int_thread_offload: offload indicator
745 * API to register a dmub callback handler for a dmub notification
746 * Also sets indicator whether callback processing to be offloaded.
747 * to dmub interrupt handling thread
748 * Return: true if successfully registered, false if there is existing registration
750 static bool register_dmub_notify_callback(struct amdgpu_device *adev,
751 enum dmub_notification_type type,
752 dmub_notify_interrupt_callback_t callback,
753 bool dmub_int_thread_offload)
755 if (callback != NULL && type < ARRAY_SIZE(adev->dm.dmub_thread_offload)) {
756 adev->dm.dmub_callback[type] = callback;
757 adev->dm.dmub_thread_offload[type] = dmub_int_thread_offload;
764 static void dm_handle_hpd_work(struct work_struct *work)
766 struct dmub_hpd_work *dmub_hpd_wrk;
768 dmub_hpd_wrk = container_of(work, struct dmub_hpd_work, handle_hpd_work);
770 if (!dmub_hpd_wrk->dmub_notify) {
771 DRM_ERROR("dmub_hpd_wrk dmub_notify is NULL");
775 if (dmub_hpd_wrk->dmub_notify->type < ARRAY_SIZE(dmub_hpd_wrk->adev->dm.dmub_callback)) {
776 dmub_hpd_wrk->adev->dm.dmub_callback[dmub_hpd_wrk->dmub_notify->type](dmub_hpd_wrk->adev,
777 dmub_hpd_wrk->dmub_notify);
780 kfree(dmub_hpd_wrk->dmub_notify);
785 #define DMUB_TRACE_MAX_READ 64
787 * dm_dmub_outbox1_low_irq() - Handles Outbox interrupt
788 * @interrupt_params: used for determining the Outbox instance
790 * Handles the Outbox Interrupt
793 static void dm_dmub_outbox1_low_irq(void *interrupt_params)
795 struct dmub_notification notify;
796 struct common_irq_params *irq_params = interrupt_params;
797 struct amdgpu_device *adev = irq_params->adev;
798 struct amdgpu_display_manager *dm = &adev->dm;
799 struct dmcub_trace_buf_entry entry = { 0 };
801 struct dmub_hpd_work *dmub_hpd_wrk;
802 struct dc_link *plink = NULL;
804 if (dc_enable_dmub_notifications(adev->dm.dc) &&
805 irq_params->irq_src == DC_IRQ_SOURCE_DMCUB_OUTBOX) {
808 dc_stat_get_dmub_notification(adev->dm.dc, ¬ify);
809 if (notify.type >= ARRAY_SIZE(dm->dmub_thread_offload)) {
810 DRM_ERROR("DM: notify type %d invalid!", notify.type);
813 if (!dm->dmub_callback[notify.type]) {
814 DRM_DEBUG_DRIVER("DMUB notification skipped, no handler: type=%d\n", notify.type);
817 if (dm->dmub_thread_offload[notify.type] == true) {
818 dmub_hpd_wrk = kzalloc(sizeof(*dmub_hpd_wrk), GFP_ATOMIC);
820 DRM_ERROR("Failed to allocate dmub_hpd_wrk");
823 dmub_hpd_wrk->dmub_notify = kzalloc(sizeof(struct dmub_notification), GFP_ATOMIC);
824 if (!dmub_hpd_wrk->dmub_notify) {
826 DRM_ERROR("Failed to allocate dmub_hpd_wrk->dmub_notify");
829 INIT_WORK(&dmub_hpd_wrk->handle_hpd_work, dm_handle_hpd_work);
830 if (dmub_hpd_wrk->dmub_notify)
831 memcpy(dmub_hpd_wrk->dmub_notify, ¬ify, sizeof(struct dmub_notification));
832 dmub_hpd_wrk->adev = adev;
833 if (notify.type == DMUB_NOTIFICATION_HPD) {
834 plink = adev->dm.dc->links[notify.link_index];
837 notify.hpd_status == DP_HPD_PLUG;
840 queue_work(adev->dm.delayed_hpd_wq, &dmub_hpd_wrk->handle_hpd_work);
842 dm->dmub_callback[notify.type](adev, ¬ify);
844 } while (notify.pending_notification);
849 if (dc_dmub_srv_get_dmub_outbox0_msg(dm->dc, &entry)) {
850 trace_amdgpu_dmub_trace_high_irq(entry.trace_code, entry.tick_count,
851 entry.param0, entry.param1);
853 DRM_DEBUG_DRIVER("trace_code:%u, tick_count:%u, param0:%u, param1:%u\n",
854 entry.trace_code, entry.tick_count, entry.param0, entry.param1);
860 } while (count <= DMUB_TRACE_MAX_READ);
862 if (count > DMUB_TRACE_MAX_READ)
863 DRM_DEBUG_DRIVER("Warning : count > DMUB_TRACE_MAX_READ");
866 static int dm_set_clockgating_state(void *handle,
867 enum amd_clockgating_state state)
872 static int dm_set_powergating_state(void *handle,
873 enum amd_powergating_state state)
878 /* Prototypes of private functions */
879 static int dm_early_init(void* handle);
881 /* Allocate memory for FBC compressed data */
882 static void amdgpu_dm_fbc_init(struct drm_connector *connector)
884 struct drm_device *dev = connector->dev;
885 struct amdgpu_device *adev = drm_to_adev(dev);
886 struct dm_compressor_info *compressor = &adev->dm.compressor;
887 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
888 struct drm_display_mode *mode;
889 unsigned long max_size = 0;
891 if (adev->dm.dc->fbc_compressor == NULL)
894 if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
897 if (compressor->bo_ptr)
901 list_for_each_entry(mode, &connector->modes, head) {
902 if (max_size < mode->htotal * mode->vtotal)
903 max_size = mode->htotal * mode->vtotal;
907 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,
908 AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr,
909 &compressor->gpu_addr, &compressor->cpu_addr);
912 DRM_ERROR("DM: Failed to initialize FBC\n");
914 adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
915 DRM_INFO("DM: FBC alloc %lu\n", max_size*4);
922 static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port,
923 int pipe, bool *enabled,
924 unsigned char *buf, int max_bytes)
926 struct drm_device *dev = dev_get_drvdata(kdev);
927 struct amdgpu_device *adev = drm_to_adev(dev);
928 struct drm_connector *connector;
929 struct drm_connector_list_iter conn_iter;
930 struct amdgpu_dm_connector *aconnector;
935 mutex_lock(&adev->dm.audio_lock);
937 drm_connector_list_iter_begin(dev, &conn_iter);
938 drm_for_each_connector_iter(connector, &conn_iter) {
939 aconnector = to_amdgpu_dm_connector(connector);
940 if (aconnector->audio_inst != port)
944 ret = drm_eld_size(connector->eld);
945 memcpy(buf, connector->eld, min(max_bytes, ret));
949 drm_connector_list_iter_end(&conn_iter);
951 mutex_unlock(&adev->dm.audio_lock);
953 DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled);
958 static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = {
959 .get_eld = amdgpu_dm_audio_component_get_eld,
962 static int amdgpu_dm_audio_component_bind(struct device *kdev,
963 struct device *hda_kdev, void *data)
965 struct drm_device *dev = dev_get_drvdata(kdev);
966 struct amdgpu_device *adev = drm_to_adev(dev);
967 struct drm_audio_component *acomp = data;
969 acomp->ops = &amdgpu_dm_audio_component_ops;
971 adev->dm.audio_component = acomp;
976 static void amdgpu_dm_audio_component_unbind(struct device *kdev,
977 struct device *hda_kdev, void *data)
979 struct drm_device *dev = dev_get_drvdata(kdev);
980 struct amdgpu_device *adev = drm_to_adev(dev);
981 struct drm_audio_component *acomp = data;
985 adev->dm.audio_component = NULL;
988 static const struct component_ops amdgpu_dm_audio_component_bind_ops = {
989 .bind = amdgpu_dm_audio_component_bind,
990 .unbind = amdgpu_dm_audio_component_unbind,
993 static int amdgpu_dm_audio_init(struct amdgpu_device *adev)
1000 adev->mode_info.audio.enabled = true;
1002 adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count;
1004 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1005 adev->mode_info.audio.pin[i].channels = -1;
1006 adev->mode_info.audio.pin[i].rate = -1;
1007 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1008 adev->mode_info.audio.pin[i].status_bits = 0;
1009 adev->mode_info.audio.pin[i].category_code = 0;
1010 adev->mode_info.audio.pin[i].connected = false;
1011 adev->mode_info.audio.pin[i].id =
1012 adev->dm.dc->res_pool->audios[i]->inst;
1013 adev->mode_info.audio.pin[i].offset = 0;
1016 ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops);
1020 adev->dm.audio_registered = true;
1025 static void amdgpu_dm_audio_fini(struct amdgpu_device *adev)
1030 if (!adev->mode_info.audio.enabled)
1033 if (adev->dm.audio_registered) {
1034 component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops);
1035 adev->dm.audio_registered = false;
1038 /* TODO: Disable audio? */
1040 adev->mode_info.audio.enabled = false;
1043 static void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin)
1045 struct drm_audio_component *acomp = adev->dm.audio_component;
1047 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) {
1048 DRM_DEBUG_KMS("Notify ELD: %d\n", pin);
1050 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
1055 static int dm_dmub_hw_init(struct amdgpu_device *adev)
1057 const struct dmcub_firmware_header_v1_0 *hdr;
1058 struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
1059 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
1060 const struct firmware *dmub_fw = adev->dm.dmub_fw;
1061 struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
1062 struct abm *abm = adev->dm.dc->res_pool->abm;
1063 struct dmub_srv_hw_params hw_params;
1064 enum dmub_status status;
1065 const unsigned char *fw_inst_const, *fw_bss_data;
1066 u32 i, fw_inst_const_size, fw_bss_data_size;
1067 bool has_hw_support;
1070 /* DMUB isn't supported on the ASIC. */
1074 DRM_ERROR("No framebuffer info for DMUB service.\n");
1079 /* Firmware required for DMUB support. */
1080 DRM_ERROR("No firmware provided for DMUB.\n");
1084 status = dmub_srv_has_hw_support(dmub_srv, &has_hw_support);
1085 if (status != DMUB_STATUS_OK) {
1086 DRM_ERROR("Error checking HW support for DMUB: %d\n", status);
1090 if (!has_hw_support) {
1091 DRM_INFO("DMUB unsupported on ASIC\n");
1095 /* Reset DMCUB if it was previously running - before we overwrite its memory. */
1096 status = dmub_srv_hw_reset(dmub_srv);
1097 if (status != DMUB_STATUS_OK)
1098 DRM_WARN("Error resetting DMUB HW: %d\n", status);
1100 hdr = (const struct dmcub_firmware_header_v1_0 *)dmub_fw->data;
1102 fw_inst_const = dmub_fw->data +
1103 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1106 fw_bss_data = dmub_fw->data +
1107 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1108 le32_to_cpu(hdr->inst_const_bytes);
1110 /* Copy firmware and bios info into FB memory. */
1111 fw_inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
1112 PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
1114 fw_bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
1116 /* if adev->firmware.load_type == AMDGPU_FW_LOAD_PSP,
1117 * amdgpu_ucode_init_single_fw will load dmub firmware
1118 * fw_inst_const part to cw0; otherwise, the firmware back door load
1119 * will be done by dm_dmub_hw_init
1121 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1122 memcpy(fb_info->fb[DMUB_WINDOW_0_INST_CONST].cpu_addr, fw_inst_const,
1123 fw_inst_const_size);
1126 if (fw_bss_data_size)
1127 memcpy(fb_info->fb[DMUB_WINDOW_2_BSS_DATA].cpu_addr,
1128 fw_bss_data, fw_bss_data_size);
1130 /* Copy firmware bios info into FB memory. */
1131 memcpy(fb_info->fb[DMUB_WINDOW_3_VBIOS].cpu_addr, adev->bios,
1134 /* Reset regions that need to be reset. */
1135 memset(fb_info->fb[DMUB_WINDOW_4_MAILBOX].cpu_addr, 0,
1136 fb_info->fb[DMUB_WINDOW_4_MAILBOX].size);
1138 memset(fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr, 0,
1139 fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size);
1141 memset(fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr, 0,
1142 fb_info->fb[DMUB_WINDOW_6_FW_STATE].size);
1144 /* Initialize hardware. */
1145 memset(&hw_params, 0, sizeof(hw_params));
1146 hw_params.fb_base = adev->gmc.fb_start;
1147 hw_params.fb_offset = adev->vm_manager.vram_base_offset;
1149 /* backdoor load firmware and trigger dmub running */
1150 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
1151 hw_params.load_inst_const = true;
1154 hw_params.psp_version = dmcu->psp_version;
1156 for (i = 0; i < fb_info->num_fb; ++i)
1157 hw_params.fb[i] = &fb_info->fb[i];
1159 switch (adev->ip_versions[DCE_HWIP][0]) {
1160 case IP_VERSION(3, 1, 3):
1161 case IP_VERSION(3, 1, 4):
1162 hw_params.dpia_supported = true;
1163 hw_params.disable_dpia = adev->dm.dc->debug.dpia_debug.bits.disable_dpia;
1169 status = dmub_srv_hw_init(dmub_srv, &hw_params);
1170 if (status != DMUB_STATUS_OK) {
1171 DRM_ERROR("Error initializing DMUB HW: %d\n", status);
1175 /* Wait for firmware load to finish. */
1176 status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
1177 if (status != DMUB_STATUS_OK)
1178 DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
1180 /* Init DMCU and ABM if available. */
1182 dmcu->funcs->dmcu_init(dmcu);
1183 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
1186 if (!adev->dm.dc->ctx->dmub_srv)
1187 adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv);
1188 if (!adev->dm.dc->ctx->dmub_srv) {
1189 DRM_ERROR("Couldn't allocate DC DMUB server!\n");
1193 DRM_INFO("DMUB hardware initialized: version=0x%08X\n",
1194 adev->dm.dmcub_fw_version);
1199 static void dm_dmub_hw_resume(struct amdgpu_device *adev)
1201 struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
1202 enum dmub_status status;
1206 /* DMUB isn't supported on the ASIC. */
1210 status = dmub_srv_is_hw_init(dmub_srv, &init);
1211 if (status != DMUB_STATUS_OK)
1212 DRM_WARN("DMUB hardware init check failed: %d\n", status);
1214 if (status == DMUB_STATUS_OK && init) {
1215 /* Wait for firmware load to finish. */
1216 status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
1217 if (status != DMUB_STATUS_OK)
1218 DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
1220 /* Perform the full hardware initialization. */
1221 dm_dmub_hw_init(adev);
1225 static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_addr_space_config *pa_config)
1228 u32 logical_addr_low;
1229 u32 logical_addr_high;
1230 u32 agp_base, agp_bot, agp_top;
1231 PHYSICAL_ADDRESS_LOC page_table_start, page_table_end, page_table_base;
1233 memset(pa_config, 0, sizeof(*pa_config));
1236 agp_bot = adev->gmc.agp_start >> 24;
1237 agp_top = adev->gmc.agp_end >> 24;
1239 /* AGP aperture is disabled */
1240 if (agp_bot == agp_top) {
1241 logical_addr_low = adev->gmc.fb_start >> 18;
1242 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1244 * Raven2 has a HW issue that it is unable to use the vram which
1245 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
1246 * workaround that increase system aperture high address (add 1)
1247 * to get rid of the VM fault and hardware hang.
1249 logical_addr_high = (adev->gmc.fb_end >> 18) + 0x1;
1251 logical_addr_high = adev->gmc.fb_end >> 18;
1253 logical_addr_low = min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18;
1254 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1256 * Raven2 has a HW issue that it is unable to use the vram which
1257 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
1258 * workaround that increase system aperture high address (add 1)
1259 * to get rid of the VM fault and hardware hang.
1261 logical_addr_high = max((adev->gmc.fb_end >> 18) + 0x1, adev->gmc.agp_end >> 18);
1263 logical_addr_high = max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18;
1266 pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
1268 page_table_start.high_part = (u32)(adev->gmc.gart_start >> 44) & 0xF;
1269 page_table_start.low_part = (u32)(adev->gmc.gart_start >> 12);
1270 page_table_end.high_part = (u32)(adev->gmc.gart_end >> 44) & 0xF;
1271 page_table_end.low_part = (u32)(adev->gmc.gart_end >> 12);
1272 page_table_base.high_part = upper_32_bits(pt_base) & 0xF;
1273 page_table_base.low_part = lower_32_bits(pt_base);
1275 pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18;
1276 pa_config->system_aperture.end_addr = (uint64_t)logical_addr_high << 18;
1278 pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24 ;
1279 pa_config->system_aperture.agp_bot = (uint64_t)agp_bot << 24;
1280 pa_config->system_aperture.agp_top = (uint64_t)agp_top << 24;
1282 pa_config->system_aperture.fb_base = adev->gmc.fb_start;
1283 pa_config->system_aperture.fb_offset = adev->vm_manager.vram_base_offset;
1284 pa_config->system_aperture.fb_top = adev->gmc.fb_end;
1286 pa_config->gart_config.page_table_start_addr = page_table_start.quad_part << 12;
1287 pa_config->gart_config.page_table_end_addr = page_table_end.quad_part << 12;
1288 pa_config->gart_config.page_table_base_addr = page_table_base.quad_part;
1290 pa_config->is_hvm_enabled = adev->mode_info.gpu_vm_support;
1294 static void force_connector_state(
1295 struct amdgpu_dm_connector *aconnector,
1296 enum drm_connector_force force_state)
1298 struct drm_connector *connector = &aconnector->base;
1300 mutex_lock(&connector->dev->mode_config.mutex);
1301 aconnector->base.force = force_state;
1302 mutex_unlock(&connector->dev->mode_config.mutex);
1304 mutex_lock(&aconnector->hpd_lock);
1305 drm_kms_helper_connector_hotplug_event(connector);
1306 mutex_unlock(&aconnector->hpd_lock);
1309 static void dm_handle_hpd_rx_offload_work(struct work_struct *work)
1311 struct hpd_rx_irq_offload_work *offload_work;
1312 struct amdgpu_dm_connector *aconnector;
1313 struct dc_link *dc_link;
1314 struct amdgpu_device *adev;
1315 enum dc_connection_type new_connection_type = dc_connection_none;
1316 unsigned long flags;
1317 union test_response test_response;
1319 memset(&test_response, 0, sizeof(test_response));
1321 offload_work = container_of(work, struct hpd_rx_irq_offload_work, work);
1322 aconnector = offload_work->offload_wq->aconnector;
1325 DRM_ERROR("Can't retrieve aconnector in hpd_rx_irq_offload_work");
1329 adev = drm_to_adev(aconnector->base.dev);
1330 dc_link = aconnector->dc_link;
1332 mutex_lock(&aconnector->hpd_lock);
1333 if (!dc_link_detect_connection_type(dc_link, &new_connection_type))
1334 DRM_ERROR("KMS: Failed to detect connector\n");
1335 mutex_unlock(&aconnector->hpd_lock);
1337 if (new_connection_type == dc_connection_none)
1340 if (amdgpu_in_reset(adev))
1343 mutex_lock(&adev->dm.dc_lock);
1344 if (offload_work->data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
1345 dc_link_dp_handle_automated_test(dc_link);
1347 if (aconnector->timing_changed) {
1348 /* force connector disconnect and reconnect */
1349 force_connector_state(aconnector, DRM_FORCE_OFF);
1351 force_connector_state(aconnector, DRM_FORCE_UNSPECIFIED);
1354 test_response.bits.ACK = 1;
1356 core_link_write_dpcd(
1360 sizeof(test_response));
1362 else if ((dc_link->connector_signal != SIGNAL_TYPE_EDP) &&
1363 dc_link_check_link_loss_status(dc_link, &offload_work->data) &&
1364 dc_link_dp_allow_hpd_rx_irq(dc_link)) {
1365 /* offload_work->data is from handle_hpd_rx_irq->
1366 * schedule_hpd_rx_offload_work.this is defer handle
1367 * for hpd short pulse. upon here, link status may be
1368 * changed, need get latest link status from dpcd
1369 * registers. if link status is good, skip run link
1372 union hpd_irq_data irq_data;
1374 memset(&irq_data, 0, sizeof(irq_data));
1376 /* before dc_link_dp_handle_link_loss, allow new link lost handle
1377 * request be added to work queue if link lost at end of dc_link_
1378 * dp_handle_link_loss
1380 spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags);
1381 offload_work->offload_wq->is_handling_link_loss = false;
1382 spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags);
1384 if ((dc_link_dp_read_hpd_rx_irq_data(dc_link, &irq_data) == DC_OK) &&
1385 dc_link_check_link_loss_status(dc_link, &irq_data))
1386 dc_link_dp_handle_link_loss(dc_link);
1388 mutex_unlock(&adev->dm.dc_lock);
1391 kfree(offload_work);
1395 static struct hpd_rx_irq_offload_work_queue *hpd_rx_irq_create_workqueue(struct dc *dc)
1397 int max_caps = dc->caps.max_links;
1399 struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq = NULL;
1401 hpd_rx_offload_wq = kcalloc(max_caps, sizeof(*hpd_rx_offload_wq), GFP_KERNEL);
1403 if (!hpd_rx_offload_wq)
1407 for (i = 0; i < max_caps; i++) {
1408 hpd_rx_offload_wq[i].wq =
1409 create_singlethread_workqueue("amdgpu_dm_hpd_rx_offload_wq");
1411 if (hpd_rx_offload_wq[i].wq == NULL) {
1412 DRM_ERROR("create amdgpu_dm_hpd_rx_offload_wq fail!");
1416 spin_lock_init(&hpd_rx_offload_wq[i].offload_lock);
1419 return hpd_rx_offload_wq;
1422 for (i = 0; i < max_caps; i++) {
1423 if (hpd_rx_offload_wq[i].wq)
1424 destroy_workqueue(hpd_rx_offload_wq[i].wq);
1426 kfree(hpd_rx_offload_wq);
1430 struct amdgpu_stutter_quirk {
1438 static const struct amdgpu_stutter_quirk amdgpu_stutter_quirk_list[] = {
1439 /* https://bugzilla.kernel.org/show_bug.cgi?id=214417 */
1440 { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 },
1444 static bool dm_should_disable_stutter(struct pci_dev *pdev)
1446 const struct amdgpu_stutter_quirk *p = amdgpu_stutter_quirk_list;
1448 while (p && p->chip_device != 0) {
1449 if (pdev->vendor == p->chip_vendor &&
1450 pdev->device == p->chip_device &&
1451 pdev->subsystem_vendor == p->subsys_vendor &&
1452 pdev->subsystem_device == p->subsys_device &&
1453 pdev->revision == p->revision) {
1461 static const struct dmi_system_id hpd_disconnect_quirk_table[] = {
1464 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1465 DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3660"),
1470 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1471 DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3260"),
1476 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1477 DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3460"),
1482 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1483 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower Plus 7010"),
1488 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1489 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower 7010"),
1494 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1495 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF Plus 7010"),
1500 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1501 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF 7010"),
1506 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1507 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro Plus 7010"),
1512 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1513 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro 7010"),
1517 /* TODO: refactor this from a fixed table to a dynamic option */
1520 static void retrieve_dmi_info(struct amdgpu_display_manager *dm)
1522 const struct dmi_system_id *dmi_id;
1524 dm->aux_hpd_discon_quirk = false;
1526 dmi_id = dmi_first_match(hpd_disconnect_quirk_table);
1528 dm->aux_hpd_discon_quirk = true;
1529 DRM_INFO("aux_hpd_discon_quirk attached\n");
1533 static int amdgpu_dm_init(struct amdgpu_device *adev)
1535 struct dc_init_data init_data;
1536 struct dc_callback_init init_params;
1539 adev->dm.ddev = adev_to_drm(adev);
1540 adev->dm.adev = adev;
1542 /* Zero all the fields */
1543 memset(&init_data, 0, sizeof(init_data));
1544 memset(&init_params, 0, sizeof(init_params));
1546 mutex_init(&adev->dm.dpia_aux_lock);
1547 mutex_init(&adev->dm.dc_lock);
1548 mutex_init(&adev->dm.audio_lock);
1550 if(amdgpu_dm_irq_init(adev)) {
1551 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
1555 init_data.asic_id.chip_family = adev->family;
1557 init_data.asic_id.pci_revision_id = adev->pdev->revision;
1558 init_data.asic_id.hw_internal_rev = adev->external_rev_id;
1559 init_data.asic_id.chip_id = adev->pdev->device;
1561 init_data.asic_id.vram_width = adev->gmc.vram_width;
1562 /* TODO: initialize init_data.asic_id.vram_type here!!!! */
1563 init_data.asic_id.atombios_base_address =
1564 adev->mode_info.atom_context->bios;
1566 init_data.driver = adev;
1568 adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
1570 if (!adev->dm.cgs_device) {
1571 DRM_ERROR("amdgpu: failed to create cgs device.\n");
1575 init_data.cgs_device = adev->dm.cgs_device;
1577 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
1579 switch (adev->ip_versions[DCE_HWIP][0]) {
1580 case IP_VERSION(2, 1, 0):
1581 switch (adev->dm.dmcub_fw_version) {
1582 case 0: /* development */
1583 case 0x1: /* linux-firmware.git hash 6d9f399 */
1584 case 0x01000000: /* linux-firmware.git hash 9a0b0f4 */
1585 init_data.flags.disable_dmcu = false;
1588 init_data.flags.disable_dmcu = true;
1591 case IP_VERSION(2, 0, 3):
1592 init_data.flags.disable_dmcu = true;
1598 switch (adev->asic_type) {
1601 init_data.flags.gpu_vm_support = true;
1604 switch (adev->ip_versions[DCE_HWIP][0]) {
1605 case IP_VERSION(1, 0, 0):
1606 case IP_VERSION(1, 0, 1):
1607 /* enable S/G on PCO and RV2 */
1608 if ((adev->apu_flags & AMD_APU_IS_RAVEN2) ||
1609 (adev->apu_flags & AMD_APU_IS_PICASSO))
1610 init_data.flags.gpu_vm_support = true;
1612 case IP_VERSION(2, 1, 0):
1613 case IP_VERSION(3, 0, 1):
1614 case IP_VERSION(3, 1, 2):
1615 case IP_VERSION(3, 1, 3):
1616 case IP_VERSION(3, 1, 4):
1617 case IP_VERSION(3, 1, 5):
1618 case IP_VERSION(3, 1, 6):
1619 init_data.flags.gpu_vm_support = true;
1626 if (init_data.flags.gpu_vm_support &&
1627 (amdgpu_sg_display == 0))
1628 init_data.flags.gpu_vm_support = false;
1630 if (init_data.flags.gpu_vm_support)
1631 adev->mode_info.gpu_vm_support = true;
1633 if (amdgpu_dc_feature_mask & DC_FBC_MASK)
1634 init_data.flags.fbc_support = true;
1636 if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK)
1637 init_data.flags.multi_mon_pp_mclk_switch = true;
1639 if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK)
1640 init_data.flags.disable_fractional_pwm = true;
1642 if (amdgpu_dc_feature_mask & DC_EDP_NO_POWER_SEQUENCING)
1643 init_data.flags.edp_no_power_sequencing = true;
1645 if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP1_4A)
1646 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP1_4A = true;
1647 if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP2_0)
1648 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP2_0 = true;
1650 /* Disable SubVP + DRR config by default */
1651 init_data.flags.disable_subvp_drr = true;
1652 if (amdgpu_dc_feature_mask & DC_ENABLE_SUBVP_DRR)
1653 init_data.flags.disable_subvp_drr = false;
1655 init_data.flags.seamless_boot_edp_requested = false;
1657 if (check_seamless_boot_capability(adev)) {
1658 init_data.flags.seamless_boot_edp_requested = true;
1659 init_data.flags.allow_seamless_boot_optimization = true;
1660 DRM_INFO("Seamless boot condition check passed\n");
1663 init_data.flags.enable_mipi_converter_optimization = true;
1665 init_data.dcn_reg_offsets = adev->reg_offset[DCE_HWIP][0];
1666 init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0];
1668 INIT_LIST_HEAD(&adev->dm.da_list);
1670 retrieve_dmi_info(&adev->dm);
1672 /* Display Core create. */
1673 adev->dm.dc = dc_create(&init_data);
1676 DRM_INFO("Display Core initialized with v%s!\n", DC_VER);
1678 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER);
1682 if (amdgpu_dc_debug_mask & DC_DISABLE_PIPE_SPLIT) {
1683 adev->dm.dc->debug.force_single_disp_pipe_split = false;
1684 adev->dm.dc->debug.pipe_split_policy = MPC_SPLIT_AVOID;
1687 if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY)
1688 adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;
1689 if (dm_should_disable_stutter(adev->pdev))
1690 adev->dm.dc->debug.disable_stutter = true;
1692 if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER)
1693 adev->dm.dc->debug.disable_stutter = true;
1695 if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) {
1696 adev->dm.dc->debug.disable_dsc = true;
1699 if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING)
1700 adev->dm.dc->debug.disable_clock_gate = true;
1702 if (amdgpu_dc_debug_mask & DC_FORCE_SUBVP_MCLK_SWITCH)
1703 adev->dm.dc->debug.force_subvp_mclk_switch = true;
1705 adev->dm.dc->debug.visual_confirm = amdgpu_dc_visual_confirm;
1707 /* TODO: Remove after DP2 receiver gets proper support of Cable ID feature */
1708 adev->dm.dc->debug.ignore_cable_id = true;
1710 /* TODO: There is a new drm mst change where the freedom of
1711 * vc_next_start_slot update is revoked/moved into drm, instead of in
1712 * driver. This forces us to make sure to get vc_next_start_slot updated
1713 * in drm function each time without considering if mst_state is active
1714 * or not. Otherwise, next time hotplug will give wrong start_slot
1715 * number. We are implementing a temporary solution to even notify drm
1716 * mst deallocation when link is no longer of MST type when uncommitting
1717 * the stream so we will have more time to work on a proper solution.
1718 * Ideally when dm_helpers_dp_mst_stop_top_mgr message is triggered, we
1719 * should notify drm to do a complete "reset" of its states and stop
1720 * calling further drm mst functions when link is no longer of an MST
1721 * type. This could happen when we unplug an MST hubs/displays. When
1722 * uncommit stream comes later after unplug, we should just reset
1723 * hardware states only.
1725 adev->dm.dc->debug.temp_mst_deallocation_sequence = true;
1727 if (adev->dm.dc->caps.dp_hdmi21_pcon_support)
1728 DRM_INFO("DP-HDMI FRL PCON supported\n");
1730 r = dm_dmub_hw_init(adev);
1732 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
1736 dc_hardware_init(adev->dm.dc);
1738 adev->dm.hpd_rx_offload_wq = hpd_rx_irq_create_workqueue(adev->dm.dc);
1739 if (!adev->dm.hpd_rx_offload_wq) {
1740 DRM_ERROR("amdgpu: failed to create hpd rx offload workqueue.\n");
1744 if ((adev->flags & AMD_IS_APU) && (adev->asic_type >= CHIP_CARRIZO)) {
1745 struct dc_phy_addr_space_config pa_config;
1747 mmhub_read_system_context(adev, &pa_config);
1749 // Call the DC init_memory func
1750 dc_setup_system_context(adev->dm.dc, &pa_config);
1753 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
1754 if (!adev->dm.freesync_module) {
1756 "amdgpu: failed to initialize freesync_module.\n");
1758 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
1759 adev->dm.freesync_module);
1761 amdgpu_dm_init_color_mod();
1763 if (adev->dm.dc->caps.max_links > 0) {
1764 adev->dm.vblank_control_workqueue =
1765 create_singlethread_workqueue("dm_vblank_control_workqueue");
1766 if (!adev->dm.vblank_control_workqueue)
1767 DRM_ERROR("amdgpu: failed to initialize vblank_workqueue.\n");
1770 if (adev->dm.dc->caps.max_links > 0 && adev->family >= AMDGPU_FAMILY_RV) {
1771 adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc);
1773 if (!adev->dm.hdcp_workqueue)
1774 DRM_ERROR("amdgpu: failed to initialize hdcp_workqueue.\n");
1776 DRM_DEBUG_DRIVER("amdgpu: hdcp_workqueue init done %p.\n", adev->dm.hdcp_workqueue);
1778 dc_init_callbacks(adev->dm.dc, &init_params);
1780 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
1781 adev->dm.secure_display_ctxs = amdgpu_dm_crtc_secure_display_create_contexts(adev);
1782 if (!adev->dm.secure_display_ctxs) {
1783 DRM_ERROR("amdgpu: failed to initialize secure_display_ctxs.\n");
1786 if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
1787 init_completion(&adev->dm.dmub_aux_transfer_done);
1788 adev->dm.dmub_notify = kzalloc(sizeof(struct dmub_notification), GFP_KERNEL);
1789 if (!adev->dm.dmub_notify) {
1790 DRM_INFO("amdgpu: fail to allocate adev->dm.dmub_notify");
1794 adev->dm.delayed_hpd_wq = create_singlethread_workqueue("amdgpu_dm_hpd_wq");
1795 if (!adev->dm.delayed_hpd_wq) {
1796 DRM_ERROR("amdgpu: failed to create hpd offload workqueue.\n");
1800 amdgpu_dm_outbox_init(adev);
1801 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_AUX_REPLY,
1802 dmub_aux_setconfig_callback, false)) {
1803 DRM_ERROR("amdgpu: fail to register dmub aux callback");
1806 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD, dmub_hpd_callback, true)) {
1807 DRM_ERROR("amdgpu: fail to register dmub hpd callback");
1810 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD_IRQ, dmub_hpd_callback, true)) {
1811 DRM_ERROR("amdgpu: fail to register dmub hpd callback");
1816 /* Enable outbox notification only after IRQ handlers are registered and DMUB is alive.
1817 * It is expected that DMUB will resend any pending notifications at this point, for
1818 * example HPD from DPIA.
1820 if (dc_is_dmub_outbox_supported(adev->dm.dc))
1821 dc_enable_dmub_outbox(adev->dm.dc);
1823 if (amdgpu_dm_initialize_drm_device(adev)) {
1825 "amdgpu: failed to initialize sw for display support.\n");
1829 /* create fake encoders for MST */
1830 dm_dp_create_fake_mst_encoders(adev);
1832 /* TODO: Add_display_info? */
1834 /* TODO use dynamic cursor width */
1835 adev_to_drm(adev)->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
1836 adev_to_drm(adev)->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
1838 if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) {
1840 "amdgpu: failed to initialize sw for display support.\n");
1845 DRM_DEBUG_DRIVER("KMS initialized.\n");
1849 amdgpu_dm_fini(adev);
1854 static int amdgpu_dm_early_fini(void *handle)
1856 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1858 amdgpu_dm_audio_fini(adev);
1863 static void amdgpu_dm_fini(struct amdgpu_device *adev)
1867 if (adev->dm.vblank_control_workqueue) {
1868 destroy_workqueue(adev->dm.vblank_control_workqueue);
1869 adev->dm.vblank_control_workqueue = NULL;
1872 amdgpu_dm_destroy_drm_device(&adev->dm);
1874 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
1875 if (adev->dm.secure_display_ctxs) {
1876 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1877 if (adev->dm.secure_display_ctxs[i].crtc) {
1878 flush_work(&adev->dm.secure_display_ctxs[i].notify_ta_work);
1879 flush_work(&adev->dm.secure_display_ctxs[i].forward_roi_work);
1882 kfree(adev->dm.secure_display_ctxs);
1883 adev->dm.secure_display_ctxs = NULL;
1886 if (adev->dm.hdcp_workqueue) {
1887 hdcp_destroy(&adev->dev->kobj, adev->dm.hdcp_workqueue);
1888 adev->dm.hdcp_workqueue = NULL;
1892 dc_deinit_callbacks(adev->dm.dc);
1894 dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv);
1896 if (dc_enable_dmub_notifications(adev->dm.dc)) {
1897 kfree(adev->dm.dmub_notify);
1898 adev->dm.dmub_notify = NULL;
1899 destroy_workqueue(adev->dm.delayed_hpd_wq);
1900 adev->dm.delayed_hpd_wq = NULL;
1903 if (adev->dm.dmub_bo)
1904 amdgpu_bo_free_kernel(&adev->dm.dmub_bo,
1905 &adev->dm.dmub_bo_gpu_addr,
1906 &adev->dm.dmub_bo_cpu_addr);
1908 if (adev->dm.hpd_rx_offload_wq) {
1909 for (i = 0; i < adev->dm.dc->caps.max_links; i++) {
1910 if (adev->dm.hpd_rx_offload_wq[i].wq) {
1911 destroy_workqueue(adev->dm.hpd_rx_offload_wq[i].wq);
1912 adev->dm.hpd_rx_offload_wq[i].wq = NULL;
1916 kfree(adev->dm.hpd_rx_offload_wq);
1917 adev->dm.hpd_rx_offload_wq = NULL;
1920 /* DC Destroy TODO: Replace destroy DAL */
1922 dc_destroy(&adev->dm.dc);
1924 * TODO: pageflip, vlank interrupt
1926 * amdgpu_dm_irq_fini(adev);
1929 if (adev->dm.cgs_device) {
1930 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
1931 adev->dm.cgs_device = NULL;
1933 if (adev->dm.freesync_module) {
1934 mod_freesync_destroy(adev->dm.freesync_module);
1935 adev->dm.freesync_module = NULL;
1938 mutex_destroy(&adev->dm.audio_lock);
1939 mutex_destroy(&adev->dm.dc_lock);
1940 mutex_destroy(&adev->dm.dpia_aux_lock);
1945 static int load_dmcu_fw(struct amdgpu_device *adev)
1947 const char *fw_name_dmcu = NULL;
1949 const struct dmcu_firmware_header_v1_0 *hdr;
1951 switch(adev->asic_type) {
1952 #if defined(CONFIG_DRM_AMD_DC_SI)
1967 case CHIP_POLARIS11:
1968 case CHIP_POLARIS10:
1969 case CHIP_POLARIS12:
1976 fw_name_dmcu = FIRMWARE_NAVI12_DMCU;
1979 if (ASICREV_IS_PICASSO(adev->external_rev_id))
1980 fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
1981 else if (ASICREV_IS_RAVEN2(adev->external_rev_id))
1982 fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
1987 switch (adev->ip_versions[DCE_HWIP][0]) {
1988 case IP_VERSION(2, 0, 2):
1989 case IP_VERSION(2, 0, 3):
1990 case IP_VERSION(2, 0, 0):
1991 case IP_VERSION(2, 1, 0):
1992 case IP_VERSION(3, 0, 0):
1993 case IP_VERSION(3, 0, 2):
1994 case IP_VERSION(3, 0, 3):
1995 case IP_VERSION(3, 0, 1):
1996 case IP_VERSION(3, 1, 2):
1997 case IP_VERSION(3, 1, 3):
1998 case IP_VERSION(3, 1, 4):
1999 case IP_VERSION(3, 1, 5):
2000 case IP_VERSION(3, 1, 6):
2001 case IP_VERSION(3, 2, 0):
2002 case IP_VERSION(3, 2, 1):
2007 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
2011 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
2012 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n");
2016 r = amdgpu_ucode_request(adev, &adev->dm.fw_dmcu, fw_name_dmcu);
2018 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */
2019 DRM_DEBUG_KMS("dm: DMCU firmware not found\n");
2020 adev->dm.fw_dmcu = NULL;
2024 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n",
2026 amdgpu_ucode_release(&adev->dm.fw_dmcu);
2030 hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data;
2031 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM;
2032 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu;
2033 adev->firmware.fw_size +=
2034 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
2036 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV;
2037 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu;
2038 adev->firmware.fw_size +=
2039 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
2041 adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version);
2043 DRM_DEBUG_KMS("PSP loading DMCU firmware\n");
2048 static uint32_t amdgpu_dm_dmub_reg_read(void *ctx, uint32_t address)
2050 struct amdgpu_device *adev = ctx;
2052 return dm_read_reg(adev->dm.dc->ctx, address);
2055 static void amdgpu_dm_dmub_reg_write(void *ctx, uint32_t address,
2058 struct amdgpu_device *adev = ctx;
2060 return dm_write_reg(adev->dm.dc->ctx, address, value);
2063 static int dm_dmub_sw_init(struct amdgpu_device *adev)
2065 struct dmub_srv_create_params create_params;
2066 struct dmub_srv_region_params region_params;
2067 struct dmub_srv_region_info region_info;
2068 struct dmub_srv_fb_params fb_params;
2069 struct dmub_srv_fb_info *fb_info;
2070 struct dmub_srv *dmub_srv;
2071 const struct dmcub_firmware_header_v1_0 *hdr;
2072 enum dmub_asic dmub_asic;
2073 enum dmub_status status;
2076 switch (adev->ip_versions[DCE_HWIP][0]) {
2077 case IP_VERSION(2, 1, 0):
2078 dmub_asic = DMUB_ASIC_DCN21;
2080 case IP_VERSION(3, 0, 0):
2081 dmub_asic = DMUB_ASIC_DCN30;
2083 case IP_VERSION(3, 0, 1):
2084 dmub_asic = DMUB_ASIC_DCN301;
2086 case IP_VERSION(3, 0, 2):
2087 dmub_asic = DMUB_ASIC_DCN302;
2089 case IP_VERSION(3, 0, 3):
2090 dmub_asic = DMUB_ASIC_DCN303;
2092 case IP_VERSION(3, 1, 2):
2093 case IP_VERSION(3, 1, 3):
2094 dmub_asic = (adev->external_rev_id == YELLOW_CARP_B0) ? DMUB_ASIC_DCN31B : DMUB_ASIC_DCN31;
2096 case IP_VERSION(3, 1, 4):
2097 dmub_asic = DMUB_ASIC_DCN314;
2099 case IP_VERSION(3, 1, 5):
2100 dmub_asic = DMUB_ASIC_DCN315;
2102 case IP_VERSION(3, 1, 6):
2103 dmub_asic = DMUB_ASIC_DCN316;
2105 case IP_VERSION(3, 2, 0):
2106 dmub_asic = DMUB_ASIC_DCN32;
2108 case IP_VERSION(3, 2, 1):
2109 dmub_asic = DMUB_ASIC_DCN321;
2112 /* ASIC doesn't support DMUB. */
2116 hdr = (const struct dmcub_firmware_header_v1_0 *)adev->dm.dmub_fw->data;
2117 adev->dm.dmcub_fw_version = le32_to_cpu(hdr->header.ucode_version);
2119 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
2120 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].ucode_id =
2121 AMDGPU_UCODE_ID_DMCUB;
2122 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].fw =
2124 adev->firmware.fw_size +=
2125 ALIGN(le32_to_cpu(hdr->inst_const_bytes), PAGE_SIZE);
2127 DRM_INFO("Loading DMUB firmware via PSP: version=0x%08X\n",
2128 adev->dm.dmcub_fw_version);
2132 adev->dm.dmub_srv = kzalloc(sizeof(*adev->dm.dmub_srv), GFP_KERNEL);
2133 dmub_srv = adev->dm.dmub_srv;
2136 DRM_ERROR("Failed to allocate DMUB service!\n");
2140 memset(&create_params, 0, sizeof(create_params));
2141 create_params.user_ctx = adev;
2142 create_params.funcs.reg_read = amdgpu_dm_dmub_reg_read;
2143 create_params.funcs.reg_write = amdgpu_dm_dmub_reg_write;
2144 create_params.asic = dmub_asic;
2146 /* Create the DMUB service. */
2147 status = dmub_srv_create(dmub_srv, &create_params);
2148 if (status != DMUB_STATUS_OK) {
2149 DRM_ERROR("Error creating DMUB service: %d\n", status);
2153 /* Calculate the size of all the regions for the DMUB service. */
2154 memset(®ion_params, 0, sizeof(region_params));
2156 region_params.inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
2157 PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
2158 region_params.bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
2159 region_params.vbios_size = adev->bios_size;
2160 region_params.fw_bss_data = region_params.bss_data_size ?
2161 adev->dm.dmub_fw->data +
2162 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
2163 le32_to_cpu(hdr->inst_const_bytes) : NULL;
2164 region_params.fw_inst_const =
2165 adev->dm.dmub_fw->data +
2166 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
2169 status = dmub_srv_calc_region_info(dmub_srv, ®ion_params,
2172 if (status != DMUB_STATUS_OK) {
2173 DRM_ERROR("Error calculating DMUB region info: %d\n", status);
2178 * Allocate a framebuffer based on the total size of all the regions.
2179 * TODO: Move this into GART.
2181 r = amdgpu_bo_create_kernel(adev, region_info.fb_size, PAGE_SIZE,
2182 AMDGPU_GEM_DOMAIN_VRAM |
2183 AMDGPU_GEM_DOMAIN_GTT,
2185 &adev->dm.dmub_bo_gpu_addr,
2186 &adev->dm.dmub_bo_cpu_addr);
2190 /* Rebase the regions on the framebuffer address. */
2191 memset(&fb_params, 0, sizeof(fb_params));
2192 fb_params.cpu_addr = adev->dm.dmub_bo_cpu_addr;
2193 fb_params.gpu_addr = adev->dm.dmub_bo_gpu_addr;
2194 fb_params.region_info = ®ion_info;
2196 adev->dm.dmub_fb_info =
2197 kzalloc(sizeof(*adev->dm.dmub_fb_info), GFP_KERNEL);
2198 fb_info = adev->dm.dmub_fb_info;
2202 "Failed to allocate framebuffer info for DMUB service!\n");
2206 status = dmub_srv_calc_fb_info(dmub_srv, &fb_params, fb_info);
2207 if (status != DMUB_STATUS_OK) {
2208 DRM_ERROR("Error calculating DMUB FB info: %d\n", status);
2215 static int dm_sw_init(void *handle)
2217 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2220 r = dm_dmub_sw_init(adev);
2224 return load_dmcu_fw(adev);
2227 static int dm_sw_fini(void *handle)
2229 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2231 kfree(adev->dm.dmub_fb_info);
2232 adev->dm.dmub_fb_info = NULL;
2234 if (adev->dm.dmub_srv) {
2235 dmub_srv_destroy(adev->dm.dmub_srv);
2236 adev->dm.dmub_srv = NULL;
2239 amdgpu_ucode_release(&adev->dm.dmub_fw);
2240 amdgpu_ucode_release(&adev->dm.fw_dmcu);
2245 static int detect_mst_link_for_all_connectors(struct drm_device *dev)
2247 struct amdgpu_dm_connector *aconnector;
2248 struct drm_connector *connector;
2249 struct drm_connector_list_iter iter;
2252 drm_connector_list_iter_begin(dev, &iter);
2253 drm_for_each_connector_iter(connector, &iter) {
2254 aconnector = to_amdgpu_dm_connector(connector);
2255 if (aconnector->dc_link->type == dc_connection_mst_branch &&
2256 aconnector->mst_mgr.aux) {
2257 DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
2259 aconnector->base.base.id);
2261 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
2263 DRM_ERROR("DM_MST: Failed to start MST\n");
2264 aconnector->dc_link->type =
2265 dc_connection_single;
2266 ret = dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,
2267 aconnector->dc_link);
2272 drm_connector_list_iter_end(&iter);
2277 static int dm_late_init(void *handle)
2279 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2281 struct dmcu_iram_parameters params;
2282 unsigned int linear_lut[16];
2284 struct dmcu *dmcu = NULL;
2286 dmcu = adev->dm.dc->res_pool->dmcu;
2288 for (i = 0; i < 16; i++)
2289 linear_lut[i] = 0xFFFF * i / 15;
2292 params.backlight_ramping_override = false;
2293 params.backlight_ramping_start = 0xCCCC;
2294 params.backlight_ramping_reduction = 0xCCCCCCCC;
2295 params.backlight_lut_array_size = 16;
2296 params.backlight_lut_array = linear_lut;
2298 /* Min backlight level after ABM reduction, Don't allow below 1%
2299 * 0xFFFF x 0.01 = 0x28F
2301 params.min_abm_backlight = 0x28F;
2302 /* In the case where abm is implemented on dmcub,
2303 * dmcu object will be null.
2304 * ABM 2.4 and up are implemented on dmcub.
2307 if (!dmcu_load_iram(dmcu, params))
2309 } else if (adev->dm.dc->ctx->dmub_srv) {
2310 struct dc_link *edp_links[MAX_NUM_EDP];
2313 dc_get_edp_links(adev->dm.dc, edp_links, &edp_num);
2314 for (i = 0; i < edp_num; i++) {
2315 if (!dmub_init_abm_config(adev->dm.dc->res_pool, params, i))
2320 return detect_mst_link_for_all_connectors(adev_to_drm(adev));
2323 static void s3_handle_mst(struct drm_device *dev, bool suspend)
2325 struct amdgpu_dm_connector *aconnector;
2326 struct drm_connector *connector;
2327 struct drm_connector_list_iter iter;
2328 struct drm_dp_mst_topology_mgr *mgr;
2330 bool need_hotplug = false;
2332 drm_connector_list_iter_begin(dev, &iter);
2333 drm_for_each_connector_iter(connector, &iter) {
2334 aconnector = to_amdgpu_dm_connector(connector);
2335 if (aconnector->dc_link->type != dc_connection_mst_branch ||
2336 aconnector->mst_root)
2339 mgr = &aconnector->mst_mgr;
2342 drm_dp_mst_topology_mgr_suspend(mgr);
2344 /* if extended timeout is supported in hardware,
2345 * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer
2346 * CTS 4.2.1.1 regression introduced by CTS specs requirement update.
2348 try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD);
2349 if (!dp_is_lttpr_present(aconnector->dc_link))
2350 try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
2352 ret = drm_dp_mst_topology_mgr_resume(mgr, true);
2354 dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,
2355 aconnector->dc_link);
2356 need_hotplug = true;
2360 drm_connector_list_iter_end(&iter);
2363 drm_kms_helper_hotplug_event(dev);
2366 static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev)
2370 /* This interface is for dGPU Navi1x.Linux dc-pplib interface depends
2371 * on window driver dc implementation.
2372 * For Navi1x, clock settings of dcn watermarks are fixed. the settings
2373 * should be passed to smu during boot up and resume from s3.
2374 * boot up: dc calculate dcn watermark clock settings within dc_create,
2375 * dcn20_resource_construct
2376 * then call pplib functions below to pass the settings to smu:
2377 * smu_set_watermarks_for_clock_ranges
2378 * smu_set_watermarks_table
2379 * navi10_set_watermarks_table
2380 * smu_write_watermarks_table
2382 * For Renoir, clock settings of dcn watermark are also fixed values.
2383 * dc has implemented different flow for window driver:
2384 * dc_hardware_init / dc_set_power_state
2389 * smu_set_watermarks_for_clock_ranges
2390 * renoir_set_watermarks_table
2391 * smu_write_watermarks_table
2394 * dc_hardware_init -> amdgpu_dm_init
2395 * dc_set_power_state --> dm_resume
2397 * therefore, this function apply to navi10/12/14 but not Renoir
2400 switch (adev->ip_versions[DCE_HWIP][0]) {
2401 case IP_VERSION(2, 0, 2):
2402 case IP_VERSION(2, 0, 0):
2408 ret = amdgpu_dpm_write_watermarks_table(adev);
2410 DRM_ERROR("Failed to update WMTABLE!\n");
2418 * dm_hw_init() - Initialize DC device
2419 * @handle: The base driver device containing the amdgpu_dm device.
2421 * Initialize the &struct amdgpu_display_manager device. This involves calling
2422 * the initializers of each DM component, then populating the struct with them.
2424 * Although the function implies hardware initialization, both hardware and
2425 * software are initialized here. Splitting them out to their relevant init
2426 * hooks is a future TODO item.
2428 * Some notable things that are initialized here:
2430 * - Display Core, both software and hardware
2431 * - DC modules that we need (freesync and color management)
2432 * - DRM software states
2433 * - Interrupt sources and handlers
2435 * - Debug FS entries, if enabled
2437 static int dm_hw_init(void *handle)
2439 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2440 /* Create DAL display manager */
2441 amdgpu_dm_init(adev);
2442 amdgpu_dm_hpd_init(adev);
2448 * dm_hw_fini() - Teardown DC device
2449 * @handle: The base driver device containing the amdgpu_dm device.
2451 * Teardown components within &struct amdgpu_display_manager that require
2452 * cleanup. This involves cleaning up the DRM device, DC, and any modules that
2453 * were loaded. Also flush IRQ workqueues and disable them.
2455 static int dm_hw_fini(void *handle)
2457 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2459 amdgpu_dm_hpd_fini(adev);
2461 amdgpu_dm_irq_fini(adev);
2462 amdgpu_dm_fini(adev);
2467 static void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev,
2468 struct dc_state *state, bool enable)
2470 enum dc_irq_source irq_source;
2471 struct amdgpu_crtc *acrtc;
2475 for (i = 0; i < state->stream_count; i++) {
2476 acrtc = get_crtc_by_otg_inst(
2477 adev, state->stream_status[i].primary_otg_inst);
2479 if (acrtc && state->stream_status[i].plane_count != 0) {
2480 irq_source = IRQ_TYPE_PFLIP + acrtc->otg_inst;
2481 rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
2482 DRM_DEBUG_VBL("crtc %d - vupdate irq %sabling: r=%d\n",
2483 acrtc->crtc_id, enable ? "en" : "dis", rc);
2485 DRM_WARN("Failed to %s pflip interrupts\n",
2486 enable ? "enable" : "disable");
2489 rc = amdgpu_dm_crtc_enable_vblank(&acrtc->base);
2491 DRM_WARN("Failed to enable vblank interrupts\n");
2493 amdgpu_dm_crtc_disable_vblank(&acrtc->base);
2501 static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc)
2503 struct dc_state *context = NULL;
2504 enum dc_status res = DC_ERROR_UNEXPECTED;
2506 struct dc_stream_state *del_streams[MAX_PIPES];
2507 int del_streams_count = 0;
2509 memset(del_streams, 0, sizeof(del_streams));
2511 context = dc_create_state(dc);
2512 if (context == NULL)
2513 goto context_alloc_fail;
2515 dc_resource_state_copy_construct_current(dc, context);
2517 /* First remove from context all streams */
2518 for (i = 0; i < context->stream_count; i++) {
2519 struct dc_stream_state *stream = context->streams[i];
2521 del_streams[del_streams_count++] = stream;
2524 /* Remove all planes for removed streams and then remove the streams */
2525 for (i = 0; i < del_streams_count; i++) {
2526 if (!dc_rem_all_planes_for_stream(dc, del_streams[i], context)) {
2527 res = DC_FAIL_DETACH_SURFACES;
2531 res = dc_remove_stream_from_ctx(dc, context, del_streams[i]);
2536 res = dc_commit_streams(dc, context->streams, context->stream_count);
2539 dc_release_state(context);
2545 static void hpd_rx_irq_work_suspend(struct amdgpu_display_manager *dm)
2549 if (dm->hpd_rx_offload_wq) {
2550 for (i = 0; i < dm->dc->caps.max_links; i++)
2551 flush_workqueue(dm->hpd_rx_offload_wq[i].wq);
2555 static int dm_suspend(void *handle)
2557 struct amdgpu_device *adev = handle;
2558 struct amdgpu_display_manager *dm = &adev->dm;
2561 if (amdgpu_in_reset(adev)) {
2562 mutex_lock(&dm->dc_lock);
2564 dc_allow_idle_optimizations(adev->dm.dc, false);
2566 dm->cached_dc_state = dc_copy_state(dm->dc->current_state);
2568 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false);
2570 amdgpu_dm_commit_zero_streams(dm->dc);
2572 amdgpu_dm_irq_suspend(adev);
2574 hpd_rx_irq_work_suspend(dm);
2579 WARN_ON(adev->dm.cached_state);
2580 adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev));
2582 s3_handle_mst(adev_to_drm(adev), true);
2584 amdgpu_dm_irq_suspend(adev);
2586 hpd_rx_irq_work_suspend(dm);
2588 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
2593 struct amdgpu_dm_connector *
2594 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
2595 struct drm_crtc *crtc)
2598 struct drm_connector_state *new_con_state;
2599 struct drm_connector *connector;
2600 struct drm_crtc *crtc_from_state;
2602 for_each_new_connector_in_state(state, connector, new_con_state, i) {
2603 crtc_from_state = new_con_state->crtc;
2605 if (crtc_from_state == crtc)
2606 return to_amdgpu_dm_connector(connector);
2612 static void emulated_link_detect(struct dc_link *link)
2614 struct dc_sink_init_data sink_init_data = { 0 };
2615 struct display_sink_capability sink_caps = { 0 };
2616 enum dc_edid_status edid_status;
2617 struct dc_context *dc_ctx = link->ctx;
2618 struct dc_sink *sink = NULL;
2619 struct dc_sink *prev_sink = NULL;
2621 link->type = dc_connection_none;
2622 prev_sink = link->local_sink;
2625 dc_sink_release(prev_sink);
2627 switch (link->connector_signal) {
2628 case SIGNAL_TYPE_HDMI_TYPE_A: {
2629 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2630 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
2634 case SIGNAL_TYPE_DVI_SINGLE_LINK: {
2635 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2636 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
2640 case SIGNAL_TYPE_DVI_DUAL_LINK: {
2641 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2642 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
2646 case SIGNAL_TYPE_LVDS: {
2647 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2648 sink_caps.signal = SIGNAL_TYPE_LVDS;
2652 case SIGNAL_TYPE_EDP: {
2653 sink_caps.transaction_type =
2654 DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
2655 sink_caps.signal = SIGNAL_TYPE_EDP;
2659 case SIGNAL_TYPE_DISPLAY_PORT: {
2660 sink_caps.transaction_type =
2661 DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
2662 sink_caps.signal = SIGNAL_TYPE_VIRTUAL;
2667 DC_ERROR("Invalid connector type! signal:%d\n",
2668 link->connector_signal);
2672 sink_init_data.link = link;
2673 sink_init_data.sink_signal = sink_caps.signal;
2675 sink = dc_sink_create(&sink_init_data);
2677 DC_ERROR("Failed to create sink!\n");
2681 /* dc_sink_create returns a new reference */
2682 link->local_sink = sink;
2684 edid_status = dm_helpers_read_local_edid(
2689 if (edid_status != EDID_OK)
2690 DC_ERROR("Failed to read EDID");
2694 static void dm_gpureset_commit_state(struct dc_state *dc_state,
2695 struct amdgpu_display_manager *dm)
2698 struct dc_surface_update surface_updates[MAX_SURFACES];
2699 struct dc_plane_info plane_infos[MAX_SURFACES];
2700 struct dc_scaling_info scaling_infos[MAX_SURFACES];
2701 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
2702 struct dc_stream_update stream_update;
2706 bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
2709 dm_error("Failed to allocate update bundle\n");
2713 for (k = 0; k < dc_state->stream_count; k++) {
2714 bundle->stream_update.stream = dc_state->streams[k];
2716 for (m = 0; m < dc_state->stream_status->plane_count; m++) {
2717 bundle->surface_updates[m].surface =
2718 dc_state->stream_status->plane_states[m];
2719 bundle->surface_updates[m].surface->force_full_update =
2723 update_planes_and_stream_adapter(dm->dc,
2725 dc_state->stream_status->plane_count,
2726 dc_state->streams[k],
2727 &bundle->stream_update,
2728 bundle->surface_updates);
2737 static int dm_resume(void *handle)
2739 struct amdgpu_device *adev = handle;
2740 struct drm_device *ddev = adev_to_drm(adev);
2741 struct amdgpu_display_manager *dm = &adev->dm;
2742 struct amdgpu_dm_connector *aconnector;
2743 struct drm_connector *connector;
2744 struct drm_connector_list_iter iter;
2745 struct drm_crtc *crtc;
2746 struct drm_crtc_state *new_crtc_state;
2747 struct dm_crtc_state *dm_new_crtc_state;
2748 struct drm_plane *plane;
2749 struct drm_plane_state *new_plane_state;
2750 struct dm_plane_state *dm_new_plane_state;
2751 struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state);
2752 enum dc_connection_type new_connection_type = dc_connection_none;
2753 struct dc_state *dc_state;
2756 if (amdgpu_in_reset(adev)) {
2757 dc_state = dm->cached_dc_state;
2760 * The dc->current_state is backed up into dm->cached_dc_state
2761 * before we commit 0 streams.
2763 * DC will clear link encoder assignments on the real state
2764 * but the changes won't propagate over to the copy we made
2765 * before the 0 streams commit.
2767 * DC expects that link encoder assignments are *not* valid
2768 * when committing a state, so as a workaround we can copy
2769 * off of the current state.
2771 * We lose the previous assignments, but we had already
2772 * commit 0 streams anyway.
2774 link_enc_cfg_copy(adev->dm.dc->current_state, dc_state);
2776 r = dm_dmub_hw_init(adev);
2778 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
2780 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
2783 amdgpu_dm_irq_resume_early(adev);
2785 for (i = 0; i < dc_state->stream_count; i++) {
2786 dc_state->streams[i]->mode_changed = true;
2787 for (j = 0; j < dc_state->stream_status[i].plane_count; j++) {
2788 dc_state->stream_status[i].plane_states[j]->update_flags.raw
2793 if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
2794 amdgpu_dm_outbox_init(adev);
2795 dc_enable_dmub_outbox(adev->dm.dc);
2798 WARN_ON(!dc_commit_streams(dm->dc, dc_state->streams, dc_state->stream_count));
2800 dm_gpureset_commit_state(dm->cached_dc_state, dm);
2802 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, true);
2804 dc_release_state(dm->cached_dc_state);
2805 dm->cached_dc_state = NULL;
2807 amdgpu_dm_irq_resume_late(adev);
2809 mutex_unlock(&dm->dc_lock);
2813 /* Recreate dc_state - DC invalidates it when setting power state to S3. */
2814 dc_release_state(dm_state->context);
2815 dm_state->context = dc_create_state(dm->dc);
2816 /* TODO: Remove dc_state->dccg, use dc->dccg directly. */
2817 dc_resource_state_construct(dm->dc, dm_state->context);
2819 /* Before powering on DC we need to re-initialize DMUB. */
2820 dm_dmub_hw_resume(adev);
2822 /* Re-enable outbox interrupts for DPIA. */
2823 if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
2824 amdgpu_dm_outbox_init(adev);
2825 dc_enable_dmub_outbox(adev->dm.dc);
2828 /* power on hardware */
2829 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
2831 /* program HPD filter */
2835 * early enable HPD Rx IRQ, should be done before set mode as short
2836 * pulse interrupts are used for MST
2838 amdgpu_dm_irq_resume_early(adev);
2840 /* On resume we need to rewrite the MSTM control bits to enable MST*/
2841 s3_handle_mst(ddev, false);
2844 drm_connector_list_iter_begin(ddev, &iter);
2845 drm_for_each_connector_iter(connector, &iter) {
2846 aconnector = to_amdgpu_dm_connector(connector);
2848 if (!aconnector->dc_link)
2852 * this is the case when traversing through already created
2853 * MST connectors, should be skipped
2855 if (aconnector->dc_link->type == dc_connection_mst_branch)
2858 mutex_lock(&aconnector->hpd_lock);
2859 if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type))
2860 DRM_ERROR("KMS: Failed to detect connector\n");
2862 if (aconnector->base.force && new_connection_type == dc_connection_none) {
2863 emulated_link_detect(aconnector->dc_link);
2865 mutex_lock(&dm->dc_lock);
2866 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
2867 mutex_unlock(&dm->dc_lock);
2870 if (aconnector->fake_enable && aconnector->dc_link->local_sink)
2871 aconnector->fake_enable = false;
2873 if (aconnector->dc_sink)
2874 dc_sink_release(aconnector->dc_sink);
2875 aconnector->dc_sink = NULL;
2876 amdgpu_dm_update_connector_after_detect(aconnector);
2877 mutex_unlock(&aconnector->hpd_lock);
2879 drm_connector_list_iter_end(&iter);
2881 /* Force mode set in atomic commit */
2882 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)
2883 new_crtc_state->active_changed = true;
2886 * atomic_check is expected to create the dc states. We need to release
2887 * them here, since they were duplicated as part of the suspend
2890 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {
2891 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
2892 if (dm_new_crtc_state->stream) {
2893 WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
2894 dc_stream_release(dm_new_crtc_state->stream);
2895 dm_new_crtc_state->stream = NULL;
2899 for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) {
2900 dm_new_plane_state = to_dm_plane_state(new_plane_state);
2901 if (dm_new_plane_state->dc_state) {
2902 WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
2903 dc_plane_state_release(dm_new_plane_state->dc_state);
2904 dm_new_plane_state->dc_state = NULL;
2908 drm_atomic_helper_resume(ddev, dm->cached_state);
2910 dm->cached_state = NULL;
2912 amdgpu_dm_irq_resume_late(adev);
2914 amdgpu_dm_smu_write_watermarks_table(adev);
2922 * DM (and consequently DC) is registered in the amdgpu base driver as a IP
2923 * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to
2924 * the base driver's device list to be initialized and torn down accordingly.
2926 * The functions to do so are provided as hooks in &struct amd_ip_funcs.
2929 static const struct amd_ip_funcs amdgpu_dm_funcs = {
2931 .early_init = dm_early_init,
2932 .late_init = dm_late_init,
2933 .sw_init = dm_sw_init,
2934 .sw_fini = dm_sw_fini,
2935 .early_fini = amdgpu_dm_early_fini,
2936 .hw_init = dm_hw_init,
2937 .hw_fini = dm_hw_fini,
2938 .suspend = dm_suspend,
2939 .resume = dm_resume,
2940 .is_idle = dm_is_idle,
2941 .wait_for_idle = dm_wait_for_idle,
2942 .check_soft_reset = dm_check_soft_reset,
2943 .soft_reset = dm_soft_reset,
2944 .set_clockgating_state = dm_set_clockgating_state,
2945 .set_powergating_state = dm_set_powergating_state,
2948 const struct amdgpu_ip_block_version dm_ip_block =
2950 .type = AMD_IP_BLOCK_TYPE_DCE,
2954 .funcs = &amdgpu_dm_funcs,
2964 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
2965 .fb_create = amdgpu_display_user_framebuffer_create,
2966 .get_format_info = amdgpu_dm_plane_get_format_info,
2967 .atomic_check = amdgpu_dm_atomic_check,
2968 .atomic_commit = drm_atomic_helper_commit,
2971 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
2972 .atomic_commit_tail = amdgpu_dm_atomic_commit_tail,
2973 .atomic_commit_setup = drm_dp_mst_atomic_setup_commit,
2976 static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector)
2978 struct amdgpu_dm_backlight_caps *caps;
2979 struct amdgpu_display_manager *dm;
2980 struct drm_connector *conn_base;
2981 struct amdgpu_device *adev;
2982 struct dc_link *link = NULL;
2983 struct drm_luminance_range_info *luminance_range;
2986 if (!aconnector || !aconnector->dc_link)
2989 link = aconnector->dc_link;
2990 if (link->connector_signal != SIGNAL_TYPE_EDP)
2993 conn_base = &aconnector->base;
2994 adev = drm_to_adev(conn_base->dev);
2996 for (i = 0; i < dm->num_of_edps; i++) {
2997 if (link == dm->backlight_link[i])
3000 if (i >= dm->num_of_edps)
3002 caps = &dm->backlight_caps[i];
3003 caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps;
3004 caps->aux_support = false;
3006 if (caps->ext_caps->bits.oled == 1 /*||
3007 caps->ext_caps->bits.sdr_aux_backlight_control == 1 ||
3008 caps->ext_caps->bits.hdr_aux_backlight_control == 1*/)
3009 caps->aux_support = true;
3011 if (amdgpu_backlight == 0)
3012 caps->aux_support = false;
3013 else if (amdgpu_backlight == 1)
3014 caps->aux_support = true;
3016 luminance_range = &conn_base->display_info.luminance_range;
3018 if (luminance_range->max_luminance) {
3019 caps->aux_min_input_signal = luminance_range->min_luminance;
3020 caps->aux_max_input_signal = luminance_range->max_luminance;
3022 caps->aux_min_input_signal = 0;
3023 caps->aux_max_input_signal = 512;
3027 void amdgpu_dm_update_connector_after_detect(
3028 struct amdgpu_dm_connector *aconnector)
3030 struct drm_connector *connector = &aconnector->base;
3031 struct drm_device *dev = connector->dev;
3032 struct dc_sink *sink;
3034 /* MST handled by drm_mst framework */
3035 if (aconnector->mst_mgr.mst_state == true)
3038 sink = aconnector->dc_link->local_sink;
3040 dc_sink_retain(sink);
3043 * Edid mgmt connector gets first update only in mode_valid hook and then
3044 * the connector sink is set to either fake or physical sink depends on link status.
3045 * Skip if already done during boot.
3047 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
3048 && aconnector->dc_em_sink) {
3051 * For S3 resume with headless use eml_sink to fake stream
3052 * because on resume connector->sink is set to NULL
3054 mutex_lock(&dev->mode_config.mutex);
3057 if (aconnector->dc_sink) {
3058 amdgpu_dm_update_freesync_caps(connector, NULL);
3060 * retain and release below are used to
3061 * bump up refcount for sink because the link doesn't point
3062 * to it anymore after disconnect, so on next crtc to connector
3063 * reshuffle by UMD we will get into unwanted dc_sink release
3065 dc_sink_release(aconnector->dc_sink);
3067 aconnector->dc_sink = sink;
3068 dc_sink_retain(aconnector->dc_sink);
3069 amdgpu_dm_update_freesync_caps(connector,
3072 amdgpu_dm_update_freesync_caps(connector, NULL);
3073 if (!aconnector->dc_sink) {
3074 aconnector->dc_sink = aconnector->dc_em_sink;
3075 dc_sink_retain(aconnector->dc_sink);
3079 mutex_unlock(&dev->mode_config.mutex);
3082 dc_sink_release(sink);
3087 * TODO: temporary guard to look for proper fix
3088 * if this sink is MST sink, we should not do anything
3090 if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
3091 dc_sink_release(sink);
3095 if (aconnector->dc_sink == sink) {
3097 * We got a DP short pulse (Link Loss, DP CTS, etc...).
3100 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
3101 aconnector->connector_id);
3103 dc_sink_release(sink);
3107 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
3108 aconnector->connector_id, aconnector->dc_sink, sink);
3110 mutex_lock(&dev->mode_config.mutex);
3113 * 1. Update status of the drm connector
3114 * 2. Send an event and let userspace tell us what to do
3118 * TODO: check if we still need the S3 mode update workaround.
3119 * If yes, put it here.
3121 if (aconnector->dc_sink) {
3122 amdgpu_dm_update_freesync_caps(connector, NULL);
3123 dc_sink_release(aconnector->dc_sink);
3126 aconnector->dc_sink = sink;
3127 dc_sink_retain(aconnector->dc_sink);
3128 if (sink->dc_edid.length == 0) {
3129 aconnector->edid = NULL;
3130 if (aconnector->dc_link->aux_mode) {
3131 drm_dp_cec_unset_edid(
3132 &aconnector->dm_dp_aux.aux);
3136 (struct edid *)sink->dc_edid.raw_edid;
3138 if (aconnector->dc_link->aux_mode)
3139 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,
3143 aconnector->timing_requested = kzalloc(sizeof(struct dc_crtc_timing), GFP_KERNEL);
3144 if (!aconnector->timing_requested)
3145 dm_error("%s: failed to create aconnector->requested_timing\n", __func__);
3147 drm_connector_update_edid_property(connector, aconnector->edid);
3148 amdgpu_dm_update_freesync_caps(connector, aconnector->edid);
3149 update_connector_ext_caps(aconnector);
3151 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
3152 amdgpu_dm_update_freesync_caps(connector, NULL);
3153 drm_connector_update_edid_property(connector, NULL);
3154 aconnector->num_modes = 0;
3155 dc_sink_release(aconnector->dc_sink);
3156 aconnector->dc_sink = NULL;
3157 aconnector->edid = NULL;
3158 kfree(aconnector->timing_requested);
3159 aconnector->timing_requested = NULL;
3160 /* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */
3161 if (connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
3162 connector->state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
3165 mutex_unlock(&dev->mode_config.mutex);
3167 update_subconnector_property(aconnector);
3170 dc_sink_release(sink);
3173 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector)
3175 struct drm_connector *connector = &aconnector->base;
3176 struct drm_device *dev = connector->dev;
3177 enum dc_connection_type new_connection_type = dc_connection_none;
3178 struct amdgpu_device *adev = drm_to_adev(dev);
3179 struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
3182 if (adev->dm.disable_hpd_irq)
3186 * In case of failure or MST no need to update connector status or notify the OS
3187 * since (for MST case) MST does this in its own context.
3189 mutex_lock(&aconnector->hpd_lock);
3191 if (adev->dm.hdcp_workqueue) {
3192 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
3193 dm_con_state->update_hdcp = true;
3195 if (aconnector->fake_enable)
3196 aconnector->fake_enable = false;
3198 aconnector->timing_changed = false;
3200 if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type))
3201 DRM_ERROR("KMS: Failed to detect connector\n");
3203 if (aconnector->base.force && new_connection_type == dc_connection_none) {
3204 emulated_link_detect(aconnector->dc_link);
3206 drm_modeset_lock_all(dev);
3207 dm_restore_drm_connector_state(dev, connector);
3208 drm_modeset_unlock_all(dev);
3210 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
3211 drm_kms_helper_connector_hotplug_event(connector);
3213 mutex_lock(&adev->dm.dc_lock);
3214 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
3215 mutex_unlock(&adev->dm.dc_lock);
3217 amdgpu_dm_update_connector_after_detect(aconnector);
3219 drm_modeset_lock_all(dev);
3220 dm_restore_drm_connector_state(dev, connector);
3221 drm_modeset_unlock_all(dev);
3223 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
3224 drm_kms_helper_connector_hotplug_event(connector);
3227 mutex_unlock(&aconnector->hpd_lock);
3231 static void handle_hpd_irq(void *param)
3233 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
3235 handle_hpd_irq_helper(aconnector);
3239 static void dm_handle_mst_sideband_msg(struct amdgpu_dm_connector *aconnector)
3241 u8 esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
3243 bool new_irq_handled = false;
3245 int dpcd_bytes_to_read;
3247 const int max_process_count = 30;
3248 int process_count = 0;
3250 const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
3252 if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
3253 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
3254 /* DPCD 0x200 - 0x201 for downstream IRQ */
3255 dpcd_addr = DP_SINK_COUNT;
3257 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
3258 /* DPCD 0x2002 - 0x2005 for downstream IRQ */
3259 dpcd_addr = DP_SINK_COUNT_ESI;
3262 dret = drm_dp_dpcd_read(
3263 &aconnector->dm_dp_aux.aux,
3266 dpcd_bytes_to_read);
3268 while (dret == dpcd_bytes_to_read &&
3269 process_count < max_process_count) {
3275 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3276 /* handle HPD short pulse irq */
3277 if (aconnector->mst_mgr.mst_state)
3279 &aconnector->mst_mgr,
3283 if (new_irq_handled) {
3284 /* ACK at DPCD to notify down stream */
3285 const int ack_dpcd_bytes_to_write =
3286 dpcd_bytes_to_read - 1;
3288 for (retry = 0; retry < 3; retry++) {
3291 wret = drm_dp_dpcd_write(
3292 &aconnector->dm_dp_aux.aux,
3295 ack_dpcd_bytes_to_write);
3296 if (wret == ack_dpcd_bytes_to_write)
3300 /* check if there is new irq to be handled */
3301 dret = drm_dp_dpcd_read(
3302 &aconnector->dm_dp_aux.aux,
3305 dpcd_bytes_to_read);
3307 new_irq_handled = false;
3313 if (process_count == max_process_count)
3314 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
3317 static void schedule_hpd_rx_offload_work(struct hpd_rx_irq_offload_work_queue *offload_wq,
3318 union hpd_irq_data hpd_irq_data)
3320 struct hpd_rx_irq_offload_work *offload_work =
3321 kzalloc(sizeof(*offload_work), GFP_KERNEL);
3323 if (!offload_work) {
3324 DRM_ERROR("Failed to allocate hpd_rx_irq_offload_work.\n");
3328 INIT_WORK(&offload_work->work, dm_handle_hpd_rx_offload_work);
3329 offload_work->data = hpd_irq_data;
3330 offload_work->offload_wq = offload_wq;
3332 queue_work(offload_wq->wq, &offload_work->work);
3333 DRM_DEBUG_KMS("queue work to handle hpd_rx offload work");
3336 static void handle_hpd_rx_irq(void *param)
3338 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
3339 struct drm_connector *connector = &aconnector->base;
3340 struct drm_device *dev = connector->dev;
3341 struct dc_link *dc_link = aconnector->dc_link;
3342 bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
3343 bool result = false;
3344 enum dc_connection_type new_connection_type = dc_connection_none;
3345 struct amdgpu_device *adev = drm_to_adev(dev);
3346 union hpd_irq_data hpd_irq_data;
3347 bool link_loss = false;
3348 bool has_left_work = false;
3349 int idx = dc_link->link_index;
3350 struct hpd_rx_irq_offload_work_queue *offload_wq = &adev->dm.hpd_rx_offload_wq[idx];
3352 memset(&hpd_irq_data, 0, sizeof(hpd_irq_data));
3354 if (adev->dm.disable_hpd_irq)
3358 * TODO:Temporary add mutex to protect hpd interrupt not have a gpio
3359 * conflict, after implement i2c helper, this mutex should be
3362 mutex_lock(&aconnector->hpd_lock);
3364 result = dc_link_handle_hpd_rx_irq(dc_link, &hpd_irq_data,
3365 &link_loss, true, &has_left_work);
3370 if (hpd_irq_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
3371 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3375 if (dc_link_dp_allow_hpd_rx_irq(dc_link)) {
3376 if (hpd_irq_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY ||
3377 hpd_irq_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) {
3378 dm_handle_mst_sideband_msg(aconnector);
3385 spin_lock(&offload_wq->offload_lock);
3386 skip = offload_wq->is_handling_link_loss;
3389 offload_wq->is_handling_link_loss = true;
3391 spin_unlock(&offload_wq->offload_lock);
3394 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3401 if (result && !is_mst_root_connector) {
3402 /* Downstream Port status changed. */
3403 if (!dc_link_detect_connection_type(dc_link, &new_connection_type))
3404 DRM_ERROR("KMS: Failed to detect connector\n");
3406 if (aconnector->base.force && new_connection_type == dc_connection_none) {
3407 emulated_link_detect(dc_link);
3409 if (aconnector->fake_enable)
3410 aconnector->fake_enable = false;
3412 amdgpu_dm_update_connector_after_detect(aconnector);
3415 drm_modeset_lock_all(dev);
3416 dm_restore_drm_connector_state(dev, connector);
3417 drm_modeset_unlock_all(dev);
3419 drm_kms_helper_connector_hotplug_event(connector);
3423 mutex_lock(&adev->dm.dc_lock);
3424 ret = dc_link_detect(dc_link, DETECT_REASON_HPDRX);
3425 mutex_unlock(&adev->dm.dc_lock);
3428 if (aconnector->fake_enable)
3429 aconnector->fake_enable = false;
3431 amdgpu_dm_update_connector_after_detect(aconnector);
3433 drm_modeset_lock_all(dev);
3434 dm_restore_drm_connector_state(dev, connector);
3435 drm_modeset_unlock_all(dev);
3437 drm_kms_helper_connector_hotplug_event(connector);
3441 if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ) {
3442 if (adev->dm.hdcp_workqueue)
3443 hdcp_handle_cpirq(adev->dm.hdcp_workqueue, aconnector->base.index);
3446 if (dc_link->type != dc_connection_mst_branch)
3447 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux);
3449 mutex_unlock(&aconnector->hpd_lock);
3452 static void register_hpd_handlers(struct amdgpu_device *adev)
3454 struct drm_device *dev = adev_to_drm(adev);
3455 struct drm_connector *connector;
3456 struct amdgpu_dm_connector *aconnector;
3457 const struct dc_link *dc_link;
3458 struct dc_interrupt_params int_params = {0};
3460 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3461 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3463 list_for_each_entry(connector,
3464 &dev->mode_config.connector_list, head) {
3466 aconnector = to_amdgpu_dm_connector(connector);
3467 dc_link = aconnector->dc_link;
3469 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
3470 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3471 int_params.irq_source = dc_link->irq_source_hpd;
3473 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3475 (void *) aconnector);
3478 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
3480 /* Also register for DP short pulse (hpd_rx). */
3481 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3482 int_params.irq_source = dc_link->irq_source_hpd_rx;
3484 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3486 (void *) aconnector);
3488 if (adev->dm.hpd_rx_offload_wq)
3489 adev->dm.hpd_rx_offload_wq[dc_link->link_index].aconnector =
3495 #if defined(CONFIG_DRM_AMD_DC_SI)
3496 /* Register IRQ sources and initialize IRQ callbacks */
3497 static int dce60_register_irq_handlers(struct amdgpu_device *adev)
3499 struct dc *dc = adev->dm.dc;
3500 struct common_irq_params *c_irq_params;
3501 struct dc_interrupt_params int_params = {0};
3504 unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
3506 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3507 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3510 * Actions of amdgpu_irq_add_id():
3511 * 1. Register a set() function with base driver.
3512 * Base driver will call set() function to enable/disable an
3513 * interrupt in DC hardware.
3514 * 2. Register amdgpu_dm_irq_handler().
3515 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3516 * coming from DC hardware.
3517 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3518 * for acknowledging and handling. */
3520 /* Use VBLANK interrupt */
3521 for (i = 0; i < adev->mode_info.num_crtc; i++) {
3522 r = amdgpu_irq_add_id(adev, client_id, i+1 , &adev->crtc_irq);
3524 DRM_ERROR("Failed to add crtc irq id!\n");
3528 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3529 int_params.irq_source =
3530 dc_interrupt_to_irq_source(dc, i+1 , 0);
3532 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3534 c_irq_params->adev = adev;
3535 c_irq_params->irq_src = int_params.irq_source;
3537 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3538 dm_crtc_high_irq, c_irq_params);
3541 /* Use GRPH_PFLIP interrupt */
3542 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
3543 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
3544 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
3546 DRM_ERROR("Failed to add page flip irq id!\n");
3550 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3551 int_params.irq_source =
3552 dc_interrupt_to_irq_source(dc, i, 0);
3554 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3556 c_irq_params->adev = adev;
3557 c_irq_params->irq_src = int_params.irq_source;
3559 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3560 dm_pflip_high_irq, c_irq_params);
3565 r = amdgpu_irq_add_id(adev, client_id,
3566 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
3568 DRM_ERROR("Failed to add hpd irq id!\n");
3572 register_hpd_handlers(adev);
3578 /* Register IRQ sources and initialize IRQ callbacks */
3579 static int dce110_register_irq_handlers(struct amdgpu_device *adev)
3581 struct dc *dc = adev->dm.dc;
3582 struct common_irq_params *c_irq_params;
3583 struct dc_interrupt_params int_params = {0};
3586 unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
3588 if (adev->family >= AMDGPU_FAMILY_AI)
3589 client_id = SOC15_IH_CLIENTID_DCE;
3591 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3592 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3595 * Actions of amdgpu_irq_add_id():
3596 * 1. Register a set() function with base driver.
3597 * Base driver will call set() function to enable/disable an
3598 * interrupt in DC hardware.
3599 * 2. Register amdgpu_dm_irq_handler().
3600 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3601 * coming from DC hardware.
3602 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3603 * for acknowledging and handling. */
3605 /* Use VBLANK interrupt */
3606 for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
3607 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
3609 DRM_ERROR("Failed to add crtc irq id!\n");
3613 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3614 int_params.irq_source =
3615 dc_interrupt_to_irq_source(dc, i, 0);
3617 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3619 c_irq_params->adev = adev;
3620 c_irq_params->irq_src = int_params.irq_source;
3622 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3623 dm_crtc_high_irq, c_irq_params);
3626 /* Use VUPDATE interrupt */
3627 for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) {
3628 r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq);
3630 DRM_ERROR("Failed to add vupdate irq id!\n");
3634 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3635 int_params.irq_source =
3636 dc_interrupt_to_irq_source(dc, i, 0);
3638 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
3640 c_irq_params->adev = adev;
3641 c_irq_params->irq_src = int_params.irq_source;
3643 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3644 dm_vupdate_high_irq, c_irq_params);
3647 /* Use GRPH_PFLIP interrupt */
3648 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
3649 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
3650 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
3652 DRM_ERROR("Failed to add page flip irq id!\n");
3656 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3657 int_params.irq_source =
3658 dc_interrupt_to_irq_source(dc, i, 0);
3660 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3662 c_irq_params->adev = adev;
3663 c_irq_params->irq_src = int_params.irq_source;
3665 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3666 dm_pflip_high_irq, c_irq_params);
3671 r = amdgpu_irq_add_id(adev, client_id,
3672 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
3674 DRM_ERROR("Failed to add hpd irq id!\n");
3678 register_hpd_handlers(adev);
3683 /* Register IRQ sources and initialize IRQ callbacks */
3684 static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
3686 struct dc *dc = adev->dm.dc;
3687 struct common_irq_params *c_irq_params;
3688 struct dc_interrupt_params int_params = {0};
3691 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
3692 static const unsigned int vrtl_int_srcid[] = {
3693 DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL,
3694 DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL,
3695 DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL,
3696 DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL,
3697 DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL,
3698 DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL
3702 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3703 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3706 * Actions of amdgpu_irq_add_id():
3707 * 1. Register a set() function with base driver.
3708 * Base driver will call set() function to enable/disable an
3709 * interrupt in DC hardware.
3710 * 2. Register amdgpu_dm_irq_handler().
3711 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3712 * coming from DC hardware.
3713 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3714 * for acknowledging and handling.
3717 /* Use VSTARTUP interrupt */
3718 for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
3719 i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
3721 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);
3724 DRM_ERROR("Failed to add crtc irq id!\n");
3728 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3729 int_params.irq_source =
3730 dc_interrupt_to_irq_source(dc, i, 0);
3732 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3734 c_irq_params->adev = adev;
3735 c_irq_params->irq_src = int_params.irq_source;
3737 amdgpu_dm_irq_register_interrupt(
3738 adev, &int_params, dm_crtc_high_irq, c_irq_params);
3741 /* Use otg vertical line interrupt */
3742 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
3743 for (i = 0; i <= adev->mode_info.num_crtc - 1; i++) {
3744 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE,
3745 vrtl_int_srcid[i], &adev->vline0_irq);
3748 DRM_ERROR("Failed to add vline0 irq id!\n");
3752 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3753 int_params.irq_source =
3754 dc_interrupt_to_irq_source(dc, vrtl_int_srcid[i], 0);
3756 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID) {
3757 DRM_ERROR("Failed to register vline0 irq %d!\n", vrtl_int_srcid[i]);
3761 c_irq_params = &adev->dm.vline0_params[int_params.irq_source
3762 - DC_IRQ_SOURCE_DC1_VLINE0];
3764 c_irq_params->adev = adev;
3765 c_irq_params->irq_src = int_params.irq_source;
3767 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3768 dm_dcn_vertical_interrupt0_high_irq, c_irq_params);
3772 /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to
3773 * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx
3774 * to trigger at end of each vblank, regardless of state of the lock,
3775 * matching DCE behaviour.
3777 for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT;
3778 i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1;
3780 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq);
3783 DRM_ERROR("Failed to add vupdate irq id!\n");
3787 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3788 int_params.irq_source =
3789 dc_interrupt_to_irq_source(dc, i, 0);
3791 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
3793 c_irq_params->adev = adev;
3794 c_irq_params->irq_src = int_params.irq_source;
3796 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3797 dm_vupdate_high_irq, c_irq_params);
3800 /* Use GRPH_PFLIP interrupt */
3801 for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
3802 i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + dc->caps.max_otg_num - 1;
3804 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
3806 DRM_ERROR("Failed to add page flip irq id!\n");
3810 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3811 int_params.irq_source =
3812 dc_interrupt_to_irq_source(dc, i, 0);
3814 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3816 c_irq_params->adev = adev;
3817 c_irq_params->irq_src = int_params.irq_source;
3819 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3820 dm_pflip_high_irq, c_irq_params);
3825 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
3828 DRM_ERROR("Failed to add hpd irq id!\n");
3832 register_hpd_handlers(adev);
3836 /* Register Outbox IRQ sources and initialize IRQ callbacks */
3837 static int register_outbox_irq_handlers(struct amdgpu_device *adev)
3839 struct dc *dc = adev->dm.dc;
3840 struct common_irq_params *c_irq_params;
3841 struct dc_interrupt_params int_params = {0};
3844 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3845 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3847 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT,
3848 &adev->dmub_outbox_irq);
3850 DRM_ERROR("Failed to add outbox irq id!\n");
3854 if (dc->ctx->dmub_srv) {
3855 i = DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT;
3856 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3857 int_params.irq_source =
3858 dc_interrupt_to_irq_source(dc, i, 0);
3860 c_irq_params = &adev->dm.dmub_outbox_params[0];
3862 c_irq_params->adev = adev;
3863 c_irq_params->irq_src = int_params.irq_source;
3865 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3866 dm_dmub_outbox1_low_irq, c_irq_params);
3873 * Acquires the lock for the atomic state object and returns
3874 * the new atomic state.
3876 * This should only be called during atomic check.
3878 int dm_atomic_get_state(struct drm_atomic_state *state,
3879 struct dm_atomic_state **dm_state)
3881 struct drm_device *dev = state->dev;
3882 struct amdgpu_device *adev = drm_to_adev(dev);
3883 struct amdgpu_display_manager *dm = &adev->dm;
3884 struct drm_private_state *priv_state;
3889 priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj);
3890 if (IS_ERR(priv_state))
3891 return PTR_ERR(priv_state);
3893 *dm_state = to_dm_atomic_state(priv_state);
3898 static struct dm_atomic_state *
3899 dm_atomic_get_new_state(struct drm_atomic_state *state)
3901 struct drm_device *dev = state->dev;
3902 struct amdgpu_device *adev = drm_to_adev(dev);
3903 struct amdgpu_display_manager *dm = &adev->dm;
3904 struct drm_private_obj *obj;
3905 struct drm_private_state *new_obj_state;
3908 for_each_new_private_obj_in_state(state, obj, new_obj_state, i) {
3909 if (obj->funcs == dm->atomic_obj.funcs)
3910 return to_dm_atomic_state(new_obj_state);
3916 static struct drm_private_state *
3917 dm_atomic_duplicate_state(struct drm_private_obj *obj)
3919 struct dm_atomic_state *old_state, *new_state;
3921 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
3925 __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base);
3927 old_state = to_dm_atomic_state(obj->state);
3929 if (old_state && old_state->context)
3930 new_state->context = dc_copy_state(old_state->context);
3932 if (!new_state->context) {
3937 return &new_state->base;
3940 static void dm_atomic_destroy_state(struct drm_private_obj *obj,
3941 struct drm_private_state *state)
3943 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
3945 if (dm_state && dm_state->context)
3946 dc_release_state(dm_state->context);
3951 static struct drm_private_state_funcs dm_atomic_state_funcs = {
3952 .atomic_duplicate_state = dm_atomic_duplicate_state,
3953 .atomic_destroy_state = dm_atomic_destroy_state,
3956 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
3958 struct dm_atomic_state *state;
3961 adev->mode_info.mode_config_initialized = true;
3963 adev_to_drm(adev)->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
3964 adev_to_drm(adev)->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
3966 adev_to_drm(adev)->mode_config.max_width = 16384;
3967 adev_to_drm(adev)->mode_config.max_height = 16384;
3969 adev_to_drm(adev)->mode_config.preferred_depth = 24;
3970 if (adev->asic_type == CHIP_HAWAII)
3971 /* disable prefer shadow for now due to hibernation issues */
3972 adev_to_drm(adev)->mode_config.prefer_shadow = 0;
3974 adev_to_drm(adev)->mode_config.prefer_shadow = 1;
3975 /* indicates support for immediate flip */
3976 adev_to_drm(adev)->mode_config.async_page_flip = true;
3978 state = kzalloc(sizeof(*state), GFP_KERNEL);
3982 state->context = dc_create_state(adev->dm.dc);
3983 if (!state->context) {
3988 dc_resource_state_copy_construct_current(adev->dm.dc, state->context);
3990 drm_atomic_private_obj_init(adev_to_drm(adev),
3991 &adev->dm.atomic_obj,
3993 &dm_atomic_state_funcs);
3995 r = amdgpu_display_modeset_create_props(adev);
3997 dc_release_state(state->context);
4002 r = amdgpu_dm_audio_init(adev);
4004 dc_release_state(state->context);
4012 #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12
4013 #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255
4014 #define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50
4016 static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm,
4019 #if defined(CONFIG_ACPI)
4020 struct amdgpu_dm_backlight_caps caps;
4022 memset(&caps, 0, sizeof(caps));
4024 if (dm->backlight_caps[bl_idx].caps_valid)
4027 amdgpu_acpi_get_backlight_caps(&caps);
4028 if (caps.caps_valid) {
4029 dm->backlight_caps[bl_idx].caps_valid = true;
4030 if (caps.aux_support)
4032 dm->backlight_caps[bl_idx].min_input_signal = caps.min_input_signal;
4033 dm->backlight_caps[bl_idx].max_input_signal = caps.max_input_signal;
4035 dm->backlight_caps[bl_idx].min_input_signal =
4036 AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
4037 dm->backlight_caps[bl_idx].max_input_signal =
4038 AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
4041 if (dm->backlight_caps[bl_idx].aux_support)
4044 dm->backlight_caps[bl_idx].min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
4045 dm->backlight_caps[bl_idx].max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
4049 static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps,
4050 unsigned *min, unsigned *max)
4055 if (caps->aux_support) {
4056 // Firmware limits are in nits, DC API wants millinits.
4057 *max = 1000 * caps->aux_max_input_signal;
4058 *min = 1000 * caps->aux_min_input_signal;
4060 // Firmware limits are 8-bit, PWM control is 16-bit.
4061 *max = 0x101 * caps->max_input_signal;
4062 *min = 0x101 * caps->min_input_signal;
4067 static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *caps,
4068 uint32_t brightness)
4072 if (!get_brightness_range(caps, &min, &max))
4075 // Rescale 0..255 to min..max
4076 return min + DIV_ROUND_CLOSEST((max - min) * brightness,
4077 AMDGPU_MAX_BL_LEVEL);
4080 static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *caps,
4081 uint32_t brightness)
4085 if (!get_brightness_range(caps, &min, &max))
4088 if (brightness < min)
4090 // Rescale min..max to 0..255
4091 return DIV_ROUND_CLOSEST(AMDGPU_MAX_BL_LEVEL * (brightness - min),
4095 static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm,
4097 u32 user_brightness)
4099 struct amdgpu_dm_backlight_caps caps;
4100 struct dc_link *link;
4104 amdgpu_dm_update_backlight_caps(dm, bl_idx);
4105 caps = dm->backlight_caps[bl_idx];
4107 dm->brightness[bl_idx] = user_brightness;
4108 /* update scratch register */
4110 amdgpu_atombios_scratch_regs_set_backlight_level(dm->adev, dm->brightness[bl_idx]);
4111 brightness = convert_brightness_from_user(&caps, dm->brightness[bl_idx]);
4112 link = (struct dc_link *)dm->backlight_link[bl_idx];
4114 /* Change brightness based on AUX property */
4115 if (caps.aux_support) {
4116 rc = dc_link_set_backlight_level_nits(link, true, brightness,
4117 AUX_BL_DEFAULT_TRANSITION_TIME_MS);
4119 DRM_DEBUG("DM: Failed to update backlight via AUX on eDP[%d]\n", bl_idx);
4121 rc = dc_link_set_backlight_level(link, brightness, 0);
4123 DRM_DEBUG("DM: Failed to update backlight on eDP[%d]\n", bl_idx);
4127 dm->actual_brightness[bl_idx] = user_brightness;
4130 static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
4132 struct amdgpu_display_manager *dm = bl_get_data(bd);
4135 for (i = 0; i < dm->num_of_edps; i++) {
4136 if (bd == dm->backlight_dev[i])
4139 if (i >= AMDGPU_DM_MAX_NUM_EDP)
4141 amdgpu_dm_backlight_set_level(dm, i, bd->props.brightness);
4146 static u32 amdgpu_dm_backlight_get_level(struct amdgpu_display_manager *dm,
4149 struct amdgpu_dm_backlight_caps caps;
4150 struct dc_link *link = (struct dc_link *)dm->backlight_link[bl_idx];
4152 amdgpu_dm_update_backlight_caps(dm, bl_idx);
4153 caps = dm->backlight_caps[bl_idx];
4155 if (caps.aux_support) {
4159 rc = dc_link_get_backlight_level_nits(link, &avg, &peak);
4161 return dm->brightness[bl_idx];
4162 return convert_brightness_to_user(&caps, avg);
4164 int ret = dc_link_get_backlight_level(link);
4166 if (ret == DC_ERROR_UNEXPECTED)
4167 return dm->brightness[bl_idx];
4168 return convert_brightness_to_user(&caps, ret);
4172 static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
4174 struct amdgpu_display_manager *dm = bl_get_data(bd);
4177 for (i = 0; i < dm->num_of_edps; i++) {
4178 if (bd == dm->backlight_dev[i])
4181 if (i >= AMDGPU_DM_MAX_NUM_EDP)
4183 return amdgpu_dm_backlight_get_level(dm, i);
4186 static const struct backlight_ops amdgpu_dm_backlight_ops = {
4187 .options = BL_CORE_SUSPENDRESUME,
4188 .get_brightness = amdgpu_dm_backlight_get_brightness,
4189 .update_status = amdgpu_dm_backlight_update_status,
4193 amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm)
4196 struct backlight_properties props = { 0 };
4198 amdgpu_dm_update_backlight_caps(dm, dm->num_of_edps);
4199 dm->brightness[dm->num_of_edps] = AMDGPU_MAX_BL_LEVEL;
4201 if (!acpi_video_backlight_use_native()) {
4202 drm_info(adev_to_drm(dm->adev), "Skipping amdgpu DM backlight registration\n");
4203 /* Try registering an ACPI video backlight device instead. */
4204 acpi_video_register_backlight();
4208 props.max_brightness = AMDGPU_MAX_BL_LEVEL;
4209 props.brightness = AMDGPU_MAX_BL_LEVEL;
4210 props.type = BACKLIGHT_RAW;
4212 snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
4213 adev_to_drm(dm->adev)->primary->index + dm->num_of_edps);
4215 dm->backlight_dev[dm->num_of_edps] = backlight_device_register(bl_name,
4216 adev_to_drm(dm->adev)->dev,
4218 &amdgpu_dm_backlight_ops,
4221 if (IS_ERR(dm->backlight_dev[dm->num_of_edps]))
4222 DRM_ERROR("DM: Backlight registration failed!\n");
4224 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
4227 static int initialize_plane(struct amdgpu_display_manager *dm,
4228 struct amdgpu_mode_info *mode_info, int plane_id,
4229 enum drm_plane_type plane_type,
4230 const struct dc_plane_cap *plane_cap)
4232 struct drm_plane *plane;
4233 unsigned long possible_crtcs;
4236 plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL);
4238 DRM_ERROR("KMS: Failed to allocate plane\n");
4241 plane->type = plane_type;
4244 * HACK: IGT tests expect that the primary plane for a CRTC
4245 * can only have one possible CRTC. Only expose support for
4246 * any CRTC if they're not going to be used as a primary plane
4247 * for a CRTC - like overlay or underlay planes.
4249 possible_crtcs = 1 << plane_id;
4250 if (plane_id >= dm->dc->caps.max_streams)
4251 possible_crtcs = 0xff;
4253 ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap);
4256 DRM_ERROR("KMS: Failed to initialize plane\n");
4262 mode_info->planes[plane_id] = plane;
4268 static void register_backlight_device(struct amdgpu_display_manager *dm,
4269 struct dc_link *link)
4271 if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
4272 link->type != dc_connection_none) {
4274 * Event if registration failed, we should continue with
4275 * DM initialization because not having a backlight control
4276 * is better then a black screen.
4278 if (!dm->backlight_dev[dm->num_of_edps])
4279 amdgpu_dm_register_backlight_device(dm);
4281 if (dm->backlight_dev[dm->num_of_edps]) {
4282 dm->backlight_link[dm->num_of_edps] = link;
4288 static void amdgpu_set_panel_orientation(struct drm_connector *connector);
4291 * In this architecture, the association
4292 * connector -> encoder -> crtc
4293 * id not really requried. The crtc and connector will hold the
4294 * display_index as an abstraction to use with DAL component
4296 * Returns 0 on success
4298 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
4300 struct amdgpu_display_manager *dm = &adev->dm;
4302 struct amdgpu_dm_connector *aconnector = NULL;
4303 struct amdgpu_encoder *aencoder = NULL;
4304 struct amdgpu_mode_info *mode_info = &adev->mode_info;
4307 enum dc_connection_type new_connection_type = dc_connection_none;
4308 const struct dc_plane_cap *plane;
4309 bool psr_feature_enabled = false;
4310 int max_overlay = dm->dc->caps.max_slave_planes;
4312 dm->display_indexes_num = dm->dc->caps.max_streams;
4313 /* Update the actual used number of crtc */
4314 adev->mode_info.num_crtc = adev->dm.display_indexes_num;
4316 amdgpu_dm_set_irq_funcs(adev);
4318 link_cnt = dm->dc->caps.max_links;
4319 if (amdgpu_dm_mode_config_init(dm->adev)) {
4320 DRM_ERROR("DM: Failed to initialize mode config\n");
4324 /* There is one primary plane per CRTC */
4325 primary_planes = dm->dc->caps.max_streams;
4326 ASSERT(primary_planes <= AMDGPU_MAX_PLANES);
4329 * Initialize primary planes, implicit planes for legacy IOCTLS.
4330 * Order is reversed to match iteration order in atomic check.
4332 for (i = (primary_planes - 1); i >= 0; i--) {
4333 plane = &dm->dc->caps.planes[i];
4335 if (initialize_plane(dm, mode_info, i,
4336 DRM_PLANE_TYPE_PRIMARY, plane)) {
4337 DRM_ERROR("KMS: Failed to initialize primary plane\n");
4343 * Initialize overlay planes, index starting after primary planes.
4344 * These planes have a higher DRM index than the primary planes since
4345 * they should be considered as having a higher z-order.
4346 * Order is reversed to match iteration order in atomic check.
4348 * Only support DCN for now, and only expose one so we don't encourage
4349 * userspace to use up all the pipes.
4351 for (i = 0; i < dm->dc->caps.max_planes; ++i) {
4352 struct dc_plane_cap *plane = &dm->dc->caps.planes[i];
4354 /* Do not create overlay if MPO disabled */
4355 if (amdgpu_dc_debug_mask & DC_DISABLE_MPO)
4358 if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL)
4361 if (!plane->pixel_format_support.argb8888)
4364 if (max_overlay-- == 0)
4367 if (initialize_plane(dm, NULL, primary_planes + i,
4368 DRM_PLANE_TYPE_OVERLAY, plane)) {
4369 DRM_ERROR("KMS: Failed to initialize overlay plane\n");
4374 for (i = 0; i < dm->dc->caps.max_streams; i++)
4375 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) {
4376 DRM_ERROR("KMS: Failed to initialize crtc\n");
4380 /* Use Outbox interrupt */
4381 switch (adev->ip_versions[DCE_HWIP][0]) {
4382 case IP_VERSION(3, 0, 0):
4383 case IP_VERSION(3, 1, 2):
4384 case IP_VERSION(3, 1, 3):
4385 case IP_VERSION(3, 1, 4):
4386 case IP_VERSION(3, 1, 5):
4387 case IP_VERSION(3, 1, 6):
4388 case IP_VERSION(3, 2, 0):
4389 case IP_VERSION(3, 2, 1):
4390 case IP_VERSION(2, 1, 0):
4391 if (register_outbox_irq_handlers(dm->adev)) {
4392 DRM_ERROR("DM: Failed to initialize IRQ\n");
4397 DRM_DEBUG_KMS("Unsupported DCN IP version for outbox: 0x%X\n",
4398 adev->ip_versions[DCE_HWIP][0]);
4401 /* Determine whether to enable PSR support by default. */
4402 if (!(amdgpu_dc_debug_mask & DC_DISABLE_PSR)) {
4403 switch (adev->ip_versions[DCE_HWIP][0]) {
4404 case IP_VERSION(3, 1, 2):
4405 case IP_VERSION(3, 1, 3):
4406 case IP_VERSION(3, 1, 4):
4407 case IP_VERSION(3, 1, 5):
4408 case IP_VERSION(3, 1, 6):
4409 case IP_VERSION(3, 2, 0):
4410 case IP_VERSION(3, 2, 1):
4411 psr_feature_enabled = true;
4414 psr_feature_enabled = amdgpu_dc_feature_mask & DC_PSR_MASK;
4419 /* loops over all connectors on the board */
4420 for (i = 0; i < link_cnt; i++) {
4421 struct dc_link *link = NULL;
4423 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
4425 "KMS: Cannot support more than %d display indexes\n",
4426 AMDGPU_DM_MAX_DISPLAY_INDEX);
4430 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
4434 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
4438 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
4439 DRM_ERROR("KMS: Failed to initialize encoder\n");
4443 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
4444 DRM_ERROR("KMS: Failed to initialize connector\n");
4448 link = dc_get_link_at_index(dm->dc, i);
4450 if (!dc_link_detect_connection_type(link, &new_connection_type))
4451 DRM_ERROR("KMS: Failed to detect connector\n");
4453 if (aconnector->base.force && new_connection_type == dc_connection_none) {
4454 emulated_link_detect(link);
4455 amdgpu_dm_update_connector_after_detect(aconnector);
4459 mutex_lock(&dm->dc_lock);
4460 ret = dc_link_detect(link, DETECT_REASON_BOOT);
4461 mutex_unlock(&dm->dc_lock);
4464 amdgpu_dm_update_connector_after_detect(aconnector);
4465 register_backlight_device(dm, link);
4467 if (dm->num_of_edps)
4468 update_connector_ext_caps(aconnector);
4470 if (psr_feature_enabled)
4471 amdgpu_dm_set_psr_caps(link);
4473 /* TODO: Fix vblank control helpers to delay PSR entry to allow this when
4474 * PSR is also supported.
4476 if (link->psr_settings.psr_feature_enabled)
4477 adev_to_drm(adev)->vblank_disable_immediate = false;
4480 amdgpu_set_panel_orientation(&aconnector->base);
4483 /* If we didn't find a panel, notify the acpi video detection */
4484 if (dm->adev->flags & AMD_IS_APU && dm->num_of_edps == 0)
4485 acpi_video_report_nolcd();
4487 /* Software is initialized. Now we can register interrupt handlers. */
4488 switch (adev->asic_type) {
4489 #if defined(CONFIG_DRM_AMD_DC_SI)
4494 if (dce60_register_irq_handlers(dm->adev)) {
4495 DRM_ERROR("DM: Failed to initialize IRQ\n");
4509 case CHIP_POLARIS11:
4510 case CHIP_POLARIS10:
4511 case CHIP_POLARIS12:
4516 if (dce110_register_irq_handlers(dm->adev)) {
4517 DRM_ERROR("DM: Failed to initialize IRQ\n");
4522 switch (adev->ip_versions[DCE_HWIP][0]) {
4523 case IP_VERSION(1, 0, 0):
4524 case IP_VERSION(1, 0, 1):
4525 case IP_VERSION(2, 0, 2):
4526 case IP_VERSION(2, 0, 3):
4527 case IP_VERSION(2, 0, 0):
4528 case IP_VERSION(2, 1, 0):
4529 case IP_VERSION(3, 0, 0):
4530 case IP_VERSION(3, 0, 2):
4531 case IP_VERSION(3, 0, 3):
4532 case IP_VERSION(3, 0, 1):
4533 case IP_VERSION(3, 1, 2):
4534 case IP_VERSION(3, 1, 3):
4535 case IP_VERSION(3, 1, 4):
4536 case IP_VERSION(3, 1, 5):
4537 case IP_VERSION(3, 1, 6):
4538 case IP_VERSION(3, 2, 0):
4539 case IP_VERSION(3, 2, 1):
4540 if (dcn10_register_irq_handlers(dm->adev)) {
4541 DRM_ERROR("DM: Failed to initialize IRQ\n");
4546 DRM_ERROR("Unsupported DCE IP versions: 0x%X\n",
4547 adev->ip_versions[DCE_HWIP][0]);
4561 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
4563 drm_atomic_private_obj_fini(&dm->atomic_obj);
4567 /******************************************************************************
4568 * amdgpu_display_funcs functions
4569 *****************************************************************************/
4572 * dm_bandwidth_update - program display watermarks
4574 * @adev: amdgpu_device pointer
4576 * Calculate and program the display watermarks and line buffer allocation.
4578 static void dm_bandwidth_update(struct amdgpu_device *adev)
4580 /* TODO: implement later */
4583 static const struct amdgpu_display_funcs dm_display_funcs = {
4584 .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
4585 .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
4586 .backlight_set_level = NULL, /* never called for DC */
4587 .backlight_get_level = NULL, /* never called for DC */
4588 .hpd_sense = NULL,/* called unconditionally */
4589 .hpd_set_polarity = NULL, /* called unconditionally */
4590 .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
4591 .page_flip_get_scanoutpos =
4592 dm_crtc_get_scanoutpos,/* called unconditionally */
4593 .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
4594 .add_connector = NULL, /* VBIOS parsing. DAL does it. */
4597 #if defined(CONFIG_DEBUG_KERNEL_DC)
4599 static ssize_t s3_debug_store(struct device *device,
4600 struct device_attribute *attr,
4606 struct drm_device *drm_dev = dev_get_drvdata(device);
4607 struct amdgpu_device *adev = drm_to_adev(drm_dev);
4609 ret = kstrtoint(buf, 0, &s3_state);
4614 drm_kms_helper_hotplug_event(adev_to_drm(adev));
4619 return ret == 0 ? count : 0;
4622 DEVICE_ATTR_WO(s3_debug);
4626 static int dm_init_microcode(struct amdgpu_device *adev)
4631 switch (adev->ip_versions[DCE_HWIP][0]) {
4632 case IP_VERSION(2, 1, 0):
4633 fw_name_dmub = FIRMWARE_RENOIR_DMUB;
4634 if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
4635 fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB;
4637 case IP_VERSION(3, 0, 0):
4638 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0))
4639 fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB;
4641 fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB;
4643 case IP_VERSION(3, 0, 1):
4644 fw_name_dmub = FIRMWARE_VANGOGH_DMUB;
4646 case IP_VERSION(3, 0, 2):
4647 fw_name_dmub = FIRMWARE_DIMGREY_CAVEFISH_DMUB;
4649 case IP_VERSION(3, 0, 3):
4650 fw_name_dmub = FIRMWARE_BEIGE_GOBY_DMUB;
4652 case IP_VERSION(3, 1, 2):
4653 case IP_VERSION(3, 1, 3):
4654 fw_name_dmub = FIRMWARE_YELLOW_CARP_DMUB;
4656 case IP_VERSION(3, 1, 4):
4657 fw_name_dmub = FIRMWARE_DCN_314_DMUB;
4659 case IP_VERSION(3, 1, 5):
4660 fw_name_dmub = FIRMWARE_DCN_315_DMUB;
4662 case IP_VERSION(3, 1, 6):
4663 fw_name_dmub = FIRMWARE_DCN316_DMUB;
4665 case IP_VERSION(3, 2, 0):
4666 fw_name_dmub = FIRMWARE_DCN_V3_2_0_DMCUB;
4668 case IP_VERSION(3, 2, 1):
4669 fw_name_dmub = FIRMWARE_DCN_V3_2_1_DMCUB;
4672 /* ASIC doesn't support DMUB. */
4675 r = amdgpu_ucode_request(adev, &adev->dm.dmub_fw, fw_name_dmub);
4677 DRM_ERROR("DMUB firmware loading failed: %d\n", r);
4681 static int dm_early_init(void *handle)
4683 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4684 struct amdgpu_mode_info *mode_info = &adev->mode_info;
4685 struct atom_context *ctx = mode_info->atom_context;
4686 int index = GetIndexIntoMasterTable(DATA, Object_Header);
4689 /* if there is no object header, skip DM */
4690 if (!amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) {
4691 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
4692 dev_info(adev->dev, "No object header, skipping DM\n");
4696 switch (adev->asic_type) {
4697 #if defined(CONFIG_DRM_AMD_DC_SI)
4701 adev->mode_info.num_crtc = 6;
4702 adev->mode_info.num_hpd = 6;
4703 adev->mode_info.num_dig = 6;
4706 adev->mode_info.num_crtc = 2;
4707 adev->mode_info.num_hpd = 2;
4708 adev->mode_info.num_dig = 2;
4713 adev->mode_info.num_crtc = 6;
4714 adev->mode_info.num_hpd = 6;
4715 adev->mode_info.num_dig = 6;
4718 adev->mode_info.num_crtc = 4;
4719 adev->mode_info.num_hpd = 6;
4720 adev->mode_info.num_dig = 7;
4724 adev->mode_info.num_crtc = 2;
4725 adev->mode_info.num_hpd = 6;
4726 adev->mode_info.num_dig = 6;
4730 adev->mode_info.num_crtc = 6;
4731 adev->mode_info.num_hpd = 6;
4732 adev->mode_info.num_dig = 7;
4735 adev->mode_info.num_crtc = 3;
4736 adev->mode_info.num_hpd = 6;
4737 adev->mode_info.num_dig = 9;
4740 adev->mode_info.num_crtc = 2;
4741 adev->mode_info.num_hpd = 6;
4742 adev->mode_info.num_dig = 9;
4744 case CHIP_POLARIS11:
4745 case CHIP_POLARIS12:
4746 adev->mode_info.num_crtc = 5;
4747 adev->mode_info.num_hpd = 5;
4748 adev->mode_info.num_dig = 5;
4750 case CHIP_POLARIS10:
4752 adev->mode_info.num_crtc = 6;
4753 adev->mode_info.num_hpd = 6;
4754 adev->mode_info.num_dig = 6;
4759 adev->mode_info.num_crtc = 6;
4760 adev->mode_info.num_hpd = 6;
4761 adev->mode_info.num_dig = 6;
4765 switch (adev->ip_versions[DCE_HWIP][0]) {
4766 case IP_VERSION(2, 0, 2):
4767 case IP_VERSION(3, 0, 0):
4768 adev->mode_info.num_crtc = 6;
4769 adev->mode_info.num_hpd = 6;
4770 adev->mode_info.num_dig = 6;
4772 case IP_VERSION(2, 0, 0):
4773 case IP_VERSION(3, 0, 2):
4774 adev->mode_info.num_crtc = 5;
4775 adev->mode_info.num_hpd = 5;
4776 adev->mode_info.num_dig = 5;
4778 case IP_VERSION(2, 0, 3):
4779 case IP_VERSION(3, 0, 3):
4780 adev->mode_info.num_crtc = 2;
4781 adev->mode_info.num_hpd = 2;
4782 adev->mode_info.num_dig = 2;
4784 case IP_VERSION(1, 0, 0):
4785 case IP_VERSION(1, 0, 1):
4786 case IP_VERSION(3, 0, 1):
4787 case IP_VERSION(2, 1, 0):
4788 case IP_VERSION(3, 1, 2):
4789 case IP_VERSION(3, 1, 3):
4790 case IP_VERSION(3, 1, 4):
4791 case IP_VERSION(3, 1, 5):
4792 case IP_VERSION(3, 1, 6):
4793 case IP_VERSION(3, 2, 0):
4794 case IP_VERSION(3, 2, 1):
4795 adev->mode_info.num_crtc = 4;
4796 adev->mode_info.num_hpd = 4;
4797 adev->mode_info.num_dig = 4;
4800 DRM_ERROR("Unsupported DCE IP versions: 0x%x\n",
4801 adev->ip_versions[DCE_HWIP][0]);
4807 if (adev->mode_info.funcs == NULL)
4808 adev->mode_info.funcs = &dm_display_funcs;
4811 * Note: Do NOT change adev->audio_endpt_rreg and
4812 * adev->audio_endpt_wreg because they are initialised in
4813 * amdgpu_device_init()
4815 #if defined(CONFIG_DEBUG_KERNEL_DC)
4817 adev_to_drm(adev)->dev,
4818 &dev_attr_s3_debug);
4820 adev->dc_enabled = true;
4822 return dm_init_microcode(adev);
4825 static bool modereset_required(struct drm_crtc_state *crtc_state)
4827 return !crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state);
4830 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
4832 drm_encoder_cleanup(encoder);
4836 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
4837 .destroy = amdgpu_dm_encoder_destroy,
4841 fill_plane_color_attributes(const struct drm_plane_state *plane_state,
4842 const enum surface_pixel_format format,
4843 enum dc_color_space *color_space)
4847 *color_space = COLOR_SPACE_SRGB;
4849 /* DRM color properties only affect non-RGB formats. */
4850 if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
4853 full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE);
4855 switch (plane_state->color_encoding) {
4856 case DRM_COLOR_YCBCR_BT601:
4858 *color_space = COLOR_SPACE_YCBCR601;
4860 *color_space = COLOR_SPACE_YCBCR601_LIMITED;
4863 case DRM_COLOR_YCBCR_BT709:
4865 *color_space = COLOR_SPACE_YCBCR709;
4867 *color_space = COLOR_SPACE_YCBCR709_LIMITED;
4870 case DRM_COLOR_YCBCR_BT2020:
4872 *color_space = COLOR_SPACE_2020_YCBCR;
4885 fill_dc_plane_info_and_addr(struct amdgpu_device *adev,
4886 const struct drm_plane_state *plane_state,
4887 const u64 tiling_flags,
4888 struct dc_plane_info *plane_info,
4889 struct dc_plane_address *address,
4891 bool force_disable_dcc)
4893 const struct drm_framebuffer *fb = plane_state->fb;
4894 const struct amdgpu_framebuffer *afb =
4895 to_amdgpu_framebuffer(plane_state->fb);
4898 memset(plane_info, 0, sizeof(*plane_info));
4900 switch (fb->format->format) {
4902 plane_info->format =
4903 SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
4905 case DRM_FORMAT_RGB565:
4906 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
4908 case DRM_FORMAT_XRGB8888:
4909 case DRM_FORMAT_ARGB8888:
4910 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
4912 case DRM_FORMAT_XRGB2101010:
4913 case DRM_FORMAT_ARGB2101010:
4914 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
4916 case DRM_FORMAT_XBGR2101010:
4917 case DRM_FORMAT_ABGR2101010:
4918 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
4920 case DRM_FORMAT_XBGR8888:
4921 case DRM_FORMAT_ABGR8888:
4922 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888;
4924 case DRM_FORMAT_NV21:
4925 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
4927 case DRM_FORMAT_NV12:
4928 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
4930 case DRM_FORMAT_P010:
4931 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb;
4933 case DRM_FORMAT_XRGB16161616F:
4934 case DRM_FORMAT_ARGB16161616F:
4935 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F;
4937 case DRM_FORMAT_XBGR16161616F:
4938 case DRM_FORMAT_ABGR16161616F:
4939 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F;
4941 case DRM_FORMAT_XRGB16161616:
4942 case DRM_FORMAT_ARGB16161616:
4943 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616;
4945 case DRM_FORMAT_XBGR16161616:
4946 case DRM_FORMAT_ABGR16161616:
4947 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616;
4951 "Unsupported screen format %p4cc\n",
4952 &fb->format->format);
4956 switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
4957 case DRM_MODE_ROTATE_0:
4958 plane_info->rotation = ROTATION_ANGLE_0;
4960 case DRM_MODE_ROTATE_90:
4961 plane_info->rotation = ROTATION_ANGLE_90;
4963 case DRM_MODE_ROTATE_180:
4964 plane_info->rotation = ROTATION_ANGLE_180;
4966 case DRM_MODE_ROTATE_270:
4967 plane_info->rotation = ROTATION_ANGLE_270;
4970 plane_info->rotation = ROTATION_ANGLE_0;
4975 plane_info->visible = true;
4976 plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE;
4978 plane_info->layer_index = plane_state->normalized_zpos;
4980 ret = fill_plane_color_attributes(plane_state, plane_info->format,
4981 &plane_info->color_space);
4985 ret = amdgpu_dm_plane_fill_plane_buffer_attributes(adev, afb, plane_info->format,
4986 plane_info->rotation, tiling_flags,
4987 &plane_info->tiling_info,
4988 &plane_info->plane_size,
4989 &plane_info->dcc, address,
4990 tmz_surface, force_disable_dcc);
4994 amdgpu_dm_plane_fill_blending_from_plane_state(
4995 plane_state, &plane_info->per_pixel_alpha, &plane_info->pre_multiplied_alpha,
4996 &plane_info->global_alpha, &plane_info->global_alpha_value);
5001 static int fill_dc_plane_attributes(struct amdgpu_device *adev,
5002 struct dc_plane_state *dc_plane_state,
5003 struct drm_plane_state *plane_state,
5004 struct drm_crtc_state *crtc_state)
5006 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
5007 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)plane_state->fb;
5008 struct dc_scaling_info scaling_info;
5009 struct dc_plane_info plane_info;
5011 bool force_disable_dcc = false;
5013 ret = amdgpu_dm_plane_fill_dc_scaling_info(adev, plane_state, &scaling_info);
5017 dc_plane_state->src_rect = scaling_info.src_rect;
5018 dc_plane_state->dst_rect = scaling_info.dst_rect;
5019 dc_plane_state->clip_rect = scaling_info.clip_rect;
5020 dc_plane_state->scaling_quality = scaling_info.scaling_quality;
5022 force_disable_dcc = adev->asic_type == CHIP_RAVEN && adev->in_suspend;
5023 ret = fill_dc_plane_info_and_addr(adev, plane_state,
5026 &dc_plane_state->address,
5032 dc_plane_state->format = plane_info.format;
5033 dc_plane_state->color_space = plane_info.color_space;
5034 dc_plane_state->format = plane_info.format;
5035 dc_plane_state->plane_size = plane_info.plane_size;
5036 dc_plane_state->rotation = plane_info.rotation;
5037 dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror;
5038 dc_plane_state->stereo_format = plane_info.stereo_format;
5039 dc_plane_state->tiling_info = plane_info.tiling_info;
5040 dc_plane_state->visible = plane_info.visible;
5041 dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha;
5042 dc_plane_state->pre_multiplied_alpha = plane_info.pre_multiplied_alpha;
5043 dc_plane_state->global_alpha = plane_info.global_alpha;
5044 dc_plane_state->global_alpha_value = plane_info.global_alpha_value;
5045 dc_plane_state->dcc = plane_info.dcc;
5046 dc_plane_state->layer_index = plane_info.layer_index;
5047 dc_plane_state->flip_int_enabled = true;
5050 * Always set input transfer function, since plane state is refreshed
5053 ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dc_plane_state);
5060 static inline void fill_dc_dirty_rect(struct drm_plane *plane,
5061 struct rect *dirty_rect, int32_t x,
5062 s32 y, s32 width, s32 height,
5065 if (*i > DC_MAX_DIRTY_RECTS)
5068 if (*i == DC_MAX_DIRTY_RECTS)
5073 dirty_rect->width = width;
5074 dirty_rect->height = height;
5078 "[PLANE:%d] PSR FFU dirty rect size (%d, %d)\n",
5079 plane->base.id, width, height);
5082 "[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)",
5083 plane->base.id, x, y, width, height);
5090 * fill_dc_dirty_rects() - Fill DC dirty regions for PSR selective updates
5092 * @plane: DRM plane containing dirty regions that need to be flushed to the eDP
5094 * @old_plane_state: Old state of @plane
5095 * @new_plane_state: New state of @plane
5096 * @crtc_state: New state of CRTC connected to the @plane
5097 * @flip_addrs: DC flip tracking struct, which also tracts dirty rects
5098 * @dirty_regions_changed: dirty regions changed
5100 * For PSR SU, DC informs the DMUB uController of dirty rectangle regions
5101 * (referred to as "damage clips" in DRM nomenclature) that require updating on
5102 * the eDP remote buffer. The responsibility of specifying the dirty regions is
5105 * A damage-aware DRM client should fill the FB_DAMAGE_CLIPS property on the
5106 * plane with regions that require flushing to the eDP remote buffer. In
5107 * addition, certain use cases - such as cursor and multi-plane overlay (MPO) -
5108 * implicitly provide damage clips without any client support via the plane
5111 static void fill_dc_dirty_rects(struct drm_plane *plane,
5112 struct drm_plane_state *old_plane_state,
5113 struct drm_plane_state *new_plane_state,
5114 struct drm_crtc_state *crtc_state,
5115 struct dc_flip_addrs *flip_addrs,
5116 bool *dirty_regions_changed)
5118 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
5119 struct rect *dirty_rects = flip_addrs->dirty_rects;
5121 struct drm_mode_rect *clips;
5125 *dirty_regions_changed = false;
5128 * Cursor plane has it's own dirty rect update interface. See
5129 * dcn10_dmub_update_cursor_data and dmub_cmd_update_cursor_info_data
5131 if (plane->type == DRM_PLANE_TYPE_CURSOR)
5134 num_clips = drm_plane_get_damage_clips_count(new_plane_state);
5135 clips = drm_plane_get_damage_clips(new_plane_state);
5137 if (!dm_crtc_state->mpo_requested) {
5138 if (!num_clips || num_clips > DC_MAX_DIRTY_RECTS)
5141 for (; flip_addrs->dirty_rect_count < num_clips; clips++)
5142 fill_dc_dirty_rect(new_plane_state->plane,
5143 &dirty_rects[flip_addrs->dirty_rect_count],
5144 clips->x1, clips->y1,
5145 clips->x2 - clips->x1, clips->y2 - clips->y1,
5146 &flip_addrs->dirty_rect_count,
5152 * MPO is requested. Add entire plane bounding box to dirty rects if
5153 * flipped to or damaged.
5155 * If plane is moved or resized, also add old bounding box to dirty
5158 fb_changed = old_plane_state->fb->base.id !=
5159 new_plane_state->fb->base.id;
5160 bb_changed = (old_plane_state->crtc_x != new_plane_state->crtc_x ||
5161 old_plane_state->crtc_y != new_plane_state->crtc_y ||
5162 old_plane_state->crtc_w != new_plane_state->crtc_w ||
5163 old_plane_state->crtc_h != new_plane_state->crtc_h);
5166 "[PLANE:%d] PSR bb_changed:%d fb_changed:%d num_clips:%d\n",
5167 new_plane_state->plane->base.id,
5168 bb_changed, fb_changed, num_clips);
5170 *dirty_regions_changed = bb_changed;
5173 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5174 new_plane_state->crtc_x,
5175 new_plane_state->crtc_y,
5176 new_plane_state->crtc_w,
5177 new_plane_state->crtc_h, &i, false);
5179 /* Add old plane bounding-box if plane is moved or resized */
5180 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5181 old_plane_state->crtc_x,
5182 old_plane_state->crtc_y,
5183 old_plane_state->crtc_w,
5184 old_plane_state->crtc_h, &i, false);
5188 for (; i < num_clips; clips++)
5189 fill_dc_dirty_rect(new_plane_state->plane,
5190 &dirty_rects[i], clips->x1,
5191 clips->y1, clips->x2 - clips->x1,
5192 clips->y2 - clips->y1, &i, false);
5193 } else if (fb_changed && !bb_changed) {
5194 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
5195 new_plane_state->crtc_x,
5196 new_plane_state->crtc_y,
5197 new_plane_state->crtc_w,
5198 new_plane_state->crtc_h, &i, false);
5201 if (i > DC_MAX_DIRTY_RECTS)
5204 flip_addrs->dirty_rect_count = i;
5208 fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[0], 0, 0,
5209 dm_crtc_state->base.mode.crtc_hdisplay,
5210 dm_crtc_state->base.mode.crtc_vdisplay,
5211 &flip_addrs->dirty_rect_count, true);
5214 static void update_stream_scaling_settings(const struct drm_display_mode *mode,
5215 const struct dm_connector_state *dm_state,
5216 struct dc_stream_state *stream)
5218 enum amdgpu_rmx_type rmx_type;
5220 struct rect src = { 0 }; /* viewport in composition space*/
5221 struct rect dst = { 0 }; /* stream addressable area */
5223 /* no mode. nothing to be done */
5227 /* Full screen scaling by default */
5228 src.width = mode->hdisplay;
5229 src.height = mode->vdisplay;
5230 dst.width = stream->timing.h_addressable;
5231 dst.height = stream->timing.v_addressable;
5234 rmx_type = dm_state->scaling;
5235 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
5236 if (src.width * dst.height <
5237 src.height * dst.width) {
5238 /* height needs less upscaling/more downscaling */
5239 dst.width = src.width *
5240 dst.height / src.height;
5242 /* width needs less upscaling/more downscaling */
5243 dst.height = src.height *
5244 dst.width / src.width;
5246 } else if (rmx_type == RMX_CENTER) {
5250 dst.x = (stream->timing.h_addressable - dst.width) / 2;
5251 dst.y = (stream->timing.v_addressable - dst.height) / 2;
5253 if (dm_state->underscan_enable) {
5254 dst.x += dm_state->underscan_hborder / 2;
5255 dst.y += dm_state->underscan_vborder / 2;
5256 dst.width -= dm_state->underscan_hborder;
5257 dst.height -= dm_state->underscan_vborder;
5264 DRM_DEBUG_KMS("Destination Rectangle x:%d y:%d width:%d height:%d\n",
5265 dst.x, dst.y, dst.width, dst.height);
5269 static enum dc_color_depth
5270 convert_color_depth_from_display_info(const struct drm_connector *connector,
5271 bool is_y420, int requested_bpc)
5278 /* Cap display bpc based on HDMI 2.0 HF-VSDB */
5279 if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48)
5281 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36)
5283 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30)
5286 bpc = (uint8_t)connector->display_info.bpc;
5287 /* Assume 8 bpc by default if no bpc is specified. */
5288 bpc = bpc ? bpc : 8;
5291 if (requested_bpc > 0) {
5293 * Cap display bpc based on the user requested value.
5295 * The value for state->max_bpc may not correctly updated
5296 * depending on when the connector gets added to the state
5297 * or if this was called outside of atomic check, so it
5298 * can't be used directly.
5300 bpc = min_t(u8, bpc, requested_bpc);
5302 /* Round down to the nearest even number. */
5303 bpc = bpc - (bpc & 1);
5309 * Temporary Work around, DRM doesn't parse color depth for
5310 * EDID revision before 1.4
5311 * TODO: Fix edid parsing
5313 return COLOR_DEPTH_888;
5315 return COLOR_DEPTH_666;
5317 return COLOR_DEPTH_888;
5319 return COLOR_DEPTH_101010;
5321 return COLOR_DEPTH_121212;
5323 return COLOR_DEPTH_141414;
5325 return COLOR_DEPTH_161616;
5327 return COLOR_DEPTH_UNDEFINED;
5331 static enum dc_aspect_ratio
5332 get_aspect_ratio(const struct drm_display_mode *mode_in)
5334 /* 1-1 mapping, since both enums follow the HDMI spec. */
5335 return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio;
5338 static enum dc_color_space
5339 get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
5341 enum dc_color_space color_space = COLOR_SPACE_SRGB;
5343 switch (dc_crtc_timing->pixel_encoding) {
5344 case PIXEL_ENCODING_YCBCR422:
5345 case PIXEL_ENCODING_YCBCR444:
5346 case PIXEL_ENCODING_YCBCR420:
5349 * 27030khz is the separation point between HDTV and SDTV
5350 * according to HDMI spec, we use YCbCr709 and YCbCr601
5353 if (dc_crtc_timing->pix_clk_100hz > 270300) {
5354 if (dc_crtc_timing->flags.Y_ONLY)
5356 COLOR_SPACE_YCBCR709_LIMITED;
5358 color_space = COLOR_SPACE_YCBCR709;
5360 if (dc_crtc_timing->flags.Y_ONLY)
5362 COLOR_SPACE_YCBCR601_LIMITED;
5364 color_space = COLOR_SPACE_YCBCR601;
5369 case PIXEL_ENCODING_RGB:
5370 color_space = COLOR_SPACE_SRGB;
5381 static bool adjust_colour_depth_from_display_info(
5382 struct dc_crtc_timing *timing_out,
5383 const struct drm_display_info *info)
5385 enum dc_color_depth depth = timing_out->display_color_depth;
5388 normalized_clk = timing_out->pix_clk_100hz / 10;
5389 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */
5390 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
5391 normalized_clk /= 2;
5392 /* Adjusting pix clock following on HDMI spec based on colour depth */
5394 case COLOR_DEPTH_888:
5396 case COLOR_DEPTH_101010:
5397 normalized_clk = (normalized_clk * 30) / 24;
5399 case COLOR_DEPTH_121212:
5400 normalized_clk = (normalized_clk * 36) / 24;
5402 case COLOR_DEPTH_161616:
5403 normalized_clk = (normalized_clk * 48) / 24;
5406 /* The above depths are the only ones valid for HDMI. */
5409 if (normalized_clk <= info->max_tmds_clock) {
5410 timing_out->display_color_depth = depth;
5413 } while (--depth > COLOR_DEPTH_666);
5417 static void fill_stream_properties_from_drm_display_mode(
5418 struct dc_stream_state *stream,
5419 const struct drm_display_mode *mode_in,
5420 const struct drm_connector *connector,
5421 const struct drm_connector_state *connector_state,
5422 const struct dc_stream_state *old_stream,
5425 struct dc_crtc_timing *timing_out = &stream->timing;
5426 const struct drm_display_info *info = &connector->display_info;
5427 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
5428 struct hdmi_vendor_infoframe hv_frame;
5429 struct hdmi_avi_infoframe avi_frame;
5431 memset(&hv_frame, 0, sizeof(hv_frame));
5432 memset(&avi_frame, 0, sizeof(avi_frame));
5434 timing_out->h_border_left = 0;
5435 timing_out->h_border_right = 0;
5436 timing_out->v_border_top = 0;
5437 timing_out->v_border_bottom = 0;
5438 /* TODO: un-hardcode */
5439 if (drm_mode_is_420_only(info, mode_in)
5440 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5441 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5442 else if (drm_mode_is_420_also(info, mode_in)
5443 && aconnector->force_yuv420_output)
5444 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5445 else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR444)
5446 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5447 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
5449 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
5451 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
5452 timing_out->display_color_depth = convert_color_depth_from_display_info(
5454 (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420),
5456 timing_out->scan_type = SCANNING_TYPE_NODATA;
5457 timing_out->hdmi_vic = 0;
5460 timing_out->vic = old_stream->timing.vic;
5461 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY;
5462 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY;
5464 timing_out->vic = drm_match_cea_mode(mode_in);
5465 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
5466 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
5467 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
5468 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
5471 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
5472 drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, (struct drm_connector *)connector, mode_in);
5473 timing_out->vic = avi_frame.video_code;
5474 drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, (struct drm_connector *)connector, mode_in);
5475 timing_out->hdmi_vic = hv_frame.vic;
5478 if (is_freesync_video_mode(mode_in, aconnector)) {
5479 timing_out->h_addressable = mode_in->hdisplay;
5480 timing_out->h_total = mode_in->htotal;
5481 timing_out->h_sync_width = mode_in->hsync_end - mode_in->hsync_start;
5482 timing_out->h_front_porch = mode_in->hsync_start - mode_in->hdisplay;
5483 timing_out->v_total = mode_in->vtotal;
5484 timing_out->v_addressable = mode_in->vdisplay;
5485 timing_out->v_front_porch = mode_in->vsync_start - mode_in->vdisplay;
5486 timing_out->v_sync_width = mode_in->vsync_end - mode_in->vsync_start;
5487 timing_out->pix_clk_100hz = mode_in->clock * 10;
5489 timing_out->h_addressable = mode_in->crtc_hdisplay;
5490 timing_out->h_total = mode_in->crtc_htotal;
5491 timing_out->h_sync_width = mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
5492 timing_out->h_front_porch = mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
5493 timing_out->v_total = mode_in->crtc_vtotal;
5494 timing_out->v_addressable = mode_in->crtc_vdisplay;
5495 timing_out->v_front_porch = mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
5496 timing_out->v_sync_width = mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
5497 timing_out->pix_clk_100hz = mode_in->crtc_clock * 10;
5500 timing_out->aspect_ratio = get_aspect_ratio(mode_in);
5502 stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
5503 stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
5504 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
5505 if (!adjust_colour_depth_from_display_info(timing_out, info) &&
5506 drm_mode_is_420_also(info, mode_in) &&
5507 timing_out->pixel_encoding != PIXEL_ENCODING_YCBCR420) {
5508 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5509 adjust_colour_depth_from_display_info(timing_out, info);
5513 stream->output_color_space = get_output_color_space(timing_out);
5516 static void fill_audio_info(struct audio_info *audio_info,
5517 const struct drm_connector *drm_connector,
5518 const struct dc_sink *dc_sink)
5521 int cea_revision = 0;
5522 const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
5524 audio_info->manufacture_id = edid_caps->manufacturer_id;
5525 audio_info->product_id = edid_caps->product_id;
5527 cea_revision = drm_connector->display_info.cea_rev;
5529 strscpy(audio_info->display_name,
5530 edid_caps->display_name,
5531 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
5533 if (cea_revision >= 3) {
5534 audio_info->mode_count = edid_caps->audio_mode_count;
5536 for (i = 0; i < audio_info->mode_count; ++i) {
5537 audio_info->modes[i].format_code =
5538 (enum audio_format_code)
5539 (edid_caps->audio_modes[i].format_code);
5540 audio_info->modes[i].channel_count =
5541 edid_caps->audio_modes[i].channel_count;
5542 audio_info->modes[i].sample_rates.all =
5543 edid_caps->audio_modes[i].sample_rate;
5544 audio_info->modes[i].sample_size =
5545 edid_caps->audio_modes[i].sample_size;
5549 audio_info->flags.all = edid_caps->speaker_flags;
5551 /* TODO: We only check for the progressive mode, check for interlace mode too */
5552 if (drm_connector->latency_present[0]) {
5553 audio_info->video_latency = drm_connector->video_latency[0];
5554 audio_info->audio_latency = drm_connector->audio_latency[0];
5557 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
5562 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
5563 struct drm_display_mode *dst_mode)
5565 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
5566 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
5567 dst_mode->crtc_clock = src_mode->crtc_clock;
5568 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
5569 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
5570 dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start;
5571 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
5572 dst_mode->crtc_htotal = src_mode->crtc_htotal;
5573 dst_mode->crtc_hskew = src_mode->crtc_hskew;
5574 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
5575 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
5576 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
5577 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
5578 dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
5582 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
5583 const struct drm_display_mode *native_mode,
5586 if (scale_enabled) {
5587 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
5588 } else if (native_mode->clock == drm_mode->clock &&
5589 native_mode->htotal == drm_mode->htotal &&
5590 native_mode->vtotal == drm_mode->vtotal) {
5591 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
5593 /* no scaling nor amdgpu inserted, no need to patch */
5597 static struct dc_sink *
5598 create_fake_sink(struct amdgpu_dm_connector *aconnector)
5600 struct dc_sink_init_data sink_init_data = { 0 };
5601 struct dc_sink *sink = NULL;
5602 sink_init_data.link = aconnector->dc_link;
5603 sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
5605 sink = dc_sink_create(&sink_init_data);
5607 DRM_ERROR("Failed to create sink!\n");
5610 sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
5615 static void set_multisync_trigger_params(
5616 struct dc_stream_state *stream)
5618 struct dc_stream_state *master = NULL;
5620 if (stream->triggered_crtc_reset.enabled) {
5621 master = stream->triggered_crtc_reset.event_source;
5622 stream->triggered_crtc_reset.event =
5623 master->timing.flags.VSYNC_POSITIVE_POLARITY ?
5624 CRTC_EVENT_VSYNC_RISING : CRTC_EVENT_VSYNC_FALLING;
5625 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_PIXEL;
5629 static void set_master_stream(struct dc_stream_state *stream_set[],
5632 int j, highest_rfr = 0, master_stream = 0;
5634 for (j = 0; j < stream_count; j++) {
5635 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
5636 int refresh_rate = 0;
5638 refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/
5639 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
5640 if (refresh_rate > highest_rfr) {
5641 highest_rfr = refresh_rate;
5646 for (j = 0; j < stream_count; j++) {
5648 stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
5652 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
5655 struct dc_stream_state *stream;
5657 if (context->stream_count < 2)
5659 for (i = 0; i < context->stream_count ; i++) {
5660 if (!context->streams[i])
5663 * TODO: add a function to read AMD VSDB bits and set
5664 * crtc_sync_master.multi_sync_enabled flag
5665 * For now it's set to false
5669 set_master_stream(context->streams, context->stream_count);
5671 for (i = 0; i < context->stream_count ; i++) {
5672 stream = context->streams[i];
5677 set_multisync_trigger_params(stream);
5682 * DOC: FreeSync Video
5684 * When a userspace application wants to play a video, the content follows a
5685 * standard format definition that usually specifies the FPS for that format.
5686 * The below list illustrates some video format and the expected FPS,
5689 * - TV/NTSC (23.976 FPS)
5692 * - TV/NTSC (29.97 FPS)
5693 * - TV/NTSC (30 FPS)
5694 * - Cinema HFR (48 FPS)
5696 * - Commonly used (60 FPS)
5697 * - Multiples of 24 (48,72,96 FPS)
5699 * The list of standards video format is not huge and can be added to the
5700 * connector modeset list beforehand. With that, userspace can leverage
5701 * FreeSync to extends the front porch in order to attain the target refresh
5702 * rate. Such a switch will happen seamlessly, without screen blanking or
5703 * reprogramming of the output in any other way. If the userspace requests a
5704 * modesetting change compatible with FreeSync modes that only differ in the
5705 * refresh rate, DC will skip the full update and avoid blink during the
5706 * transition. For example, the video player can change the modesetting from
5707 * 60Hz to 30Hz for playing TV/NTSC content when it goes full screen without
5708 * causing any display blink. This same concept can be applied to a mode
5711 static struct drm_display_mode *
5712 get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector,
5713 bool use_probed_modes)
5715 struct drm_display_mode *m, *m_pref = NULL;
5716 u16 current_refresh, highest_refresh;
5717 struct list_head *list_head = use_probed_modes ?
5718 &aconnector->base.probed_modes :
5719 &aconnector->base.modes;
5721 if (aconnector->freesync_vid_base.clock != 0)
5722 return &aconnector->freesync_vid_base;
5724 /* Find the preferred mode */
5725 list_for_each_entry (m, list_head, head) {
5726 if (m->type & DRM_MODE_TYPE_PREFERRED) {
5733 /* Probably an EDID with no preferred mode. Fallback to first entry */
5734 m_pref = list_first_entry_or_null(
5735 &aconnector->base.modes, struct drm_display_mode, head);
5737 DRM_DEBUG_DRIVER("No preferred mode found in EDID\n");
5742 highest_refresh = drm_mode_vrefresh(m_pref);
5745 * Find the mode with highest refresh rate with same resolution.
5746 * For some monitors, preferred mode is not the mode with highest
5747 * supported refresh rate.
5749 list_for_each_entry (m, list_head, head) {
5750 current_refresh = drm_mode_vrefresh(m);
5752 if (m->hdisplay == m_pref->hdisplay &&
5753 m->vdisplay == m_pref->vdisplay &&
5754 highest_refresh < current_refresh) {
5755 highest_refresh = current_refresh;
5760 drm_mode_copy(&aconnector->freesync_vid_base, m_pref);
5764 static bool is_freesync_video_mode(const struct drm_display_mode *mode,
5765 struct amdgpu_dm_connector *aconnector)
5767 struct drm_display_mode *high_mode;
5770 high_mode = get_highest_refresh_rate_mode(aconnector, false);
5771 if (!high_mode || !mode)
5774 timing_diff = high_mode->vtotal - mode->vtotal;
5776 if (high_mode->clock == 0 || high_mode->clock != mode->clock ||
5777 high_mode->hdisplay != mode->hdisplay ||
5778 high_mode->vdisplay != mode->vdisplay ||
5779 high_mode->hsync_start != mode->hsync_start ||
5780 high_mode->hsync_end != mode->hsync_end ||
5781 high_mode->htotal != mode->htotal ||
5782 high_mode->hskew != mode->hskew ||
5783 high_mode->vscan != mode->vscan ||
5784 high_mode->vsync_start - mode->vsync_start != timing_diff ||
5785 high_mode->vsync_end - mode->vsync_end != timing_diff)
5791 static void update_dsc_caps(struct amdgpu_dm_connector *aconnector,
5792 struct dc_sink *sink, struct dc_stream_state *stream,
5793 struct dsc_dec_dpcd_caps *dsc_caps)
5795 stream->timing.flags.DSC = 0;
5796 dsc_caps->is_dsc_supported = false;
5798 if (aconnector->dc_link && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT ||
5799 sink->sink_signal == SIGNAL_TYPE_EDP)) {
5800 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE ||
5801 sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER)
5802 dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
5803 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
5804 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
5810 static void apply_dsc_policy_for_edp(struct amdgpu_dm_connector *aconnector,
5811 struct dc_sink *sink, struct dc_stream_state *stream,
5812 struct dsc_dec_dpcd_caps *dsc_caps,
5813 uint32_t max_dsc_target_bpp_limit_override)
5815 const struct dc_link_settings *verified_link_cap = NULL;
5816 u32 link_bw_in_kbps;
5817 u32 edp_min_bpp_x16, edp_max_bpp_x16;
5818 struct dc *dc = sink->ctx->dc;
5819 struct dc_dsc_bw_range bw_range = {0};
5820 struct dc_dsc_config dsc_cfg = {0};
5821 struct dc_dsc_config_options dsc_options = {0};
5823 dc_dsc_get_default_config_option(dc, &dsc_options);
5824 dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16;
5826 verified_link_cap = dc_link_get_link_cap(stream->link);
5827 link_bw_in_kbps = dc_link_bandwidth_kbps(stream->link, verified_link_cap);
5828 edp_min_bpp_x16 = 8 * 16;
5829 edp_max_bpp_x16 = 8 * 16;
5831 if (edp_max_bpp_x16 > dsc_caps->edp_max_bits_per_pixel)
5832 edp_max_bpp_x16 = dsc_caps->edp_max_bits_per_pixel;
5834 if (edp_max_bpp_x16 < edp_min_bpp_x16)
5835 edp_min_bpp_x16 = edp_max_bpp_x16;
5837 if (dc_dsc_compute_bandwidth_range(dc->res_pool->dscs[0],
5838 dc->debug.dsc_min_slice_height_override,
5839 edp_min_bpp_x16, edp_max_bpp_x16,
5844 if (bw_range.max_kbps < link_bw_in_kbps) {
5845 if (dc_dsc_compute_config(dc->res_pool->dscs[0],
5851 stream->timing.dsc_cfg = dsc_cfg;
5852 stream->timing.flags.DSC = 1;
5853 stream->timing.dsc_cfg.bits_per_pixel = edp_max_bpp_x16;
5859 if (dc_dsc_compute_config(dc->res_pool->dscs[0],
5865 stream->timing.dsc_cfg = dsc_cfg;
5866 stream->timing.flags.DSC = 1;
5871 static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector,
5872 struct dc_sink *sink, struct dc_stream_state *stream,
5873 struct dsc_dec_dpcd_caps *dsc_caps)
5875 struct drm_connector *drm_connector = &aconnector->base;
5876 u32 link_bandwidth_kbps;
5877 struct dc *dc = sink->ctx->dc;
5878 u32 max_supported_bw_in_kbps, timing_bw_in_kbps;
5879 u32 dsc_max_supported_bw_in_kbps;
5880 u32 max_dsc_target_bpp_limit_override =
5881 drm_connector->display_info.max_dsc_bpp;
5882 struct dc_dsc_config_options dsc_options = {0};
5884 dc_dsc_get_default_config_option(dc, &dsc_options);
5885 dsc_options.max_target_bpp_limit_override_x16 = max_dsc_target_bpp_limit_override * 16;
5887 link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
5888 dc_link_get_link_cap(aconnector->dc_link));
5890 /* Set DSC policy according to dsc_clock_en */
5891 dc_dsc_policy_set_enable_dsc_when_not_needed(
5892 aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE);
5894 if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_EDP &&
5895 !aconnector->dc_link->panel_config.dsc.disable_dsc_edp &&
5896 dc->caps.edp_dsc_support && aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE) {
5898 apply_dsc_policy_for_edp(aconnector, sink, stream, dsc_caps, max_dsc_target_bpp_limit_override);
5900 } else if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) {
5901 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) {
5902 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
5905 link_bandwidth_kbps,
5907 &stream->timing.dsc_cfg)) {
5908 stream->timing.flags.DSC = 1;
5909 DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from SST RX\n", __func__, drm_connector->name);
5911 } else if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) {
5912 timing_bw_in_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing);
5913 max_supported_bw_in_kbps = link_bandwidth_kbps;
5914 dsc_max_supported_bw_in_kbps = link_bandwidth_kbps;
5916 if (timing_bw_in_kbps > max_supported_bw_in_kbps &&
5917 max_supported_bw_in_kbps > 0 &&
5918 dsc_max_supported_bw_in_kbps > 0)
5919 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
5922 dsc_max_supported_bw_in_kbps,
5924 &stream->timing.dsc_cfg)) {
5925 stream->timing.flags.DSC = 1;
5926 DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from DP-HDMI PCON\n",
5927 __func__, drm_connector->name);
5932 /* Overwrite the stream flag if DSC is enabled through debugfs */
5933 if (aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE)
5934 stream->timing.flags.DSC = 1;
5936 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_h)
5937 stream->timing.dsc_cfg.num_slices_h = aconnector->dsc_settings.dsc_num_slices_h;
5939 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_v)
5940 stream->timing.dsc_cfg.num_slices_v = aconnector->dsc_settings.dsc_num_slices_v;
5942 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_bits_per_pixel)
5943 stream->timing.dsc_cfg.bits_per_pixel = aconnector->dsc_settings.dsc_bits_per_pixel;
5946 static struct dc_stream_state *
5947 create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
5948 const struct drm_display_mode *drm_mode,
5949 const struct dm_connector_state *dm_state,
5950 const struct dc_stream_state *old_stream,
5953 struct drm_display_mode *preferred_mode = NULL;
5954 struct drm_connector *drm_connector;
5955 const struct drm_connector_state *con_state =
5956 dm_state ? &dm_state->base : NULL;
5957 struct dc_stream_state *stream = NULL;
5958 struct drm_display_mode mode;
5959 struct drm_display_mode saved_mode;
5960 struct drm_display_mode *freesync_mode = NULL;
5961 bool native_mode_found = false;
5962 bool recalculate_timing = false;
5963 bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false;
5965 int preferred_refresh = 0;
5966 enum color_transfer_func tf = TRANSFER_FUNC_UNKNOWN;
5967 struct dsc_dec_dpcd_caps dsc_caps;
5969 struct dc_sink *sink = NULL;
5971 drm_mode_init(&mode, drm_mode);
5972 memset(&saved_mode, 0, sizeof(saved_mode));
5974 if (aconnector == NULL) {
5975 DRM_ERROR("aconnector is NULL!\n");
5979 drm_connector = &aconnector->base;
5981 if (!aconnector->dc_sink) {
5982 sink = create_fake_sink(aconnector);
5986 sink = aconnector->dc_sink;
5987 dc_sink_retain(sink);
5990 stream = dc_create_stream_for_sink(sink);
5992 if (stream == NULL) {
5993 DRM_ERROR("Failed to create stream for sink!\n");
5997 stream->dm_stream_context = aconnector;
5999 stream->timing.flags.LTE_340MCSC_SCRAMBLE =
6000 drm_connector->display_info.hdmi.scdc.scrambling.low_rates;
6002 list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
6003 /* Search for preferred mode */
6004 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
6005 native_mode_found = true;
6009 if (!native_mode_found)
6010 preferred_mode = list_first_entry_or_null(
6011 &aconnector->base.modes,
6012 struct drm_display_mode,
6015 mode_refresh = drm_mode_vrefresh(&mode);
6017 if (preferred_mode == NULL) {
6019 * This may not be an error, the use case is when we have no
6020 * usermode calls to reset and set mode upon hotplug. In this
6021 * case, we call set mode ourselves to restore the previous mode
6022 * and the modelist may not be filled in in time.
6024 DRM_DEBUG_DRIVER("No preferred mode found\n");
6026 recalculate_timing = amdgpu_freesync_vid_mode &&
6027 is_freesync_video_mode(&mode, aconnector);
6028 if (recalculate_timing) {
6029 freesync_mode = get_highest_refresh_rate_mode(aconnector, false);
6030 drm_mode_copy(&saved_mode, &mode);
6031 drm_mode_copy(&mode, freesync_mode);
6033 decide_crtc_timing_for_drm_display_mode(
6034 &mode, preferred_mode, scale);
6036 preferred_refresh = drm_mode_vrefresh(preferred_mode);
6040 if (recalculate_timing)
6041 drm_mode_set_crtcinfo(&saved_mode, 0);
6043 drm_mode_set_crtcinfo(&mode, 0);
6046 * If scaling is enabled and refresh rate didn't change
6047 * we copy the vic and polarities of the old timings
6049 if (!scale || mode_refresh != preferred_refresh)
6050 fill_stream_properties_from_drm_display_mode(
6051 stream, &mode, &aconnector->base, con_state, NULL,
6054 fill_stream_properties_from_drm_display_mode(
6055 stream, &mode, &aconnector->base, con_state, old_stream,
6058 if (aconnector->timing_changed) {
6059 DC_LOG_DEBUG("%s: overriding timing for automated test, bpc %d, changing to %d\n",
6061 stream->timing.display_color_depth,
6062 aconnector->timing_requested->display_color_depth);
6063 stream->timing = *aconnector->timing_requested;
6066 /* SST DSC determination policy */
6067 update_dsc_caps(aconnector, sink, stream, &dsc_caps);
6068 if (aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE && dsc_caps.is_dsc_supported)
6069 apply_dsc_policy_for_stream(aconnector, sink, stream, &dsc_caps);
6071 update_stream_scaling_settings(&mode, dm_state, stream);
6074 &stream->audio_info,
6078 update_stream_signal(stream, sink);
6080 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
6081 mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket);
6083 if (stream->link->psr_settings.psr_feature_enabled) {
6085 // should decide stream support vsc sdp colorimetry capability
6086 // before building vsc info packet
6088 stream->use_vsc_sdp_for_colorimetry = false;
6089 if (aconnector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
6090 stream->use_vsc_sdp_for_colorimetry =
6091 aconnector->dc_sink->is_vsc_sdp_colorimetry_supported;
6093 if (stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED)
6094 stream->use_vsc_sdp_for_colorimetry = true;
6096 if (stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22)
6097 tf = TRANSFER_FUNC_GAMMA_22;
6098 mod_build_vsc_infopacket(stream, &stream->vsc_infopacket, stream->output_color_space, tf);
6099 aconnector->psr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY;
6103 dc_sink_release(sink);
6108 static enum drm_connector_status
6109 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
6112 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6116 * 1. This interface is NOT called in context of HPD irq.
6117 * 2. This interface *is called* in context of user-mode ioctl. Which
6118 * makes it a bad place for *any* MST-related activity.
6121 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
6122 !aconnector->fake_enable)
6123 connected = (aconnector->dc_sink != NULL);
6125 connected = (aconnector->base.force == DRM_FORCE_ON ||
6126 aconnector->base.force == DRM_FORCE_ON_DIGITAL);
6128 update_subconnector_property(aconnector);
6130 return (connected ? connector_status_connected :
6131 connector_status_disconnected);
6134 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
6135 struct drm_connector_state *connector_state,
6136 struct drm_property *property,
6139 struct drm_device *dev = connector->dev;
6140 struct amdgpu_device *adev = drm_to_adev(dev);
6141 struct dm_connector_state *dm_old_state =
6142 to_dm_connector_state(connector->state);
6143 struct dm_connector_state *dm_new_state =
6144 to_dm_connector_state(connector_state);
6148 if (property == dev->mode_config.scaling_mode_property) {
6149 enum amdgpu_rmx_type rmx_type;
6152 case DRM_MODE_SCALE_CENTER:
6153 rmx_type = RMX_CENTER;
6155 case DRM_MODE_SCALE_ASPECT:
6156 rmx_type = RMX_ASPECT;
6158 case DRM_MODE_SCALE_FULLSCREEN:
6159 rmx_type = RMX_FULL;
6161 case DRM_MODE_SCALE_NONE:
6167 if (dm_old_state->scaling == rmx_type)
6170 dm_new_state->scaling = rmx_type;
6172 } else if (property == adev->mode_info.underscan_hborder_property) {
6173 dm_new_state->underscan_hborder = val;
6175 } else if (property == adev->mode_info.underscan_vborder_property) {
6176 dm_new_state->underscan_vborder = val;
6178 } else if (property == adev->mode_info.underscan_property) {
6179 dm_new_state->underscan_enable = val;
6181 } else if (property == adev->mode_info.abm_level_property) {
6182 dm_new_state->abm_level = val;
6189 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
6190 const struct drm_connector_state *state,
6191 struct drm_property *property,
6194 struct drm_device *dev = connector->dev;
6195 struct amdgpu_device *adev = drm_to_adev(dev);
6196 struct dm_connector_state *dm_state =
6197 to_dm_connector_state(state);
6200 if (property == dev->mode_config.scaling_mode_property) {
6201 switch (dm_state->scaling) {
6203 *val = DRM_MODE_SCALE_CENTER;
6206 *val = DRM_MODE_SCALE_ASPECT;
6209 *val = DRM_MODE_SCALE_FULLSCREEN;
6213 *val = DRM_MODE_SCALE_NONE;
6217 } else if (property == adev->mode_info.underscan_hborder_property) {
6218 *val = dm_state->underscan_hborder;
6220 } else if (property == adev->mode_info.underscan_vborder_property) {
6221 *val = dm_state->underscan_vborder;
6223 } else if (property == adev->mode_info.underscan_property) {
6224 *val = dm_state->underscan_enable;
6226 } else if (property == adev->mode_info.abm_level_property) {
6227 *val = dm_state->abm_level;
6234 static void amdgpu_dm_connector_unregister(struct drm_connector *connector)
6236 struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector);
6238 drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux);
6241 static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
6243 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6244 const struct dc_link *link = aconnector->dc_link;
6245 struct amdgpu_device *adev = drm_to_adev(connector->dev);
6246 struct amdgpu_display_manager *dm = &adev->dm;
6250 * Call only if mst_mgr was initialized before since it's not done
6251 * for all connector types.
6253 if (aconnector->mst_mgr.dev)
6254 drm_dp_mst_topology_mgr_destroy(&aconnector->mst_mgr);
6256 for (i = 0; i < dm->num_of_edps; i++) {
6257 if ((link == dm->backlight_link[i]) && dm->backlight_dev[i]) {
6258 backlight_device_unregister(dm->backlight_dev[i]);
6259 dm->backlight_dev[i] = NULL;
6263 if (aconnector->dc_em_sink)
6264 dc_sink_release(aconnector->dc_em_sink);
6265 aconnector->dc_em_sink = NULL;
6266 if (aconnector->dc_sink)
6267 dc_sink_release(aconnector->dc_sink);
6268 aconnector->dc_sink = NULL;
6270 drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux);
6271 drm_connector_unregister(connector);
6272 drm_connector_cleanup(connector);
6273 if (aconnector->i2c) {
6274 i2c_del_adapter(&aconnector->i2c->base);
6275 kfree(aconnector->i2c);
6277 kfree(aconnector->dm_dp_aux.aux.name);
6282 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
6284 struct dm_connector_state *state =
6285 to_dm_connector_state(connector->state);
6287 if (connector->state)
6288 __drm_atomic_helper_connector_destroy_state(connector->state);
6292 state = kzalloc(sizeof(*state), GFP_KERNEL);
6295 state->scaling = RMX_OFF;
6296 state->underscan_enable = false;
6297 state->underscan_hborder = 0;
6298 state->underscan_vborder = 0;
6299 state->base.max_requested_bpc = 8;
6300 state->vcpi_slots = 0;
6303 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
6304 state->abm_level = amdgpu_dm_abm_level;
6306 __drm_atomic_helper_connector_reset(connector, &state->base);
6310 struct drm_connector_state *
6311 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
6313 struct dm_connector_state *state =
6314 to_dm_connector_state(connector->state);
6316 struct dm_connector_state *new_state =
6317 kmemdup(state, sizeof(*state), GFP_KERNEL);
6322 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
6324 new_state->freesync_capable = state->freesync_capable;
6325 new_state->abm_level = state->abm_level;
6326 new_state->scaling = state->scaling;
6327 new_state->underscan_enable = state->underscan_enable;
6328 new_state->underscan_hborder = state->underscan_hborder;
6329 new_state->underscan_vborder = state->underscan_vborder;
6330 new_state->vcpi_slots = state->vcpi_slots;
6331 new_state->pbn = state->pbn;
6332 return &new_state->base;
6336 amdgpu_dm_connector_late_register(struct drm_connector *connector)
6338 struct amdgpu_dm_connector *amdgpu_dm_connector =
6339 to_amdgpu_dm_connector(connector);
6342 if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
6343 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
6344 amdgpu_dm_connector->dm_dp_aux.aux.dev = connector->kdev;
6345 r = drm_dp_aux_register(&amdgpu_dm_connector->dm_dp_aux.aux);
6350 #if defined(CONFIG_DEBUG_FS)
6351 connector_debugfs_init(amdgpu_dm_connector);
6357 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
6358 .reset = amdgpu_dm_connector_funcs_reset,
6359 .detect = amdgpu_dm_connector_detect,
6360 .fill_modes = drm_helper_probe_single_connector_modes,
6361 .destroy = amdgpu_dm_connector_destroy,
6362 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
6363 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
6364 .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
6365 .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
6366 .late_register = amdgpu_dm_connector_late_register,
6367 .early_unregister = amdgpu_dm_connector_unregister
6370 static int get_modes(struct drm_connector *connector)
6372 return amdgpu_dm_connector_get_modes(connector);
6375 static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
6377 struct dc_sink_init_data init_params = {
6378 .link = aconnector->dc_link,
6379 .sink_signal = SIGNAL_TYPE_VIRTUAL
6383 if (!aconnector->base.edid_blob_ptr) {
6384 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
6385 aconnector->base.name);
6387 aconnector->base.force = DRM_FORCE_OFF;
6391 edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
6393 aconnector->edid = edid;
6395 aconnector->dc_em_sink = dc_link_add_remote_sink(
6396 aconnector->dc_link,
6398 (edid->extensions + 1) * EDID_LENGTH,
6401 if (aconnector->base.force == DRM_FORCE_ON) {
6402 aconnector->dc_sink = aconnector->dc_link->local_sink ?
6403 aconnector->dc_link->local_sink :
6404 aconnector->dc_em_sink;
6405 dc_sink_retain(aconnector->dc_sink);
6409 static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
6411 struct dc_link *link = (struct dc_link *)aconnector->dc_link;
6414 * In case of headless boot with force on for DP managed connector
6415 * Those settings have to be != 0 to get initial modeset
6417 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
6418 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
6419 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
6422 create_eml_sink(aconnector);
6425 static enum dc_status dm_validate_stream_and_context(struct dc *dc,
6426 struct dc_stream_state *stream)
6428 enum dc_status dc_result = DC_ERROR_UNEXPECTED;
6429 struct dc_plane_state *dc_plane_state = NULL;
6430 struct dc_state *dc_state = NULL;
6435 dc_plane_state = dc_create_plane_state(dc);
6436 if (!dc_plane_state)
6439 dc_state = dc_create_state(dc);
6443 /* populate stream to plane */
6444 dc_plane_state->src_rect.height = stream->src.height;
6445 dc_plane_state->src_rect.width = stream->src.width;
6446 dc_plane_state->dst_rect.height = stream->src.height;
6447 dc_plane_state->dst_rect.width = stream->src.width;
6448 dc_plane_state->clip_rect.height = stream->src.height;
6449 dc_plane_state->clip_rect.width = stream->src.width;
6450 dc_plane_state->plane_size.surface_pitch = ((stream->src.width + 255) / 256) * 256;
6451 dc_plane_state->plane_size.surface_size.height = stream->src.height;
6452 dc_plane_state->plane_size.surface_size.width = stream->src.width;
6453 dc_plane_state->plane_size.chroma_size.height = stream->src.height;
6454 dc_plane_state->plane_size.chroma_size.width = stream->src.width;
6455 dc_plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
6456 dc_plane_state->tiling_info.gfx9.swizzle = DC_SW_UNKNOWN;
6457 dc_plane_state->rotation = ROTATION_ANGLE_0;
6458 dc_plane_state->is_tiling_rotated = false;
6459 dc_plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_LINEAR_GENERAL;
6461 dc_result = dc_validate_stream(dc, stream);
6462 if (dc_result == DC_OK)
6463 dc_result = dc_validate_plane(dc, dc_plane_state);
6465 if (dc_result == DC_OK)
6466 dc_result = dc_add_stream_to_ctx(dc, dc_state, stream);
6468 if (dc_result == DC_OK && !dc_add_plane_to_context(
6473 dc_result = DC_FAIL_ATTACH_SURFACES;
6475 if (dc_result == DC_OK)
6476 dc_result = dc_validate_global_state(dc, dc_state, true);
6480 dc_release_state(dc_state);
6483 dc_plane_state_release(dc_plane_state);
6488 struct dc_stream_state *
6489 create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector,
6490 const struct drm_display_mode *drm_mode,
6491 const struct dm_connector_state *dm_state,
6492 const struct dc_stream_state *old_stream)
6494 struct drm_connector *connector = &aconnector->base;
6495 struct amdgpu_device *adev = drm_to_adev(connector->dev);
6496 struct dc_stream_state *stream;
6497 const struct drm_connector_state *drm_state = dm_state ? &dm_state->base : NULL;
6498 int requested_bpc = drm_state ? drm_state->max_requested_bpc : 8;
6499 enum dc_status dc_result = DC_OK;
6502 stream = create_stream_for_sink(aconnector, drm_mode,
6503 dm_state, old_stream,
6505 if (stream == NULL) {
6506 DRM_ERROR("Failed to create stream for sink!\n");
6510 dc_result = dc_validate_stream(adev->dm.dc, stream);
6511 if (dc_result == DC_OK && stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
6512 dc_result = dm_dp_mst_is_port_support_mode(aconnector, stream);
6514 if (dc_result == DC_OK)
6515 dc_result = dm_validate_stream_and_context(adev->dm.dc, stream);
6517 if (dc_result != DC_OK) {
6518 DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n",
6523 dc_status_to_str(dc_result));
6525 dc_stream_release(stream);
6527 requested_bpc -= 2; /* lower bpc to retry validation */
6530 } while (stream == NULL && requested_bpc >= 6);
6532 if (dc_result == DC_FAIL_ENC_VALIDATE && !aconnector->force_yuv420_output) {
6533 DRM_DEBUG_KMS("Retry forcing YCbCr420 encoding\n");
6535 aconnector->force_yuv420_output = true;
6536 stream = create_validate_stream_for_sink(aconnector, drm_mode,
6537 dm_state, old_stream);
6538 aconnector->force_yuv420_output = false;
6544 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
6545 struct drm_display_mode *mode)
6547 int result = MODE_ERROR;
6548 struct dc_sink *dc_sink;
6549 /* TODO: Unhardcode stream count */
6550 struct dc_stream_state *stream;
6551 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6553 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
6554 (mode->flags & DRM_MODE_FLAG_DBLSCAN))
6558 * Only run this the first time mode_valid is called to initilialize
6561 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
6562 !aconnector->dc_em_sink)
6563 handle_edid_mgmt(aconnector);
6565 dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
6567 if (dc_sink == NULL && aconnector->base.force != DRM_FORCE_ON_DIGITAL &&
6568 aconnector->base.force != DRM_FORCE_ON) {
6569 DRM_ERROR("dc_sink is NULL!\n");
6573 stream = create_validate_stream_for_sink(aconnector, mode, NULL, NULL);
6575 dc_stream_release(stream);
6580 /* TODO: error handling*/
6584 static int fill_hdr_info_packet(const struct drm_connector_state *state,
6585 struct dc_info_packet *out)
6587 struct hdmi_drm_infoframe frame;
6588 unsigned char buf[30]; /* 26 + 4 */
6592 memset(out, 0, sizeof(*out));
6594 if (!state->hdr_output_metadata)
6597 ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state);
6601 len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf));
6605 /* Static metadata is a fixed 26 bytes + 4 byte header. */
6609 /* Prepare the infopacket for DC. */
6610 switch (state->connector->connector_type) {
6611 case DRM_MODE_CONNECTOR_HDMIA:
6612 out->hb0 = 0x87; /* type */
6613 out->hb1 = 0x01; /* version */
6614 out->hb2 = 0x1A; /* length */
6615 out->sb[0] = buf[3]; /* checksum */
6619 case DRM_MODE_CONNECTOR_DisplayPort:
6620 case DRM_MODE_CONNECTOR_eDP:
6621 out->hb0 = 0x00; /* sdp id, zero */
6622 out->hb1 = 0x87; /* type */
6623 out->hb2 = 0x1D; /* payload len - 1 */
6624 out->hb3 = (0x13 << 2); /* sdp version */
6625 out->sb[0] = 0x01; /* version */
6626 out->sb[1] = 0x1A; /* length */
6634 memcpy(&out->sb[i], &buf[4], 26);
6637 print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb,
6638 sizeof(out->sb), false);
6644 amdgpu_dm_connector_atomic_check(struct drm_connector *conn,
6645 struct drm_atomic_state *state)
6647 struct drm_connector_state *new_con_state =
6648 drm_atomic_get_new_connector_state(state, conn);
6649 struct drm_connector_state *old_con_state =
6650 drm_atomic_get_old_connector_state(state, conn);
6651 struct drm_crtc *crtc = new_con_state->crtc;
6652 struct drm_crtc_state *new_crtc_state;
6653 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(conn);
6656 trace_amdgpu_dm_connector_atomic_check(new_con_state);
6658 if (conn->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
6659 ret = drm_dp_mst_root_conn_atomic_check(new_con_state, &aconn->mst_mgr);
6667 if (!drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state)) {
6668 struct dc_info_packet hdr_infopacket;
6670 ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket);
6674 new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
6675 if (IS_ERR(new_crtc_state))
6676 return PTR_ERR(new_crtc_state);
6679 * DC considers the stream backends changed if the
6680 * static metadata changes. Forcing the modeset also
6681 * gives a simple way for userspace to switch from
6682 * 8bpc to 10bpc when setting the metadata to enter
6685 * Changing the static metadata after it's been
6686 * set is permissible, however. So only force a
6687 * modeset if we're entering or exiting HDR.
6689 new_crtc_state->mode_changed =
6690 !old_con_state->hdr_output_metadata ||
6691 !new_con_state->hdr_output_metadata;
6697 static const struct drm_connector_helper_funcs
6698 amdgpu_dm_connector_helper_funcs = {
6700 * If hotplugging a second bigger display in FB Con mode, bigger resolution
6701 * modes will be filtered by drm_mode_validate_size(), and those modes
6702 * are missing after user start lightdm. So we need to renew modes list.
6703 * in get_modes call back, not just return the modes count
6705 .get_modes = get_modes,
6706 .mode_valid = amdgpu_dm_connector_mode_valid,
6707 .atomic_check = amdgpu_dm_connector_atomic_check,
6710 static void dm_encoder_helper_disable(struct drm_encoder *encoder)
6715 int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth)
6717 switch (display_color_depth) {
6718 case COLOR_DEPTH_666:
6720 case COLOR_DEPTH_888:
6722 case COLOR_DEPTH_101010:
6724 case COLOR_DEPTH_121212:
6726 case COLOR_DEPTH_141414:
6728 case COLOR_DEPTH_161616:
6736 static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
6737 struct drm_crtc_state *crtc_state,
6738 struct drm_connector_state *conn_state)
6740 struct drm_atomic_state *state = crtc_state->state;
6741 struct drm_connector *connector = conn_state->connector;
6742 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6743 struct dm_connector_state *dm_new_connector_state = to_dm_connector_state(conn_state);
6744 const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
6745 struct drm_dp_mst_topology_mgr *mst_mgr;
6746 struct drm_dp_mst_port *mst_port;
6747 struct drm_dp_mst_topology_state *mst_state;
6748 enum dc_color_depth color_depth;
6750 bool is_y420 = false;
6752 if (!aconnector->mst_output_port || !aconnector->dc_sink)
6755 mst_port = aconnector->mst_output_port;
6756 mst_mgr = &aconnector->mst_root->mst_mgr;
6758 if (!crtc_state->connectors_changed && !crtc_state->mode_changed)
6761 mst_state = drm_atomic_get_mst_topology_state(state, mst_mgr);
6762 if (IS_ERR(mst_state))
6763 return PTR_ERR(mst_state);
6765 if (!mst_state->pbn_div)
6766 mst_state->pbn_div = dm_mst_get_pbn_divider(aconnector->mst_root->dc_link);
6768 if (!state->duplicated) {
6769 int max_bpc = conn_state->max_requested_bpc;
6770 is_y420 = drm_mode_is_420_also(&connector->display_info, adjusted_mode) &&
6771 aconnector->force_yuv420_output;
6772 color_depth = convert_color_depth_from_display_info(connector,
6775 bpp = convert_dc_color_depth_into_bpc(color_depth) * 3;
6776 clock = adjusted_mode->clock;
6777 dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp, false);
6780 dm_new_connector_state->vcpi_slots =
6781 drm_dp_atomic_find_time_slots(state, mst_mgr, mst_port,
6782 dm_new_connector_state->pbn);
6783 if (dm_new_connector_state->vcpi_slots < 0) {
6784 DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots);
6785 return dm_new_connector_state->vcpi_slots;
6790 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
6791 .disable = dm_encoder_helper_disable,
6792 .atomic_check = dm_encoder_helper_atomic_check
6795 static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state,
6796 struct dc_state *dc_state,
6797 struct dsc_mst_fairness_vars *vars)
6799 struct dc_stream_state *stream = NULL;
6800 struct drm_connector *connector;
6801 struct drm_connector_state *new_con_state;
6802 struct amdgpu_dm_connector *aconnector;
6803 struct dm_connector_state *dm_conn_state;
6805 int vcpi, pbn_div, pbn, slot_num = 0;
6807 for_each_new_connector_in_state(state, connector, new_con_state, i) {
6809 aconnector = to_amdgpu_dm_connector(connector);
6811 if (!aconnector->mst_output_port)
6814 if (!new_con_state || !new_con_state->crtc)
6817 dm_conn_state = to_dm_connector_state(new_con_state);
6819 for (j = 0; j < dc_state->stream_count; j++) {
6820 stream = dc_state->streams[j];
6824 if ((struct amdgpu_dm_connector *)stream->dm_stream_context == aconnector)
6833 pbn_div = dm_mst_get_pbn_divider(stream->link);
6834 /* pbn is calculated by compute_mst_dsc_configs_for_state*/
6835 for (j = 0; j < dc_state->stream_count; j++) {
6836 if (vars[j].aconnector == aconnector) {
6842 if (j == dc_state->stream_count)
6845 slot_num = DIV_ROUND_UP(pbn, pbn_div);
6847 if (stream->timing.flags.DSC != 1) {
6848 dm_conn_state->pbn = pbn;
6849 dm_conn_state->vcpi_slots = slot_num;
6851 ret = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port,
6852 dm_conn_state->pbn, false);
6859 vcpi = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, pbn, true);
6863 dm_conn_state->pbn = pbn;
6864 dm_conn_state->vcpi_slots = vcpi;
6869 static int to_drm_connector_type(enum signal_type st)
6872 case SIGNAL_TYPE_HDMI_TYPE_A:
6873 return DRM_MODE_CONNECTOR_HDMIA;
6874 case SIGNAL_TYPE_EDP:
6875 return DRM_MODE_CONNECTOR_eDP;
6876 case SIGNAL_TYPE_LVDS:
6877 return DRM_MODE_CONNECTOR_LVDS;
6878 case SIGNAL_TYPE_RGB:
6879 return DRM_MODE_CONNECTOR_VGA;
6880 case SIGNAL_TYPE_DISPLAY_PORT:
6881 case SIGNAL_TYPE_DISPLAY_PORT_MST:
6882 return DRM_MODE_CONNECTOR_DisplayPort;
6883 case SIGNAL_TYPE_DVI_DUAL_LINK:
6884 case SIGNAL_TYPE_DVI_SINGLE_LINK:
6885 return DRM_MODE_CONNECTOR_DVID;
6886 case SIGNAL_TYPE_VIRTUAL:
6887 return DRM_MODE_CONNECTOR_VIRTUAL;
6890 return DRM_MODE_CONNECTOR_Unknown;
6894 static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector)
6896 struct drm_encoder *encoder;
6898 /* There is only one encoder per connector */
6899 drm_connector_for_each_possible_encoder(connector, encoder)
6905 static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
6907 struct drm_encoder *encoder;
6908 struct amdgpu_encoder *amdgpu_encoder;
6910 encoder = amdgpu_dm_connector_to_encoder(connector);
6912 if (encoder == NULL)
6915 amdgpu_encoder = to_amdgpu_encoder(encoder);
6917 amdgpu_encoder->native_mode.clock = 0;
6919 if (!list_empty(&connector->probed_modes)) {
6920 struct drm_display_mode *preferred_mode = NULL;
6922 list_for_each_entry(preferred_mode,
6923 &connector->probed_modes,
6925 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
6926 amdgpu_encoder->native_mode = *preferred_mode;
6934 static struct drm_display_mode *
6935 amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
6937 int hdisplay, int vdisplay)
6939 struct drm_device *dev = encoder->dev;
6940 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
6941 struct drm_display_mode *mode = NULL;
6942 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
6944 mode = drm_mode_duplicate(dev, native_mode);
6949 mode->hdisplay = hdisplay;
6950 mode->vdisplay = vdisplay;
6951 mode->type &= ~DRM_MODE_TYPE_PREFERRED;
6952 strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
6958 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
6959 struct drm_connector *connector)
6961 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
6962 struct drm_display_mode *mode = NULL;
6963 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
6964 struct amdgpu_dm_connector *amdgpu_dm_connector =
6965 to_amdgpu_dm_connector(connector);
6969 char name[DRM_DISPLAY_MODE_LEN];
6972 } common_modes[] = {
6973 { "640x480", 640, 480},
6974 { "800x600", 800, 600},
6975 { "1024x768", 1024, 768},
6976 { "1280x720", 1280, 720},
6977 { "1280x800", 1280, 800},
6978 {"1280x1024", 1280, 1024},
6979 { "1440x900", 1440, 900},
6980 {"1680x1050", 1680, 1050},
6981 {"1600x1200", 1600, 1200},
6982 {"1920x1080", 1920, 1080},
6983 {"1920x1200", 1920, 1200}
6986 n = ARRAY_SIZE(common_modes);
6988 for (i = 0; i < n; i++) {
6989 struct drm_display_mode *curmode = NULL;
6990 bool mode_existed = false;
6992 if (common_modes[i].w > native_mode->hdisplay ||
6993 common_modes[i].h > native_mode->vdisplay ||
6994 (common_modes[i].w == native_mode->hdisplay &&
6995 common_modes[i].h == native_mode->vdisplay))
6998 list_for_each_entry(curmode, &connector->probed_modes, head) {
6999 if (common_modes[i].w == curmode->hdisplay &&
7000 common_modes[i].h == curmode->vdisplay) {
7001 mode_existed = true;
7009 mode = amdgpu_dm_create_common_mode(encoder,
7010 common_modes[i].name, common_modes[i].w,
7015 drm_mode_probed_add(connector, mode);
7016 amdgpu_dm_connector->num_modes++;
7020 static void amdgpu_set_panel_orientation(struct drm_connector *connector)
7022 struct drm_encoder *encoder;
7023 struct amdgpu_encoder *amdgpu_encoder;
7024 const struct drm_display_mode *native_mode;
7026 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP &&
7027 connector->connector_type != DRM_MODE_CONNECTOR_LVDS)
7030 mutex_lock(&connector->dev->mode_config.mutex);
7031 amdgpu_dm_connector_get_modes(connector);
7032 mutex_unlock(&connector->dev->mode_config.mutex);
7034 encoder = amdgpu_dm_connector_to_encoder(connector);
7038 amdgpu_encoder = to_amdgpu_encoder(encoder);
7040 native_mode = &amdgpu_encoder->native_mode;
7041 if (native_mode->hdisplay == 0 || native_mode->vdisplay == 0)
7044 drm_connector_set_panel_orientation_with_quirk(connector,
7045 DRM_MODE_PANEL_ORIENTATION_UNKNOWN,
7046 native_mode->hdisplay,
7047 native_mode->vdisplay);
7050 static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
7053 struct amdgpu_dm_connector *amdgpu_dm_connector =
7054 to_amdgpu_dm_connector(connector);
7057 /* empty probed_modes */
7058 INIT_LIST_HEAD(&connector->probed_modes);
7059 amdgpu_dm_connector->num_modes =
7060 drm_add_edid_modes(connector, edid);
7062 /* sorting the probed modes before calling function
7063 * amdgpu_dm_get_native_mode() since EDID can have
7064 * more than one preferred mode. The modes that are
7065 * later in the probed mode list could be of higher
7066 * and preferred resolution. For example, 3840x2160
7067 * resolution in base EDID preferred timing and 4096x2160
7068 * preferred resolution in DID extension block later.
7070 drm_mode_sort(&connector->probed_modes);
7071 amdgpu_dm_get_native_mode(connector);
7073 /* Freesync capabilities are reset by calling
7074 * drm_add_edid_modes() and need to be
7077 amdgpu_dm_update_freesync_caps(connector, edid);
7079 amdgpu_dm_connector->num_modes = 0;
7083 static bool is_duplicate_mode(struct amdgpu_dm_connector *aconnector,
7084 struct drm_display_mode *mode)
7086 struct drm_display_mode *m;
7088 list_for_each_entry (m, &aconnector->base.probed_modes, head) {
7089 if (drm_mode_equal(m, mode))
7096 static uint add_fs_modes(struct amdgpu_dm_connector *aconnector)
7098 const struct drm_display_mode *m;
7099 struct drm_display_mode *new_mode;
7101 u32 new_modes_count = 0;
7103 /* Standard FPS values
7112 * 60 - Commonly used
7113 * 48,72,96,120 - Multiples of 24
7115 static const u32 common_rates[] = {
7116 23976, 24000, 25000, 29970, 30000,
7117 48000, 50000, 60000, 72000, 96000, 120000
7121 * Find mode with highest refresh rate with the same resolution
7122 * as the preferred mode. Some monitors report a preferred mode
7123 * with lower resolution than the highest refresh rate supported.
7126 m = get_highest_refresh_rate_mode(aconnector, true);
7130 for (i = 0; i < ARRAY_SIZE(common_rates); i++) {
7131 u64 target_vtotal, target_vtotal_diff;
7134 if (drm_mode_vrefresh(m) * 1000 < common_rates[i])
7137 if (common_rates[i] < aconnector->min_vfreq * 1000 ||
7138 common_rates[i] > aconnector->max_vfreq * 1000)
7141 num = (unsigned long long)m->clock * 1000 * 1000;
7142 den = common_rates[i] * (unsigned long long)m->htotal;
7143 target_vtotal = div_u64(num, den);
7144 target_vtotal_diff = target_vtotal - m->vtotal;
7146 /* Check for illegal modes */
7147 if (m->vsync_start + target_vtotal_diff < m->vdisplay ||
7148 m->vsync_end + target_vtotal_diff < m->vsync_start ||
7149 m->vtotal + target_vtotal_diff < m->vsync_end)
7152 new_mode = drm_mode_duplicate(aconnector->base.dev, m);
7156 new_mode->vtotal += (u16)target_vtotal_diff;
7157 new_mode->vsync_start += (u16)target_vtotal_diff;
7158 new_mode->vsync_end += (u16)target_vtotal_diff;
7159 new_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
7160 new_mode->type |= DRM_MODE_TYPE_DRIVER;
7162 if (!is_duplicate_mode(aconnector, new_mode)) {
7163 drm_mode_probed_add(&aconnector->base, new_mode);
7164 new_modes_count += 1;
7166 drm_mode_destroy(aconnector->base.dev, new_mode);
7169 return new_modes_count;
7172 static void amdgpu_dm_connector_add_freesync_modes(struct drm_connector *connector,
7175 struct amdgpu_dm_connector *amdgpu_dm_connector =
7176 to_amdgpu_dm_connector(connector);
7178 if (!(amdgpu_freesync_vid_mode && edid))
7181 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
7182 amdgpu_dm_connector->num_modes +=
7183 add_fs_modes(amdgpu_dm_connector);
7186 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
7188 struct amdgpu_dm_connector *amdgpu_dm_connector =
7189 to_amdgpu_dm_connector(connector);
7190 struct drm_encoder *encoder;
7191 struct edid *edid = amdgpu_dm_connector->edid;
7192 struct dc_link_settings *verified_link_cap =
7193 &amdgpu_dm_connector->dc_link->verified_link_cap;
7194 const struct dc *dc = amdgpu_dm_connector->dc_link->dc;
7196 encoder = amdgpu_dm_connector_to_encoder(connector);
7198 if (!drm_edid_is_valid(edid)) {
7199 amdgpu_dm_connector->num_modes =
7200 drm_add_modes_noedid(connector, 640, 480);
7201 if (dc->link_srv->dp_get_encoding_format(verified_link_cap) == DP_128b_132b_ENCODING)
7202 amdgpu_dm_connector->num_modes +=
7203 drm_add_modes_noedid(connector, 1920, 1080);
7205 amdgpu_dm_connector_ddc_get_modes(connector, edid);
7206 amdgpu_dm_connector_add_common_modes(encoder, connector);
7207 amdgpu_dm_connector_add_freesync_modes(connector, edid);
7209 amdgpu_dm_fbc_init(connector);
7211 return amdgpu_dm_connector->num_modes;
7214 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
7215 struct amdgpu_dm_connector *aconnector,
7217 struct dc_link *link,
7220 struct amdgpu_device *adev = drm_to_adev(dm->ddev);
7223 * Some of the properties below require access to state, like bpc.
7224 * Allocate some default initial connector state with our reset helper.
7226 if (aconnector->base.funcs->reset)
7227 aconnector->base.funcs->reset(&aconnector->base);
7229 aconnector->connector_id = link_index;
7230 aconnector->dc_link = link;
7231 aconnector->base.interlace_allowed = false;
7232 aconnector->base.doublescan_allowed = false;
7233 aconnector->base.stereo_allowed = false;
7234 aconnector->base.dpms = DRM_MODE_DPMS_OFF;
7235 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
7236 aconnector->audio_inst = -1;
7237 aconnector->pack_sdp_v1_3 = false;
7238 aconnector->as_type = ADAPTIVE_SYNC_TYPE_NONE;
7239 memset(&aconnector->vsdb_info, 0, sizeof(aconnector->vsdb_info));
7240 mutex_init(&aconnector->hpd_lock);
7243 * configure support HPD hot plug connector_>polled default value is 0
7244 * which means HPD hot plug not supported
7246 switch (connector_type) {
7247 case DRM_MODE_CONNECTOR_HDMIA:
7248 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7249 aconnector->base.ycbcr_420_allowed =
7250 link->link_enc->features.hdmi_ycbcr420_supported ? true : false;
7252 case DRM_MODE_CONNECTOR_DisplayPort:
7253 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7254 link->link_enc = link_enc_cfg_get_link_enc(link);
7255 ASSERT(link->link_enc);
7257 aconnector->base.ycbcr_420_allowed =
7258 link->link_enc->features.dp_ycbcr420_supported ? true : false;
7260 case DRM_MODE_CONNECTOR_DVID:
7261 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
7267 drm_object_attach_property(&aconnector->base.base,
7268 dm->ddev->mode_config.scaling_mode_property,
7269 DRM_MODE_SCALE_NONE);
7271 drm_object_attach_property(&aconnector->base.base,
7272 adev->mode_info.underscan_property,
7274 drm_object_attach_property(&aconnector->base.base,
7275 adev->mode_info.underscan_hborder_property,
7277 drm_object_attach_property(&aconnector->base.base,
7278 adev->mode_info.underscan_vborder_property,
7281 if (!aconnector->mst_root)
7282 drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16);
7284 /* This defaults to the max in the range, but we want 8bpc for non-edp. */
7285 aconnector->base.state->max_bpc = 16;
7286 aconnector->base.state->max_requested_bpc = aconnector->base.state->max_bpc;
7288 if (connector_type == DRM_MODE_CONNECTOR_eDP &&
7289 (dc_is_dmcu_initialized(adev->dm.dc) || adev->dm.dc->ctx->dmub_srv)) {
7290 drm_object_attach_property(&aconnector->base.base,
7291 adev->mode_info.abm_level_property, 0);
7294 if (connector_type == DRM_MODE_CONNECTOR_HDMIA ||
7295 connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
7296 connector_type == DRM_MODE_CONNECTOR_eDP) {
7297 drm_connector_attach_hdr_output_metadata_property(&aconnector->base);
7299 if (!aconnector->mst_root)
7300 drm_connector_attach_vrr_capable_property(&aconnector->base);
7302 if (adev->dm.hdcp_workqueue)
7303 drm_connector_attach_content_protection_property(&aconnector->base, true);
7307 static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
7308 struct i2c_msg *msgs, int num)
7310 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
7311 struct ddc_service *ddc_service = i2c->ddc_service;
7312 struct i2c_command cmd;
7316 cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
7321 cmd.number_of_payloads = num;
7322 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
7325 for (i = 0; i < num; i++) {
7326 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
7327 cmd.payloads[i].address = msgs[i].addr;
7328 cmd.payloads[i].length = msgs[i].len;
7329 cmd.payloads[i].data = msgs[i].buf;
7333 ddc_service->ctx->dc,
7334 ddc_service->link->link_index,
7338 kfree(cmd.payloads);
7342 static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
7344 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
7347 static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
7348 .master_xfer = amdgpu_dm_i2c_xfer,
7349 .functionality = amdgpu_dm_i2c_func,
7352 static struct amdgpu_i2c_adapter *
7353 create_i2c(struct ddc_service *ddc_service,
7357 struct amdgpu_device *adev = ddc_service->ctx->driver_context;
7358 struct amdgpu_i2c_adapter *i2c;
7360 i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
7363 i2c->base.owner = THIS_MODULE;
7364 i2c->base.class = I2C_CLASS_DDC;
7365 i2c->base.dev.parent = &adev->pdev->dev;
7366 i2c->base.algo = &amdgpu_dm_i2c_algo;
7367 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
7368 i2c_set_adapdata(&i2c->base, i2c);
7369 i2c->ddc_service = ddc_service;
7376 * Note: this function assumes that dc_link_detect() was called for the
7377 * dc_link which will be represented by this aconnector.
7379 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
7380 struct amdgpu_dm_connector *aconnector,
7382 struct amdgpu_encoder *aencoder)
7386 struct dc *dc = dm->dc;
7387 struct dc_link *link = dc_get_link_at_index(dc, link_index);
7388 struct amdgpu_i2c_adapter *i2c;
7390 link->priv = aconnector;
7392 DRM_DEBUG_DRIVER("%s()\n", __func__);
7394 i2c = create_i2c(link->ddc, link->link_index, &res);
7396 DRM_ERROR("Failed to create i2c adapter data\n");
7400 aconnector->i2c = i2c;
7401 res = i2c_add_adapter(&i2c->base);
7404 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
7408 connector_type = to_drm_connector_type(link->connector_signal);
7410 res = drm_connector_init_with_ddc(
7413 &amdgpu_dm_connector_funcs,
7418 DRM_ERROR("connector_init failed\n");
7419 aconnector->connector_id = -1;
7423 drm_connector_helper_add(
7425 &amdgpu_dm_connector_helper_funcs);
7427 amdgpu_dm_connector_init_helper(
7434 drm_connector_attach_encoder(
7435 &aconnector->base, &aencoder->base);
7437 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
7438 || connector_type == DRM_MODE_CONNECTOR_eDP)
7439 amdgpu_dm_initialize_dp_connector(dm, aconnector, link->link_index);
7444 aconnector->i2c = NULL;
7449 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
7451 switch (adev->mode_info.num_crtc) {
7468 static int amdgpu_dm_encoder_init(struct drm_device *dev,
7469 struct amdgpu_encoder *aencoder,
7470 uint32_t link_index)
7472 struct amdgpu_device *adev = drm_to_adev(dev);
7474 int res = drm_encoder_init(dev,
7476 &amdgpu_dm_encoder_funcs,
7477 DRM_MODE_ENCODER_TMDS,
7480 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
7483 aencoder->encoder_id = link_index;
7485 aencoder->encoder_id = -1;
7487 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
7492 static void manage_dm_interrupts(struct amdgpu_device *adev,
7493 struct amdgpu_crtc *acrtc,
7497 * We have no guarantee that the frontend index maps to the same
7498 * backend index - some even map to more than one.
7500 * TODO: Use a different interrupt or check DC itself for the mapping.
7503 amdgpu_display_crtc_idx_to_irq_type(
7508 drm_crtc_vblank_on(&acrtc->base);
7511 &adev->pageflip_irq,
7513 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
7520 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
7528 &adev->pageflip_irq,
7530 drm_crtc_vblank_off(&acrtc->base);
7534 static void dm_update_pflip_irq_state(struct amdgpu_device *adev,
7535 struct amdgpu_crtc *acrtc)
7538 amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id);
7541 * This reads the current state for the IRQ and force reapplies
7542 * the setting to hardware.
7544 amdgpu_irq_update(adev, &adev->pageflip_irq, irq_type);
7548 is_scaling_state_different(const struct dm_connector_state *dm_state,
7549 const struct dm_connector_state *old_dm_state)
7551 if (dm_state->scaling != old_dm_state->scaling)
7553 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
7554 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
7556 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
7557 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
7559 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
7560 dm_state->underscan_vborder != old_dm_state->underscan_vborder)
7565 static bool is_content_protection_different(struct drm_crtc_state *new_crtc_state,
7566 struct drm_crtc_state *old_crtc_state,
7567 struct drm_connector_state *new_conn_state,
7568 struct drm_connector_state *old_conn_state,
7569 const struct drm_connector *connector,
7570 struct hdcp_workqueue *hdcp_w)
7572 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
7573 struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
7575 pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n",
7576 connector->index, connector->status, connector->dpms);
7577 pr_debug("[HDCP_DM] state protection old: %x new: %x\n",
7578 old_conn_state->content_protection, new_conn_state->content_protection);
7581 pr_debug("[HDCP_DM] old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
7582 old_crtc_state->enable,
7583 old_crtc_state->active,
7584 old_crtc_state->mode_changed,
7585 old_crtc_state->active_changed,
7586 old_crtc_state->connectors_changed);
7589 pr_debug("[HDCP_DM] NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
7590 new_crtc_state->enable,
7591 new_crtc_state->active,
7592 new_crtc_state->mode_changed,
7593 new_crtc_state->active_changed,
7594 new_crtc_state->connectors_changed);
7596 /* hdcp content type change */
7597 if (old_conn_state->hdcp_content_type != new_conn_state->hdcp_content_type &&
7598 new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
7599 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7600 pr_debug("[HDCP_DM] Type0/1 change %s :true\n", __func__);
7604 /* CP is being re enabled, ignore this */
7605 if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED &&
7606 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7607 if (new_crtc_state && new_crtc_state->mode_changed) {
7608 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7609 pr_debug("[HDCP_DM] ENABLED->DESIRED & mode_changed %s :true\n", __func__);
7612 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED;
7613 pr_debug("[HDCP_DM] ENABLED -> DESIRED %s :false\n", __func__);
7617 /* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED
7619 * Handles: UNDESIRED -> ENABLED
7621 if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED &&
7622 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
7623 new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7625 /* Stream removed and re-enabled
7627 * Can sometimes overlap with the HPD case,
7628 * thus set update_hdcp to false to avoid
7629 * setting HDCP multiple times.
7631 * Handles: DESIRED -> DESIRED (Special case)
7633 if (!(old_conn_state->crtc && old_conn_state->crtc->enabled) &&
7634 new_conn_state->crtc && new_conn_state->crtc->enabled &&
7635 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7636 dm_con_state->update_hdcp = false;
7637 pr_debug("[HDCP_DM] DESIRED->DESIRED (Stream removed and re-enabled) %s :true\n",
7642 /* Hot-plug, headless s3, dpms
7644 * Only start HDCP if the display is connected/enabled.
7645 * update_hdcp flag will be set to false until the next
7648 * Handles: DESIRED -> DESIRED (Special case)
7650 if (dm_con_state->update_hdcp &&
7651 new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED &&
7652 connector->dpms == DRM_MODE_DPMS_ON && aconnector->dc_sink != NULL) {
7653 dm_con_state->update_hdcp = false;
7654 pr_debug("[HDCP_DM] DESIRED->DESIRED (Hot-plug, headless s3, dpms) %s :true\n",
7659 if (old_conn_state->content_protection == new_conn_state->content_protection) {
7660 if (new_conn_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7661 if (new_crtc_state && new_crtc_state->mode_changed) {
7662 pr_debug("[HDCP_DM] DESIRED->DESIRED or ENABLE->ENABLE mode_change %s :true\n",
7666 pr_debug("[HDCP_DM] DESIRED->DESIRED & ENABLE->ENABLE %s :false\n",
7671 pr_debug("[HDCP_DM] UNDESIRED->UNDESIRED %s :false\n", __func__);
7675 if (new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_ENABLED) {
7676 pr_debug("[HDCP_DM] UNDESIRED->DESIRED or DESIRED->UNDESIRED or ENABLED->UNDESIRED %s :true\n",
7681 pr_debug("[HDCP_DM] DESIRED->ENABLED %s :false\n", __func__);
7685 static void remove_stream(struct amdgpu_device *adev,
7686 struct amdgpu_crtc *acrtc,
7687 struct dc_stream_state *stream)
7689 /* this is the update mode case */
7691 acrtc->otg_inst = -1;
7692 acrtc->enabled = false;
7695 static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
7698 assert_spin_locked(&acrtc->base.dev->event_lock);
7699 WARN_ON(acrtc->event);
7701 acrtc->event = acrtc->base.state->event;
7703 /* Set the flip status */
7704 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
7706 /* Mark this event as consumed */
7707 acrtc->base.state->event = NULL;
7709 DC_LOG_PFLIP("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
7713 static void update_freesync_state_on_stream(
7714 struct amdgpu_display_manager *dm,
7715 struct dm_crtc_state *new_crtc_state,
7716 struct dc_stream_state *new_stream,
7717 struct dc_plane_state *surface,
7718 u32 flip_timestamp_in_us)
7720 struct mod_vrr_params vrr_params;
7721 struct dc_info_packet vrr_infopacket = {0};
7722 struct amdgpu_device *adev = dm->adev;
7723 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
7724 unsigned long flags;
7725 bool pack_sdp_v1_3 = false;
7726 struct amdgpu_dm_connector *aconn;
7727 enum vrr_packet_type packet_type = PACKET_TYPE_VRR;
7733 * TODO: Determine why min/max totals and vrefresh can be 0 here.
7734 * For now it's sufficient to just guard against these conditions.
7737 if (!new_stream->timing.h_total || !new_stream->timing.v_total)
7740 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
7741 vrr_params = acrtc->dm_irq_params.vrr_params;
7744 mod_freesync_handle_preflip(
7745 dm->freesync_module,
7748 flip_timestamp_in_us,
7751 if (adev->family < AMDGPU_FAMILY_AI &&
7752 amdgpu_dm_crtc_vrr_active(new_crtc_state)) {
7753 mod_freesync_handle_v_update(dm->freesync_module,
7754 new_stream, &vrr_params);
7756 /* Need to call this before the frame ends. */
7757 dc_stream_adjust_vmin_vmax(dm->dc,
7758 new_crtc_state->stream,
7759 &vrr_params.adjust);
7763 aconn = (struct amdgpu_dm_connector *)new_stream->dm_stream_context;
7765 if (aconn && aconn->as_type == FREESYNC_TYPE_PCON_IN_WHITELIST) {
7766 pack_sdp_v1_3 = aconn->pack_sdp_v1_3;
7768 if (aconn->vsdb_info.amd_vsdb_version == 1)
7769 packet_type = PACKET_TYPE_FS_V1;
7770 else if (aconn->vsdb_info.amd_vsdb_version == 2)
7771 packet_type = PACKET_TYPE_FS_V2;
7772 else if (aconn->vsdb_info.amd_vsdb_version == 3)
7773 packet_type = PACKET_TYPE_FS_V3;
7775 mod_build_adaptive_sync_infopacket(new_stream, aconn->as_type, NULL,
7776 &new_stream->adaptive_sync_infopacket);
7779 mod_freesync_build_vrr_infopacket(
7780 dm->freesync_module,
7784 TRANSFER_FUNC_UNKNOWN,
7788 new_crtc_state->freesync_vrr_info_changed |=
7789 (memcmp(&new_crtc_state->vrr_infopacket,
7791 sizeof(vrr_infopacket)) != 0);
7793 acrtc->dm_irq_params.vrr_params = vrr_params;
7794 new_crtc_state->vrr_infopacket = vrr_infopacket;
7796 new_stream->vrr_infopacket = vrr_infopacket;
7797 new_stream->allow_freesync = mod_freesync_get_freesync_enabled(&vrr_params);
7799 if (new_crtc_state->freesync_vrr_info_changed)
7800 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d",
7801 new_crtc_state->base.crtc->base.id,
7802 (int)new_crtc_state->base.vrr_enabled,
7803 (int)vrr_params.state);
7805 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
7808 static void update_stream_irq_parameters(
7809 struct amdgpu_display_manager *dm,
7810 struct dm_crtc_state *new_crtc_state)
7812 struct dc_stream_state *new_stream = new_crtc_state->stream;
7813 struct mod_vrr_params vrr_params;
7814 struct mod_freesync_config config = new_crtc_state->freesync_config;
7815 struct amdgpu_device *adev = dm->adev;
7816 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
7817 unsigned long flags;
7823 * TODO: Determine why min/max totals and vrefresh can be 0 here.
7824 * For now it's sufficient to just guard against these conditions.
7826 if (!new_stream->timing.h_total || !new_stream->timing.v_total)
7829 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
7830 vrr_params = acrtc->dm_irq_params.vrr_params;
7832 if (new_crtc_state->vrr_supported &&
7833 config.min_refresh_in_uhz &&
7834 config.max_refresh_in_uhz) {
7836 * if freesync compatible mode was set, config.state will be set
7839 if (config.state == VRR_STATE_ACTIVE_FIXED && config.fixed_refresh_in_uhz &&
7840 (!drm_atomic_crtc_needs_modeset(&new_crtc_state->base) ||
7841 new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)) {
7842 vrr_params.max_refresh_in_uhz = config.max_refresh_in_uhz;
7843 vrr_params.min_refresh_in_uhz = config.min_refresh_in_uhz;
7844 vrr_params.fixed_refresh_in_uhz = config.fixed_refresh_in_uhz;
7845 vrr_params.state = VRR_STATE_ACTIVE_FIXED;
7847 config.state = new_crtc_state->base.vrr_enabled ?
7848 VRR_STATE_ACTIVE_VARIABLE :
7852 config.state = VRR_STATE_UNSUPPORTED;
7855 mod_freesync_build_vrr_params(dm->freesync_module,
7857 &config, &vrr_params);
7859 new_crtc_state->freesync_config = config;
7860 /* Copy state for access from DM IRQ handler */
7861 acrtc->dm_irq_params.freesync_config = config;
7862 acrtc->dm_irq_params.active_planes = new_crtc_state->active_planes;
7863 acrtc->dm_irq_params.vrr_params = vrr_params;
7864 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
7867 static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state,
7868 struct dm_crtc_state *new_state)
7870 bool old_vrr_active = amdgpu_dm_crtc_vrr_active(old_state);
7871 bool new_vrr_active = amdgpu_dm_crtc_vrr_active(new_state);
7873 if (!old_vrr_active && new_vrr_active) {
7874 /* Transition VRR inactive -> active:
7875 * While VRR is active, we must not disable vblank irq, as a
7876 * reenable after disable would compute bogus vblank/pflip
7877 * timestamps if it likely happened inside display front-porch.
7879 * We also need vupdate irq for the actual core vblank handling
7882 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, true) != 0);
7883 WARN_ON(drm_crtc_vblank_get(new_state->base.crtc) != 0);
7884 DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n",
7885 __func__, new_state->base.crtc->base.id);
7886 } else if (old_vrr_active && !new_vrr_active) {
7887 /* Transition VRR active -> inactive:
7888 * Allow vblank irq disable again for fixed refresh rate.
7890 WARN_ON(amdgpu_dm_crtc_set_vupdate_irq(new_state->base.crtc, false) != 0);
7891 drm_crtc_vblank_put(new_state->base.crtc);
7892 DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n",
7893 __func__, new_state->base.crtc->base.id);
7897 static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state)
7899 struct drm_plane *plane;
7900 struct drm_plane_state *old_plane_state;
7904 * TODO: Make this per-stream so we don't issue redundant updates for
7905 * commits with multiple streams.
7907 for_each_old_plane_in_state(state, plane, old_plane_state, i)
7908 if (plane->type == DRM_PLANE_TYPE_CURSOR)
7909 amdgpu_dm_plane_handle_cursor_update(plane, old_plane_state);
7912 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
7913 struct dc_state *dc_state,
7914 struct drm_device *dev,
7915 struct amdgpu_display_manager *dm,
7916 struct drm_crtc *pcrtc,
7917 bool wait_for_vblank)
7920 u64 timestamp_ns = ktime_get_ns();
7921 struct drm_plane *plane;
7922 struct drm_plane_state *old_plane_state, *new_plane_state;
7923 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
7924 struct drm_crtc_state *new_pcrtc_state =
7925 drm_atomic_get_new_crtc_state(state, pcrtc);
7926 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
7927 struct dm_crtc_state *dm_old_crtc_state =
7928 to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
7929 int planes_count = 0, vpos, hpos;
7930 unsigned long flags;
7931 u32 target_vblank, last_flip_vblank;
7932 bool vrr_active = amdgpu_dm_crtc_vrr_active(acrtc_state);
7933 bool cursor_update = false;
7934 bool pflip_present = false;
7935 bool dirty_rects_changed = false;
7937 struct dc_surface_update surface_updates[MAX_SURFACES];
7938 struct dc_plane_info plane_infos[MAX_SURFACES];
7939 struct dc_scaling_info scaling_infos[MAX_SURFACES];
7940 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
7941 struct dc_stream_update stream_update;
7944 bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
7947 dm_error("Failed to allocate update bundle\n");
7952 * Disable the cursor first if we're disabling all the planes.
7953 * It'll remain on the screen after the planes are re-enabled
7956 if (acrtc_state->active_planes == 0)
7957 amdgpu_dm_commit_cursors(state);
7959 /* update planes when needed */
7960 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
7961 struct drm_crtc *crtc = new_plane_state->crtc;
7962 struct drm_crtc_state *new_crtc_state;
7963 struct drm_framebuffer *fb = new_plane_state->fb;
7964 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)fb;
7965 bool plane_needs_flip;
7966 struct dc_plane_state *dc_plane;
7967 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
7969 /* Cursor plane is handled after stream updates */
7970 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
7971 if ((fb && crtc == pcrtc) ||
7972 (old_plane_state->fb && old_plane_state->crtc == pcrtc))
7973 cursor_update = true;
7978 if (!fb || !crtc || pcrtc != crtc)
7981 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
7982 if (!new_crtc_state->active)
7985 dc_plane = dm_new_plane_state->dc_state;
7987 bundle->surface_updates[planes_count].surface = dc_plane;
7988 if (new_pcrtc_state->color_mgmt_changed) {
7989 bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction;
7990 bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func;
7991 bundle->surface_updates[planes_count].gamut_remap_matrix = &dc_plane->gamut_remap_matrix;
7994 amdgpu_dm_plane_fill_dc_scaling_info(dm->adev, new_plane_state,
7995 &bundle->scaling_infos[planes_count]);
7997 bundle->surface_updates[planes_count].scaling_info =
7998 &bundle->scaling_infos[planes_count];
8000 plane_needs_flip = old_plane_state->fb && new_plane_state->fb;
8002 pflip_present = pflip_present || plane_needs_flip;
8004 if (!plane_needs_flip) {
8009 fill_dc_plane_info_and_addr(
8010 dm->adev, new_plane_state,
8012 &bundle->plane_infos[planes_count],
8013 &bundle->flip_addrs[planes_count].address,
8014 afb->tmz_surface, false);
8016 drm_dbg_state(state->dev, "plane: id=%d dcc_en=%d\n",
8017 new_plane_state->plane->index,
8018 bundle->plane_infos[planes_count].dcc.enable);
8020 bundle->surface_updates[planes_count].plane_info =
8021 &bundle->plane_infos[planes_count];
8023 if (acrtc_state->stream->link->psr_settings.psr_feature_enabled) {
8024 fill_dc_dirty_rects(plane, old_plane_state,
8025 new_plane_state, new_crtc_state,
8026 &bundle->flip_addrs[planes_count],
8027 &dirty_rects_changed);
8030 * If the dirty regions changed, PSR-SU need to be disabled temporarily
8031 * and enabled it again after dirty regions are stable to avoid video glitch.
8032 * PSR-SU will be enabled in vblank_control_worker() if user pause the video
8033 * during the PSR-SU was disabled.
8035 if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
8036 acrtc_attach->dm_irq_params.allow_psr_entry &&
8037 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
8038 !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
8040 dirty_rects_changed) {
8041 mutex_lock(&dm->dc_lock);
8042 acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns =
8044 if (acrtc_state->stream->link->psr_settings.psr_allow_active)
8045 amdgpu_dm_psr_disable(acrtc_state->stream);
8046 mutex_unlock(&dm->dc_lock);
8051 * Only allow immediate flips for fast updates that don't
8052 * change FB pitch, DCC state, rotation or mirroing.
8054 bundle->flip_addrs[planes_count].flip_immediate =
8055 crtc->state->async_flip &&
8056 acrtc_state->update_type == UPDATE_TYPE_FAST;
8058 timestamp_ns = ktime_get_ns();
8059 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000);
8060 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count];
8061 bundle->surface_updates[planes_count].surface = dc_plane;
8063 if (!bundle->surface_updates[planes_count].surface) {
8064 DRM_ERROR("No surface for CRTC: id=%d\n",
8065 acrtc_attach->crtc_id);
8069 if (plane == pcrtc->primary)
8070 update_freesync_state_on_stream(
8073 acrtc_state->stream,
8075 bundle->flip_addrs[planes_count].flip_timestamp_in_us);
8077 drm_dbg_state(state->dev, "%s Flipping to hi: 0x%x, low: 0x%x\n",
8079 bundle->flip_addrs[planes_count].address.grph.addr.high_part,
8080 bundle->flip_addrs[planes_count].address.grph.addr.low_part);
8086 if (pflip_present) {
8088 /* Use old throttling in non-vrr fixed refresh rate mode
8089 * to keep flip scheduling based on target vblank counts
8090 * working in a backwards compatible way, e.g., for
8091 * clients using the GLX_OML_sync_control extension or
8092 * DRI3/Present extension with defined target_msc.
8094 last_flip_vblank = amdgpu_get_vblank_counter_kms(pcrtc);
8097 /* For variable refresh rate mode only:
8098 * Get vblank of last completed flip to avoid > 1 vrr
8099 * flips per video frame by use of throttling, but allow
8100 * flip programming anywhere in the possibly large
8101 * variable vrr vblank interval for fine-grained flip
8102 * timing control and more opportunity to avoid stutter
8103 * on late submission of flips.
8105 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8106 last_flip_vblank = acrtc_attach->dm_irq_params.last_flip_vblank;
8107 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8110 target_vblank = last_flip_vblank + wait_for_vblank;
8113 * Wait until we're out of the vertical blank period before the one
8114 * targeted by the flip
8116 while ((acrtc_attach->enabled &&
8117 (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id,
8118 0, &vpos, &hpos, NULL,
8119 NULL, &pcrtc->hwmode)
8120 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
8121 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
8122 (int)(target_vblank -
8123 amdgpu_get_vblank_counter_kms(pcrtc)) > 0)) {
8124 usleep_range(1000, 1100);
8128 * Prepare the flip event for the pageflip interrupt to handle.
8130 * This only works in the case where we've already turned on the
8131 * appropriate hardware blocks (eg. HUBP) so in the transition case
8132 * from 0 -> n planes we have to skip a hardware generated event
8133 * and rely on sending it from software.
8135 if (acrtc_attach->base.state->event &&
8136 acrtc_state->active_planes > 0) {
8137 drm_crtc_vblank_get(pcrtc);
8139 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8141 WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE);
8142 prepare_flip_isr(acrtc_attach);
8144 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8147 if (acrtc_state->stream) {
8148 if (acrtc_state->freesync_vrr_info_changed)
8149 bundle->stream_update.vrr_infopacket =
8150 &acrtc_state->stream->vrr_infopacket;
8152 } else if (cursor_update && acrtc_state->active_planes > 0 &&
8153 acrtc_attach->base.state->event) {
8154 drm_crtc_vblank_get(pcrtc);
8156 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8158 acrtc_attach->event = acrtc_attach->base.state->event;
8159 acrtc_attach->base.state->event = NULL;
8161 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8164 /* Update the planes if changed or disable if we don't have any. */
8165 if ((planes_count || acrtc_state->active_planes == 0) &&
8166 acrtc_state->stream) {
8168 * If PSR or idle optimizations are enabled then flush out
8169 * any pending work before hardware programming.
8171 if (dm->vblank_control_workqueue)
8172 flush_workqueue(dm->vblank_control_workqueue);
8174 bundle->stream_update.stream = acrtc_state->stream;
8175 if (new_pcrtc_state->mode_changed) {
8176 bundle->stream_update.src = acrtc_state->stream->src;
8177 bundle->stream_update.dst = acrtc_state->stream->dst;
8180 if (new_pcrtc_state->color_mgmt_changed) {
8182 * TODO: This isn't fully correct since we've actually
8183 * already modified the stream in place.
8185 bundle->stream_update.gamut_remap =
8186 &acrtc_state->stream->gamut_remap_matrix;
8187 bundle->stream_update.output_csc_transform =
8188 &acrtc_state->stream->csc_color_matrix;
8189 bundle->stream_update.out_transfer_func =
8190 acrtc_state->stream->out_transfer_func;
8193 acrtc_state->stream->abm_level = acrtc_state->abm_level;
8194 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level)
8195 bundle->stream_update.abm_level = &acrtc_state->abm_level;
8198 * If FreeSync state on the stream has changed then we need to
8199 * re-adjust the min/max bounds now that DC doesn't handle this
8200 * as part of commit.
8202 if (is_dc_timing_adjust_needed(dm_old_crtc_state, acrtc_state)) {
8203 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
8204 dc_stream_adjust_vmin_vmax(
8205 dm->dc, acrtc_state->stream,
8206 &acrtc_attach->dm_irq_params.vrr_params.adjust);
8207 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
8209 mutex_lock(&dm->dc_lock);
8210 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
8211 acrtc_state->stream->link->psr_settings.psr_allow_active)
8212 amdgpu_dm_psr_disable(acrtc_state->stream);
8214 update_planes_and_stream_adapter(dm->dc,
8215 acrtc_state->update_type,
8217 acrtc_state->stream,
8218 &bundle->stream_update,
8219 bundle->surface_updates);
8222 * Enable or disable the interrupts on the backend.
8224 * Most pipes are put into power gating when unused.
8226 * When power gating is enabled on a pipe we lose the
8227 * interrupt enablement state when power gating is disabled.
8229 * So we need to update the IRQ control state in hardware
8230 * whenever the pipe turns on (since it could be previously
8231 * power gated) or off (since some pipes can't be power gated
8234 if (dm_old_crtc_state->active_planes != acrtc_state->active_planes)
8235 dm_update_pflip_irq_state(drm_to_adev(dev),
8238 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
8239 acrtc_state->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED &&
8240 !acrtc_state->stream->link->psr_settings.psr_feature_enabled)
8241 amdgpu_dm_link_setup_psr(acrtc_state->stream);
8243 /* Decrement skip count when PSR is enabled and we're doing fast updates. */
8244 if (acrtc_state->update_type == UPDATE_TYPE_FAST &&
8245 acrtc_state->stream->link->psr_settings.psr_feature_enabled) {
8246 struct amdgpu_dm_connector *aconn =
8247 (struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context;
8249 if (aconn->psr_skip_count > 0)
8250 aconn->psr_skip_count--;
8252 /* Allow PSR when skip count is 0. */
8253 acrtc_attach->dm_irq_params.allow_psr_entry = !aconn->psr_skip_count;
8256 * If sink supports PSR SU, there is no need to rely on
8257 * a vblank event disable request to enable PSR. PSR SU
8258 * can be enabled immediately once OS demonstrates an
8259 * adequate number of fast atomic commits to notify KMD
8260 * of update events. See `vblank_control_worker()`.
8262 if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
8263 acrtc_attach->dm_irq_params.allow_psr_entry &&
8264 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
8265 !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
8267 !acrtc_state->stream->link->psr_settings.psr_allow_active &&
8269 acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns) >
8271 amdgpu_dm_psr_enable(acrtc_state->stream);
8273 acrtc_attach->dm_irq_params.allow_psr_entry = false;
8276 mutex_unlock(&dm->dc_lock);
8280 * Update cursor state *after* programming all the planes.
8281 * This avoids redundant programming in the case where we're going
8282 * to be disabling a single plane - those pipes are being disabled.
8284 if (acrtc_state->active_planes)
8285 amdgpu_dm_commit_cursors(state);
8291 static void amdgpu_dm_commit_audio(struct drm_device *dev,
8292 struct drm_atomic_state *state)
8294 struct amdgpu_device *adev = drm_to_adev(dev);
8295 struct amdgpu_dm_connector *aconnector;
8296 struct drm_connector *connector;
8297 struct drm_connector_state *old_con_state, *new_con_state;
8298 struct drm_crtc_state *new_crtc_state;
8299 struct dm_crtc_state *new_dm_crtc_state;
8300 const struct dc_stream_status *status;
8303 /* Notify device removals. */
8304 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8305 if (old_con_state->crtc != new_con_state->crtc) {
8306 /* CRTC changes require notification. */
8310 if (!new_con_state->crtc)
8313 new_crtc_state = drm_atomic_get_new_crtc_state(
8314 state, new_con_state->crtc);
8316 if (!new_crtc_state)
8319 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8323 aconnector = to_amdgpu_dm_connector(connector);
8325 mutex_lock(&adev->dm.audio_lock);
8326 inst = aconnector->audio_inst;
8327 aconnector->audio_inst = -1;
8328 mutex_unlock(&adev->dm.audio_lock);
8330 amdgpu_dm_audio_eld_notify(adev, inst);
8333 /* Notify audio device additions. */
8334 for_each_new_connector_in_state(state, connector, new_con_state, i) {
8335 if (!new_con_state->crtc)
8338 new_crtc_state = drm_atomic_get_new_crtc_state(
8339 state, new_con_state->crtc);
8341 if (!new_crtc_state)
8344 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8347 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
8348 if (!new_dm_crtc_state->stream)
8351 status = dc_stream_get_status(new_dm_crtc_state->stream);
8355 aconnector = to_amdgpu_dm_connector(connector);
8357 mutex_lock(&adev->dm.audio_lock);
8358 inst = status->audio_inst;
8359 aconnector->audio_inst = inst;
8360 mutex_unlock(&adev->dm.audio_lock);
8362 amdgpu_dm_audio_eld_notify(adev, inst);
8367 * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
8368 * @crtc_state: the DRM CRTC state
8369 * @stream_state: the DC stream state.
8371 * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
8372 * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
8374 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
8375 struct dc_stream_state *stream_state)
8377 stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state);
8381 * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation.
8382 * @state: The atomic state to commit
8384 * This will tell DC to commit the constructed DC state from atomic_check,
8385 * programming the hardware. Any failures here implies a hardware failure, since
8386 * atomic check should have filtered anything non-kosher.
8388 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
8390 struct drm_device *dev = state->dev;
8391 struct amdgpu_device *adev = drm_to_adev(dev);
8392 struct amdgpu_display_manager *dm = &adev->dm;
8393 struct dm_atomic_state *dm_state;
8394 struct dc_state *dc_state = NULL, *dc_state_temp = NULL;
8396 struct drm_crtc *crtc;
8397 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
8398 unsigned long flags;
8399 bool wait_for_vblank = true;
8400 struct drm_connector *connector;
8401 struct drm_connector_state *old_con_state, *new_con_state;
8402 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
8403 int crtc_disable_count = 0;
8404 bool mode_set_reset_required = false;
8407 trace_amdgpu_dm_atomic_commit_tail_begin(state);
8409 r = drm_atomic_helper_wait_for_fences(dev, state, false);
8411 DRM_ERROR("Waiting for fences timed out!");
8413 drm_atomic_helper_update_legacy_modeset_state(dev, state);
8414 drm_dp_mst_atomic_wait_for_dependencies(state);
8416 dm_state = dm_atomic_get_new_state(state);
8417 if (dm_state && dm_state->context) {
8418 dc_state = dm_state->context;
8420 /* No state changes, retain current state. */
8421 dc_state_temp = dc_create_state(dm->dc);
8422 ASSERT(dc_state_temp);
8423 dc_state = dc_state_temp;
8424 dc_resource_state_copy_construct_current(dm->dc, dc_state);
8427 for_each_oldnew_crtc_in_state (state, crtc, old_crtc_state,
8428 new_crtc_state, i) {
8429 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8431 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8433 if (old_crtc_state->active &&
8434 (!new_crtc_state->active ||
8435 drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8436 manage_dm_interrupts(adev, acrtc, false);
8437 dc_stream_release(dm_old_crtc_state->stream);
8441 drm_atomic_helper_calc_timestamping_constants(state);
8443 /* update changed items */
8444 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
8445 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8447 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8448 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8450 drm_dbg_state(state->dev,
8451 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
8452 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
8453 "connectors_changed:%d\n",
8455 new_crtc_state->enable,
8456 new_crtc_state->active,
8457 new_crtc_state->planes_changed,
8458 new_crtc_state->mode_changed,
8459 new_crtc_state->active_changed,
8460 new_crtc_state->connectors_changed);
8462 /* Disable cursor if disabling crtc */
8463 if (old_crtc_state->active && !new_crtc_state->active) {
8464 struct dc_cursor_position position;
8466 memset(&position, 0, sizeof(position));
8467 mutex_lock(&dm->dc_lock);
8468 dc_stream_set_cursor_position(dm_old_crtc_state->stream, &position);
8469 mutex_unlock(&dm->dc_lock);
8472 /* Copy all transient state flags into dc state */
8473 if (dm_new_crtc_state->stream) {
8474 amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
8475 dm_new_crtc_state->stream);
8478 /* handles headless hotplug case, updating new_state and
8479 * aconnector as needed
8482 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
8484 DRM_DEBUG_ATOMIC("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
8486 if (!dm_new_crtc_state->stream) {
8488 * this could happen because of issues with
8489 * userspace notifications delivery.
8490 * In this case userspace tries to set mode on
8491 * display which is disconnected in fact.
8492 * dc_sink is NULL in this case on aconnector.
8493 * We expect reset mode will come soon.
8495 * This can also happen when unplug is done
8496 * during resume sequence ended
8498 * In this case, we want to pretend we still
8499 * have a sink to keep the pipe running so that
8500 * hw state is consistent with the sw state
8502 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
8503 __func__, acrtc->base.base.id);
8507 if (dm_old_crtc_state->stream)
8508 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
8510 pm_runtime_get_noresume(dev->dev);
8512 acrtc->enabled = true;
8513 acrtc->hw_mode = new_crtc_state->mode;
8514 crtc->hwmode = new_crtc_state->mode;
8515 mode_set_reset_required = true;
8516 } else if (modereset_required(new_crtc_state)) {
8517 DRM_DEBUG_ATOMIC("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
8518 /* i.e. reset mode */
8519 if (dm_old_crtc_state->stream)
8520 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
8522 mode_set_reset_required = true;
8524 } /* for_each_crtc_in_state() */
8527 /* if there mode set or reset, disable eDP PSR */
8528 if (mode_set_reset_required) {
8529 if (dm->vblank_control_workqueue)
8530 flush_workqueue(dm->vblank_control_workqueue);
8532 amdgpu_dm_psr_disable_all(dm);
8535 dm_enable_per_frame_crtc_master_sync(dc_state);
8536 mutex_lock(&dm->dc_lock);
8537 WARN_ON(!dc_commit_streams(dm->dc, dc_state->streams, dc_state->stream_count));
8539 /* Allow idle optimization when vblank count is 0 for display off */
8540 if (dm->active_vblank_irq_count == 0)
8541 dc_allow_idle_optimizations(dm->dc, true);
8542 mutex_unlock(&dm->dc_lock);
8545 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
8546 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8548 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8550 if (dm_new_crtc_state->stream != NULL) {
8551 const struct dc_stream_status *status =
8552 dc_stream_get_status(dm_new_crtc_state->stream);
8555 status = dc_stream_get_status_from_state(dc_state,
8556 dm_new_crtc_state->stream);
8558 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc);
8560 acrtc->otg_inst = status->primary_otg_inst;
8563 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8564 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8565 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8566 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8568 pr_debug("[HDCP_DM] -------------- i : %x ----------\n", i);
8573 pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n",
8574 connector->index, connector->status, connector->dpms);
8575 pr_debug("[HDCP_DM] state protection old: %x new: %x\n",
8576 old_con_state->content_protection, new_con_state->content_protection);
8578 if (aconnector->dc_sink) {
8579 if (aconnector->dc_sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&
8580 aconnector->dc_sink->sink_signal != SIGNAL_TYPE_NONE) {
8581 pr_debug("[HDCP_DM] pipe_ctx dispname=%s\n",
8582 aconnector->dc_sink->edid_caps.display_name);
8586 new_crtc_state = NULL;
8587 old_crtc_state = NULL;
8590 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8591 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8595 pr_debug("old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
8596 old_crtc_state->enable,
8597 old_crtc_state->active,
8598 old_crtc_state->mode_changed,
8599 old_crtc_state->active_changed,
8600 old_crtc_state->connectors_changed);
8603 pr_debug("NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
8604 new_crtc_state->enable,
8605 new_crtc_state->active,
8606 new_crtc_state->mode_changed,
8607 new_crtc_state->active_changed,
8608 new_crtc_state->connectors_changed);
8611 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8612 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8613 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8614 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8616 new_crtc_state = NULL;
8617 old_crtc_state = NULL;
8620 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8621 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8624 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8626 if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL &&
8627 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) {
8628 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
8629 new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
8630 dm_new_con_state->update_hdcp = true;
8634 if (is_content_protection_different(new_crtc_state, old_crtc_state, new_con_state,
8635 old_con_state, connector, adev->dm.hdcp_workqueue)) {
8636 /* when display is unplugged from mst hub, connctor will
8637 * be destroyed within dm_dp_mst_connector_destroy. connector
8638 * hdcp perperties, like type, undesired, desired, enabled,
8639 * will be lost. So, save hdcp properties into hdcp_work within
8640 * amdgpu_dm_atomic_commit_tail. if the same display is
8641 * plugged back with same display index, its hdcp properties
8642 * will be retrieved from hdcp_work within dm_dp_mst_get_modes
8645 bool enable_encryption = false;
8647 if (new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED)
8648 enable_encryption = true;
8650 if (aconnector->dc_link && aconnector->dc_sink &&
8651 aconnector->dc_link->type == dc_connection_mst_branch) {
8652 struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue;
8653 struct hdcp_workqueue *hdcp_w =
8654 &hdcp_work[aconnector->dc_link->link_index];
8656 hdcp_w->hdcp_content_type[connector->index] =
8657 new_con_state->hdcp_content_type;
8658 hdcp_w->content_protection[connector->index] =
8659 new_con_state->content_protection;
8662 if (new_crtc_state && new_crtc_state->mode_changed &&
8663 new_con_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED)
8664 enable_encryption = true;
8666 DRM_INFO("[HDCP_DM] hdcp_update_display enable_encryption = %x\n", enable_encryption);
8668 hdcp_update_display(
8669 adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector,
8670 new_con_state->hdcp_content_type, enable_encryption);
8674 /* Handle connector state changes */
8675 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8676 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8677 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
8678 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8679 struct dc_surface_update dummy_updates[MAX_SURFACES];
8680 struct dc_stream_update stream_update;
8681 struct dc_info_packet hdr_packet;
8682 struct dc_stream_status *status = NULL;
8683 bool abm_changed, hdr_changed, scaling_changed;
8685 memset(&dummy_updates, 0, sizeof(dummy_updates));
8686 memset(&stream_update, 0, sizeof(stream_update));
8689 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8690 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8693 /* Skip any modesets/resets */
8694 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
8697 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8698 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8700 scaling_changed = is_scaling_state_different(dm_new_con_state,
8703 abm_changed = dm_new_crtc_state->abm_level !=
8704 dm_old_crtc_state->abm_level;
8707 !drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state);
8709 if (!scaling_changed && !abm_changed && !hdr_changed)
8712 stream_update.stream = dm_new_crtc_state->stream;
8713 if (scaling_changed) {
8714 update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
8715 dm_new_con_state, dm_new_crtc_state->stream);
8717 stream_update.src = dm_new_crtc_state->stream->src;
8718 stream_update.dst = dm_new_crtc_state->stream->dst;
8722 dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level;
8724 stream_update.abm_level = &dm_new_crtc_state->abm_level;
8728 fill_hdr_info_packet(new_con_state, &hdr_packet);
8729 stream_update.hdr_static_metadata = &hdr_packet;
8732 status = dc_stream_get_status(dm_new_crtc_state->stream);
8734 if (WARN_ON(!status))
8737 WARN_ON(!status->plane_count);
8740 * TODO: DC refuses to perform stream updates without a dc_surface_update.
8741 * Here we create an empty update on each plane.
8742 * To fix this, DC should permit updating only stream properties.
8744 for (j = 0; j < status->plane_count; j++)
8745 dummy_updates[j].surface = status->plane_states[0];
8748 mutex_lock(&dm->dc_lock);
8749 dc_update_planes_and_stream(dm->dc,
8751 status->plane_count,
8752 dm_new_crtc_state->stream,
8754 mutex_unlock(&dm->dc_lock);
8758 * Enable interrupts for CRTCs that are newly enabled or went through
8759 * a modeset. It was intentionally deferred until after the front end
8760 * state was modified to wait until the OTG was on and so the IRQ
8761 * handlers didn't access stale or invalid state.
8763 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
8764 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8765 #ifdef CONFIG_DEBUG_FS
8766 enum amdgpu_dm_pipe_crc_source cur_crc_src;
8768 /* Count number of newly disabled CRTCs for dropping PM refs later. */
8769 if (old_crtc_state->active && !new_crtc_state->active)
8770 crtc_disable_count++;
8772 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8773 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8775 /* For freesync config update on crtc state and params for irq */
8776 update_stream_irq_parameters(dm, dm_new_crtc_state);
8778 #ifdef CONFIG_DEBUG_FS
8779 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8780 cur_crc_src = acrtc->dm_irq_params.crc_src;
8781 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8784 if (new_crtc_state->active &&
8785 (!old_crtc_state->active ||
8786 drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8787 dc_stream_retain(dm_new_crtc_state->stream);
8788 acrtc->dm_irq_params.stream = dm_new_crtc_state->stream;
8789 manage_dm_interrupts(adev, acrtc, true);
8791 /* Handle vrr on->off / off->on transitions */
8792 amdgpu_dm_handle_vrr_transition(dm_old_crtc_state, dm_new_crtc_state);
8794 #ifdef CONFIG_DEBUG_FS
8795 if (new_crtc_state->active &&
8796 (!old_crtc_state->active ||
8797 drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8799 * Frontend may have changed so reapply the CRC capture
8800 * settings for the stream.
8802 if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) {
8803 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
8804 if (amdgpu_dm_crc_window_is_activated(crtc)) {
8805 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8806 acrtc->dm_irq_params.window_param.update_win = true;
8809 * It takes 2 frames for HW to stably generate CRC when
8810 * resuming from suspend, so we set skip_frame_cnt 2.
8812 acrtc->dm_irq_params.window_param.skip_frame_cnt = 2;
8813 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8816 if (amdgpu_dm_crtc_configure_crc_source(
8817 crtc, dm_new_crtc_state, cur_crc_src))
8818 DRM_DEBUG_DRIVER("Failed to configure crc source");
8824 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j)
8825 if (new_crtc_state->async_flip)
8826 wait_for_vblank = false;
8828 /* update planes when needed per crtc*/
8829 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
8830 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8832 if (dm_new_crtc_state->stream)
8833 amdgpu_dm_commit_planes(state, dc_state, dev,
8834 dm, crtc, wait_for_vblank);
8837 /* Update audio instances for each connector. */
8838 amdgpu_dm_commit_audio(dev, state);
8840 /* restore the backlight level */
8841 for (i = 0; i < dm->num_of_edps; i++) {
8842 if (dm->backlight_dev[i] &&
8843 (dm->actual_brightness[i] != dm->brightness[i]))
8844 amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]);
8848 * send vblank event on all events not handled in flip and
8849 * mark consumed event for drm_atomic_helper_commit_hw_done
8851 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8852 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
8854 if (new_crtc_state->event)
8855 drm_send_event_locked(dev, &new_crtc_state->event->base);
8857 new_crtc_state->event = NULL;
8859 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8861 /* Signal HW programming completion */
8862 drm_atomic_helper_commit_hw_done(state);
8864 if (wait_for_vblank)
8865 drm_atomic_helper_wait_for_flip_done(dev, state);
8867 drm_atomic_helper_cleanup_planes(dev, state);
8869 /* return the stolen vga memory back to VRAM */
8870 if (!adev->mman.keep_stolen_vga_memory)
8871 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
8872 amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
8875 * Finally, drop a runtime PM reference for each newly disabled CRTC,
8876 * so we can put the GPU into runtime suspend if we're not driving any
8879 for (i = 0; i < crtc_disable_count; i++)
8880 pm_runtime_put_autosuspend(dev->dev);
8881 pm_runtime_mark_last_busy(dev->dev);
8884 dc_release_state(dc_state_temp);
8887 static int dm_force_atomic_commit(struct drm_connector *connector)
8890 struct drm_device *ddev = connector->dev;
8891 struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
8892 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
8893 struct drm_plane *plane = disconnected_acrtc->base.primary;
8894 struct drm_connector_state *conn_state;
8895 struct drm_crtc_state *crtc_state;
8896 struct drm_plane_state *plane_state;
8901 state->acquire_ctx = ddev->mode_config.acquire_ctx;
8903 /* Construct an atomic state to restore previous display setting */
8906 * Attach connectors to drm_atomic_state
8908 conn_state = drm_atomic_get_connector_state(state, connector);
8910 ret = PTR_ERR_OR_ZERO(conn_state);
8914 /* Attach crtc to drm_atomic_state*/
8915 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
8917 ret = PTR_ERR_OR_ZERO(crtc_state);
8921 /* force a restore */
8922 crtc_state->mode_changed = true;
8924 /* Attach plane to drm_atomic_state */
8925 plane_state = drm_atomic_get_plane_state(state, plane);
8927 ret = PTR_ERR_OR_ZERO(plane_state);
8931 /* Call commit internally with the state we just constructed */
8932 ret = drm_atomic_commit(state);
8935 drm_atomic_state_put(state);
8937 DRM_ERROR("Restoring old state failed with %i\n", ret);
8943 * This function handles all cases when set mode does not come upon hotplug.
8944 * This includes when a display is unplugged then plugged back into the
8945 * same port and when running without usermode desktop manager supprot
8947 void dm_restore_drm_connector_state(struct drm_device *dev,
8948 struct drm_connector *connector)
8950 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8951 struct amdgpu_crtc *disconnected_acrtc;
8952 struct dm_crtc_state *acrtc_state;
8954 if (!aconnector->dc_sink || !connector->state || !connector->encoder)
8957 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
8958 if (!disconnected_acrtc)
8961 acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
8962 if (!acrtc_state->stream)
8966 * If the previous sink is not released and different from the current,
8967 * we deduce we are in a state where we can not rely on usermode call
8968 * to turn on the display, so we do it here
8970 if (acrtc_state->stream->sink != aconnector->dc_sink)
8971 dm_force_atomic_commit(&aconnector->base);
8975 * Grabs all modesetting locks to serialize against any blocking commits,
8976 * Waits for completion of all non blocking commits.
8978 static int do_aquire_global_lock(struct drm_device *dev,
8979 struct drm_atomic_state *state)
8981 struct drm_crtc *crtc;
8982 struct drm_crtc_commit *commit;
8986 * Adding all modeset locks to aquire_ctx will
8987 * ensure that when the framework release it the
8988 * extra locks we are locking here will get released to
8990 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
8994 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8995 spin_lock(&crtc->commit_lock);
8996 commit = list_first_entry_or_null(&crtc->commit_list,
8997 struct drm_crtc_commit, commit_entry);
8999 drm_crtc_commit_get(commit);
9000 spin_unlock(&crtc->commit_lock);
9006 * Make sure all pending HW programming completed and
9009 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
9012 ret = wait_for_completion_interruptible_timeout(
9013 &commit->flip_done, 10*HZ);
9016 DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
9017 "timed out\n", crtc->base.id, crtc->name);
9019 drm_crtc_commit_put(commit);
9022 return ret < 0 ? ret : 0;
9025 static void get_freesync_config_for_crtc(
9026 struct dm_crtc_state *new_crtc_state,
9027 struct dm_connector_state *new_con_state)
9029 struct mod_freesync_config config = {0};
9030 struct amdgpu_dm_connector *aconnector =
9031 to_amdgpu_dm_connector(new_con_state->base.connector);
9032 struct drm_display_mode *mode = &new_crtc_state->base.mode;
9033 int vrefresh = drm_mode_vrefresh(mode);
9034 bool fs_vid_mode = false;
9036 new_crtc_state->vrr_supported = new_con_state->freesync_capable &&
9037 vrefresh >= aconnector->min_vfreq &&
9038 vrefresh <= aconnector->max_vfreq;
9040 if (new_crtc_state->vrr_supported) {
9041 new_crtc_state->stream->ignore_msa_timing_param = true;
9042 fs_vid_mode = new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
9044 config.min_refresh_in_uhz = aconnector->min_vfreq * 1000000;
9045 config.max_refresh_in_uhz = aconnector->max_vfreq * 1000000;
9046 config.vsif_supported = true;
9050 config.state = VRR_STATE_ACTIVE_FIXED;
9051 config.fixed_refresh_in_uhz = new_crtc_state->freesync_config.fixed_refresh_in_uhz;
9053 } else if (new_crtc_state->base.vrr_enabled) {
9054 config.state = VRR_STATE_ACTIVE_VARIABLE;
9056 config.state = VRR_STATE_INACTIVE;
9060 new_crtc_state->freesync_config = config;
9063 static void reset_freesync_config_for_crtc(
9064 struct dm_crtc_state *new_crtc_state)
9066 new_crtc_state->vrr_supported = false;
9068 memset(&new_crtc_state->vrr_infopacket, 0,
9069 sizeof(new_crtc_state->vrr_infopacket));
9073 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
9074 struct drm_crtc_state *new_crtc_state)
9076 const struct drm_display_mode *old_mode, *new_mode;
9078 if (!old_crtc_state || !new_crtc_state)
9081 old_mode = &old_crtc_state->mode;
9082 new_mode = &new_crtc_state->mode;
9084 if (old_mode->clock == new_mode->clock &&
9085 old_mode->hdisplay == new_mode->hdisplay &&
9086 old_mode->vdisplay == new_mode->vdisplay &&
9087 old_mode->htotal == new_mode->htotal &&
9088 old_mode->vtotal != new_mode->vtotal &&
9089 old_mode->hsync_start == new_mode->hsync_start &&
9090 old_mode->vsync_start != new_mode->vsync_start &&
9091 old_mode->hsync_end == new_mode->hsync_end &&
9092 old_mode->vsync_end != new_mode->vsync_end &&
9093 old_mode->hskew == new_mode->hskew &&
9094 old_mode->vscan == new_mode->vscan &&
9095 (old_mode->vsync_end - old_mode->vsync_start) ==
9096 (new_mode->vsync_end - new_mode->vsync_start))
9102 static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state) {
9104 struct drm_crtc_state *new_crtc_state = &dm_new_crtc_state->base;
9106 dm_new_crtc_state->freesync_config.state = VRR_STATE_ACTIVE_FIXED;
9108 num = (unsigned long long)new_crtc_state->mode.clock * 1000 * 1000000;
9109 den = (unsigned long long)new_crtc_state->mode.htotal *
9110 (unsigned long long)new_crtc_state->mode.vtotal;
9112 res = div_u64(num, den);
9113 dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = res;
9116 static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
9117 struct drm_atomic_state *state,
9118 struct drm_crtc *crtc,
9119 struct drm_crtc_state *old_crtc_state,
9120 struct drm_crtc_state *new_crtc_state,
9122 bool *lock_and_validation_needed)
9124 struct dm_atomic_state *dm_state = NULL;
9125 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
9126 struct dc_stream_state *new_stream;
9130 * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set
9131 * update changed items
9133 struct amdgpu_crtc *acrtc = NULL;
9134 struct amdgpu_dm_connector *aconnector = NULL;
9135 struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL;
9136 struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL;
9140 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9141 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9142 acrtc = to_amdgpu_crtc(crtc);
9143 aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
9145 /* TODO This hack should go away */
9146 if (aconnector && enable) {
9147 /* Make sure fake sink is created in plug-in scenario */
9148 drm_new_conn_state = drm_atomic_get_new_connector_state(state,
9150 drm_old_conn_state = drm_atomic_get_old_connector_state(state,
9153 if (IS_ERR(drm_new_conn_state)) {
9154 ret = PTR_ERR_OR_ZERO(drm_new_conn_state);
9158 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
9159 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state);
9161 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9164 new_stream = create_validate_stream_for_sink(aconnector,
9165 &new_crtc_state->mode,
9167 dm_old_crtc_state->stream);
9170 * we can have no stream on ACTION_SET if a display
9171 * was disconnected during S3, in this case it is not an
9172 * error, the OS will be updated after detection, and
9173 * will do the right thing on next atomic commit
9177 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
9178 __func__, acrtc->base.base.id);
9184 * TODO: Check VSDB bits to decide whether this should
9185 * be enabled or not.
9187 new_stream->triggered_crtc_reset.enabled =
9188 dm->force_timing_sync;
9190 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
9192 ret = fill_hdr_info_packet(drm_new_conn_state,
9193 &new_stream->hdr_static_metadata);
9198 * If we already removed the old stream from the context
9199 * (and set the new stream to NULL) then we can't reuse
9200 * the old stream even if the stream and scaling are unchanged.
9201 * We'll hit the BUG_ON and black screen.
9203 * TODO: Refactor this function to allow this check to work
9204 * in all conditions.
9206 if (amdgpu_freesync_vid_mode &&
9207 dm_new_crtc_state->stream &&
9208 is_timing_unchanged_for_freesync(new_crtc_state, old_crtc_state))
9211 if (dm_new_crtc_state->stream &&
9212 dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
9213 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
9214 new_crtc_state->mode_changed = false;
9215 DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
9216 new_crtc_state->mode_changed);
9220 /* mode_changed flag may get updated above, need to check again */
9221 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
9224 drm_dbg_state(state->dev,
9225 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
9226 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
9227 "connectors_changed:%d\n",
9229 new_crtc_state->enable,
9230 new_crtc_state->active,
9231 new_crtc_state->planes_changed,
9232 new_crtc_state->mode_changed,
9233 new_crtc_state->active_changed,
9234 new_crtc_state->connectors_changed);
9236 /* Remove stream for any changed/disabled CRTC */
9239 if (!dm_old_crtc_state->stream)
9242 /* Unset freesync video if it was active before */
9243 if (dm_old_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) {
9244 dm_new_crtc_state->freesync_config.state = VRR_STATE_INACTIVE;
9245 dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = 0;
9248 /* Now check if we should set freesync video mode */
9249 if (amdgpu_freesync_vid_mode && dm_new_crtc_state->stream &&
9250 is_timing_unchanged_for_freesync(new_crtc_state,
9252 new_crtc_state->mode_changed = false;
9254 "Mode change not required for front porch change, "
9255 "setting mode_changed to %d",
9256 new_crtc_state->mode_changed);
9258 set_freesync_fixed_config(dm_new_crtc_state);
9261 } else if (amdgpu_freesync_vid_mode && aconnector &&
9262 is_freesync_video_mode(&new_crtc_state->mode,
9264 struct drm_display_mode *high_mode;
9266 high_mode = get_highest_refresh_rate_mode(aconnector, false);
9267 if (!drm_mode_equal(&new_crtc_state->mode, high_mode)) {
9268 set_freesync_fixed_config(dm_new_crtc_state);
9272 ret = dm_atomic_get_state(state, &dm_state);
9276 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
9279 /* i.e. reset mode */
9280 if (dc_remove_stream_from_ctx(
9283 dm_old_crtc_state->stream) != DC_OK) {
9288 dc_stream_release(dm_old_crtc_state->stream);
9289 dm_new_crtc_state->stream = NULL;
9291 reset_freesync_config_for_crtc(dm_new_crtc_state);
9293 *lock_and_validation_needed = true;
9295 } else {/* Add stream for any updated/enabled CRTC */
9297 * Quick fix to prevent NULL pointer on new_stream when
9298 * added MST connectors not found in existing crtc_state in the chained mode
9299 * TODO: need to dig out the root cause of that
9304 if (modereset_required(new_crtc_state))
9307 if (amdgpu_dm_crtc_modeset_required(new_crtc_state, new_stream,
9308 dm_old_crtc_state->stream)) {
9310 WARN_ON(dm_new_crtc_state->stream);
9312 ret = dm_atomic_get_state(state, &dm_state);
9316 dm_new_crtc_state->stream = new_stream;
9318 dc_stream_retain(new_stream);
9320 DRM_DEBUG_ATOMIC("Enabling DRM crtc: %d\n",
9323 if (dc_add_stream_to_ctx(
9326 dm_new_crtc_state->stream) != DC_OK) {
9331 *lock_and_validation_needed = true;
9336 /* Release extra reference */
9338 dc_stream_release(new_stream);
9341 * We want to do dc stream updates that do not require a
9342 * full modeset below.
9344 if (!(enable && aconnector && new_crtc_state->active))
9347 * Given above conditions, the dc state cannot be NULL because:
9348 * 1. We're in the process of enabling CRTCs (just been added
9349 * to the dc context, or already is on the context)
9350 * 2. Has a valid connector attached, and
9351 * 3. Is currently active and enabled.
9352 * => The dc stream state currently exists.
9354 BUG_ON(dm_new_crtc_state->stream == NULL);
9356 /* Scaling or underscan settings */
9357 if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state) ||
9358 drm_atomic_crtc_needs_modeset(new_crtc_state))
9359 update_stream_scaling_settings(
9360 &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);
9363 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
9366 * Color management settings. We also update color properties
9367 * when a modeset is needed, to ensure it gets reprogrammed.
9369 if (dm_new_crtc_state->base.color_mgmt_changed ||
9370 drm_atomic_crtc_needs_modeset(new_crtc_state)) {
9371 ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state);
9376 /* Update Freesync settings. */
9377 get_freesync_config_for_crtc(dm_new_crtc_state,
9384 dc_stream_release(new_stream);
9388 static bool should_reset_plane(struct drm_atomic_state *state,
9389 struct drm_plane *plane,
9390 struct drm_plane_state *old_plane_state,
9391 struct drm_plane_state *new_plane_state)
9393 struct drm_plane *other;
9394 struct drm_plane_state *old_other_state, *new_other_state;
9395 struct drm_crtc_state *new_crtc_state;
9399 * TODO: Remove this hack once the checks below are sufficient
9400 * enough to determine when we need to reset all the planes on
9403 if (state->allow_modeset)
9406 /* Exit early if we know that we're adding or removing the plane. */
9407 if (old_plane_state->crtc != new_plane_state->crtc)
9410 /* old crtc == new_crtc == NULL, plane not in context. */
9411 if (!new_plane_state->crtc)
9415 drm_atomic_get_new_crtc_state(state, new_plane_state->crtc);
9417 if (!new_crtc_state)
9420 /* CRTC Degamma changes currently require us to recreate planes. */
9421 if (new_crtc_state->color_mgmt_changed)
9424 if (drm_atomic_crtc_needs_modeset(new_crtc_state))
9428 * If there are any new primary or overlay planes being added or
9429 * removed then the z-order can potentially change. To ensure
9430 * correct z-order and pipe acquisition the current DC architecture
9431 * requires us to remove and recreate all existing planes.
9433 * TODO: Come up with a more elegant solution for this.
9435 for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) {
9436 struct amdgpu_framebuffer *old_afb, *new_afb;
9437 if (other->type == DRM_PLANE_TYPE_CURSOR)
9440 if (old_other_state->crtc != new_plane_state->crtc &&
9441 new_other_state->crtc != new_plane_state->crtc)
9444 if (old_other_state->crtc != new_other_state->crtc)
9447 /* Src/dst size and scaling updates. */
9448 if (old_other_state->src_w != new_other_state->src_w ||
9449 old_other_state->src_h != new_other_state->src_h ||
9450 old_other_state->crtc_w != new_other_state->crtc_w ||
9451 old_other_state->crtc_h != new_other_state->crtc_h)
9454 /* Rotation / mirroring updates. */
9455 if (old_other_state->rotation != new_other_state->rotation)
9458 /* Blending updates. */
9459 if (old_other_state->pixel_blend_mode !=
9460 new_other_state->pixel_blend_mode)
9463 /* Alpha updates. */
9464 if (old_other_state->alpha != new_other_state->alpha)
9467 /* Colorspace changes. */
9468 if (old_other_state->color_range != new_other_state->color_range ||
9469 old_other_state->color_encoding != new_other_state->color_encoding)
9472 /* Framebuffer checks fall at the end. */
9473 if (!old_other_state->fb || !new_other_state->fb)
9476 /* Pixel format changes can require bandwidth updates. */
9477 if (old_other_state->fb->format != new_other_state->fb->format)
9480 old_afb = (struct amdgpu_framebuffer *)old_other_state->fb;
9481 new_afb = (struct amdgpu_framebuffer *)new_other_state->fb;
9483 /* Tiling and DCC changes also require bandwidth updates. */
9484 if (old_afb->tiling_flags != new_afb->tiling_flags ||
9485 old_afb->base.modifier != new_afb->base.modifier)
9492 static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc,
9493 struct drm_plane_state *new_plane_state,
9494 struct drm_framebuffer *fb)
9496 struct amdgpu_device *adev = drm_to_adev(new_acrtc->base.dev);
9497 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
9501 if (fb->width > new_acrtc->max_cursor_width ||
9502 fb->height > new_acrtc->max_cursor_height) {
9503 DRM_DEBUG_ATOMIC("Bad cursor FB size %dx%d\n",
9504 new_plane_state->fb->width,
9505 new_plane_state->fb->height);
9508 if (new_plane_state->src_w != fb->width << 16 ||
9509 new_plane_state->src_h != fb->height << 16) {
9510 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
9514 /* Pitch in pixels */
9515 pitch = fb->pitches[0] / fb->format->cpp[0];
9517 if (fb->width != pitch) {
9518 DRM_DEBUG_ATOMIC("Cursor FB width %d doesn't match pitch %d",
9527 /* FB pitch is supported by cursor plane */
9530 DRM_DEBUG_ATOMIC("Bad cursor FB pitch %d px\n", pitch);
9534 /* Core DRM takes care of checking FB modifiers, so we only need to
9535 * check tiling flags when the FB doesn't have a modifier. */
9536 if (!(fb->flags & DRM_MODE_FB_MODIFIERS)) {
9537 if (adev->family < AMDGPU_FAMILY_AI) {
9538 linear = AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_2D_TILED_THIN1 &&
9539 AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 &&
9540 AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE) == 0;
9542 linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0;
9545 DRM_DEBUG_ATOMIC("Cursor FB not linear");
9553 static int dm_update_plane_state(struct dc *dc,
9554 struct drm_atomic_state *state,
9555 struct drm_plane *plane,
9556 struct drm_plane_state *old_plane_state,
9557 struct drm_plane_state *new_plane_state,
9559 bool *lock_and_validation_needed,
9560 bool *is_top_most_overlay)
9563 struct dm_atomic_state *dm_state = NULL;
9564 struct drm_crtc *new_plane_crtc, *old_plane_crtc;
9565 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
9566 struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
9567 struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
9568 struct amdgpu_crtc *new_acrtc;
9573 new_plane_crtc = new_plane_state->crtc;
9574 old_plane_crtc = old_plane_state->crtc;
9575 dm_new_plane_state = to_dm_plane_state(new_plane_state);
9576 dm_old_plane_state = to_dm_plane_state(old_plane_state);
9578 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
9579 if (!enable || !new_plane_crtc ||
9580 drm_atomic_plane_disabling(plane->state, new_plane_state))
9583 new_acrtc = to_amdgpu_crtc(new_plane_crtc);
9585 if (new_plane_state->src_x != 0 || new_plane_state->src_y != 0) {
9586 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
9590 if (new_plane_state->fb) {
9591 ret = dm_check_cursor_fb(new_acrtc, new_plane_state,
9592 new_plane_state->fb);
9600 needs_reset = should_reset_plane(state, plane, old_plane_state,
9603 /* Remove any changed/removed planes */
9608 if (!old_plane_crtc)
9611 old_crtc_state = drm_atomic_get_old_crtc_state(
9612 state, old_plane_crtc);
9613 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9615 if (!dm_old_crtc_state->stream)
9618 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",
9619 plane->base.id, old_plane_crtc->base.id);
9621 ret = dm_atomic_get_state(state, &dm_state);
9625 if (!dc_remove_plane_from_context(
9627 dm_old_crtc_state->stream,
9628 dm_old_plane_state->dc_state,
9629 dm_state->context)) {
9635 dc_plane_state_release(dm_old_plane_state->dc_state);
9636 dm_new_plane_state->dc_state = NULL;
9638 *lock_and_validation_needed = true;
9640 } else { /* Add new planes */
9641 struct dc_plane_state *dc_new_plane_state;
9643 if (drm_atomic_plane_disabling(plane->state, new_plane_state))
9646 if (!new_plane_crtc)
9649 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
9650 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9652 if (!dm_new_crtc_state->stream)
9658 ret = amdgpu_dm_plane_helper_check_state(new_plane_state, new_crtc_state);
9662 WARN_ON(dm_new_plane_state->dc_state);
9664 dc_new_plane_state = dc_create_plane_state(dc);
9665 if (!dc_new_plane_state)
9668 /* Block top most plane from being a video plane */
9669 if (plane->type == DRM_PLANE_TYPE_OVERLAY) {
9670 if (is_video_format(new_plane_state->fb->format->format) && *is_top_most_overlay)
9673 *is_top_most_overlay = false;
9676 DRM_DEBUG_ATOMIC("Enabling DRM plane: %d on DRM crtc %d\n",
9677 plane->base.id, new_plane_crtc->base.id);
9679 ret = fill_dc_plane_attributes(
9680 drm_to_adev(new_plane_crtc->dev),
9685 dc_plane_state_release(dc_new_plane_state);
9689 ret = dm_atomic_get_state(state, &dm_state);
9691 dc_plane_state_release(dc_new_plane_state);
9696 * Any atomic check errors that occur after this will
9697 * not need a release. The plane state will be attached
9698 * to the stream, and therefore part of the atomic
9699 * state. It'll be released when the atomic state is
9702 if (!dc_add_plane_to_context(
9704 dm_new_crtc_state->stream,
9706 dm_state->context)) {
9708 dc_plane_state_release(dc_new_plane_state);
9712 dm_new_plane_state->dc_state = dc_new_plane_state;
9714 dm_new_crtc_state->mpo_requested |= (plane->type == DRM_PLANE_TYPE_OVERLAY);
9716 /* Tell DC to do a full surface update every time there
9717 * is a plane change. Inefficient, but works for now.
9719 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
9721 *lock_and_validation_needed = true;
9728 static void dm_get_oriented_plane_size(struct drm_plane_state *plane_state,
9729 int *src_w, int *src_h)
9731 switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
9732 case DRM_MODE_ROTATE_90:
9733 case DRM_MODE_ROTATE_270:
9734 *src_w = plane_state->src_h >> 16;
9735 *src_h = plane_state->src_w >> 16;
9737 case DRM_MODE_ROTATE_0:
9738 case DRM_MODE_ROTATE_180:
9740 *src_w = plane_state->src_w >> 16;
9741 *src_h = plane_state->src_h >> 16;
9746 static int dm_check_crtc_cursor(struct drm_atomic_state *state,
9747 struct drm_crtc *crtc,
9748 struct drm_crtc_state *new_crtc_state)
9750 struct drm_plane *cursor = crtc->cursor, *underlying;
9751 struct drm_plane_state *new_cursor_state, *new_underlying_state;
9753 int cursor_scale_w, cursor_scale_h, underlying_scale_w, underlying_scale_h;
9754 int cursor_src_w, cursor_src_h;
9755 int underlying_src_w, underlying_src_h;
9757 /* On DCE and DCN there is no dedicated hardware cursor plane. We get a
9758 * cursor per pipe but it's going to inherit the scaling and
9759 * positioning from the underlying pipe. Check the cursor plane's
9760 * blending properties match the underlying planes'. */
9762 new_cursor_state = drm_atomic_get_new_plane_state(state, cursor);
9763 if (!new_cursor_state || !new_cursor_state->fb) {
9767 dm_get_oriented_plane_size(new_cursor_state, &cursor_src_w, &cursor_src_h);
9768 cursor_scale_w = new_cursor_state->crtc_w * 1000 / cursor_src_w;
9769 cursor_scale_h = new_cursor_state->crtc_h * 1000 / cursor_src_h;
9771 for_each_new_plane_in_state_reverse(state, underlying, new_underlying_state, i) {
9772 /* Narrow down to non-cursor planes on the same CRTC as the cursor */
9773 if (new_underlying_state->crtc != crtc || underlying == crtc->cursor)
9776 /* Ignore disabled planes */
9777 if (!new_underlying_state->fb)
9780 dm_get_oriented_plane_size(new_underlying_state,
9781 &underlying_src_w, &underlying_src_h);
9782 underlying_scale_w = new_underlying_state->crtc_w * 1000 / underlying_src_w;
9783 underlying_scale_h = new_underlying_state->crtc_h * 1000 / underlying_src_h;
9785 if (cursor_scale_w != underlying_scale_w ||
9786 cursor_scale_h != underlying_scale_h) {
9787 drm_dbg_atomic(crtc->dev,
9788 "Cursor [PLANE:%d:%s] scaling doesn't match underlying [PLANE:%d:%s]\n",
9789 cursor->base.id, cursor->name, underlying->base.id, underlying->name);
9793 /* If this plane covers the whole CRTC, no need to check planes underneath */
9794 if (new_underlying_state->crtc_x <= 0 &&
9795 new_underlying_state->crtc_y <= 0 &&
9796 new_underlying_state->crtc_x + new_underlying_state->crtc_w >= new_crtc_state->mode.hdisplay &&
9797 new_underlying_state->crtc_y + new_underlying_state->crtc_h >= new_crtc_state->mode.vdisplay)
9804 static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc)
9806 struct drm_connector *connector;
9807 struct drm_connector_state *conn_state, *old_conn_state;
9808 struct amdgpu_dm_connector *aconnector = NULL;
9810 for_each_oldnew_connector_in_state(state, connector, old_conn_state, conn_state, i) {
9811 if (!conn_state->crtc)
9812 conn_state = old_conn_state;
9814 if (conn_state->crtc != crtc)
9817 aconnector = to_amdgpu_dm_connector(connector);
9818 if (!aconnector->mst_output_port || !aconnector->mst_root)
9827 return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_root->mst_mgr);
9831 * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.
9833 * @dev: The DRM device
9834 * @state: The atomic state to commit
9836 * Validate that the given atomic state is programmable by DC into hardware.
9837 * This involves constructing a &struct dc_state reflecting the new hardware
9838 * state we wish to commit, then querying DC to see if it is programmable. It's
9839 * important not to modify the existing DC state. Otherwise, atomic_check
9840 * may unexpectedly commit hardware changes.
9842 * When validating the DC state, it's important that the right locks are
9843 * acquired. For full updates case which removes/adds/updates streams on one
9844 * CRTC while flipping on another CRTC, acquiring global lock will guarantee
9845 * that any such full update commit will wait for completion of any outstanding
9846 * flip using DRMs synchronization events.
9848 * Note that DM adds the affected connectors for all CRTCs in state, when that
9849 * might not seem necessary. This is because DC stream creation requires the
9850 * DC sink, which is tied to the DRM connector state. Cleaning this up should
9851 * be possible but non-trivial - a possible TODO item.
9853 * Return: -Error code if validation failed.
9855 static int amdgpu_dm_atomic_check(struct drm_device *dev,
9856 struct drm_atomic_state *state)
9858 struct amdgpu_device *adev = drm_to_adev(dev);
9859 struct dm_atomic_state *dm_state = NULL;
9860 struct dc *dc = adev->dm.dc;
9861 struct drm_connector *connector;
9862 struct drm_connector_state *old_con_state, *new_con_state;
9863 struct drm_crtc *crtc;
9864 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
9865 struct drm_plane *plane;
9866 struct drm_plane_state *old_plane_state, *new_plane_state;
9867 enum dc_status status;
9869 bool lock_and_validation_needed = false;
9870 bool is_top_most_overlay = true;
9871 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
9872 struct drm_dp_mst_topology_mgr *mgr;
9873 struct drm_dp_mst_topology_state *mst_state;
9874 struct dsc_mst_fairness_vars vars[MAX_PIPES];
9876 trace_amdgpu_dm_atomic_check_begin(state);
9878 ret = drm_atomic_helper_check_modeset(dev, state);
9880 DRM_DEBUG_DRIVER("drm_atomic_helper_check_modeset() failed\n");
9884 /* Check connector changes */
9885 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
9886 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
9887 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
9889 /* Skip connectors that are disabled or part of modeset already. */
9890 if (!new_con_state->crtc)
9893 new_crtc_state = drm_atomic_get_crtc_state(state, new_con_state->crtc);
9894 if (IS_ERR(new_crtc_state)) {
9895 DRM_DEBUG_DRIVER("drm_atomic_get_crtc_state() failed\n");
9896 ret = PTR_ERR(new_crtc_state);
9900 if (dm_old_con_state->abm_level != dm_new_con_state->abm_level ||
9901 dm_old_con_state->scaling != dm_new_con_state->scaling)
9902 new_crtc_state->connectors_changed = true;
9905 if (dc_resource_is_dsc_encoding_supported(dc)) {
9906 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
9907 if (drm_atomic_crtc_needs_modeset(new_crtc_state)) {
9908 ret = add_affected_mst_dsc_crtcs(state, crtc);
9910 DRM_DEBUG_DRIVER("add_affected_mst_dsc_crtcs() failed\n");
9916 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
9917 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9919 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
9920 !new_crtc_state->color_mgmt_changed &&
9921 old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled &&
9922 dm_old_crtc_state->dsc_force_changed == false)
9925 ret = amdgpu_dm_verify_lut_sizes(new_crtc_state);
9927 DRM_DEBUG_DRIVER("amdgpu_dm_verify_lut_sizes() failed\n");
9931 if (!new_crtc_state->enable)
9934 ret = drm_atomic_add_affected_connectors(state, crtc);
9936 DRM_DEBUG_DRIVER("drm_atomic_add_affected_connectors() failed\n");
9940 ret = drm_atomic_add_affected_planes(state, crtc);
9942 DRM_DEBUG_DRIVER("drm_atomic_add_affected_planes() failed\n");
9946 if (dm_old_crtc_state->dsc_force_changed)
9947 new_crtc_state->mode_changed = true;
9951 * Add all primary and overlay planes on the CRTC to the state
9952 * whenever a plane is enabled to maintain correct z-ordering
9953 * and to enable fast surface updates.
9955 drm_for_each_crtc(crtc, dev) {
9956 bool modified = false;
9958 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
9959 if (plane->type == DRM_PLANE_TYPE_CURSOR)
9962 if (new_plane_state->crtc == crtc ||
9963 old_plane_state->crtc == crtc) {
9972 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) {
9973 if (plane->type == DRM_PLANE_TYPE_CURSOR)
9977 drm_atomic_get_plane_state(state, plane);
9979 if (IS_ERR(new_plane_state)) {
9980 ret = PTR_ERR(new_plane_state);
9981 DRM_DEBUG_DRIVER("new_plane_state is BAD\n");
9988 * DC consults the zpos (layer_index in DC terminology) to determine the
9989 * hw plane on which to enable the hw cursor (see
9990 * `dcn10_can_pipe_disable_cursor`). By now, all modified planes are in
9991 * atomic state, so call drm helper to normalize zpos.
9993 ret = drm_atomic_normalize_zpos(dev, state);
9995 drm_dbg(dev, "drm_atomic_normalize_zpos() failed\n");
9999 /* Remove exiting planes if they are modified */
10000 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
10001 ret = dm_update_plane_state(dc, state, plane,
10005 &lock_and_validation_needed,
10006 &is_top_most_overlay);
10008 DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n");
10013 /* Disable all crtcs which require disable */
10014 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10015 ret = dm_update_crtc_state(&adev->dm, state, crtc,
10019 &lock_and_validation_needed);
10021 DRM_DEBUG_DRIVER("DISABLE: dm_update_crtc_state() failed\n");
10026 /* Enable all crtcs which require enable */
10027 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
10028 ret = dm_update_crtc_state(&adev->dm, state, crtc,
10032 &lock_and_validation_needed);
10034 DRM_DEBUG_DRIVER("ENABLE: dm_update_crtc_state() failed\n");
10039 /* Add new/modified planes */
10040 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
10041 ret = dm_update_plane_state(dc, state, plane,
10045 &lock_and_validation_needed,
10046 &is_top_most_overlay);
10048 DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n");
10053 if (dc_resource_is_dsc_encoding_supported(dc)) {
10054 ret = pre_validate_dsc(state, &dm_state, vars);
10059 /* Run this here since we want to validate the streams we created */
10060 ret = drm_atomic_helper_check_planes(dev, state);
10062 DRM_DEBUG_DRIVER("drm_atomic_helper_check_planes() failed\n");
10066 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10067 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
10068 if (dm_new_crtc_state->mpo_requested)
10069 DRM_DEBUG_DRIVER("MPO enablement requested on crtc:[%p]\n", crtc);
10072 /* Check cursor planes scaling */
10073 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
10074 ret = dm_check_crtc_cursor(state, crtc, new_crtc_state);
10076 DRM_DEBUG_DRIVER("dm_check_crtc_cursor() failed\n");
10081 if (state->legacy_cursor_update) {
10083 * This is a fast cursor update coming from the plane update
10084 * helper, check if it can be done asynchronously for better
10087 state->async_update =
10088 !drm_atomic_helper_async_check(dev, state);
10091 * Skip the remaining global validation if this is an async
10092 * update. Cursor updates can be done without affecting
10093 * state or bandwidth calcs and this avoids the performance
10094 * penalty of locking the private state object and
10095 * allocating a new dc_state.
10097 if (state->async_update)
10101 /* Check scaling and underscan changes*/
10102 /* TODO Removed scaling changes validation due to inability to commit
10103 * new stream into context w\o causing full reset. Need to
10104 * decide how to handle.
10106 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
10107 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
10108 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
10109 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
10111 /* Skip any modesets/resets */
10112 if (!acrtc || drm_atomic_crtc_needs_modeset(
10113 drm_atomic_get_new_crtc_state(state, &acrtc->base)))
10116 /* Skip any thing not scale or underscan changes */
10117 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
10120 lock_and_validation_needed = true;
10123 /* set the slot info for each mst_state based on the link encoding format */
10124 for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) {
10125 struct amdgpu_dm_connector *aconnector;
10126 struct drm_connector *connector;
10127 struct drm_connector_list_iter iter;
10128 u8 link_coding_cap;
10130 drm_connector_list_iter_begin(dev, &iter);
10131 drm_for_each_connector_iter(connector, &iter) {
10132 if (connector->index == mst_state->mgr->conn_base_id) {
10133 aconnector = to_amdgpu_dm_connector(connector);
10134 link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link);
10135 drm_dp_mst_update_slots(mst_state, link_coding_cap);
10140 drm_connector_list_iter_end(&iter);
10144 * Streams and planes are reset when there are changes that affect
10145 * bandwidth. Anything that affects bandwidth needs to go through
10146 * DC global validation to ensure that the configuration can be applied
10149 * We have to currently stall out here in atomic_check for outstanding
10150 * commits to finish in this case because our IRQ handlers reference
10151 * DRM state directly - we can end up disabling interrupts too early
10154 * TODO: Remove this stall and drop DM state private objects.
10156 if (lock_and_validation_needed) {
10157 ret = dm_atomic_get_state(state, &dm_state);
10159 DRM_DEBUG_DRIVER("dm_atomic_get_state() failed\n");
10163 ret = do_aquire_global_lock(dev, state);
10165 DRM_DEBUG_DRIVER("do_aquire_global_lock() failed\n");
10169 ret = compute_mst_dsc_configs_for_state(state, dm_state->context, vars);
10171 DRM_DEBUG_DRIVER("compute_mst_dsc_configs_for_state() failed\n");
10175 ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context, vars);
10177 DRM_DEBUG_DRIVER("dm_update_mst_vcpi_slots_for_dsc() failed\n");
10182 * Perform validation of MST topology in the state:
10183 * We need to perform MST atomic check before calling
10184 * dc_validate_global_state(), or there is a chance
10185 * to get stuck in an infinite loop and hang eventually.
10187 ret = drm_dp_mst_atomic_check(state);
10189 DRM_DEBUG_DRIVER("drm_dp_mst_atomic_check() failed\n");
10192 status = dc_validate_global_state(dc, dm_state->context, true);
10193 if (status != DC_OK) {
10194 DRM_DEBUG_DRIVER("DC global validation failure: %s (%d)",
10195 dc_status_to_str(status), status);
10201 * The commit is a fast update. Fast updates shouldn't change
10202 * the DC context, affect global validation, and can have their
10203 * commit work done in parallel with other commits not touching
10204 * the same resource. If we have a new DC context as part of
10205 * the DM atomic state from validation we need to free it and
10206 * retain the existing one instead.
10208 * Furthermore, since the DM atomic state only contains the DC
10209 * context and can safely be annulled, we can free the state
10210 * and clear the associated private object now to free
10211 * some memory and avoid a possible use-after-free later.
10214 for (i = 0; i < state->num_private_objs; i++) {
10215 struct drm_private_obj *obj = state->private_objs[i].ptr;
10217 if (obj->funcs == adev->dm.atomic_obj.funcs) {
10218 int j = state->num_private_objs-1;
10220 dm_atomic_destroy_state(obj,
10221 state->private_objs[i].state);
10223 /* If i is not at the end of the array then the
10224 * last element needs to be moved to where i was
10225 * before the array can safely be truncated.
10228 state->private_objs[i] =
10229 state->private_objs[j];
10231 state->private_objs[j].ptr = NULL;
10232 state->private_objs[j].state = NULL;
10233 state->private_objs[j].old_state = NULL;
10234 state->private_objs[j].new_state = NULL;
10236 state->num_private_objs = j;
10242 /* Store the overall update type for use later in atomic check. */
10243 for_each_new_crtc_in_state (state, crtc, new_crtc_state, i) {
10244 struct dm_crtc_state *dm_new_crtc_state =
10245 to_dm_crtc_state(new_crtc_state);
10247 dm_new_crtc_state->update_type = lock_and_validation_needed ?
10252 /* Must be success */
10255 trace_amdgpu_dm_atomic_check_finish(state, ret);
10260 if (ret == -EDEADLK)
10261 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
10262 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
10263 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
10265 DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret);
10267 trace_amdgpu_dm_atomic_check_finish(state, ret);
10272 static bool is_dp_capable_without_timing_msa(struct dc *dc,
10273 struct amdgpu_dm_connector *amdgpu_dm_connector)
10276 bool capable = false;
10278 if (amdgpu_dm_connector->dc_link &&
10279 dm_helpers_dp_read_dpcd(
10281 amdgpu_dm_connector->dc_link,
10282 DP_DOWN_STREAM_PORT_COUNT,
10284 sizeof(dpcd_data))) {
10285 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
10291 static bool dm_edid_parser_send_cea(struct amdgpu_display_manager *dm,
10292 unsigned int offset,
10293 unsigned int total_length,
10295 unsigned int length,
10296 struct amdgpu_hdmi_vsdb_info *vsdb)
10299 union dmub_rb_cmd cmd;
10300 struct dmub_cmd_send_edid_cea *input;
10301 struct dmub_cmd_edid_cea_output *output;
10303 if (length > DMUB_EDID_CEA_DATA_CHUNK_BYTES)
10306 memset(&cmd, 0, sizeof(cmd));
10308 input = &cmd.edid_cea.data.input;
10310 cmd.edid_cea.header.type = DMUB_CMD__EDID_CEA;
10311 cmd.edid_cea.header.sub_type = 0;
10312 cmd.edid_cea.header.payload_bytes =
10313 sizeof(cmd.edid_cea) - sizeof(cmd.edid_cea.header);
10314 input->offset = offset;
10315 input->length = length;
10316 input->cea_total_length = total_length;
10317 memcpy(input->payload, data, length);
10319 res = dc_dmub_srv_cmd_with_reply_data(dm->dc->ctx->dmub_srv, &cmd);
10321 DRM_ERROR("EDID CEA parser failed\n");
10325 output = &cmd.edid_cea.data.output;
10327 if (output->type == DMUB_CMD__EDID_CEA_ACK) {
10328 if (!output->ack.success) {
10329 DRM_ERROR("EDID CEA ack failed at offset %d\n",
10330 output->ack.offset);
10332 } else if (output->type == DMUB_CMD__EDID_CEA_AMD_VSDB) {
10333 if (!output->amd_vsdb.vsdb_found)
10336 vsdb->freesync_supported = output->amd_vsdb.freesync_supported;
10337 vsdb->amd_vsdb_version = output->amd_vsdb.amd_vsdb_version;
10338 vsdb->min_refresh_rate_hz = output->amd_vsdb.min_frame_rate;
10339 vsdb->max_refresh_rate_hz = output->amd_vsdb.max_frame_rate;
10341 DRM_WARN("Unknown EDID CEA parser results\n");
10348 static bool parse_edid_cea_dmcu(struct amdgpu_display_manager *dm,
10349 u8 *edid_ext, int len,
10350 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10354 /* send extension block to DMCU for parsing */
10355 for (i = 0; i < len; i += 8) {
10359 /* send 8 bytes a time */
10360 if (!dc_edid_parser_send_cea(dm->dc, i, len, &edid_ext[i], 8))
10364 /* EDID block sent completed, expect result */
10365 int version, min_rate, max_rate;
10367 res = dc_edid_parser_recv_amd_vsdb(dm->dc, &version, &min_rate, &max_rate);
10369 /* amd vsdb found */
10370 vsdb_info->freesync_supported = 1;
10371 vsdb_info->amd_vsdb_version = version;
10372 vsdb_info->min_refresh_rate_hz = min_rate;
10373 vsdb_info->max_refresh_rate_hz = max_rate;
10381 res = dc_edid_parser_recv_cea_ack(dm->dc, &offset);
10389 static bool parse_edid_cea_dmub(struct amdgpu_display_manager *dm,
10390 u8 *edid_ext, int len,
10391 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10395 /* send extension block to DMCU for parsing */
10396 for (i = 0; i < len; i += 8) {
10397 /* send 8 bytes a time */
10398 if (!dm_edid_parser_send_cea(dm, i, len, &edid_ext[i], 8, vsdb_info))
10402 return vsdb_info->freesync_supported;
10405 static bool parse_edid_cea(struct amdgpu_dm_connector *aconnector,
10406 u8 *edid_ext, int len,
10407 struct amdgpu_hdmi_vsdb_info *vsdb_info)
10409 struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev);
10412 mutex_lock(&adev->dm.dc_lock);
10413 if (adev->dm.dmub_srv)
10414 ret = parse_edid_cea_dmub(&adev->dm, edid_ext, len, vsdb_info);
10416 ret = parse_edid_cea_dmcu(&adev->dm, edid_ext, len, vsdb_info);
10417 mutex_unlock(&adev->dm.dc_lock);
10421 static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector,
10422 struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info)
10424 u8 *edid_ext = NULL;
10426 bool valid_vsdb_found = false;
10428 /*----- drm_find_cea_extension() -----*/
10429 /* No EDID or EDID extensions */
10430 if (edid == NULL || edid->extensions == 0)
10433 /* Find CEA extension */
10434 for (i = 0; i < edid->extensions; i++) {
10435 edid_ext = (uint8_t *)edid + EDID_LENGTH * (i + 1);
10436 if (edid_ext[0] == CEA_EXT)
10440 if (i == edid->extensions)
10443 /*----- cea_db_offsets() -----*/
10444 if (edid_ext[0] != CEA_EXT)
10447 valid_vsdb_found = parse_edid_cea(aconnector, edid_ext, EDID_LENGTH, vsdb_info);
10449 return valid_vsdb_found ? i : -ENODEV;
10453 * amdgpu_dm_update_freesync_caps - Update Freesync capabilities
10455 * @connector: Connector to query.
10456 * @edid: EDID from monitor
10458 * Amdgpu supports Freesync in DP and HDMI displays, and it is required to keep
10459 * track of some of the display information in the internal data struct used by
10460 * amdgpu_dm. This function checks which type of connector we need to set the
10461 * FreeSync parameters.
10463 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
10467 struct detailed_timing *timing;
10468 struct detailed_non_pixel *data;
10469 struct detailed_data_monitor_range *range;
10470 struct amdgpu_dm_connector *amdgpu_dm_connector =
10471 to_amdgpu_dm_connector(connector);
10472 struct dm_connector_state *dm_con_state = NULL;
10473 struct dc_sink *sink;
10475 struct drm_device *dev = connector->dev;
10476 struct amdgpu_device *adev = drm_to_adev(dev);
10477 struct amdgpu_hdmi_vsdb_info vsdb_info = {0};
10478 bool freesync_capable = false;
10479 enum adaptive_sync_type as_type = ADAPTIVE_SYNC_TYPE_NONE;
10481 if (!connector->state) {
10482 DRM_ERROR("%s - Connector has no state", __func__);
10486 sink = amdgpu_dm_connector->dc_sink ?
10487 amdgpu_dm_connector->dc_sink :
10488 amdgpu_dm_connector->dc_em_sink;
10490 if (!edid || !sink) {
10491 dm_con_state = to_dm_connector_state(connector->state);
10493 amdgpu_dm_connector->min_vfreq = 0;
10494 amdgpu_dm_connector->max_vfreq = 0;
10495 amdgpu_dm_connector->pixel_clock_mhz = 0;
10496 connector->display_info.monitor_range.min_vfreq = 0;
10497 connector->display_info.monitor_range.max_vfreq = 0;
10498 freesync_capable = false;
10503 dm_con_state = to_dm_connector_state(connector->state);
10505 if (!adev->dm.freesync_module)
10508 if (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
10509 || sink->sink_signal == SIGNAL_TYPE_EDP) {
10510 bool edid_check_required = false;
10513 edid_check_required = is_dp_capable_without_timing_msa(
10515 amdgpu_dm_connector);
10518 if (edid_check_required == true && (edid->version > 1 ||
10519 (edid->version == 1 && edid->revision > 1))) {
10520 for (i = 0; i < 4; i++) {
10522 timing = &edid->detailed_timings[i];
10523 data = &timing->data.other_data;
10524 range = &data->data.range;
10526 * Check if monitor has continuous frequency mode
10528 if (data->type != EDID_DETAIL_MONITOR_RANGE)
10531 * Check for flag range limits only. If flag == 1 then
10532 * no additional timing information provided.
10533 * Default GTF, GTF Secondary curve and CVT are not
10536 if (range->flags != 1)
10539 amdgpu_dm_connector->min_vfreq = range->min_vfreq;
10540 amdgpu_dm_connector->max_vfreq = range->max_vfreq;
10541 amdgpu_dm_connector->pixel_clock_mhz =
10542 range->pixel_clock_mhz * 10;
10544 connector->display_info.monitor_range.min_vfreq = range->min_vfreq;
10545 connector->display_info.monitor_range.max_vfreq = range->max_vfreq;
10550 if (amdgpu_dm_connector->max_vfreq -
10551 amdgpu_dm_connector->min_vfreq > 10) {
10553 freesync_capable = true;
10556 } else if (edid && sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) {
10557 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
10558 if (i >= 0 && vsdb_info.freesync_supported) {
10559 timing = &edid->detailed_timings[i];
10560 data = &timing->data.other_data;
10562 amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
10563 amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
10564 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
10565 freesync_capable = true;
10567 connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz;
10568 connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz;
10572 as_type = dm_get_adaptive_sync_support_type(amdgpu_dm_connector->dc_link);
10574 if (as_type == FREESYNC_TYPE_PCON_IN_WHITELIST) {
10575 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
10576 if (i >= 0 && vsdb_info.freesync_supported && vsdb_info.amd_vsdb_version > 0) {
10578 amdgpu_dm_connector->pack_sdp_v1_3 = true;
10579 amdgpu_dm_connector->as_type = as_type;
10580 amdgpu_dm_connector->vsdb_info = vsdb_info;
10582 amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
10583 amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
10584 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
10585 freesync_capable = true;
10587 connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz;
10588 connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz;
10594 dm_con_state->freesync_capable = freesync_capable;
10596 if (connector->vrr_capable_property)
10597 drm_connector_set_vrr_capable_property(connector,
10601 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev)
10603 struct amdgpu_device *adev = drm_to_adev(dev);
10604 struct dc *dc = adev->dm.dc;
10607 mutex_lock(&adev->dm.dc_lock);
10608 if (dc->current_state) {
10609 for (i = 0; i < dc->current_state->stream_count; ++i)
10610 dc->current_state->streams[i]
10611 ->triggered_crtc_reset.enabled =
10612 adev->dm.force_timing_sync;
10614 dm_enable_per_frame_crtc_master_sync(dc->current_state);
10615 dc_trigger_sync(dc, dc->current_state);
10617 mutex_unlock(&adev->dm.dc_lock);
10620 void dm_write_reg_func(const struct dc_context *ctx, uint32_t address,
10621 u32 value, const char *func_name)
10623 #ifdef DM_CHECK_ADDR_0
10624 if (address == 0) {
10625 DC_ERR("invalid register write. address = 0");
10629 cgs_write_register(ctx->cgs_device, address, value);
10630 trace_amdgpu_dc_wreg(&ctx->perf_trace->write_count, address, value);
10633 uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address,
10634 const char *func_name)
10637 #ifdef DM_CHECK_ADDR_0
10638 if (address == 0) {
10639 DC_ERR("invalid register read; address = 0\n");
10644 if (ctx->dmub_srv &&
10645 ctx->dmub_srv->reg_helper_offload.gather_in_progress &&
10646 !ctx->dmub_srv->reg_helper_offload.should_burst_write) {
10651 value = cgs_read_register(ctx->cgs_device, address);
10653 trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address, value);
10658 int amdgpu_dm_process_dmub_aux_transfer_sync(
10659 struct dc_context *ctx,
10660 unsigned int link_index,
10661 struct aux_payload *payload,
10662 enum aux_return_code_type *operation_result)
10664 struct amdgpu_device *adev = ctx->driver_context;
10665 struct dmub_notification *p_notify = adev->dm.dmub_notify;
10668 mutex_lock(&adev->dm.dpia_aux_lock);
10669 if (!dc_process_dmub_aux_transfer_async(ctx->dc, link_index, payload)) {
10670 *operation_result = AUX_RET_ERROR_ENGINE_ACQUIRE;
10674 if (!wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) {
10675 DRM_ERROR("wait_for_completion_timeout timeout!");
10676 *operation_result = AUX_RET_ERROR_TIMEOUT;
10680 if (p_notify->result != AUX_RET_SUCCESS) {
10682 * Transient states before tunneling is enabled could
10683 * lead to this error. We can ignore this for now.
10685 if (p_notify->result != AUX_RET_ERROR_PROTOCOL_ERROR) {
10686 DRM_WARN("DPIA AUX failed on 0x%x(%d), error %d\n",
10687 payload->address, payload->length,
10690 *operation_result = AUX_RET_ERROR_INVALID_REPLY;
10695 payload->reply[0] = adev->dm.dmub_notify->aux_reply.command;
10696 if (!payload->write && p_notify->aux_reply.length &&
10697 (payload->reply[0] == AUX_TRANSACTION_REPLY_AUX_ACK)) {
10699 if (payload->length != p_notify->aux_reply.length) {
10700 DRM_WARN("invalid read length %d from DPIA AUX 0x%x(%d)!\n",
10701 p_notify->aux_reply.length,
10702 payload->address, payload->length);
10703 *operation_result = AUX_RET_ERROR_INVALID_REPLY;
10707 memcpy(payload->data, p_notify->aux_reply.data,
10708 p_notify->aux_reply.length);
10712 ret = p_notify->aux_reply.length;
10713 *operation_result = p_notify->result;
10715 reinit_completion(&adev->dm.dmub_aux_transfer_done);
10716 mutex_unlock(&adev->dm.dpia_aux_lock);
10720 int amdgpu_dm_process_dmub_set_config_sync(
10721 struct dc_context *ctx,
10722 unsigned int link_index,
10723 struct set_config_cmd_payload *payload,
10724 enum set_config_status *operation_result)
10726 struct amdgpu_device *adev = ctx->driver_context;
10727 bool is_cmd_complete;
10730 mutex_lock(&adev->dm.dpia_aux_lock);
10731 is_cmd_complete = dc_process_dmub_set_config_async(ctx->dc,
10732 link_index, payload, adev->dm.dmub_notify);
10734 if (is_cmd_complete || wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ)) {
10736 *operation_result = adev->dm.dmub_notify->sc_status;
10738 DRM_ERROR("wait_for_completion_timeout timeout!");
10740 *operation_result = SET_CONFIG_UNKNOWN_ERROR;
10743 if (!is_cmd_complete)
10744 reinit_completion(&adev->dm.dmub_aux_transfer_done);
10745 mutex_unlock(&adev->dm.dpia_aux_lock);
10750 * Check whether seamless boot is supported.
10752 * So far we only support seamless boot on CHIP_VANGOGH.
10753 * If everything goes well, we may consider expanding
10754 * seamless boot to other ASICs.
10756 bool check_seamless_boot_capability(struct amdgpu_device *adev)
10758 switch (adev->ip_versions[DCE_HWIP][0]) {
10759 case IP_VERSION(3, 0, 1):
10760 if (!adev->mman.keep_stolen_vga_memory)