2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 /* The caprices of the preprocessor require that this be declared right here */
27 #define CREATE_TRACE_POINTS
29 #include "dm_services_types.h"
31 #include "dc_link_dp.h"
32 #include "link_enc_cfg.h"
33 #include "dc/inc/core_types.h"
34 #include "dal_asic_id.h"
35 #include "dmub/dmub_srv.h"
36 #include "dc/inc/hw/dmcu.h"
37 #include "dc/inc/hw/abm.h"
38 #include "dc/dc_dmub_srv.h"
39 #include "dc/dc_edid_parser.h"
40 #include "dc/dc_stat.h"
41 #include "amdgpu_dm_trace.h"
45 #include "amdgpu_display.h"
46 #include "amdgpu_ucode.h"
48 #include "amdgpu_dm.h"
49 #include "amdgpu_dm_plane.h"
50 #include "amdgpu_dm_crtc.h"
51 #ifdef CONFIG_DRM_AMD_DC_HDCP
52 #include "amdgpu_dm_hdcp.h"
53 #include <drm/display/drm_hdcp_helper.h>
55 #include "amdgpu_pm.h"
56 #include "amdgpu_atombios.h"
58 #include "amd_shared.h"
59 #include "amdgpu_dm_irq.h"
60 #include "dm_helpers.h"
61 #include "amdgpu_dm_mst_types.h"
62 #if defined(CONFIG_DEBUG_FS)
63 #include "amdgpu_dm_debugfs.h"
65 #include "amdgpu_dm_psr.h"
67 #include "ivsrcid/ivsrcid_vislands30.h"
69 #include "i2caux_interface.h"
70 #include <linux/module.h>
71 #include <linux/moduleparam.h>
72 #include <linux/types.h>
73 #include <linux/pm_runtime.h>
74 #include <linux/pci.h>
75 #include <linux/firmware.h>
76 #include <linux/component.h>
77 #include <linux/dmi.h>
79 #include <drm/display/drm_dp_mst_helper.h>
80 #include <drm/display/drm_hdmi_helper.h>
81 #include <drm/drm_atomic.h>
82 #include <drm/drm_atomic_uapi.h>
83 #include <drm/drm_atomic_helper.h>
84 #include <drm/drm_blend.h>
85 #include <drm/drm_fb_helper.h>
86 #include <drm/drm_fourcc.h>
87 #include <drm/drm_edid.h>
88 #include <drm/drm_vblank.h>
89 #include <drm/drm_audio_component.h>
90 #include <drm/drm_gem_atomic_helper.h>
91 #include <drm/drm_plane_helper.h>
93 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
95 #include "dcn/dcn_1_0_offset.h"
96 #include "dcn/dcn_1_0_sh_mask.h"
97 #include "soc15_hw_ip.h"
98 #include "soc15_common.h"
99 #include "vega10_ip_offset.h"
101 #include "soc15_common.h"
103 #include "gc/gc_11_0_0_offset.h"
104 #include "gc/gc_11_0_0_sh_mask.h"
106 #include "modules/inc/mod_freesync.h"
107 #include "modules/power/power_helpers.h"
108 #include "modules/inc/mod_info_packet.h"
110 #define FIRMWARE_RENOIR_DMUB "amdgpu/renoir_dmcub.bin"
111 MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB);
112 #define FIRMWARE_SIENNA_CICHLID_DMUB "amdgpu/sienna_cichlid_dmcub.bin"
113 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID_DMUB);
114 #define FIRMWARE_NAVY_FLOUNDER_DMUB "amdgpu/navy_flounder_dmcub.bin"
115 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER_DMUB);
116 #define FIRMWARE_GREEN_SARDINE_DMUB "amdgpu/green_sardine_dmcub.bin"
117 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE_DMUB);
118 #define FIRMWARE_VANGOGH_DMUB "amdgpu/vangogh_dmcub.bin"
119 MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB);
120 #define FIRMWARE_DIMGREY_CAVEFISH_DMUB "amdgpu/dimgrey_cavefish_dmcub.bin"
121 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH_DMUB);
122 #define FIRMWARE_BEIGE_GOBY_DMUB "amdgpu/beige_goby_dmcub.bin"
123 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY_DMUB);
124 #define FIRMWARE_YELLOW_CARP_DMUB "amdgpu/yellow_carp_dmcub.bin"
125 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP_DMUB);
126 #define FIRMWARE_DCN_314_DMUB "amdgpu/dcn_3_1_4_dmcub.bin"
127 MODULE_FIRMWARE(FIRMWARE_DCN_314_DMUB);
128 #define FIRMWARE_DCN_315_DMUB "amdgpu/dcn_3_1_5_dmcub.bin"
129 MODULE_FIRMWARE(FIRMWARE_DCN_315_DMUB);
130 #define FIRMWARE_DCN316_DMUB "amdgpu/dcn_3_1_6_dmcub.bin"
131 MODULE_FIRMWARE(FIRMWARE_DCN316_DMUB);
133 #define FIRMWARE_DCN_V3_2_0_DMCUB "amdgpu/dcn_3_2_0_dmcub.bin"
134 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_0_DMCUB);
135 #define FIRMWARE_DCN_V3_2_1_DMCUB "amdgpu/dcn_3_2_1_dmcub.bin"
136 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_1_DMCUB);
138 #define FIRMWARE_RAVEN_DMCU "amdgpu/raven_dmcu.bin"
139 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
141 #define FIRMWARE_NAVI12_DMCU "amdgpu/navi12_dmcu.bin"
142 MODULE_FIRMWARE(FIRMWARE_NAVI12_DMCU);
144 /* Number of bytes in PSP header for firmware. */
145 #define PSP_HEADER_BYTES 0x100
147 /* Number of bytes in PSP footer for firmware. */
148 #define PSP_FOOTER_BYTES 0x100
153 * The AMDgpu display manager, **amdgpu_dm** (or even simpler,
154 * **dm**) sits between DRM and DC. It acts as a liaison, converting DRM
155 * requests into DC requests, and DC responses into DRM responses.
157 * The root control structure is &struct amdgpu_display_manager.
160 /* basic init/fini API */
161 static int amdgpu_dm_init(struct amdgpu_device *adev);
162 static void amdgpu_dm_fini(struct amdgpu_device *adev);
163 static bool is_freesync_video_mode(const struct drm_display_mode *mode, struct amdgpu_dm_connector *aconnector);
165 static enum drm_mode_subconnector get_subconnector_type(struct dc_link *link)
167 switch (link->dpcd_caps.dongle_type) {
168 case DISPLAY_DONGLE_NONE:
169 return DRM_MODE_SUBCONNECTOR_Native;
170 case DISPLAY_DONGLE_DP_VGA_CONVERTER:
171 return DRM_MODE_SUBCONNECTOR_VGA;
172 case DISPLAY_DONGLE_DP_DVI_CONVERTER:
173 case DISPLAY_DONGLE_DP_DVI_DONGLE:
174 return DRM_MODE_SUBCONNECTOR_DVID;
175 case DISPLAY_DONGLE_DP_HDMI_CONVERTER:
176 case DISPLAY_DONGLE_DP_HDMI_DONGLE:
177 return DRM_MODE_SUBCONNECTOR_HDMIA;
178 case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
180 return DRM_MODE_SUBCONNECTOR_Unknown;
184 static void update_subconnector_property(struct amdgpu_dm_connector *aconnector)
186 struct dc_link *link = aconnector->dc_link;
187 struct drm_connector *connector = &aconnector->base;
188 enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
190 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
193 if (aconnector->dc_sink)
194 subconnector = get_subconnector_type(link);
196 drm_object_property_set_value(&connector->base,
197 connector->dev->mode_config.dp_subconnector_property,
202 * initializes drm_device display related structures, based on the information
203 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
204 * drm_encoder, drm_mode_config
206 * Returns 0 on success
208 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
209 /* removes and deallocates the drm structures, created by the above function */
210 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
212 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
213 struct amdgpu_dm_connector *amdgpu_dm_connector,
215 struct amdgpu_encoder *amdgpu_encoder);
216 static int amdgpu_dm_encoder_init(struct drm_device *dev,
217 struct amdgpu_encoder *aencoder,
218 uint32_t link_index);
220 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
222 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
224 static int amdgpu_dm_atomic_check(struct drm_device *dev,
225 struct drm_atomic_state *state);
227 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector);
228 static void handle_hpd_rx_irq(void *param);
231 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
232 struct drm_crtc_state *new_crtc_state);
234 * dm_vblank_get_counter
237 * Get counter for number of vertical blanks
240 * struct amdgpu_device *adev - [in] desired amdgpu device
241 * int disp_idx - [in] which CRTC to get the counter from
244 * Counter for vertical blanks
246 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
248 if (crtc >= adev->mode_info.num_crtc)
251 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
253 if (acrtc->dm_irq_params.stream == NULL) {
254 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
259 return dc_stream_get_vblank_counter(acrtc->dm_irq_params.stream);
263 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
264 u32 *vbl, u32 *position)
266 uint32_t v_blank_start, v_blank_end, h_position, v_position;
268 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
271 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
273 if (acrtc->dm_irq_params.stream == NULL) {
274 DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
280 * TODO rework base driver to use values directly.
281 * for now parse it back into reg-format
283 dc_stream_get_scanoutpos(acrtc->dm_irq_params.stream,
289 *position = v_position | (h_position << 16);
290 *vbl = v_blank_start | (v_blank_end << 16);
296 static bool dm_is_idle(void *handle)
302 static int dm_wait_for_idle(void *handle)
308 static bool dm_check_soft_reset(void *handle)
313 static int dm_soft_reset(void *handle)
319 static struct amdgpu_crtc *
320 get_crtc_by_otg_inst(struct amdgpu_device *adev,
323 struct drm_device *dev = adev_to_drm(adev);
324 struct drm_crtc *crtc;
325 struct amdgpu_crtc *amdgpu_crtc;
327 if (WARN_ON(otg_inst == -1))
328 return adev->mode_info.crtcs[0];
330 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
331 amdgpu_crtc = to_amdgpu_crtc(crtc);
333 if (amdgpu_crtc->otg_inst == otg_inst)
340 static inline bool is_dc_timing_adjust_needed(struct dm_crtc_state *old_state,
341 struct dm_crtc_state *new_state)
343 if (new_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)
345 else if (amdgpu_dm_vrr_active(old_state) != amdgpu_dm_vrr_active(new_state))
352 * dm_pflip_high_irq() - Handle pageflip interrupt
353 * @interrupt_params: ignored
355 * Handles the pageflip interrupt by notifying all interested parties
356 * that the pageflip has been completed.
358 static void dm_pflip_high_irq(void *interrupt_params)
360 struct amdgpu_crtc *amdgpu_crtc;
361 struct common_irq_params *irq_params = interrupt_params;
362 struct amdgpu_device *adev = irq_params->adev;
364 struct drm_pending_vblank_event *e;
365 uint32_t vpos, hpos, v_blank_start, v_blank_end;
368 amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
370 /* IRQ could occur when in initial stage */
371 /* TODO work and BO cleanup */
372 if (amdgpu_crtc == NULL) {
373 DC_LOG_PFLIP("CRTC is null, returning.\n");
377 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
379 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
380 DC_LOG_PFLIP("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
381 amdgpu_crtc->pflip_status,
382 AMDGPU_FLIP_SUBMITTED,
383 amdgpu_crtc->crtc_id,
385 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
389 /* page flip completed. */
390 e = amdgpu_crtc->event;
391 amdgpu_crtc->event = NULL;
395 vrr_active = amdgpu_dm_vrr_active_irq(amdgpu_crtc);
397 /* Fixed refresh rate, or VRR scanout position outside front-porch? */
399 !dc_stream_get_scanoutpos(amdgpu_crtc->dm_irq_params.stream, &v_blank_start,
400 &v_blank_end, &hpos, &vpos) ||
401 (vpos < v_blank_start)) {
402 /* Update to correct count and vblank timestamp if racing with
403 * vblank irq. This also updates to the correct vblank timestamp
404 * even in VRR mode, as scanout is past the front-porch atm.
406 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
408 /* Wake up userspace by sending the pageflip event with proper
409 * count and timestamp of vblank of flip completion.
412 drm_crtc_send_vblank_event(&amdgpu_crtc->base, e);
414 /* Event sent, so done with vblank for this flip */
415 drm_crtc_vblank_put(&amdgpu_crtc->base);
418 /* VRR active and inside front-porch: vblank count and
419 * timestamp for pageflip event will only be up to date after
420 * drm_crtc_handle_vblank() has been executed from late vblank
421 * irq handler after start of back-porch (vline 0). We queue the
422 * pageflip event for send-out by drm_crtc_handle_vblank() with
423 * updated timestamp and count, once it runs after us.
425 * We need to open-code this instead of using the helper
426 * drm_crtc_arm_vblank_event(), as that helper would
427 * call drm_crtc_accurate_vblank_count(), which we must
428 * not call in VRR mode while we are in front-porch!
431 /* sequence will be replaced by real count during send-out. */
432 e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base);
433 e->pipe = amdgpu_crtc->crtc_id;
435 list_add_tail(&e->base.link, &adev_to_drm(adev)->vblank_event_list);
439 /* Keep track of vblank of this flip for flip throttling. We use the
440 * cooked hw counter, as that one incremented at start of this vblank
441 * of pageflip completion, so last_flip_vblank is the forbidden count
442 * for queueing new pageflips if vsync + VRR is enabled.
444 amdgpu_crtc->dm_irq_params.last_flip_vblank =
445 amdgpu_get_vblank_counter_kms(&amdgpu_crtc->base);
447 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
448 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
450 DC_LOG_PFLIP("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n",
451 amdgpu_crtc->crtc_id, amdgpu_crtc,
452 vrr_active, (int) !e);
455 static void dm_vupdate_high_irq(void *interrupt_params)
457 struct common_irq_params *irq_params = interrupt_params;
458 struct amdgpu_device *adev = irq_params->adev;
459 struct amdgpu_crtc *acrtc;
460 struct drm_device *drm_dev;
461 struct drm_vblank_crtc *vblank;
462 ktime_t frame_duration_ns, previous_timestamp;
466 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE);
469 vrr_active = amdgpu_dm_vrr_active_irq(acrtc);
470 drm_dev = acrtc->base.dev;
471 vblank = &drm_dev->vblank[acrtc->base.index];
472 previous_timestamp = atomic64_read(&irq_params->previous_timestamp);
473 frame_duration_ns = vblank->time - previous_timestamp;
475 if (frame_duration_ns > 0) {
476 trace_amdgpu_refresh_rate_track(acrtc->base.index,
478 ktime_divns(NSEC_PER_SEC, frame_duration_ns));
479 atomic64_set(&irq_params->previous_timestamp, vblank->time);
482 DC_LOG_VBLANK("crtc:%d, vupdate-vrr:%d\n",
486 /* Core vblank handling is done here after end of front-porch in
487 * vrr mode, as vblank timestamping will give valid results
488 * while now done after front-porch. This will also deliver
489 * page-flip completion events that have been queued to us
490 * if a pageflip happened inside front-porch.
493 dm_crtc_handle_vblank(acrtc);
495 /* BTR processing for pre-DCE12 ASICs */
496 if (acrtc->dm_irq_params.stream &&
497 adev->family < AMDGPU_FAMILY_AI) {
498 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
499 mod_freesync_handle_v_update(
500 adev->dm.freesync_module,
501 acrtc->dm_irq_params.stream,
502 &acrtc->dm_irq_params.vrr_params);
504 dc_stream_adjust_vmin_vmax(
506 acrtc->dm_irq_params.stream,
507 &acrtc->dm_irq_params.vrr_params.adjust);
508 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
515 * dm_crtc_high_irq() - Handles CRTC interrupt
516 * @interrupt_params: used for determining the CRTC instance
518 * Handles the CRTC/VSYNC interrupt by notfying DRM's VBLANK
521 static void dm_crtc_high_irq(void *interrupt_params)
523 struct common_irq_params *irq_params = interrupt_params;
524 struct amdgpu_device *adev = irq_params->adev;
525 struct amdgpu_crtc *acrtc;
529 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
533 vrr_active = amdgpu_dm_vrr_active_irq(acrtc);
535 DC_LOG_VBLANK("crtc:%d, vupdate-vrr:%d, planes:%d\n", acrtc->crtc_id,
536 vrr_active, acrtc->dm_irq_params.active_planes);
539 * Core vblank handling at start of front-porch is only possible
540 * in non-vrr mode, as only there vblank timestamping will give
541 * valid results while done in front-porch. Otherwise defer it
542 * to dm_vupdate_high_irq after end of front-porch.
545 dm_crtc_handle_vblank(acrtc);
548 * Following stuff must happen at start of vblank, for crc
549 * computation and below-the-range btr support in vrr mode.
551 amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
553 /* BTR updates need to happen before VUPDATE on Vega and above. */
554 if (adev->family < AMDGPU_FAMILY_AI)
557 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
559 if (acrtc->dm_irq_params.stream &&
560 acrtc->dm_irq_params.vrr_params.supported &&
561 acrtc->dm_irq_params.freesync_config.state ==
562 VRR_STATE_ACTIVE_VARIABLE) {
563 mod_freesync_handle_v_update(adev->dm.freesync_module,
564 acrtc->dm_irq_params.stream,
565 &acrtc->dm_irq_params.vrr_params);
567 dc_stream_adjust_vmin_vmax(adev->dm.dc, acrtc->dm_irq_params.stream,
568 &acrtc->dm_irq_params.vrr_params.adjust);
572 * If there aren't any active_planes then DCH HUBP may be clock-gated.
573 * In that case, pageflip completion interrupts won't fire and pageflip
574 * completion events won't get delivered. Prevent this by sending
575 * pending pageflip events from here if a flip is still pending.
577 * If any planes are enabled, use dm_pflip_high_irq() instead, to
578 * avoid race conditions between flip programming and completion,
579 * which could cause too early flip completion events.
581 if (adev->family >= AMDGPU_FAMILY_RV &&
582 acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED &&
583 acrtc->dm_irq_params.active_planes == 0) {
585 drm_crtc_send_vblank_event(&acrtc->base, acrtc->event);
587 drm_crtc_vblank_put(&acrtc->base);
589 acrtc->pflip_status = AMDGPU_FLIP_NONE;
592 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
595 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
597 * dm_dcn_vertical_interrupt0_high_irq() - Handles OTG Vertical interrupt0 for
598 * DCN generation ASICs
599 * @interrupt_params: interrupt parameters
601 * Used to set crc window/read out crc value at vertical line 0 position
603 static void dm_dcn_vertical_interrupt0_high_irq(void *interrupt_params)
605 struct common_irq_params *irq_params = interrupt_params;
606 struct amdgpu_device *adev = irq_params->adev;
607 struct amdgpu_crtc *acrtc;
609 acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VLINE0);
614 amdgpu_dm_crtc_handle_crc_window_irq(&acrtc->base);
616 #endif /* CONFIG_DRM_AMD_SECURE_DISPLAY */
619 * dmub_aux_setconfig_callback - Callback for AUX or SET_CONFIG command.
620 * @adev: amdgpu_device pointer
621 * @notify: dmub notification structure
623 * Dmub AUX or SET_CONFIG command completion processing callback
624 * Copies dmub notification to DM which is to be read by AUX command.
625 * issuing thread and also signals the event to wake up the thread.
627 static void dmub_aux_setconfig_callback(struct amdgpu_device *adev,
628 struct dmub_notification *notify)
630 if (adev->dm.dmub_notify)
631 memcpy(adev->dm.dmub_notify, notify, sizeof(struct dmub_notification));
632 if (notify->type == DMUB_NOTIFICATION_AUX_REPLY)
633 complete(&adev->dm.dmub_aux_transfer_done);
637 * dmub_hpd_callback - DMUB HPD interrupt processing callback.
638 * @adev: amdgpu_device pointer
639 * @notify: dmub notification structure
641 * Dmub Hpd interrupt processing callback. Gets displayindex through the
642 * ink index and calls helper to do the processing.
644 static void dmub_hpd_callback(struct amdgpu_device *adev,
645 struct dmub_notification *notify)
647 struct amdgpu_dm_connector *aconnector;
648 struct amdgpu_dm_connector *hpd_aconnector = NULL;
649 struct drm_connector *connector;
650 struct drm_connector_list_iter iter;
651 struct dc_link *link;
652 uint8_t link_index = 0;
653 struct drm_device *dev;
658 if (notify == NULL) {
659 DRM_ERROR("DMUB HPD callback notification was NULL");
663 if (notify->link_index > adev->dm.dc->link_count) {
664 DRM_ERROR("DMUB HPD index (%u)is abnormal", notify->link_index);
668 link_index = notify->link_index;
669 link = adev->dm.dc->links[link_index];
672 drm_connector_list_iter_begin(dev, &iter);
673 drm_for_each_connector_iter(connector, &iter) {
674 aconnector = to_amdgpu_dm_connector(connector);
675 if (link && aconnector->dc_link == link) {
676 DRM_INFO("DMUB HPD callback: link_index=%u\n", link_index);
677 hpd_aconnector = aconnector;
681 drm_connector_list_iter_end(&iter);
683 if (hpd_aconnector) {
684 if (notify->type == DMUB_NOTIFICATION_HPD)
685 handle_hpd_irq_helper(hpd_aconnector);
686 else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ)
687 handle_hpd_rx_irq(hpd_aconnector);
692 * register_dmub_notify_callback - Sets callback for DMUB notify
693 * @adev: amdgpu_device pointer
694 * @type: Type of dmub notification
695 * @callback: Dmub interrupt callback function
696 * @dmub_int_thread_offload: offload indicator
698 * API to register a dmub callback handler for a dmub notification
699 * Also sets indicator whether callback processing to be offloaded.
700 * to dmub interrupt handling thread
701 * Return: true if successfully registered, false if there is existing registration
703 static bool register_dmub_notify_callback(struct amdgpu_device *adev,
704 enum dmub_notification_type type,
705 dmub_notify_interrupt_callback_t callback,
706 bool dmub_int_thread_offload)
708 if (callback != NULL && type < ARRAY_SIZE(adev->dm.dmub_thread_offload)) {
709 adev->dm.dmub_callback[type] = callback;
710 adev->dm.dmub_thread_offload[type] = dmub_int_thread_offload;
717 static void dm_handle_hpd_work(struct work_struct *work)
719 struct dmub_hpd_work *dmub_hpd_wrk;
721 dmub_hpd_wrk = container_of(work, struct dmub_hpd_work, handle_hpd_work);
723 if (!dmub_hpd_wrk->dmub_notify) {
724 DRM_ERROR("dmub_hpd_wrk dmub_notify is NULL");
728 if (dmub_hpd_wrk->dmub_notify->type < ARRAY_SIZE(dmub_hpd_wrk->adev->dm.dmub_callback)) {
729 dmub_hpd_wrk->adev->dm.dmub_callback[dmub_hpd_wrk->dmub_notify->type](dmub_hpd_wrk->adev,
730 dmub_hpd_wrk->dmub_notify);
733 kfree(dmub_hpd_wrk->dmub_notify);
738 #define DMUB_TRACE_MAX_READ 64
740 * dm_dmub_outbox1_low_irq() - Handles Outbox interrupt
741 * @interrupt_params: used for determining the Outbox instance
743 * Handles the Outbox Interrupt
746 static void dm_dmub_outbox1_low_irq(void *interrupt_params)
748 struct dmub_notification notify;
749 struct common_irq_params *irq_params = interrupt_params;
750 struct amdgpu_device *adev = irq_params->adev;
751 struct amdgpu_display_manager *dm = &adev->dm;
752 struct dmcub_trace_buf_entry entry = { 0 };
754 struct dmub_hpd_work *dmub_hpd_wrk;
755 struct dc_link *plink = NULL;
757 if (dc_enable_dmub_notifications(adev->dm.dc) &&
758 irq_params->irq_src == DC_IRQ_SOURCE_DMCUB_OUTBOX) {
761 dc_stat_get_dmub_notification(adev->dm.dc, ¬ify);
762 if (notify.type >= ARRAY_SIZE(dm->dmub_thread_offload)) {
763 DRM_ERROR("DM: notify type %d invalid!", notify.type);
766 if (!dm->dmub_callback[notify.type]) {
767 DRM_DEBUG_DRIVER("DMUB notification skipped, no handler: type=%d\n", notify.type);
770 if (dm->dmub_thread_offload[notify.type] == true) {
771 dmub_hpd_wrk = kzalloc(sizeof(*dmub_hpd_wrk), GFP_ATOMIC);
773 DRM_ERROR("Failed to allocate dmub_hpd_wrk");
776 dmub_hpd_wrk->dmub_notify = kzalloc(sizeof(struct dmub_notification), GFP_ATOMIC);
777 if (!dmub_hpd_wrk->dmub_notify) {
779 DRM_ERROR("Failed to allocate dmub_hpd_wrk->dmub_notify");
782 INIT_WORK(&dmub_hpd_wrk->handle_hpd_work, dm_handle_hpd_work);
783 if (dmub_hpd_wrk->dmub_notify)
784 memcpy(dmub_hpd_wrk->dmub_notify, ¬ify, sizeof(struct dmub_notification));
785 dmub_hpd_wrk->adev = adev;
786 if (notify.type == DMUB_NOTIFICATION_HPD) {
787 plink = adev->dm.dc->links[notify.link_index];
790 notify.hpd_status == DP_HPD_PLUG;
793 queue_work(adev->dm.delayed_hpd_wq, &dmub_hpd_wrk->handle_hpd_work);
795 dm->dmub_callback[notify.type](adev, ¬ify);
797 } while (notify.pending_notification);
802 if (dc_dmub_srv_get_dmub_outbox0_msg(dm->dc, &entry)) {
803 trace_amdgpu_dmub_trace_high_irq(entry.trace_code, entry.tick_count,
804 entry.param0, entry.param1);
806 DRM_DEBUG_DRIVER("trace_code:%u, tick_count:%u, param0:%u, param1:%u\n",
807 entry.trace_code, entry.tick_count, entry.param0, entry.param1);
813 } while (count <= DMUB_TRACE_MAX_READ);
815 if (count > DMUB_TRACE_MAX_READ)
816 DRM_DEBUG_DRIVER("Warning : count > DMUB_TRACE_MAX_READ");
819 static int dm_set_clockgating_state(void *handle,
820 enum amd_clockgating_state state)
825 static int dm_set_powergating_state(void *handle,
826 enum amd_powergating_state state)
831 /* Prototypes of private functions */
832 static int dm_early_init(void* handle);
834 /* Allocate memory for FBC compressed data */
835 static void amdgpu_dm_fbc_init(struct drm_connector *connector)
837 struct drm_device *dev = connector->dev;
838 struct amdgpu_device *adev = drm_to_adev(dev);
839 struct dm_compressor_info *compressor = &adev->dm.compressor;
840 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
841 struct drm_display_mode *mode;
842 unsigned long max_size = 0;
844 if (adev->dm.dc->fbc_compressor == NULL)
847 if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
850 if (compressor->bo_ptr)
854 list_for_each_entry(mode, &connector->modes, head) {
855 if (max_size < mode->htotal * mode->vtotal)
856 max_size = mode->htotal * mode->vtotal;
860 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,
861 AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr,
862 &compressor->gpu_addr, &compressor->cpu_addr);
865 DRM_ERROR("DM: Failed to initialize FBC\n");
867 adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
868 DRM_INFO("DM: FBC alloc %lu\n", max_size*4);
875 static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port,
876 int pipe, bool *enabled,
877 unsigned char *buf, int max_bytes)
879 struct drm_device *dev = dev_get_drvdata(kdev);
880 struct amdgpu_device *adev = drm_to_adev(dev);
881 struct drm_connector *connector;
882 struct drm_connector_list_iter conn_iter;
883 struct amdgpu_dm_connector *aconnector;
888 mutex_lock(&adev->dm.audio_lock);
890 drm_connector_list_iter_begin(dev, &conn_iter);
891 drm_for_each_connector_iter(connector, &conn_iter) {
892 aconnector = to_amdgpu_dm_connector(connector);
893 if (aconnector->audio_inst != port)
897 ret = drm_eld_size(connector->eld);
898 memcpy(buf, connector->eld, min(max_bytes, ret));
902 drm_connector_list_iter_end(&conn_iter);
904 mutex_unlock(&adev->dm.audio_lock);
906 DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled);
911 static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = {
912 .get_eld = amdgpu_dm_audio_component_get_eld,
915 static int amdgpu_dm_audio_component_bind(struct device *kdev,
916 struct device *hda_kdev, void *data)
918 struct drm_device *dev = dev_get_drvdata(kdev);
919 struct amdgpu_device *adev = drm_to_adev(dev);
920 struct drm_audio_component *acomp = data;
922 acomp->ops = &amdgpu_dm_audio_component_ops;
924 adev->dm.audio_component = acomp;
929 static void amdgpu_dm_audio_component_unbind(struct device *kdev,
930 struct device *hda_kdev, void *data)
932 struct drm_device *dev = dev_get_drvdata(kdev);
933 struct amdgpu_device *adev = drm_to_adev(dev);
934 struct drm_audio_component *acomp = data;
938 adev->dm.audio_component = NULL;
941 static const struct component_ops amdgpu_dm_audio_component_bind_ops = {
942 .bind = amdgpu_dm_audio_component_bind,
943 .unbind = amdgpu_dm_audio_component_unbind,
946 static int amdgpu_dm_audio_init(struct amdgpu_device *adev)
953 adev->mode_info.audio.enabled = true;
955 adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count;
957 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
958 adev->mode_info.audio.pin[i].channels = -1;
959 adev->mode_info.audio.pin[i].rate = -1;
960 adev->mode_info.audio.pin[i].bits_per_sample = -1;
961 adev->mode_info.audio.pin[i].status_bits = 0;
962 adev->mode_info.audio.pin[i].category_code = 0;
963 adev->mode_info.audio.pin[i].connected = false;
964 adev->mode_info.audio.pin[i].id =
965 adev->dm.dc->res_pool->audios[i]->inst;
966 adev->mode_info.audio.pin[i].offset = 0;
969 ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops);
973 adev->dm.audio_registered = true;
978 static void amdgpu_dm_audio_fini(struct amdgpu_device *adev)
983 if (!adev->mode_info.audio.enabled)
986 if (adev->dm.audio_registered) {
987 component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops);
988 adev->dm.audio_registered = false;
991 /* TODO: Disable audio? */
993 adev->mode_info.audio.enabled = false;
996 static void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin)
998 struct drm_audio_component *acomp = adev->dm.audio_component;
1000 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) {
1001 DRM_DEBUG_KMS("Notify ELD: %d\n", pin);
1003 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
1008 static int dm_dmub_hw_init(struct amdgpu_device *adev)
1010 const struct dmcub_firmware_header_v1_0 *hdr;
1011 struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
1012 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
1013 const struct firmware *dmub_fw = adev->dm.dmub_fw;
1014 struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
1015 struct abm *abm = adev->dm.dc->res_pool->abm;
1016 struct dmub_srv_hw_params hw_params;
1017 enum dmub_status status;
1018 const unsigned char *fw_inst_const, *fw_bss_data;
1019 uint32_t i, fw_inst_const_size, fw_bss_data_size;
1020 bool has_hw_support;
1023 /* DMUB isn't supported on the ASIC. */
1027 DRM_ERROR("No framebuffer info for DMUB service.\n");
1032 /* Firmware required for DMUB support. */
1033 DRM_ERROR("No firmware provided for DMUB.\n");
1037 status = dmub_srv_has_hw_support(dmub_srv, &has_hw_support);
1038 if (status != DMUB_STATUS_OK) {
1039 DRM_ERROR("Error checking HW support for DMUB: %d\n", status);
1043 if (!has_hw_support) {
1044 DRM_INFO("DMUB unsupported on ASIC\n");
1048 /* Reset DMCUB if it was previously running - before we overwrite its memory. */
1049 status = dmub_srv_hw_reset(dmub_srv);
1050 if (status != DMUB_STATUS_OK)
1051 DRM_WARN("Error resetting DMUB HW: %d\n", status);
1053 hdr = (const struct dmcub_firmware_header_v1_0 *)dmub_fw->data;
1055 fw_inst_const = dmub_fw->data +
1056 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1059 fw_bss_data = dmub_fw->data +
1060 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1061 le32_to_cpu(hdr->inst_const_bytes);
1063 /* Copy firmware and bios info into FB memory. */
1064 fw_inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
1065 PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
1067 fw_bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
1069 /* if adev->firmware.load_type == AMDGPU_FW_LOAD_PSP,
1070 * amdgpu_ucode_init_single_fw will load dmub firmware
1071 * fw_inst_const part to cw0; otherwise, the firmware back door load
1072 * will be done by dm_dmub_hw_init
1074 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1075 memcpy(fb_info->fb[DMUB_WINDOW_0_INST_CONST].cpu_addr, fw_inst_const,
1076 fw_inst_const_size);
1079 if (fw_bss_data_size)
1080 memcpy(fb_info->fb[DMUB_WINDOW_2_BSS_DATA].cpu_addr,
1081 fw_bss_data, fw_bss_data_size);
1083 /* Copy firmware bios info into FB memory. */
1084 memcpy(fb_info->fb[DMUB_WINDOW_3_VBIOS].cpu_addr, adev->bios,
1087 /* Reset regions that need to be reset. */
1088 memset(fb_info->fb[DMUB_WINDOW_4_MAILBOX].cpu_addr, 0,
1089 fb_info->fb[DMUB_WINDOW_4_MAILBOX].size);
1091 memset(fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr, 0,
1092 fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size);
1094 memset(fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr, 0,
1095 fb_info->fb[DMUB_WINDOW_6_FW_STATE].size);
1097 /* Initialize hardware. */
1098 memset(&hw_params, 0, sizeof(hw_params));
1099 hw_params.fb_base = adev->gmc.fb_start;
1100 hw_params.fb_offset = adev->gmc.aper_base;
1102 /* backdoor load firmware and trigger dmub running */
1103 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
1104 hw_params.load_inst_const = true;
1107 hw_params.psp_version = dmcu->psp_version;
1109 for (i = 0; i < fb_info->num_fb; ++i)
1110 hw_params.fb[i] = &fb_info->fb[i];
1112 switch (adev->ip_versions[DCE_HWIP][0]) {
1113 case IP_VERSION(3, 1, 3): /* Only for this asic hw internal rev B0 */
1114 hw_params.dpia_supported = true;
1115 hw_params.disable_dpia = adev->dm.dc->debug.dpia_debug.bits.disable_dpia;
1121 status = dmub_srv_hw_init(dmub_srv, &hw_params);
1122 if (status != DMUB_STATUS_OK) {
1123 DRM_ERROR("Error initializing DMUB HW: %d\n", status);
1127 /* Wait for firmware load to finish. */
1128 status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
1129 if (status != DMUB_STATUS_OK)
1130 DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
1132 /* Init DMCU and ABM if available. */
1134 dmcu->funcs->dmcu_init(dmcu);
1135 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
1138 if (!adev->dm.dc->ctx->dmub_srv)
1139 adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv);
1140 if (!adev->dm.dc->ctx->dmub_srv) {
1141 DRM_ERROR("Couldn't allocate DC DMUB server!\n");
1145 DRM_INFO("DMUB hardware initialized: version=0x%08X\n",
1146 adev->dm.dmcub_fw_version);
1151 static void dm_dmub_hw_resume(struct amdgpu_device *adev)
1153 struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
1154 enum dmub_status status;
1158 /* DMUB isn't supported on the ASIC. */
1162 status = dmub_srv_is_hw_init(dmub_srv, &init);
1163 if (status != DMUB_STATUS_OK)
1164 DRM_WARN("DMUB hardware init check failed: %d\n", status);
1166 if (status == DMUB_STATUS_OK && init) {
1167 /* Wait for firmware load to finish. */
1168 status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
1169 if (status != DMUB_STATUS_OK)
1170 DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
1172 /* Perform the full hardware initialization. */
1173 dm_dmub_hw_init(adev);
1177 static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_addr_space_config *pa_config)
1180 uint32_t logical_addr_low;
1181 uint32_t logical_addr_high;
1182 uint32_t agp_base, agp_bot, agp_top;
1183 PHYSICAL_ADDRESS_LOC page_table_start, page_table_end, page_table_base;
1185 memset(pa_config, 0, sizeof(*pa_config));
1187 logical_addr_low = min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18;
1188 pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
1190 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1192 * Raven2 has a HW issue that it is unable to use the vram which
1193 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
1194 * workaround that increase system aperture high address (add 1)
1195 * to get rid of the VM fault and hardware hang.
1197 logical_addr_high = max((adev->gmc.fb_end >> 18) + 0x1, adev->gmc.agp_end >> 18);
1199 logical_addr_high = max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18;
1202 agp_bot = adev->gmc.agp_start >> 24;
1203 agp_top = adev->gmc.agp_end >> 24;
1206 page_table_start.high_part = (u32)(adev->gmc.gart_start >> 44) & 0xF;
1207 page_table_start.low_part = (u32)(adev->gmc.gart_start >> 12);
1208 page_table_end.high_part = (u32)(adev->gmc.gart_end >> 44) & 0xF;
1209 page_table_end.low_part = (u32)(adev->gmc.gart_end >> 12);
1210 page_table_base.high_part = upper_32_bits(pt_base) & 0xF;
1211 page_table_base.low_part = lower_32_bits(pt_base);
1213 pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18;
1214 pa_config->system_aperture.end_addr = (uint64_t)logical_addr_high << 18;
1216 pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24 ;
1217 pa_config->system_aperture.agp_bot = (uint64_t)agp_bot << 24;
1218 pa_config->system_aperture.agp_top = (uint64_t)agp_top << 24;
1220 pa_config->system_aperture.fb_base = adev->gmc.fb_start;
1221 pa_config->system_aperture.fb_offset = adev->gmc.aper_base;
1222 pa_config->system_aperture.fb_top = adev->gmc.fb_end;
1224 pa_config->gart_config.page_table_start_addr = page_table_start.quad_part << 12;
1225 pa_config->gart_config.page_table_end_addr = page_table_end.quad_part << 12;
1226 pa_config->gart_config.page_table_base_addr = page_table_base.quad_part;
1228 pa_config->is_hvm_enabled = 0;
1232 static void dm_handle_hpd_rx_offload_work(struct work_struct *work)
1234 struct hpd_rx_irq_offload_work *offload_work;
1235 struct amdgpu_dm_connector *aconnector;
1236 struct dc_link *dc_link;
1237 struct amdgpu_device *adev;
1238 enum dc_connection_type new_connection_type = dc_connection_none;
1239 unsigned long flags;
1241 offload_work = container_of(work, struct hpd_rx_irq_offload_work, work);
1242 aconnector = offload_work->offload_wq->aconnector;
1245 DRM_ERROR("Can't retrieve aconnector in hpd_rx_irq_offload_work");
1249 adev = drm_to_adev(aconnector->base.dev);
1250 dc_link = aconnector->dc_link;
1252 mutex_lock(&aconnector->hpd_lock);
1253 if (!dc_link_detect_sink(dc_link, &new_connection_type))
1254 DRM_ERROR("KMS: Failed to detect connector\n");
1255 mutex_unlock(&aconnector->hpd_lock);
1257 if (new_connection_type == dc_connection_none)
1260 if (amdgpu_in_reset(adev))
1263 mutex_lock(&adev->dm.dc_lock);
1264 if (offload_work->data.bytes.device_service_irq.bits.AUTOMATED_TEST)
1265 dc_link_dp_handle_automated_test(dc_link);
1266 else if ((dc_link->connector_signal != SIGNAL_TYPE_EDP) &&
1267 hpd_rx_irq_check_link_loss_status(dc_link, &offload_work->data) &&
1268 dc_link_dp_allow_hpd_rx_irq(dc_link)) {
1269 dc_link_dp_handle_link_loss(dc_link);
1270 spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags);
1271 offload_work->offload_wq->is_handling_link_loss = false;
1272 spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags);
1274 mutex_unlock(&adev->dm.dc_lock);
1277 kfree(offload_work);
1281 static struct hpd_rx_irq_offload_work_queue *hpd_rx_irq_create_workqueue(struct dc *dc)
1283 int max_caps = dc->caps.max_links;
1285 struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq = NULL;
1287 hpd_rx_offload_wq = kcalloc(max_caps, sizeof(*hpd_rx_offload_wq), GFP_KERNEL);
1289 if (!hpd_rx_offload_wq)
1293 for (i = 0; i < max_caps; i++) {
1294 hpd_rx_offload_wq[i].wq =
1295 create_singlethread_workqueue("amdgpu_dm_hpd_rx_offload_wq");
1297 if (hpd_rx_offload_wq[i].wq == NULL) {
1298 DRM_ERROR("create amdgpu_dm_hpd_rx_offload_wq fail!");
1302 spin_lock_init(&hpd_rx_offload_wq[i].offload_lock);
1305 return hpd_rx_offload_wq;
1308 struct amdgpu_stutter_quirk {
1316 static const struct amdgpu_stutter_quirk amdgpu_stutter_quirk_list[] = {
1317 /* https://bugzilla.kernel.org/show_bug.cgi?id=214417 */
1318 { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 },
1322 static bool dm_should_disable_stutter(struct pci_dev *pdev)
1324 const struct amdgpu_stutter_quirk *p = amdgpu_stutter_quirk_list;
1326 while (p && p->chip_device != 0) {
1327 if (pdev->vendor == p->chip_vendor &&
1328 pdev->device == p->chip_device &&
1329 pdev->subsystem_vendor == p->subsys_vendor &&
1330 pdev->subsystem_device == p->subsys_device &&
1331 pdev->revision == p->revision) {
1339 static const struct dmi_system_id hpd_disconnect_quirk_table[] = {
1342 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1343 DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3660"),
1348 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1349 DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3260"),
1354 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1355 DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3460"),
1361 static void retrieve_dmi_info(struct amdgpu_display_manager *dm)
1363 const struct dmi_system_id *dmi_id;
1365 dm->aux_hpd_discon_quirk = false;
1367 dmi_id = dmi_first_match(hpd_disconnect_quirk_table);
1369 dm->aux_hpd_discon_quirk = true;
1370 DRM_INFO("aux_hpd_discon_quirk attached\n");
1374 static int amdgpu_dm_init(struct amdgpu_device *adev)
1376 struct dc_init_data init_data;
1377 #ifdef CONFIG_DRM_AMD_DC_HDCP
1378 struct dc_callback_init init_params;
1382 adev->dm.ddev = adev_to_drm(adev);
1383 adev->dm.adev = adev;
1385 /* Zero all the fields */
1386 memset(&init_data, 0, sizeof(init_data));
1387 #ifdef CONFIG_DRM_AMD_DC_HDCP
1388 memset(&init_params, 0, sizeof(init_params));
1391 mutex_init(&adev->dm.dc_lock);
1392 mutex_init(&adev->dm.audio_lock);
1393 spin_lock_init(&adev->dm.vblank_lock);
1395 if(amdgpu_dm_irq_init(adev)) {
1396 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
1400 init_data.asic_id.chip_family = adev->family;
1402 init_data.asic_id.pci_revision_id = adev->pdev->revision;
1403 init_data.asic_id.hw_internal_rev = adev->external_rev_id;
1404 init_data.asic_id.chip_id = adev->pdev->device;
1406 init_data.asic_id.vram_width = adev->gmc.vram_width;
1407 /* TODO: initialize init_data.asic_id.vram_type here!!!! */
1408 init_data.asic_id.atombios_base_address =
1409 adev->mode_info.atom_context->bios;
1411 init_data.driver = adev;
1413 adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
1415 if (!adev->dm.cgs_device) {
1416 DRM_ERROR("amdgpu: failed to create cgs device.\n");
1420 init_data.cgs_device = adev->dm.cgs_device;
1422 init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
1424 switch (adev->ip_versions[DCE_HWIP][0]) {
1425 case IP_VERSION(2, 1, 0):
1426 switch (adev->dm.dmcub_fw_version) {
1427 case 0: /* development */
1428 case 0x1: /* linux-firmware.git hash 6d9f399 */
1429 case 0x01000000: /* linux-firmware.git hash 9a0b0f4 */
1430 init_data.flags.disable_dmcu = false;
1433 init_data.flags.disable_dmcu = true;
1436 case IP_VERSION(2, 0, 3):
1437 init_data.flags.disable_dmcu = true;
1443 switch (adev->asic_type) {
1446 init_data.flags.gpu_vm_support = true;
1449 switch (adev->ip_versions[DCE_HWIP][0]) {
1450 case IP_VERSION(1, 0, 0):
1451 case IP_VERSION(1, 0, 1):
1452 /* enable S/G on PCO and RV2 */
1453 if ((adev->apu_flags & AMD_APU_IS_RAVEN2) ||
1454 (adev->apu_flags & AMD_APU_IS_PICASSO))
1455 init_data.flags.gpu_vm_support = true;
1457 case IP_VERSION(2, 1, 0):
1458 case IP_VERSION(3, 0, 1):
1459 case IP_VERSION(3, 1, 2):
1460 case IP_VERSION(3, 1, 3):
1461 case IP_VERSION(3, 1, 5):
1462 case IP_VERSION(3, 1, 6):
1463 init_data.flags.gpu_vm_support = true;
1471 if (init_data.flags.gpu_vm_support)
1472 adev->mode_info.gpu_vm_support = true;
1474 if (amdgpu_dc_feature_mask & DC_FBC_MASK)
1475 init_data.flags.fbc_support = true;
1477 if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK)
1478 init_data.flags.multi_mon_pp_mclk_switch = true;
1480 if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK)
1481 init_data.flags.disable_fractional_pwm = true;
1483 if (amdgpu_dc_feature_mask & DC_EDP_NO_POWER_SEQUENCING)
1484 init_data.flags.edp_no_power_sequencing = true;
1486 if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP1_4A)
1487 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP1_4A = true;
1488 if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP2_0)
1489 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP2_0 = true;
1491 init_data.flags.seamless_boot_edp_requested = false;
1493 if (check_seamless_boot_capability(adev)) {
1494 init_data.flags.seamless_boot_edp_requested = true;
1495 init_data.flags.allow_seamless_boot_optimization = true;
1496 DRM_INFO("Seamless boot condition check passed\n");
1499 init_data.flags.enable_mipi_converter_optimization = true;
1501 init_data.dcn_reg_offsets = adev->reg_offset[DCE_HWIP][0];
1502 init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0];
1504 INIT_LIST_HEAD(&adev->dm.da_list);
1506 retrieve_dmi_info(&adev->dm);
1508 /* Display Core create. */
1509 adev->dm.dc = dc_create(&init_data);
1512 DRM_INFO("Display Core initialized with v%s!\n", DC_VER);
1514 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER);
1518 if (amdgpu_dc_debug_mask & DC_DISABLE_PIPE_SPLIT) {
1519 adev->dm.dc->debug.force_single_disp_pipe_split = false;
1520 adev->dm.dc->debug.pipe_split_policy = MPC_SPLIT_AVOID;
1523 if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY)
1524 adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;
1525 if (dm_should_disable_stutter(adev->pdev))
1526 adev->dm.dc->debug.disable_stutter = true;
1528 if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER)
1529 adev->dm.dc->debug.disable_stutter = true;
1531 if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) {
1532 adev->dm.dc->debug.disable_dsc = true;
1533 adev->dm.dc->debug.disable_dsc_edp = true;
1536 if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING)
1537 adev->dm.dc->debug.disable_clock_gate = true;
1539 if (amdgpu_dc_debug_mask & DC_FORCE_SUBVP_MCLK_SWITCH)
1540 adev->dm.dc->debug.force_subvp_mclk_switch = true;
1542 adev->dm.dc->debug.visual_confirm = amdgpu_dc_visual_confirm;
1544 r = dm_dmub_hw_init(adev);
1546 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
1550 dc_hardware_init(adev->dm.dc);
1552 adev->dm.hpd_rx_offload_wq = hpd_rx_irq_create_workqueue(adev->dm.dc);
1553 if (!adev->dm.hpd_rx_offload_wq) {
1554 DRM_ERROR("amdgpu: failed to create hpd rx offload workqueue.\n");
1558 if ((adev->flags & AMD_IS_APU) && (adev->asic_type >= CHIP_CARRIZO)) {
1559 struct dc_phy_addr_space_config pa_config;
1561 mmhub_read_system_context(adev, &pa_config);
1563 // Call the DC init_memory func
1564 dc_setup_system_context(adev->dm.dc, &pa_config);
1567 adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
1568 if (!adev->dm.freesync_module) {
1570 "amdgpu: failed to initialize freesync_module.\n");
1572 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
1573 adev->dm.freesync_module);
1575 amdgpu_dm_init_color_mod();
1577 if (adev->dm.dc->caps.max_links > 0) {
1578 adev->dm.vblank_control_workqueue =
1579 create_singlethread_workqueue("dm_vblank_control_workqueue");
1580 if (!adev->dm.vblank_control_workqueue)
1581 DRM_ERROR("amdgpu: failed to initialize vblank_workqueue.\n");
1584 #ifdef CONFIG_DRM_AMD_DC_HDCP
1585 if (adev->dm.dc->caps.max_links > 0 && adev->family >= AMDGPU_FAMILY_RV) {
1586 adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc);
1588 if (!adev->dm.hdcp_workqueue)
1589 DRM_ERROR("amdgpu: failed to initialize hdcp_workqueue.\n");
1591 DRM_DEBUG_DRIVER("amdgpu: hdcp_workqueue init done %p.\n", adev->dm.hdcp_workqueue);
1593 dc_init_callbacks(adev->dm.dc, &init_params);
1596 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
1597 adev->dm.crc_rd_wrk = amdgpu_dm_crtc_secure_display_create_work();
1599 if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
1600 init_completion(&adev->dm.dmub_aux_transfer_done);
1601 adev->dm.dmub_notify = kzalloc(sizeof(struct dmub_notification), GFP_KERNEL);
1602 if (!adev->dm.dmub_notify) {
1603 DRM_INFO("amdgpu: fail to allocate adev->dm.dmub_notify");
1607 adev->dm.delayed_hpd_wq = create_singlethread_workqueue("amdgpu_dm_hpd_wq");
1608 if (!adev->dm.delayed_hpd_wq) {
1609 DRM_ERROR("amdgpu: failed to create hpd offload workqueue.\n");
1613 amdgpu_dm_outbox_init(adev);
1614 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_AUX_REPLY,
1615 dmub_aux_setconfig_callback, false)) {
1616 DRM_ERROR("amdgpu: fail to register dmub aux callback");
1619 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD, dmub_hpd_callback, true)) {
1620 DRM_ERROR("amdgpu: fail to register dmub hpd callback");
1623 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD_IRQ, dmub_hpd_callback, true)) {
1624 DRM_ERROR("amdgpu: fail to register dmub hpd callback");
1629 if (amdgpu_dm_initialize_drm_device(adev)) {
1631 "amdgpu: failed to initialize sw for display support.\n");
1635 /* Enable outbox notification only after IRQ handlers are registered and DMUB is alive.
1636 * It is expected that DMUB will resend any pending notifications at this point, for
1637 * example HPD from DPIA.
1639 if (dc_is_dmub_outbox_supported(adev->dm.dc))
1640 dc_enable_dmub_outbox(adev->dm.dc);
1642 /* create fake encoders for MST */
1643 dm_dp_create_fake_mst_encoders(adev);
1645 /* TODO: Add_display_info? */
1647 /* TODO use dynamic cursor width */
1648 adev_to_drm(adev)->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
1649 adev_to_drm(adev)->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
1651 if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) {
1653 "amdgpu: failed to initialize sw for display support.\n");
1658 DRM_DEBUG_DRIVER("KMS initialized.\n");
1662 amdgpu_dm_fini(adev);
1667 static int amdgpu_dm_early_fini(void *handle)
1669 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1671 amdgpu_dm_audio_fini(adev);
1676 static void amdgpu_dm_fini(struct amdgpu_device *adev)
1680 if (adev->dm.vblank_control_workqueue) {
1681 destroy_workqueue(adev->dm.vblank_control_workqueue);
1682 adev->dm.vblank_control_workqueue = NULL;
1685 for (i = 0; i < adev->dm.display_indexes_num; i++) {
1686 drm_encoder_cleanup(&adev->dm.mst_encoders[i].base);
1689 amdgpu_dm_destroy_drm_device(&adev->dm);
1691 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
1692 if (adev->dm.crc_rd_wrk) {
1693 flush_work(&adev->dm.crc_rd_wrk->notify_ta_work);
1694 kfree(adev->dm.crc_rd_wrk);
1695 adev->dm.crc_rd_wrk = NULL;
1698 #ifdef CONFIG_DRM_AMD_DC_HDCP
1699 if (adev->dm.hdcp_workqueue) {
1700 hdcp_destroy(&adev->dev->kobj, adev->dm.hdcp_workqueue);
1701 adev->dm.hdcp_workqueue = NULL;
1705 dc_deinit_callbacks(adev->dm.dc);
1708 dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv);
1710 if (dc_enable_dmub_notifications(adev->dm.dc)) {
1711 kfree(adev->dm.dmub_notify);
1712 adev->dm.dmub_notify = NULL;
1713 destroy_workqueue(adev->dm.delayed_hpd_wq);
1714 adev->dm.delayed_hpd_wq = NULL;
1717 if (adev->dm.dmub_bo)
1718 amdgpu_bo_free_kernel(&adev->dm.dmub_bo,
1719 &adev->dm.dmub_bo_gpu_addr,
1720 &adev->dm.dmub_bo_cpu_addr);
1722 if (adev->dm.hpd_rx_offload_wq) {
1723 for (i = 0; i < adev->dm.dc->caps.max_links; i++) {
1724 if (adev->dm.hpd_rx_offload_wq[i].wq) {
1725 destroy_workqueue(adev->dm.hpd_rx_offload_wq[i].wq);
1726 adev->dm.hpd_rx_offload_wq[i].wq = NULL;
1730 kfree(adev->dm.hpd_rx_offload_wq);
1731 adev->dm.hpd_rx_offload_wq = NULL;
1734 /* DC Destroy TODO: Replace destroy DAL */
1736 dc_destroy(&adev->dm.dc);
1738 * TODO: pageflip, vlank interrupt
1740 * amdgpu_dm_irq_fini(adev);
1743 if (adev->dm.cgs_device) {
1744 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
1745 adev->dm.cgs_device = NULL;
1747 if (adev->dm.freesync_module) {
1748 mod_freesync_destroy(adev->dm.freesync_module);
1749 adev->dm.freesync_module = NULL;
1752 mutex_destroy(&adev->dm.audio_lock);
1753 mutex_destroy(&adev->dm.dc_lock);
1758 static int load_dmcu_fw(struct amdgpu_device *adev)
1760 const char *fw_name_dmcu = NULL;
1762 const struct dmcu_firmware_header_v1_0 *hdr;
1764 switch(adev->asic_type) {
1765 #if defined(CONFIG_DRM_AMD_DC_SI)
1780 case CHIP_POLARIS11:
1781 case CHIP_POLARIS10:
1782 case CHIP_POLARIS12:
1789 fw_name_dmcu = FIRMWARE_NAVI12_DMCU;
1792 if (ASICREV_IS_PICASSO(adev->external_rev_id))
1793 fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
1794 else if (ASICREV_IS_RAVEN2(adev->external_rev_id))
1795 fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
1800 switch (adev->ip_versions[DCE_HWIP][0]) {
1801 case IP_VERSION(2, 0, 2):
1802 case IP_VERSION(2, 0, 3):
1803 case IP_VERSION(2, 0, 0):
1804 case IP_VERSION(2, 1, 0):
1805 case IP_VERSION(3, 0, 0):
1806 case IP_VERSION(3, 0, 2):
1807 case IP_VERSION(3, 0, 3):
1808 case IP_VERSION(3, 0, 1):
1809 case IP_VERSION(3, 1, 2):
1810 case IP_VERSION(3, 1, 3):
1811 case IP_VERSION(3, 1, 4):
1812 case IP_VERSION(3, 1, 5):
1813 case IP_VERSION(3, 1, 6):
1814 case IP_VERSION(3, 2, 0):
1815 case IP_VERSION(3, 2, 1):
1820 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
1824 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1825 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n");
1829 r = request_firmware_direct(&adev->dm.fw_dmcu, fw_name_dmcu, adev->dev);
1831 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */
1832 DRM_DEBUG_KMS("dm: DMCU firmware not found\n");
1833 adev->dm.fw_dmcu = NULL;
1837 dev_err(adev->dev, "amdgpu_dm: Can't load firmware \"%s\"\n",
1842 r = amdgpu_ucode_validate(adev->dm.fw_dmcu);
1844 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n",
1846 release_firmware(adev->dm.fw_dmcu);
1847 adev->dm.fw_dmcu = NULL;
1851 hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data;
1852 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM;
1853 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu;
1854 adev->firmware.fw_size +=
1855 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
1857 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV;
1858 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu;
1859 adev->firmware.fw_size +=
1860 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
1862 adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version);
1864 DRM_DEBUG_KMS("PSP loading DMCU firmware\n");
1869 static uint32_t amdgpu_dm_dmub_reg_read(void *ctx, uint32_t address)
1871 struct amdgpu_device *adev = ctx;
1873 return dm_read_reg(adev->dm.dc->ctx, address);
1876 static void amdgpu_dm_dmub_reg_write(void *ctx, uint32_t address,
1879 struct amdgpu_device *adev = ctx;
1881 return dm_write_reg(adev->dm.dc->ctx, address, value);
1884 static int dm_dmub_sw_init(struct amdgpu_device *adev)
1886 struct dmub_srv_create_params create_params;
1887 struct dmub_srv_region_params region_params;
1888 struct dmub_srv_region_info region_info;
1889 struct dmub_srv_fb_params fb_params;
1890 struct dmub_srv_fb_info *fb_info;
1891 struct dmub_srv *dmub_srv;
1892 const struct dmcub_firmware_header_v1_0 *hdr;
1893 const char *fw_name_dmub;
1894 enum dmub_asic dmub_asic;
1895 enum dmub_status status;
1898 switch (adev->ip_versions[DCE_HWIP][0]) {
1899 case IP_VERSION(2, 1, 0):
1900 dmub_asic = DMUB_ASIC_DCN21;
1901 fw_name_dmub = FIRMWARE_RENOIR_DMUB;
1902 if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
1903 fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB;
1905 case IP_VERSION(3, 0, 0):
1906 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) {
1907 dmub_asic = DMUB_ASIC_DCN30;
1908 fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB;
1910 dmub_asic = DMUB_ASIC_DCN30;
1911 fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB;
1914 case IP_VERSION(3, 0, 1):
1915 dmub_asic = DMUB_ASIC_DCN301;
1916 fw_name_dmub = FIRMWARE_VANGOGH_DMUB;
1918 case IP_VERSION(3, 0, 2):
1919 dmub_asic = DMUB_ASIC_DCN302;
1920 fw_name_dmub = FIRMWARE_DIMGREY_CAVEFISH_DMUB;
1922 case IP_VERSION(3, 0, 3):
1923 dmub_asic = DMUB_ASIC_DCN303;
1924 fw_name_dmub = FIRMWARE_BEIGE_GOBY_DMUB;
1926 case IP_VERSION(3, 1, 2):
1927 case IP_VERSION(3, 1, 3):
1928 dmub_asic = (adev->external_rev_id == YELLOW_CARP_B0) ? DMUB_ASIC_DCN31B : DMUB_ASIC_DCN31;
1929 fw_name_dmub = FIRMWARE_YELLOW_CARP_DMUB;
1931 case IP_VERSION(3, 1, 4):
1932 dmub_asic = DMUB_ASIC_DCN314;
1933 fw_name_dmub = FIRMWARE_DCN_314_DMUB;
1935 case IP_VERSION(3, 1, 5):
1936 dmub_asic = DMUB_ASIC_DCN315;
1937 fw_name_dmub = FIRMWARE_DCN_315_DMUB;
1939 case IP_VERSION(3, 1, 6):
1940 dmub_asic = DMUB_ASIC_DCN316;
1941 fw_name_dmub = FIRMWARE_DCN316_DMUB;
1943 case IP_VERSION(3, 2, 0):
1944 dmub_asic = DMUB_ASIC_DCN32;
1945 fw_name_dmub = FIRMWARE_DCN_V3_2_0_DMCUB;
1947 case IP_VERSION(3, 2, 1):
1948 dmub_asic = DMUB_ASIC_DCN321;
1949 fw_name_dmub = FIRMWARE_DCN_V3_2_1_DMCUB;
1952 /* ASIC doesn't support DMUB. */
1956 r = request_firmware_direct(&adev->dm.dmub_fw, fw_name_dmub, adev->dev);
1958 DRM_ERROR("DMUB firmware loading failed: %d\n", r);
1962 r = amdgpu_ucode_validate(adev->dm.dmub_fw);
1964 DRM_ERROR("Couldn't validate DMUB firmware: %d\n", r);
1968 hdr = (const struct dmcub_firmware_header_v1_0 *)adev->dm.dmub_fw->data;
1969 adev->dm.dmcub_fw_version = le32_to_cpu(hdr->header.ucode_version);
1971 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1972 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].ucode_id =
1973 AMDGPU_UCODE_ID_DMCUB;
1974 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].fw =
1976 adev->firmware.fw_size +=
1977 ALIGN(le32_to_cpu(hdr->inst_const_bytes), PAGE_SIZE);
1979 DRM_INFO("Loading DMUB firmware via PSP: version=0x%08X\n",
1980 adev->dm.dmcub_fw_version);
1984 adev->dm.dmub_srv = kzalloc(sizeof(*adev->dm.dmub_srv), GFP_KERNEL);
1985 dmub_srv = adev->dm.dmub_srv;
1988 DRM_ERROR("Failed to allocate DMUB service!\n");
1992 memset(&create_params, 0, sizeof(create_params));
1993 create_params.user_ctx = adev;
1994 create_params.funcs.reg_read = amdgpu_dm_dmub_reg_read;
1995 create_params.funcs.reg_write = amdgpu_dm_dmub_reg_write;
1996 create_params.asic = dmub_asic;
1998 /* Create the DMUB service. */
1999 status = dmub_srv_create(dmub_srv, &create_params);
2000 if (status != DMUB_STATUS_OK) {
2001 DRM_ERROR("Error creating DMUB service: %d\n", status);
2005 /* Calculate the size of all the regions for the DMUB service. */
2006 memset(®ion_params, 0, sizeof(region_params));
2008 region_params.inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
2009 PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
2010 region_params.bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
2011 region_params.vbios_size = adev->bios_size;
2012 region_params.fw_bss_data = region_params.bss_data_size ?
2013 adev->dm.dmub_fw->data +
2014 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
2015 le32_to_cpu(hdr->inst_const_bytes) : NULL;
2016 region_params.fw_inst_const =
2017 adev->dm.dmub_fw->data +
2018 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
2021 status = dmub_srv_calc_region_info(dmub_srv, ®ion_params,
2024 if (status != DMUB_STATUS_OK) {
2025 DRM_ERROR("Error calculating DMUB region info: %d\n", status);
2030 * Allocate a framebuffer based on the total size of all the regions.
2031 * TODO: Move this into GART.
2033 r = amdgpu_bo_create_kernel(adev, region_info.fb_size, PAGE_SIZE,
2034 AMDGPU_GEM_DOMAIN_VRAM, &adev->dm.dmub_bo,
2035 &adev->dm.dmub_bo_gpu_addr,
2036 &adev->dm.dmub_bo_cpu_addr);
2040 /* Rebase the regions on the framebuffer address. */
2041 memset(&fb_params, 0, sizeof(fb_params));
2042 fb_params.cpu_addr = adev->dm.dmub_bo_cpu_addr;
2043 fb_params.gpu_addr = adev->dm.dmub_bo_gpu_addr;
2044 fb_params.region_info = ®ion_info;
2046 adev->dm.dmub_fb_info =
2047 kzalloc(sizeof(*adev->dm.dmub_fb_info), GFP_KERNEL);
2048 fb_info = adev->dm.dmub_fb_info;
2052 "Failed to allocate framebuffer info for DMUB service!\n");
2056 status = dmub_srv_calc_fb_info(dmub_srv, &fb_params, fb_info);
2057 if (status != DMUB_STATUS_OK) {
2058 DRM_ERROR("Error calculating DMUB FB info: %d\n", status);
2065 static int dm_sw_init(void *handle)
2067 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2070 r = dm_dmub_sw_init(adev);
2074 return load_dmcu_fw(adev);
2077 static int dm_sw_fini(void *handle)
2079 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2081 kfree(adev->dm.dmub_fb_info);
2082 adev->dm.dmub_fb_info = NULL;
2084 if (adev->dm.dmub_srv) {
2085 dmub_srv_destroy(adev->dm.dmub_srv);
2086 adev->dm.dmub_srv = NULL;
2089 release_firmware(adev->dm.dmub_fw);
2090 adev->dm.dmub_fw = NULL;
2092 release_firmware(adev->dm.fw_dmcu);
2093 adev->dm.fw_dmcu = NULL;
2098 static int detect_mst_link_for_all_connectors(struct drm_device *dev)
2100 struct amdgpu_dm_connector *aconnector;
2101 struct drm_connector *connector;
2102 struct drm_connector_list_iter iter;
2105 drm_connector_list_iter_begin(dev, &iter);
2106 drm_for_each_connector_iter(connector, &iter) {
2107 aconnector = to_amdgpu_dm_connector(connector);
2108 if (aconnector->dc_link->type == dc_connection_mst_branch &&
2109 aconnector->mst_mgr.aux) {
2110 DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
2112 aconnector->base.base.id);
2114 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
2116 DRM_ERROR("DM_MST: Failed to start MST\n");
2117 aconnector->dc_link->type =
2118 dc_connection_single;
2123 drm_connector_list_iter_end(&iter);
2128 static int dm_late_init(void *handle)
2130 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2132 struct dmcu_iram_parameters params;
2133 unsigned int linear_lut[16];
2135 struct dmcu *dmcu = NULL;
2137 dmcu = adev->dm.dc->res_pool->dmcu;
2139 for (i = 0; i < 16; i++)
2140 linear_lut[i] = 0xFFFF * i / 15;
2143 params.backlight_ramping_override = false;
2144 params.backlight_ramping_start = 0xCCCC;
2145 params.backlight_ramping_reduction = 0xCCCCCCCC;
2146 params.backlight_lut_array_size = 16;
2147 params.backlight_lut_array = linear_lut;
2149 /* Min backlight level after ABM reduction, Don't allow below 1%
2150 * 0xFFFF x 0.01 = 0x28F
2152 params.min_abm_backlight = 0x28F;
2153 /* In the case where abm is implemented on dmcub,
2154 * dmcu object will be null.
2155 * ABM 2.4 and up are implemented on dmcub.
2158 if (!dmcu_load_iram(dmcu, params))
2160 } else if (adev->dm.dc->ctx->dmub_srv) {
2161 struct dc_link *edp_links[MAX_NUM_EDP];
2164 get_edp_links(adev->dm.dc, edp_links, &edp_num);
2165 for (i = 0; i < edp_num; i++) {
2166 if (!dmub_init_abm_config(adev->dm.dc->res_pool, params, i))
2171 return detect_mst_link_for_all_connectors(adev_to_drm(adev));
2174 static void s3_handle_mst(struct drm_device *dev, bool suspend)
2176 struct amdgpu_dm_connector *aconnector;
2177 struct drm_connector *connector;
2178 struct drm_connector_list_iter iter;
2179 struct drm_dp_mst_topology_mgr *mgr;
2181 bool need_hotplug = false;
2183 drm_connector_list_iter_begin(dev, &iter);
2184 drm_for_each_connector_iter(connector, &iter) {
2185 aconnector = to_amdgpu_dm_connector(connector);
2186 if (aconnector->dc_link->type != dc_connection_mst_branch ||
2187 aconnector->mst_port)
2190 mgr = &aconnector->mst_mgr;
2193 drm_dp_mst_topology_mgr_suspend(mgr);
2195 ret = drm_dp_mst_topology_mgr_resume(mgr, true);
2197 dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,
2198 aconnector->dc_link);
2199 need_hotplug = true;
2203 drm_connector_list_iter_end(&iter);
2206 drm_kms_helper_hotplug_event(dev);
2209 static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev)
2213 /* This interface is for dGPU Navi1x.Linux dc-pplib interface depends
2214 * on window driver dc implementation.
2215 * For Navi1x, clock settings of dcn watermarks are fixed. the settings
2216 * should be passed to smu during boot up and resume from s3.
2217 * boot up: dc calculate dcn watermark clock settings within dc_create,
2218 * dcn20_resource_construct
2219 * then call pplib functions below to pass the settings to smu:
2220 * smu_set_watermarks_for_clock_ranges
2221 * smu_set_watermarks_table
2222 * navi10_set_watermarks_table
2223 * smu_write_watermarks_table
2225 * For Renoir, clock settings of dcn watermark are also fixed values.
2226 * dc has implemented different flow for window driver:
2227 * dc_hardware_init / dc_set_power_state
2232 * smu_set_watermarks_for_clock_ranges
2233 * renoir_set_watermarks_table
2234 * smu_write_watermarks_table
2237 * dc_hardware_init -> amdgpu_dm_init
2238 * dc_set_power_state --> dm_resume
2240 * therefore, this function apply to navi10/12/14 but not Renoir
2243 switch (adev->ip_versions[DCE_HWIP][0]) {
2244 case IP_VERSION(2, 0, 2):
2245 case IP_VERSION(2, 0, 0):
2251 ret = amdgpu_dpm_write_watermarks_table(adev);
2253 DRM_ERROR("Failed to update WMTABLE!\n");
2261 * dm_hw_init() - Initialize DC device
2262 * @handle: The base driver device containing the amdgpu_dm device.
2264 * Initialize the &struct amdgpu_display_manager device. This involves calling
2265 * the initializers of each DM component, then populating the struct with them.
2267 * Although the function implies hardware initialization, both hardware and
2268 * software are initialized here. Splitting them out to their relevant init
2269 * hooks is a future TODO item.
2271 * Some notable things that are initialized here:
2273 * - Display Core, both software and hardware
2274 * - DC modules that we need (freesync and color management)
2275 * - DRM software states
2276 * - Interrupt sources and handlers
2278 * - Debug FS entries, if enabled
2280 static int dm_hw_init(void *handle)
2282 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2283 /* Create DAL display manager */
2284 amdgpu_dm_init(adev);
2285 amdgpu_dm_hpd_init(adev);
2291 * dm_hw_fini() - Teardown DC device
2292 * @handle: The base driver device containing the amdgpu_dm device.
2294 * Teardown components within &struct amdgpu_display_manager that require
2295 * cleanup. This involves cleaning up the DRM device, DC, and any modules that
2296 * were loaded. Also flush IRQ workqueues and disable them.
2298 static int dm_hw_fini(void *handle)
2300 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2302 amdgpu_dm_hpd_fini(adev);
2304 amdgpu_dm_irq_fini(adev);
2305 amdgpu_dm_fini(adev);
2310 static void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev,
2311 struct dc_state *state, bool enable)
2313 enum dc_irq_source irq_source;
2314 struct amdgpu_crtc *acrtc;
2318 for (i = 0; i < state->stream_count; i++) {
2319 acrtc = get_crtc_by_otg_inst(
2320 adev, state->stream_status[i].primary_otg_inst);
2322 if (acrtc && state->stream_status[i].plane_count != 0) {
2323 irq_source = IRQ_TYPE_PFLIP + acrtc->otg_inst;
2324 rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
2325 DRM_DEBUG_VBL("crtc %d - vupdate irq %sabling: r=%d\n",
2326 acrtc->crtc_id, enable ? "en" : "dis", rc);
2328 DRM_WARN("Failed to %s pflip interrupts\n",
2329 enable ? "enable" : "disable");
2332 rc = dm_enable_vblank(&acrtc->base);
2334 DRM_WARN("Failed to enable vblank interrupts\n");
2336 dm_disable_vblank(&acrtc->base);
2344 static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc)
2346 struct dc_state *context = NULL;
2347 enum dc_status res = DC_ERROR_UNEXPECTED;
2349 struct dc_stream_state *del_streams[MAX_PIPES];
2350 int del_streams_count = 0;
2352 memset(del_streams, 0, sizeof(del_streams));
2354 context = dc_create_state(dc);
2355 if (context == NULL)
2356 goto context_alloc_fail;
2358 dc_resource_state_copy_construct_current(dc, context);
2360 /* First remove from context all streams */
2361 for (i = 0; i < context->stream_count; i++) {
2362 struct dc_stream_state *stream = context->streams[i];
2364 del_streams[del_streams_count++] = stream;
2367 /* Remove all planes for removed streams and then remove the streams */
2368 for (i = 0; i < del_streams_count; i++) {
2369 if (!dc_rem_all_planes_for_stream(dc, del_streams[i], context)) {
2370 res = DC_FAIL_DETACH_SURFACES;
2374 res = dc_remove_stream_from_ctx(dc, context, del_streams[i]);
2379 res = dc_commit_state(dc, context);
2382 dc_release_state(context);
2388 static void hpd_rx_irq_work_suspend(struct amdgpu_display_manager *dm)
2392 if (dm->hpd_rx_offload_wq) {
2393 for (i = 0; i < dm->dc->caps.max_links; i++)
2394 flush_workqueue(dm->hpd_rx_offload_wq[i].wq);
2398 static int dm_suspend(void *handle)
2400 struct amdgpu_device *adev = handle;
2401 struct amdgpu_display_manager *dm = &adev->dm;
2404 if (amdgpu_in_reset(adev)) {
2405 mutex_lock(&dm->dc_lock);
2407 dc_allow_idle_optimizations(adev->dm.dc, false);
2409 dm->cached_dc_state = dc_copy_state(dm->dc->current_state);
2411 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false);
2413 amdgpu_dm_commit_zero_streams(dm->dc);
2415 amdgpu_dm_irq_suspend(adev);
2417 hpd_rx_irq_work_suspend(dm);
2422 WARN_ON(adev->dm.cached_state);
2423 adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev));
2425 s3_handle_mst(adev_to_drm(adev), true);
2427 amdgpu_dm_irq_suspend(adev);
2429 hpd_rx_irq_work_suspend(dm);
2431 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
2436 struct amdgpu_dm_connector *
2437 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
2438 struct drm_crtc *crtc)
2441 struct drm_connector_state *new_con_state;
2442 struct drm_connector *connector;
2443 struct drm_crtc *crtc_from_state;
2445 for_each_new_connector_in_state(state, connector, new_con_state, i) {
2446 crtc_from_state = new_con_state->crtc;
2448 if (crtc_from_state == crtc)
2449 return to_amdgpu_dm_connector(connector);
2455 static void emulated_link_detect(struct dc_link *link)
2457 struct dc_sink_init_data sink_init_data = { 0 };
2458 struct display_sink_capability sink_caps = { 0 };
2459 enum dc_edid_status edid_status;
2460 struct dc_context *dc_ctx = link->ctx;
2461 struct dc_sink *sink = NULL;
2462 struct dc_sink *prev_sink = NULL;
2464 link->type = dc_connection_none;
2465 prev_sink = link->local_sink;
2468 dc_sink_release(prev_sink);
2470 switch (link->connector_signal) {
2471 case SIGNAL_TYPE_HDMI_TYPE_A: {
2472 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2473 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
2477 case SIGNAL_TYPE_DVI_SINGLE_LINK: {
2478 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2479 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
2483 case SIGNAL_TYPE_DVI_DUAL_LINK: {
2484 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2485 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
2489 case SIGNAL_TYPE_LVDS: {
2490 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2491 sink_caps.signal = SIGNAL_TYPE_LVDS;
2495 case SIGNAL_TYPE_EDP: {
2496 sink_caps.transaction_type =
2497 DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
2498 sink_caps.signal = SIGNAL_TYPE_EDP;
2502 case SIGNAL_TYPE_DISPLAY_PORT: {
2503 sink_caps.transaction_type =
2504 DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
2505 sink_caps.signal = SIGNAL_TYPE_VIRTUAL;
2510 DC_ERROR("Invalid connector type! signal:%d\n",
2511 link->connector_signal);
2515 sink_init_data.link = link;
2516 sink_init_data.sink_signal = sink_caps.signal;
2518 sink = dc_sink_create(&sink_init_data);
2520 DC_ERROR("Failed to create sink!\n");
2524 /* dc_sink_create returns a new reference */
2525 link->local_sink = sink;
2527 edid_status = dm_helpers_read_local_edid(
2532 if (edid_status != EDID_OK)
2533 DC_ERROR("Failed to read EDID");
2537 static void dm_gpureset_commit_state(struct dc_state *dc_state,
2538 struct amdgpu_display_manager *dm)
2541 struct dc_surface_update surface_updates[MAX_SURFACES];
2542 struct dc_plane_info plane_infos[MAX_SURFACES];
2543 struct dc_scaling_info scaling_infos[MAX_SURFACES];
2544 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
2545 struct dc_stream_update stream_update;
2549 bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
2552 dm_error("Failed to allocate update bundle\n");
2556 for (k = 0; k < dc_state->stream_count; k++) {
2557 bundle->stream_update.stream = dc_state->streams[k];
2559 for (m = 0; m < dc_state->stream_status->plane_count; m++) {
2560 bundle->surface_updates[m].surface =
2561 dc_state->stream_status->plane_states[m];
2562 bundle->surface_updates[m].surface->force_full_update =
2565 dc_commit_updates_for_stream(
2566 dm->dc, bundle->surface_updates,
2567 dc_state->stream_status->plane_count,
2568 dc_state->streams[k], &bundle->stream_update, dc_state);
2577 static int dm_resume(void *handle)
2579 struct amdgpu_device *adev = handle;
2580 struct drm_device *ddev = adev_to_drm(adev);
2581 struct amdgpu_display_manager *dm = &adev->dm;
2582 struct amdgpu_dm_connector *aconnector;
2583 struct drm_connector *connector;
2584 struct drm_connector_list_iter iter;
2585 struct drm_crtc *crtc;
2586 struct drm_crtc_state *new_crtc_state;
2587 struct dm_crtc_state *dm_new_crtc_state;
2588 struct drm_plane *plane;
2589 struct drm_plane_state *new_plane_state;
2590 struct dm_plane_state *dm_new_plane_state;
2591 struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state);
2592 enum dc_connection_type new_connection_type = dc_connection_none;
2593 struct dc_state *dc_state;
2596 if (amdgpu_in_reset(adev)) {
2597 dc_state = dm->cached_dc_state;
2600 * The dc->current_state is backed up into dm->cached_dc_state
2601 * before we commit 0 streams.
2603 * DC will clear link encoder assignments on the real state
2604 * but the changes won't propagate over to the copy we made
2605 * before the 0 streams commit.
2607 * DC expects that link encoder assignments are *not* valid
2608 * when committing a state, so as a workaround we can copy
2609 * off of the current state.
2611 * We lose the previous assignments, but we had already
2612 * commit 0 streams anyway.
2614 link_enc_cfg_copy(adev->dm.dc->current_state, dc_state);
2616 r = dm_dmub_hw_init(adev);
2618 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
2620 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
2623 amdgpu_dm_irq_resume_early(adev);
2625 for (i = 0; i < dc_state->stream_count; i++) {
2626 dc_state->streams[i]->mode_changed = true;
2627 for (j = 0; j < dc_state->stream_status[i].plane_count; j++) {
2628 dc_state->stream_status[i].plane_states[j]->update_flags.raw
2633 if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
2634 amdgpu_dm_outbox_init(adev);
2635 dc_enable_dmub_outbox(adev->dm.dc);
2638 WARN_ON(!dc_commit_state(dm->dc, dc_state));
2640 dm_gpureset_commit_state(dm->cached_dc_state, dm);
2642 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, true);
2644 dc_release_state(dm->cached_dc_state);
2645 dm->cached_dc_state = NULL;
2647 amdgpu_dm_irq_resume_late(adev);
2649 mutex_unlock(&dm->dc_lock);
2653 /* Recreate dc_state - DC invalidates it when setting power state to S3. */
2654 dc_release_state(dm_state->context);
2655 dm_state->context = dc_create_state(dm->dc);
2656 /* TODO: Remove dc_state->dccg, use dc->dccg directly. */
2657 dc_resource_state_construct(dm->dc, dm_state->context);
2659 /* Before powering on DC we need to re-initialize DMUB. */
2660 dm_dmub_hw_resume(adev);
2662 /* Re-enable outbox interrupts for DPIA. */
2663 if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
2664 amdgpu_dm_outbox_init(adev);
2665 dc_enable_dmub_outbox(adev->dm.dc);
2668 /* power on hardware */
2669 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
2671 /* program HPD filter */
2675 * early enable HPD Rx IRQ, should be done before set mode as short
2676 * pulse interrupts are used for MST
2678 amdgpu_dm_irq_resume_early(adev);
2680 /* On resume we need to rewrite the MSTM control bits to enable MST*/
2681 s3_handle_mst(ddev, false);
2684 drm_connector_list_iter_begin(ddev, &iter);
2685 drm_for_each_connector_iter(connector, &iter) {
2686 aconnector = to_amdgpu_dm_connector(connector);
2689 * this is the case when traversing through already created
2690 * MST connectors, should be skipped
2692 if (aconnector->dc_link &&
2693 aconnector->dc_link->type == dc_connection_mst_branch)
2696 mutex_lock(&aconnector->hpd_lock);
2697 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type))
2698 DRM_ERROR("KMS: Failed to detect connector\n");
2700 if (aconnector->base.force && new_connection_type == dc_connection_none) {
2701 emulated_link_detect(aconnector->dc_link);
2703 mutex_lock(&dm->dc_lock);
2704 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
2705 mutex_unlock(&dm->dc_lock);
2708 if (aconnector->fake_enable && aconnector->dc_link->local_sink)
2709 aconnector->fake_enable = false;
2711 if (aconnector->dc_sink)
2712 dc_sink_release(aconnector->dc_sink);
2713 aconnector->dc_sink = NULL;
2714 amdgpu_dm_update_connector_after_detect(aconnector);
2715 mutex_unlock(&aconnector->hpd_lock);
2717 drm_connector_list_iter_end(&iter);
2719 /* Force mode set in atomic commit */
2720 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)
2721 new_crtc_state->active_changed = true;
2724 * atomic_check is expected to create the dc states. We need to release
2725 * them here, since they were duplicated as part of the suspend
2728 for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {
2729 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
2730 if (dm_new_crtc_state->stream) {
2731 WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
2732 dc_stream_release(dm_new_crtc_state->stream);
2733 dm_new_crtc_state->stream = NULL;
2737 for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) {
2738 dm_new_plane_state = to_dm_plane_state(new_plane_state);
2739 if (dm_new_plane_state->dc_state) {
2740 WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
2741 dc_plane_state_release(dm_new_plane_state->dc_state);
2742 dm_new_plane_state->dc_state = NULL;
2746 drm_atomic_helper_resume(ddev, dm->cached_state);
2748 dm->cached_state = NULL;
2750 amdgpu_dm_irq_resume_late(adev);
2752 amdgpu_dm_smu_write_watermarks_table(adev);
2760 * DM (and consequently DC) is registered in the amdgpu base driver as a IP
2761 * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to
2762 * the base driver's device list to be initialized and torn down accordingly.
2764 * The functions to do so are provided as hooks in &struct amd_ip_funcs.
2767 static const struct amd_ip_funcs amdgpu_dm_funcs = {
2769 .early_init = dm_early_init,
2770 .late_init = dm_late_init,
2771 .sw_init = dm_sw_init,
2772 .sw_fini = dm_sw_fini,
2773 .early_fini = amdgpu_dm_early_fini,
2774 .hw_init = dm_hw_init,
2775 .hw_fini = dm_hw_fini,
2776 .suspend = dm_suspend,
2777 .resume = dm_resume,
2778 .is_idle = dm_is_idle,
2779 .wait_for_idle = dm_wait_for_idle,
2780 .check_soft_reset = dm_check_soft_reset,
2781 .soft_reset = dm_soft_reset,
2782 .set_clockgating_state = dm_set_clockgating_state,
2783 .set_powergating_state = dm_set_powergating_state,
2786 const struct amdgpu_ip_block_version dm_ip_block =
2788 .type = AMD_IP_BLOCK_TYPE_DCE,
2792 .funcs = &amdgpu_dm_funcs,
2802 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
2803 .fb_create = amdgpu_display_user_framebuffer_create,
2804 .get_format_info = amd_get_format_info,
2805 .output_poll_changed = drm_fb_helper_output_poll_changed,
2806 .atomic_check = amdgpu_dm_atomic_check,
2807 .atomic_commit = drm_atomic_helper_commit,
2810 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
2811 .atomic_commit_tail = amdgpu_dm_atomic_commit_tail,
2812 .atomic_commit_setup = drm_dp_mst_atomic_setup_commit,
2815 static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector)
2817 struct amdgpu_dm_backlight_caps *caps;
2818 struct amdgpu_display_manager *dm;
2819 struct drm_connector *conn_base;
2820 struct amdgpu_device *adev;
2821 struct dc_link *link = NULL;
2822 struct drm_luminance_range_info *luminance_range;
2825 if (!aconnector || !aconnector->dc_link)
2828 link = aconnector->dc_link;
2829 if (link->connector_signal != SIGNAL_TYPE_EDP)
2832 conn_base = &aconnector->base;
2833 adev = drm_to_adev(conn_base->dev);
2835 for (i = 0; i < dm->num_of_edps; i++) {
2836 if (link == dm->backlight_link[i])
2839 if (i >= dm->num_of_edps)
2841 caps = &dm->backlight_caps[i];
2842 caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps;
2843 caps->aux_support = false;
2845 if (caps->ext_caps->bits.oled == 1 /*||
2846 caps->ext_caps->bits.sdr_aux_backlight_control == 1 ||
2847 caps->ext_caps->bits.hdr_aux_backlight_control == 1*/)
2848 caps->aux_support = true;
2850 if (amdgpu_backlight == 0)
2851 caps->aux_support = false;
2852 else if (amdgpu_backlight == 1)
2853 caps->aux_support = true;
2855 luminance_range = &conn_base->display_info.luminance_range;
2856 caps->aux_min_input_signal = luminance_range->min_luminance;
2857 caps->aux_max_input_signal = luminance_range->max_luminance;
2860 void amdgpu_dm_update_connector_after_detect(
2861 struct amdgpu_dm_connector *aconnector)
2863 struct drm_connector *connector = &aconnector->base;
2864 struct drm_device *dev = connector->dev;
2865 struct dc_sink *sink;
2867 /* MST handled by drm_mst framework */
2868 if (aconnector->mst_mgr.mst_state == true)
2871 sink = aconnector->dc_link->local_sink;
2873 dc_sink_retain(sink);
2876 * Edid mgmt connector gets first update only in mode_valid hook and then
2877 * the connector sink is set to either fake or physical sink depends on link status.
2878 * Skip if already done during boot.
2880 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
2881 && aconnector->dc_em_sink) {
2884 * For S3 resume with headless use eml_sink to fake stream
2885 * because on resume connector->sink is set to NULL
2887 mutex_lock(&dev->mode_config.mutex);
2890 if (aconnector->dc_sink) {
2891 amdgpu_dm_update_freesync_caps(connector, NULL);
2893 * retain and release below are used to
2894 * bump up refcount for sink because the link doesn't point
2895 * to it anymore after disconnect, so on next crtc to connector
2896 * reshuffle by UMD we will get into unwanted dc_sink release
2898 dc_sink_release(aconnector->dc_sink);
2900 aconnector->dc_sink = sink;
2901 dc_sink_retain(aconnector->dc_sink);
2902 amdgpu_dm_update_freesync_caps(connector,
2905 amdgpu_dm_update_freesync_caps(connector, NULL);
2906 if (!aconnector->dc_sink) {
2907 aconnector->dc_sink = aconnector->dc_em_sink;
2908 dc_sink_retain(aconnector->dc_sink);
2912 mutex_unlock(&dev->mode_config.mutex);
2915 dc_sink_release(sink);
2920 * TODO: temporary guard to look for proper fix
2921 * if this sink is MST sink, we should not do anything
2923 if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
2924 dc_sink_release(sink);
2928 if (aconnector->dc_sink == sink) {
2930 * We got a DP short pulse (Link Loss, DP CTS, etc...).
2933 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
2934 aconnector->connector_id);
2936 dc_sink_release(sink);
2940 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
2941 aconnector->connector_id, aconnector->dc_sink, sink);
2943 mutex_lock(&dev->mode_config.mutex);
2946 * 1. Update status of the drm connector
2947 * 2. Send an event and let userspace tell us what to do
2951 * TODO: check if we still need the S3 mode update workaround.
2952 * If yes, put it here.
2954 if (aconnector->dc_sink) {
2955 amdgpu_dm_update_freesync_caps(connector, NULL);
2956 dc_sink_release(aconnector->dc_sink);
2959 aconnector->dc_sink = sink;
2960 dc_sink_retain(aconnector->dc_sink);
2961 if (sink->dc_edid.length == 0) {
2962 aconnector->edid = NULL;
2963 if (aconnector->dc_link->aux_mode) {
2964 drm_dp_cec_unset_edid(
2965 &aconnector->dm_dp_aux.aux);
2969 (struct edid *)sink->dc_edid.raw_edid;
2971 if (aconnector->dc_link->aux_mode)
2972 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,
2976 drm_connector_update_edid_property(connector, aconnector->edid);
2977 amdgpu_dm_update_freesync_caps(connector, aconnector->edid);
2978 update_connector_ext_caps(aconnector);
2980 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
2981 amdgpu_dm_update_freesync_caps(connector, NULL);
2982 drm_connector_update_edid_property(connector, NULL);
2983 aconnector->num_modes = 0;
2984 dc_sink_release(aconnector->dc_sink);
2985 aconnector->dc_sink = NULL;
2986 aconnector->edid = NULL;
2987 #ifdef CONFIG_DRM_AMD_DC_HDCP
2988 /* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */
2989 if (connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
2990 connector->state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
2994 mutex_unlock(&dev->mode_config.mutex);
2996 update_subconnector_property(aconnector);
2999 dc_sink_release(sink);
3002 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector)
3004 struct drm_connector *connector = &aconnector->base;
3005 struct drm_device *dev = connector->dev;
3006 enum dc_connection_type new_connection_type = dc_connection_none;
3007 struct amdgpu_device *adev = drm_to_adev(dev);
3008 #ifdef CONFIG_DRM_AMD_DC_HDCP
3009 struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
3013 if (adev->dm.disable_hpd_irq)
3017 * In case of failure or MST no need to update connector status or notify the OS
3018 * since (for MST case) MST does this in its own context.
3020 mutex_lock(&aconnector->hpd_lock);
3022 #ifdef CONFIG_DRM_AMD_DC_HDCP
3023 if (adev->dm.hdcp_workqueue) {
3024 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
3025 dm_con_state->update_hdcp = true;
3028 if (aconnector->fake_enable)
3029 aconnector->fake_enable = false;
3031 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type))
3032 DRM_ERROR("KMS: Failed to detect connector\n");
3034 if (aconnector->base.force && new_connection_type == dc_connection_none) {
3035 emulated_link_detect(aconnector->dc_link);
3037 drm_modeset_lock_all(dev);
3038 dm_restore_drm_connector_state(dev, connector);
3039 drm_modeset_unlock_all(dev);
3041 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
3042 drm_kms_helper_connector_hotplug_event(connector);
3044 mutex_lock(&adev->dm.dc_lock);
3045 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
3046 mutex_unlock(&adev->dm.dc_lock);
3048 amdgpu_dm_update_connector_after_detect(aconnector);
3050 drm_modeset_lock_all(dev);
3051 dm_restore_drm_connector_state(dev, connector);
3052 drm_modeset_unlock_all(dev);
3054 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
3055 drm_kms_helper_connector_hotplug_event(connector);
3058 mutex_unlock(&aconnector->hpd_lock);
3062 static void handle_hpd_irq(void *param)
3064 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
3066 handle_hpd_irq_helper(aconnector);
3070 static void dm_handle_mst_sideband_msg(struct amdgpu_dm_connector *aconnector)
3072 uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
3074 bool new_irq_handled = false;
3076 int dpcd_bytes_to_read;
3078 const int max_process_count = 30;
3079 int process_count = 0;
3081 const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
3083 if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
3084 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
3085 /* DPCD 0x200 - 0x201 for downstream IRQ */
3086 dpcd_addr = DP_SINK_COUNT;
3088 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
3089 /* DPCD 0x2002 - 0x2005 for downstream IRQ */
3090 dpcd_addr = DP_SINK_COUNT_ESI;
3093 dret = drm_dp_dpcd_read(
3094 &aconnector->dm_dp_aux.aux,
3097 dpcd_bytes_to_read);
3099 while (dret == dpcd_bytes_to_read &&
3100 process_count < max_process_count) {
3106 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3107 /* handle HPD short pulse irq */
3108 if (aconnector->mst_mgr.mst_state)
3110 &aconnector->mst_mgr,
3114 if (new_irq_handled) {
3115 /* ACK at DPCD to notify down stream */
3116 const int ack_dpcd_bytes_to_write =
3117 dpcd_bytes_to_read - 1;
3119 for (retry = 0; retry < 3; retry++) {
3122 wret = drm_dp_dpcd_write(
3123 &aconnector->dm_dp_aux.aux,
3126 ack_dpcd_bytes_to_write);
3127 if (wret == ack_dpcd_bytes_to_write)
3131 /* check if there is new irq to be handled */
3132 dret = drm_dp_dpcd_read(
3133 &aconnector->dm_dp_aux.aux,
3136 dpcd_bytes_to_read);
3138 new_irq_handled = false;
3144 if (process_count == max_process_count)
3145 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
3148 static void schedule_hpd_rx_offload_work(struct hpd_rx_irq_offload_work_queue *offload_wq,
3149 union hpd_irq_data hpd_irq_data)
3151 struct hpd_rx_irq_offload_work *offload_work =
3152 kzalloc(sizeof(*offload_work), GFP_KERNEL);
3154 if (!offload_work) {
3155 DRM_ERROR("Failed to allocate hpd_rx_irq_offload_work.\n");
3159 INIT_WORK(&offload_work->work, dm_handle_hpd_rx_offload_work);
3160 offload_work->data = hpd_irq_data;
3161 offload_work->offload_wq = offload_wq;
3163 queue_work(offload_wq->wq, &offload_work->work);
3164 DRM_DEBUG_KMS("queue work to handle hpd_rx offload work");
3167 static void handle_hpd_rx_irq(void *param)
3169 struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
3170 struct drm_connector *connector = &aconnector->base;
3171 struct drm_device *dev = connector->dev;
3172 struct dc_link *dc_link = aconnector->dc_link;
3173 bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
3174 bool result = false;
3175 enum dc_connection_type new_connection_type = dc_connection_none;
3176 struct amdgpu_device *adev = drm_to_adev(dev);
3177 union hpd_irq_data hpd_irq_data;
3178 bool link_loss = false;
3179 bool has_left_work = false;
3180 int idx = aconnector->base.index;
3181 struct hpd_rx_irq_offload_work_queue *offload_wq = &adev->dm.hpd_rx_offload_wq[idx];
3183 memset(&hpd_irq_data, 0, sizeof(hpd_irq_data));
3185 if (adev->dm.disable_hpd_irq)
3189 * TODO:Temporary add mutex to protect hpd interrupt not have a gpio
3190 * conflict, after implement i2c helper, this mutex should be
3193 mutex_lock(&aconnector->hpd_lock);
3195 result = dc_link_handle_hpd_rx_irq(dc_link, &hpd_irq_data,
3196 &link_loss, true, &has_left_work);
3201 if (hpd_irq_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
3202 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3206 if (dc_link_dp_allow_hpd_rx_irq(dc_link)) {
3207 if (hpd_irq_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY ||
3208 hpd_irq_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) {
3209 dm_handle_mst_sideband_msg(aconnector);
3216 spin_lock(&offload_wq->offload_lock);
3217 skip = offload_wq->is_handling_link_loss;
3220 offload_wq->is_handling_link_loss = true;
3222 spin_unlock(&offload_wq->offload_lock);
3225 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3232 if (result && !is_mst_root_connector) {
3233 /* Downstream Port status changed. */
3234 if (!dc_link_detect_sink(dc_link, &new_connection_type))
3235 DRM_ERROR("KMS: Failed to detect connector\n");
3237 if (aconnector->base.force && new_connection_type == dc_connection_none) {
3238 emulated_link_detect(dc_link);
3240 if (aconnector->fake_enable)
3241 aconnector->fake_enable = false;
3243 amdgpu_dm_update_connector_after_detect(aconnector);
3246 drm_modeset_lock_all(dev);
3247 dm_restore_drm_connector_state(dev, connector);
3248 drm_modeset_unlock_all(dev);
3250 drm_kms_helper_connector_hotplug_event(connector);
3254 mutex_lock(&adev->dm.dc_lock);
3255 ret = dc_link_detect(dc_link, DETECT_REASON_HPDRX);
3256 mutex_unlock(&adev->dm.dc_lock);
3259 if (aconnector->fake_enable)
3260 aconnector->fake_enable = false;
3262 amdgpu_dm_update_connector_after_detect(aconnector);
3264 drm_modeset_lock_all(dev);
3265 dm_restore_drm_connector_state(dev, connector);
3266 drm_modeset_unlock_all(dev);
3268 drm_kms_helper_connector_hotplug_event(connector);
3272 #ifdef CONFIG_DRM_AMD_DC_HDCP
3273 if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ) {
3274 if (adev->dm.hdcp_workqueue)
3275 hdcp_handle_cpirq(adev->dm.hdcp_workqueue, aconnector->base.index);
3279 if (dc_link->type != dc_connection_mst_branch)
3280 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux);
3282 mutex_unlock(&aconnector->hpd_lock);
3285 static void register_hpd_handlers(struct amdgpu_device *adev)
3287 struct drm_device *dev = adev_to_drm(adev);
3288 struct drm_connector *connector;
3289 struct amdgpu_dm_connector *aconnector;
3290 const struct dc_link *dc_link;
3291 struct dc_interrupt_params int_params = {0};
3293 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3294 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3296 list_for_each_entry(connector,
3297 &dev->mode_config.connector_list, head) {
3299 aconnector = to_amdgpu_dm_connector(connector);
3300 dc_link = aconnector->dc_link;
3302 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
3303 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3304 int_params.irq_source = dc_link->irq_source_hpd;
3306 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3308 (void *) aconnector);
3311 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
3313 /* Also register for DP short pulse (hpd_rx). */
3314 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3315 int_params.irq_source = dc_link->irq_source_hpd_rx;
3317 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3319 (void *) aconnector);
3321 if (adev->dm.hpd_rx_offload_wq)
3322 adev->dm.hpd_rx_offload_wq[connector->index].aconnector =
3328 #if defined(CONFIG_DRM_AMD_DC_SI)
3329 /* Register IRQ sources and initialize IRQ callbacks */
3330 static int dce60_register_irq_handlers(struct amdgpu_device *adev)
3332 struct dc *dc = adev->dm.dc;
3333 struct common_irq_params *c_irq_params;
3334 struct dc_interrupt_params int_params = {0};
3337 unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
3339 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3340 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3343 * Actions of amdgpu_irq_add_id():
3344 * 1. Register a set() function with base driver.
3345 * Base driver will call set() function to enable/disable an
3346 * interrupt in DC hardware.
3347 * 2. Register amdgpu_dm_irq_handler().
3348 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3349 * coming from DC hardware.
3350 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3351 * for acknowledging and handling. */
3353 /* Use VBLANK interrupt */
3354 for (i = 0; i < adev->mode_info.num_crtc; i++) {
3355 r = amdgpu_irq_add_id(adev, client_id, i+1 , &adev->crtc_irq);
3357 DRM_ERROR("Failed to add crtc irq id!\n");
3361 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3362 int_params.irq_source =
3363 dc_interrupt_to_irq_source(dc, i+1 , 0);
3365 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3367 c_irq_params->adev = adev;
3368 c_irq_params->irq_src = int_params.irq_source;
3370 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3371 dm_crtc_high_irq, c_irq_params);
3374 /* Use GRPH_PFLIP interrupt */
3375 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
3376 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
3377 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
3379 DRM_ERROR("Failed to add page flip irq id!\n");
3383 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3384 int_params.irq_source =
3385 dc_interrupt_to_irq_source(dc, i, 0);
3387 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3389 c_irq_params->adev = adev;
3390 c_irq_params->irq_src = int_params.irq_source;
3392 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3393 dm_pflip_high_irq, c_irq_params);
3398 r = amdgpu_irq_add_id(adev, client_id,
3399 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
3401 DRM_ERROR("Failed to add hpd irq id!\n");
3405 register_hpd_handlers(adev);
3411 /* Register IRQ sources and initialize IRQ callbacks */
3412 static int dce110_register_irq_handlers(struct amdgpu_device *adev)
3414 struct dc *dc = adev->dm.dc;
3415 struct common_irq_params *c_irq_params;
3416 struct dc_interrupt_params int_params = {0};
3419 unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
3421 if (adev->family >= AMDGPU_FAMILY_AI)
3422 client_id = SOC15_IH_CLIENTID_DCE;
3424 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3425 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3428 * Actions of amdgpu_irq_add_id():
3429 * 1. Register a set() function with base driver.
3430 * Base driver will call set() function to enable/disable an
3431 * interrupt in DC hardware.
3432 * 2. Register amdgpu_dm_irq_handler().
3433 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3434 * coming from DC hardware.
3435 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3436 * for acknowledging and handling. */
3438 /* Use VBLANK interrupt */
3439 for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
3440 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
3442 DRM_ERROR("Failed to add crtc irq id!\n");
3446 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3447 int_params.irq_source =
3448 dc_interrupt_to_irq_source(dc, i, 0);
3450 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3452 c_irq_params->adev = adev;
3453 c_irq_params->irq_src = int_params.irq_source;
3455 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3456 dm_crtc_high_irq, c_irq_params);
3459 /* Use VUPDATE interrupt */
3460 for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) {
3461 r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq);
3463 DRM_ERROR("Failed to add vupdate irq id!\n");
3467 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3468 int_params.irq_source =
3469 dc_interrupt_to_irq_source(dc, i, 0);
3471 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
3473 c_irq_params->adev = adev;
3474 c_irq_params->irq_src = int_params.irq_source;
3476 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3477 dm_vupdate_high_irq, c_irq_params);
3480 /* Use GRPH_PFLIP interrupt */
3481 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
3482 i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
3483 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
3485 DRM_ERROR("Failed to add page flip irq id!\n");
3489 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3490 int_params.irq_source =
3491 dc_interrupt_to_irq_source(dc, i, 0);
3493 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3495 c_irq_params->adev = adev;
3496 c_irq_params->irq_src = int_params.irq_source;
3498 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3499 dm_pflip_high_irq, c_irq_params);
3504 r = amdgpu_irq_add_id(adev, client_id,
3505 VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
3507 DRM_ERROR("Failed to add hpd irq id!\n");
3511 register_hpd_handlers(adev);
3516 /* Register IRQ sources and initialize IRQ callbacks */
3517 static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
3519 struct dc *dc = adev->dm.dc;
3520 struct common_irq_params *c_irq_params;
3521 struct dc_interrupt_params int_params = {0};
3524 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
3525 static const unsigned int vrtl_int_srcid[] = {
3526 DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL,
3527 DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL,
3528 DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL,
3529 DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL,
3530 DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL,
3531 DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL
3535 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3536 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3539 * Actions of amdgpu_irq_add_id():
3540 * 1. Register a set() function with base driver.
3541 * Base driver will call set() function to enable/disable an
3542 * interrupt in DC hardware.
3543 * 2. Register amdgpu_dm_irq_handler().
3544 * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3545 * coming from DC hardware.
3546 * amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3547 * for acknowledging and handling.
3550 /* Use VSTARTUP interrupt */
3551 for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
3552 i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
3554 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);
3557 DRM_ERROR("Failed to add crtc irq id!\n");
3561 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3562 int_params.irq_source =
3563 dc_interrupt_to_irq_source(dc, i, 0);
3565 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3567 c_irq_params->adev = adev;
3568 c_irq_params->irq_src = int_params.irq_source;
3570 amdgpu_dm_irq_register_interrupt(
3571 adev, &int_params, dm_crtc_high_irq, c_irq_params);
3574 /* Use otg vertical line interrupt */
3575 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
3576 for (i = 0; i <= adev->mode_info.num_crtc - 1; i++) {
3577 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE,
3578 vrtl_int_srcid[i], &adev->vline0_irq);
3581 DRM_ERROR("Failed to add vline0 irq id!\n");
3585 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3586 int_params.irq_source =
3587 dc_interrupt_to_irq_source(dc, vrtl_int_srcid[i], 0);
3589 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID) {
3590 DRM_ERROR("Failed to register vline0 irq %d!\n", vrtl_int_srcid[i]);
3594 c_irq_params = &adev->dm.vline0_params[int_params.irq_source
3595 - DC_IRQ_SOURCE_DC1_VLINE0];
3597 c_irq_params->adev = adev;
3598 c_irq_params->irq_src = int_params.irq_source;
3600 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3601 dm_dcn_vertical_interrupt0_high_irq, c_irq_params);
3605 /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to
3606 * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx
3607 * to trigger at end of each vblank, regardless of state of the lock,
3608 * matching DCE behaviour.
3610 for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT;
3611 i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1;
3613 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq);
3616 DRM_ERROR("Failed to add vupdate irq id!\n");
3620 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3621 int_params.irq_source =
3622 dc_interrupt_to_irq_source(dc, i, 0);
3624 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
3626 c_irq_params->adev = adev;
3627 c_irq_params->irq_src = int_params.irq_source;
3629 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3630 dm_vupdate_high_irq, c_irq_params);
3633 /* Use GRPH_PFLIP interrupt */
3634 for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
3635 i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + dc->caps.max_otg_num - 1;
3637 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
3639 DRM_ERROR("Failed to add page flip irq id!\n");
3643 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3644 int_params.irq_source =
3645 dc_interrupt_to_irq_source(dc, i, 0);
3647 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3649 c_irq_params->adev = adev;
3650 c_irq_params->irq_src = int_params.irq_source;
3652 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3653 dm_pflip_high_irq, c_irq_params);
3658 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
3661 DRM_ERROR("Failed to add hpd irq id!\n");
3665 register_hpd_handlers(adev);
3669 /* Register Outbox IRQ sources and initialize IRQ callbacks */
3670 static int register_outbox_irq_handlers(struct amdgpu_device *adev)
3672 struct dc *dc = adev->dm.dc;
3673 struct common_irq_params *c_irq_params;
3674 struct dc_interrupt_params int_params = {0};
3677 int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3678 int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3680 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT,
3681 &adev->dmub_outbox_irq);
3683 DRM_ERROR("Failed to add outbox irq id!\n");
3687 if (dc->ctx->dmub_srv) {
3688 i = DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT;
3689 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3690 int_params.irq_source =
3691 dc_interrupt_to_irq_source(dc, i, 0);
3693 c_irq_params = &adev->dm.dmub_outbox_params[0];
3695 c_irq_params->adev = adev;
3696 c_irq_params->irq_src = int_params.irq_source;
3698 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3699 dm_dmub_outbox1_low_irq, c_irq_params);
3706 * Acquires the lock for the atomic state object and returns
3707 * the new atomic state.
3709 * This should only be called during atomic check.
3711 int dm_atomic_get_state(struct drm_atomic_state *state,
3712 struct dm_atomic_state **dm_state)
3714 struct drm_device *dev = state->dev;
3715 struct amdgpu_device *adev = drm_to_adev(dev);
3716 struct amdgpu_display_manager *dm = &adev->dm;
3717 struct drm_private_state *priv_state;
3722 priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj);
3723 if (IS_ERR(priv_state))
3724 return PTR_ERR(priv_state);
3726 *dm_state = to_dm_atomic_state(priv_state);
3731 static struct dm_atomic_state *
3732 dm_atomic_get_new_state(struct drm_atomic_state *state)
3734 struct drm_device *dev = state->dev;
3735 struct amdgpu_device *adev = drm_to_adev(dev);
3736 struct amdgpu_display_manager *dm = &adev->dm;
3737 struct drm_private_obj *obj;
3738 struct drm_private_state *new_obj_state;
3741 for_each_new_private_obj_in_state(state, obj, new_obj_state, i) {
3742 if (obj->funcs == dm->atomic_obj.funcs)
3743 return to_dm_atomic_state(new_obj_state);
3749 static struct drm_private_state *
3750 dm_atomic_duplicate_state(struct drm_private_obj *obj)
3752 struct dm_atomic_state *old_state, *new_state;
3754 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
3758 __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base);
3760 old_state = to_dm_atomic_state(obj->state);
3762 if (old_state && old_state->context)
3763 new_state->context = dc_copy_state(old_state->context);
3765 if (!new_state->context) {
3770 return &new_state->base;
3773 static void dm_atomic_destroy_state(struct drm_private_obj *obj,
3774 struct drm_private_state *state)
3776 struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
3778 if (dm_state && dm_state->context)
3779 dc_release_state(dm_state->context);
3784 static struct drm_private_state_funcs dm_atomic_state_funcs = {
3785 .atomic_duplicate_state = dm_atomic_duplicate_state,
3786 .atomic_destroy_state = dm_atomic_destroy_state,
3789 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
3791 struct dm_atomic_state *state;
3794 adev->mode_info.mode_config_initialized = true;
3796 adev_to_drm(adev)->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
3797 adev_to_drm(adev)->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
3799 adev_to_drm(adev)->mode_config.max_width = 16384;
3800 adev_to_drm(adev)->mode_config.max_height = 16384;
3802 adev_to_drm(adev)->mode_config.preferred_depth = 24;
3803 if (adev->asic_type == CHIP_HAWAII)
3804 /* disable prefer shadow for now due to hibernation issues */
3805 adev_to_drm(adev)->mode_config.prefer_shadow = 0;
3807 adev_to_drm(adev)->mode_config.prefer_shadow = 1;
3808 /* indicates support for immediate flip */
3809 adev_to_drm(adev)->mode_config.async_page_flip = true;
3811 adev_to_drm(adev)->mode_config.fb_base = adev->gmc.aper_base;
3813 state = kzalloc(sizeof(*state), GFP_KERNEL);
3817 state->context = dc_create_state(adev->dm.dc);
3818 if (!state->context) {
3823 dc_resource_state_copy_construct_current(adev->dm.dc, state->context);
3825 drm_atomic_private_obj_init(adev_to_drm(adev),
3826 &adev->dm.atomic_obj,
3828 &dm_atomic_state_funcs);
3830 r = amdgpu_display_modeset_create_props(adev);
3832 dc_release_state(state->context);
3837 r = amdgpu_dm_audio_init(adev);
3839 dc_release_state(state->context);
3847 #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12
3848 #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255
3849 #define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50
3851 static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm,
3854 #if defined(CONFIG_ACPI)
3855 struct amdgpu_dm_backlight_caps caps;
3857 memset(&caps, 0, sizeof(caps));
3859 if (dm->backlight_caps[bl_idx].caps_valid)
3862 amdgpu_acpi_get_backlight_caps(&caps);
3863 if (caps.caps_valid) {
3864 dm->backlight_caps[bl_idx].caps_valid = true;
3865 if (caps.aux_support)
3867 dm->backlight_caps[bl_idx].min_input_signal = caps.min_input_signal;
3868 dm->backlight_caps[bl_idx].max_input_signal = caps.max_input_signal;
3870 dm->backlight_caps[bl_idx].min_input_signal =
3871 AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
3872 dm->backlight_caps[bl_idx].max_input_signal =
3873 AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
3876 if (dm->backlight_caps[bl_idx].aux_support)
3879 dm->backlight_caps[bl_idx].min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
3880 dm->backlight_caps[bl_idx].max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
3884 static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps,
3885 unsigned *min, unsigned *max)
3890 if (caps->aux_support) {
3891 // Firmware limits are in nits, DC API wants millinits.
3892 *max = 1000 * caps->aux_max_input_signal;
3893 *min = 1000 * caps->aux_min_input_signal;
3895 // Firmware limits are 8-bit, PWM control is 16-bit.
3896 *max = 0x101 * caps->max_input_signal;
3897 *min = 0x101 * caps->min_input_signal;
3902 static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *caps,
3903 uint32_t brightness)
3907 if (!get_brightness_range(caps, &min, &max))
3910 // Rescale 0..255 to min..max
3911 return min + DIV_ROUND_CLOSEST((max - min) * brightness,
3912 AMDGPU_MAX_BL_LEVEL);
3915 static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *caps,
3916 uint32_t brightness)
3920 if (!get_brightness_range(caps, &min, &max))
3923 if (brightness < min)
3925 // Rescale min..max to 0..255
3926 return DIV_ROUND_CLOSEST(AMDGPU_MAX_BL_LEVEL * (brightness - min),
3930 static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm,
3932 u32 user_brightness)
3934 struct amdgpu_dm_backlight_caps caps;
3935 struct dc_link *link;
3939 amdgpu_dm_update_backlight_caps(dm, bl_idx);
3940 caps = dm->backlight_caps[bl_idx];
3942 dm->brightness[bl_idx] = user_brightness;
3943 /* update scratch register */
3945 amdgpu_atombios_scratch_regs_set_backlight_level(dm->adev, dm->brightness[bl_idx]);
3946 brightness = convert_brightness_from_user(&caps, dm->brightness[bl_idx]);
3947 link = (struct dc_link *)dm->backlight_link[bl_idx];
3949 /* Change brightness based on AUX property */
3950 if (caps.aux_support) {
3951 rc = dc_link_set_backlight_level_nits(link, true, brightness,
3952 AUX_BL_DEFAULT_TRANSITION_TIME_MS);
3954 DRM_DEBUG("DM: Failed to update backlight via AUX on eDP[%d]\n", bl_idx);
3956 rc = dc_link_set_backlight_level(link, brightness, 0);
3958 DRM_DEBUG("DM: Failed to update backlight on eDP[%d]\n", bl_idx);
3962 dm->actual_brightness[bl_idx] = user_brightness;
3965 static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
3967 struct amdgpu_display_manager *dm = bl_get_data(bd);
3970 for (i = 0; i < dm->num_of_edps; i++) {
3971 if (bd == dm->backlight_dev[i])
3974 if (i >= AMDGPU_DM_MAX_NUM_EDP)
3976 amdgpu_dm_backlight_set_level(dm, i, bd->props.brightness);
3981 static u32 amdgpu_dm_backlight_get_level(struct amdgpu_display_manager *dm,
3984 struct amdgpu_dm_backlight_caps caps;
3985 struct dc_link *link = (struct dc_link *)dm->backlight_link[bl_idx];
3987 amdgpu_dm_update_backlight_caps(dm, bl_idx);
3988 caps = dm->backlight_caps[bl_idx];
3990 if (caps.aux_support) {
3994 rc = dc_link_get_backlight_level_nits(link, &avg, &peak);
3996 return dm->brightness[bl_idx];
3997 return convert_brightness_to_user(&caps, avg);
3999 int ret = dc_link_get_backlight_level(link);
4001 if (ret == DC_ERROR_UNEXPECTED)
4002 return dm->brightness[bl_idx];
4003 return convert_brightness_to_user(&caps, ret);
4007 static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
4009 struct amdgpu_display_manager *dm = bl_get_data(bd);
4012 for (i = 0; i < dm->num_of_edps; i++) {
4013 if (bd == dm->backlight_dev[i])
4016 if (i >= AMDGPU_DM_MAX_NUM_EDP)
4018 return amdgpu_dm_backlight_get_level(dm, i);
4021 static const struct backlight_ops amdgpu_dm_backlight_ops = {
4022 .options = BL_CORE_SUSPENDRESUME,
4023 .get_brightness = amdgpu_dm_backlight_get_brightness,
4024 .update_status = amdgpu_dm_backlight_update_status,
4028 amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm)
4031 struct backlight_properties props = { 0 };
4033 amdgpu_dm_update_backlight_caps(dm, dm->num_of_edps);
4034 dm->brightness[dm->num_of_edps] = AMDGPU_MAX_BL_LEVEL;
4036 props.max_brightness = AMDGPU_MAX_BL_LEVEL;
4037 props.brightness = AMDGPU_MAX_BL_LEVEL;
4038 props.type = BACKLIGHT_RAW;
4040 snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
4041 adev_to_drm(dm->adev)->primary->index + dm->num_of_edps);
4043 dm->backlight_dev[dm->num_of_edps] = backlight_device_register(bl_name,
4044 adev_to_drm(dm->adev)->dev,
4046 &amdgpu_dm_backlight_ops,
4049 if (IS_ERR(dm->backlight_dev[dm->num_of_edps]))
4050 DRM_ERROR("DM: Backlight registration failed!\n");
4052 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
4055 static int initialize_plane(struct amdgpu_display_manager *dm,
4056 struct amdgpu_mode_info *mode_info, int plane_id,
4057 enum drm_plane_type plane_type,
4058 const struct dc_plane_cap *plane_cap)
4060 struct drm_plane *plane;
4061 unsigned long possible_crtcs;
4064 plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL);
4066 DRM_ERROR("KMS: Failed to allocate plane\n");
4069 plane->type = plane_type;
4072 * HACK: IGT tests expect that the primary plane for a CRTC
4073 * can only have one possible CRTC. Only expose support for
4074 * any CRTC if they're not going to be used as a primary plane
4075 * for a CRTC - like overlay or underlay planes.
4077 possible_crtcs = 1 << plane_id;
4078 if (plane_id >= dm->dc->caps.max_streams)
4079 possible_crtcs = 0xff;
4081 ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap);
4084 DRM_ERROR("KMS: Failed to initialize plane\n");
4090 mode_info->planes[plane_id] = plane;
4096 static void register_backlight_device(struct amdgpu_display_manager *dm,
4097 struct dc_link *link)
4099 if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
4100 link->type != dc_connection_none) {
4102 * Event if registration failed, we should continue with
4103 * DM initialization because not having a backlight control
4104 * is better then a black screen.
4106 if (!dm->backlight_dev[dm->num_of_edps])
4107 amdgpu_dm_register_backlight_device(dm);
4109 if (dm->backlight_dev[dm->num_of_edps]) {
4110 dm->backlight_link[dm->num_of_edps] = link;
4116 static void amdgpu_set_panel_orientation(struct drm_connector *connector);
4119 * In this architecture, the association
4120 * connector -> encoder -> crtc
4121 * id not really requried. The crtc and connector will hold the
4122 * display_index as an abstraction to use with DAL component
4124 * Returns 0 on success
4126 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
4128 struct amdgpu_display_manager *dm = &adev->dm;
4130 struct amdgpu_dm_connector *aconnector = NULL;
4131 struct amdgpu_encoder *aencoder = NULL;
4132 struct amdgpu_mode_info *mode_info = &adev->mode_info;
4134 int32_t primary_planes;
4135 enum dc_connection_type new_connection_type = dc_connection_none;
4136 const struct dc_plane_cap *plane;
4137 bool psr_feature_enabled = false;
4139 dm->display_indexes_num = dm->dc->caps.max_streams;
4140 /* Update the actual used number of crtc */
4141 adev->mode_info.num_crtc = adev->dm.display_indexes_num;
4143 link_cnt = dm->dc->caps.max_links;
4144 if (amdgpu_dm_mode_config_init(dm->adev)) {
4145 DRM_ERROR("DM: Failed to initialize mode config\n");
4149 /* There is one primary plane per CRTC */
4150 primary_planes = dm->dc->caps.max_streams;
4151 ASSERT(primary_planes <= AMDGPU_MAX_PLANES);
4154 * Initialize primary planes, implicit planes for legacy IOCTLS.
4155 * Order is reversed to match iteration order in atomic check.
4157 for (i = (primary_planes - 1); i >= 0; i--) {
4158 plane = &dm->dc->caps.planes[i];
4160 if (initialize_plane(dm, mode_info, i,
4161 DRM_PLANE_TYPE_PRIMARY, plane)) {
4162 DRM_ERROR("KMS: Failed to initialize primary plane\n");
4168 * Initialize overlay planes, index starting after primary planes.
4169 * These planes have a higher DRM index than the primary planes since
4170 * they should be considered as having a higher z-order.
4171 * Order is reversed to match iteration order in atomic check.
4173 * Only support DCN for now, and only expose one so we don't encourage
4174 * userspace to use up all the pipes.
4176 for (i = 0; i < dm->dc->caps.max_planes; ++i) {
4177 struct dc_plane_cap *plane = &dm->dc->caps.planes[i];
4179 /* Do not create overlay if MPO disabled */
4180 if (amdgpu_dc_debug_mask & DC_DISABLE_MPO)
4183 if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL)
4186 if (!plane->blends_with_above || !plane->blends_with_below)
4189 if (!plane->pixel_format_support.argb8888)
4192 if (initialize_plane(dm, NULL, primary_planes + i,
4193 DRM_PLANE_TYPE_OVERLAY, plane)) {
4194 DRM_ERROR("KMS: Failed to initialize overlay plane\n");
4198 /* Only create one overlay plane. */
4202 for (i = 0; i < dm->dc->caps.max_streams; i++)
4203 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) {
4204 DRM_ERROR("KMS: Failed to initialize crtc\n");
4208 /* Use Outbox interrupt */
4209 switch (adev->ip_versions[DCE_HWIP][0]) {
4210 case IP_VERSION(3, 0, 0):
4211 case IP_VERSION(3, 1, 2):
4212 case IP_VERSION(3, 1, 3):
4213 case IP_VERSION(3, 1, 4):
4214 case IP_VERSION(3, 1, 5):
4215 case IP_VERSION(3, 1, 6):
4216 case IP_VERSION(3, 2, 0):
4217 case IP_VERSION(3, 2, 1):
4218 case IP_VERSION(2, 1, 0):
4219 if (register_outbox_irq_handlers(dm->adev)) {
4220 DRM_ERROR("DM: Failed to initialize IRQ\n");
4225 DRM_DEBUG_KMS("Unsupported DCN IP version for outbox: 0x%X\n",
4226 adev->ip_versions[DCE_HWIP][0]);
4229 /* Determine whether to enable PSR support by default. */
4230 if (!(amdgpu_dc_debug_mask & DC_DISABLE_PSR)) {
4231 switch (adev->ip_versions[DCE_HWIP][0]) {
4232 case IP_VERSION(3, 1, 2):
4233 case IP_VERSION(3, 1, 3):
4234 case IP_VERSION(3, 1, 4):
4235 case IP_VERSION(3, 1, 5):
4236 case IP_VERSION(3, 1, 6):
4237 case IP_VERSION(3, 2, 0):
4238 case IP_VERSION(3, 2, 1):
4239 psr_feature_enabled = true;
4242 psr_feature_enabled = amdgpu_dc_feature_mask & DC_PSR_MASK;
4247 /* loops over all connectors on the board */
4248 for (i = 0; i < link_cnt; i++) {
4249 struct dc_link *link = NULL;
4251 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
4253 "KMS: Cannot support more than %d display indexes\n",
4254 AMDGPU_DM_MAX_DISPLAY_INDEX);
4258 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
4262 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
4266 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
4267 DRM_ERROR("KMS: Failed to initialize encoder\n");
4271 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
4272 DRM_ERROR("KMS: Failed to initialize connector\n");
4276 link = dc_get_link_at_index(dm->dc, i);
4278 if (!dc_link_detect_sink(link, &new_connection_type))
4279 DRM_ERROR("KMS: Failed to detect connector\n");
4281 if (aconnector->base.force && new_connection_type == dc_connection_none) {
4282 emulated_link_detect(link);
4283 amdgpu_dm_update_connector_after_detect(aconnector);
4287 mutex_lock(&dm->dc_lock);
4288 ret = dc_link_detect(link, DETECT_REASON_BOOT);
4289 mutex_unlock(&dm->dc_lock);
4292 amdgpu_dm_update_connector_after_detect(aconnector);
4293 register_backlight_device(dm, link);
4295 if (dm->num_of_edps)
4296 update_connector_ext_caps(aconnector);
4298 if (psr_feature_enabled)
4299 amdgpu_dm_set_psr_caps(link);
4301 /* TODO: Fix vblank control helpers to delay PSR entry to allow this when
4302 * PSR is also supported.
4304 if (link->psr_settings.psr_feature_enabled)
4305 adev_to_drm(adev)->vblank_disable_immediate = false;
4308 amdgpu_set_panel_orientation(&aconnector->base);
4311 /* Software is initialized. Now we can register interrupt handlers. */
4312 switch (adev->asic_type) {
4313 #if defined(CONFIG_DRM_AMD_DC_SI)
4318 if (dce60_register_irq_handlers(dm->adev)) {
4319 DRM_ERROR("DM: Failed to initialize IRQ\n");
4333 case CHIP_POLARIS11:
4334 case CHIP_POLARIS10:
4335 case CHIP_POLARIS12:
4340 if (dce110_register_irq_handlers(dm->adev)) {
4341 DRM_ERROR("DM: Failed to initialize IRQ\n");
4346 switch (adev->ip_versions[DCE_HWIP][0]) {
4347 case IP_VERSION(1, 0, 0):
4348 case IP_VERSION(1, 0, 1):
4349 case IP_VERSION(2, 0, 2):
4350 case IP_VERSION(2, 0, 3):
4351 case IP_VERSION(2, 0, 0):
4352 case IP_VERSION(2, 1, 0):
4353 case IP_VERSION(3, 0, 0):
4354 case IP_VERSION(3, 0, 2):
4355 case IP_VERSION(3, 0, 3):
4356 case IP_VERSION(3, 0, 1):
4357 case IP_VERSION(3, 1, 2):
4358 case IP_VERSION(3, 1, 3):
4359 case IP_VERSION(3, 1, 4):
4360 case IP_VERSION(3, 1, 5):
4361 case IP_VERSION(3, 1, 6):
4362 case IP_VERSION(3, 2, 0):
4363 case IP_VERSION(3, 2, 1):
4364 if (dcn10_register_irq_handlers(dm->adev)) {
4365 DRM_ERROR("DM: Failed to initialize IRQ\n");
4370 DRM_ERROR("Unsupported DCE IP versions: 0x%X\n",
4371 adev->ip_versions[DCE_HWIP][0]);
4385 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
4387 drm_atomic_private_obj_fini(&dm->atomic_obj);
4391 /******************************************************************************
4392 * amdgpu_display_funcs functions
4393 *****************************************************************************/
4396 * dm_bandwidth_update - program display watermarks
4398 * @adev: amdgpu_device pointer
4400 * Calculate and program the display watermarks and line buffer allocation.
4402 static void dm_bandwidth_update(struct amdgpu_device *adev)
4404 /* TODO: implement later */
4407 static const struct amdgpu_display_funcs dm_display_funcs = {
4408 .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
4409 .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
4410 .backlight_set_level = NULL, /* never called for DC */
4411 .backlight_get_level = NULL, /* never called for DC */
4412 .hpd_sense = NULL,/* called unconditionally */
4413 .hpd_set_polarity = NULL, /* called unconditionally */
4414 .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
4415 .page_flip_get_scanoutpos =
4416 dm_crtc_get_scanoutpos,/* called unconditionally */
4417 .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
4418 .add_connector = NULL, /* VBIOS parsing. DAL does it. */
4421 #if defined(CONFIG_DEBUG_KERNEL_DC)
4423 static ssize_t s3_debug_store(struct device *device,
4424 struct device_attribute *attr,
4430 struct drm_device *drm_dev = dev_get_drvdata(device);
4431 struct amdgpu_device *adev = drm_to_adev(drm_dev);
4433 ret = kstrtoint(buf, 0, &s3_state);
4438 drm_kms_helper_hotplug_event(adev_to_drm(adev));
4443 return ret == 0 ? count : 0;
4446 DEVICE_ATTR_WO(s3_debug);
4450 static int dm_early_init(void *handle)
4452 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4454 switch (adev->asic_type) {
4455 #if defined(CONFIG_DRM_AMD_DC_SI)
4459 adev->mode_info.num_crtc = 6;
4460 adev->mode_info.num_hpd = 6;
4461 adev->mode_info.num_dig = 6;
4464 adev->mode_info.num_crtc = 2;
4465 adev->mode_info.num_hpd = 2;
4466 adev->mode_info.num_dig = 2;
4471 adev->mode_info.num_crtc = 6;
4472 adev->mode_info.num_hpd = 6;
4473 adev->mode_info.num_dig = 6;
4476 adev->mode_info.num_crtc = 4;
4477 adev->mode_info.num_hpd = 6;
4478 adev->mode_info.num_dig = 7;
4482 adev->mode_info.num_crtc = 2;
4483 adev->mode_info.num_hpd = 6;
4484 adev->mode_info.num_dig = 6;
4488 adev->mode_info.num_crtc = 6;
4489 adev->mode_info.num_hpd = 6;
4490 adev->mode_info.num_dig = 7;
4493 adev->mode_info.num_crtc = 3;
4494 adev->mode_info.num_hpd = 6;
4495 adev->mode_info.num_dig = 9;
4498 adev->mode_info.num_crtc = 2;
4499 adev->mode_info.num_hpd = 6;
4500 adev->mode_info.num_dig = 9;
4502 case CHIP_POLARIS11:
4503 case CHIP_POLARIS12:
4504 adev->mode_info.num_crtc = 5;
4505 adev->mode_info.num_hpd = 5;
4506 adev->mode_info.num_dig = 5;
4508 case CHIP_POLARIS10:
4510 adev->mode_info.num_crtc = 6;
4511 adev->mode_info.num_hpd = 6;
4512 adev->mode_info.num_dig = 6;
4517 adev->mode_info.num_crtc = 6;
4518 adev->mode_info.num_hpd = 6;
4519 adev->mode_info.num_dig = 6;
4523 switch (adev->ip_versions[DCE_HWIP][0]) {
4524 case IP_VERSION(2, 0, 2):
4525 case IP_VERSION(3, 0, 0):
4526 adev->mode_info.num_crtc = 6;
4527 adev->mode_info.num_hpd = 6;
4528 adev->mode_info.num_dig = 6;
4530 case IP_VERSION(2, 0, 0):
4531 case IP_VERSION(3, 0, 2):
4532 adev->mode_info.num_crtc = 5;
4533 adev->mode_info.num_hpd = 5;
4534 adev->mode_info.num_dig = 5;
4536 case IP_VERSION(2, 0, 3):
4537 case IP_VERSION(3, 0, 3):
4538 adev->mode_info.num_crtc = 2;
4539 adev->mode_info.num_hpd = 2;
4540 adev->mode_info.num_dig = 2;
4542 case IP_VERSION(1, 0, 0):
4543 case IP_VERSION(1, 0, 1):
4544 case IP_VERSION(3, 0, 1):
4545 case IP_VERSION(2, 1, 0):
4546 case IP_VERSION(3, 1, 2):
4547 case IP_VERSION(3, 1, 3):
4548 case IP_VERSION(3, 1, 4):
4549 case IP_VERSION(3, 1, 5):
4550 case IP_VERSION(3, 1, 6):
4551 case IP_VERSION(3, 2, 0):
4552 case IP_VERSION(3, 2, 1):
4553 adev->mode_info.num_crtc = 4;
4554 adev->mode_info.num_hpd = 4;
4555 adev->mode_info.num_dig = 4;
4558 DRM_ERROR("Unsupported DCE IP versions: 0x%x\n",
4559 adev->ip_versions[DCE_HWIP][0]);
4565 amdgpu_dm_set_irq_funcs(adev);
4567 if (adev->mode_info.funcs == NULL)
4568 adev->mode_info.funcs = &dm_display_funcs;
4571 * Note: Do NOT change adev->audio_endpt_rreg and
4572 * adev->audio_endpt_wreg because they are initialised in
4573 * amdgpu_device_init()
4575 #if defined(CONFIG_DEBUG_KERNEL_DC)
4577 adev_to_drm(adev)->dev,
4578 &dev_attr_s3_debug);
4584 static bool modereset_required(struct drm_crtc_state *crtc_state)
4586 return !crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state);
4589 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
4591 drm_encoder_cleanup(encoder);
4595 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
4596 .destroy = amdgpu_dm_encoder_destroy,
4600 fill_plane_color_attributes(const struct drm_plane_state *plane_state,
4601 const enum surface_pixel_format format,
4602 enum dc_color_space *color_space)
4606 *color_space = COLOR_SPACE_SRGB;
4608 /* DRM color properties only affect non-RGB formats. */
4609 if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
4612 full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE);
4614 switch (plane_state->color_encoding) {
4615 case DRM_COLOR_YCBCR_BT601:
4617 *color_space = COLOR_SPACE_YCBCR601;
4619 *color_space = COLOR_SPACE_YCBCR601_LIMITED;
4622 case DRM_COLOR_YCBCR_BT709:
4624 *color_space = COLOR_SPACE_YCBCR709;
4626 *color_space = COLOR_SPACE_YCBCR709_LIMITED;
4629 case DRM_COLOR_YCBCR_BT2020:
4631 *color_space = COLOR_SPACE_2020_YCBCR;
4644 fill_dc_plane_info_and_addr(struct amdgpu_device *adev,
4645 const struct drm_plane_state *plane_state,
4646 const uint64_t tiling_flags,
4647 struct dc_plane_info *plane_info,
4648 struct dc_plane_address *address,
4650 bool force_disable_dcc)
4652 const struct drm_framebuffer *fb = plane_state->fb;
4653 const struct amdgpu_framebuffer *afb =
4654 to_amdgpu_framebuffer(plane_state->fb);
4657 memset(plane_info, 0, sizeof(*plane_info));
4659 switch (fb->format->format) {
4661 plane_info->format =
4662 SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
4664 case DRM_FORMAT_RGB565:
4665 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
4667 case DRM_FORMAT_XRGB8888:
4668 case DRM_FORMAT_ARGB8888:
4669 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
4671 case DRM_FORMAT_XRGB2101010:
4672 case DRM_FORMAT_ARGB2101010:
4673 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
4675 case DRM_FORMAT_XBGR2101010:
4676 case DRM_FORMAT_ABGR2101010:
4677 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
4679 case DRM_FORMAT_XBGR8888:
4680 case DRM_FORMAT_ABGR8888:
4681 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888;
4683 case DRM_FORMAT_NV21:
4684 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
4686 case DRM_FORMAT_NV12:
4687 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
4689 case DRM_FORMAT_P010:
4690 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb;
4692 case DRM_FORMAT_XRGB16161616F:
4693 case DRM_FORMAT_ARGB16161616F:
4694 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F;
4696 case DRM_FORMAT_XBGR16161616F:
4697 case DRM_FORMAT_ABGR16161616F:
4698 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F;
4700 case DRM_FORMAT_XRGB16161616:
4701 case DRM_FORMAT_ARGB16161616:
4702 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616;
4704 case DRM_FORMAT_XBGR16161616:
4705 case DRM_FORMAT_ABGR16161616:
4706 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616;
4710 "Unsupported screen format %p4cc\n",
4711 &fb->format->format);
4715 switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
4716 case DRM_MODE_ROTATE_0:
4717 plane_info->rotation = ROTATION_ANGLE_0;
4719 case DRM_MODE_ROTATE_90:
4720 plane_info->rotation = ROTATION_ANGLE_90;
4722 case DRM_MODE_ROTATE_180:
4723 plane_info->rotation = ROTATION_ANGLE_180;
4725 case DRM_MODE_ROTATE_270:
4726 plane_info->rotation = ROTATION_ANGLE_270;
4729 plane_info->rotation = ROTATION_ANGLE_0;
4734 plane_info->visible = true;
4735 plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE;
4737 plane_info->layer_index = 0;
4739 ret = fill_plane_color_attributes(plane_state, plane_info->format,
4740 &plane_info->color_space);
4744 ret = fill_plane_buffer_attributes(adev, afb, plane_info->format,
4745 plane_info->rotation, tiling_flags,
4746 &plane_info->tiling_info,
4747 &plane_info->plane_size,
4748 &plane_info->dcc, address,
4749 tmz_surface, force_disable_dcc);
4753 fill_blending_from_plane_state(
4754 plane_state, &plane_info->per_pixel_alpha, &plane_info->pre_multiplied_alpha,
4755 &plane_info->global_alpha, &plane_info->global_alpha_value);
4760 static int fill_dc_plane_attributes(struct amdgpu_device *adev,
4761 struct dc_plane_state *dc_plane_state,
4762 struct drm_plane_state *plane_state,
4763 struct drm_crtc_state *crtc_state)
4765 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
4766 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)plane_state->fb;
4767 struct dc_scaling_info scaling_info;
4768 struct dc_plane_info plane_info;
4770 bool force_disable_dcc = false;
4772 ret = fill_dc_scaling_info(adev, plane_state, &scaling_info);
4776 dc_plane_state->src_rect = scaling_info.src_rect;
4777 dc_plane_state->dst_rect = scaling_info.dst_rect;
4778 dc_plane_state->clip_rect = scaling_info.clip_rect;
4779 dc_plane_state->scaling_quality = scaling_info.scaling_quality;
4781 force_disable_dcc = adev->asic_type == CHIP_RAVEN && adev->in_suspend;
4782 ret = fill_dc_plane_info_and_addr(adev, plane_state,
4785 &dc_plane_state->address,
4791 dc_plane_state->format = plane_info.format;
4792 dc_plane_state->color_space = plane_info.color_space;
4793 dc_plane_state->format = plane_info.format;
4794 dc_plane_state->plane_size = plane_info.plane_size;
4795 dc_plane_state->rotation = plane_info.rotation;
4796 dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror;
4797 dc_plane_state->stereo_format = plane_info.stereo_format;
4798 dc_plane_state->tiling_info = plane_info.tiling_info;
4799 dc_plane_state->visible = plane_info.visible;
4800 dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha;
4801 dc_plane_state->pre_multiplied_alpha = plane_info.pre_multiplied_alpha;
4802 dc_plane_state->global_alpha = plane_info.global_alpha;
4803 dc_plane_state->global_alpha_value = plane_info.global_alpha_value;
4804 dc_plane_state->dcc = plane_info.dcc;
4805 dc_plane_state->layer_index = plane_info.layer_index; // Always returns 0
4806 dc_plane_state->flip_int_enabled = true;
4809 * Always set input transfer function, since plane state is refreshed
4812 ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dc_plane_state);
4820 * fill_dc_dirty_rects() - Fill DC dirty regions for PSR selective updates
4822 * @plane: DRM plane containing dirty regions that need to be flushed to the eDP
4824 * @old_plane_state: Old state of @plane
4825 * @new_plane_state: New state of @plane
4826 * @crtc_state: New state of CRTC connected to the @plane
4827 * @flip_addrs: DC flip tracking struct, which also tracts dirty rects
4829 * For PSR SU, DC informs the DMUB uController of dirty rectangle regions
4830 * (referred to as "damage clips" in DRM nomenclature) that require updating on
4831 * the eDP remote buffer. The responsibility of specifying the dirty regions is
4834 * A damage-aware DRM client should fill the FB_DAMAGE_CLIPS property on the
4835 * plane with regions that require flushing to the eDP remote buffer. In
4836 * addition, certain use cases - such as cursor and multi-plane overlay (MPO) -
4837 * implicitly provide damage clips without any client support via the plane
4840 * Today, amdgpu_dm only supports the MPO and cursor usecase.
4842 * TODO: Also enable for FB_DAMAGE_CLIPS
4844 static void fill_dc_dirty_rects(struct drm_plane *plane,
4845 struct drm_plane_state *old_plane_state,
4846 struct drm_plane_state *new_plane_state,
4847 struct drm_crtc_state *crtc_state,
4848 struct dc_flip_addrs *flip_addrs)
4850 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
4851 struct rect *dirty_rects = flip_addrs->dirty_rects;
4857 flip_addrs->dirty_rect_count = 0;
4860 * Cursor plane has it's own dirty rect update interface. See
4861 * dcn10_dmub_update_cursor_data and dmub_cmd_update_cursor_info_data
4863 if (plane->type == DRM_PLANE_TYPE_CURSOR)
4867 * Today, we only consider MPO use-case for PSR SU. If MPO not
4868 * requested, and there is a plane update, do FFU.
4870 if (!dm_crtc_state->mpo_requested) {
4871 dirty_rects[0].x = 0;
4872 dirty_rects[0].y = 0;
4873 dirty_rects[0].width = dm_crtc_state->base.mode.crtc_hdisplay;
4874 dirty_rects[0].height = dm_crtc_state->base.mode.crtc_vdisplay;
4875 flip_addrs->dirty_rect_count = 1;
4876 DRM_DEBUG_DRIVER("[PLANE:%d] PSR FFU dirty rect size (%d, %d)\n",
4877 new_plane_state->plane->base.id,
4878 dm_crtc_state->base.mode.crtc_hdisplay,
4879 dm_crtc_state->base.mode.crtc_vdisplay);
4884 * MPO is requested. Add entire plane bounding box to dirty rects if
4885 * flipped to or damaged.
4887 * If plane is moved or resized, also add old bounding box to dirty
4890 num_clips = drm_plane_get_damage_clips_count(new_plane_state);
4891 fb_changed = old_plane_state->fb->base.id !=
4892 new_plane_state->fb->base.id;
4893 bb_changed = (old_plane_state->crtc_x != new_plane_state->crtc_x ||
4894 old_plane_state->crtc_y != new_plane_state->crtc_y ||
4895 old_plane_state->crtc_w != new_plane_state->crtc_w ||
4896 old_plane_state->crtc_h != new_plane_state->crtc_h);
4898 DRM_DEBUG_DRIVER("[PLANE:%d] PSR bb_changed:%d fb_changed:%d num_clips:%d\n",
4899 new_plane_state->plane->base.id,
4900 bb_changed, fb_changed, num_clips);
4902 if (num_clips || fb_changed || bb_changed) {
4903 dirty_rects[i].x = new_plane_state->crtc_x;
4904 dirty_rects[i].y = new_plane_state->crtc_y;
4905 dirty_rects[i].width = new_plane_state->crtc_w;
4906 dirty_rects[i].height = new_plane_state->crtc_h;
4907 DRM_DEBUG_DRIVER("[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)\n",
4908 new_plane_state->plane->base.id,
4909 dirty_rects[i].x, dirty_rects[i].y,
4910 dirty_rects[i].width, dirty_rects[i].height);
4914 /* Add old plane bounding-box if plane is moved or resized */
4916 dirty_rects[i].x = old_plane_state->crtc_x;
4917 dirty_rects[i].y = old_plane_state->crtc_y;
4918 dirty_rects[i].width = old_plane_state->crtc_w;
4919 dirty_rects[i].height = old_plane_state->crtc_h;
4920 DRM_DEBUG_DRIVER("[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)\n",
4921 old_plane_state->plane->base.id,
4922 dirty_rects[i].x, dirty_rects[i].y,
4923 dirty_rects[i].width, dirty_rects[i].height);
4927 flip_addrs->dirty_rect_count = i;
4930 static void update_stream_scaling_settings(const struct drm_display_mode *mode,
4931 const struct dm_connector_state *dm_state,
4932 struct dc_stream_state *stream)
4934 enum amdgpu_rmx_type rmx_type;
4936 struct rect src = { 0 }; /* viewport in composition space*/
4937 struct rect dst = { 0 }; /* stream addressable area */
4939 /* no mode. nothing to be done */
4943 /* Full screen scaling by default */
4944 src.width = mode->hdisplay;
4945 src.height = mode->vdisplay;
4946 dst.width = stream->timing.h_addressable;
4947 dst.height = stream->timing.v_addressable;
4950 rmx_type = dm_state->scaling;
4951 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
4952 if (src.width * dst.height <
4953 src.height * dst.width) {
4954 /* height needs less upscaling/more downscaling */
4955 dst.width = src.width *
4956 dst.height / src.height;
4958 /* width needs less upscaling/more downscaling */
4959 dst.height = src.height *
4960 dst.width / src.width;
4962 } else if (rmx_type == RMX_CENTER) {
4966 dst.x = (stream->timing.h_addressable - dst.width) / 2;
4967 dst.y = (stream->timing.v_addressable - dst.height) / 2;
4969 if (dm_state->underscan_enable) {
4970 dst.x += dm_state->underscan_hborder / 2;
4971 dst.y += dm_state->underscan_vborder / 2;
4972 dst.width -= dm_state->underscan_hborder;
4973 dst.height -= dm_state->underscan_vborder;
4980 DRM_DEBUG_KMS("Destination Rectangle x:%d y:%d width:%d height:%d\n",
4981 dst.x, dst.y, dst.width, dst.height);
4985 static enum dc_color_depth
4986 convert_color_depth_from_display_info(const struct drm_connector *connector,
4987 bool is_y420, int requested_bpc)
4994 /* Cap display bpc based on HDMI 2.0 HF-VSDB */
4995 if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48)
4997 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36)
4999 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30)
5002 bpc = (uint8_t)connector->display_info.bpc;
5003 /* Assume 8 bpc by default if no bpc is specified. */
5004 bpc = bpc ? bpc : 8;
5007 if (requested_bpc > 0) {
5009 * Cap display bpc based on the user requested value.
5011 * The value for state->max_bpc may not correctly updated
5012 * depending on when the connector gets added to the state
5013 * or if this was called outside of atomic check, so it
5014 * can't be used directly.
5016 bpc = min_t(u8, bpc, requested_bpc);
5018 /* Round down to the nearest even number. */
5019 bpc = bpc - (bpc & 1);
5025 * Temporary Work around, DRM doesn't parse color depth for
5026 * EDID revision before 1.4
5027 * TODO: Fix edid parsing
5029 return COLOR_DEPTH_888;
5031 return COLOR_DEPTH_666;
5033 return COLOR_DEPTH_888;
5035 return COLOR_DEPTH_101010;
5037 return COLOR_DEPTH_121212;
5039 return COLOR_DEPTH_141414;
5041 return COLOR_DEPTH_161616;
5043 return COLOR_DEPTH_UNDEFINED;
5047 static enum dc_aspect_ratio
5048 get_aspect_ratio(const struct drm_display_mode *mode_in)
5050 /* 1-1 mapping, since both enums follow the HDMI spec. */
5051 return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio;
5054 static enum dc_color_space
5055 get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
5057 enum dc_color_space color_space = COLOR_SPACE_SRGB;
5059 switch (dc_crtc_timing->pixel_encoding) {
5060 case PIXEL_ENCODING_YCBCR422:
5061 case PIXEL_ENCODING_YCBCR444:
5062 case PIXEL_ENCODING_YCBCR420:
5065 * 27030khz is the separation point between HDTV and SDTV
5066 * according to HDMI spec, we use YCbCr709 and YCbCr601
5069 if (dc_crtc_timing->pix_clk_100hz > 270300) {
5070 if (dc_crtc_timing->flags.Y_ONLY)
5072 COLOR_SPACE_YCBCR709_LIMITED;
5074 color_space = COLOR_SPACE_YCBCR709;
5076 if (dc_crtc_timing->flags.Y_ONLY)
5078 COLOR_SPACE_YCBCR601_LIMITED;
5080 color_space = COLOR_SPACE_YCBCR601;
5085 case PIXEL_ENCODING_RGB:
5086 color_space = COLOR_SPACE_SRGB;
5097 static bool adjust_colour_depth_from_display_info(
5098 struct dc_crtc_timing *timing_out,
5099 const struct drm_display_info *info)
5101 enum dc_color_depth depth = timing_out->display_color_depth;
5104 normalized_clk = timing_out->pix_clk_100hz / 10;
5105 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */
5106 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
5107 normalized_clk /= 2;
5108 /* Adjusting pix clock following on HDMI spec based on colour depth */
5110 case COLOR_DEPTH_888:
5112 case COLOR_DEPTH_101010:
5113 normalized_clk = (normalized_clk * 30) / 24;
5115 case COLOR_DEPTH_121212:
5116 normalized_clk = (normalized_clk * 36) / 24;
5118 case COLOR_DEPTH_161616:
5119 normalized_clk = (normalized_clk * 48) / 24;
5122 /* The above depths are the only ones valid for HDMI. */
5125 if (normalized_clk <= info->max_tmds_clock) {
5126 timing_out->display_color_depth = depth;
5129 } while (--depth > COLOR_DEPTH_666);
5133 static void fill_stream_properties_from_drm_display_mode(
5134 struct dc_stream_state *stream,
5135 const struct drm_display_mode *mode_in,
5136 const struct drm_connector *connector,
5137 const struct drm_connector_state *connector_state,
5138 const struct dc_stream_state *old_stream,
5141 struct dc_crtc_timing *timing_out = &stream->timing;
5142 const struct drm_display_info *info = &connector->display_info;
5143 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
5144 struct hdmi_vendor_infoframe hv_frame;
5145 struct hdmi_avi_infoframe avi_frame;
5147 memset(&hv_frame, 0, sizeof(hv_frame));
5148 memset(&avi_frame, 0, sizeof(avi_frame));
5150 timing_out->h_border_left = 0;
5151 timing_out->h_border_right = 0;
5152 timing_out->v_border_top = 0;
5153 timing_out->v_border_bottom = 0;
5154 /* TODO: un-hardcode */
5155 if (drm_mode_is_420_only(info, mode_in)
5156 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5157 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5158 else if (drm_mode_is_420_also(info, mode_in)
5159 && aconnector->force_yuv420_output)
5160 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5161 else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR444)
5162 && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5163 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
5165 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
5167 timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
5168 timing_out->display_color_depth = convert_color_depth_from_display_info(
5170 (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420),
5172 timing_out->scan_type = SCANNING_TYPE_NODATA;
5173 timing_out->hdmi_vic = 0;
5176 timing_out->vic = old_stream->timing.vic;
5177 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY;
5178 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY;
5180 timing_out->vic = drm_match_cea_mode(mode_in);
5181 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
5182 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
5183 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
5184 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
5187 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
5188 drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, (struct drm_connector *)connector, mode_in);
5189 timing_out->vic = avi_frame.video_code;
5190 drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, (struct drm_connector *)connector, mode_in);
5191 timing_out->hdmi_vic = hv_frame.vic;
5194 if (is_freesync_video_mode(mode_in, aconnector)) {
5195 timing_out->h_addressable = mode_in->hdisplay;
5196 timing_out->h_total = mode_in->htotal;
5197 timing_out->h_sync_width = mode_in->hsync_end - mode_in->hsync_start;
5198 timing_out->h_front_porch = mode_in->hsync_start - mode_in->hdisplay;
5199 timing_out->v_total = mode_in->vtotal;
5200 timing_out->v_addressable = mode_in->vdisplay;
5201 timing_out->v_front_porch = mode_in->vsync_start - mode_in->vdisplay;
5202 timing_out->v_sync_width = mode_in->vsync_end - mode_in->vsync_start;
5203 timing_out->pix_clk_100hz = mode_in->clock * 10;
5205 timing_out->h_addressable = mode_in->crtc_hdisplay;
5206 timing_out->h_total = mode_in->crtc_htotal;
5207 timing_out->h_sync_width = mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
5208 timing_out->h_front_porch = mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
5209 timing_out->v_total = mode_in->crtc_vtotal;
5210 timing_out->v_addressable = mode_in->crtc_vdisplay;
5211 timing_out->v_front_porch = mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
5212 timing_out->v_sync_width = mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
5213 timing_out->pix_clk_100hz = mode_in->crtc_clock * 10;
5216 timing_out->aspect_ratio = get_aspect_ratio(mode_in);
5218 stream->output_color_space = get_output_color_space(timing_out);
5220 stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
5221 stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
5222 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
5223 if (!adjust_colour_depth_from_display_info(timing_out, info) &&
5224 drm_mode_is_420_also(info, mode_in) &&
5225 timing_out->pixel_encoding != PIXEL_ENCODING_YCBCR420) {
5226 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5227 adjust_colour_depth_from_display_info(timing_out, info);
5232 static void fill_audio_info(struct audio_info *audio_info,
5233 const struct drm_connector *drm_connector,
5234 const struct dc_sink *dc_sink)
5237 int cea_revision = 0;
5238 const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
5240 audio_info->manufacture_id = edid_caps->manufacturer_id;
5241 audio_info->product_id = edid_caps->product_id;
5243 cea_revision = drm_connector->display_info.cea_rev;
5245 strscpy(audio_info->display_name,
5246 edid_caps->display_name,
5247 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
5249 if (cea_revision >= 3) {
5250 audio_info->mode_count = edid_caps->audio_mode_count;
5252 for (i = 0; i < audio_info->mode_count; ++i) {
5253 audio_info->modes[i].format_code =
5254 (enum audio_format_code)
5255 (edid_caps->audio_modes[i].format_code);
5256 audio_info->modes[i].channel_count =
5257 edid_caps->audio_modes[i].channel_count;
5258 audio_info->modes[i].sample_rates.all =
5259 edid_caps->audio_modes[i].sample_rate;
5260 audio_info->modes[i].sample_size =
5261 edid_caps->audio_modes[i].sample_size;
5265 audio_info->flags.all = edid_caps->speaker_flags;
5267 /* TODO: We only check for the progressive mode, check for interlace mode too */
5268 if (drm_connector->latency_present[0]) {
5269 audio_info->video_latency = drm_connector->video_latency[0];
5270 audio_info->audio_latency = drm_connector->audio_latency[0];
5273 /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
5278 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
5279 struct drm_display_mode *dst_mode)
5281 dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
5282 dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
5283 dst_mode->crtc_clock = src_mode->crtc_clock;
5284 dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
5285 dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
5286 dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start;
5287 dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
5288 dst_mode->crtc_htotal = src_mode->crtc_htotal;
5289 dst_mode->crtc_hskew = src_mode->crtc_hskew;
5290 dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
5291 dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
5292 dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
5293 dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
5294 dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
5298 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
5299 const struct drm_display_mode *native_mode,
5302 if (scale_enabled) {
5303 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
5304 } else if (native_mode->clock == drm_mode->clock &&
5305 native_mode->htotal == drm_mode->htotal &&
5306 native_mode->vtotal == drm_mode->vtotal) {
5307 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
5309 /* no scaling nor amdgpu inserted, no need to patch */
5313 static struct dc_sink *
5314 create_fake_sink(struct amdgpu_dm_connector *aconnector)
5316 struct dc_sink_init_data sink_init_data = { 0 };
5317 struct dc_sink *sink = NULL;
5318 sink_init_data.link = aconnector->dc_link;
5319 sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
5321 sink = dc_sink_create(&sink_init_data);
5323 DRM_ERROR("Failed to create sink!\n");
5326 sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
5331 static void set_multisync_trigger_params(
5332 struct dc_stream_state *stream)
5334 struct dc_stream_state *master = NULL;
5336 if (stream->triggered_crtc_reset.enabled) {
5337 master = stream->triggered_crtc_reset.event_source;
5338 stream->triggered_crtc_reset.event =
5339 master->timing.flags.VSYNC_POSITIVE_POLARITY ?
5340 CRTC_EVENT_VSYNC_RISING : CRTC_EVENT_VSYNC_FALLING;
5341 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_PIXEL;
5345 static void set_master_stream(struct dc_stream_state *stream_set[],
5348 int j, highest_rfr = 0, master_stream = 0;
5350 for (j = 0; j < stream_count; j++) {
5351 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
5352 int refresh_rate = 0;
5354 refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/
5355 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
5356 if (refresh_rate > highest_rfr) {
5357 highest_rfr = refresh_rate;
5362 for (j = 0; j < stream_count; j++) {
5364 stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
5368 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
5371 struct dc_stream_state *stream;
5373 if (context->stream_count < 2)
5375 for (i = 0; i < context->stream_count ; i++) {
5376 if (!context->streams[i])
5379 * TODO: add a function to read AMD VSDB bits and set
5380 * crtc_sync_master.multi_sync_enabled flag
5381 * For now it's set to false
5385 set_master_stream(context->streams, context->stream_count);
5387 for (i = 0; i < context->stream_count ; i++) {
5388 stream = context->streams[i];
5393 set_multisync_trigger_params(stream);
5398 * DOC: FreeSync Video
5400 * When a userspace application wants to play a video, the content follows a
5401 * standard format definition that usually specifies the FPS for that format.
5402 * The below list illustrates some video format and the expected FPS,
5405 * - TV/NTSC (23.976 FPS)
5408 * - TV/NTSC (29.97 FPS)
5409 * - TV/NTSC (30 FPS)
5410 * - Cinema HFR (48 FPS)
5412 * - Commonly used (60 FPS)
5413 * - Multiples of 24 (48,72,96 FPS)
5415 * The list of standards video format is not huge and can be added to the
5416 * connector modeset list beforehand. With that, userspace can leverage
5417 * FreeSync to extends the front porch in order to attain the target refresh
5418 * rate. Such a switch will happen seamlessly, without screen blanking or
5419 * reprogramming of the output in any other way. If the userspace requests a
5420 * modesetting change compatible with FreeSync modes that only differ in the
5421 * refresh rate, DC will skip the full update and avoid blink during the
5422 * transition. For example, the video player can change the modesetting from
5423 * 60Hz to 30Hz for playing TV/NTSC content when it goes full screen without
5424 * causing any display blink. This same concept can be applied to a mode
5427 static struct drm_display_mode *
5428 get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector,
5429 bool use_probed_modes)
5431 struct drm_display_mode *m, *m_pref = NULL;
5432 u16 current_refresh, highest_refresh;
5433 struct list_head *list_head = use_probed_modes ?
5434 &aconnector->base.probed_modes :
5435 &aconnector->base.modes;
5437 if (aconnector->freesync_vid_base.clock != 0)
5438 return &aconnector->freesync_vid_base;
5440 /* Find the preferred mode */
5441 list_for_each_entry (m, list_head, head) {
5442 if (m->type & DRM_MODE_TYPE_PREFERRED) {
5449 /* Probably an EDID with no preferred mode. Fallback to first entry */
5450 m_pref = list_first_entry_or_null(
5451 &aconnector->base.modes, struct drm_display_mode, head);
5453 DRM_DEBUG_DRIVER("No preferred mode found in EDID\n");
5458 highest_refresh = drm_mode_vrefresh(m_pref);
5461 * Find the mode with highest refresh rate with same resolution.
5462 * For some monitors, preferred mode is not the mode with highest
5463 * supported refresh rate.
5465 list_for_each_entry (m, list_head, head) {
5466 current_refresh = drm_mode_vrefresh(m);
5468 if (m->hdisplay == m_pref->hdisplay &&
5469 m->vdisplay == m_pref->vdisplay &&
5470 highest_refresh < current_refresh) {
5471 highest_refresh = current_refresh;
5476 drm_mode_copy(&aconnector->freesync_vid_base, m_pref);
5480 static bool is_freesync_video_mode(const struct drm_display_mode *mode,
5481 struct amdgpu_dm_connector *aconnector)
5483 struct drm_display_mode *high_mode;
5486 high_mode = get_highest_refresh_rate_mode(aconnector, false);
5487 if (!high_mode || !mode)
5490 timing_diff = high_mode->vtotal - mode->vtotal;
5492 if (high_mode->clock == 0 || high_mode->clock != mode->clock ||
5493 high_mode->hdisplay != mode->hdisplay ||
5494 high_mode->vdisplay != mode->vdisplay ||
5495 high_mode->hsync_start != mode->hsync_start ||
5496 high_mode->hsync_end != mode->hsync_end ||
5497 high_mode->htotal != mode->htotal ||
5498 high_mode->hskew != mode->hskew ||
5499 high_mode->vscan != mode->vscan ||
5500 high_mode->vsync_start - mode->vsync_start != timing_diff ||
5501 high_mode->vsync_end - mode->vsync_end != timing_diff)
5507 #if defined(CONFIG_DRM_AMD_DC_DCN)
5508 static void update_dsc_caps(struct amdgpu_dm_connector *aconnector,
5509 struct dc_sink *sink, struct dc_stream_state *stream,
5510 struct dsc_dec_dpcd_caps *dsc_caps)
5512 stream->timing.flags.DSC = 0;
5513 dsc_caps->is_dsc_supported = false;
5515 if (aconnector->dc_link && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT ||
5516 sink->sink_signal == SIGNAL_TYPE_EDP)) {
5517 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE ||
5518 sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER)
5519 dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
5520 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
5521 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
5527 static void apply_dsc_policy_for_edp(struct amdgpu_dm_connector *aconnector,
5528 struct dc_sink *sink, struct dc_stream_state *stream,
5529 struct dsc_dec_dpcd_caps *dsc_caps,
5530 uint32_t max_dsc_target_bpp_limit_override)
5532 const struct dc_link_settings *verified_link_cap = NULL;
5533 uint32_t link_bw_in_kbps;
5534 uint32_t edp_min_bpp_x16, edp_max_bpp_x16;
5535 struct dc *dc = sink->ctx->dc;
5536 struct dc_dsc_bw_range bw_range = {0};
5537 struct dc_dsc_config dsc_cfg = {0};
5539 verified_link_cap = dc_link_get_link_cap(stream->link);
5540 link_bw_in_kbps = dc_link_bandwidth_kbps(stream->link, verified_link_cap);
5541 edp_min_bpp_x16 = 8 * 16;
5542 edp_max_bpp_x16 = 8 * 16;
5544 if (edp_max_bpp_x16 > dsc_caps->edp_max_bits_per_pixel)
5545 edp_max_bpp_x16 = dsc_caps->edp_max_bits_per_pixel;
5547 if (edp_max_bpp_x16 < edp_min_bpp_x16)
5548 edp_min_bpp_x16 = edp_max_bpp_x16;
5550 if (dc_dsc_compute_bandwidth_range(dc->res_pool->dscs[0],
5551 dc->debug.dsc_min_slice_height_override,
5552 edp_min_bpp_x16, edp_max_bpp_x16,
5557 if (bw_range.max_kbps < link_bw_in_kbps) {
5558 if (dc_dsc_compute_config(dc->res_pool->dscs[0],
5560 dc->debug.dsc_min_slice_height_override,
5561 max_dsc_target_bpp_limit_override,
5565 stream->timing.dsc_cfg = dsc_cfg;
5566 stream->timing.flags.DSC = 1;
5567 stream->timing.dsc_cfg.bits_per_pixel = edp_max_bpp_x16;
5573 if (dc_dsc_compute_config(dc->res_pool->dscs[0],
5575 dc->debug.dsc_min_slice_height_override,
5576 max_dsc_target_bpp_limit_override,
5580 stream->timing.dsc_cfg = dsc_cfg;
5581 stream->timing.flags.DSC = 1;
5586 static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector,
5587 struct dc_sink *sink, struct dc_stream_state *stream,
5588 struct dsc_dec_dpcd_caps *dsc_caps)
5590 struct drm_connector *drm_connector = &aconnector->base;
5591 uint32_t link_bandwidth_kbps;
5592 uint32_t max_dsc_target_bpp_limit_override = 0;
5593 struct dc *dc = sink->ctx->dc;
5594 uint32_t max_supported_bw_in_kbps, timing_bw_in_kbps;
5595 uint32_t dsc_max_supported_bw_in_kbps;
5597 link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
5598 dc_link_get_link_cap(aconnector->dc_link));
5599 if (stream->link && stream->link->local_sink)
5600 max_dsc_target_bpp_limit_override =
5601 stream->link->local_sink->edid_caps.panel_patch.max_dsc_target_bpp_limit;
5603 /* Set DSC policy according to dsc_clock_en */
5604 dc_dsc_policy_set_enable_dsc_when_not_needed(
5605 aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE);
5607 if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_EDP && !dc->debug.disable_dsc_edp &&
5608 dc->caps.edp_dsc_support && aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE) {
5610 apply_dsc_policy_for_edp(aconnector, sink, stream, dsc_caps, max_dsc_target_bpp_limit_override);
5612 } else if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) {
5613 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) {
5614 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
5616 aconnector->dc_link->ctx->dc->debug.dsc_min_slice_height_override,
5617 max_dsc_target_bpp_limit_override,
5618 link_bandwidth_kbps,
5620 &stream->timing.dsc_cfg)) {
5621 stream->timing.flags.DSC = 1;
5622 DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from SST RX\n", __func__, drm_connector->name);
5624 } else if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) {
5625 timing_bw_in_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing);
5626 max_supported_bw_in_kbps = link_bandwidth_kbps;
5627 dsc_max_supported_bw_in_kbps = link_bandwidth_kbps;
5629 if (timing_bw_in_kbps > max_supported_bw_in_kbps &&
5630 max_supported_bw_in_kbps > 0 &&
5631 dsc_max_supported_bw_in_kbps > 0)
5632 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
5634 aconnector->dc_link->ctx->dc->debug.dsc_min_slice_height_override,
5635 max_dsc_target_bpp_limit_override,
5636 dsc_max_supported_bw_in_kbps,
5638 &stream->timing.dsc_cfg)) {
5639 stream->timing.flags.DSC = 1;
5640 DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from DP-HDMI PCON\n",
5641 __func__, drm_connector->name);
5646 /* Overwrite the stream flag if DSC is enabled through debugfs */
5647 if (aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE)
5648 stream->timing.flags.DSC = 1;
5650 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_h)
5651 stream->timing.dsc_cfg.num_slices_h = aconnector->dsc_settings.dsc_num_slices_h;
5653 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_v)
5654 stream->timing.dsc_cfg.num_slices_v = aconnector->dsc_settings.dsc_num_slices_v;
5656 if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_bits_per_pixel)
5657 stream->timing.dsc_cfg.bits_per_pixel = aconnector->dsc_settings.dsc_bits_per_pixel;
5659 #endif /* CONFIG_DRM_AMD_DC_DCN */
5661 static struct dc_stream_state *
5662 create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
5663 const struct drm_display_mode *drm_mode,
5664 const struct dm_connector_state *dm_state,
5665 const struct dc_stream_state *old_stream,
5668 struct drm_display_mode *preferred_mode = NULL;
5669 struct drm_connector *drm_connector;
5670 const struct drm_connector_state *con_state =
5671 dm_state ? &dm_state->base : NULL;
5672 struct dc_stream_state *stream = NULL;
5673 struct drm_display_mode mode = *drm_mode;
5674 struct drm_display_mode saved_mode;
5675 struct drm_display_mode *freesync_mode = NULL;
5676 bool native_mode_found = false;
5677 bool recalculate_timing = false;
5678 bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false;
5680 int preferred_refresh = 0;
5681 #if defined(CONFIG_DRM_AMD_DC_DCN)
5682 struct dsc_dec_dpcd_caps dsc_caps;
5685 struct dc_sink *sink = NULL;
5687 memset(&saved_mode, 0, sizeof(saved_mode));
5689 if (aconnector == NULL) {
5690 DRM_ERROR("aconnector is NULL!\n");
5694 drm_connector = &aconnector->base;
5696 if (!aconnector->dc_sink) {
5697 sink = create_fake_sink(aconnector);
5701 sink = aconnector->dc_sink;
5702 dc_sink_retain(sink);
5705 stream = dc_create_stream_for_sink(sink);
5707 if (stream == NULL) {
5708 DRM_ERROR("Failed to create stream for sink!\n");
5712 stream->dm_stream_context = aconnector;
5714 stream->timing.flags.LTE_340MCSC_SCRAMBLE =
5715 drm_connector->display_info.hdmi.scdc.scrambling.low_rates;
5717 list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
5718 /* Search for preferred mode */
5719 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
5720 native_mode_found = true;
5724 if (!native_mode_found)
5725 preferred_mode = list_first_entry_or_null(
5726 &aconnector->base.modes,
5727 struct drm_display_mode,
5730 mode_refresh = drm_mode_vrefresh(&mode);
5732 if (preferred_mode == NULL) {
5734 * This may not be an error, the use case is when we have no
5735 * usermode calls to reset and set mode upon hotplug. In this
5736 * case, we call set mode ourselves to restore the previous mode
5737 * and the modelist may not be filled in in time.
5739 DRM_DEBUG_DRIVER("No preferred mode found\n");
5741 recalculate_timing = is_freesync_video_mode(&mode, aconnector);
5742 if (recalculate_timing) {
5743 freesync_mode = get_highest_refresh_rate_mode(aconnector, false);
5744 drm_mode_copy(&saved_mode, &mode);
5745 drm_mode_copy(&mode, freesync_mode);
5747 decide_crtc_timing_for_drm_display_mode(
5748 &mode, preferred_mode, scale);
5750 preferred_refresh = drm_mode_vrefresh(preferred_mode);
5754 if (recalculate_timing)
5755 drm_mode_set_crtcinfo(&saved_mode, 0);
5757 drm_mode_set_crtcinfo(&mode, 0);
5760 * If scaling is enabled and refresh rate didn't change
5761 * we copy the vic and polarities of the old timings
5763 if (!scale || mode_refresh != preferred_refresh)
5764 fill_stream_properties_from_drm_display_mode(
5765 stream, &mode, &aconnector->base, con_state, NULL,
5768 fill_stream_properties_from_drm_display_mode(
5769 stream, &mode, &aconnector->base, con_state, old_stream,
5772 #if defined(CONFIG_DRM_AMD_DC_DCN)
5773 /* SST DSC determination policy */
5774 update_dsc_caps(aconnector, sink, stream, &dsc_caps);
5775 if (aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE && dsc_caps.is_dsc_supported)
5776 apply_dsc_policy_for_stream(aconnector, sink, stream, &dsc_caps);
5779 update_stream_scaling_settings(&mode, dm_state, stream);
5782 &stream->audio_info,
5786 update_stream_signal(stream, sink);
5788 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5789 mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket);
5791 if (stream->link->psr_settings.psr_feature_enabled) {
5793 // should decide stream support vsc sdp colorimetry capability
5794 // before building vsc info packet
5796 stream->use_vsc_sdp_for_colorimetry = false;
5797 if (aconnector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
5798 stream->use_vsc_sdp_for_colorimetry =
5799 aconnector->dc_sink->is_vsc_sdp_colorimetry_supported;
5801 if (stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED)
5802 stream->use_vsc_sdp_for_colorimetry = true;
5804 mod_build_vsc_infopacket(stream, &stream->vsc_infopacket, stream->output_color_space);
5805 aconnector->psr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY;
5809 dc_sink_release(sink);
5814 static enum drm_connector_status
5815 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
5818 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
5822 * 1. This interface is NOT called in context of HPD irq.
5823 * 2. This interface *is called* in context of user-mode ioctl. Which
5824 * makes it a bad place for *any* MST-related activity.
5827 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
5828 !aconnector->fake_enable)
5829 connected = (aconnector->dc_sink != NULL);
5831 connected = (aconnector->base.force == DRM_FORCE_ON ||
5832 aconnector->base.force == DRM_FORCE_ON_DIGITAL);
5834 update_subconnector_property(aconnector);
5836 return (connected ? connector_status_connected :
5837 connector_status_disconnected);
5840 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
5841 struct drm_connector_state *connector_state,
5842 struct drm_property *property,
5845 struct drm_device *dev = connector->dev;
5846 struct amdgpu_device *adev = drm_to_adev(dev);
5847 struct dm_connector_state *dm_old_state =
5848 to_dm_connector_state(connector->state);
5849 struct dm_connector_state *dm_new_state =
5850 to_dm_connector_state(connector_state);
5854 if (property == dev->mode_config.scaling_mode_property) {
5855 enum amdgpu_rmx_type rmx_type;
5858 case DRM_MODE_SCALE_CENTER:
5859 rmx_type = RMX_CENTER;
5861 case DRM_MODE_SCALE_ASPECT:
5862 rmx_type = RMX_ASPECT;
5864 case DRM_MODE_SCALE_FULLSCREEN:
5865 rmx_type = RMX_FULL;
5867 case DRM_MODE_SCALE_NONE:
5873 if (dm_old_state->scaling == rmx_type)
5876 dm_new_state->scaling = rmx_type;
5878 } else if (property == adev->mode_info.underscan_hborder_property) {
5879 dm_new_state->underscan_hborder = val;
5881 } else if (property == adev->mode_info.underscan_vborder_property) {
5882 dm_new_state->underscan_vborder = val;
5884 } else if (property == adev->mode_info.underscan_property) {
5885 dm_new_state->underscan_enable = val;
5887 } else if (property == adev->mode_info.abm_level_property) {
5888 dm_new_state->abm_level = val;
5895 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
5896 const struct drm_connector_state *state,
5897 struct drm_property *property,
5900 struct drm_device *dev = connector->dev;
5901 struct amdgpu_device *adev = drm_to_adev(dev);
5902 struct dm_connector_state *dm_state =
5903 to_dm_connector_state(state);
5906 if (property == dev->mode_config.scaling_mode_property) {
5907 switch (dm_state->scaling) {
5909 *val = DRM_MODE_SCALE_CENTER;
5912 *val = DRM_MODE_SCALE_ASPECT;
5915 *val = DRM_MODE_SCALE_FULLSCREEN;
5919 *val = DRM_MODE_SCALE_NONE;
5923 } else if (property == adev->mode_info.underscan_hborder_property) {
5924 *val = dm_state->underscan_hborder;
5926 } else if (property == adev->mode_info.underscan_vborder_property) {
5927 *val = dm_state->underscan_vborder;
5929 } else if (property == adev->mode_info.underscan_property) {
5930 *val = dm_state->underscan_enable;
5932 } else if (property == adev->mode_info.abm_level_property) {
5933 *val = dm_state->abm_level;
5940 static void amdgpu_dm_connector_unregister(struct drm_connector *connector)
5942 struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector);
5944 drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux);
5947 static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
5949 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
5950 const struct dc_link *link = aconnector->dc_link;
5951 struct amdgpu_device *adev = drm_to_adev(connector->dev);
5952 struct amdgpu_display_manager *dm = &adev->dm;
5956 * Call only if mst_mgr was initialized before since it's not done
5957 * for all connector types.
5959 if (aconnector->mst_mgr.dev)
5960 drm_dp_mst_topology_mgr_destroy(&aconnector->mst_mgr);
5962 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
5963 defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
5964 for (i = 0; i < dm->num_of_edps; i++) {
5965 if ((link == dm->backlight_link[i]) && dm->backlight_dev[i]) {
5966 backlight_device_unregister(dm->backlight_dev[i]);
5967 dm->backlight_dev[i] = NULL;
5972 if (aconnector->dc_em_sink)
5973 dc_sink_release(aconnector->dc_em_sink);
5974 aconnector->dc_em_sink = NULL;
5975 if (aconnector->dc_sink)
5976 dc_sink_release(aconnector->dc_sink);
5977 aconnector->dc_sink = NULL;
5979 drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux);
5980 drm_connector_unregister(connector);
5981 drm_connector_cleanup(connector);
5982 if (aconnector->i2c) {
5983 i2c_del_adapter(&aconnector->i2c->base);
5984 kfree(aconnector->i2c);
5986 kfree(aconnector->dm_dp_aux.aux.name);
5991 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
5993 struct dm_connector_state *state =
5994 to_dm_connector_state(connector->state);
5996 if (connector->state)
5997 __drm_atomic_helper_connector_destroy_state(connector->state);
6001 state = kzalloc(sizeof(*state), GFP_KERNEL);
6004 state->scaling = RMX_OFF;
6005 state->underscan_enable = false;
6006 state->underscan_hborder = 0;
6007 state->underscan_vborder = 0;
6008 state->base.max_requested_bpc = 8;
6009 state->vcpi_slots = 0;
6012 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
6013 state->abm_level = amdgpu_dm_abm_level;
6015 __drm_atomic_helper_connector_reset(connector, &state->base);
6019 struct drm_connector_state *
6020 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
6022 struct dm_connector_state *state =
6023 to_dm_connector_state(connector->state);
6025 struct dm_connector_state *new_state =
6026 kmemdup(state, sizeof(*state), GFP_KERNEL);
6031 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
6033 new_state->freesync_capable = state->freesync_capable;
6034 new_state->abm_level = state->abm_level;
6035 new_state->scaling = state->scaling;
6036 new_state->underscan_enable = state->underscan_enable;
6037 new_state->underscan_hborder = state->underscan_hborder;
6038 new_state->underscan_vborder = state->underscan_vborder;
6039 new_state->vcpi_slots = state->vcpi_slots;
6040 new_state->pbn = state->pbn;
6041 return &new_state->base;
6045 amdgpu_dm_connector_late_register(struct drm_connector *connector)
6047 struct amdgpu_dm_connector *amdgpu_dm_connector =
6048 to_amdgpu_dm_connector(connector);
6051 if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
6052 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
6053 amdgpu_dm_connector->dm_dp_aux.aux.dev = connector->kdev;
6054 r = drm_dp_aux_register(&amdgpu_dm_connector->dm_dp_aux.aux);
6059 #if defined(CONFIG_DEBUG_FS)
6060 connector_debugfs_init(amdgpu_dm_connector);
6066 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
6067 .reset = amdgpu_dm_connector_funcs_reset,
6068 .detect = amdgpu_dm_connector_detect,
6069 .fill_modes = drm_helper_probe_single_connector_modes,
6070 .destroy = amdgpu_dm_connector_destroy,
6071 .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
6072 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
6073 .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
6074 .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
6075 .late_register = amdgpu_dm_connector_late_register,
6076 .early_unregister = amdgpu_dm_connector_unregister
6079 static int get_modes(struct drm_connector *connector)
6081 return amdgpu_dm_connector_get_modes(connector);
6084 static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
6086 struct dc_sink_init_data init_params = {
6087 .link = aconnector->dc_link,
6088 .sink_signal = SIGNAL_TYPE_VIRTUAL
6092 if (!aconnector->base.edid_blob_ptr) {
6093 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
6094 aconnector->base.name);
6096 aconnector->base.force = DRM_FORCE_OFF;
6097 aconnector->base.override_edid = false;
6101 edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
6103 aconnector->edid = edid;
6105 aconnector->dc_em_sink = dc_link_add_remote_sink(
6106 aconnector->dc_link,
6108 (edid->extensions + 1) * EDID_LENGTH,
6111 if (aconnector->base.force == DRM_FORCE_ON) {
6112 aconnector->dc_sink = aconnector->dc_link->local_sink ?
6113 aconnector->dc_link->local_sink :
6114 aconnector->dc_em_sink;
6115 dc_sink_retain(aconnector->dc_sink);
6119 static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
6121 struct dc_link *link = (struct dc_link *)aconnector->dc_link;
6124 * In case of headless boot with force on for DP managed connector
6125 * Those settings have to be != 0 to get initial modeset
6127 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
6128 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
6129 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
6133 aconnector->base.override_edid = true;
6134 create_eml_sink(aconnector);
6137 struct dc_stream_state *
6138 create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector,
6139 const struct drm_display_mode *drm_mode,
6140 const struct dm_connector_state *dm_state,
6141 const struct dc_stream_state *old_stream)
6143 struct drm_connector *connector = &aconnector->base;
6144 struct amdgpu_device *adev = drm_to_adev(connector->dev);
6145 struct dc_stream_state *stream;
6146 const struct drm_connector_state *drm_state = dm_state ? &dm_state->base : NULL;
6147 int requested_bpc = drm_state ? drm_state->max_requested_bpc : 8;
6148 enum dc_status dc_result = DC_OK;
6151 stream = create_stream_for_sink(aconnector, drm_mode,
6152 dm_state, old_stream,
6154 if (stream == NULL) {
6155 DRM_ERROR("Failed to create stream for sink!\n");
6159 dc_result = dc_validate_stream(adev->dm.dc, stream);
6160 if (dc_result == DC_OK && stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
6161 dc_result = dm_dp_mst_is_port_support_mode(aconnector, stream);
6163 if (dc_result != DC_OK) {
6164 DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n",
6169 dc_status_to_str(dc_result));
6171 dc_stream_release(stream);
6173 requested_bpc -= 2; /* lower bpc to retry validation */
6176 } while (stream == NULL && requested_bpc >= 6);
6178 if (dc_result == DC_FAIL_ENC_VALIDATE && !aconnector->force_yuv420_output) {
6179 DRM_DEBUG_KMS("Retry forcing YCbCr420 encoding\n");
6181 aconnector->force_yuv420_output = true;
6182 stream = create_validate_stream_for_sink(aconnector, drm_mode,
6183 dm_state, old_stream);
6184 aconnector->force_yuv420_output = false;
6190 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
6191 struct drm_display_mode *mode)
6193 int result = MODE_ERROR;
6194 struct dc_sink *dc_sink;
6195 /* TODO: Unhardcode stream count */
6196 struct dc_stream_state *stream;
6197 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6199 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
6200 (mode->flags & DRM_MODE_FLAG_DBLSCAN))
6204 * Only run this the first time mode_valid is called to initilialize
6207 if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
6208 !aconnector->dc_em_sink)
6209 handle_edid_mgmt(aconnector);
6211 dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
6213 if (dc_sink == NULL && aconnector->base.force != DRM_FORCE_ON_DIGITAL &&
6214 aconnector->base.force != DRM_FORCE_ON) {
6215 DRM_ERROR("dc_sink is NULL!\n");
6219 stream = create_validate_stream_for_sink(aconnector, mode, NULL, NULL);
6221 dc_stream_release(stream);
6226 /* TODO: error handling*/
6230 static int fill_hdr_info_packet(const struct drm_connector_state *state,
6231 struct dc_info_packet *out)
6233 struct hdmi_drm_infoframe frame;
6234 unsigned char buf[30]; /* 26 + 4 */
6238 memset(out, 0, sizeof(*out));
6240 if (!state->hdr_output_metadata)
6243 ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state);
6247 len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf));
6251 /* Static metadata is a fixed 26 bytes + 4 byte header. */
6255 /* Prepare the infopacket for DC. */
6256 switch (state->connector->connector_type) {
6257 case DRM_MODE_CONNECTOR_HDMIA:
6258 out->hb0 = 0x87; /* type */
6259 out->hb1 = 0x01; /* version */
6260 out->hb2 = 0x1A; /* length */
6261 out->sb[0] = buf[3]; /* checksum */
6265 case DRM_MODE_CONNECTOR_DisplayPort:
6266 case DRM_MODE_CONNECTOR_eDP:
6267 out->hb0 = 0x00; /* sdp id, zero */
6268 out->hb1 = 0x87; /* type */
6269 out->hb2 = 0x1D; /* payload len - 1 */
6270 out->hb3 = (0x13 << 2); /* sdp version */
6271 out->sb[0] = 0x01; /* version */
6272 out->sb[1] = 0x1A; /* length */
6280 memcpy(&out->sb[i], &buf[4], 26);
6283 print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb,
6284 sizeof(out->sb), false);
6290 amdgpu_dm_connector_atomic_check(struct drm_connector *conn,
6291 struct drm_atomic_state *state)
6293 struct drm_connector_state *new_con_state =
6294 drm_atomic_get_new_connector_state(state, conn);
6295 struct drm_connector_state *old_con_state =
6296 drm_atomic_get_old_connector_state(state, conn);
6297 struct drm_crtc *crtc = new_con_state->crtc;
6298 struct drm_crtc_state *new_crtc_state;
6299 struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(conn);
6302 trace_amdgpu_dm_connector_atomic_check(new_con_state);
6304 if (conn->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
6305 ret = drm_dp_mst_root_conn_atomic_check(new_con_state, &aconn->mst_mgr);
6313 if (!drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state)) {
6314 struct dc_info_packet hdr_infopacket;
6316 ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket);
6320 new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
6321 if (IS_ERR(new_crtc_state))
6322 return PTR_ERR(new_crtc_state);
6325 * DC considers the stream backends changed if the
6326 * static metadata changes. Forcing the modeset also
6327 * gives a simple way for userspace to switch from
6328 * 8bpc to 10bpc when setting the metadata to enter
6331 * Changing the static metadata after it's been
6332 * set is permissible, however. So only force a
6333 * modeset if we're entering or exiting HDR.
6335 new_crtc_state->mode_changed =
6336 !old_con_state->hdr_output_metadata ||
6337 !new_con_state->hdr_output_metadata;
6343 static const struct drm_connector_helper_funcs
6344 amdgpu_dm_connector_helper_funcs = {
6346 * If hotplugging a second bigger display in FB Con mode, bigger resolution
6347 * modes will be filtered by drm_mode_validate_size(), and those modes
6348 * are missing after user start lightdm. So we need to renew modes list.
6349 * in get_modes call back, not just return the modes count
6351 .get_modes = get_modes,
6352 .mode_valid = amdgpu_dm_connector_mode_valid,
6353 .atomic_check = amdgpu_dm_connector_atomic_check,
6356 static void dm_encoder_helper_disable(struct drm_encoder *encoder)
6361 int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth)
6363 switch (display_color_depth) {
6364 case COLOR_DEPTH_666:
6366 case COLOR_DEPTH_888:
6368 case COLOR_DEPTH_101010:
6370 case COLOR_DEPTH_121212:
6372 case COLOR_DEPTH_141414:
6374 case COLOR_DEPTH_161616:
6382 static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
6383 struct drm_crtc_state *crtc_state,
6384 struct drm_connector_state *conn_state)
6386 struct drm_atomic_state *state = crtc_state->state;
6387 struct drm_connector *connector = conn_state->connector;
6388 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6389 struct dm_connector_state *dm_new_connector_state = to_dm_connector_state(conn_state);
6390 const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
6391 struct drm_dp_mst_topology_mgr *mst_mgr;
6392 struct drm_dp_mst_port *mst_port;
6393 struct drm_dp_mst_topology_state *mst_state;
6394 enum dc_color_depth color_depth;
6396 bool is_y420 = false;
6398 if (!aconnector->port || !aconnector->dc_sink)
6401 mst_port = aconnector->port;
6402 mst_mgr = &aconnector->mst_port->mst_mgr;
6404 if (!crtc_state->connectors_changed && !crtc_state->mode_changed)
6407 mst_state = drm_atomic_get_mst_topology_state(state, mst_mgr);
6408 if (IS_ERR(mst_state))
6409 return PTR_ERR(mst_state);
6411 if (!mst_state->pbn_div)
6412 mst_state->pbn_div = dm_mst_get_pbn_divider(aconnector->mst_port->dc_link);
6414 if (!state->duplicated) {
6415 int max_bpc = conn_state->max_requested_bpc;
6416 is_y420 = drm_mode_is_420_also(&connector->display_info, adjusted_mode) &&
6417 aconnector->force_yuv420_output;
6418 color_depth = convert_color_depth_from_display_info(connector,
6421 bpp = convert_dc_color_depth_into_bpc(color_depth) * 3;
6422 clock = adjusted_mode->clock;
6423 dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp, false);
6426 dm_new_connector_state->vcpi_slots =
6427 drm_dp_atomic_find_time_slots(state, mst_mgr, mst_port,
6428 dm_new_connector_state->pbn);
6429 if (dm_new_connector_state->vcpi_slots < 0) {
6430 DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots);
6431 return dm_new_connector_state->vcpi_slots;
6436 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
6437 .disable = dm_encoder_helper_disable,
6438 .atomic_check = dm_encoder_helper_atomic_check
6441 #if defined(CONFIG_DRM_AMD_DC_DCN)
6442 static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state,
6443 struct dc_state *dc_state,
6444 struct dsc_mst_fairness_vars *vars)
6446 struct dc_stream_state *stream = NULL;
6447 struct drm_connector *connector;
6448 struct drm_connector_state *new_con_state;
6449 struct amdgpu_dm_connector *aconnector;
6450 struct dm_connector_state *dm_conn_state;
6452 int vcpi, pbn_div, pbn, slot_num = 0;
6454 for_each_new_connector_in_state(state, connector, new_con_state, i) {
6456 aconnector = to_amdgpu_dm_connector(connector);
6458 if (!aconnector->port)
6461 if (!new_con_state || !new_con_state->crtc)
6464 dm_conn_state = to_dm_connector_state(new_con_state);
6466 for (j = 0; j < dc_state->stream_count; j++) {
6467 stream = dc_state->streams[j];
6471 if ((struct amdgpu_dm_connector *)stream->dm_stream_context == aconnector)
6480 pbn_div = dm_mst_get_pbn_divider(stream->link);
6481 /* pbn is calculated by compute_mst_dsc_configs_for_state*/
6482 for (j = 0; j < dc_state->stream_count; j++) {
6483 if (vars[j].aconnector == aconnector) {
6489 if (j == dc_state->stream_count)
6492 slot_num = DIV_ROUND_UP(pbn, pbn_div);
6494 if (stream->timing.flags.DSC != 1) {
6495 dm_conn_state->pbn = pbn;
6496 dm_conn_state->vcpi_slots = slot_num;
6498 drm_dp_mst_atomic_enable_dsc(state, aconnector->port, dm_conn_state->pbn,
6503 vcpi = drm_dp_mst_atomic_enable_dsc(state, aconnector->port, pbn, true);
6507 dm_conn_state->pbn = pbn;
6508 dm_conn_state->vcpi_slots = vcpi;
6514 static int to_drm_connector_type(enum signal_type st)
6517 case SIGNAL_TYPE_HDMI_TYPE_A:
6518 return DRM_MODE_CONNECTOR_HDMIA;
6519 case SIGNAL_TYPE_EDP:
6520 return DRM_MODE_CONNECTOR_eDP;
6521 case SIGNAL_TYPE_LVDS:
6522 return DRM_MODE_CONNECTOR_LVDS;
6523 case SIGNAL_TYPE_RGB:
6524 return DRM_MODE_CONNECTOR_VGA;
6525 case SIGNAL_TYPE_DISPLAY_PORT:
6526 case SIGNAL_TYPE_DISPLAY_PORT_MST:
6527 return DRM_MODE_CONNECTOR_DisplayPort;
6528 case SIGNAL_TYPE_DVI_DUAL_LINK:
6529 case SIGNAL_TYPE_DVI_SINGLE_LINK:
6530 return DRM_MODE_CONNECTOR_DVID;
6531 case SIGNAL_TYPE_VIRTUAL:
6532 return DRM_MODE_CONNECTOR_VIRTUAL;
6535 return DRM_MODE_CONNECTOR_Unknown;
6539 static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector)
6541 struct drm_encoder *encoder;
6543 /* There is only one encoder per connector */
6544 drm_connector_for_each_possible_encoder(connector, encoder)
6550 static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
6552 struct drm_encoder *encoder;
6553 struct amdgpu_encoder *amdgpu_encoder;
6555 encoder = amdgpu_dm_connector_to_encoder(connector);
6557 if (encoder == NULL)
6560 amdgpu_encoder = to_amdgpu_encoder(encoder);
6562 amdgpu_encoder->native_mode.clock = 0;
6564 if (!list_empty(&connector->probed_modes)) {
6565 struct drm_display_mode *preferred_mode = NULL;
6567 list_for_each_entry(preferred_mode,
6568 &connector->probed_modes,
6570 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
6571 amdgpu_encoder->native_mode = *preferred_mode;
6579 static struct drm_display_mode *
6580 amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
6582 int hdisplay, int vdisplay)
6584 struct drm_device *dev = encoder->dev;
6585 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
6586 struct drm_display_mode *mode = NULL;
6587 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
6589 mode = drm_mode_duplicate(dev, native_mode);
6594 mode->hdisplay = hdisplay;
6595 mode->vdisplay = vdisplay;
6596 mode->type &= ~DRM_MODE_TYPE_PREFERRED;
6597 strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
6603 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
6604 struct drm_connector *connector)
6606 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
6607 struct drm_display_mode *mode = NULL;
6608 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
6609 struct amdgpu_dm_connector *amdgpu_dm_connector =
6610 to_amdgpu_dm_connector(connector);
6614 char name[DRM_DISPLAY_MODE_LEN];
6617 } common_modes[] = {
6618 { "640x480", 640, 480},
6619 { "800x600", 800, 600},
6620 { "1024x768", 1024, 768},
6621 { "1280x720", 1280, 720},
6622 { "1280x800", 1280, 800},
6623 {"1280x1024", 1280, 1024},
6624 { "1440x900", 1440, 900},
6625 {"1680x1050", 1680, 1050},
6626 {"1600x1200", 1600, 1200},
6627 {"1920x1080", 1920, 1080},
6628 {"1920x1200", 1920, 1200}
6631 n = ARRAY_SIZE(common_modes);
6633 for (i = 0; i < n; i++) {
6634 struct drm_display_mode *curmode = NULL;
6635 bool mode_existed = false;
6637 if (common_modes[i].w > native_mode->hdisplay ||
6638 common_modes[i].h > native_mode->vdisplay ||
6639 (common_modes[i].w == native_mode->hdisplay &&
6640 common_modes[i].h == native_mode->vdisplay))
6643 list_for_each_entry(curmode, &connector->probed_modes, head) {
6644 if (common_modes[i].w == curmode->hdisplay &&
6645 common_modes[i].h == curmode->vdisplay) {
6646 mode_existed = true;
6654 mode = amdgpu_dm_create_common_mode(encoder,
6655 common_modes[i].name, common_modes[i].w,
6660 drm_mode_probed_add(connector, mode);
6661 amdgpu_dm_connector->num_modes++;
6665 static void amdgpu_set_panel_orientation(struct drm_connector *connector)
6667 struct drm_encoder *encoder;
6668 struct amdgpu_encoder *amdgpu_encoder;
6669 const struct drm_display_mode *native_mode;
6671 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP &&
6672 connector->connector_type != DRM_MODE_CONNECTOR_LVDS)
6675 mutex_lock(&connector->dev->mode_config.mutex);
6676 amdgpu_dm_connector_get_modes(connector);
6677 mutex_unlock(&connector->dev->mode_config.mutex);
6679 encoder = amdgpu_dm_connector_to_encoder(connector);
6683 amdgpu_encoder = to_amdgpu_encoder(encoder);
6685 native_mode = &amdgpu_encoder->native_mode;
6686 if (native_mode->hdisplay == 0 || native_mode->vdisplay == 0)
6689 drm_connector_set_panel_orientation_with_quirk(connector,
6690 DRM_MODE_PANEL_ORIENTATION_UNKNOWN,
6691 native_mode->hdisplay,
6692 native_mode->vdisplay);
6695 static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
6698 struct amdgpu_dm_connector *amdgpu_dm_connector =
6699 to_amdgpu_dm_connector(connector);
6702 /* empty probed_modes */
6703 INIT_LIST_HEAD(&connector->probed_modes);
6704 amdgpu_dm_connector->num_modes =
6705 drm_add_edid_modes(connector, edid);
6707 /* sorting the probed modes before calling function
6708 * amdgpu_dm_get_native_mode() since EDID can have
6709 * more than one preferred mode. The modes that are
6710 * later in the probed mode list could be of higher
6711 * and preferred resolution. For example, 3840x2160
6712 * resolution in base EDID preferred timing and 4096x2160
6713 * preferred resolution in DID extension block later.
6715 drm_mode_sort(&connector->probed_modes);
6716 amdgpu_dm_get_native_mode(connector);
6718 /* Freesync capabilities are reset by calling
6719 * drm_add_edid_modes() and need to be
6722 amdgpu_dm_update_freesync_caps(connector, edid);
6724 amdgpu_dm_connector->num_modes = 0;
6728 static bool is_duplicate_mode(struct amdgpu_dm_connector *aconnector,
6729 struct drm_display_mode *mode)
6731 struct drm_display_mode *m;
6733 list_for_each_entry (m, &aconnector->base.probed_modes, head) {
6734 if (drm_mode_equal(m, mode))
6741 static uint add_fs_modes(struct amdgpu_dm_connector *aconnector)
6743 const struct drm_display_mode *m;
6744 struct drm_display_mode *new_mode;
6746 uint32_t new_modes_count = 0;
6748 /* Standard FPS values
6757 * 60 - Commonly used
6758 * 48,72,96,120 - Multiples of 24
6760 static const uint32_t common_rates[] = {
6761 23976, 24000, 25000, 29970, 30000,
6762 48000, 50000, 60000, 72000, 96000, 120000
6766 * Find mode with highest refresh rate with the same resolution
6767 * as the preferred mode. Some monitors report a preferred mode
6768 * with lower resolution than the highest refresh rate supported.
6771 m = get_highest_refresh_rate_mode(aconnector, true);
6775 for (i = 0; i < ARRAY_SIZE(common_rates); i++) {
6776 uint64_t target_vtotal, target_vtotal_diff;
6779 if (drm_mode_vrefresh(m) * 1000 < common_rates[i])
6782 if (common_rates[i] < aconnector->min_vfreq * 1000 ||
6783 common_rates[i] > aconnector->max_vfreq * 1000)
6786 num = (unsigned long long)m->clock * 1000 * 1000;
6787 den = common_rates[i] * (unsigned long long)m->htotal;
6788 target_vtotal = div_u64(num, den);
6789 target_vtotal_diff = target_vtotal - m->vtotal;
6791 /* Check for illegal modes */
6792 if (m->vsync_start + target_vtotal_diff < m->vdisplay ||
6793 m->vsync_end + target_vtotal_diff < m->vsync_start ||
6794 m->vtotal + target_vtotal_diff < m->vsync_end)
6797 new_mode = drm_mode_duplicate(aconnector->base.dev, m);
6801 new_mode->vtotal += (u16)target_vtotal_diff;
6802 new_mode->vsync_start += (u16)target_vtotal_diff;
6803 new_mode->vsync_end += (u16)target_vtotal_diff;
6804 new_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
6805 new_mode->type |= DRM_MODE_TYPE_DRIVER;
6807 if (!is_duplicate_mode(aconnector, new_mode)) {
6808 drm_mode_probed_add(&aconnector->base, new_mode);
6809 new_modes_count += 1;
6811 drm_mode_destroy(aconnector->base.dev, new_mode);
6814 return new_modes_count;
6817 static void amdgpu_dm_connector_add_freesync_modes(struct drm_connector *connector,
6820 struct amdgpu_dm_connector *amdgpu_dm_connector =
6821 to_amdgpu_dm_connector(connector);
6826 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
6827 amdgpu_dm_connector->num_modes +=
6828 add_fs_modes(amdgpu_dm_connector);
6831 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
6833 struct amdgpu_dm_connector *amdgpu_dm_connector =
6834 to_amdgpu_dm_connector(connector);
6835 struct drm_encoder *encoder;
6836 struct edid *edid = amdgpu_dm_connector->edid;
6838 encoder = amdgpu_dm_connector_to_encoder(connector);
6840 if (!drm_edid_is_valid(edid)) {
6841 amdgpu_dm_connector->num_modes =
6842 drm_add_modes_noedid(connector, 640, 480);
6844 amdgpu_dm_connector_ddc_get_modes(connector, edid);
6845 amdgpu_dm_connector_add_common_modes(encoder, connector);
6846 amdgpu_dm_connector_add_freesync_modes(connector, edid);
6848 amdgpu_dm_fbc_init(connector);
6850 return amdgpu_dm_connector->num_modes;
6853 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
6854 struct amdgpu_dm_connector *aconnector,
6856 struct dc_link *link,
6859 struct amdgpu_device *adev = drm_to_adev(dm->ddev);
6862 * Some of the properties below require access to state, like bpc.
6863 * Allocate some default initial connector state with our reset helper.
6865 if (aconnector->base.funcs->reset)
6866 aconnector->base.funcs->reset(&aconnector->base);
6868 aconnector->connector_id = link_index;
6869 aconnector->dc_link = link;
6870 aconnector->base.interlace_allowed = false;
6871 aconnector->base.doublescan_allowed = false;
6872 aconnector->base.stereo_allowed = false;
6873 aconnector->base.dpms = DRM_MODE_DPMS_OFF;
6874 aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
6875 aconnector->audio_inst = -1;
6876 mutex_init(&aconnector->hpd_lock);
6879 * configure support HPD hot plug connector_>polled default value is 0
6880 * which means HPD hot plug not supported
6882 switch (connector_type) {
6883 case DRM_MODE_CONNECTOR_HDMIA:
6884 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
6885 aconnector->base.ycbcr_420_allowed =
6886 link->link_enc->features.hdmi_ycbcr420_supported ? true : false;
6888 case DRM_MODE_CONNECTOR_DisplayPort:
6889 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
6890 link->link_enc = link_enc_cfg_get_link_enc(link);
6891 ASSERT(link->link_enc);
6893 aconnector->base.ycbcr_420_allowed =
6894 link->link_enc->features.dp_ycbcr420_supported ? true : false;
6896 case DRM_MODE_CONNECTOR_DVID:
6897 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
6903 drm_object_attach_property(&aconnector->base.base,
6904 dm->ddev->mode_config.scaling_mode_property,
6905 DRM_MODE_SCALE_NONE);
6907 drm_object_attach_property(&aconnector->base.base,
6908 adev->mode_info.underscan_property,
6910 drm_object_attach_property(&aconnector->base.base,
6911 adev->mode_info.underscan_hborder_property,
6913 drm_object_attach_property(&aconnector->base.base,
6914 adev->mode_info.underscan_vborder_property,
6917 if (!aconnector->mst_port)
6918 drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16);
6920 /* This defaults to the max in the range, but we want 8bpc for non-edp. */
6921 aconnector->base.state->max_bpc = (connector_type == DRM_MODE_CONNECTOR_eDP) ? 16 : 8;
6922 aconnector->base.state->max_requested_bpc = aconnector->base.state->max_bpc;
6924 if (connector_type == DRM_MODE_CONNECTOR_eDP &&
6925 (dc_is_dmcu_initialized(adev->dm.dc) || adev->dm.dc->ctx->dmub_srv)) {
6926 drm_object_attach_property(&aconnector->base.base,
6927 adev->mode_info.abm_level_property, 0);
6930 if (connector_type == DRM_MODE_CONNECTOR_HDMIA ||
6931 connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
6932 connector_type == DRM_MODE_CONNECTOR_eDP) {
6933 drm_connector_attach_hdr_output_metadata_property(&aconnector->base);
6935 if (!aconnector->mst_port)
6936 drm_connector_attach_vrr_capable_property(&aconnector->base);
6938 #ifdef CONFIG_DRM_AMD_DC_HDCP
6939 if (adev->dm.hdcp_workqueue)
6940 drm_connector_attach_content_protection_property(&aconnector->base, true);
6945 static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
6946 struct i2c_msg *msgs, int num)
6948 struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
6949 struct ddc_service *ddc_service = i2c->ddc_service;
6950 struct i2c_command cmd;
6954 cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
6959 cmd.number_of_payloads = num;
6960 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
6963 for (i = 0; i < num; i++) {
6964 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
6965 cmd.payloads[i].address = msgs[i].addr;
6966 cmd.payloads[i].length = msgs[i].len;
6967 cmd.payloads[i].data = msgs[i].buf;
6971 ddc_service->ctx->dc,
6972 ddc_service->link->link_index,
6976 kfree(cmd.payloads);
6980 static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
6982 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
6985 static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
6986 .master_xfer = amdgpu_dm_i2c_xfer,
6987 .functionality = amdgpu_dm_i2c_func,
6990 static struct amdgpu_i2c_adapter *
6991 create_i2c(struct ddc_service *ddc_service,
6995 struct amdgpu_device *adev = ddc_service->ctx->driver_context;
6996 struct amdgpu_i2c_adapter *i2c;
6998 i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
7001 i2c->base.owner = THIS_MODULE;
7002 i2c->base.class = I2C_CLASS_DDC;
7003 i2c->base.dev.parent = &adev->pdev->dev;
7004 i2c->base.algo = &amdgpu_dm_i2c_algo;
7005 snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
7006 i2c_set_adapdata(&i2c->base, i2c);
7007 i2c->ddc_service = ddc_service;
7014 * Note: this function assumes that dc_link_detect() was called for the
7015 * dc_link which will be represented by this aconnector.
7017 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
7018 struct amdgpu_dm_connector *aconnector,
7019 uint32_t link_index,
7020 struct amdgpu_encoder *aencoder)
7024 struct dc *dc = dm->dc;
7025 struct dc_link *link = dc_get_link_at_index(dc, link_index);
7026 struct amdgpu_i2c_adapter *i2c;
7028 link->priv = aconnector;
7030 DRM_DEBUG_DRIVER("%s()\n", __func__);
7032 i2c = create_i2c(link->ddc, link->link_index, &res);
7034 DRM_ERROR("Failed to create i2c adapter data\n");
7038 aconnector->i2c = i2c;
7039 res = i2c_add_adapter(&i2c->base);
7042 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
7046 connector_type = to_drm_connector_type(link->connector_signal);
7048 res = drm_connector_init_with_ddc(
7051 &amdgpu_dm_connector_funcs,
7056 DRM_ERROR("connector_init failed\n");
7057 aconnector->connector_id = -1;
7061 drm_connector_helper_add(
7063 &amdgpu_dm_connector_helper_funcs);
7065 amdgpu_dm_connector_init_helper(
7072 drm_connector_attach_encoder(
7073 &aconnector->base, &aencoder->base);
7075 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
7076 || connector_type == DRM_MODE_CONNECTOR_eDP)
7077 amdgpu_dm_initialize_dp_connector(dm, aconnector, link->link_index);
7082 aconnector->i2c = NULL;
7087 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
7089 switch (adev->mode_info.num_crtc) {
7106 static int amdgpu_dm_encoder_init(struct drm_device *dev,
7107 struct amdgpu_encoder *aencoder,
7108 uint32_t link_index)
7110 struct amdgpu_device *adev = drm_to_adev(dev);
7112 int res = drm_encoder_init(dev,
7114 &amdgpu_dm_encoder_funcs,
7115 DRM_MODE_ENCODER_TMDS,
7118 aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
7121 aencoder->encoder_id = link_index;
7123 aencoder->encoder_id = -1;
7125 drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
7130 static void manage_dm_interrupts(struct amdgpu_device *adev,
7131 struct amdgpu_crtc *acrtc,
7135 * We have no guarantee that the frontend index maps to the same
7136 * backend index - some even map to more than one.
7138 * TODO: Use a different interrupt or check DC itself for the mapping.
7141 amdgpu_display_crtc_idx_to_irq_type(
7146 drm_crtc_vblank_on(&acrtc->base);
7149 &adev->pageflip_irq,
7151 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
7158 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
7166 &adev->pageflip_irq,
7168 drm_crtc_vblank_off(&acrtc->base);
7172 static void dm_update_pflip_irq_state(struct amdgpu_device *adev,
7173 struct amdgpu_crtc *acrtc)
7176 amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id);
7179 * This reads the current state for the IRQ and force reapplies
7180 * the setting to hardware.
7182 amdgpu_irq_update(adev, &adev->pageflip_irq, irq_type);
7186 is_scaling_state_different(const struct dm_connector_state *dm_state,
7187 const struct dm_connector_state *old_dm_state)
7189 if (dm_state->scaling != old_dm_state->scaling)
7191 if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
7192 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
7194 } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
7195 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
7197 } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
7198 dm_state->underscan_vborder != old_dm_state->underscan_vborder)
7203 #ifdef CONFIG_DRM_AMD_DC_HDCP
7204 static bool is_content_protection_different(struct drm_connector_state *state,
7205 const struct drm_connector_state *old_state,
7206 const struct drm_connector *connector, struct hdcp_workqueue *hdcp_w)
7208 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
7209 struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
7211 /* Handle: Type0/1 change */
7212 if (old_state->hdcp_content_type != state->hdcp_content_type &&
7213 state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
7214 state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7218 /* CP is being re enabled, ignore this
7220 * Handles: ENABLED -> DESIRED
7222 if (old_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED &&
7223 state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7224 state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED;
7228 /* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED
7230 * Handles: UNDESIRED -> ENABLED
7232 if (old_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED &&
7233 state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
7234 state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7236 /* Stream removed and re-enabled
7238 * Can sometimes overlap with the HPD case,
7239 * thus set update_hdcp to false to avoid
7240 * setting HDCP multiple times.
7242 * Handles: DESIRED -> DESIRED (Special case)
7244 if (!(old_state->crtc && old_state->crtc->enabled) &&
7245 state->crtc && state->crtc->enabled &&
7246 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7247 dm_con_state->update_hdcp = false;
7251 /* Hot-plug, headless s3, dpms
7253 * Only start HDCP if the display is connected/enabled.
7254 * update_hdcp flag will be set to false until the next
7257 * Handles: DESIRED -> DESIRED (Special case)
7259 if (dm_con_state->update_hdcp && state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED &&
7260 connector->dpms == DRM_MODE_DPMS_ON && aconnector->dc_sink != NULL) {
7261 dm_con_state->update_hdcp = false;
7266 * Handles: UNDESIRED -> UNDESIRED
7267 * DESIRED -> DESIRED
7268 * ENABLED -> ENABLED
7270 if (old_state->content_protection == state->content_protection)
7274 * Handles: UNDESIRED -> DESIRED
7275 * DESIRED -> UNDESIRED
7276 * ENABLED -> UNDESIRED
7278 if (state->content_protection != DRM_MODE_CONTENT_PROTECTION_ENABLED)
7282 * Handles: DESIRED -> ENABLED
7288 static void remove_stream(struct amdgpu_device *adev,
7289 struct amdgpu_crtc *acrtc,
7290 struct dc_stream_state *stream)
7292 /* this is the update mode case */
7294 acrtc->otg_inst = -1;
7295 acrtc->enabled = false;
7298 static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
7301 assert_spin_locked(&acrtc->base.dev->event_lock);
7302 WARN_ON(acrtc->event);
7304 acrtc->event = acrtc->base.state->event;
7306 /* Set the flip status */
7307 acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
7309 /* Mark this event as consumed */
7310 acrtc->base.state->event = NULL;
7312 DC_LOG_PFLIP("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
7316 static void update_freesync_state_on_stream(
7317 struct amdgpu_display_manager *dm,
7318 struct dm_crtc_state *new_crtc_state,
7319 struct dc_stream_state *new_stream,
7320 struct dc_plane_state *surface,
7321 u32 flip_timestamp_in_us)
7323 struct mod_vrr_params vrr_params;
7324 struct dc_info_packet vrr_infopacket = {0};
7325 struct amdgpu_device *adev = dm->adev;
7326 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
7327 unsigned long flags;
7328 bool pack_sdp_v1_3 = false;
7334 * TODO: Determine why min/max totals and vrefresh can be 0 here.
7335 * For now it's sufficient to just guard against these conditions.
7338 if (!new_stream->timing.h_total || !new_stream->timing.v_total)
7341 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
7342 vrr_params = acrtc->dm_irq_params.vrr_params;
7345 mod_freesync_handle_preflip(
7346 dm->freesync_module,
7349 flip_timestamp_in_us,
7352 if (adev->family < AMDGPU_FAMILY_AI &&
7353 amdgpu_dm_vrr_active(new_crtc_state)) {
7354 mod_freesync_handle_v_update(dm->freesync_module,
7355 new_stream, &vrr_params);
7357 /* Need to call this before the frame ends. */
7358 dc_stream_adjust_vmin_vmax(dm->dc,
7359 new_crtc_state->stream,
7360 &vrr_params.adjust);
7364 mod_freesync_build_vrr_infopacket(
7365 dm->freesync_module,
7369 TRANSFER_FUNC_UNKNOWN,
7373 new_crtc_state->freesync_timing_changed |=
7374 (memcmp(&acrtc->dm_irq_params.vrr_params.adjust,
7376 sizeof(vrr_params.adjust)) != 0);
7378 new_crtc_state->freesync_vrr_info_changed |=
7379 (memcmp(&new_crtc_state->vrr_infopacket,
7381 sizeof(vrr_infopacket)) != 0);
7383 acrtc->dm_irq_params.vrr_params = vrr_params;
7384 new_crtc_state->vrr_infopacket = vrr_infopacket;
7386 new_stream->adjust = acrtc->dm_irq_params.vrr_params.adjust;
7387 new_stream->vrr_infopacket = vrr_infopacket;
7389 if (new_crtc_state->freesync_vrr_info_changed)
7390 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d",
7391 new_crtc_state->base.crtc->base.id,
7392 (int)new_crtc_state->base.vrr_enabled,
7393 (int)vrr_params.state);
7395 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
7398 static void update_stream_irq_parameters(
7399 struct amdgpu_display_manager *dm,
7400 struct dm_crtc_state *new_crtc_state)
7402 struct dc_stream_state *new_stream = new_crtc_state->stream;
7403 struct mod_vrr_params vrr_params;
7404 struct mod_freesync_config config = new_crtc_state->freesync_config;
7405 struct amdgpu_device *adev = dm->adev;
7406 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
7407 unsigned long flags;
7413 * TODO: Determine why min/max totals and vrefresh can be 0 here.
7414 * For now it's sufficient to just guard against these conditions.
7416 if (!new_stream->timing.h_total || !new_stream->timing.v_total)
7419 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
7420 vrr_params = acrtc->dm_irq_params.vrr_params;
7422 if (new_crtc_state->vrr_supported &&
7423 config.min_refresh_in_uhz &&
7424 config.max_refresh_in_uhz) {
7426 * if freesync compatible mode was set, config.state will be set
7429 if (config.state == VRR_STATE_ACTIVE_FIXED && config.fixed_refresh_in_uhz &&
7430 (!drm_atomic_crtc_needs_modeset(&new_crtc_state->base) ||
7431 new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)) {
7432 vrr_params.max_refresh_in_uhz = config.max_refresh_in_uhz;
7433 vrr_params.min_refresh_in_uhz = config.min_refresh_in_uhz;
7434 vrr_params.fixed_refresh_in_uhz = config.fixed_refresh_in_uhz;
7435 vrr_params.state = VRR_STATE_ACTIVE_FIXED;
7437 config.state = new_crtc_state->base.vrr_enabled ?
7438 VRR_STATE_ACTIVE_VARIABLE :
7442 config.state = VRR_STATE_UNSUPPORTED;
7445 mod_freesync_build_vrr_params(dm->freesync_module,
7447 &config, &vrr_params);
7449 new_crtc_state->freesync_timing_changed |=
7450 (memcmp(&acrtc->dm_irq_params.vrr_params.adjust,
7451 &vrr_params.adjust, sizeof(vrr_params.adjust)) != 0);
7453 new_crtc_state->freesync_config = config;
7454 /* Copy state for access from DM IRQ handler */
7455 acrtc->dm_irq_params.freesync_config = config;
7456 acrtc->dm_irq_params.active_planes = new_crtc_state->active_planes;
7457 acrtc->dm_irq_params.vrr_params = vrr_params;
7458 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
7461 static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state,
7462 struct dm_crtc_state *new_state)
7464 bool old_vrr_active = amdgpu_dm_vrr_active(old_state);
7465 bool new_vrr_active = amdgpu_dm_vrr_active(new_state);
7467 if (!old_vrr_active && new_vrr_active) {
7468 /* Transition VRR inactive -> active:
7469 * While VRR is active, we must not disable vblank irq, as a
7470 * reenable after disable would compute bogus vblank/pflip
7471 * timestamps if it likely happened inside display front-porch.
7473 * We also need vupdate irq for the actual core vblank handling
7476 dm_set_vupdate_irq(new_state->base.crtc, true);
7477 drm_crtc_vblank_get(new_state->base.crtc);
7478 DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n",
7479 __func__, new_state->base.crtc->base.id);
7480 } else if (old_vrr_active && !new_vrr_active) {
7481 /* Transition VRR active -> inactive:
7482 * Allow vblank irq disable again for fixed refresh rate.
7484 dm_set_vupdate_irq(new_state->base.crtc, false);
7485 drm_crtc_vblank_put(new_state->base.crtc);
7486 DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n",
7487 __func__, new_state->base.crtc->base.id);
7491 static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state)
7493 struct drm_plane *plane;
7494 struct drm_plane_state *old_plane_state;
7498 * TODO: Make this per-stream so we don't issue redundant updates for
7499 * commits with multiple streams.
7501 for_each_old_plane_in_state(state, plane, old_plane_state, i)
7502 if (plane->type == DRM_PLANE_TYPE_CURSOR)
7503 handle_cursor_update(plane, old_plane_state);
7506 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
7507 struct dc_state *dc_state,
7508 struct drm_device *dev,
7509 struct amdgpu_display_manager *dm,
7510 struct drm_crtc *pcrtc,
7511 bool wait_for_vblank)
7514 uint64_t timestamp_ns;
7515 struct drm_plane *plane;
7516 struct drm_plane_state *old_plane_state, *new_plane_state;
7517 struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
7518 struct drm_crtc_state *new_pcrtc_state =
7519 drm_atomic_get_new_crtc_state(state, pcrtc);
7520 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
7521 struct dm_crtc_state *dm_old_crtc_state =
7522 to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
7523 int planes_count = 0, vpos, hpos;
7524 unsigned long flags;
7525 uint32_t target_vblank, last_flip_vblank;
7526 bool vrr_active = amdgpu_dm_vrr_active(acrtc_state);
7527 bool cursor_update = false;
7528 bool pflip_present = false;
7530 struct dc_surface_update surface_updates[MAX_SURFACES];
7531 struct dc_plane_info plane_infos[MAX_SURFACES];
7532 struct dc_scaling_info scaling_infos[MAX_SURFACES];
7533 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
7534 struct dc_stream_update stream_update;
7537 bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
7540 dm_error("Failed to allocate update bundle\n");
7545 * Disable the cursor first if we're disabling all the planes.
7546 * It'll remain on the screen after the planes are re-enabled
7549 if (acrtc_state->active_planes == 0)
7550 amdgpu_dm_commit_cursors(state);
7552 /* update planes when needed */
7553 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
7554 struct drm_crtc *crtc = new_plane_state->crtc;
7555 struct drm_crtc_state *new_crtc_state;
7556 struct drm_framebuffer *fb = new_plane_state->fb;
7557 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)fb;
7558 bool plane_needs_flip;
7559 struct dc_plane_state *dc_plane;
7560 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
7562 /* Cursor plane is handled after stream updates */
7563 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
7564 if ((fb && crtc == pcrtc) ||
7565 (old_plane_state->fb && old_plane_state->crtc == pcrtc))
7566 cursor_update = true;
7571 if (!fb || !crtc || pcrtc != crtc)
7574 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
7575 if (!new_crtc_state->active)
7578 dc_plane = dm_new_plane_state->dc_state;
7580 bundle->surface_updates[planes_count].surface = dc_plane;
7581 if (new_pcrtc_state->color_mgmt_changed) {
7582 bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction;
7583 bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func;
7584 bundle->surface_updates[planes_count].gamut_remap_matrix = &dc_plane->gamut_remap_matrix;
7587 fill_dc_scaling_info(dm->adev, new_plane_state,
7588 &bundle->scaling_infos[planes_count]);
7590 bundle->surface_updates[planes_count].scaling_info =
7591 &bundle->scaling_infos[planes_count];
7593 plane_needs_flip = old_plane_state->fb && new_plane_state->fb;
7595 pflip_present = pflip_present || plane_needs_flip;
7597 if (!plane_needs_flip) {
7602 fill_dc_plane_info_and_addr(
7603 dm->adev, new_plane_state,
7605 &bundle->plane_infos[planes_count],
7606 &bundle->flip_addrs[planes_count].address,
7607 afb->tmz_surface, false);
7609 drm_dbg_state(state->dev, "plane: id=%d dcc_en=%d\n",
7610 new_plane_state->plane->index,
7611 bundle->plane_infos[planes_count].dcc.enable);
7613 bundle->surface_updates[planes_count].plane_info =
7614 &bundle->plane_infos[planes_count];
7616 fill_dc_dirty_rects(plane, old_plane_state, new_plane_state,
7618 &bundle->flip_addrs[planes_count]);
7621 * Only allow immediate flips for fast updates that don't
7622 * change FB pitch, DCC state, rotation or mirroing.
7624 bundle->flip_addrs[planes_count].flip_immediate =
7625 crtc->state->async_flip &&
7626 acrtc_state->update_type == UPDATE_TYPE_FAST;
7628 timestamp_ns = ktime_get_ns();
7629 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000);
7630 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count];
7631 bundle->surface_updates[planes_count].surface = dc_plane;
7633 if (!bundle->surface_updates[planes_count].surface) {
7634 DRM_ERROR("No surface for CRTC: id=%d\n",
7635 acrtc_attach->crtc_id);
7639 if (plane == pcrtc->primary)
7640 update_freesync_state_on_stream(
7643 acrtc_state->stream,
7645 bundle->flip_addrs[planes_count].flip_timestamp_in_us);
7647 drm_dbg_state(state->dev, "%s Flipping to hi: 0x%x, low: 0x%x\n",
7649 bundle->flip_addrs[planes_count].address.grph.addr.high_part,
7650 bundle->flip_addrs[planes_count].address.grph.addr.low_part);
7656 if (pflip_present) {
7658 /* Use old throttling in non-vrr fixed refresh rate mode
7659 * to keep flip scheduling based on target vblank counts
7660 * working in a backwards compatible way, e.g., for
7661 * clients using the GLX_OML_sync_control extension or
7662 * DRI3/Present extension with defined target_msc.
7664 last_flip_vblank = amdgpu_get_vblank_counter_kms(pcrtc);
7667 /* For variable refresh rate mode only:
7668 * Get vblank of last completed flip to avoid > 1 vrr
7669 * flips per video frame by use of throttling, but allow
7670 * flip programming anywhere in the possibly large
7671 * variable vrr vblank interval for fine-grained flip
7672 * timing control and more opportunity to avoid stutter
7673 * on late submission of flips.
7675 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
7676 last_flip_vblank = acrtc_attach->dm_irq_params.last_flip_vblank;
7677 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
7680 target_vblank = last_flip_vblank + wait_for_vblank;
7683 * Wait until we're out of the vertical blank period before the one
7684 * targeted by the flip
7686 while ((acrtc_attach->enabled &&
7687 (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id,
7688 0, &vpos, &hpos, NULL,
7689 NULL, &pcrtc->hwmode)
7690 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
7691 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
7692 (int)(target_vblank -
7693 amdgpu_get_vblank_counter_kms(pcrtc)) > 0)) {
7694 usleep_range(1000, 1100);
7698 * Prepare the flip event for the pageflip interrupt to handle.
7700 * This only works in the case where we've already turned on the
7701 * appropriate hardware blocks (eg. HUBP) so in the transition case
7702 * from 0 -> n planes we have to skip a hardware generated event
7703 * and rely on sending it from software.
7705 if (acrtc_attach->base.state->event &&
7706 acrtc_state->active_planes > 0) {
7707 drm_crtc_vblank_get(pcrtc);
7709 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
7711 WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE);
7712 prepare_flip_isr(acrtc_attach);
7714 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
7717 if (acrtc_state->stream) {
7718 if (acrtc_state->freesync_vrr_info_changed)
7719 bundle->stream_update.vrr_infopacket =
7720 &acrtc_state->stream->vrr_infopacket;
7722 } else if (cursor_update && acrtc_state->active_planes > 0 &&
7723 acrtc_attach->base.state->event) {
7724 drm_crtc_vblank_get(pcrtc);
7726 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
7728 acrtc_attach->event = acrtc_attach->base.state->event;
7729 acrtc_attach->base.state->event = NULL;
7731 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
7734 /* Update the planes if changed or disable if we don't have any. */
7735 if ((planes_count || acrtc_state->active_planes == 0) &&
7736 acrtc_state->stream) {
7738 * If PSR or idle optimizations are enabled then flush out
7739 * any pending work before hardware programming.
7741 if (dm->vblank_control_workqueue)
7742 flush_workqueue(dm->vblank_control_workqueue);
7744 bundle->stream_update.stream = acrtc_state->stream;
7745 if (new_pcrtc_state->mode_changed) {
7746 bundle->stream_update.src = acrtc_state->stream->src;
7747 bundle->stream_update.dst = acrtc_state->stream->dst;
7750 if (new_pcrtc_state->color_mgmt_changed) {
7752 * TODO: This isn't fully correct since we've actually
7753 * already modified the stream in place.
7755 bundle->stream_update.gamut_remap =
7756 &acrtc_state->stream->gamut_remap_matrix;
7757 bundle->stream_update.output_csc_transform =
7758 &acrtc_state->stream->csc_color_matrix;
7759 bundle->stream_update.out_transfer_func =
7760 acrtc_state->stream->out_transfer_func;
7763 acrtc_state->stream->abm_level = acrtc_state->abm_level;
7764 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level)
7765 bundle->stream_update.abm_level = &acrtc_state->abm_level;
7768 * If FreeSync state on the stream has changed then we need to
7769 * re-adjust the min/max bounds now that DC doesn't handle this
7770 * as part of commit.
7772 if (is_dc_timing_adjust_needed(dm_old_crtc_state, acrtc_state)) {
7773 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
7774 dc_stream_adjust_vmin_vmax(
7775 dm->dc, acrtc_state->stream,
7776 &acrtc_attach->dm_irq_params.vrr_params.adjust);
7777 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
7779 mutex_lock(&dm->dc_lock);
7780 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
7781 acrtc_state->stream->link->psr_settings.psr_allow_active)
7782 amdgpu_dm_psr_disable(acrtc_state->stream);
7784 dc_commit_updates_for_stream(dm->dc,
7785 bundle->surface_updates,
7787 acrtc_state->stream,
7788 &bundle->stream_update,
7792 * Enable or disable the interrupts on the backend.
7794 * Most pipes are put into power gating when unused.
7796 * When power gating is enabled on a pipe we lose the
7797 * interrupt enablement state when power gating is disabled.
7799 * So we need to update the IRQ control state in hardware
7800 * whenever the pipe turns on (since it could be previously
7801 * power gated) or off (since some pipes can't be power gated
7804 if (dm_old_crtc_state->active_planes != acrtc_state->active_planes)
7805 dm_update_pflip_irq_state(drm_to_adev(dev),
7808 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
7809 acrtc_state->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED &&
7810 !acrtc_state->stream->link->psr_settings.psr_feature_enabled)
7811 amdgpu_dm_link_setup_psr(acrtc_state->stream);
7813 /* Decrement skip count when PSR is enabled and we're doing fast updates. */
7814 if (acrtc_state->update_type == UPDATE_TYPE_FAST &&
7815 acrtc_state->stream->link->psr_settings.psr_feature_enabled) {
7816 struct amdgpu_dm_connector *aconn =
7817 (struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context;
7819 if (aconn->psr_skip_count > 0)
7820 aconn->psr_skip_count--;
7822 /* Allow PSR when skip count is 0. */
7823 acrtc_attach->dm_irq_params.allow_psr_entry = !aconn->psr_skip_count;
7826 * If sink supports PSR SU, there is no need to rely on
7827 * a vblank event disable request to enable PSR. PSR SU
7828 * can be enabled immediately once OS demonstrates an
7829 * adequate number of fast atomic commits to notify KMD
7830 * of update events. See `vblank_control_worker()`.
7832 if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
7833 acrtc_attach->dm_irq_params.allow_psr_entry &&
7834 !acrtc_state->stream->link->psr_settings.psr_allow_active)
7835 amdgpu_dm_psr_enable(acrtc_state->stream);
7837 acrtc_attach->dm_irq_params.allow_psr_entry = false;
7840 mutex_unlock(&dm->dc_lock);
7844 * Update cursor state *after* programming all the planes.
7845 * This avoids redundant programming in the case where we're going
7846 * to be disabling a single plane - those pipes are being disabled.
7848 if (acrtc_state->active_planes)
7849 amdgpu_dm_commit_cursors(state);
7855 static void amdgpu_dm_commit_audio(struct drm_device *dev,
7856 struct drm_atomic_state *state)
7858 struct amdgpu_device *adev = drm_to_adev(dev);
7859 struct amdgpu_dm_connector *aconnector;
7860 struct drm_connector *connector;
7861 struct drm_connector_state *old_con_state, *new_con_state;
7862 struct drm_crtc_state *new_crtc_state;
7863 struct dm_crtc_state *new_dm_crtc_state;
7864 const struct dc_stream_status *status;
7867 /* Notify device removals. */
7868 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
7869 if (old_con_state->crtc != new_con_state->crtc) {
7870 /* CRTC changes require notification. */
7874 if (!new_con_state->crtc)
7877 new_crtc_state = drm_atomic_get_new_crtc_state(
7878 state, new_con_state->crtc);
7880 if (!new_crtc_state)
7883 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
7887 aconnector = to_amdgpu_dm_connector(connector);
7889 mutex_lock(&adev->dm.audio_lock);
7890 inst = aconnector->audio_inst;
7891 aconnector->audio_inst = -1;
7892 mutex_unlock(&adev->dm.audio_lock);
7894 amdgpu_dm_audio_eld_notify(adev, inst);
7897 /* Notify audio device additions. */
7898 for_each_new_connector_in_state(state, connector, new_con_state, i) {
7899 if (!new_con_state->crtc)
7902 new_crtc_state = drm_atomic_get_new_crtc_state(
7903 state, new_con_state->crtc);
7905 if (!new_crtc_state)
7908 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
7911 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
7912 if (!new_dm_crtc_state->stream)
7915 status = dc_stream_get_status(new_dm_crtc_state->stream);
7919 aconnector = to_amdgpu_dm_connector(connector);
7921 mutex_lock(&adev->dm.audio_lock);
7922 inst = status->audio_inst;
7923 aconnector->audio_inst = inst;
7924 mutex_unlock(&adev->dm.audio_lock);
7926 amdgpu_dm_audio_eld_notify(adev, inst);
7931 * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
7932 * @crtc_state: the DRM CRTC state
7933 * @stream_state: the DC stream state.
7935 * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
7936 * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
7938 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
7939 struct dc_stream_state *stream_state)
7941 stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state);
7945 * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation.
7946 * @state: The atomic state to commit
7948 * This will tell DC to commit the constructed DC state from atomic_check,
7949 * programming the hardware. Any failures here implies a hardware failure, since
7950 * atomic check should have filtered anything non-kosher.
7952 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
7954 struct drm_device *dev = state->dev;
7955 struct amdgpu_device *adev = drm_to_adev(dev);
7956 struct amdgpu_display_manager *dm = &adev->dm;
7957 struct dm_atomic_state *dm_state;
7958 struct dc_state *dc_state = NULL, *dc_state_temp = NULL;
7960 struct drm_crtc *crtc;
7961 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
7962 unsigned long flags;
7963 bool wait_for_vblank = true;
7964 struct drm_connector *connector;
7965 struct drm_connector_state *old_con_state, *new_con_state;
7966 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
7967 int crtc_disable_count = 0;
7968 bool mode_set_reset_required = false;
7971 trace_amdgpu_dm_atomic_commit_tail_begin(state);
7973 r = drm_atomic_helper_wait_for_fences(dev, state, false);
7975 DRM_ERROR("Waiting for fences timed out!");
7977 drm_atomic_helper_update_legacy_modeset_state(dev, state);
7978 drm_dp_mst_atomic_wait_for_dependencies(state);
7980 dm_state = dm_atomic_get_new_state(state);
7981 if (dm_state && dm_state->context) {
7982 dc_state = dm_state->context;
7984 /* No state changes, retain current state. */
7985 dc_state_temp = dc_create_state(dm->dc);
7986 ASSERT(dc_state_temp);
7987 dc_state = dc_state_temp;
7988 dc_resource_state_copy_construct_current(dm->dc, dc_state);
7991 for_each_oldnew_crtc_in_state (state, crtc, old_crtc_state,
7992 new_crtc_state, i) {
7993 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
7995 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
7997 if (old_crtc_state->active &&
7998 (!new_crtc_state->active ||
7999 drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8000 manage_dm_interrupts(adev, acrtc, false);
8001 dc_stream_release(dm_old_crtc_state->stream);
8005 drm_atomic_helper_calc_timestamping_constants(state);
8007 /* update changed items */
8008 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
8009 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8011 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8012 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8014 drm_dbg_state(state->dev,
8015 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
8016 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
8017 "connectors_changed:%d\n",
8019 new_crtc_state->enable,
8020 new_crtc_state->active,
8021 new_crtc_state->planes_changed,
8022 new_crtc_state->mode_changed,
8023 new_crtc_state->active_changed,
8024 new_crtc_state->connectors_changed);
8026 /* Disable cursor if disabling crtc */
8027 if (old_crtc_state->active && !new_crtc_state->active) {
8028 struct dc_cursor_position position;
8030 memset(&position, 0, sizeof(position));
8031 mutex_lock(&dm->dc_lock);
8032 dc_stream_set_cursor_position(dm_old_crtc_state->stream, &position);
8033 mutex_unlock(&dm->dc_lock);
8036 /* Copy all transient state flags into dc state */
8037 if (dm_new_crtc_state->stream) {
8038 amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
8039 dm_new_crtc_state->stream);
8042 /* handles headless hotplug case, updating new_state and
8043 * aconnector as needed
8046 if (modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
8048 DRM_DEBUG_ATOMIC("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
8050 if (!dm_new_crtc_state->stream) {
8052 * this could happen because of issues with
8053 * userspace notifications delivery.
8054 * In this case userspace tries to set mode on
8055 * display which is disconnected in fact.
8056 * dc_sink is NULL in this case on aconnector.
8057 * We expect reset mode will come soon.
8059 * This can also happen when unplug is done
8060 * during resume sequence ended
8062 * In this case, we want to pretend we still
8063 * have a sink to keep the pipe running so that
8064 * hw state is consistent with the sw state
8066 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
8067 __func__, acrtc->base.base.id);
8071 if (dm_old_crtc_state->stream)
8072 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
8074 pm_runtime_get_noresume(dev->dev);
8076 acrtc->enabled = true;
8077 acrtc->hw_mode = new_crtc_state->mode;
8078 crtc->hwmode = new_crtc_state->mode;
8079 mode_set_reset_required = true;
8080 } else if (modereset_required(new_crtc_state)) {
8081 DRM_DEBUG_ATOMIC("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
8082 /* i.e. reset mode */
8083 if (dm_old_crtc_state->stream)
8084 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
8086 mode_set_reset_required = true;
8088 } /* for_each_crtc_in_state() */
8091 /* if there mode set or reset, disable eDP PSR */
8092 if (mode_set_reset_required) {
8093 if (dm->vblank_control_workqueue)
8094 flush_workqueue(dm->vblank_control_workqueue);
8096 amdgpu_dm_psr_disable_all(dm);
8099 dm_enable_per_frame_crtc_master_sync(dc_state);
8100 mutex_lock(&dm->dc_lock);
8101 WARN_ON(!dc_commit_state(dm->dc, dc_state));
8103 /* Allow idle optimization when vblank count is 0 for display off */
8104 if (dm->active_vblank_irq_count == 0)
8105 dc_allow_idle_optimizations(dm->dc, true);
8106 mutex_unlock(&dm->dc_lock);
8109 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
8110 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8112 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8114 if (dm_new_crtc_state->stream != NULL) {
8115 const struct dc_stream_status *status =
8116 dc_stream_get_status(dm_new_crtc_state->stream);
8119 status = dc_stream_get_status_from_state(dc_state,
8120 dm_new_crtc_state->stream);
8122 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc);
8124 acrtc->otg_inst = status->primary_otg_inst;
8127 #ifdef CONFIG_DRM_AMD_DC_HDCP
8128 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8129 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8130 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8131 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8133 new_crtc_state = NULL;
8136 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8138 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8140 if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL &&
8141 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) {
8142 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
8143 new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
8144 dm_new_con_state->update_hdcp = true;
8148 if (is_content_protection_different(new_con_state, old_con_state, connector, adev->dm.hdcp_workqueue))
8149 hdcp_update_display(
8150 adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector,
8151 new_con_state->hdcp_content_type,
8152 new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED);
8156 /* Handle connector state changes */
8157 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8158 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8159 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
8160 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8161 struct dc_surface_update dummy_updates[MAX_SURFACES];
8162 struct dc_stream_update stream_update;
8163 struct dc_info_packet hdr_packet;
8164 struct dc_stream_status *status = NULL;
8165 bool abm_changed, hdr_changed, scaling_changed;
8167 memset(&dummy_updates, 0, sizeof(dummy_updates));
8168 memset(&stream_update, 0, sizeof(stream_update));
8171 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8172 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8175 /* Skip any modesets/resets */
8176 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
8179 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8180 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8182 scaling_changed = is_scaling_state_different(dm_new_con_state,
8185 abm_changed = dm_new_crtc_state->abm_level !=
8186 dm_old_crtc_state->abm_level;
8189 !drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state);
8191 if (!scaling_changed && !abm_changed && !hdr_changed)
8194 stream_update.stream = dm_new_crtc_state->stream;
8195 if (scaling_changed) {
8196 update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
8197 dm_new_con_state, dm_new_crtc_state->stream);
8199 stream_update.src = dm_new_crtc_state->stream->src;
8200 stream_update.dst = dm_new_crtc_state->stream->dst;
8204 dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level;
8206 stream_update.abm_level = &dm_new_crtc_state->abm_level;
8210 fill_hdr_info_packet(new_con_state, &hdr_packet);
8211 stream_update.hdr_static_metadata = &hdr_packet;
8214 status = dc_stream_get_status(dm_new_crtc_state->stream);
8216 if (WARN_ON(!status))
8219 WARN_ON(!status->plane_count);
8222 * TODO: DC refuses to perform stream updates without a dc_surface_update.
8223 * Here we create an empty update on each plane.
8224 * To fix this, DC should permit updating only stream properties.
8226 for (j = 0; j < status->plane_count; j++)
8227 dummy_updates[j].surface = status->plane_states[0];
8230 mutex_lock(&dm->dc_lock);
8231 dc_commit_updates_for_stream(dm->dc,
8233 status->plane_count,
8234 dm_new_crtc_state->stream,
8237 mutex_unlock(&dm->dc_lock);
8240 /* Count number of newly disabled CRTCs for dropping PM refs later. */
8241 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
8242 new_crtc_state, i) {
8243 if (old_crtc_state->active && !new_crtc_state->active)
8244 crtc_disable_count++;
8246 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8247 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8249 /* For freesync config update on crtc state and params for irq */
8250 update_stream_irq_parameters(dm, dm_new_crtc_state);
8252 /* Handle vrr on->off / off->on transitions */
8253 amdgpu_dm_handle_vrr_transition(dm_old_crtc_state,
8258 * Enable interrupts for CRTCs that are newly enabled or went through
8259 * a modeset. It was intentionally deferred until after the front end
8260 * state was modified to wait until the OTG was on and so the IRQ
8261 * handlers didn't access stale or invalid state.
8263 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
8264 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8265 #ifdef CONFIG_DEBUG_FS
8266 bool configure_crc = false;
8267 enum amdgpu_dm_pipe_crc_source cur_crc_src;
8268 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
8269 struct crc_rd_work *crc_rd_wrk = dm->crc_rd_wrk;
8271 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8272 cur_crc_src = acrtc->dm_irq_params.crc_src;
8273 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8275 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8277 if (new_crtc_state->active &&
8278 (!old_crtc_state->active ||
8279 drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8280 dc_stream_retain(dm_new_crtc_state->stream);
8281 acrtc->dm_irq_params.stream = dm_new_crtc_state->stream;
8282 manage_dm_interrupts(adev, acrtc, true);
8284 #ifdef CONFIG_DEBUG_FS
8286 * Frontend may have changed so reapply the CRC capture
8287 * settings for the stream.
8289 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8291 if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) {
8292 configure_crc = true;
8293 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
8294 if (amdgpu_dm_crc_window_is_activated(crtc)) {
8295 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8296 acrtc->dm_irq_params.crc_window.update_win = true;
8297 acrtc->dm_irq_params.crc_window.skip_frame_cnt = 2;
8298 spin_lock_irq(&crc_rd_wrk->crc_rd_work_lock);
8299 crc_rd_wrk->crtc = crtc;
8300 spin_unlock_irq(&crc_rd_wrk->crc_rd_work_lock);
8301 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8307 if (amdgpu_dm_crtc_configure_crc_source(
8308 crtc, dm_new_crtc_state, cur_crc_src))
8309 DRM_DEBUG_DRIVER("Failed to configure crc source");
8314 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j)
8315 if (new_crtc_state->async_flip)
8316 wait_for_vblank = false;
8318 /* update planes when needed per crtc*/
8319 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
8320 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8322 if (dm_new_crtc_state->stream)
8323 amdgpu_dm_commit_planes(state, dc_state, dev,
8324 dm, crtc, wait_for_vblank);
8327 /* Update audio instances for each connector. */
8328 amdgpu_dm_commit_audio(dev, state);
8330 /* restore the backlight level */
8331 for (i = 0; i < dm->num_of_edps; i++) {
8332 if (dm->backlight_dev[i] &&
8333 (dm->actual_brightness[i] != dm->brightness[i]))
8334 amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]);
8338 * send vblank event on all events not handled in flip and
8339 * mark consumed event for drm_atomic_helper_commit_hw_done
8341 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8342 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
8344 if (new_crtc_state->event)
8345 drm_send_event_locked(dev, &new_crtc_state->event->base);
8347 new_crtc_state->event = NULL;
8349 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8351 /* Signal HW programming completion */
8352 drm_atomic_helper_commit_hw_done(state);
8354 if (wait_for_vblank)
8355 drm_atomic_helper_wait_for_flip_done(dev, state);
8357 drm_atomic_helper_cleanup_planes(dev, state);
8359 /* return the stolen vga memory back to VRAM */
8360 if (!adev->mman.keep_stolen_vga_memory)
8361 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
8362 amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
8365 * Finally, drop a runtime PM reference for each newly disabled CRTC,
8366 * so we can put the GPU into runtime suspend if we're not driving any
8369 for (i = 0; i < crtc_disable_count; i++)
8370 pm_runtime_put_autosuspend(dev->dev);
8371 pm_runtime_mark_last_busy(dev->dev);
8374 dc_release_state(dc_state_temp);
8377 static int dm_force_atomic_commit(struct drm_connector *connector)
8380 struct drm_device *ddev = connector->dev;
8381 struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
8382 struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
8383 struct drm_plane *plane = disconnected_acrtc->base.primary;
8384 struct drm_connector_state *conn_state;
8385 struct drm_crtc_state *crtc_state;
8386 struct drm_plane_state *plane_state;
8391 state->acquire_ctx = ddev->mode_config.acquire_ctx;
8393 /* Construct an atomic state to restore previous display setting */
8396 * Attach connectors to drm_atomic_state
8398 conn_state = drm_atomic_get_connector_state(state, connector);
8400 ret = PTR_ERR_OR_ZERO(conn_state);
8404 /* Attach crtc to drm_atomic_state*/
8405 crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
8407 ret = PTR_ERR_OR_ZERO(crtc_state);
8411 /* force a restore */
8412 crtc_state->mode_changed = true;
8414 /* Attach plane to drm_atomic_state */
8415 plane_state = drm_atomic_get_plane_state(state, plane);
8417 ret = PTR_ERR_OR_ZERO(plane_state);
8421 /* Call commit internally with the state we just constructed */
8422 ret = drm_atomic_commit(state);
8425 drm_atomic_state_put(state);
8427 DRM_ERROR("Restoring old state failed with %i\n", ret);
8433 * This function handles all cases when set mode does not come upon hotplug.
8434 * This includes when a display is unplugged then plugged back into the
8435 * same port and when running without usermode desktop manager supprot
8437 void dm_restore_drm_connector_state(struct drm_device *dev,
8438 struct drm_connector *connector)
8440 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8441 struct amdgpu_crtc *disconnected_acrtc;
8442 struct dm_crtc_state *acrtc_state;
8444 if (!aconnector->dc_sink || !connector->state || !connector->encoder)
8447 disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
8448 if (!disconnected_acrtc)
8451 acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
8452 if (!acrtc_state->stream)
8456 * If the previous sink is not released and different from the current,
8457 * we deduce we are in a state where we can not rely on usermode call
8458 * to turn on the display, so we do it here
8460 if (acrtc_state->stream->sink != aconnector->dc_sink)
8461 dm_force_atomic_commit(&aconnector->base);
8465 * Grabs all modesetting locks to serialize against any blocking commits,
8466 * Waits for completion of all non blocking commits.
8468 static int do_aquire_global_lock(struct drm_device *dev,
8469 struct drm_atomic_state *state)
8471 struct drm_crtc *crtc;
8472 struct drm_crtc_commit *commit;
8476 * Adding all modeset locks to aquire_ctx will
8477 * ensure that when the framework release it the
8478 * extra locks we are locking here will get released to
8480 ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
8484 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8485 spin_lock(&crtc->commit_lock);
8486 commit = list_first_entry_or_null(&crtc->commit_list,
8487 struct drm_crtc_commit, commit_entry);
8489 drm_crtc_commit_get(commit);
8490 spin_unlock(&crtc->commit_lock);
8496 * Make sure all pending HW programming completed and
8499 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
8502 ret = wait_for_completion_interruptible_timeout(
8503 &commit->flip_done, 10*HZ);
8506 DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
8507 "timed out\n", crtc->base.id, crtc->name);
8509 drm_crtc_commit_put(commit);
8512 return ret < 0 ? ret : 0;
8515 static void get_freesync_config_for_crtc(
8516 struct dm_crtc_state *new_crtc_state,
8517 struct dm_connector_state *new_con_state)
8519 struct mod_freesync_config config = {0};
8520 struct amdgpu_dm_connector *aconnector =
8521 to_amdgpu_dm_connector(new_con_state->base.connector);
8522 struct drm_display_mode *mode = &new_crtc_state->base.mode;
8523 int vrefresh = drm_mode_vrefresh(mode);
8524 bool fs_vid_mode = false;
8526 new_crtc_state->vrr_supported = new_con_state->freesync_capable &&
8527 vrefresh >= aconnector->min_vfreq &&
8528 vrefresh <= aconnector->max_vfreq;
8530 if (new_crtc_state->vrr_supported) {
8531 new_crtc_state->stream->ignore_msa_timing_param = true;
8532 fs_vid_mode = new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
8534 config.min_refresh_in_uhz = aconnector->min_vfreq * 1000000;
8535 config.max_refresh_in_uhz = aconnector->max_vfreq * 1000000;
8536 config.vsif_supported = true;
8540 config.state = VRR_STATE_ACTIVE_FIXED;
8541 config.fixed_refresh_in_uhz = new_crtc_state->freesync_config.fixed_refresh_in_uhz;
8543 } else if (new_crtc_state->base.vrr_enabled) {
8544 config.state = VRR_STATE_ACTIVE_VARIABLE;
8546 config.state = VRR_STATE_INACTIVE;
8550 new_crtc_state->freesync_config = config;
8553 static void reset_freesync_config_for_crtc(
8554 struct dm_crtc_state *new_crtc_state)
8556 new_crtc_state->vrr_supported = false;
8558 memset(&new_crtc_state->vrr_infopacket, 0,
8559 sizeof(new_crtc_state->vrr_infopacket));
8563 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
8564 struct drm_crtc_state *new_crtc_state)
8566 const struct drm_display_mode *old_mode, *new_mode;
8568 if (!old_crtc_state || !new_crtc_state)
8571 old_mode = &old_crtc_state->mode;
8572 new_mode = &new_crtc_state->mode;
8574 if (old_mode->clock == new_mode->clock &&
8575 old_mode->hdisplay == new_mode->hdisplay &&
8576 old_mode->vdisplay == new_mode->vdisplay &&
8577 old_mode->htotal == new_mode->htotal &&
8578 old_mode->vtotal != new_mode->vtotal &&
8579 old_mode->hsync_start == new_mode->hsync_start &&
8580 old_mode->vsync_start != new_mode->vsync_start &&
8581 old_mode->hsync_end == new_mode->hsync_end &&
8582 old_mode->vsync_end != new_mode->vsync_end &&
8583 old_mode->hskew == new_mode->hskew &&
8584 old_mode->vscan == new_mode->vscan &&
8585 (old_mode->vsync_end - old_mode->vsync_start) ==
8586 (new_mode->vsync_end - new_mode->vsync_start))
8592 static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state) {
8593 uint64_t num, den, res;
8594 struct drm_crtc_state *new_crtc_state = &dm_new_crtc_state->base;
8596 dm_new_crtc_state->freesync_config.state = VRR_STATE_ACTIVE_FIXED;
8598 num = (unsigned long long)new_crtc_state->mode.clock * 1000 * 1000000;
8599 den = (unsigned long long)new_crtc_state->mode.htotal *
8600 (unsigned long long)new_crtc_state->mode.vtotal;
8602 res = div_u64(num, den);
8603 dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = res;
8606 static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
8607 struct drm_atomic_state *state,
8608 struct drm_crtc *crtc,
8609 struct drm_crtc_state *old_crtc_state,
8610 struct drm_crtc_state *new_crtc_state,
8612 bool *lock_and_validation_needed)
8614 struct dm_atomic_state *dm_state = NULL;
8615 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
8616 struct dc_stream_state *new_stream;
8620 * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set
8621 * update changed items
8623 struct amdgpu_crtc *acrtc = NULL;
8624 struct amdgpu_dm_connector *aconnector = NULL;
8625 struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL;
8626 struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL;
8630 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8631 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8632 acrtc = to_amdgpu_crtc(crtc);
8633 aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
8635 /* TODO This hack should go away */
8636 if (aconnector && enable) {
8637 /* Make sure fake sink is created in plug-in scenario */
8638 drm_new_conn_state = drm_atomic_get_new_connector_state(state,
8640 drm_old_conn_state = drm_atomic_get_old_connector_state(state,
8643 if (IS_ERR(drm_new_conn_state)) {
8644 ret = PTR_ERR_OR_ZERO(drm_new_conn_state);
8648 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
8649 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state);
8651 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8654 new_stream = create_validate_stream_for_sink(aconnector,
8655 &new_crtc_state->mode,
8657 dm_old_crtc_state->stream);
8660 * we can have no stream on ACTION_SET if a display
8661 * was disconnected during S3, in this case it is not an
8662 * error, the OS will be updated after detection, and
8663 * will do the right thing on next atomic commit
8667 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
8668 __func__, acrtc->base.base.id);
8674 * TODO: Check VSDB bits to decide whether this should
8675 * be enabled or not.
8677 new_stream->triggered_crtc_reset.enabled =
8678 dm->force_timing_sync;
8680 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
8682 ret = fill_hdr_info_packet(drm_new_conn_state,
8683 &new_stream->hdr_static_metadata);
8688 * If we already removed the old stream from the context
8689 * (and set the new stream to NULL) then we can't reuse
8690 * the old stream even if the stream and scaling are unchanged.
8691 * We'll hit the BUG_ON and black screen.
8693 * TODO: Refactor this function to allow this check to work
8694 * in all conditions.
8696 if (dm_new_crtc_state->stream &&
8697 is_timing_unchanged_for_freesync(new_crtc_state, old_crtc_state))
8700 if (dm_new_crtc_state->stream &&
8701 dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
8702 dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
8703 new_crtc_state->mode_changed = false;
8704 DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
8705 new_crtc_state->mode_changed);
8709 /* mode_changed flag may get updated above, need to check again */
8710 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8713 drm_dbg_state(state->dev,
8714 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
8715 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
8716 "connectors_changed:%d\n",
8718 new_crtc_state->enable,
8719 new_crtc_state->active,
8720 new_crtc_state->planes_changed,
8721 new_crtc_state->mode_changed,
8722 new_crtc_state->active_changed,
8723 new_crtc_state->connectors_changed);
8725 /* Remove stream for any changed/disabled CRTC */
8728 if (!dm_old_crtc_state->stream)
8731 if (dm_new_crtc_state->stream &&
8732 is_timing_unchanged_for_freesync(new_crtc_state,
8734 new_crtc_state->mode_changed = false;
8736 "Mode change not required for front porch change, "
8737 "setting mode_changed to %d",
8738 new_crtc_state->mode_changed);
8740 set_freesync_fixed_config(dm_new_crtc_state);
8743 } else if (aconnector &&
8744 is_freesync_video_mode(&new_crtc_state->mode,
8746 struct drm_display_mode *high_mode;
8748 high_mode = get_highest_refresh_rate_mode(aconnector, false);
8749 if (!drm_mode_equal(&new_crtc_state->mode, high_mode)) {
8750 set_freesync_fixed_config(dm_new_crtc_state);
8754 ret = dm_atomic_get_state(state, &dm_state);
8758 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
8761 /* i.e. reset mode */
8762 if (dc_remove_stream_from_ctx(
8765 dm_old_crtc_state->stream) != DC_OK) {
8770 dc_stream_release(dm_old_crtc_state->stream);
8771 dm_new_crtc_state->stream = NULL;
8773 reset_freesync_config_for_crtc(dm_new_crtc_state);
8775 *lock_and_validation_needed = true;
8777 } else {/* Add stream for any updated/enabled CRTC */
8779 * Quick fix to prevent NULL pointer on new_stream when
8780 * added MST connectors not found in existing crtc_state in the chained mode
8781 * TODO: need to dig out the root cause of that
8786 if (modereset_required(new_crtc_state))
8789 if (modeset_required(new_crtc_state, new_stream,
8790 dm_old_crtc_state->stream)) {
8792 WARN_ON(dm_new_crtc_state->stream);
8794 ret = dm_atomic_get_state(state, &dm_state);
8798 dm_new_crtc_state->stream = new_stream;
8800 dc_stream_retain(new_stream);
8802 DRM_DEBUG_ATOMIC("Enabling DRM crtc: %d\n",
8805 if (dc_add_stream_to_ctx(
8808 dm_new_crtc_state->stream) != DC_OK) {
8813 *lock_and_validation_needed = true;
8818 /* Release extra reference */
8820 dc_stream_release(new_stream);
8823 * We want to do dc stream updates that do not require a
8824 * full modeset below.
8826 if (!(enable && aconnector && new_crtc_state->active))
8829 * Given above conditions, the dc state cannot be NULL because:
8830 * 1. We're in the process of enabling CRTCs (just been added
8831 * to the dc context, or already is on the context)
8832 * 2. Has a valid connector attached, and
8833 * 3. Is currently active and enabled.
8834 * => The dc stream state currently exists.
8836 BUG_ON(dm_new_crtc_state->stream == NULL);
8838 /* Scaling or underscan settings */
8839 if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state) ||
8840 drm_atomic_crtc_needs_modeset(new_crtc_state))
8841 update_stream_scaling_settings(
8842 &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);
8845 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
8848 * Color management settings. We also update color properties
8849 * when a modeset is needed, to ensure it gets reprogrammed.
8851 if (dm_new_crtc_state->base.color_mgmt_changed ||
8852 drm_atomic_crtc_needs_modeset(new_crtc_state)) {
8853 ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state);
8858 /* Update Freesync settings. */
8859 get_freesync_config_for_crtc(dm_new_crtc_state,
8866 dc_stream_release(new_stream);
8870 static bool should_reset_plane(struct drm_atomic_state *state,
8871 struct drm_plane *plane,
8872 struct drm_plane_state *old_plane_state,
8873 struct drm_plane_state *new_plane_state)
8875 struct drm_plane *other;
8876 struct drm_plane_state *old_other_state, *new_other_state;
8877 struct drm_crtc_state *new_crtc_state;
8881 * TODO: Remove this hack once the checks below are sufficient
8882 * enough to determine when we need to reset all the planes on
8885 if (state->allow_modeset)
8888 /* Exit early if we know that we're adding or removing the plane. */
8889 if (old_plane_state->crtc != new_plane_state->crtc)
8892 /* old crtc == new_crtc == NULL, plane not in context. */
8893 if (!new_plane_state->crtc)
8897 drm_atomic_get_new_crtc_state(state, new_plane_state->crtc);
8899 if (!new_crtc_state)
8902 /* CRTC Degamma changes currently require us to recreate planes. */
8903 if (new_crtc_state->color_mgmt_changed)
8906 if (drm_atomic_crtc_needs_modeset(new_crtc_state))
8910 * If there are any new primary or overlay planes being added or
8911 * removed then the z-order can potentially change. To ensure
8912 * correct z-order and pipe acquisition the current DC architecture
8913 * requires us to remove and recreate all existing planes.
8915 * TODO: Come up with a more elegant solution for this.
8917 for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) {
8918 struct amdgpu_framebuffer *old_afb, *new_afb;
8919 if (other->type == DRM_PLANE_TYPE_CURSOR)
8922 if (old_other_state->crtc != new_plane_state->crtc &&
8923 new_other_state->crtc != new_plane_state->crtc)
8926 if (old_other_state->crtc != new_other_state->crtc)
8929 /* Src/dst size and scaling updates. */
8930 if (old_other_state->src_w != new_other_state->src_w ||
8931 old_other_state->src_h != new_other_state->src_h ||
8932 old_other_state->crtc_w != new_other_state->crtc_w ||
8933 old_other_state->crtc_h != new_other_state->crtc_h)
8936 /* Rotation / mirroring updates. */
8937 if (old_other_state->rotation != new_other_state->rotation)
8940 /* Blending updates. */
8941 if (old_other_state->pixel_blend_mode !=
8942 new_other_state->pixel_blend_mode)
8945 /* Alpha updates. */
8946 if (old_other_state->alpha != new_other_state->alpha)
8949 /* Colorspace changes. */
8950 if (old_other_state->color_range != new_other_state->color_range ||
8951 old_other_state->color_encoding != new_other_state->color_encoding)
8954 /* Framebuffer checks fall at the end. */
8955 if (!old_other_state->fb || !new_other_state->fb)
8958 /* Pixel format changes can require bandwidth updates. */
8959 if (old_other_state->fb->format != new_other_state->fb->format)
8962 old_afb = (struct amdgpu_framebuffer *)old_other_state->fb;
8963 new_afb = (struct amdgpu_framebuffer *)new_other_state->fb;
8965 /* Tiling and DCC changes also require bandwidth updates. */
8966 if (old_afb->tiling_flags != new_afb->tiling_flags ||
8967 old_afb->base.modifier != new_afb->base.modifier)
8974 static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc,
8975 struct drm_plane_state *new_plane_state,
8976 struct drm_framebuffer *fb)
8978 struct amdgpu_device *adev = drm_to_adev(new_acrtc->base.dev);
8979 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
8983 if (fb->width > new_acrtc->max_cursor_width ||
8984 fb->height > new_acrtc->max_cursor_height) {
8985 DRM_DEBUG_ATOMIC("Bad cursor FB size %dx%d\n",
8986 new_plane_state->fb->width,
8987 new_plane_state->fb->height);
8990 if (new_plane_state->src_w != fb->width << 16 ||
8991 new_plane_state->src_h != fb->height << 16) {
8992 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
8996 /* Pitch in pixels */
8997 pitch = fb->pitches[0] / fb->format->cpp[0];
8999 if (fb->width != pitch) {
9000 DRM_DEBUG_ATOMIC("Cursor FB width %d doesn't match pitch %d",
9009 /* FB pitch is supported by cursor plane */
9012 DRM_DEBUG_ATOMIC("Bad cursor FB pitch %d px\n", pitch);
9016 /* Core DRM takes care of checking FB modifiers, so we only need to
9017 * check tiling flags when the FB doesn't have a modifier. */
9018 if (!(fb->flags & DRM_MODE_FB_MODIFIERS)) {
9019 if (adev->family < AMDGPU_FAMILY_AI) {
9020 linear = AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_2D_TILED_THIN1 &&
9021 AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 &&
9022 AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE) == 0;
9024 linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0;
9027 DRM_DEBUG_ATOMIC("Cursor FB not linear");
9035 static int dm_update_plane_state(struct dc *dc,
9036 struct drm_atomic_state *state,
9037 struct drm_plane *plane,
9038 struct drm_plane_state *old_plane_state,
9039 struct drm_plane_state *new_plane_state,
9041 bool *lock_and_validation_needed)
9044 struct dm_atomic_state *dm_state = NULL;
9045 struct drm_crtc *new_plane_crtc, *old_plane_crtc;
9046 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
9047 struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
9048 struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
9049 struct amdgpu_crtc *new_acrtc;
9054 new_plane_crtc = new_plane_state->crtc;
9055 old_plane_crtc = old_plane_state->crtc;
9056 dm_new_plane_state = to_dm_plane_state(new_plane_state);
9057 dm_old_plane_state = to_dm_plane_state(old_plane_state);
9059 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
9060 if (!enable || !new_plane_crtc ||
9061 drm_atomic_plane_disabling(plane->state, new_plane_state))
9064 new_acrtc = to_amdgpu_crtc(new_plane_crtc);
9066 if (new_plane_state->src_x != 0 || new_plane_state->src_y != 0) {
9067 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
9071 if (new_plane_state->fb) {
9072 ret = dm_check_cursor_fb(new_acrtc, new_plane_state,
9073 new_plane_state->fb);
9081 needs_reset = should_reset_plane(state, plane, old_plane_state,
9084 /* Remove any changed/removed planes */
9089 if (!old_plane_crtc)
9092 old_crtc_state = drm_atomic_get_old_crtc_state(
9093 state, old_plane_crtc);
9094 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9096 if (!dm_old_crtc_state->stream)
9099 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",
9100 plane->base.id, old_plane_crtc->base.id);
9102 ret = dm_atomic_get_state(state, &dm_state);
9106 if (!dc_remove_plane_from_context(
9108 dm_old_crtc_state->stream,
9109 dm_old_plane_state->dc_state,
9110 dm_state->context)) {
9116 dc_plane_state_release(dm_old_plane_state->dc_state);
9117 dm_new_plane_state->dc_state = NULL;
9119 *lock_and_validation_needed = true;
9121 } else { /* Add new planes */
9122 struct dc_plane_state *dc_new_plane_state;
9124 if (drm_atomic_plane_disabling(plane->state, new_plane_state))
9127 if (!new_plane_crtc)
9130 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
9131 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9133 if (!dm_new_crtc_state->stream)
9139 ret = dm_plane_helper_check_state(new_plane_state, new_crtc_state);
9143 WARN_ON(dm_new_plane_state->dc_state);
9145 dc_new_plane_state = dc_create_plane_state(dc);
9146 if (!dc_new_plane_state)
9149 DRM_DEBUG_ATOMIC("Enabling DRM plane: %d on DRM crtc %d\n",
9150 plane->base.id, new_plane_crtc->base.id);
9152 ret = fill_dc_plane_attributes(
9153 drm_to_adev(new_plane_crtc->dev),
9158 dc_plane_state_release(dc_new_plane_state);
9162 ret = dm_atomic_get_state(state, &dm_state);
9164 dc_plane_state_release(dc_new_plane_state);
9169 * Any atomic check errors that occur after this will
9170 * not need a release. The plane state will be attached
9171 * to the stream, and therefore part of the atomic
9172 * state. It'll be released when the atomic state is
9175 if (!dc_add_plane_to_context(
9177 dm_new_crtc_state->stream,
9179 dm_state->context)) {
9181 dc_plane_state_release(dc_new_plane_state);
9185 dm_new_plane_state->dc_state = dc_new_plane_state;
9187 dm_new_crtc_state->mpo_requested |= (plane->type == DRM_PLANE_TYPE_OVERLAY);
9189 /* Tell DC to do a full surface update every time there
9190 * is a plane change. Inefficient, but works for now.
9192 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
9194 *lock_and_validation_needed = true;
9201 static void dm_get_oriented_plane_size(struct drm_plane_state *plane_state,
9202 int *src_w, int *src_h)
9204 switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
9205 case DRM_MODE_ROTATE_90:
9206 case DRM_MODE_ROTATE_270:
9207 *src_w = plane_state->src_h >> 16;
9208 *src_h = plane_state->src_w >> 16;
9210 case DRM_MODE_ROTATE_0:
9211 case DRM_MODE_ROTATE_180:
9213 *src_w = plane_state->src_w >> 16;
9214 *src_h = plane_state->src_h >> 16;
9219 static int dm_check_crtc_cursor(struct drm_atomic_state *state,
9220 struct drm_crtc *crtc,
9221 struct drm_crtc_state *new_crtc_state)
9223 struct drm_plane *cursor = crtc->cursor, *underlying;
9224 struct drm_plane_state *new_cursor_state, *new_underlying_state;
9226 int cursor_scale_w, cursor_scale_h, underlying_scale_w, underlying_scale_h;
9227 int cursor_src_w, cursor_src_h;
9228 int underlying_src_w, underlying_src_h;
9230 /* On DCE and DCN there is no dedicated hardware cursor plane. We get a
9231 * cursor per pipe but it's going to inherit the scaling and
9232 * positioning from the underlying pipe. Check the cursor plane's
9233 * blending properties match the underlying planes'. */
9235 new_cursor_state = drm_atomic_get_new_plane_state(state, cursor);
9236 if (!new_cursor_state || !new_cursor_state->fb) {
9240 dm_get_oriented_plane_size(new_cursor_state, &cursor_src_w, &cursor_src_h);
9241 cursor_scale_w = new_cursor_state->crtc_w * 1000 / cursor_src_w;
9242 cursor_scale_h = new_cursor_state->crtc_h * 1000 / cursor_src_h;
9244 for_each_new_plane_in_state_reverse(state, underlying, new_underlying_state, i) {
9245 /* Narrow down to non-cursor planes on the same CRTC as the cursor */
9246 if (new_underlying_state->crtc != crtc || underlying == crtc->cursor)
9249 /* Ignore disabled planes */
9250 if (!new_underlying_state->fb)
9253 dm_get_oriented_plane_size(new_underlying_state,
9254 &underlying_src_w, &underlying_src_h);
9255 underlying_scale_w = new_underlying_state->crtc_w * 1000 / underlying_src_w;
9256 underlying_scale_h = new_underlying_state->crtc_h * 1000 / underlying_src_h;
9258 if (cursor_scale_w != underlying_scale_w ||
9259 cursor_scale_h != underlying_scale_h) {
9260 drm_dbg_atomic(crtc->dev,
9261 "Cursor [PLANE:%d:%s] scaling doesn't match underlying [PLANE:%d:%s]\n",
9262 cursor->base.id, cursor->name, underlying->base.id, underlying->name);
9266 /* If this plane covers the whole CRTC, no need to check planes underneath */
9267 if (new_underlying_state->crtc_x <= 0 &&
9268 new_underlying_state->crtc_y <= 0 &&
9269 new_underlying_state->crtc_x + new_underlying_state->crtc_w >= new_crtc_state->mode.hdisplay &&
9270 new_underlying_state->crtc_y + new_underlying_state->crtc_h >= new_crtc_state->mode.vdisplay)
9277 #if defined(CONFIG_DRM_AMD_DC_DCN)
9278 static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc)
9280 struct drm_connector *connector;
9281 struct drm_connector_state *conn_state, *old_conn_state;
9282 struct amdgpu_dm_connector *aconnector = NULL;
9284 for_each_oldnew_connector_in_state(state, connector, old_conn_state, conn_state, i) {
9285 if (!conn_state->crtc)
9286 conn_state = old_conn_state;
9288 if (conn_state->crtc != crtc)
9291 aconnector = to_amdgpu_dm_connector(connector);
9292 if (!aconnector->port || !aconnector->mst_port)
9301 return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_port->mst_mgr);
9306 * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.
9307 * @dev: The DRM device
9308 * @state: The atomic state to commit
9310 * Validate that the given atomic state is programmable by DC into hardware.
9311 * This involves constructing a &struct dc_state reflecting the new hardware
9312 * state we wish to commit, then querying DC to see if it is programmable. It's
9313 * important not to modify the existing DC state. Otherwise, atomic_check
9314 * may unexpectedly commit hardware changes.
9316 * When validating the DC state, it's important that the right locks are
9317 * acquired. For full updates case which removes/adds/updates streams on one
9318 * CRTC while flipping on another CRTC, acquiring global lock will guarantee
9319 * that any such full update commit will wait for completion of any outstanding
9320 * flip using DRMs synchronization events.
9322 * Note that DM adds the affected connectors for all CRTCs in state, when that
9323 * might not seem necessary. This is because DC stream creation requires the
9324 * DC sink, which is tied to the DRM connector state. Cleaning this up should
9325 * be possible but non-trivial - a possible TODO item.
9327 * Return: -Error code if validation failed.
9329 static int amdgpu_dm_atomic_check(struct drm_device *dev,
9330 struct drm_atomic_state *state)
9332 struct amdgpu_device *adev = drm_to_adev(dev);
9333 struct dm_atomic_state *dm_state = NULL;
9334 struct dc *dc = adev->dm.dc;
9335 struct drm_connector *connector;
9336 struct drm_connector_state *old_con_state, *new_con_state;
9337 struct drm_crtc *crtc;
9338 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
9339 struct drm_plane *plane;
9340 struct drm_plane_state *old_plane_state, *new_plane_state;
9341 enum dc_status status;
9343 bool lock_and_validation_needed = false;
9344 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
9345 #if defined(CONFIG_DRM_AMD_DC_DCN)
9346 struct dsc_mst_fairness_vars vars[MAX_PIPES];
9349 trace_amdgpu_dm_atomic_check_begin(state);
9351 ret = drm_atomic_helper_check_modeset(dev, state);
9353 DRM_DEBUG_DRIVER("drm_atomic_helper_check_modeset() failed\n");
9357 /* Check connector changes */
9358 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
9359 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
9360 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
9362 /* Skip connectors that are disabled or part of modeset already. */
9363 if (!old_con_state->crtc && !new_con_state->crtc)
9366 if (!new_con_state->crtc)
9369 new_crtc_state = drm_atomic_get_crtc_state(state, new_con_state->crtc);
9370 if (IS_ERR(new_crtc_state)) {
9371 DRM_DEBUG_DRIVER("drm_atomic_get_crtc_state() failed\n");
9372 ret = PTR_ERR(new_crtc_state);
9376 if (dm_old_con_state->abm_level !=
9377 dm_new_con_state->abm_level)
9378 new_crtc_state->connectors_changed = true;
9381 #if defined(CONFIG_DRM_AMD_DC_DCN)
9382 if (dc_resource_is_dsc_encoding_supported(dc)) {
9383 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
9384 if (drm_atomic_crtc_needs_modeset(new_crtc_state)) {
9385 ret = add_affected_mst_dsc_crtcs(state, crtc);
9387 DRM_DEBUG_DRIVER("add_affected_mst_dsc_crtcs() failed\n");
9392 if (!pre_validate_dsc(state, &dm_state, vars)) {
9398 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
9399 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9401 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
9402 !new_crtc_state->color_mgmt_changed &&
9403 old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled &&
9404 dm_old_crtc_state->dsc_force_changed == false)
9407 ret = amdgpu_dm_verify_lut_sizes(new_crtc_state);
9409 DRM_DEBUG_DRIVER("amdgpu_dm_verify_lut_sizes() failed\n");
9413 if (!new_crtc_state->enable)
9416 ret = drm_atomic_add_affected_connectors(state, crtc);
9418 DRM_DEBUG_DRIVER("drm_atomic_add_affected_connectors() failed\n");
9422 ret = drm_atomic_add_affected_planes(state, crtc);
9424 DRM_DEBUG_DRIVER("drm_atomic_add_affected_planes() failed\n");
9428 if (dm_old_crtc_state->dsc_force_changed)
9429 new_crtc_state->mode_changed = true;
9433 * Add all primary and overlay planes on the CRTC to the state
9434 * whenever a plane is enabled to maintain correct z-ordering
9435 * and to enable fast surface updates.
9437 drm_for_each_crtc(crtc, dev) {
9438 bool modified = false;
9440 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
9441 if (plane->type == DRM_PLANE_TYPE_CURSOR)
9444 if (new_plane_state->crtc == crtc ||
9445 old_plane_state->crtc == crtc) {
9454 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) {
9455 if (plane->type == DRM_PLANE_TYPE_CURSOR)
9459 drm_atomic_get_plane_state(state, plane);
9461 if (IS_ERR(new_plane_state)) {
9462 ret = PTR_ERR(new_plane_state);
9463 DRM_DEBUG_DRIVER("new_plane_state is BAD\n");
9469 /* Remove exiting planes if they are modified */
9470 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
9471 ret = dm_update_plane_state(dc, state, plane,
9475 &lock_and_validation_needed);
9477 DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n");
9482 /* Disable all crtcs which require disable */
9483 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
9484 ret = dm_update_crtc_state(&adev->dm, state, crtc,
9488 &lock_and_validation_needed);
9490 DRM_DEBUG_DRIVER("DISABLE: dm_update_crtc_state() failed\n");
9495 /* Enable all crtcs which require enable */
9496 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
9497 ret = dm_update_crtc_state(&adev->dm, state, crtc,
9501 &lock_and_validation_needed);
9503 DRM_DEBUG_DRIVER("ENABLE: dm_update_crtc_state() failed\n");
9508 /* Add new/modified planes */
9509 for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
9510 ret = dm_update_plane_state(dc, state, plane,
9514 &lock_and_validation_needed);
9516 DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n");
9521 /* Run this here since we want to validate the streams we created */
9522 ret = drm_atomic_helper_check_planes(dev, state);
9524 DRM_DEBUG_DRIVER("drm_atomic_helper_check_planes() failed\n");
9528 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
9529 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9530 if (dm_new_crtc_state->mpo_requested)
9531 DRM_DEBUG_DRIVER("MPO enablement requested on crtc:[%p]\n", crtc);
9534 /* Check cursor planes scaling */
9535 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
9536 ret = dm_check_crtc_cursor(state, crtc, new_crtc_state);
9538 DRM_DEBUG_DRIVER("dm_check_crtc_cursor() failed\n");
9543 if (state->legacy_cursor_update) {
9545 * This is a fast cursor update coming from the plane update
9546 * helper, check if it can be done asynchronously for better
9549 state->async_update =
9550 !drm_atomic_helper_async_check(dev, state);
9553 * Skip the remaining global validation if this is an async
9554 * update. Cursor updates can be done without affecting
9555 * state or bandwidth calcs and this avoids the performance
9556 * penalty of locking the private state object and
9557 * allocating a new dc_state.
9559 if (state->async_update)
9563 /* Check scaling and underscan changes*/
9564 /* TODO Removed scaling changes validation due to inability to commit
9565 * new stream into context w\o causing full reset. Need to
9566 * decide how to handle.
9568 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
9569 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
9570 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
9571 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
9573 /* Skip any modesets/resets */
9574 if (!acrtc || drm_atomic_crtc_needs_modeset(
9575 drm_atomic_get_new_crtc_state(state, &acrtc->base)))
9578 /* Skip any thing not scale or underscan changes */
9579 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
9582 lock_and_validation_needed = true;
9586 * Streams and planes are reset when there are changes that affect
9587 * bandwidth. Anything that affects bandwidth needs to go through
9588 * DC global validation to ensure that the configuration can be applied
9591 * We have to currently stall out here in atomic_check for outstanding
9592 * commits to finish in this case because our IRQ handlers reference
9593 * DRM state directly - we can end up disabling interrupts too early
9596 * TODO: Remove this stall and drop DM state private objects.
9598 if (lock_and_validation_needed) {
9599 ret = dm_atomic_get_state(state, &dm_state);
9601 DRM_DEBUG_DRIVER("dm_atomic_get_state() failed\n");
9605 ret = do_aquire_global_lock(dev, state);
9607 DRM_DEBUG_DRIVER("do_aquire_global_lock() failed\n");
9611 #if defined(CONFIG_DRM_AMD_DC_DCN)
9612 if (!compute_mst_dsc_configs_for_state(state, dm_state->context, vars)) {
9613 DRM_DEBUG_DRIVER("compute_mst_dsc_configs_for_state() failed\n");
9618 ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context, vars);
9620 DRM_DEBUG_DRIVER("dm_update_mst_vcpi_slots_for_dsc() failed\n");
9626 * Perform validation of MST topology in the state:
9627 * We need to perform MST atomic check before calling
9628 * dc_validate_global_state(), or there is a chance
9629 * to get stuck in an infinite loop and hang eventually.
9631 ret = drm_dp_mst_atomic_check(state);
9633 DRM_DEBUG_DRIVER("drm_dp_mst_atomic_check() failed\n");
9636 status = dc_validate_global_state(dc, dm_state->context, true);
9637 if (status != DC_OK) {
9638 DRM_DEBUG_DRIVER("DC global validation failure: %s (%d)",
9639 dc_status_to_str(status), status);
9645 * The commit is a fast update. Fast updates shouldn't change
9646 * the DC context, affect global validation, and can have their
9647 * commit work done in parallel with other commits not touching
9648 * the same resource. If we have a new DC context as part of
9649 * the DM atomic state from validation we need to free it and
9650 * retain the existing one instead.
9652 * Furthermore, since the DM atomic state only contains the DC
9653 * context and can safely be annulled, we can free the state
9654 * and clear the associated private object now to free
9655 * some memory and avoid a possible use-after-free later.
9658 for (i = 0; i < state->num_private_objs; i++) {
9659 struct drm_private_obj *obj = state->private_objs[i].ptr;
9661 if (obj->funcs == adev->dm.atomic_obj.funcs) {
9662 int j = state->num_private_objs-1;
9664 dm_atomic_destroy_state(obj,
9665 state->private_objs[i].state);
9667 /* If i is not at the end of the array then the
9668 * last element needs to be moved to where i was
9669 * before the array can safely be truncated.
9672 state->private_objs[i] =
9673 state->private_objs[j];
9675 state->private_objs[j].ptr = NULL;
9676 state->private_objs[j].state = NULL;
9677 state->private_objs[j].old_state = NULL;
9678 state->private_objs[j].new_state = NULL;
9680 state->num_private_objs = j;
9686 /* Store the overall update type for use later in atomic check. */
9687 for_each_new_crtc_in_state (state, crtc, new_crtc_state, i) {
9688 struct dm_crtc_state *dm_new_crtc_state =
9689 to_dm_crtc_state(new_crtc_state);
9691 dm_new_crtc_state->update_type = lock_and_validation_needed ?
9696 /* Must be success */
9699 trace_amdgpu_dm_atomic_check_finish(state, ret);
9704 if (ret == -EDEADLK)
9705 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
9706 else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
9707 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
9709 DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret);
9711 trace_amdgpu_dm_atomic_check_finish(state, ret);
9716 static bool is_dp_capable_without_timing_msa(struct dc *dc,
9717 struct amdgpu_dm_connector *amdgpu_dm_connector)
9720 bool capable = false;
9722 if (amdgpu_dm_connector->dc_link &&
9723 dm_helpers_dp_read_dpcd(
9725 amdgpu_dm_connector->dc_link,
9726 DP_DOWN_STREAM_PORT_COUNT,
9728 sizeof(dpcd_data))) {
9729 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
9735 static bool dm_edid_parser_send_cea(struct amdgpu_display_manager *dm,
9736 unsigned int offset,
9737 unsigned int total_length,
9739 unsigned int length,
9740 struct amdgpu_hdmi_vsdb_info *vsdb)
9743 union dmub_rb_cmd cmd;
9744 struct dmub_cmd_send_edid_cea *input;
9745 struct dmub_cmd_edid_cea_output *output;
9747 if (length > DMUB_EDID_CEA_DATA_CHUNK_BYTES)
9750 memset(&cmd, 0, sizeof(cmd));
9752 input = &cmd.edid_cea.data.input;
9754 cmd.edid_cea.header.type = DMUB_CMD__EDID_CEA;
9755 cmd.edid_cea.header.sub_type = 0;
9756 cmd.edid_cea.header.payload_bytes =
9757 sizeof(cmd.edid_cea) - sizeof(cmd.edid_cea.header);
9758 input->offset = offset;
9759 input->length = length;
9760 input->cea_total_length = total_length;
9761 memcpy(input->payload, data, length);
9763 res = dc_dmub_srv_cmd_with_reply_data(dm->dc->ctx->dmub_srv, &cmd);
9765 DRM_ERROR("EDID CEA parser failed\n");
9769 output = &cmd.edid_cea.data.output;
9771 if (output->type == DMUB_CMD__EDID_CEA_ACK) {
9772 if (!output->ack.success) {
9773 DRM_ERROR("EDID CEA ack failed at offset %d\n",
9774 output->ack.offset);
9776 } else if (output->type == DMUB_CMD__EDID_CEA_AMD_VSDB) {
9777 if (!output->amd_vsdb.vsdb_found)
9780 vsdb->freesync_supported = output->amd_vsdb.freesync_supported;
9781 vsdb->amd_vsdb_version = output->amd_vsdb.amd_vsdb_version;
9782 vsdb->min_refresh_rate_hz = output->amd_vsdb.min_frame_rate;
9783 vsdb->max_refresh_rate_hz = output->amd_vsdb.max_frame_rate;
9785 DRM_WARN("Unknown EDID CEA parser results\n");
9792 static bool parse_edid_cea_dmcu(struct amdgpu_display_manager *dm,
9793 uint8_t *edid_ext, int len,
9794 struct amdgpu_hdmi_vsdb_info *vsdb_info)
9798 /* send extension block to DMCU for parsing */
9799 for (i = 0; i < len; i += 8) {
9803 /* send 8 bytes a time */
9804 if (!dc_edid_parser_send_cea(dm->dc, i, len, &edid_ext[i], 8))
9808 /* EDID block sent completed, expect result */
9809 int version, min_rate, max_rate;
9811 res = dc_edid_parser_recv_amd_vsdb(dm->dc, &version, &min_rate, &max_rate);
9813 /* amd vsdb found */
9814 vsdb_info->freesync_supported = 1;
9815 vsdb_info->amd_vsdb_version = version;
9816 vsdb_info->min_refresh_rate_hz = min_rate;
9817 vsdb_info->max_refresh_rate_hz = max_rate;
9825 res = dc_edid_parser_recv_cea_ack(dm->dc, &offset);
9833 static bool parse_edid_cea_dmub(struct amdgpu_display_manager *dm,
9834 uint8_t *edid_ext, int len,
9835 struct amdgpu_hdmi_vsdb_info *vsdb_info)
9839 /* send extension block to DMCU for parsing */
9840 for (i = 0; i < len; i += 8) {
9841 /* send 8 bytes a time */
9842 if (!dm_edid_parser_send_cea(dm, i, len, &edid_ext[i], 8, vsdb_info))
9846 return vsdb_info->freesync_supported;
9849 static bool parse_edid_cea(struct amdgpu_dm_connector *aconnector,
9850 uint8_t *edid_ext, int len,
9851 struct amdgpu_hdmi_vsdb_info *vsdb_info)
9853 struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev);
9855 if (adev->dm.dmub_srv)
9856 return parse_edid_cea_dmub(&adev->dm, edid_ext, len, vsdb_info);
9858 return parse_edid_cea_dmcu(&adev->dm, edid_ext, len, vsdb_info);
9861 static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector,
9862 struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info)
9864 uint8_t *edid_ext = NULL;
9866 bool valid_vsdb_found = false;
9868 /*----- drm_find_cea_extension() -----*/
9869 /* No EDID or EDID extensions */
9870 if (edid == NULL || edid->extensions == 0)
9873 /* Find CEA extension */
9874 for (i = 0; i < edid->extensions; i++) {
9875 edid_ext = (uint8_t *)edid + EDID_LENGTH * (i + 1);
9876 if (edid_ext[0] == CEA_EXT)
9880 if (i == edid->extensions)
9883 /*----- cea_db_offsets() -----*/
9884 if (edid_ext[0] != CEA_EXT)
9887 valid_vsdb_found = parse_edid_cea(aconnector, edid_ext, EDID_LENGTH, vsdb_info);
9889 return valid_vsdb_found ? i : -ENODEV;
9892 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
9896 struct detailed_timing *timing;
9897 struct detailed_non_pixel *data;
9898 struct detailed_data_monitor_range *range;
9899 struct amdgpu_dm_connector *amdgpu_dm_connector =
9900 to_amdgpu_dm_connector(connector);
9901 struct dm_connector_state *dm_con_state = NULL;
9902 struct dc_sink *sink;
9904 struct drm_device *dev = connector->dev;
9905 struct amdgpu_device *adev = drm_to_adev(dev);
9906 bool freesync_capable = false;
9907 struct amdgpu_hdmi_vsdb_info vsdb_info = {0};
9909 if (!connector->state) {
9910 DRM_ERROR("%s - Connector has no state", __func__);
9914 sink = amdgpu_dm_connector->dc_sink ?
9915 amdgpu_dm_connector->dc_sink :
9916 amdgpu_dm_connector->dc_em_sink;
9918 if (!edid || !sink) {
9919 dm_con_state = to_dm_connector_state(connector->state);
9921 amdgpu_dm_connector->min_vfreq = 0;
9922 amdgpu_dm_connector->max_vfreq = 0;
9923 amdgpu_dm_connector->pixel_clock_mhz = 0;
9924 connector->display_info.monitor_range.min_vfreq = 0;
9925 connector->display_info.monitor_range.max_vfreq = 0;
9926 freesync_capable = false;
9931 dm_con_state = to_dm_connector_state(connector->state);
9933 if (!adev->dm.freesync_module)
9937 if (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
9938 || sink->sink_signal == SIGNAL_TYPE_EDP) {
9939 bool edid_check_required = false;
9942 edid_check_required = is_dp_capable_without_timing_msa(
9944 amdgpu_dm_connector);
9947 if (edid_check_required == true && (edid->version > 1 ||
9948 (edid->version == 1 && edid->revision > 1))) {
9949 for (i = 0; i < 4; i++) {
9951 timing = &edid->detailed_timings[i];
9952 data = &timing->data.other_data;
9953 range = &data->data.range;
9955 * Check if monitor has continuous frequency mode
9957 if (data->type != EDID_DETAIL_MONITOR_RANGE)
9960 * Check for flag range limits only. If flag == 1 then
9961 * no additional timing information provided.
9962 * Default GTF, GTF Secondary curve and CVT are not
9965 if (range->flags != 1)
9968 amdgpu_dm_connector->min_vfreq = range->min_vfreq;
9969 amdgpu_dm_connector->max_vfreq = range->max_vfreq;
9970 amdgpu_dm_connector->pixel_clock_mhz =
9971 range->pixel_clock_mhz * 10;
9973 connector->display_info.monitor_range.min_vfreq = range->min_vfreq;
9974 connector->display_info.monitor_range.max_vfreq = range->max_vfreq;
9979 if (amdgpu_dm_connector->max_vfreq -
9980 amdgpu_dm_connector->min_vfreq > 10) {
9982 freesync_capable = true;
9985 } else if (edid && sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) {
9986 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
9987 if (i >= 0 && vsdb_info.freesync_supported) {
9988 timing = &edid->detailed_timings[i];
9989 data = &timing->data.other_data;
9991 amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
9992 amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
9993 if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
9994 freesync_capable = true;
9996 connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz;
9997 connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz;
10003 dm_con_state->freesync_capable = freesync_capable;
10005 if (connector->vrr_capable_property)
10006 drm_connector_set_vrr_capable_property(connector,
10010 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev)
10012 struct amdgpu_device *adev = drm_to_adev(dev);
10013 struct dc *dc = adev->dm.dc;
10016 mutex_lock(&adev->dm.dc_lock);
10017 if (dc->current_state) {
10018 for (i = 0; i < dc->current_state->stream_count; ++i)
10019 dc->current_state->streams[i]
10020 ->triggered_crtc_reset.enabled =
10021 adev->dm.force_timing_sync;
10023 dm_enable_per_frame_crtc_master_sync(dc->current_state);
10024 dc_trigger_sync(dc, dc->current_state);
10026 mutex_unlock(&adev->dm.dc_lock);
10029 void dm_write_reg_func(const struct dc_context *ctx, uint32_t address,
10030 uint32_t value, const char *func_name)
10032 #ifdef DM_CHECK_ADDR_0
10033 if (address == 0) {
10034 DC_ERR("invalid register write. address = 0");
10038 cgs_write_register(ctx->cgs_device, address, value);
10039 trace_amdgpu_dc_wreg(&ctx->perf_trace->write_count, address, value);
10042 uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address,
10043 const char *func_name)
10046 #ifdef DM_CHECK_ADDR_0
10047 if (address == 0) {
10048 DC_ERR("invalid register read; address = 0\n");
10053 if (ctx->dmub_srv &&
10054 ctx->dmub_srv->reg_helper_offload.gather_in_progress &&
10055 !ctx->dmub_srv->reg_helper_offload.should_burst_write) {
10060 value = cgs_read_register(ctx->cgs_device, address);
10062 trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address, value);
10067 static int amdgpu_dm_set_dmub_async_sync_status(bool is_cmd_aux,
10068 struct dc_context *ctx,
10069 uint8_t status_type,
10070 uint32_t *operation_result)
10072 struct amdgpu_device *adev = ctx->driver_context;
10073 int return_status = -1;
10074 struct dmub_notification *p_notify = adev->dm.dmub_notify;
10077 if (status_type == DMUB_ASYNC_TO_SYNC_ACCESS_SUCCESS) {
10078 return_status = p_notify->aux_reply.length;
10079 *operation_result = p_notify->result;
10080 } else if (status_type == DMUB_ASYNC_TO_SYNC_ACCESS_TIMEOUT) {
10081 *operation_result = AUX_RET_ERROR_TIMEOUT;
10082 } else if (status_type == DMUB_ASYNC_TO_SYNC_ACCESS_FAIL) {
10083 *operation_result = AUX_RET_ERROR_ENGINE_ACQUIRE;
10085 *operation_result = AUX_RET_ERROR_UNKNOWN;
10088 if (status_type == DMUB_ASYNC_TO_SYNC_ACCESS_SUCCESS) {
10090 *operation_result = p_notify->sc_status;
10092 *operation_result = SET_CONFIG_UNKNOWN_ERROR;
10096 return return_status;
10099 int amdgpu_dm_process_dmub_aux_transfer_sync(bool is_cmd_aux, struct dc_context *ctx,
10100 unsigned int link_index, void *cmd_payload, void *operation_result)
10102 struct amdgpu_device *adev = ctx->driver_context;
10106 dc_process_dmub_aux_transfer_async(ctx->dc,
10107 link_index, (struct aux_payload *)cmd_payload);
10108 } else if (dc_process_dmub_set_config_async(ctx->dc, link_index,
10109 (struct set_config_cmd_payload *)cmd_payload,
10110 adev->dm.dmub_notify)) {
10111 return amdgpu_dm_set_dmub_async_sync_status(is_cmd_aux,
10112 ctx, DMUB_ASYNC_TO_SYNC_ACCESS_SUCCESS,
10113 (uint32_t *)operation_result);
10116 ret = wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ);
10118 DRM_ERROR("wait_for_completion_timeout timeout!");
10119 return amdgpu_dm_set_dmub_async_sync_status(is_cmd_aux,
10120 ctx, DMUB_ASYNC_TO_SYNC_ACCESS_TIMEOUT,
10121 (uint32_t *)operation_result);
10125 if (adev->dm.dmub_notify->result == AUX_RET_SUCCESS) {
10126 struct aux_payload *payload = (struct aux_payload *)cmd_payload;
10128 payload->reply[0] = adev->dm.dmub_notify->aux_reply.command;
10129 if (!payload->write && adev->dm.dmub_notify->aux_reply.length &&
10130 payload->reply[0] == AUX_TRANSACTION_REPLY_AUX_ACK) {
10131 memcpy(payload->data, adev->dm.dmub_notify->aux_reply.data,
10132 adev->dm.dmub_notify->aux_reply.length);
10137 return amdgpu_dm_set_dmub_async_sync_status(is_cmd_aux,
10138 ctx, DMUB_ASYNC_TO_SYNC_ACCESS_SUCCESS,
10139 (uint32_t *)operation_result);
10143 * Check whether seamless boot is supported.
10145 * So far we only support seamless boot on CHIP_VANGOGH.
10146 * If everything goes well, we may consider expanding
10147 * seamless boot to other ASICs.
10149 bool check_seamless_boot_capability(struct amdgpu_device *adev)
10151 switch (adev->asic_type) {
10153 if (!adev->mman.keep_stolen_vga_memory)