drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 /* The caprices of the preprocessor require that this be declared right here */
  27 #define CREATE_TRACE_POINTS
  28
  29 #include "dm_services_types.h"
  30 #include "dc.h"
  31 #include "dc_link_dp.h"
  32 #include "link_enc_cfg.h"
  33 #include "dc/inc/core_types.h"
  34 #include "dal_asic_id.h"
  35 #include "dmub/dmub_srv.h"
  36 #include "dc/inc/hw/dmcu.h"
  37 #include "dc/inc/hw/abm.h"
  38 #include "dc/dc_dmub_srv.h"
  39 #include "dc/dc_edid_parser.h"
  40 #include "dc/dc_stat.h"
  41 #include "amdgpu_dm_trace.h"
  42
  43 #include "vid.h"
  44 #include "amdgpu.h"
  45 #include "amdgpu_display.h"
  46 #include "amdgpu_ucode.h"
  47 #include "atom.h"
  48 #include "amdgpu_dm.h"
  49 #include "amdgpu_dm_plane.h"
  50 #include "amdgpu_dm_crtc.h"
  51 #ifdef CONFIG_DRM_AMD_DC_HDCP
  52 #include "amdgpu_dm_hdcp.h"
  53 #include <drm/display/drm_hdcp_helper.h>
  54 #endif
  55 #include "amdgpu_pm.h"
  56 #include "amdgpu_atombios.h"
  57
  58 #include "amd_shared.h"
  59 #include "amdgpu_dm_irq.h"
  60 #include "dm_helpers.h"
  61 #include "amdgpu_dm_mst_types.h"
  62 #if defined(CONFIG_DEBUG_FS)
  63 #include "amdgpu_dm_debugfs.h"
  64 #endif
  65 #include "amdgpu_dm_psr.h"
  66
  67 #include "ivsrcid/ivsrcid_vislands30.h"
  68
  69 #include "i2caux_interface.h"
  70 #include <linux/module.h>
  71 #include <linux/moduleparam.h>
  72 #include <linux/types.h>
  73 #include <linux/pm_runtime.h>
  74 #include <linux/pci.h>
  75 #include <linux/firmware.h>
  76 #include <linux/component.h>
  77 #include <linux/dmi.h>
  78
  79 #include <drm/display/drm_dp_mst_helper.h>
  80 #include <drm/display/drm_hdmi_helper.h>
  81 #include <drm/drm_atomic.h>
  82 #include <drm/drm_atomic_uapi.h>
  83 #include <drm/drm_atomic_helper.h>
  84 #include <drm/drm_blend.h>
  85 #include <drm/drm_fb_helper.h>
  86 #include <drm/drm_fourcc.h>
  87 #include <drm/drm_edid.h>
  88 #include <drm/drm_vblank.h>
  89 #include <drm/drm_audio_component.h>
  90 #include <drm/drm_gem_atomic_helper.h>
  91 #include <drm/drm_plane_helper.h>
  92
  93 #include <acpi/video.h>
  94
  95 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
  96
  97 #include "dcn/dcn_1_0_offset.h"
  98 #include "dcn/dcn_1_0_sh_mask.h"
  99 #include "soc15_hw_ip.h"
 100 #include "soc15_common.h"
 101 #include "vega10_ip_offset.h"
 102
 103 #include "gc/gc_11_0_0_offset.h"
 104 #include "gc/gc_11_0_0_sh_mask.h"
 105
 106 #include "modules/inc/mod_freesync.h"
 107 #include "modules/power/power_helpers.h"
 108 #include "modules/inc/mod_info_packet.h"
 109
 110 #define FIRMWARE_RENOIR_DMUB "amdgpu/renoir_dmcub.bin"
 111 MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB);
 112 #define FIRMWARE_SIENNA_CICHLID_DMUB "amdgpu/sienna_cichlid_dmcub.bin"
 113 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID_DMUB);
 114 #define FIRMWARE_NAVY_FLOUNDER_DMUB "amdgpu/navy_flounder_dmcub.bin"
 115 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER_DMUB);
 116 #define FIRMWARE_GREEN_SARDINE_DMUB "amdgpu/green_sardine_dmcub.bin"
 117 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE_DMUB);
 118 #define FIRMWARE_VANGOGH_DMUB "amdgpu/vangogh_dmcub.bin"
 119 MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB);
 120 #define FIRMWARE_DIMGREY_CAVEFISH_DMUB "amdgpu/dimgrey_cavefish_dmcub.bin"
 121 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH_DMUB);
 122 #define FIRMWARE_BEIGE_GOBY_DMUB "amdgpu/beige_goby_dmcub.bin"
 123 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY_DMUB);
 124 #define FIRMWARE_YELLOW_CARP_DMUB "amdgpu/yellow_carp_dmcub.bin"
 125 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP_DMUB);
 126 #define FIRMWARE_DCN_314_DMUB "amdgpu/dcn_3_1_4_dmcub.bin"
 127 MODULE_FIRMWARE(FIRMWARE_DCN_314_DMUB);
 128 #define FIRMWARE_DCN_315_DMUB "amdgpu/dcn_3_1_5_dmcub.bin"
 129 MODULE_FIRMWARE(FIRMWARE_DCN_315_DMUB);
 130 #define FIRMWARE_DCN316_DMUB "amdgpu/dcn_3_1_6_dmcub.bin"
 131 MODULE_FIRMWARE(FIRMWARE_DCN316_DMUB);
 132
 133 #define FIRMWARE_DCN_V3_2_0_DMCUB "amdgpu/dcn_3_2_0_dmcub.bin"
 134 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_0_DMCUB);
 135 #define FIRMWARE_DCN_V3_2_1_DMCUB "amdgpu/dcn_3_2_1_dmcub.bin"
 136 MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_1_DMCUB);
 137
 138 #define FIRMWARE_RAVEN_DMCU             "amdgpu/raven_dmcu.bin"
 139 MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
 140
 141 #define FIRMWARE_NAVI12_DMCU            "amdgpu/navi12_dmcu.bin"
 142 MODULE_FIRMWARE(FIRMWARE_NAVI12_DMCU);
 143
 144 /* Number of bytes in PSP header for firmware. */
 145 #define PSP_HEADER_BYTES 0x100
 146
 147 /* Number of bytes in PSP footer for firmware. */
 148 #define PSP_FOOTER_BYTES 0x100
 149
 150 /**
 151  * DOC: overview
 152  *
 153  * The AMDgpu display manager, **amdgpu_dm** (or even simpler,
 154  * **dm**) sits between DRM and DC. It acts as a liaison, converting DRM
 155  * requests into DC requests, and DC responses into DRM responses.
 156  *
 157  * The root control structure is &struct amdgpu_display_manager.
 158  */
 159
 160 /* basic init/fini API */
 161 static int amdgpu_dm_init(struct amdgpu_device *adev);
 162 static void amdgpu_dm_fini(struct amdgpu_device *adev);
 163 static bool is_freesync_video_mode(const struct drm_display_mode *mode, struct amdgpu_dm_connector *aconnector);
 164
 165 static enum drm_mode_subconnector get_subconnector_type(struct dc_link *link)
 166 {
 167         switch (link->dpcd_caps.dongle_type) {
 168         case DISPLAY_DONGLE_NONE:
 169                 return DRM_MODE_SUBCONNECTOR_Native;
 170         case DISPLAY_DONGLE_DP_VGA_CONVERTER:
 171                 return DRM_MODE_SUBCONNECTOR_VGA;
 172         case DISPLAY_DONGLE_DP_DVI_CONVERTER:
 173         case DISPLAY_DONGLE_DP_DVI_DONGLE:
 174                 return DRM_MODE_SUBCONNECTOR_DVID;
 175         case DISPLAY_DONGLE_DP_HDMI_CONVERTER:
 176         case DISPLAY_DONGLE_DP_HDMI_DONGLE:
 177                 return DRM_MODE_SUBCONNECTOR_HDMIA;
 178         case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
 179         default:
 180                 return DRM_MODE_SUBCONNECTOR_Unknown;
 181         }
 182 }
 183
 184 static void update_subconnector_property(struct amdgpu_dm_connector *aconnector)
 185 {
 186         struct dc_link *link = aconnector->dc_link;
 187         struct drm_connector *connector = &aconnector->base;
 188         enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
 189
 190         if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
 191                 return;
 192
 193         if (aconnector->dc_sink)
 194                 subconnector = get_subconnector_type(link);
 195
 196         drm_object_property_set_value(&connector->base,
 197                         connector->dev->mode_config.dp_subconnector_property,
 198                         subconnector);
 199 }
 200
 201 /*
 202  * initializes drm_device display related structures, based on the information
 203  * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
 204  * drm_encoder, drm_mode_config
 205  *
 206  * Returns 0 on success
 207  */
 208 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
 209 /* removes and deallocates the drm structures, created by the above function */
 210 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
 211
 212 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
 213                                     struct amdgpu_dm_connector *amdgpu_dm_connector,
 214                                     uint32_t link_index,
 215                                     struct amdgpu_encoder *amdgpu_encoder);
 216 static int amdgpu_dm_encoder_init(struct drm_device *dev,
 217                                   struct amdgpu_encoder *aencoder,
 218                                   uint32_t link_index);
 219
 220 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
 221
 222 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
 223
 224 static int amdgpu_dm_atomic_check(struct drm_device *dev,
 225                                   struct drm_atomic_state *state);
 226
 227 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector);
 228 static void handle_hpd_rx_irq(void *param);
 229
 230 static bool
 231 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
 232                                  struct drm_crtc_state *new_crtc_state);
 233 /*
 234  * dm_vblank_get_counter
 235  *
 236  * @brief
 237  * Get counter for number of vertical blanks
 238  *
 239  * @param
 240  * struct amdgpu_device *adev - [in] desired amdgpu device
 241  * int disp_idx - [in] which CRTC to get the counter from
 242  *
 243  * @return
 244  * Counter for vertical blanks
 245  */
 246 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
 247 {
 248         if (crtc >= adev->mode_info.num_crtc)
 249                 return 0;
 250         else {
 251                 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
 252
 253                 if (acrtc->dm_irq_params.stream == NULL) {
 254                         DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
 255                                   crtc);
 256                         return 0;
 257                 }
 258
 259                 return dc_stream_get_vblank_counter(acrtc->dm_irq_params.stream);
 260         }
 261 }
 262
 263 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
 264                                   u32 *vbl, u32 *position)
 265 {
 266         uint32_t v_blank_start, v_blank_end, h_position, v_position;
 267
 268         if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
 269                 return -EINVAL;
 270         else {
 271                 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
 272
 273                 if (acrtc->dm_irq_params.stream ==  NULL) {
 274                         DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
 275                                   crtc);
 276                         return 0;
 277                 }
 278
 279                 /*
 280                  * TODO rework base driver to use values directly.
 281                  * for now parse it back into reg-format
 282                  */
 283                 dc_stream_get_scanoutpos(acrtc->dm_irq_params.stream,
 284                                          &v_blank_start,
 285                                          &v_blank_end,
 286                                          &h_position,
 287                                          &v_position);
 288
 289                 *position = v_position | (h_position << 16);
 290                 *vbl = v_blank_start | (v_blank_end << 16);
 291         }
 292
 293         return 0;
 294 }
 295
 296 static bool dm_is_idle(void *handle)
 297 {
 298         /* XXX todo */
 299         return true;
 300 }
 301
 302 static int dm_wait_for_idle(void *handle)
 303 {
 304         /* XXX todo */
 305         return 0;
 306 }
 307
 308 static bool dm_check_soft_reset(void *handle)
 309 {
 310         return false;
 311 }
 312
 313 static int dm_soft_reset(void *handle)
 314 {
 315         /* XXX todo */
 316         return 0;
 317 }
 318
 319 static struct amdgpu_crtc *
 320 get_crtc_by_otg_inst(struct amdgpu_device *adev,
 321                      int otg_inst)
 322 {
 323         struct drm_device *dev = adev_to_drm(adev);
 324         struct drm_crtc *crtc;
 325         struct amdgpu_crtc *amdgpu_crtc;
 326
 327         if (WARN_ON(otg_inst == -1))
 328                 return adev->mode_info.crtcs[0];
 329
 330         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 331                 amdgpu_crtc = to_amdgpu_crtc(crtc);
 332
 333                 if (amdgpu_crtc->otg_inst == otg_inst)
 334                         return amdgpu_crtc;
 335         }
 336
 337         return NULL;
 338 }
 339
 340 static inline bool is_dc_timing_adjust_needed(struct dm_crtc_state *old_state,
 341                                               struct dm_crtc_state *new_state)
 342 {
 343         if (new_state->freesync_config.state ==  VRR_STATE_ACTIVE_FIXED)
 344                 return true;
 345         else if (amdgpu_dm_vrr_active(old_state) != amdgpu_dm_vrr_active(new_state))
 346                 return true;
 347         else
 348                 return false;
 349 }
 350
 351 /**
 352  * dm_pflip_high_irq() - Handle pageflip interrupt
 353  * @interrupt_params: ignored
 354  *
 355  * Handles the pageflip interrupt by notifying all interested parties
 356  * that the pageflip has been completed.
 357  */
 358 static void dm_pflip_high_irq(void *interrupt_params)
 359 {
 360         struct amdgpu_crtc *amdgpu_crtc;
 361         struct common_irq_params *irq_params = interrupt_params;
 362         struct amdgpu_device *adev = irq_params->adev;
 363         unsigned long flags;
 364         struct drm_pending_vblank_event *e;
 365         uint32_t vpos, hpos, v_blank_start, v_blank_end;
 366         bool vrr_active;
 367
 368         amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
 369
 370         /* IRQ could occur when in initial stage */
 371         /* TODO work and BO cleanup */
 372         if (amdgpu_crtc == NULL) {
 373                 DC_LOG_PFLIP("CRTC is null, returning.\n");
 374                 return;
 375         }
 376
 377         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
 378
 379         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
 380                 DC_LOG_PFLIP("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
 381                                                  amdgpu_crtc->pflip_status,
 382                                                  AMDGPU_FLIP_SUBMITTED,
 383                                                  amdgpu_crtc->crtc_id,
 384                                                  amdgpu_crtc);
 385                 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 386                 return;
 387         }
 388
 389         /* page flip completed. */
 390         e = amdgpu_crtc->event;
 391         amdgpu_crtc->event = NULL;
 392
 393         WARN_ON(!e);
 394
 395         vrr_active = amdgpu_dm_vrr_active_irq(amdgpu_crtc);
 396
 397         /* Fixed refresh rate, or VRR scanout position outside front-porch? */
 398         if (!vrr_active ||
 399             !dc_stream_get_scanoutpos(amdgpu_crtc->dm_irq_params.stream, &v_blank_start,
 400                                       &v_blank_end, &hpos, &vpos) ||
 401             (vpos < v_blank_start)) {
 402                 /* Update to correct count and vblank timestamp if racing with
 403                  * vblank irq. This also updates to the correct vblank timestamp
 404                  * even in VRR mode, as scanout is past the front-porch atm.
 405                  */
 406                 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
 407
 408                 /* Wake up userspace by sending the pageflip event with proper
 409                  * count and timestamp of vblank of flip completion.
 410                  */
 411                 if (e) {
 412                         drm_crtc_send_vblank_event(&amdgpu_crtc->base, e);
 413
 414                         /* Event sent, so done with vblank for this flip */
 415                         drm_crtc_vblank_put(&amdgpu_crtc->base);
 416                 }
 417         } else if (e) {
 418                 /* VRR active and inside front-porch: vblank count and
 419                  * timestamp for pageflip event will only be up to date after
 420                  * drm_crtc_handle_vblank() has been executed from late vblank
 421                  * irq handler after start of back-porch (vline 0). We queue the
 422                  * pageflip event for send-out by drm_crtc_handle_vblank() with
 423                  * updated timestamp and count, once it runs after us.
 424                  *
 425                  * We need to open-code this instead of using the helper
 426                  * drm_crtc_arm_vblank_event(), as that helper would
 427                  * call drm_crtc_accurate_vblank_count(), which we must
 428                  * not call in VRR mode while we are in front-porch!
 429                  */
 430
 431                 /* sequence will be replaced by real count during send-out. */
 432                 e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base);
 433                 e->pipe = amdgpu_crtc->crtc_id;
 434
 435                 list_add_tail(&e->base.link, &adev_to_drm(adev)->vblank_event_list);
 436                 e = NULL;
 437         }
 438
 439         /* Keep track of vblank of this flip for flip throttling. We use the
 440          * cooked hw counter, as that one incremented at start of this vblank
 441          * of pageflip completion, so last_flip_vblank is the forbidden count
 442          * for queueing new pageflips if vsync + VRR is enabled.
 443          */
 444         amdgpu_crtc->dm_irq_params.last_flip_vblank =
 445                 amdgpu_get_vblank_counter_kms(&amdgpu_crtc->base);
 446
 447         amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
 448         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 449
 450         DC_LOG_PFLIP("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n",
 451                      amdgpu_crtc->crtc_id, amdgpu_crtc,
 452                      vrr_active, (int) !e);
 453 }
 454
 455 static void dm_vupdate_high_irq(void *interrupt_params)
 456 {
 457         struct common_irq_params *irq_params = interrupt_params;
 458         struct amdgpu_device *adev = irq_params->adev;
 459         struct amdgpu_crtc *acrtc;
 460         struct drm_device *drm_dev;
 461         struct drm_vblank_crtc *vblank;
 462         ktime_t frame_duration_ns, previous_timestamp;
 463         unsigned long flags;
 464         int vrr_active;
 465
 466         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE);
 467
 468         if (acrtc) {
 469                 vrr_active = amdgpu_dm_vrr_active_irq(acrtc);
 470                 drm_dev = acrtc->base.dev;
 471                 vblank = &drm_dev->vblank[acrtc->base.index];
 472                 previous_timestamp = atomic64_read(&irq_params->previous_timestamp);
 473                 frame_duration_ns = vblank->time - previous_timestamp;
 474
 475                 if (frame_duration_ns > 0) {
 476                         trace_amdgpu_refresh_rate_track(acrtc->base.index,
 477                                                 frame_duration_ns,
 478                                                 ktime_divns(NSEC_PER_SEC, frame_duration_ns));
 479                         atomic64_set(&irq_params->previous_timestamp, vblank->time);
 480                 }
 481
 482                 DC_LOG_VBLANK("crtc:%d, vupdate-vrr:%d\n",
 483                               acrtc->crtc_id,
 484                               vrr_active);
 485
 486                 /* Core vblank handling is done here after end of front-porch in
 487                  * vrr mode, as vblank timestamping will give valid results
 488                  * while now done after front-porch. This will also deliver
 489                  * page-flip completion events that have been queued to us
 490                  * if a pageflip happened inside front-porch.
 491                  */
 492                 if (vrr_active) {
 493                         dm_crtc_handle_vblank(acrtc);
 494
 495                         /* BTR processing for pre-DCE12 ASICs */
 496                         if (acrtc->dm_irq_params.stream &&
 497                             adev->family < AMDGPU_FAMILY_AI) {
 498                                 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
 499                                 mod_freesync_handle_v_update(
 500                                     adev->dm.freesync_module,
 501                                     acrtc->dm_irq_params.stream,
 502                                     &acrtc->dm_irq_params.vrr_params);
 503
 504                                 dc_stream_adjust_vmin_vmax(
 505                                     adev->dm.dc,
 506                                     acrtc->dm_irq_params.stream,
 507                                     &acrtc->dm_irq_params.vrr_params.adjust);
 508                                 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 509                         }
 510                 }
 511         }
 512 }
 513
 514 /**
 515  * dm_crtc_high_irq() - Handles CRTC interrupt
 516  * @interrupt_params: used for determining the CRTC instance
 517  *
 518  * Handles the CRTC/VSYNC interrupt by notfying DRM's VBLANK
 519  * event handler.
 520  */
 521 static void dm_crtc_high_irq(void *interrupt_params)
 522 {
 523         struct common_irq_params *irq_params = interrupt_params;
 524         struct amdgpu_device *adev = irq_params->adev;
 525         struct amdgpu_crtc *acrtc;
 526         unsigned long flags;
 527         int vrr_active;
 528
 529         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
 530         if (!acrtc)
 531                 return;
 532
 533         vrr_active = amdgpu_dm_vrr_active_irq(acrtc);
 534
 535         DC_LOG_VBLANK("crtc:%d, vupdate-vrr:%d, planes:%d\n", acrtc->crtc_id,
 536                       vrr_active, acrtc->dm_irq_params.active_planes);
 537
 538         /**
 539          * Core vblank handling at start of front-porch is only possible
 540          * in non-vrr mode, as only there vblank timestamping will give
 541          * valid results while done in front-porch. Otherwise defer it
 542          * to dm_vupdate_high_irq after end of front-porch.
 543          */
 544         if (!vrr_active)
 545                 dm_crtc_handle_vblank(acrtc);
 546
 547         /**
 548          * Following stuff must happen at start of vblank, for crc
 549          * computation and below-the-range btr support in vrr mode.
 550          */
 551         amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
 552
 553         /* BTR updates need to happen before VUPDATE on Vega and above. */
 554         if (adev->family < AMDGPU_FAMILY_AI)
 555                 return;
 556
 557         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
 558
 559         if (acrtc->dm_irq_params.stream &&
 560             acrtc->dm_irq_params.vrr_params.supported &&
 561             acrtc->dm_irq_params.freesync_config.state ==
 562                     VRR_STATE_ACTIVE_VARIABLE) {
 563                 mod_freesync_handle_v_update(adev->dm.freesync_module,
 564                                              acrtc->dm_irq_params.stream,
 565                                              &acrtc->dm_irq_params.vrr_params);
 566
 567                 dc_stream_adjust_vmin_vmax(adev->dm.dc, acrtc->dm_irq_params.stream,
 568                                            &acrtc->dm_irq_params.vrr_params.adjust);
 569         }
 570
 571         /*
 572          * If there aren't any active_planes then DCH HUBP may be clock-gated.
 573          * In that case, pageflip completion interrupts won't fire and pageflip
 574          * completion events won't get delivered. Prevent this by sending
 575          * pending pageflip events from here if a flip is still pending.
 576          *
 577          * If any planes are enabled, use dm_pflip_high_irq() instead, to
 578          * avoid race conditions between flip programming and completion,
 579          * which could cause too early flip completion events.
 580          */
 581         if (adev->family >= AMDGPU_FAMILY_RV &&
 582             acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED &&
 583             acrtc->dm_irq_params.active_planes == 0) {
 584                 if (acrtc->event) {
 585                         drm_crtc_send_vblank_event(&acrtc->base, acrtc->event);
 586                         acrtc->event = NULL;
 587                         drm_crtc_vblank_put(&acrtc->base);
 588                 }
 589                 acrtc->pflip_status = AMDGPU_FLIP_NONE;
 590         }
 591
 592         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 593 }
 594
 595 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
 596 /**
 597  * dm_dcn_vertical_interrupt0_high_irq() - Handles OTG Vertical interrupt0 for
 598  * DCN generation ASICs
 599  * @interrupt_params: interrupt parameters
 600  *
 601  * Used to set crc window/read out crc value at vertical line 0 position
 602  */
 603 static void dm_dcn_vertical_interrupt0_high_irq(void *interrupt_params)
 604 {
 605         struct common_irq_params *irq_params = interrupt_params;
 606         struct amdgpu_device *adev = irq_params->adev;
 607         struct amdgpu_crtc *acrtc;
 608
 609         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VLINE0);
 610
 611         if (!acrtc)
 612                 return;
 613
 614         amdgpu_dm_crtc_handle_crc_window_irq(&acrtc->base);
 615 }
 616 #endif /* CONFIG_DRM_AMD_SECURE_DISPLAY */
 617
 618 /**
 619  * dmub_aux_setconfig_callback - Callback for AUX or SET_CONFIG command.
 620  * @adev: amdgpu_device pointer
 621  * @notify: dmub notification structure
 622  *
 623  * Dmub AUX or SET_CONFIG command completion processing callback
 624  * Copies dmub notification to DM which is to be read by AUX command.
 625  * issuing thread and also signals the event to wake up the thread.
 626  */
 627 static void dmub_aux_setconfig_callback(struct amdgpu_device *adev,
 628                                         struct dmub_notification *notify)
 629 {
 630         if (adev->dm.dmub_notify)
 631                 memcpy(adev->dm.dmub_notify, notify, sizeof(struct dmub_notification));
 632         if (notify->type == DMUB_NOTIFICATION_AUX_REPLY)
 633                 complete(&adev->dm.dmub_aux_transfer_done);
 634 }
 635
 636 /**
 637  * dmub_hpd_callback - DMUB HPD interrupt processing callback.
 638  * @adev: amdgpu_device pointer
 639  * @notify: dmub notification structure
 640  *
 641  * Dmub Hpd interrupt processing callback. Gets displayindex through the
 642  * ink index and calls helper to do the processing.
 643  */
 644 static void dmub_hpd_callback(struct amdgpu_device *adev,
 645                               struct dmub_notification *notify)
 646 {
 647         struct amdgpu_dm_connector *aconnector;
 648         struct amdgpu_dm_connector *hpd_aconnector = NULL;
 649         struct drm_connector *connector;
 650         struct drm_connector_list_iter iter;
 651         struct dc_link *link;
 652         uint8_t link_index = 0;
 653         struct drm_device *dev;
 654
 655         if (adev == NULL)
 656                 return;
 657
 658         if (notify == NULL) {
 659                 DRM_ERROR("DMUB HPD callback notification was NULL");
 660                 return;
 661         }
 662
 663         if (notify->link_index > adev->dm.dc->link_count) {
 664                 DRM_ERROR("DMUB HPD index (%u)is abnormal", notify->link_index);
 665                 return;
 666         }
 667
 668         link_index = notify->link_index;
 669         link = adev->dm.dc->links[link_index];
 670         dev = adev->dm.ddev;
 671
 672         drm_connector_list_iter_begin(dev, &iter);
 673         drm_for_each_connector_iter(connector, &iter) {
 674                 aconnector = to_amdgpu_dm_connector(connector);
 675                 if (link && aconnector->dc_link == link) {
 676                         DRM_INFO("DMUB HPD callback: link_index=%u\n", link_index);
 677                         hpd_aconnector = aconnector;
 678                         break;
 679                 }
 680         }
 681         drm_connector_list_iter_end(&iter);
 682
 683         if (hpd_aconnector) {
 684                 if (notify->type == DMUB_NOTIFICATION_HPD)
 685                         handle_hpd_irq_helper(hpd_aconnector);
 686                 else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ)
 687                         handle_hpd_rx_irq(hpd_aconnector);
 688         }
 689 }
 690
 691 /**
 692  * register_dmub_notify_callback - Sets callback for DMUB notify
 693  * @adev: amdgpu_device pointer
 694  * @type: Type of dmub notification
 695  * @callback: Dmub interrupt callback function
 696  * @dmub_int_thread_offload: offload indicator
 697  *
 698  * API to register a dmub callback handler for a dmub notification
 699  * Also sets indicator whether callback processing to be offloaded.
 700  * to dmub interrupt handling thread
 701  * Return: true if successfully registered, false if there is existing registration
 702  */
 703 static bool register_dmub_notify_callback(struct amdgpu_device *adev,
 704                                           enum dmub_notification_type type,
 705                                           dmub_notify_interrupt_callback_t callback,
 706                                           bool dmub_int_thread_offload)
 707 {
 708         if (callback != NULL && type < ARRAY_SIZE(adev->dm.dmub_thread_offload)) {
 709                 adev->dm.dmub_callback[type] = callback;
 710                 adev->dm.dmub_thread_offload[type] = dmub_int_thread_offload;
 711         } else
 712                 return false;
 713
 714         return true;
 715 }
 716
 717 static void dm_handle_hpd_work(struct work_struct *work)
 718 {
 719         struct dmub_hpd_work *dmub_hpd_wrk;
 720
 721         dmub_hpd_wrk = container_of(work, struct dmub_hpd_work, handle_hpd_work);
 722
 723         if (!dmub_hpd_wrk->dmub_notify) {
 724                 DRM_ERROR("dmub_hpd_wrk dmub_notify is NULL");
 725                 return;
 726         }
 727
 728         if (dmub_hpd_wrk->dmub_notify->type < ARRAY_SIZE(dmub_hpd_wrk->adev->dm.dmub_callback)) {
 729                 dmub_hpd_wrk->adev->dm.dmub_callback[dmub_hpd_wrk->dmub_notify->type](dmub_hpd_wrk->adev,
 730                 dmub_hpd_wrk->dmub_notify);
 731         }
 732
 733         kfree(dmub_hpd_wrk->dmub_notify);
 734         kfree(dmub_hpd_wrk);
 735
 736 }
 737
 738 #define DMUB_TRACE_MAX_READ 64
 739 /**
 740  * dm_dmub_outbox1_low_irq() - Handles Outbox interrupt
 741  * @interrupt_params: used for determining the Outbox instance
 742  *
 743  * Handles the Outbox Interrupt
 744  * event handler.
 745  */
 746 static void dm_dmub_outbox1_low_irq(void *interrupt_params)
 747 {
 748         struct dmub_notification notify;
 749         struct common_irq_params *irq_params = interrupt_params;
 750         struct amdgpu_device *adev = irq_params->adev;
 751         struct amdgpu_display_manager *dm = &adev->dm;
 752         struct dmcub_trace_buf_entry entry = { 0 };
 753         uint32_t count = 0;
 754         struct dmub_hpd_work *dmub_hpd_wrk;
 755         struct dc_link *plink = NULL;
 756
 757         if (dc_enable_dmub_notifications(adev->dm.dc) &&
 758                 irq_params->irq_src == DC_IRQ_SOURCE_DMCUB_OUTBOX) {
 759
 760                 do {
 761                         dc_stat_get_dmub_notification(adev->dm.dc, &notify);
 762                         if (notify.type >= ARRAY_SIZE(dm->dmub_thread_offload)) {
 763                                 DRM_ERROR("DM: notify type %d invalid!", notify.type);
 764                                 continue;
 765                         }
 766                         if (!dm->dmub_callback[notify.type]) {
 767                                 DRM_DEBUG_DRIVER("DMUB notification skipped, no handler: type=%d\n", notify.type);
 768                                 continue;
 769                         }
 770                         if (dm->dmub_thread_offload[notify.type] == true) {
 771                                 dmub_hpd_wrk = kzalloc(sizeof(*dmub_hpd_wrk), GFP_ATOMIC);
 772                                 if (!dmub_hpd_wrk) {
 773                                         DRM_ERROR("Failed to allocate dmub_hpd_wrk");
 774                                         return;
 775                                 }
 776                                 dmub_hpd_wrk->dmub_notify = kzalloc(sizeof(struct dmub_notification), GFP_ATOMIC);
 777                                 if (!dmub_hpd_wrk->dmub_notify) {
 778                                         kfree(dmub_hpd_wrk);
 779                                         DRM_ERROR("Failed to allocate dmub_hpd_wrk->dmub_notify");
 780                                         return;
 781                                 }
 782                                 INIT_WORK(&dmub_hpd_wrk->handle_hpd_work, dm_handle_hpd_work);
 783                                 if (dmub_hpd_wrk->dmub_notify)
 784                                         memcpy(dmub_hpd_wrk->dmub_notify, &notify, sizeof(struct dmub_notification));
 785                                 dmub_hpd_wrk->adev = adev;
 786                                 if (notify.type == DMUB_NOTIFICATION_HPD) {
 787                                         plink = adev->dm.dc->links[notify.link_index];
 788                                         if (plink) {
 789                                                 plink->hpd_status =
 790                                                         notify.hpd_status == DP_HPD_PLUG;
 791                                         }
 792                                 }
 793                                 queue_work(adev->dm.delayed_hpd_wq, &dmub_hpd_wrk->handle_hpd_work);
 794                         } else {
 795                                 dm->dmub_callback[notify.type](adev, &notify);
 796                         }
 797                 } while (notify.pending_notification);
 798         }
 799
 800
 801         do {
 802                 if (dc_dmub_srv_get_dmub_outbox0_msg(dm->dc, &entry)) {
 803                         trace_amdgpu_dmub_trace_high_irq(entry.trace_code, entry.tick_count,
 804                                                         entry.param0, entry.param1);
 805
 806                         DRM_DEBUG_DRIVER("trace_code:%u, tick_count:%u, param0:%u, param1:%u\n",
 807                                  entry.trace_code, entry.tick_count, entry.param0, entry.param1);
 808                 } else
 809                         break;
 810
 811                 count++;
 812
 813         } while (count <= DMUB_TRACE_MAX_READ);
 814
 815         if (count > DMUB_TRACE_MAX_READ)
 816                 DRM_DEBUG_DRIVER("Warning : count > DMUB_TRACE_MAX_READ");
 817 }
 818
 819 static int dm_set_clockgating_state(void *handle,
 820                   enum amd_clockgating_state state)
 821 {
 822         return 0;
 823 }
 824
 825 static int dm_set_powergating_state(void *handle,
 826                   enum amd_powergating_state state)
 827 {
 828         return 0;
 829 }
 830
 831 /* Prototypes of private functions */
 832 static int dm_early_init(void* handle);
 833
 834 /* Allocate memory for FBC compressed data  */
 835 static void amdgpu_dm_fbc_init(struct drm_connector *connector)
 836 {
 837         struct drm_device *dev = connector->dev;
 838         struct amdgpu_device *adev = drm_to_adev(dev);
 839         struct dm_compressor_info *compressor = &adev->dm.compressor;
 840         struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
 841         struct drm_display_mode *mode;
 842         unsigned long max_size = 0;
 843
 844         if (adev->dm.dc->fbc_compressor == NULL)
 845                 return;
 846
 847         if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
 848                 return;
 849
 850         if (compressor->bo_ptr)
 851                 return;
 852
 853
 854         list_for_each_entry(mode, &connector->modes, head) {
 855                 if (max_size < mode->htotal * mode->vtotal)
 856                         max_size = mode->htotal * mode->vtotal;
 857         }
 858
 859         if (max_size) {
 860                 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,
 861                             AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr,
 862                             &compressor->gpu_addr, &compressor->cpu_addr);
 863
 864                 if (r)
 865                         DRM_ERROR("DM: Failed to initialize FBC\n");
 866                 else {
 867                         adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
 868                         DRM_INFO("DM: FBC alloc %lu\n", max_size*4);
 869                 }
 870
 871         }
 872
 873 }
 874
 875 static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port,
 876                                           int pipe, bool *enabled,
 877                                           unsigned char *buf, int max_bytes)
 878 {
 879         struct drm_device *dev = dev_get_drvdata(kdev);
 880         struct amdgpu_device *adev = drm_to_adev(dev);
 881         struct drm_connector *connector;
 882         struct drm_connector_list_iter conn_iter;
 883         struct amdgpu_dm_connector *aconnector;
 884         int ret = 0;
 885
 886         *enabled = false;
 887
 888         mutex_lock(&adev->dm.audio_lock);
 889
 890         drm_connector_list_iter_begin(dev, &conn_iter);
 891         drm_for_each_connector_iter(connector, &conn_iter) {
 892                 aconnector = to_amdgpu_dm_connector(connector);
 893                 if (aconnector->audio_inst != port)
 894                         continue;
 895
 896                 *enabled = true;
 897                 ret = drm_eld_size(connector->eld);
 898                 memcpy(buf, connector->eld, min(max_bytes, ret));
 899
 900                 break;
 901         }
 902         drm_connector_list_iter_end(&conn_iter);
 903
 904         mutex_unlock(&adev->dm.audio_lock);
 905
 906         DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled);
 907
 908         return ret;
 909 }
 910
 911 static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = {
 912         .get_eld = amdgpu_dm_audio_component_get_eld,
 913 };
 914
 915 static int amdgpu_dm_audio_component_bind(struct device *kdev,
 916                                        struct device *hda_kdev, void *data)
 917 {
 918         struct drm_device *dev = dev_get_drvdata(kdev);
 919         struct amdgpu_device *adev = drm_to_adev(dev);
 920         struct drm_audio_component *acomp = data;
 921
 922         acomp->ops = &amdgpu_dm_audio_component_ops;
 923         acomp->dev = kdev;
 924         adev->dm.audio_component = acomp;
 925
 926         return 0;
 927 }
 928
 929 static void amdgpu_dm_audio_component_unbind(struct device *kdev,
 930                                           struct device *hda_kdev, void *data)
 931 {
 932         struct drm_device *dev = dev_get_drvdata(kdev);
 933         struct amdgpu_device *adev = drm_to_adev(dev);
 934         struct drm_audio_component *acomp = data;
 935
 936         acomp->ops = NULL;
 937         acomp->dev = NULL;
 938         adev->dm.audio_component = NULL;
 939 }
 940
 941 static const struct component_ops amdgpu_dm_audio_component_bind_ops = {
 942         .bind   = amdgpu_dm_audio_component_bind,
 943         .unbind = amdgpu_dm_audio_component_unbind,
 944 };
 945
 946 static int amdgpu_dm_audio_init(struct amdgpu_device *adev)
 947 {
 948         int i, ret;
 949
 950         if (!amdgpu_audio)
 951                 return 0;
 952
 953         adev->mode_info.audio.enabled = true;
 954
 955         adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count;
 956
 957         for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
 958                 adev->mode_info.audio.pin[i].channels = -1;
 959                 adev->mode_info.audio.pin[i].rate = -1;
 960                 adev->mode_info.audio.pin[i].bits_per_sample = -1;
 961                 adev->mode_info.audio.pin[i].status_bits = 0;
 962                 adev->mode_info.audio.pin[i].category_code = 0;
 963                 adev->mode_info.audio.pin[i].connected = false;
 964                 adev->mode_info.audio.pin[i].id =
 965                         adev->dm.dc->res_pool->audios[i]->inst;
 966                 adev->mode_info.audio.pin[i].offset = 0;
 967         }
 968
 969         ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops);
 970         if (ret < 0)
 971                 return ret;
 972
 973         adev->dm.audio_registered = true;
 974
 975         return 0;
 976 }
 977
 978 static void amdgpu_dm_audio_fini(struct amdgpu_device *adev)
 979 {
 980         if (!amdgpu_audio)
 981                 return;
 982
 983         if (!adev->mode_info.audio.enabled)
 984                 return;
 985
 986         if (adev->dm.audio_registered) {
 987                 component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops);
 988                 adev->dm.audio_registered = false;
 989         }
 990
 991         /* TODO: Disable audio? */
 992
 993         adev->mode_info.audio.enabled = false;
 994 }
 995
 996 static  void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin)
 997 {
 998         struct drm_audio_component *acomp = adev->dm.audio_component;
 999
1000         if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) {
1001                 DRM_DEBUG_KMS("Notify ELD: %d\n", pin);
1002
1003                 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
1004                                                  pin, -1);
1005         }
1006 }
1007
1008 static int dm_dmub_hw_init(struct amdgpu_device *adev)
1009 {
1010         const struct dmcub_firmware_header_v1_0 *hdr;
1011         struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
1012         struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
1013         const struct firmware *dmub_fw = adev->dm.dmub_fw;
1014         struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
1015         struct abm *abm = adev->dm.dc->res_pool->abm;
1016         struct dmub_srv_hw_params hw_params;
1017         enum dmub_status status;
1018         const unsigned char *fw_inst_const, *fw_bss_data;
1019         uint32_t i, fw_inst_const_size, fw_bss_data_size;
1020         bool has_hw_support;
1021
1022         if (!dmub_srv)
1023                 /* DMUB isn't supported on the ASIC. */
1024                 return 0;
1025
1026         if (!fb_info) {
1027                 DRM_ERROR("No framebuffer info for DMUB service.\n");
1028                 return -EINVAL;
1029         }
1030
1031         if (!dmub_fw) {
1032                 /* Firmware required for DMUB support. */
1033                 DRM_ERROR("No firmware provided for DMUB.\n");
1034                 return -EINVAL;
1035         }
1036
1037         status = dmub_srv_has_hw_support(dmub_srv, &has_hw_support);
1038         if (status != DMUB_STATUS_OK) {
1039                 DRM_ERROR("Error checking HW support for DMUB: %d\n", status);
1040                 return -EINVAL;
1041         }
1042
1043         if (!has_hw_support) {
1044                 DRM_INFO("DMUB unsupported on ASIC\n");
1045                 return 0;
1046         }
1047
1048         /* Reset DMCUB if it was previously running - before we overwrite its memory. */
1049         status = dmub_srv_hw_reset(dmub_srv);
1050         if (status != DMUB_STATUS_OK)
1051                 DRM_WARN("Error resetting DMUB HW: %d\n", status);
1052
1053         hdr = (const struct dmcub_firmware_header_v1_0 *)dmub_fw->data;
1054
1055         fw_inst_const = dmub_fw->data +
1056                         le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1057                         PSP_HEADER_BYTES;
1058
1059         fw_bss_data = dmub_fw->data +
1060                       le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
1061                       le32_to_cpu(hdr->inst_const_bytes);
1062
1063         /* Copy firmware and bios info into FB memory. */
1064         fw_inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
1065                              PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
1066
1067         fw_bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
1068
1069         /* if adev->firmware.load_type == AMDGPU_FW_LOAD_PSP,
1070          * amdgpu_ucode_init_single_fw will load dmub firmware
1071          * fw_inst_const part to cw0; otherwise, the firmware back door load
1072          * will be done by dm_dmub_hw_init
1073          */
1074         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1075                 memcpy(fb_info->fb[DMUB_WINDOW_0_INST_CONST].cpu_addr, fw_inst_const,
1076                                 fw_inst_const_size);
1077         }
1078
1079         if (fw_bss_data_size)
1080                 memcpy(fb_info->fb[DMUB_WINDOW_2_BSS_DATA].cpu_addr,
1081                        fw_bss_data, fw_bss_data_size);
1082
1083         /* Copy firmware bios info into FB memory. */
1084         memcpy(fb_info->fb[DMUB_WINDOW_3_VBIOS].cpu_addr, adev->bios,
1085                adev->bios_size);
1086
1087         /* Reset regions that need to be reset. */
1088         memset(fb_info->fb[DMUB_WINDOW_4_MAILBOX].cpu_addr, 0,
1089         fb_info->fb[DMUB_WINDOW_4_MAILBOX].size);
1090
1091         memset(fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr, 0,
1092                fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size);
1093
1094         memset(fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr, 0,
1095                fb_info->fb[DMUB_WINDOW_6_FW_STATE].size);
1096
1097         /* Initialize hardware. */
1098         memset(&hw_params, 0, sizeof(hw_params));
1099         hw_params.fb_base = adev->gmc.fb_start;
1100         hw_params.fb_offset = adev->gmc.aper_base;
1101
1102         /* backdoor load firmware and trigger dmub running */
1103         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
1104                 hw_params.load_inst_const = true;
1105
1106         if (dmcu)
1107                 hw_params.psp_version = dmcu->psp_version;
1108
1109         for (i = 0; i < fb_info->num_fb; ++i)
1110                 hw_params.fb[i] = &fb_info->fb[i];
1111
1112         switch (adev->ip_versions[DCE_HWIP][0]) {
1113         case IP_VERSION(3, 1, 3):
1114         case IP_VERSION(3, 1, 4):
1115                 hw_params.dpia_supported = true;
1116                 hw_params.disable_dpia = adev->dm.dc->debug.dpia_debug.bits.disable_dpia;
1117                 break;
1118         default:
1119                 break;
1120         }
1121
1122         status = dmub_srv_hw_init(dmub_srv, &hw_params);
1123         if (status != DMUB_STATUS_OK) {
1124                 DRM_ERROR("Error initializing DMUB HW: %d\n", status);
1125                 return -EINVAL;
1126         }
1127
1128         /* Wait for firmware load to finish. */
1129         status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
1130         if (status != DMUB_STATUS_OK)
1131                 DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
1132
1133         /* Init DMCU and ABM if available. */
1134         if (dmcu && abm) {
1135                 dmcu->funcs->dmcu_init(dmcu);
1136                 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
1137         }
1138
1139         if (!adev->dm.dc->ctx->dmub_srv)
1140                 adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv);
1141         if (!adev->dm.dc->ctx->dmub_srv) {
1142                 DRM_ERROR("Couldn't allocate DC DMUB server!\n");
1143                 return -ENOMEM;
1144         }
1145
1146         DRM_INFO("DMUB hardware initialized: version=0x%08X\n",
1147                  adev->dm.dmcub_fw_version);
1148
1149         return 0;
1150 }
1151
1152 static void dm_dmub_hw_resume(struct amdgpu_device *adev)
1153 {
1154         struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
1155         enum dmub_status status;
1156         bool init;
1157
1158         if (!dmub_srv) {
1159                 /* DMUB isn't supported on the ASIC. */
1160                 return;
1161         }
1162
1163         status = dmub_srv_is_hw_init(dmub_srv, &init);
1164         if (status != DMUB_STATUS_OK)
1165                 DRM_WARN("DMUB hardware init check failed: %d\n", status);
1166
1167         if (status == DMUB_STATUS_OK && init) {
1168                 /* Wait for firmware load to finish. */
1169                 status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
1170                 if (status != DMUB_STATUS_OK)
1171                         DRM_WARN("Wait for DMUB auto-load failed: %d\n", status);
1172         } else {
1173                 /* Perform the full hardware initialization. */
1174                 dm_dmub_hw_init(adev);
1175         }
1176 }
1177
1178 static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_addr_space_config *pa_config)
1179 {
1180         uint64_t pt_base;
1181         uint32_t logical_addr_low;
1182         uint32_t logical_addr_high;
1183         uint32_t agp_base, agp_bot, agp_top;
1184         PHYSICAL_ADDRESS_LOC page_table_start, page_table_end, page_table_base;
1185
1186         memset(pa_config, 0, sizeof(*pa_config));
1187
1188         logical_addr_low  = min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18;
1189         pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
1190
1191         if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1192                 /*
1193                  * Raven2 has a HW issue that it is unable to use the vram which
1194                  * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
1195                  * workaround that increase system aperture high address (add 1)
1196                  * to get rid of the VM fault and hardware hang.
1197                  */
1198                 logical_addr_high = max((adev->gmc.fb_end >> 18) + 0x1, adev->gmc.agp_end >> 18);
1199         else
1200                 logical_addr_high = max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18;
1201
1202         agp_base = 0;
1203         agp_bot = adev->gmc.agp_start >> 24;
1204         agp_top = adev->gmc.agp_end >> 24;
1205
1206
1207         page_table_start.high_part = (u32)(adev->gmc.gart_start >> 44) & 0xF;
1208         page_table_start.low_part = (u32)(adev->gmc.gart_start >> 12);
1209         page_table_end.high_part = (u32)(adev->gmc.gart_end >> 44) & 0xF;
1210         page_table_end.low_part = (u32)(adev->gmc.gart_end >> 12);
1211         page_table_base.high_part = upper_32_bits(pt_base) & 0xF;
1212         page_table_base.low_part = lower_32_bits(pt_base);
1213
1214         pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18;
1215         pa_config->system_aperture.end_addr = (uint64_t)logical_addr_high << 18;
1216
1217         pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24 ;
1218         pa_config->system_aperture.agp_bot = (uint64_t)agp_bot << 24;
1219         pa_config->system_aperture.agp_top = (uint64_t)agp_top << 24;
1220
1221         pa_config->system_aperture.fb_base = adev->gmc.fb_start;
1222         pa_config->system_aperture.fb_offset = adev->gmc.aper_base;
1223         pa_config->system_aperture.fb_top = adev->gmc.fb_end;
1224
1225         pa_config->gart_config.page_table_start_addr = page_table_start.quad_part << 12;
1226         pa_config->gart_config.page_table_end_addr = page_table_end.quad_part << 12;
1227         pa_config->gart_config.page_table_base_addr = page_table_base.quad_part;
1228
1229         pa_config->is_hvm_enabled = 0;
1230
1231 }
1232
1233 static void dm_handle_hpd_rx_offload_work(struct work_struct *work)
1234 {
1235         struct hpd_rx_irq_offload_work *offload_work;
1236         struct amdgpu_dm_connector *aconnector;
1237         struct dc_link *dc_link;
1238         struct amdgpu_device *adev;
1239         enum dc_connection_type new_connection_type = dc_connection_none;
1240         unsigned long flags;
1241
1242         offload_work = container_of(work, struct hpd_rx_irq_offload_work, work);
1243         aconnector = offload_work->offload_wq->aconnector;
1244
1245         if (!aconnector) {
1246                 DRM_ERROR("Can't retrieve aconnector in hpd_rx_irq_offload_work");
1247                 goto skip;
1248         }
1249
1250         adev = drm_to_adev(aconnector->base.dev);
1251         dc_link = aconnector->dc_link;
1252
1253         mutex_lock(&aconnector->hpd_lock);
1254         if (!dc_link_detect_sink(dc_link, &new_connection_type))
1255                 DRM_ERROR("KMS: Failed to detect connector\n");
1256         mutex_unlock(&aconnector->hpd_lock);
1257
1258         if (new_connection_type == dc_connection_none)
1259                 goto skip;
1260
1261         if (amdgpu_in_reset(adev))
1262                 goto skip;
1263
1264         mutex_lock(&adev->dm.dc_lock);
1265         if (offload_work->data.bytes.device_service_irq.bits.AUTOMATED_TEST)
1266                 dc_link_dp_handle_automated_test(dc_link);
1267         else if ((dc_link->connector_signal != SIGNAL_TYPE_EDP) &&
1268                         hpd_rx_irq_check_link_loss_status(dc_link, &offload_work->data) &&
1269                         dc_link_dp_allow_hpd_rx_irq(dc_link)) {
1270                 dc_link_dp_handle_link_loss(dc_link);
1271                 spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags);
1272                 offload_work->offload_wq->is_handling_link_loss = false;
1273                 spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags);
1274         }
1275         mutex_unlock(&adev->dm.dc_lock);
1276
1277 skip:
1278         kfree(offload_work);
1279
1280 }
1281
1282 static struct hpd_rx_irq_offload_work_queue *hpd_rx_irq_create_workqueue(struct dc *dc)
1283 {
1284         int max_caps = dc->caps.max_links;
1285         int i = 0;
1286         struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq = NULL;
1287
1288         hpd_rx_offload_wq = kcalloc(max_caps, sizeof(*hpd_rx_offload_wq), GFP_KERNEL);
1289
1290         if (!hpd_rx_offload_wq)
1291                 return NULL;
1292
1293
1294         for (i = 0; i < max_caps; i++) {
1295                 hpd_rx_offload_wq[i].wq =
1296                                     create_singlethread_workqueue("amdgpu_dm_hpd_rx_offload_wq");
1297
1298                 if (hpd_rx_offload_wq[i].wq == NULL) {
1299                         DRM_ERROR("create amdgpu_dm_hpd_rx_offload_wq fail!");
1300                         goto out_err;
1301                 }
1302
1303                 spin_lock_init(&hpd_rx_offload_wq[i].offload_lock);
1304         }
1305
1306         return hpd_rx_offload_wq;
1307
1308 out_err:
1309         for (i = 0; i < max_caps; i++) {
1310                 if (hpd_rx_offload_wq[i].wq)
1311                         destroy_workqueue(hpd_rx_offload_wq[i].wq);
1312         }
1313         kfree(hpd_rx_offload_wq);
1314         return NULL;
1315 }
1316
1317 struct amdgpu_stutter_quirk {
1318         u16 chip_vendor;
1319         u16 chip_device;
1320         u16 subsys_vendor;
1321         u16 subsys_device;
1322         u8 revision;
1323 };
1324
1325 static const struct amdgpu_stutter_quirk amdgpu_stutter_quirk_list[] = {
1326         /* https://bugzilla.kernel.org/show_bug.cgi?id=214417 */
1327         { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 },
1328         { 0, 0, 0, 0, 0 },
1329 };
1330
1331 static bool dm_should_disable_stutter(struct pci_dev *pdev)
1332 {
1333         const struct amdgpu_stutter_quirk *p = amdgpu_stutter_quirk_list;
1334
1335         while (p && p->chip_device != 0) {
1336                 if (pdev->vendor == p->chip_vendor &&
1337                     pdev->device == p->chip_device &&
1338                     pdev->subsystem_vendor == p->subsys_vendor &&
1339                     pdev->subsystem_device == p->subsys_device &&
1340                     pdev->revision == p->revision) {
1341                         return true;
1342                 }
1343                 ++p;
1344         }
1345         return false;
1346 }
1347
1348 static const struct dmi_system_id hpd_disconnect_quirk_table[] = {
1349         {
1350                 .matches = {
1351                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1352                         DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3660"),
1353                 },
1354         },
1355         {
1356                 .matches = {
1357                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1358                         DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3260"),
1359                 },
1360         },
1361         {
1362                 .matches = {
1363                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
1364                         DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3460"),
1365                 },
1366         },
1367         {}
1368 };
1369
1370 static void retrieve_dmi_info(struct amdgpu_display_manager *dm)
1371 {
1372         const struct dmi_system_id *dmi_id;
1373
1374         dm->aux_hpd_discon_quirk = false;
1375
1376         dmi_id = dmi_first_match(hpd_disconnect_quirk_table);
1377         if (dmi_id) {
1378                 dm->aux_hpd_discon_quirk = true;
1379                 DRM_INFO("aux_hpd_discon_quirk attached\n");
1380         }
1381 }
1382
1383 static int amdgpu_dm_init(struct amdgpu_device *adev)
1384 {
1385         struct dc_init_data init_data;
1386 #ifdef CONFIG_DRM_AMD_DC_HDCP
1387         struct dc_callback_init init_params;
1388 #endif
1389         int r;
1390
1391         adev->dm.ddev = adev_to_drm(adev);
1392         adev->dm.adev = adev;
1393
1394         /* Zero all the fields */
1395         memset(&init_data, 0, sizeof(init_data));
1396 #ifdef CONFIG_DRM_AMD_DC_HDCP
1397         memset(&init_params, 0, sizeof(init_params));
1398 #endif
1399
1400         mutex_init(&adev->dm.dc_lock);
1401         mutex_init(&adev->dm.audio_lock);
1402         spin_lock_init(&adev->dm.vblank_lock);
1403
1404         if(amdgpu_dm_irq_init(adev)) {
1405                 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
1406                 goto error;
1407         }
1408
1409         init_data.asic_id.chip_family = adev->family;
1410
1411         init_data.asic_id.pci_revision_id = adev->pdev->revision;
1412         init_data.asic_id.hw_internal_rev = adev->external_rev_id;
1413         init_data.asic_id.chip_id = adev->pdev->device;
1414
1415         init_data.asic_id.vram_width = adev->gmc.vram_width;
1416         /* TODO: initialize init_data.asic_id.vram_type here!!!! */
1417         init_data.asic_id.atombios_base_address =
1418                 adev->mode_info.atom_context->bios;
1419
1420         init_data.driver = adev;
1421
1422         adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
1423
1424         if (!adev->dm.cgs_device) {
1425                 DRM_ERROR("amdgpu: failed to create cgs device.\n");
1426                 goto error;
1427         }
1428
1429         init_data.cgs_device = adev->dm.cgs_device;
1430
1431         init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
1432
1433         switch (adev->ip_versions[DCE_HWIP][0]) {
1434         case IP_VERSION(2, 1, 0):
1435                 switch (adev->dm.dmcub_fw_version) {
1436                 case 0: /* development */
1437                 case 0x1: /* linux-firmware.git hash 6d9f399 */
1438                 case 0x01000000: /* linux-firmware.git hash 9a0b0f4 */
1439                         init_data.flags.disable_dmcu = false;
1440                         break;
1441                 default:
1442                         init_data.flags.disable_dmcu = true;
1443                 }
1444                 break;
1445         case IP_VERSION(2, 0, 3):
1446                 init_data.flags.disable_dmcu = true;
1447                 break;
1448         default:
1449                 break;
1450         }
1451
1452         switch (adev->asic_type) {
1453         case CHIP_CARRIZO:
1454         case CHIP_STONEY:
1455                 init_data.flags.gpu_vm_support = true;
1456                 break;
1457         default:
1458                 switch (adev->ip_versions[DCE_HWIP][0]) {
1459                 case IP_VERSION(1, 0, 0):
1460                 case IP_VERSION(1, 0, 1):
1461                         /* enable S/G on PCO and RV2 */
1462                         if ((adev->apu_flags & AMD_APU_IS_RAVEN2) ||
1463                             (adev->apu_flags & AMD_APU_IS_PICASSO))
1464                                 init_data.flags.gpu_vm_support = true;
1465                         break;
1466                 case IP_VERSION(2, 1, 0):
1467                 case IP_VERSION(3, 0, 1):
1468                 case IP_VERSION(3, 1, 2):
1469                 case IP_VERSION(3, 1, 3):
1470                 case IP_VERSION(3, 1, 5):
1471                 case IP_VERSION(3, 1, 6):
1472                         init_data.flags.gpu_vm_support = true;
1473                         break;
1474                 default:
1475                         break;
1476                 }
1477                 break;
1478         }
1479
1480         if (init_data.flags.gpu_vm_support)
1481                 adev->mode_info.gpu_vm_support = true;
1482
1483         if (amdgpu_dc_feature_mask & DC_FBC_MASK)
1484                 init_data.flags.fbc_support = true;
1485
1486         if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK)
1487                 init_data.flags.multi_mon_pp_mclk_switch = true;
1488
1489         if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK)
1490                 init_data.flags.disable_fractional_pwm = true;
1491
1492         if (amdgpu_dc_feature_mask & DC_EDP_NO_POWER_SEQUENCING)
1493                 init_data.flags.edp_no_power_sequencing = true;
1494
1495         if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP1_4A)
1496                 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP1_4A = true;
1497         if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP2_0)
1498                 init_data.flags.allow_lttpr_non_transparent_mode.bits.DP2_0 = true;
1499
1500         init_data.flags.seamless_boot_edp_requested = false;
1501
1502         if (check_seamless_boot_capability(adev)) {
1503                 init_data.flags.seamless_boot_edp_requested = true;
1504                 init_data.flags.allow_seamless_boot_optimization = true;
1505                 DRM_INFO("Seamless boot condition check passed\n");
1506         }
1507
1508         init_data.flags.enable_mipi_converter_optimization = true;
1509
1510         init_data.dcn_reg_offsets = adev->reg_offset[DCE_HWIP][0];
1511         init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0];
1512
1513         INIT_LIST_HEAD(&adev->dm.da_list);
1514
1515         retrieve_dmi_info(&adev->dm);
1516
1517         /* Display Core create. */
1518         adev->dm.dc = dc_create(&init_data);
1519
1520         if (adev->dm.dc) {
1521                 DRM_INFO("Display Core initialized with v%s!\n", DC_VER);
1522         } else {
1523                 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER);
1524                 goto error;
1525         }
1526
1527         if (amdgpu_dc_debug_mask & DC_DISABLE_PIPE_SPLIT) {
1528                 adev->dm.dc->debug.force_single_disp_pipe_split = false;
1529                 adev->dm.dc->debug.pipe_split_policy = MPC_SPLIT_AVOID;
1530         }
1531
1532         if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY)
1533                 adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;
1534         if (dm_should_disable_stutter(adev->pdev))
1535                 adev->dm.dc->debug.disable_stutter = true;
1536
1537         if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER)
1538                 adev->dm.dc->debug.disable_stutter = true;
1539
1540         if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) {
1541                 adev->dm.dc->debug.disable_dsc = true;
1542         }
1543
1544         if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING)
1545                 adev->dm.dc->debug.disable_clock_gate = true;
1546
1547         if (amdgpu_dc_debug_mask & DC_FORCE_SUBVP_MCLK_SWITCH)
1548                 adev->dm.dc->debug.force_subvp_mclk_switch = true;
1549
1550         adev->dm.dc->debug.visual_confirm = amdgpu_dc_visual_confirm;
1551
1552         r = dm_dmub_hw_init(adev);
1553         if (r) {
1554                 DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
1555                 goto error;
1556         }
1557
1558         dc_hardware_init(adev->dm.dc);
1559
1560         adev->dm.hpd_rx_offload_wq = hpd_rx_irq_create_workqueue(adev->dm.dc);
1561         if (!adev->dm.hpd_rx_offload_wq) {
1562                 DRM_ERROR("amdgpu: failed to create hpd rx offload workqueue.\n");
1563                 goto error;
1564         }
1565
1566         if ((adev->flags & AMD_IS_APU) && (adev->asic_type >= CHIP_CARRIZO)) {
1567                 struct dc_phy_addr_space_config pa_config;
1568
1569                 mmhub_read_system_context(adev, &pa_config);
1570
1571                 // Call the DC init_memory func
1572                 dc_setup_system_context(adev->dm.dc, &pa_config);
1573         }
1574
1575         adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
1576         if (!adev->dm.freesync_module) {
1577                 DRM_ERROR(
1578                 "amdgpu: failed to initialize freesync_module.\n");
1579         } else
1580                 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
1581                                 adev->dm.freesync_module);
1582
1583         amdgpu_dm_init_color_mod();
1584
1585         if (adev->dm.dc->caps.max_links > 0) {
1586                 adev->dm.vblank_control_workqueue =
1587                         create_singlethread_workqueue("dm_vblank_control_workqueue");
1588                 if (!adev->dm.vblank_control_workqueue)
1589                         DRM_ERROR("amdgpu: failed to initialize vblank_workqueue.\n");
1590         }
1591
1592 #ifdef CONFIG_DRM_AMD_DC_HDCP
1593         if (adev->dm.dc->caps.max_links > 0 && adev->family >= AMDGPU_FAMILY_RV) {
1594                 adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc);
1595
1596                 if (!adev->dm.hdcp_workqueue)
1597                         DRM_ERROR("amdgpu: failed to initialize hdcp_workqueue.\n");
1598                 else
1599                         DRM_DEBUG_DRIVER("amdgpu: hdcp_workqueue init done %p.\n", adev->dm.hdcp_workqueue);
1600
1601                 dc_init_callbacks(adev->dm.dc, &init_params);
1602         }
1603 #endif
1604 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
1605         adev->dm.crc_rd_wrk = amdgpu_dm_crtc_secure_display_create_work();
1606 #endif
1607         if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
1608                 init_completion(&adev->dm.dmub_aux_transfer_done);
1609                 adev->dm.dmub_notify = kzalloc(sizeof(struct dmub_notification), GFP_KERNEL);
1610                 if (!adev->dm.dmub_notify) {
1611                         DRM_INFO("amdgpu: fail to allocate adev->dm.dmub_notify");
1612                         goto error;
1613                 }
1614
1615                 adev->dm.delayed_hpd_wq = create_singlethread_workqueue("amdgpu_dm_hpd_wq");
1616                 if (!adev->dm.delayed_hpd_wq) {
1617                         DRM_ERROR("amdgpu: failed to create hpd offload workqueue.\n");
1618                         goto error;
1619                 }
1620
1621                 amdgpu_dm_outbox_init(adev);
1622                 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_AUX_REPLY,
1623                         dmub_aux_setconfig_callback, false)) {
1624                         DRM_ERROR("amdgpu: fail to register dmub aux callback");
1625                         goto error;
1626                 }
1627                 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD, dmub_hpd_callback, true)) {
1628                         DRM_ERROR("amdgpu: fail to register dmub hpd callback");
1629                         goto error;
1630                 }
1631                 if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD_IRQ, dmub_hpd_callback, true)) {
1632                         DRM_ERROR("amdgpu: fail to register dmub hpd callback");
1633                         goto error;
1634                 }
1635         }
1636
1637         if (amdgpu_dm_initialize_drm_device(adev)) {
1638                 DRM_ERROR(
1639                 "amdgpu: failed to initialize sw for display support.\n");
1640                 goto error;
1641         }
1642
1643         /* Enable outbox notification only after IRQ handlers are registered and DMUB is alive.
1644          * It is expected that DMUB will resend any pending notifications at this point, for
1645          * example HPD from DPIA.
1646          */
1647         if (dc_is_dmub_outbox_supported(adev->dm.dc))
1648                 dc_enable_dmub_outbox(adev->dm.dc);
1649
1650         /* create fake encoders for MST */
1651         dm_dp_create_fake_mst_encoders(adev);
1652
1653         /* TODO: Add_display_info? */
1654
1655         /* TODO use dynamic cursor width */
1656         adev_to_drm(adev)->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
1657         adev_to_drm(adev)->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
1658
1659         if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) {
1660                 DRM_ERROR(
1661                 "amdgpu: failed to initialize sw for display support.\n");
1662                 goto error;
1663         }
1664
1665
1666         DRM_DEBUG_DRIVER("KMS initialized.\n");
1667
1668         return 0;
1669 error:
1670         amdgpu_dm_fini(adev);
1671
1672         return -EINVAL;
1673 }
1674
1675 static int amdgpu_dm_early_fini(void *handle)
1676 {
1677         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1678
1679         amdgpu_dm_audio_fini(adev);
1680
1681         return 0;
1682 }
1683
1684 static void amdgpu_dm_fini(struct amdgpu_device *adev)
1685 {
1686         int i;
1687
1688         if (adev->dm.vblank_control_workqueue) {
1689                 destroy_workqueue(adev->dm.vblank_control_workqueue);
1690                 adev->dm.vblank_control_workqueue = NULL;
1691         }
1692
1693         for (i = 0; i < adev->dm.display_indexes_num; i++) {
1694                 drm_encoder_cleanup(&adev->dm.mst_encoders[i].base);
1695         }
1696
1697         amdgpu_dm_destroy_drm_device(&adev->dm);
1698
1699 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
1700         if (adev->dm.crc_rd_wrk) {
1701                 flush_work(&adev->dm.crc_rd_wrk->notify_ta_work);
1702                 kfree(adev->dm.crc_rd_wrk);
1703                 adev->dm.crc_rd_wrk = NULL;
1704         }
1705 #endif
1706 #ifdef CONFIG_DRM_AMD_DC_HDCP
1707         if (adev->dm.hdcp_workqueue) {
1708                 hdcp_destroy(&adev->dev->kobj, adev->dm.hdcp_workqueue);
1709                 adev->dm.hdcp_workqueue = NULL;
1710         }
1711
1712         if (adev->dm.dc)
1713                 dc_deinit_callbacks(adev->dm.dc);
1714 #endif
1715
1716         dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv);
1717
1718         if (dc_enable_dmub_notifications(adev->dm.dc)) {
1719                 kfree(adev->dm.dmub_notify);
1720                 adev->dm.dmub_notify = NULL;
1721                 destroy_workqueue(adev->dm.delayed_hpd_wq);
1722                 adev->dm.delayed_hpd_wq = NULL;
1723         }
1724
1725         if (adev->dm.dmub_bo)
1726                 amdgpu_bo_free_kernel(&adev->dm.dmub_bo,
1727                                       &adev->dm.dmub_bo_gpu_addr,
1728                                       &adev->dm.dmub_bo_cpu_addr);
1729
1730         if (adev->dm.hpd_rx_offload_wq) {
1731                 for (i = 0; i < adev->dm.dc->caps.max_links; i++) {
1732                         if (adev->dm.hpd_rx_offload_wq[i].wq) {
1733                                 destroy_workqueue(adev->dm.hpd_rx_offload_wq[i].wq);
1734                                 adev->dm.hpd_rx_offload_wq[i].wq = NULL;
1735                         }
1736                 }
1737
1738                 kfree(adev->dm.hpd_rx_offload_wq);
1739                 adev->dm.hpd_rx_offload_wq = NULL;
1740         }
1741
1742         /* DC Destroy TODO: Replace destroy DAL */
1743         if (adev->dm.dc)
1744                 dc_destroy(&adev->dm.dc);
1745         /*
1746          * TODO: pageflip, vlank interrupt
1747          *
1748          * amdgpu_dm_irq_fini(adev);
1749          */
1750
1751         if (adev->dm.cgs_device) {
1752                 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
1753                 adev->dm.cgs_device = NULL;
1754         }
1755         if (adev->dm.freesync_module) {
1756                 mod_freesync_destroy(adev->dm.freesync_module);
1757                 adev->dm.freesync_module = NULL;
1758         }
1759
1760         mutex_destroy(&adev->dm.audio_lock);
1761         mutex_destroy(&adev->dm.dc_lock);
1762
1763         return;
1764 }
1765
1766 static int load_dmcu_fw(struct amdgpu_device *adev)
1767 {
1768         const char *fw_name_dmcu = NULL;
1769         int r;
1770         const struct dmcu_firmware_header_v1_0 *hdr;
1771
1772         switch(adev->asic_type) {
1773 #if defined(CONFIG_DRM_AMD_DC_SI)
1774         case CHIP_TAHITI:
1775         case CHIP_PITCAIRN:
1776         case CHIP_VERDE:
1777         case CHIP_OLAND:
1778 #endif
1779         case CHIP_BONAIRE:
1780         case CHIP_HAWAII:
1781         case CHIP_KAVERI:
1782         case CHIP_KABINI:
1783         case CHIP_MULLINS:
1784         case CHIP_TONGA:
1785         case CHIP_FIJI:
1786         case CHIP_CARRIZO:
1787         case CHIP_STONEY:
1788         case CHIP_POLARIS11:
1789         case CHIP_POLARIS10:
1790         case CHIP_POLARIS12:
1791         case CHIP_VEGAM:
1792         case CHIP_VEGA10:
1793         case CHIP_VEGA12:
1794         case CHIP_VEGA20:
1795                 return 0;
1796         case CHIP_NAVI12:
1797                 fw_name_dmcu = FIRMWARE_NAVI12_DMCU;
1798                 break;
1799         case CHIP_RAVEN:
1800                 if (ASICREV_IS_PICASSO(adev->external_rev_id))
1801                         fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
1802                 else if (ASICREV_IS_RAVEN2(adev->external_rev_id))
1803                         fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
1804                 else
1805                         return 0;
1806                 break;
1807         default:
1808                 switch (adev->ip_versions[DCE_HWIP][0]) {
1809                 case IP_VERSION(2, 0, 2):
1810                 case IP_VERSION(2, 0, 3):
1811                 case IP_VERSION(2, 0, 0):
1812                 case IP_VERSION(2, 1, 0):
1813                 case IP_VERSION(3, 0, 0):
1814                 case IP_VERSION(3, 0, 2):
1815                 case IP_VERSION(3, 0, 3):
1816                 case IP_VERSION(3, 0, 1):
1817                 case IP_VERSION(3, 1, 2):
1818                 case IP_VERSION(3, 1, 3):
1819                 case IP_VERSION(3, 1, 4):
1820                 case IP_VERSION(3, 1, 5):
1821                 case IP_VERSION(3, 1, 6):
1822                 case IP_VERSION(3, 2, 0):
1823                 case IP_VERSION(3, 2, 1):
1824                         return 0;
1825                 default:
1826                         break;
1827                 }
1828                 DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
1829                 return -EINVAL;
1830         }
1831
1832         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1833                 DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n");
1834                 return 0;
1835         }
1836
1837         r = request_firmware_direct(&adev->dm.fw_dmcu, fw_name_dmcu, adev->dev);
1838         if (r == -ENOENT) {
1839                 /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */
1840                 DRM_DEBUG_KMS("dm: DMCU firmware not found\n");
1841                 adev->dm.fw_dmcu = NULL;
1842                 return 0;
1843         }
1844         if (r) {
1845                 dev_err(adev->dev, "amdgpu_dm: Can't load firmware \"%s\"\n",
1846                         fw_name_dmcu);
1847                 return r;
1848         }
1849
1850         r = amdgpu_ucode_validate(adev->dm.fw_dmcu);
1851         if (r) {
1852                 dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n",
1853                         fw_name_dmcu);
1854                 release_firmware(adev->dm.fw_dmcu);
1855                 adev->dm.fw_dmcu = NULL;
1856                 return r;
1857         }
1858
1859         hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data;
1860         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM;
1861         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu;
1862         adev->firmware.fw_size +=
1863                 ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
1864
1865         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV;
1866         adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu;
1867         adev->firmware.fw_size +=
1868                 ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
1869
1870         adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version);
1871
1872         DRM_DEBUG_KMS("PSP loading DMCU firmware\n");
1873
1874         return 0;
1875 }
1876
1877 static uint32_t amdgpu_dm_dmub_reg_read(void *ctx, uint32_t address)
1878 {
1879         struct amdgpu_device *adev = ctx;
1880
1881         return dm_read_reg(adev->dm.dc->ctx, address);
1882 }
1883
1884 static void amdgpu_dm_dmub_reg_write(void *ctx, uint32_t address,
1885                                      uint32_t value)
1886 {
1887         struct amdgpu_device *adev = ctx;
1888
1889         return dm_write_reg(adev->dm.dc->ctx, address, value);
1890 }
1891
1892 static int dm_dmub_sw_init(struct amdgpu_device *adev)
1893 {
1894         struct dmub_srv_create_params create_params;
1895         struct dmub_srv_region_params region_params;
1896         struct dmub_srv_region_info region_info;
1897         struct dmub_srv_fb_params fb_params;
1898         struct dmub_srv_fb_info *fb_info;
1899         struct dmub_srv *dmub_srv;
1900         const struct dmcub_firmware_header_v1_0 *hdr;
1901         const char *fw_name_dmub;
1902         enum dmub_asic dmub_asic;
1903         enum dmub_status status;
1904         int r;
1905
1906         switch (adev->ip_versions[DCE_HWIP][0]) {
1907         case IP_VERSION(2, 1, 0):
1908                 dmub_asic = DMUB_ASIC_DCN21;
1909                 fw_name_dmub = FIRMWARE_RENOIR_DMUB;
1910                 if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
1911                         fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB;
1912                 break;
1913         case IP_VERSION(3, 0, 0):
1914                 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) {
1915                         dmub_asic = DMUB_ASIC_DCN30;
1916                         fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB;
1917                 } else {
1918                         dmub_asic = DMUB_ASIC_DCN30;
1919                         fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB;
1920                 }
1921                 break;
1922         case IP_VERSION(3, 0, 1):
1923                 dmub_asic = DMUB_ASIC_DCN301;
1924                 fw_name_dmub = FIRMWARE_VANGOGH_DMUB;
1925                 break;
1926         case IP_VERSION(3, 0, 2):
1927                 dmub_asic = DMUB_ASIC_DCN302;
1928                 fw_name_dmub = FIRMWARE_DIMGREY_CAVEFISH_DMUB;
1929                 break;
1930         case IP_VERSION(3, 0, 3):
1931                 dmub_asic = DMUB_ASIC_DCN303;
1932                 fw_name_dmub = FIRMWARE_BEIGE_GOBY_DMUB;
1933                 break;
1934         case IP_VERSION(3, 1, 2):
1935         case IP_VERSION(3, 1, 3):
1936                 dmub_asic = (adev->external_rev_id == YELLOW_CARP_B0) ? DMUB_ASIC_DCN31B : DMUB_ASIC_DCN31;
1937                 fw_name_dmub = FIRMWARE_YELLOW_CARP_DMUB;
1938                 break;
1939         case IP_VERSION(3, 1, 4):
1940                 dmub_asic = DMUB_ASIC_DCN314;
1941                 fw_name_dmub = FIRMWARE_DCN_314_DMUB;
1942                 break;
1943         case IP_VERSION(3, 1, 5):
1944                 dmub_asic = DMUB_ASIC_DCN315;
1945                 fw_name_dmub = FIRMWARE_DCN_315_DMUB;
1946                 break;
1947         case IP_VERSION(3, 1, 6):
1948                 dmub_asic = DMUB_ASIC_DCN316;
1949                 fw_name_dmub = FIRMWARE_DCN316_DMUB;
1950                 break;
1951         case IP_VERSION(3, 2, 0):
1952                 dmub_asic = DMUB_ASIC_DCN32;
1953                 fw_name_dmub = FIRMWARE_DCN_V3_2_0_DMCUB;
1954                 break;
1955         case IP_VERSION(3, 2, 1):
1956                 dmub_asic = DMUB_ASIC_DCN321;
1957                 fw_name_dmub = FIRMWARE_DCN_V3_2_1_DMCUB;
1958                 break;
1959         default:
1960                 /* ASIC doesn't support DMUB. */
1961                 return 0;
1962         }
1963
1964         r = request_firmware_direct(&adev->dm.dmub_fw, fw_name_dmub, adev->dev);
1965         if (r) {
1966                 DRM_ERROR("DMUB firmware loading failed: %d\n", r);
1967                 return 0;
1968         }
1969
1970         r = amdgpu_ucode_validate(adev->dm.dmub_fw);
1971         if (r) {
1972                 DRM_ERROR("Couldn't validate DMUB firmware: %d\n", r);
1973                 return 0;
1974         }
1975
1976         hdr = (const struct dmcub_firmware_header_v1_0 *)adev->dm.dmub_fw->data;
1977         adev->dm.dmcub_fw_version = le32_to_cpu(hdr->header.ucode_version);
1978
1979         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1980                 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].ucode_id =
1981                         AMDGPU_UCODE_ID_DMCUB;
1982                 adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].fw =
1983                         adev->dm.dmub_fw;
1984                 adev->firmware.fw_size +=
1985                         ALIGN(le32_to_cpu(hdr->inst_const_bytes), PAGE_SIZE);
1986
1987                 DRM_INFO("Loading DMUB firmware via PSP: version=0x%08X\n",
1988                          adev->dm.dmcub_fw_version);
1989         }
1990
1991
1992         adev->dm.dmub_srv = kzalloc(sizeof(*adev->dm.dmub_srv), GFP_KERNEL);
1993         dmub_srv = adev->dm.dmub_srv;
1994
1995         if (!dmub_srv) {
1996                 DRM_ERROR("Failed to allocate DMUB service!\n");
1997                 return -ENOMEM;
1998         }
1999
2000         memset(&create_params, 0, sizeof(create_params));
2001         create_params.user_ctx = adev;
2002         create_params.funcs.reg_read = amdgpu_dm_dmub_reg_read;
2003         create_params.funcs.reg_write = amdgpu_dm_dmub_reg_write;
2004         create_params.asic = dmub_asic;
2005
2006         /* Create the DMUB service. */
2007         status = dmub_srv_create(dmub_srv, &create_params);
2008         if (status != DMUB_STATUS_OK) {
2009                 DRM_ERROR("Error creating DMUB service: %d\n", status);
2010                 return -EINVAL;
2011         }
2012
2013         /* Calculate the size of all the regions for the DMUB service. */
2014         memset(&region_params, 0, sizeof(region_params));
2015
2016         region_params.inst_const_size = le32_to_cpu(hdr->inst_const_bytes) -
2017                                         PSP_HEADER_BYTES - PSP_FOOTER_BYTES;
2018         region_params.bss_data_size = le32_to_cpu(hdr->bss_data_bytes);
2019         region_params.vbios_size = adev->bios_size;
2020         region_params.fw_bss_data = region_params.bss_data_size ?
2021                 adev->dm.dmub_fw->data +
2022                 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
2023                 le32_to_cpu(hdr->inst_const_bytes) : NULL;
2024         region_params.fw_inst_const =
2025                 adev->dm.dmub_fw->data +
2026                 le32_to_cpu(hdr->header.ucode_array_offset_bytes) +
2027                 PSP_HEADER_BYTES;
2028
2029         status = dmub_srv_calc_region_info(dmub_srv, &region_params,
2030                                            &region_info);
2031
2032         if (status != DMUB_STATUS_OK) {
2033                 DRM_ERROR("Error calculating DMUB region info: %d\n", status);
2034                 return -EINVAL;
2035         }
2036
2037         /*
2038          * Allocate a framebuffer based on the total size of all the regions.
2039          * TODO: Move this into GART.
2040          */
2041         r = amdgpu_bo_create_kernel(adev, region_info.fb_size, PAGE_SIZE,
2042                                     AMDGPU_GEM_DOMAIN_VRAM, &adev->dm.dmub_bo,
2043                                     &adev->dm.dmub_bo_gpu_addr,
2044                                     &adev->dm.dmub_bo_cpu_addr);
2045         if (r)
2046                 return r;
2047
2048         /* Rebase the regions on the framebuffer address. */
2049         memset(&fb_params, 0, sizeof(fb_params));
2050         fb_params.cpu_addr = adev->dm.dmub_bo_cpu_addr;
2051         fb_params.gpu_addr = adev->dm.dmub_bo_gpu_addr;
2052         fb_params.region_info = &region_info;
2053
2054         adev->dm.dmub_fb_info =
2055                 kzalloc(sizeof(*adev->dm.dmub_fb_info), GFP_KERNEL);
2056         fb_info = adev->dm.dmub_fb_info;
2057
2058         if (!fb_info) {
2059                 DRM_ERROR(
2060                         "Failed to allocate framebuffer info for DMUB service!\n");
2061                 return -ENOMEM;
2062         }
2063
2064         status = dmub_srv_calc_fb_info(dmub_srv, &fb_params, fb_info);
2065         if (status != DMUB_STATUS_OK) {
2066                 DRM_ERROR("Error calculating DMUB FB info: %d\n", status);
2067                 return -EINVAL;
2068         }
2069
2070         return 0;
2071 }
2072
2073 static int dm_sw_init(void *handle)
2074 {
2075         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2076         int r;
2077
2078         r = dm_dmub_sw_init(adev);
2079         if (r)
2080                 return r;
2081
2082         return load_dmcu_fw(adev);
2083 }
2084
2085 static int dm_sw_fini(void *handle)
2086 {
2087         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2088
2089         kfree(adev->dm.dmub_fb_info);
2090         adev->dm.dmub_fb_info = NULL;
2091
2092         if (adev->dm.dmub_srv) {
2093                 dmub_srv_destroy(adev->dm.dmub_srv);
2094                 adev->dm.dmub_srv = NULL;
2095         }
2096
2097         release_firmware(adev->dm.dmub_fw);
2098         adev->dm.dmub_fw = NULL;
2099
2100         release_firmware(adev->dm.fw_dmcu);
2101         adev->dm.fw_dmcu = NULL;
2102
2103         return 0;
2104 }
2105
2106 static int detect_mst_link_for_all_connectors(struct drm_device *dev)
2107 {
2108         struct amdgpu_dm_connector *aconnector;
2109         struct drm_connector *connector;
2110         struct drm_connector_list_iter iter;
2111         int ret = 0;
2112
2113         drm_connector_list_iter_begin(dev, &iter);
2114         drm_for_each_connector_iter(connector, &iter) {
2115                 aconnector = to_amdgpu_dm_connector(connector);
2116                 if (aconnector->dc_link->type == dc_connection_mst_branch &&
2117                     aconnector->mst_mgr.aux) {
2118                         DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
2119                                          aconnector,
2120                                          aconnector->base.base.id);
2121
2122                         ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
2123                         if (ret < 0) {
2124                                 DRM_ERROR("DM_MST: Failed to start MST\n");
2125                                 aconnector->dc_link->type =
2126                                         dc_connection_single;
2127                                 break;
2128                         }
2129                 }
2130         }
2131         drm_connector_list_iter_end(&iter);
2132
2133         return ret;
2134 }
2135
2136 static int dm_late_init(void *handle)
2137 {
2138         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2139
2140         struct dmcu_iram_parameters params;
2141         unsigned int linear_lut[16];
2142         int i;
2143         struct dmcu *dmcu = NULL;
2144
2145         dmcu = adev->dm.dc->res_pool->dmcu;
2146
2147         for (i = 0; i < 16; i++)
2148                 linear_lut[i] = 0xFFFF * i / 15;
2149
2150         params.set = 0;
2151         params.backlight_ramping_override = false;
2152         params.backlight_ramping_start = 0xCCCC;
2153         params.backlight_ramping_reduction = 0xCCCCCCCC;
2154         params.backlight_lut_array_size = 16;
2155         params.backlight_lut_array = linear_lut;
2156
2157         /* Min backlight level after ABM reduction,  Don't allow below 1%
2158          * 0xFFFF x 0.01 = 0x28F
2159          */
2160         params.min_abm_backlight = 0x28F;
2161         /* In the case where abm is implemented on dmcub,
2162         * dmcu object will be null.
2163         * ABM 2.4 and up are implemented on dmcub.
2164         */
2165         if (dmcu) {
2166                 if (!dmcu_load_iram(dmcu, params))
2167                         return -EINVAL;
2168         } else if (adev->dm.dc->ctx->dmub_srv) {
2169                 struct dc_link *edp_links[MAX_NUM_EDP];
2170                 int edp_num;
2171
2172                 get_edp_links(adev->dm.dc, edp_links, &edp_num);
2173                 for (i = 0; i < edp_num; i++) {
2174                         if (!dmub_init_abm_config(adev->dm.dc->res_pool, params, i))
2175                                 return -EINVAL;
2176                 }
2177         }
2178
2179         return detect_mst_link_for_all_connectors(adev_to_drm(adev));
2180 }
2181
2182 static void s3_handle_mst(struct drm_device *dev, bool suspend)
2183 {
2184         struct amdgpu_dm_connector *aconnector;
2185         struct drm_connector *connector;
2186         struct drm_connector_list_iter iter;
2187         struct drm_dp_mst_topology_mgr *mgr;
2188         int ret;
2189         bool need_hotplug = false;
2190
2191         drm_connector_list_iter_begin(dev, &iter);
2192         drm_for_each_connector_iter(connector, &iter) {
2193                 aconnector = to_amdgpu_dm_connector(connector);
2194                 if (aconnector->dc_link->type != dc_connection_mst_branch ||
2195                     aconnector->mst_port)
2196                         continue;
2197
2198                 mgr = &aconnector->mst_mgr;
2199
2200                 if (suspend) {
2201                         drm_dp_mst_topology_mgr_suspend(mgr);
2202                 } else {
2203                         ret = drm_dp_mst_topology_mgr_resume(mgr, true);
2204                         if (ret < 0) {
2205                                 dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,
2206                                         aconnector->dc_link);
2207                                 need_hotplug = true;
2208                         }
2209                 }
2210         }
2211         drm_connector_list_iter_end(&iter);
2212
2213         if (need_hotplug)
2214                 drm_kms_helper_hotplug_event(dev);
2215 }
2216
2217 static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev)
2218 {
2219         int ret = 0;
2220
2221         /* This interface is for dGPU Navi1x.Linux dc-pplib interface depends
2222          * on window driver dc implementation.
2223          * For Navi1x, clock settings of dcn watermarks are fixed. the settings
2224          * should be passed to smu during boot up and resume from s3.
2225          * boot up: dc calculate dcn watermark clock settings within dc_create,
2226          * dcn20_resource_construct
2227          * then call pplib functions below to pass the settings to smu:
2228          * smu_set_watermarks_for_clock_ranges
2229          * smu_set_watermarks_table
2230          * navi10_set_watermarks_table
2231          * smu_write_watermarks_table
2232          *
2233          * For Renoir, clock settings of dcn watermark are also fixed values.
2234          * dc has implemented different flow for window driver:
2235          * dc_hardware_init / dc_set_power_state
2236          * dcn10_init_hw
2237          * notify_wm_ranges
2238          * set_wm_ranges
2239          * -- Linux
2240          * smu_set_watermarks_for_clock_ranges
2241          * renoir_set_watermarks_table
2242          * smu_write_watermarks_table
2243          *
2244          * For Linux,
2245          * dc_hardware_init -> amdgpu_dm_init
2246          * dc_set_power_state --> dm_resume
2247          *
2248          * therefore, this function apply to navi10/12/14 but not Renoir
2249          * *
2250          */
2251         switch (adev->ip_versions[DCE_HWIP][0]) {
2252         case IP_VERSION(2, 0, 2):
2253         case IP_VERSION(2, 0, 0):
2254                 break;
2255         default:
2256                 return 0;
2257         }
2258
2259         ret = amdgpu_dpm_write_watermarks_table(adev);
2260         if (ret) {
2261                 DRM_ERROR("Failed to update WMTABLE!\n");
2262                 return ret;
2263         }
2264
2265         return 0;
2266 }
2267
2268 /**
2269  * dm_hw_init() - Initialize DC device
2270  * @handle: The base driver device containing the amdgpu_dm device.
2271  *
2272  * Initialize the &struct amdgpu_display_manager device. This involves calling
2273  * the initializers of each DM component, then populating the struct with them.
2274  *
2275  * Although the function implies hardware initialization, both hardware and
2276  * software are initialized here. Splitting them out to their relevant init
2277  * hooks is a future TODO item.
2278  *
2279  * Some notable things that are initialized here:
2280  *
2281  * - Display Core, both software and hardware
2282  * - DC modules that we need (freesync and color management)
2283  * - DRM software states
2284  * - Interrupt sources and handlers
2285  * - Vblank support
2286  * - Debug FS entries, if enabled
2287  */
2288 static int dm_hw_init(void *handle)
2289 {
2290         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2291         /* Create DAL display manager */
2292         amdgpu_dm_init(adev);
2293         amdgpu_dm_hpd_init(adev);
2294
2295         return 0;
2296 }
2297
2298 /**
2299  * dm_hw_fini() - Teardown DC device
2300  * @handle: The base driver device containing the amdgpu_dm device.
2301  *
2302  * Teardown components within &struct amdgpu_display_manager that require
2303  * cleanup. This involves cleaning up the DRM device, DC, and any modules that
2304  * were loaded. Also flush IRQ workqueues and disable them.
2305  */
2306 static int dm_hw_fini(void *handle)
2307 {
2308         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2309
2310         amdgpu_dm_hpd_fini(adev);
2311
2312         amdgpu_dm_irq_fini(adev);
2313         amdgpu_dm_fini(adev);
2314         return 0;
2315 }
2316
2317
2318 static void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev,
2319                                  struct dc_state *state, bool enable)
2320 {
2321         enum dc_irq_source irq_source;
2322         struct amdgpu_crtc *acrtc;
2323         int rc = -EBUSY;
2324         int i = 0;
2325
2326         for (i = 0; i < state->stream_count; i++) {
2327                 acrtc = get_crtc_by_otg_inst(
2328                                 adev, state->stream_status[i].primary_otg_inst);
2329
2330                 if (acrtc && state->stream_status[i].plane_count != 0) {
2331                         irq_source = IRQ_TYPE_PFLIP + acrtc->otg_inst;
2332                         rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
2333                         DRM_DEBUG_VBL("crtc %d - vupdate irq %sabling: r=%d\n",
2334                                       acrtc->crtc_id, enable ? "en" : "dis", rc);
2335                         if (rc)
2336                                 DRM_WARN("Failed to %s pflip interrupts\n",
2337                                          enable ? "enable" : "disable");
2338
2339                         if (enable) {
2340                                 rc = dm_enable_vblank(&acrtc->base);
2341                                 if (rc)
2342                                         DRM_WARN("Failed to enable vblank interrupts\n");
2343                         } else {
2344                                 dm_disable_vblank(&acrtc->base);
2345                         }
2346
2347                 }
2348         }
2349
2350 }
2351
2352 static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc)
2353 {
2354         struct dc_state *context = NULL;
2355         enum dc_status res = DC_ERROR_UNEXPECTED;
2356         int i;
2357         struct dc_stream_state *del_streams[MAX_PIPES];
2358         int del_streams_count = 0;
2359
2360         memset(del_streams, 0, sizeof(del_streams));
2361
2362         context = dc_create_state(dc);
2363         if (context == NULL)
2364                 goto context_alloc_fail;
2365
2366         dc_resource_state_copy_construct_current(dc, context);
2367
2368         /* First remove from context all streams */
2369         for (i = 0; i < context->stream_count; i++) {
2370                 struct dc_stream_state *stream = context->streams[i];
2371
2372                 del_streams[del_streams_count++] = stream;
2373         }
2374
2375         /* Remove all planes for removed streams and then remove the streams */
2376         for (i = 0; i < del_streams_count; i++) {
2377                 if (!dc_rem_all_planes_for_stream(dc, del_streams[i], context)) {
2378                         res = DC_FAIL_DETACH_SURFACES;
2379                         goto fail;
2380                 }
2381
2382                 res = dc_remove_stream_from_ctx(dc, context, del_streams[i]);
2383                 if (res != DC_OK)
2384                         goto fail;
2385         }
2386
2387         res = dc_commit_state(dc, context);
2388
2389 fail:
2390         dc_release_state(context);
2391
2392 context_alloc_fail:
2393         return res;
2394 }
2395
2396 static void hpd_rx_irq_work_suspend(struct amdgpu_display_manager *dm)
2397 {
2398         int i;
2399
2400         if (dm->hpd_rx_offload_wq) {
2401                 for (i = 0; i < dm->dc->caps.max_links; i++)
2402                         flush_workqueue(dm->hpd_rx_offload_wq[i].wq);
2403         }
2404 }
2405
2406 static int dm_suspend(void *handle)
2407 {
2408         struct amdgpu_device *adev = handle;
2409         struct amdgpu_display_manager *dm = &adev->dm;
2410         int ret = 0;
2411
2412         if (amdgpu_in_reset(adev)) {
2413                 mutex_lock(&dm->dc_lock);
2414
2415                 dc_allow_idle_optimizations(adev->dm.dc, false);
2416
2417                 dm->cached_dc_state = dc_copy_state(dm->dc->current_state);
2418
2419                 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false);
2420
2421                 amdgpu_dm_commit_zero_streams(dm->dc);
2422
2423                 amdgpu_dm_irq_suspend(adev);
2424
2425                 hpd_rx_irq_work_suspend(dm);
2426
2427                 return ret;
2428         }
2429
2430         WARN_ON(adev->dm.cached_state);
2431         adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev));
2432
2433         s3_handle_mst(adev_to_drm(adev), true);
2434
2435         amdgpu_dm_irq_suspend(adev);
2436
2437         hpd_rx_irq_work_suspend(dm);
2438
2439         dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
2440
2441         return 0;
2442 }
2443
2444 struct amdgpu_dm_connector *
2445 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
2446                                              struct drm_crtc *crtc)
2447 {
2448         uint32_t i;
2449         struct drm_connector_state *new_con_state;
2450         struct drm_connector *connector;
2451         struct drm_crtc *crtc_from_state;
2452
2453         for_each_new_connector_in_state(state, connector, new_con_state, i) {
2454                 crtc_from_state = new_con_state->crtc;
2455
2456                 if (crtc_from_state == crtc)
2457                         return to_amdgpu_dm_connector(connector);
2458         }
2459
2460         return NULL;
2461 }
2462
2463 static void emulated_link_detect(struct dc_link *link)
2464 {
2465         struct dc_sink_init_data sink_init_data = { 0 };
2466         struct display_sink_capability sink_caps = { 0 };
2467         enum dc_edid_status edid_status;
2468         struct dc_context *dc_ctx = link->ctx;
2469         struct dc_sink *sink = NULL;
2470         struct dc_sink *prev_sink = NULL;
2471
2472         link->type = dc_connection_none;
2473         prev_sink = link->local_sink;
2474
2475         if (prev_sink)
2476                 dc_sink_release(prev_sink);
2477
2478         switch (link->connector_signal) {
2479         case SIGNAL_TYPE_HDMI_TYPE_A: {
2480                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2481                 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
2482                 break;
2483         }
2484
2485         case SIGNAL_TYPE_DVI_SINGLE_LINK: {
2486                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2487                 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
2488                 break;
2489         }
2490
2491         case SIGNAL_TYPE_DVI_DUAL_LINK: {
2492                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2493                 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
2494                 break;
2495         }
2496
2497         case SIGNAL_TYPE_LVDS: {
2498                 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
2499                 sink_caps.signal = SIGNAL_TYPE_LVDS;
2500                 break;
2501         }
2502
2503         case SIGNAL_TYPE_EDP: {
2504                 sink_caps.transaction_type =
2505                         DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
2506                 sink_caps.signal = SIGNAL_TYPE_EDP;
2507                 break;
2508         }
2509
2510         case SIGNAL_TYPE_DISPLAY_PORT: {
2511                 sink_caps.transaction_type =
2512                         DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
2513                 sink_caps.signal = SIGNAL_TYPE_VIRTUAL;
2514                 break;
2515         }
2516
2517         default:
2518                 DC_ERROR("Invalid connector type! signal:%d\n",
2519                         link->connector_signal);
2520                 return;
2521         }
2522
2523         sink_init_data.link = link;
2524         sink_init_data.sink_signal = sink_caps.signal;
2525
2526         sink = dc_sink_create(&sink_init_data);
2527         if (!sink) {
2528                 DC_ERROR("Failed to create sink!\n");
2529                 return;
2530         }
2531
2532         /* dc_sink_create returns a new reference */
2533         link->local_sink = sink;
2534
2535         edid_status = dm_helpers_read_local_edid(
2536                         link->ctx,
2537                         link,
2538                         sink);
2539
2540         if (edid_status != EDID_OK)
2541                 DC_ERROR("Failed to read EDID");
2542
2543 }
2544
2545 static void dm_gpureset_commit_state(struct dc_state *dc_state,
2546                                      struct amdgpu_display_manager *dm)
2547 {
2548         struct {
2549                 struct dc_surface_update surface_updates[MAX_SURFACES];
2550                 struct dc_plane_info plane_infos[MAX_SURFACES];
2551                 struct dc_scaling_info scaling_infos[MAX_SURFACES];
2552                 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
2553                 struct dc_stream_update stream_update;
2554         } * bundle;
2555         int k, m;
2556
2557         bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
2558
2559         if (!bundle) {
2560                 dm_error("Failed to allocate update bundle\n");
2561                 goto cleanup;
2562         }
2563
2564         for (k = 0; k < dc_state->stream_count; k++) {
2565                 bundle->stream_update.stream = dc_state->streams[k];
2566
2567                 for (m = 0; m < dc_state->stream_status->plane_count; m++) {
2568                         bundle->surface_updates[m].surface =
2569                                 dc_state->stream_status->plane_states[m];
2570                         bundle->surface_updates[m].surface->force_full_update =
2571                                 true;
2572                 }
2573                 dc_commit_updates_for_stream(
2574                         dm->dc, bundle->surface_updates,
2575                         dc_state->stream_status->plane_count,
2576                         dc_state->streams[k], &bundle->stream_update, dc_state);
2577         }
2578
2579 cleanup:
2580         kfree(bundle);
2581
2582         return;
2583 }
2584
2585 static int dm_resume(void *handle)
2586 {
2587         struct amdgpu_device *adev = handle;
2588         struct drm_device *ddev = adev_to_drm(adev);
2589         struct amdgpu_display_manager *dm = &adev->dm;
2590         struct amdgpu_dm_connector *aconnector;
2591         struct drm_connector *connector;
2592         struct drm_connector_list_iter iter;
2593         struct drm_crtc *crtc;
2594         struct drm_crtc_state *new_crtc_state;
2595         struct dm_crtc_state *dm_new_crtc_state;
2596         struct drm_plane *plane;
2597         struct drm_plane_state *new_plane_state;
2598         struct dm_plane_state *dm_new_plane_state;
2599         struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state);
2600         enum dc_connection_type new_connection_type = dc_connection_none;
2601         struct dc_state *dc_state;
2602         int i, r, j;
2603
2604         if (amdgpu_in_reset(adev)) {
2605                 dc_state = dm->cached_dc_state;
2606
2607                 /*
2608                  * The dc->current_state is backed up into dm->cached_dc_state
2609                  * before we commit 0 streams.
2610                  *
2611                  * DC will clear link encoder assignments on the real state
2612                  * but the changes won't propagate over to the copy we made
2613                  * before the 0 streams commit.
2614                  *
2615                  * DC expects that link encoder assignments are *not* valid
2616                  * when committing a state, so as a workaround we can copy
2617                  * off of the current state.
2618                  *
2619                  * We lose the previous assignments, but we had already
2620                  * commit 0 streams anyway.
2621                  */
2622                 link_enc_cfg_copy(adev->dm.dc->current_state, dc_state);
2623
2624                 r = dm_dmub_hw_init(adev);
2625                 if (r)
2626                         DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r);
2627
2628                 dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
2629                 dc_resume(dm->dc);
2630
2631                 amdgpu_dm_irq_resume_early(adev);
2632
2633                 for (i = 0; i < dc_state->stream_count; i++) {
2634                         dc_state->streams[i]->mode_changed = true;
2635                         for (j = 0; j < dc_state->stream_status[i].plane_count; j++) {
2636                                 dc_state->stream_status[i].plane_states[j]->update_flags.raw
2637                                         = 0xffffffff;
2638                         }
2639                 }
2640
2641                 if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
2642                         amdgpu_dm_outbox_init(adev);
2643                         dc_enable_dmub_outbox(adev->dm.dc);
2644                 }
2645
2646                 WARN_ON(!dc_commit_state(dm->dc, dc_state));
2647
2648                 dm_gpureset_commit_state(dm->cached_dc_state, dm);
2649
2650                 dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, true);
2651
2652                 dc_release_state(dm->cached_dc_state);
2653                 dm->cached_dc_state = NULL;
2654
2655                 amdgpu_dm_irq_resume_late(adev);
2656
2657                 mutex_unlock(&dm->dc_lock);
2658
2659                 return 0;
2660         }
2661         /* Recreate dc_state - DC invalidates it when setting power state to S3. */
2662         dc_release_state(dm_state->context);
2663         dm_state->context = dc_create_state(dm->dc);
2664         /* TODO: Remove dc_state->dccg, use dc->dccg directly. */
2665         dc_resource_state_construct(dm->dc, dm_state->context);
2666
2667         /* Before powering on DC we need to re-initialize DMUB. */
2668         dm_dmub_hw_resume(adev);
2669
2670         /* Re-enable outbox interrupts for DPIA. */
2671         if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
2672                 amdgpu_dm_outbox_init(adev);
2673                 dc_enable_dmub_outbox(adev->dm.dc);
2674         }
2675
2676         /* power on hardware */
2677         dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
2678
2679         /* program HPD filter */
2680         dc_resume(dm->dc);
2681
2682         /*
2683          * early enable HPD Rx IRQ, should be done before set mode as short
2684          * pulse interrupts are used for MST
2685          */
2686         amdgpu_dm_irq_resume_early(adev);
2687
2688         /* On resume we need to rewrite the MSTM control bits to enable MST*/
2689         s3_handle_mst(ddev, false);
2690
2691         /* Do detection*/
2692         drm_connector_list_iter_begin(ddev, &iter);
2693         drm_for_each_connector_iter(connector, &iter) {
2694                 aconnector = to_amdgpu_dm_connector(connector);
2695
2696                 /*
2697                  * this is the case when traversing through already created
2698                  * MST connectors, should be skipped
2699                  */
2700                 if (aconnector->dc_link &&
2701                     aconnector->dc_link->type == dc_connection_mst_branch)
2702                         continue;
2703
2704                 mutex_lock(&aconnector->hpd_lock);
2705                 if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type))
2706                         DRM_ERROR("KMS: Failed to detect connector\n");
2707
2708                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
2709                         emulated_link_detect(aconnector->dc_link);
2710                 } else {
2711                         mutex_lock(&dm->dc_lock);
2712                         dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
2713                         mutex_unlock(&dm->dc_lock);
2714                 }
2715
2716                 if (aconnector->fake_enable && aconnector->dc_link->local_sink)
2717                         aconnector->fake_enable = false;
2718
2719                 if (aconnector->dc_sink)
2720                         dc_sink_release(aconnector->dc_sink);
2721                 aconnector->dc_sink = NULL;
2722                 amdgpu_dm_update_connector_after_detect(aconnector);
2723                 mutex_unlock(&aconnector->hpd_lock);
2724         }
2725         drm_connector_list_iter_end(&iter);
2726
2727         /* Force mode set in atomic commit */
2728         for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)
2729                 new_crtc_state->active_changed = true;
2730
2731         /*
2732          * atomic_check is expected to create the dc states. We need to release
2733          * them here, since they were duplicated as part of the suspend
2734          * procedure.
2735          */
2736         for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {
2737                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
2738                 if (dm_new_crtc_state->stream) {
2739                         WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
2740                         dc_stream_release(dm_new_crtc_state->stream);
2741                         dm_new_crtc_state->stream = NULL;
2742                 }
2743         }
2744
2745         for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) {
2746                 dm_new_plane_state = to_dm_plane_state(new_plane_state);
2747                 if (dm_new_plane_state->dc_state) {
2748                         WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
2749                         dc_plane_state_release(dm_new_plane_state->dc_state);
2750                         dm_new_plane_state->dc_state = NULL;
2751                 }
2752         }
2753
2754         drm_atomic_helper_resume(ddev, dm->cached_state);
2755
2756         dm->cached_state = NULL;
2757
2758         amdgpu_dm_irq_resume_late(adev);
2759
2760         amdgpu_dm_smu_write_watermarks_table(adev);
2761
2762         return 0;
2763 }
2764
2765 /**
2766  * DOC: DM Lifecycle
2767  *
2768  * DM (and consequently DC) is registered in the amdgpu base driver as a IP
2769  * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to
2770  * the base driver's device list to be initialized and torn down accordingly.
2771  *
2772  * The functions to do so are provided as hooks in &struct amd_ip_funcs.
2773  */
2774
2775 static const struct amd_ip_funcs amdgpu_dm_funcs = {
2776         .name = "dm",
2777         .early_init = dm_early_init,
2778         .late_init = dm_late_init,
2779         .sw_init = dm_sw_init,
2780         .sw_fini = dm_sw_fini,
2781         .early_fini = amdgpu_dm_early_fini,
2782         .hw_init = dm_hw_init,
2783         .hw_fini = dm_hw_fini,
2784         .suspend = dm_suspend,
2785         .resume = dm_resume,
2786         .is_idle = dm_is_idle,
2787         .wait_for_idle = dm_wait_for_idle,
2788         .check_soft_reset = dm_check_soft_reset,
2789         .soft_reset = dm_soft_reset,
2790         .set_clockgating_state = dm_set_clockgating_state,
2791         .set_powergating_state = dm_set_powergating_state,
2792 };
2793
2794 const struct amdgpu_ip_block_version dm_ip_block =
2795 {
2796         .type = AMD_IP_BLOCK_TYPE_DCE,
2797         .major = 1,
2798         .minor = 0,
2799         .rev = 0,
2800         .funcs = &amdgpu_dm_funcs,
2801 };
2802
2803
2804 /**
2805  * DOC: atomic
2806  *
2807  * *WIP*
2808  */
2809
2810 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
2811         .fb_create = amdgpu_display_user_framebuffer_create,
2812         .get_format_info = amd_get_format_info,
2813         .output_poll_changed = drm_fb_helper_output_poll_changed,
2814         .atomic_check = amdgpu_dm_atomic_check,
2815         .atomic_commit = drm_atomic_helper_commit,
2816 };
2817
2818 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
2819         .atomic_commit_tail = amdgpu_dm_atomic_commit_tail,
2820         .atomic_commit_setup = drm_dp_mst_atomic_setup_commit,
2821 };
2822
2823 static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector)
2824 {
2825         struct amdgpu_dm_backlight_caps *caps;
2826         struct amdgpu_display_manager *dm;
2827         struct drm_connector *conn_base;
2828         struct amdgpu_device *adev;
2829         struct dc_link *link = NULL;
2830         struct drm_luminance_range_info *luminance_range;
2831         int i;
2832
2833         if (!aconnector || !aconnector->dc_link)
2834                 return;
2835
2836         link = aconnector->dc_link;
2837         if (link->connector_signal != SIGNAL_TYPE_EDP)
2838                 return;
2839
2840         conn_base = &aconnector->base;
2841         adev = drm_to_adev(conn_base->dev);
2842         dm = &adev->dm;
2843         for (i = 0; i < dm->num_of_edps; i++) {
2844                 if (link == dm->backlight_link[i])
2845                         break;
2846         }
2847         if (i >= dm->num_of_edps)
2848                 return;
2849         caps = &dm->backlight_caps[i];
2850         caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps;
2851         caps->aux_support = false;
2852
2853         if (caps->ext_caps->bits.oled == 1 /*||
2854             caps->ext_caps->bits.sdr_aux_backlight_control == 1 ||
2855             caps->ext_caps->bits.hdr_aux_backlight_control == 1*/)
2856                 caps->aux_support = true;
2857
2858         if (amdgpu_backlight == 0)
2859                 caps->aux_support = false;
2860         else if (amdgpu_backlight == 1)
2861                 caps->aux_support = true;
2862
2863         luminance_range = &conn_base->display_info.luminance_range;
2864         caps->aux_min_input_signal = luminance_range->min_luminance;
2865         caps->aux_max_input_signal = luminance_range->max_luminance;
2866 }
2867
2868 void amdgpu_dm_update_connector_after_detect(
2869                 struct amdgpu_dm_connector *aconnector)
2870 {
2871         struct drm_connector *connector = &aconnector->base;
2872         struct drm_device *dev = connector->dev;
2873         struct dc_sink *sink;
2874
2875         /* MST handled by drm_mst framework */
2876         if (aconnector->mst_mgr.mst_state == true)
2877                 return;
2878
2879         sink = aconnector->dc_link->local_sink;
2880         if (sink)
2881                 dc_sink_retain(sink);
2882
2883         /*
2884          * Edid mgmt connector gets first update only in mode_valid hook and then
2885          * the connector sink is set to either fake or physical sink depends on link status.
2886          * Skip if already done during boot.
2887          */
2888         if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
2889                         && aconnector->dc_em_sink) {
2890
2891                 /*
2892                  * For S3 resume with headless use eml_sink to fake stream
2893                  * because on resume connector->sink is set to NULL
2894                  */
2895                 mutex_lock(&dev->mode_config.mutex);
2896
2897                 if (sink) {
2898                         if (aconnector->dc_sink) {
2899                                 amdgpu_dm_update_freesync_caps(connector, NULL);
2900                                 /*
2901                                  * retain and release below are used to
2902                                  * bump up refcount for sink because the link doesn't point
2903                                  * to it anymore after disconnect, so on next crtc to connector
2904                                  * reshuffle by UMD we will get into unwanted dc_sink release
2905                                  */
2906                                 dc_sink_release(aconnector->dc_sink);
2907                         }
2908                         aconnector->dc_sink = sink;
2909                         dc_sink_retain(aconnector->dc_sink);
2910                         amdgpu_dm_update_freesync_caps(connector,
2911                                         aconnector->edid);
2912                 } else {
2913                         amdgpu_dm_update_freesync_caps(connector, NULL);
2914                         if (!aconnector->dc_sink) {
2915                                 aconnector->dc_sink = aconnector->dc_em_sink;
2916                                 dc_sink_retain(aconnector->dc_sink);
2917                         }
2918                 }
2919
2920                 mutex_unlock(&dev->mode_config.mutex);
2921
2922                 if (sink)
2923                         dc_sink_release(sink);
2924                 return;
2925         }
2926
2927         /*
2928          * TODO: temporary guard to look for proper fix
2929          * if this sink is MST sink, we should not do anything
2930          */
2931         if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
2932                 dc_sink_release(sink);
2933                 return;
2934         }
2935
2936         if (aconnector->dc_sink == sink) {
2937                 /*
2938                  * We got a DP short pulse (Link Loss, DP CTS, etc...).
2939                  * Do nothing!!
2940                  */
2941                 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
2942                                 aconnector->connector_id);
2943                 if (sink)
2944                         dc_sink_release(sink);
2945                 return;
2946         }
2947
2948         DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
2949                 aconnector->connector_id, aconnector->dc_sink, sink);
2950
2951         mutex_lock(&dev->mode_config.mutex);
2952
2953         /*
2954          * 1. Update status of the drm connector
2955          * 2. Send an event and let userspace tell us what to do
2956          */
2957         if (sink) {
2958                 /*
2959                  * TODO: check if we still need the S3 mode update workaround.
2960                  * If yes, put it here.
2961                  */
2962                 if (aconnector->dc_sink) {
2963                         amdgpu_dm_update_freesync_caps(connector, NULL);
2964                         dc_sink_release(aconnector->dc_sink);
2965                 }
2966
2967                 aconnector->dc_sink = sink;
2968                 dc_sink_retain(aconnector->dc_sink);
2969                 if (sink->dc_edid.length == 0) {
2970                         aconnector->edid = NULL;
2971                         if (aconnector->dc_link->aux_mode) {
2972                                 drm_dp_cec_unset_edid(
2973                                         &aconnector->dm_dp_aux.aux);
2974                         }
2975                 } else {
2976                         aconnector->edid =
2977                                 (struct edid *)sink->dc_edid.raw_edid;
2978
2979                         if (aconnector->dc_link->aux_mode)
2980                                 drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,
2981                                                     aconnector->edid);
2982                 }
2983
2984                 drm_connector_update_edid_property(connector, aconnector->edid);
2985                 amdgpu_dm_update_freesync_caps(connector, aconnector->edid);
2986                 update_connector_ext_caps(aconnector);
2987         } else {
2988                 drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
2989                 amdgpu_dm_update_freesync_caps(connector, NULL);
2990                 drm_connector_update_edid_property(connector, NULL);
2991                 aconnector->num_modes = 0;
2992                 dc_sink_release(aconnector->dc_sink);
2993                 aconnector->dc_sink = NULL;
2994                 aconnector->edid = NULL;
2995 #ifdef CONFIG_DRM_AMD_DC_HDCP
2996                 /* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */
2997                 if (connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
2998                         connector->state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
2999 #endif
3000         }
3001
3002         mutex_unlock(&dev->mode_config.mutex);
3003
3004         update_subconnector_property(aconnector);
3005
3006         if (sink)
3007                 dc_sink_release(sink);
3008 }
3009
3010 static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector)
3011 {
3012         struct drm_connector *connector = &aconnector->base;
3013         struct drm_device *dev = connector->dev;
3014         enum dc_connection_type new_connection_type = dc_connection_none;
3015         struct amdgpu_device *adev = drm_to_adev(dev);
3016 #ifdef CONFIG_DRM_AMD_DC_HDCP
3017         struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
3018 #endif
3019         bool ret = false;
3020
3021         if (adev->dm.disable_hpd_irq)
3022                 return;
3023
3024         /*
3025          * In case of failure or MST no need to update connector status or notify the OS
3026          * since (for MST case) MST does this in its own context.
3027          */
3028         mutex_lock(&aconnector->hpd_lock);
3029
3030 #ifdef CONFIG_DRM_AMD_DC_HDCP
3031         if (adev->dm.hdcp_workqueue) {
3032                 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
3033                 dm_con_state->update_hdcp = true;
3034         }
3035 #endif
3036         if (aconnector->fake_enable)
3037                 aconnector->fake_enable = false;
3038
3039         if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type))
3040                 DRM_ERROR("KMS: Failed to detect connector\n");
3041
3042         if (aconnector->base.force && new_connection_type == dc_connection_none) {
3043                 emulated_link_detect(aconnector->dc_link);
3044
3045                 drm_modeset_lock_all(dev);
3046                 dm_restore_drm_connector_state(dev, connector);
3047                 drm_modeset_unlock_all(dev);
3048
3049                 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
3050                         drm_kms_helper_connector_hotplug_event(connector);
3051         } else {
3052                 mutex_lock(&adev->dm.dc_lock);
3053                 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
3054                 mutex_unlock(&adev->dm.dc_lock);
3055                 if (ret) {
3056                         amdgpu_dm_update_connector_after_detect(aconnector);
3057
3058                         drm_modeset_lock_all(dev);
3059                         dm_restore_drm_connector_state(dev, connector);
3060                         drm_modeset_unlock_all(dev);
3061
3062                         if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
3063                                 drm_kms_helper_connector_hotplug_event(connector);
3064                 }
3065         }
3066         mutex_unlock(&aconnector->hpd_lock);
3067
3068 }
3069
3070 static void handle_hpd_irq(void *param)
3071 {
3072         struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
3073
3074         handle_hpd_irq_helper(aconnector);
3075
3076 }
3077
3078 static void dm_handle_mst_sideband_msg(struct amdgpu_dm_connector *aconnector)
3079 {
3080         uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
3081         uint8_t dret;
3082         bool new_irq_handled = false;
3083         int dpcd_addr;
3084         int dpcd_bytes_to_read;
3085
3086         const int max_process_count = 30;
3087         int process_count = 0;
3088
3089         const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
3090
3091         if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
3092                 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
3093                 /* DPCD 0x200 - 0x201 for downstream IRQ */
3094                 dpcd_addr = DP_SINK_COUNT;
3095         } else {
3096                 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
3097                 /* DPCD 0x2002 - 0x2005 for downstream IRQ */
3098                 dpcd_addr = DP_SINK_COUNT_ESI;
3099         }
3100
3101         dret = drm_dp_dpcd_read(
3102                 &aconnector->dm_dp_aux.aux,
3103                 dpcd_addr,
3104                 esi,
3105                 dpcd_bytes_to_read);
3106
3107         while (dret == dpcd_bytes_to_read &&
3108                 process_count < max_process_count) {
3109                 uint8_t retry;
3110                 dret = 0;
3111
3112                 process_count++;
3113
3114                 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3115                 /* handle HPD short pulse irq */
3116                 if (aconnector->mst_mgr.mst_state)
3117                         drm_dp_mst_hpd_irq(
3118                                 &aconnector->mst_mgr,
3119                                 esi,
3120                                 &new_irq_handled);
3121
3122                 if (new_irq_handled) {
3123                         /* ACK at DPCD to notify down stream */
3124                         const int ack_dpcd_bytes_to_write =
3125                                 dpcd_bytes_to_read - 1;
3126
3127                         for (retry = 0; retry < 3; retry++) {
3128                                 uint8_t wret;
3129
3130                                 wret = drm_dp_dpcd_write(
3131                                         &aconnector->dm_dp_aux.aux,
3132                                         dpcd_addr + 1,
3133                                         &esi[1],
3134                                         ack_dpcd_bytes_to_write);
3135                                 if (wret == ack_dpcd_bytes_to_write)
3136                                         break;
3137                         }
3138
3139                         /* check if there is new irq to be handled */
3140                         dret = drm_dp_dpcd_read(
3141                                 &aconnector->dm_dp_aux.aux,
3142                                 dpcd_addr,
3143                                 esi,
3144                                 dpcd_bytes_to_read);
3145
3146                         new_irq_handled = false;
3147                 } else {
3148                         break;
3149                 }
3150         }
3151
3152         if (process_count == max_process_count)
3153                 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
3154 }
3155
3156 static void schedule_hpd_rx_offload_work(struct hpd_rx_irq_offload_work_queue *offload_wq,
3157                                                         union hpd_irq_data hpd_irq_data)
3158 {
3159         struct hpd_rx_irq_offload_work *offload_work =
3160                                 kzalloc(sizeof(*offload_work), GFP_KERNEL);
3161
3162         if (!offload_work) {
3163                 DRM_ERROR("Failed to allocate hpd_rx_irq_offload_work.\n");
3164                 return;
3165         }
3166
3167         INIT_WORK(&offload_work->work, dm_handle_hpd_rx_offload_work);
3168         offload_work->data = hpd_irq_data;
3169         offload_work->offload_wq = offload_wq;
3170
3171         queue_work(offload_wq->wq, &offload_work->work);
3172         DRM_DEBUG_KMS("queue work to handle hpd_rx offload work");
3173 }
3174
3175 static void handle_hpd_rx_irq(void *param)
3176 {
3177         struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
3178         struct drm_connector *connector = &aconnector->base;
3179         struct drm_device *dev = connector->dev;
3180         struct dc_link *dc_link = aconnector->dc_link;
3181         bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
3182         bool result = false;
3183         enum dc_connection_type new_connection_type = dc_connection_none;
3184         struct amdgpu_device *adev = drm_to_adev(dev);
3185         union hpd_irq_data hpd_irq_data;
3186         bool link_loss = false;
3187         bool has_left_work = false;
3188         int idx = aconnector->base.index;
3189         struct hpd_rx_irq_offload_work_queue *offload_wq = &adev->dm.hpd_rx_offload_wq[idx];
3190
3191         memset(&hpd_irq_data, 0, sizeof(hpd_irq_data));
3192
3193         if (adev->dm.disable_hpd_irq)
3194                 return;
3195
3196         /*
3197          * TODO:Temporary add mutex to protect hpd interrupt not have a gpio
3198          * conflict, after implement i2c helper, this mutex should be
3199          * retired.
3200          */
3201         mutex_lock(&aconnector->hpd_lock);
3202
3203         result = dc_link_handle_hpd_rx_irq(dc_link, &hpd_irq_data,
3204                                                 &link_loss, true, &has_left_work);
3205
3206         if (!has_left_work)
3207                 goto out;
3208
3209         if (hpd_irq_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
3210                 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3211                 goto out;
3212         }
3213
3214         if (dc_link_dp_allow_hpd_rx_irq(dc_link)) {
3215                 if (hpd_irq_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY ||
3216                         hpd_irq_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) {
3217                         dm_handle_mst_sideband_msg(aconnector);
3218                         goto out;
3219                 }
3220
3221                 if (link_loss) {
3222                         bool skip = false;
3223
3224                         spin_lock(&offload_wq->offload_lock);
3225                         skip = offload_wq->is_handling_link_loss;
3226
3227                         if (!skip)
3228                                 offload_wq->is_handling_link_loss = true;
3229
3230                         spin_unlock(&offload_wq->offload_lock);
3231
3232                         if (!skip)
3233                                 schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
3234
3235                         goto out;
3236                 }
3237         }
3238
3239 out:
3240         if (result && !is_mst_root_connector) {
3241                 /* Downstream Port status changed. */
3242                 if (!dc_link_detect_sink(dc_link, &new_connection_type))
3243                         DRM_ERROR("KMS: Failed to detect connector\n");
3244
3245                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
3246                         emulated_link_detect(dc_link);
3247
3248                         if (aconnector->fake_enable)
3249                                 aconnector->fake_enable = false;
3250
3251                         amdgpu_dm_update_connector_after_detect(aconnector);
3252
3253
3254                         drm_modeset_lock_all(dev);
3255                         dm_restore_drm_connector_state(dev, connector);
3256                         drm_modeset_unlock_all(dev);
3257
3258                         drm_kms_helper_connector_hotplug_event(connector);
3259                 } else {
3260                         bool ret = false;
3261
3262                         mutex_lock(&adev->dm.dc_lock);
3263                         ret = dc_link_detect(dc_link, DETECT_REASON_HPDRX);
3264                         mutex_unlock(&adev->dm.dc_lock);
3265
3266                         if (ret) {
3267                                 if (aconnector->fake_enable)
3268                                         aconnector->fake_enable = false;
3269
3270                                 amdgpu_dm_update_connector_after_detect(aconnector);
3271
3272                                 drm_modeset_lock_all(dev);
3273                                 dm_restore_drm_connector_state(dev, connector);
3274                                 drm_modeset_unlock_all(dev);
3275
3276                                 drm_kms_helper_connector_hotplug_event(connector);
3277                         }
3278                 }
3279         }
3280 #ifdef CONFIG_DRM_AMD_DC_HDCP
3281         if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ) {
3282                 if (adev->dm.hdcp_workqueue)
3283                         hdcp_handle_cpirq(adev->dm.hdcp_workqueue,  aconnector->base.index);
3284         }
3285 #endif
3286
3287         if (dc_link->type != dc_connection_mst_branch)
3288                 drm_dp_cec_irq(&aconnector->dm_dp_aux.aux);
3289
3290         mutex_unlock(&aconnector->hpd_lock);
3291 }
3292
3293 static void register_hpd_handlers(struct amdgpu_device *adev)
3294 {
3295         struct drm_device *dev = adev_to_drm(adev);
3296         struct drm_connector *connector;
3297         struct amdgpu_dm_connector *aconnector;
3298         const struct dc_link *dc_link;
3299         struct dc_interrupt_params int_params = {0};
3300
3301         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3302         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3303
3304         list_for_each_entry(connector,
3305                         &dev->mode_config.connector_list, head) {
3306
3307                 aconnector = to_amdgpu_dm_connector(connector);
3308                 dc_link = aconnector->dc_link;
3309
3310                 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
3311                         int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3312                         int_params.irq_source = dc_link->irq_source_hpd;
3313
3314                         amdgpu_dm_irq_register_interrupt(adev, &int_params,
3315                                         handle_hpd_irq,
3316                                         (void *) aconnector);
3317                 }
3318
3319                 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
3320
3321                         /* Also register for DP short pulse (hpd_rx). */
3322                         int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3323                         int_params.irq_source = dc_link->irq_source_hpd_rx;
3324
3325                         amdgpu_dm_irq_register_interrupt(adev, &int_params,
3326                                         handle_hpd_rx_irq,
3327                                         (void *) aconnector);
3328
3329                         if (adev->dm.hpd_rx_offload_wq)
3330                                 adev->dm.hpd_rx_offload_wq[connector->index].aconnector =
3331                                         aconnector;
3332                 }
3333         }
3334 }
3335
3336 #if defined(CONFIG_DRM_AMD_DC_SI)
3337 /* Register IRQ sources and initialize IRQ callbacks */
3338 static int dce60_register_irq_handlers(struct amdgpu_device *adev)
3339 {
3340         struct dc *dc = adev->dm.dc;
3341         struct common_irq_params *c_irq_params;
3342         struct dc_interrupt_params int_params = {0};
3343         int r;
3344         int i;
3345         unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
3346
3347         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3348         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3349
3350         /*
3351          * Actions of amdgpu_irq_add_id():
3352          * 1. Register a set() function with base driver.
3353          *    Base driver will call set() function to enable/disable an
3354          *    interrupt in DC hardware.
3355          * 2. Register amdgpu_dm_irq_handler().
3356          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3357          *    coming from DC hardware.
3358          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3359          *    for acknowledging and handling. */
3360
3361         /* Use VBLANK interrupt */
3362         for (i = 0; i < adev->mode_info.num_crtc; i++) {
3363                 r = amdgpu_irq_add_id(adev, client_id, i+1 , &adev->crtc_irq);
3364                 if (r) {
3365                         DRM_ERROR("Failed to add crtc irq id!\n");
3366                         return r;
3367                 }
3368
3369                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3370                 int_params.irq_source =
3371                         dc_interrupt_to_irq_source(dc, i+1 , 0);
3372
3373                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3374
3375                 c_irq_params->adev = adev;
3376                 c_irq_params->irq_src = int_params.irq_source;
3377
3378                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3379                                 dm_crtc_high_irq, c_irq_params);
3380         }
3381
3382         /* Use GRPH_PFLIP interrupt */
3383         for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
3384                         i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
3385                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
3386                 if (r) {
3387                         DRM_ERROR("Failed to add page flip irq id!\n");
3388                         return r;
3389                 }
3390
3391                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3392                 int_params.irq_source =
3393                         dc_interrupt_to_irq_source(dc, i, 0);
3394
3395                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3396
3397                 c_irq_params->adev = adev;
3398                 c_irq_params->irq_src = int_params.irq_source;
3399
3400                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3401                                 dm_pflip_high_irq, c_irq_params);
3402
3403         }
3404
3405         /* HPD */
3406         r = amdgpu_irq_add_id(adev, client_id,
3407                         VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
3408         if (r) {
3409                 DRM_ERROR("Failed to add hpd irq id!\n");
3410                 return r;
3411         }
3412
3413         register_hpd_handlers(adev);
3414
3415         return 0;
3416 }
3417 #endif
3418
3419 /* Register IRQ sources and initialize IRQ callbacks */
3420 static int dce110_register_irq_handlers(struct amdgpu_device *adev)
3421 {
3422         struct dc *dc = adev->dm.dc;
3423         struct common_irq_params *c_irq_params;
3424         struct dc_interrupt_params int_params = {0};
3425         int r;
3426         int i;
3427         unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
3428
3429         if (adev->family >= AMDGPU_FAMILY_AI)
3430                 client_id = SOC15_IH_CLIENTID_DCE;
3431
3432         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3433         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3434
3435         /*
3436          * Actions of amdgpu_irq_add_id():
3437          * 1. Register a set() function with base driver.
3438          *    Base driver will call set() function to enable/disable an
3439          *    interrupt in DC hardware.
3440          * 2. Register amdgpu_dm_irq_handler().
3441          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3442          *    coming from DC hardware.
3443          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3444          *    for acknowledging and handling. */
3445
3446         /* Use VBLANK interrupt */
3447         for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
3448                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
3449                 if (r) {
3450                         DRM_ERROR("Failed to add crtc irq id!\n");
3451                         return r;
3452                 }
3453
3454                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3455                 int_params.irq_source =
3456                         dc_interrupt_to_irq_source(dc, i, 0);
3457
3458                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3459
3460                 c_irq_params->adev = adev;
3461                 c_irq_params->irq_src = int_params.irq_source;
3462
3463                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3464                                 dm_crtc_high_irq, c_irq_params);
3465         }
3466
3467         /* Use VUPDATE interrupt */
3468         for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) {
3469                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq);
3470                 if (r) {
3471                         DRM_ERROR("Failed to add vupdate irq id!\n");
3472                         return r;
3473                 }
3474
3475                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3476                 int_params.irq_source =
3477                         dc_interrupt_to_irq_source(dc, i, 0);
3478
3479                 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
3480
3481                 c_irq_params->adev = adev;
3482                 c_irq_params->irq_src = int_params.irq_source;
3483
3484                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3485                                 dm_vupdate_high_irq, c_irq_params);
3486         }
3487
3488         /* Use GRPH_PFLIP interrupt */
3489         for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
3490                         i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
3491                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
3492                 if (r) {
3493                         DRM_ERROR("Failed to add page flip irq id!\n");
3494                         return r;
3495                 }
3496
3497                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3498                 int_params.irq_source =
3499                         dc_interrupt_to_irq_source(dc, i, 0);
3500
3501                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3502
3503                 c_irq_params->adev = adev;
3504                 c_irq_params->irq_src = int_params.irq_source;
3505
3506                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3507                                 dm_pflip_high_irq, c_irq_params);
3508
3509         }
3510
3511         /* HPD */
3512         r = amdgpu_irq_add_id(adev, client_id,
3513                         VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
3514         if (r) {
3515                 DRM_ERROR("Failed to add hpd irq id!\n");
3516                 return r;
3517         }
3518
3519         register_hpd_handlers(adev);
3520
3521         return 0;
3522 }
3523
3524 /* Register IRQ sources and initialize IRQ callbacks */
3525 static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
3526 {
3527         struct dc *dc = adev->dm.dc;
3528         struct common_irq_params *c_irq_params;
3529         struct dc_interrupt_params int_params = {0};
3530         int r;
3531         int i;
3532 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
3533         static const unsigned int vrtl_int_srcid[] = {
3534                 DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL,
3535                 DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL,
3536                 DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL,
3537                 DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL,
3538                 DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL,
3539                 DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL
3540         };
3541 #endif
3542
3543         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3544         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3545
3546         /*
3547          * Actions of amdgpu_irq_add_id():
3548          * 1. Register a set() function with base driver.
3549          *    Base driver will call set() function to enable/disable an
3550          *    interrupt in DC hardware.
3551          * 2. Register amdgpu_dm_irq_handler().
3552          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
3553          *    coming from DC hardware.
3554          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
3555          *    for acknowledging and handling.
3556          */
3557
3558         /* Use VSTARTUP interrupt */
3559         for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
3560                         i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
3561                         i++) {
3562                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);
3563
3564                 if (r) {
3565                         DRM_ERROR("Failed to add crtc irq id!\n");
3566                         return r;
3567                 }
3568
3569                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3570                 int_params.irq_source =
3571                         dc_interrupt_to_irq_source(dc, i, 0);
3572
3573                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
3574
3575                 c_irq_params->adev = adev;
3576                 c_irq_params->irq_src = int_params.irq_source;
3577
3578                 amdgpu_dm_irq_register_interrupt(
3579                         adev, &int_params, dm_crtc_high_irq, c_irq_params);
3580         }
3581
3582         /* Use otg vertical line interrupt */
3583 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
3584         for (i = 0; i <= adev->mode_info.num_crtc - 1; i++) {
3585                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE,
3586                                 vrtl_int_srcid[i], &adev->vline0_irq);
3587
3588                 if (r) {
3589                         DRM_ERROR("Failed to add vline0 irq id!\n");
3590                         return r;
3591                 }
3592
3593                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3594                 int_params.irq_source =
3595                         dc_interrupt_to_irq_source(dc, vrtl_int_srcid[i], 0);
3596
3597                 if (int_params.irq_source == DC_IRQ_SOURCE_INVALID) {
3598                         DRM_ERROR("Failed to register vline0 irq %d!\n", vrtl_int_srcid[i]);
3599                         break;
3600                 }
3601
3602                 c_irq_params = &adev->dm.vline0_params[int_params.irq_source
3603                                         - DC_IRQ_SOURCE_DC1_VLINE0];
3604
3605                 c_irq_params->adev = adev;
3606                 c_irq_params->irq_src = int_params.irq_source;
3607
3608                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3609                                 dm_dcn_vertical_interrupt0_high_irq, c_irq_params);
3610         }
3611 #endif
3612
3613         /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to
3614          * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx
3615          * to trigger at end of each vblank, regardless of state of the lock,
3616          * matching DCE behaviour.
3617          */
3618         for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT;
3619              i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1;
3620              i++) {
3621                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq);
3622
3623                 if (r) {
3624                         DRM_ERROR("Failed to add vupdate irq id!\n");
3625                         return r;
3626                 }
3627
3628                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3629                 int_params.irq_source =
3630                         dc_interrupt_to_irq_source(dc, i, 0);
3631
3632                 c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
3633
3634                 c_irq_params->adev = adev;
3635                 c_irq_params->irq_src = int_params.irq_source;
3636
3637                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3638                                 dm_vupdate_high_irq, c_irq_params);
3639         }
3640
3641         /* Use GRPH_PFLIP interrupt */
3642         for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
3643                         i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + dc->caps.max_otg_num - 1;
3644                         i++) {
3645                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
3646                 if (r) {
3647                         DRM_ERROR("Failed to add page flip irq id!\n");
3648                         return r;
3649                 }
3650
3651                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
3652                 int_params.irq_source =
3653                         dc_interrupt_to_irq_source(dc, i, 0);
3654
3655                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
3656
3657                 c_irq_params->adev = adev;
3658                 c_irq_params->irq_src = int_params.irq_source;
3659
3660                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3661                                 dm_pflip_high_irq, c_irq_params);
3662
3663         }
3664
3665         /* HPD */
3666         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
3667                         &adev->hpd_irq);
3668         if (r) {
3669                 DRM_ERROR("Failed to add hpd irq id!\n");
3670                 return r;
3671         }
3672
3673         register_hpd_handlers(adev);
3674
3675         return 0;
3676 }
3677 /* Register Outbox IRQ sources and initialize IRQ callbacks */
3678 static int register_outbox_irq_handlers(struct amdgpu_device *adev)
3679 {
3680         struct dc *dc = adev->dm.dc;
3681         struct common_irq_params *c_irq_params;
3682         struct dc_interrupt_params int_params = {0};
3683         int r, i;
3684
3685         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
3686         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
3687
3688         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT,
3689                         &adev->dmub_outbox_irq);
3690         if (r) {
3691                 DRM_ERROR("Failed to add outbox irq id!\n");
3692                 return r;
3693         }
3694
3695         if (dc->ctx->dmub_srv) {
3696                 i = DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT;
3697                 int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
3698                 int_params.irq_source =
3699                 dc_interrupt_to_irq_source(dc, i, 0);
3700
3701                 c_irq_params = &adev->dm.dmub_outbox_params[0];
3702
3703                 c_irq_params->adev = adev;
3704                 c_irq_params->irq_src = int_params.irq_source;
3705
3706                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
3707                                 dm_dmub_outbox1_low_irq, c_irq_params);
3708         }
3709
3710         return 0;
3711 }
3712
3713 /*
3714  * Acquires the lock for the atomic state object and returns
3715  * the new atomic state.
3716  *
3717  * This should only be called during atomic check.
3718  */
3719 int dm_atomic_get_state(struct drm_atomic_state *state,
3720                         struct dm_atomic_state **dm_state)
3721 {
3722         struct drm_device *dev = state->dev;
3723         struct amdgpu_device *adev = drm_to_adev(dev);
3724         struct amdgpu_display_manager *dm = &adev->dm;
3725         struct drm_private_state *priv_state;
3726
3727         if (*dm_state)
3728                 return 0;
3729
3730         priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj);
3731         if (IS_ERR(priv_state))
3732                 return PTR_ERR(priv_state);
3733
3734         *dm_state = to_dm_atomic_state(priv_state);
3735
3736         return 0;
3737 }
3738
3739 static struct dm_atomic_state *
3740 dm_atomic_get_new_state(struct drm_atomic_state *state)
3741 {
3742         struct drm_device *dev = state->dev;
3743         struct amdgpu_device *adev = drm_to_adev(dev);
3744         struct amdgpu_display_manager *dm = &adev->dm;
3745         struct drm_private_obj *obj;
3746         struct drm_private_state *new_obj_state;
3747         int i;
3748
3749         for_each_new_private_obj_in_state(state, obj, new_obj_state, i) {
3750                 if (obj->funcs == dm->atomic_obj.funcs)
3751                         return to_dm_atomic_state(new_obj_state);
3752         }
3753
3754         return NULL;
3755 }
3756
3757 static struct drm_private_state *
3758 dm_atomic_duplicate_state(struct drm_private_obj *obj)
3759 {
3760         struct dm_atomic_state *old_state, *new_state;
3761
3762         new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
3763         if (!new_state)
3764                 return NULL;
3765
3766         __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base);
3767
3768         old_state = to_dm_atomic_state(obj->state);
3769
3770         if (old_state && old_state->context)
3771                 new_state->context = dc_copy_state(old_state->context);
3772
3773         if (!new_state->context) {
3774                 kfree(new_state);
3775                 return NULL;
3776         }
3777
3778         return &new_state->base;
3779 }
3780
3781 static void dm_atomic_destroy_state(struct drm_private_obj *obj,
3782                                     struct drm_private_state *state)
3783 {
3784         struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
3785
3786         if (dm_state && dm_state->context)
3787                 dc_release_state(dm_state->context);
3788
3789         kfree(dm_state);
3790 }
3791
3792 static struct drm_private_state_funcs dm_atomic_state_funcs = {
3793         .atomic_duplicate_state = dm_atomic_duplicate_state,
3794         .atomic_destroy_state = dm_atomic_destroy_state,
3795 };
3796
3797 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
3798 {
3799         struct dm_atomic_state *state;
3800         int r;
3801
3802         adev->mode_info.mode_config_initialized = true;
3803
3804         adev_to_drm(adev)->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
3805         adev_to_drm(adev)->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
3806
3807         adev_to_drm(adev)->mode_config.max_width = 16384;
3808         adev_to_drm(adev)->mode_config.max_height = 16384;
3809
3810         adev_to_drm(adev)->mode_config.preferred_depth = 24;
3811         if (adev->asic_type == CHIP_HAWAII)
3812                 /* disable prefer shadow for now due to hibernation issues */
3813                 adev_to_drm(adev)->mode_config.prefer_shadow = 0;
3814         else
3815                 adev_to_drm(adev)->mode_config.prefer_shadow = 1;
3816         /* indicates support for immediate flip */
3817         adev_to_drm(adev)->mode_config.async_page_flip = true;
3818
3819         adev_to_drm(adev)->mode_config.fb_base = adev->gmc.aper_base;
3820
3821         state = kzalloc(sizeof(*state), GFP_KERNEL);
3822         if (!state)
3823                 return -ENOMEM;
3824
3825         state->context = dc_create_state(adev->dm.dc);
3826         if (!state->context) {
3827                 kfree(state);
3828                 return -ENOMEM;
3829         }
3830
3831         dc_resource_state_copy_construct_current(adev->dm.dc, state->context);
3832
3833         drm_atomic_private_obj_init(adev_to_drm(adev),
3834                                     &adev->dm.atomic_obj,
3835                                     &state->base,
3836                                     &dm_atomic_state_funcs);
3837
3838         r = amdgpu_display_modeset_create_props(adev);
3839         if (r) {
3840                 dc_release_state(state->context);
3841                 kfree(state);
3842                 return r;
3843         }
3844
3845         r = amdgpu_dm_audio_init(adev);
3846         if (r) {
3847                 dc_release_state(state->context);
3848                 kfree(state);
3849                 return r;
3850         }
3851
3852         return 0;
3853 }
3854
3855 #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12
3856 #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255
3857 #define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50
3858
3859 static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm,
3860                                             int bl_idx)
3861 {
3862 #if defined(CONFIG_ACPI)
3863         struct amdgpu_dm_backlight_caps caps;
3864
3865         memset(&caps, 0, sizeof(caps));
3866
3867         if (dm->backlight_caps[bl_idx].caps_valid)
3868                 return;
3869
3870         amdgpu_acpi_get_backlight_caps(&caps);
3871         if (caps.caps_valid) {
3872                 dm->backlight_caps[bl_idx].caps_valid = true;
3873                 if (caps.aux_support)
3874                         return;
3875                 dm->backlight_caps[bl_idx].min_input_signal = caps.min_input_signal;
3876                 dm->backlight_caps[bl_idx].max_input_signal = caps.max_input_signal;
3877         } else {
3878                 dm->backlight_caps[bl_idx].min_input_signal =
3879                                 AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
3880                 dm->backlight_caps[bl_idx].max_input_signal =
3881                                 AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
3882         }
3883 #else
3884         if (dm->backlight_caps[bl_idx].aux_support)
3885                 return;
3886
3887         dm->backlight_caps[bl_idx].min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
3888         dm->backlight_caps[bl_idx].max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
3889 #endif
3890 }
3891
3892 static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps,
3893                                 unsigned *min, unsigned *max)
3894 {
3895         if (!caps)
3896                 return 0;
3897
3898         if (caps->aux_support) {
3899                 // Firmware limits are in nits, DC API wants millinits.
3900                 *max = 1000 * caps->aux_max_input_signal;
3901                 *min = 1000 * caps->aux_min_input_signal;
3902         } else {
3903                 // Firmware limits are 8-bit, PWM control is 16-bit.
3904                 *max = 0x101 * caps->max_input_signal;
3905                 *min = 0x101 * caps->min_input_signal;
3906         }
3907         return 1;
3908 }
3909
3910 static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *caps,
3911                                         uint32_t brightness)
3912 {
3913         unsigned min, max;
3914
3915         if (!get_brightness_range(caps, &min, &max))
3916                 return brightness;
3917
3918         // Rescale 0..255 to min..max
3919         return min + DIV_ROUND_CLOSEST((max - min) * brightness,
3920                                        AMDGPU_MAX_BL_LEVEL);
3921 }
3922
3923 static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *caps,
3924                                       uint32_t brightness)
3925 {
3926         unsigned min, max;
3927
3928         if (!get_brightness_range(caps, &min, &max))
3929                 return brightness;
3930
3931         if (brightness < min)
3932                 return 0;
3933         // Rescale min..max to 0..255
3934         return DIV_ROUND_CLOSEST(AMDGPU_MAX_BL_LEVEL * (brightness - min),
3935                                  max - min);
3936 }
3937
3938 static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm,
3939                                          int bl_idx,
3940                                          u32 user_brightness)
3941 {
3942         struct amdgpu_dm_backlight_caps caps;
3943         struct dc_link *link;
3944         u32 brightness;
3945         bool rc;
3946
3947         amdgpu_dm_update_backlight_caps(dm, bl_idx);
3948         caps = dm->backlight_caps[bl_idx];
3949
3950         dm->brightness[bl_idx] = user_brightness;
3951         /* update scratch register */
3952         if (bl_idx == 0)
3953                 amdgpu_atombios_scratch_regs_set_backlight_level(dm->adev, dm->brightness[bl_idx]);
3954         brightness = convert_brightness_from_user(&caps, dm->brightness[bl_idx]);
3955         link = (struct dc_link *)dm->backlight_link[bl_idx];
3956
3957         /* Change brightness based on AUX property */
3958         if (caps.aux_support) {
3959                 rc = dc_link_set_backlight_level_nits(link, true, brightness,
3960                                                       AUX_BL_DEFAULT_TRANSITION_TIME_MS);
3961                 if (!rc)
3962                         DRM_DEBUG("DM: Failed to update backlight via AUX on eDP[%d]\n", bl_idx);
3963         } else {
3964                 rc = dc_link_set_backlight_level(link, brightness, 0);
3965                 if (!rc)
3966                         DRM_DEBUG("DM: Failed to update backlight on eDP[%d]\n", bl_idx);
3967         }
3968
3969         if (rc)
3970                 dm->actual_brightness[bl_idx] = user_brightness;
3971 }
3972
3973 static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
3974 {
3975         struct amdgpu_display_manager *dm = bl_get_data(bd);
3976         int i;
3977
3978         for (i = 0; i < dm->num_of_edps; i++) {
3979                 if (bd == dm->backlight_dev[i])
3980                         break;
3981         }
3982         if (i >= AMDGPU_DM_MAX_NUM_EDP)
3983                 i = 0;
3984         amdgpu_dm_backlight_set_level(dm, i, bd->props.brightness);
3985
3986         return 0;
3987 }
3988
3989 static u32 amdgpu_dm_backlight_get_level(struct amdgpu_display_manager *dm,
3990                                          int bl_idx)
3991 {
3992         struct amdgpu_dm_backlight_caps caps;
3993         struct dc_link *link = (struct dc_link *)dm->backlight_link[bl_idx];
3994
3995         amdgpu_dm_update_backlight_caps(dm, bl_idx);
3996         caps = dm->backlight_caps[bl_idx];
3997
3998         if (caps.aux_support) {
3999                 u32 avg, peak;
4000                 bool rc;
4001
4002                 rc = dc_link_get_backlight_level_nits(link, &avg, &peak);
4003                 if (!rc)
4004                         return dm->brightness[bl_idx];
4005                 return convert_brightness_to_user(&caps, avg);
4006         } else {
4007                 int ret = dc_link_get_backlight_level(link);
4008
4009                 if (ret == DC_ERROR_UNEXPECTED)
4010                         return dm->brightness[bl_idx];
4011                 return convert_brightness_to_user(&caps, ret);
4012         }
4013 }
4014
4015 static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
4016 {
4017         struct amdgpu_display_manager *dm = bl_get_data(bd);
4018         int i;
4019
4020         for (i = 0; i < dm->num_of_edps; i++) {
4021                 if (bd == dm->backlight_dev[i])
4022                         break;
4023         }
4024         if (i >= AMDGPU_DM_MAX_NUM_EDP)
4025                 i = 0;
4026         return amdgpu_dm_backlight_get_level(dm, i);
4027 }
4028
4029 static const struct backlight_ops amdgpu_dm_backlight_ops = {
4030         .options = BL_CORE_SUSPENDRESUME,
4031         .get_brightness = amdgpu_dm_backlight_get_brightness,
4032         .update_status  = amdgpu_dm_backlight_update_status,
4033 };
4034
4035 static void
4036 amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm)
4037 {
4038         char bl_name[16];
4039         struct backlight_properties props = { 0 };
4040
4041         amdgpu_dm_update_backlight_caps(dm, dm->num_of_edps);
4042         dm->brightness[dm->num_of_edps] = AMDGPU_MAX_BL_LEVEL;
4043
4044         if (!acpi_video_backlight_use_native()) {
4045                 drm_info(adev_to_drm(dm->adev), "Skipping amdgpu DM backlight registration\n");
4046                 /* Try registering an ACPI video backlight device instead. */
4047                 acpi_video_register_backlight();
4048                 return;
4049         }
4050
4051         props.max_brightness = AMDGPU_MAX_BL_LEVEL;
4052         props.brightness = AMDGPU_MAX_BL_LEVEL;
4053         props.type = BACKLIGHT_RAW;
4054
4055         snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
4056                  adev_to_drm(dm->adev)->primary->index + dm->num_of_edps);
4057
4058         dm->backlight_dev[dm->num_of_edps] = backlight_device_register(bl_name,
4059                                                                        adev_to_drm(dm->adev)->dev,
4060                                                                        dm,
4061                                                                        &amdgpu_dm_backlight_ops,
4062                                                                        &props);
4063
4064         if (IS_ERR(dm->backlight_dev[dm->num_of_edps]))
4065                 DRM_ERROR("DM: Backlight registration failed!\n");
4066         else
4067                 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
4068 }
4069
4070 static int initialize_plane(struct amdgpu_display_manager *dm,
4071                             struct amdgpu_mode_info *mode_info, int plane_id,
4072                             enum drm_plane_type plane_type,
4073                             const struct dc_plane_cap *plane_cap)
4074 {
4075         struct drm_plane *plane;
4076         unsigned long possible_crtcs;
4077         int ret = 0;
4078
4079         plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL);
4080         if (!plane) {
4081                 DRM_ERROR("KMS: Failed to allocate plane\n");
4082                 return -ENOMEM;
4083         }
4084         plane->type = plane_type;
4085
4086         /*
4087          * HACK: IGT tests expect that the primary plane for a CRTC
4088          * can only have one possible CRTC. Only expose support for
4089          * any CRTC if they're not going to be used as a primary plane
4090          * for a CRTC - like overlay or underlay planes.
4091          */
4092         possible_crtcs = 1 << plane_id;
4093         if (plane_id >= dm->dc->caps.max_streams)
4094                 possible_crtcs = 0xff;
4095
4096         ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap);
4097
4098         if (ret) {
4099                 DRM_ERROR("KMS: Failed to initialize plane\n");
4100                 kfree(plane);
4101                 return ret;
4102         }
4103
4104         if (mode_info)
4105                 mode_info->planes[plane_id] = plane;
4106
4107         return ret;
4108 }
4109
4110
4111 static void register_backlight_device(struct amdgpu_display_manager *dm,
4112                                       struct dc_link *link)
4113 {
4114         if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
4115             link->type != dc_connection_none) {
4116                 /*
4117                  * Event if registration failed, we should continue with
4118                  * DM initialization because not having a backlight control
4119                  * is better then a black screen.
4120                  */
4121                 if (!dm->backlight_dev[dm->num_of_edps])
4122                         amdgpu_dm_register_backlight_device(dm);
4123
4124                 if (dm->backlight_dev[dm->num_of_edps]) {
4125                         dm->backlight_link[dm->num_of_edps] = link;
4126                         dm->num_of_edps++;
4127                 }
4128         }
4129 }
4130
4131 static void amdgpu_set_panel_orientation(struct drm_connector *connector);
4132
4133 /*
4134  * In this architecture, the association
4135  * connector -> encoder -> crtc
4136  * id not really requried. The crtc and connector will hold the
4137  * display_index as an abstraction to use with DAL component
4138  *
4139  * Returns 0 on success
4140  */
4141 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
4142 {
4143         struct amdgpu_display_manager *dm = &adev->dm;
4144         int32_t i;
4145         struct amdgpu_dm_connector *aconnector = NULL;
4146         struct amdgpu_encoder *aencoder = NULL;
4147         struct amdgpu_mode_info *mode_info = &adev->mode_info;
4148         uint32_t link_cnt;
4149         int32_t primary_planes;
4150         enum dc_connection_type new_connection_type = dc_connection_none;
4151         const struct dc_plane_cap *plane;
4152         bool psr_feature_enabled = false;
4153
4154         dm->display_indexes_num = dm->dc->caps.max_streams;
4155         /* Update the actual used number of crtc */
4156         adev->mode_info.num_crtc = adev->dm.display_indexes_num;
4157
4158         link_cnt = dm->dc->caps.max_links;
4159         if (amdgpu_dm_mode_config_init(dm->adev)) {
4160                 DRM_ERROR("DM: Failed to initialize mode config\n");
4161                 return -EINVAL;
4162         }
4163
4164         /* There is one primary plane per CRTC */
4165         primary_planes = dm->dc->caps.max_streams;
4166         ASSERT(primary_planes <= AMDGPU_MAX_PLANES);
4167
4168         /*
4169          * Initialize primary planes, implicit planes for legacy IOCTLS.
4170          * Order is reversed to match iteration order in atomic check.
4171          */
4172         for (i = (primary_planes - 1); i >= 0; i--) {
4173                 plane = &dm->dc->caps.planes[i];
4174
4175                 if (initialize_plane(dm, mode_info, i,
4176                                      DRM_PLANE_TYPE_PRIMARY, plane)) {
4177                         DRM_ERROR("KMS: Failed to initialize primary plane\n");
4178                         goto fail;
4179                 }
4180         }
4181
4182         /*
4183          * Initialize overlay planes, index starting after primary planes.
4184          * These planes have a higher DRM index than the primary planes since
4185          * they should be considered as having a higher z-order.
4186          * Order is reversed to match iteration order in atomic check.
4187          *
4188          * Only support DCN for now, and only expose one so we don't encourage
4189          * userspace to use up all the pipes.
4190          */
4191         for (i = 0; i < dm->dc->caps.max_planes; ++i) {
4192                 struct dc_plane_cap *plane = &dm->dc->caps.planes[i];
4193
4194                 /* Do not create overlay if MPO disabled */
4195                 if (amdgpu_dc_debug_mask & DC_DISABLE_MPO)
4196                         break;
4197
4198                 if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL)
4199                         continue;
4200
4201                 if (!plane->blends_with_above || !plane->blends_with_below)
4202                         continue;
4203
4204                 if (!plane->pixel_format_support.argb8888)
4205                         continue;
4206
4207                 if (initialize_plane(dm, NULL, primary_planes + i,
4208                                      DRM_PLANE_TYPE_OVERLAY, plane)) {
4209                         DRM_ERROR("KMS: Failed to initialize overlay plane\n");
4210                         goto fail;
4211                 }
4212
4213                 /* Only create one overlay plane. */
4214                 break;
4215         }
4216
4217         for (i = 0; i < dm->dc->caps.max_streams; i++)
4218                 if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) {
4219                         DRM_ERROR("KMS: Failed to initialize crtc\n");
4220                         goto fail;
4221                 }
4222
4223         /* Use Outbox interrupt */
4224         switch (adev->ip_versions[DCE_HWIP][0]) {
4225         case IP_VERSION(3, 0, 0):
4226         case IP_VERSION(3, 1, 2):
4227         case IP_VERSION(3, 1, 3):
4228         case IP_VERSION(3, 1, 4):
4229         case IP_VERSION(3, 1, 5):
4230         case IP_VERSION(3, 1, 6):
4231         case IP_VERSION(3, 2, 0):
4232         case IP_VERSION(3, 2, 1):
4233         case IP_VERSION(2, 1, 0):
4234                 if (register_outbox_irq_handlers(dm->adev)) {
4235                         DRM_ERROR("DM: Failed to initialize IRQ\n");
4236                         goto fail;
4237                 }
4238                 break;
4239         default:
4240                 DRM_DEBUG_KMS("Unsupported DCN IP version for outbox: 0x%X\n",
4241                               adev->ip_versions[DCE_HWIP][0]);
4242         }
4243
4244         /* Determine whether to enable PSR support by default. */
4245         if (!(amdgpu_dc_debug_mask & DC_DISABLE_PSR)) {
4246                 switch (adev->ip_versions[DCE_HWIP][0]) {
4247                 case IP_VERSION(3, 1, 2):
4248                 case IP_VERSION(3, 1, 3):
4249                 case IP_VERSION(3, 1, 4):
4250                 case IP_VERSION(3, 1, 5):
4251                 case IP_VERSION(3, 1, 6):
4252                 case IP_VERSION(3, 2, 0):
4253                 case IP_VERSION(3, 2, 1):
4254                         psr_feature_enabled = true;
4255                         break;
4256                 default:
4257                         psr_feature_enabled = amdgpu_dc_feature_mask & DC_PSR_MASK;
4258                         break;
4259                 }
4260         }
4261
4262         /* loops over all connectors on the board */
4263         for (i = 0; i < link_cnt; i++) {
4264                 struct dc_link *link = NULL;
4265
4266                 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
4267                         DRM_ERROR(
4268                                 "KMS: Cannot support more than %d display indexes\n",
4269                                         AMDGPU_DM_MAX_DISPLAY_INDEX);
4270                         continue;
4271                 }
4272
4273                 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
4274                 if (!aconnector)
4275                         goto fail;
4276
4277                 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
4278                 if (!aencoder)
4279                         goto fail;
4280
4281                 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
4282                         DRM_ERROR("KMS: Failed to initialize encoder\n");
4283                         goto fail;
4284                 }
4285
4286                 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
4287                         DRM_ERROR("KMS: Failed to initialize connector\n");
4288                         goto fail;
4289                 }
4290
4291                 link = dc_get_link_at_index(dm->dc, i);
4292
4293                 if (!dc_link_detect_sink(link, &new_connection_type))
4294                         DRM_ERROR("KMS: Failed to detect connector\n");
4295
4296                 if (aconnector->base.force && new_connection_type == dc_connection_none) {
4297                         emulated_link_detect(link);
4298                         amdgpu_dm_update_connector_after_detect(aconnector);
4299                 } else {
4300                         bool ret = false;
4301
4302                         mutex_lock(&dm->dc_lock);
4303                         ret = dc_link_detect(link, DETECT_REASON_BOOT);
4304                         mutex_unlock(&dm->dc_lock);
4305
4306                         if (ret) {
4307                                 amdgpu_dm_update_connector_after_detect(aconnector);
4308                                 register_backlight_device(dm, link);
4309
4310                                 if (dm->num_of_edps)
4311                                         update_connector_ext_caps(aconnector);
4312
4313                                 if (psr_feature_enabled)
4314                                         amdgpu_dm_set_psr_caps(link);
4315
4316                                 /* TODO: Fix vblank control helpers to delay PSR entry to allow this when
4317                                  * PSR is also supported.
4318                                  */
4319                                 if (link->psr_settings.psr_feature_enabled)
4320                                         adev_to_drm(adev)->vblank_disable_immediate = false;
4321                         }
4322                 }
4323                 amdgpu_set_panel_orientation(&aconnector->base);
4324         }
4325
4326         /* Software is initialized. Now we can register interrupt handlers. */
4327         switch (adev->asic_type) {
4328 #if defined(CONFIG_DRM_AMD_DC_SI)
4329         case CHIP_TAHITI:
4330         case CHIP_PITCAIRN:
4331         case CHIP_VERDE:
4332         case CHIP_OLAND:
4333                 if (dce60_register_irq_handlers(dm->adev)) {
4334                         DRM_ERROR("DM: Failed to initialize IRQ\n");
4335                         goto fail;
4336                 }
4337                 break;
4338 #endif
4339         case CHIP_BONAIRE:
4340         case CHIP_HAWAII:
4341         case CHIP_KAVERI:
4342         case CHIP_KABINI:
4343         case CHIP_MULLINS:
4344         case CHIP_TONGA:
4345         case CHIP_FIJI:
4346         case CHIP_CARRIZO:
4347         case CHIP_STONEY:
4348         case CHIP_POLARIS11:
4349         case CHIP_POLARIS10:
4350         case CHIP_POLARIS12:
4351         case CHIP_VEGAM:
4352         case CHIP_VEGA10:
4353         case CHIP_VEGA12:
4354         case CHIP_VEGA20:
4355                 if (dce110_register_irq_handlers(dm->adev)) {
4356                         DRM_ERROR("DM: Failed to initialize IRQ\n");
4357                         goto fail;
4358                 }
4359                 break;
4360         default:
4361                 switch (adev->ip_versions[DCE_HWIP][0]) {
4362                 case IP_VERSION(1, 0, 0):
4363                 case IP_VERSION(1, 0, 1):
4364                 case IP_VERSION(2, 0, 2):
4365                 case IP_VERSION(2, 0, 3):
4366                 case IP_VERSION(2, 0, 0):
4367                 case IP_VERSION(2, 1, 0):
4368                 case IP_VERSION(3, 0, 0):
4369                 case IP_VERSION(3, 0, 2):
4370                 case IP_VERSION(3, 0, 3):
4371                 case IP_VERSION(3, 0, 1):
4372                 case IP_VERSION(3, 1, 2):
4373                 case IP_VERSION(3, 1, 3):
4374                 case IP_VERSION(3, 1, 4):
4375                 case IP_VERSION(3, 1, 5):
4376                 case IP_VERSION(3, 1, 6):
4377                 case IP_VERSION(3, 2, 0):
4378                 case IP_VERSION(3, 2, 1):
4379                         if (dcn10_register_irq_handlers(dm->adev)) {
4380                                 DRM_ERROR("DM: Failed to initialize IRQ\n");
4381                                 goto fail;
4382                         }
4383                         break;
4384                 default:
4385                         DRM_ERROR("Unsupported DCE IP versions: 0x%X\n",
4386                                         adev->ip_versions[DCE_HWIP][0]);
4387                         goto fail;
4388                 }
4389                 break;
4390         }
4391
4392         return 0;
4393 fail:
4394         kfree(aencoder);
4395         kfree(aconnector);
4396
4397         return -EINVAL;
4398 }
4399
4400 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
4401 {
4402         drm_atomic_private_obj_fini(&dm->atomic_obj);
4403         return;
4404 }
4405
4406 /******************************************************************************
4407  * amdgpu_display_funcs functions
4408  *****************************************************************************/
4409
4410 /*
4411  * dm_bandwidth_update - program display watermarks
4412  *
4413  * @adev: amdgpu_device pointer
4414  *
4415  * Calculate and program the display watermarks and line buffer allocation.
4416  */
4417 static void dm_bandwidth_update(struct amdgpu_device *adev)
4418 {
4419         /* TODO: implement later */
4420 }
4421
4422 static const struct amdgpu_display_funcs dm_display_funcs = {
4423         .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
4424         .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
4425         .backlight_set_level = NULL, /* never called for DC */
4426         .backlight_get_level = NULL, /* never called for DC */
4427         .hpd_sense = NULL,/* called unconditionally */
4428         .hpd_set_polarity = NULL, /* called unconditionally */
4429         .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
4430         .page_flip_get_scanoutpos =
4431                 dm_crtc_get_scanoutpos,/* called unconditionally */
4432         .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
4433         .add_connector = NULL, /* VBIOS parsing. DAL does it. */
4434 };
4435
4436 #if defined(CONFIG_DEBUG_KERNEL_DC)
4437
4438 static ssize_t s3_debug_store(struct device *device,
4439                               struct device_attribute *attr,
4440                               const char *buf,
4441                               size_t count)
4442 {
4443         int ret;
4444         int s3_state;
4445         struct drm_device *drm_dev = dev_get_drvdata(device);
4446         struct amdgpu_device *adev = drm_to_adev(drm_dev);
4447
4448         ret = kstrtoint(buf, 0, &s3_state);
4449
4450         if (ret == 0) {
4451                 if (s3_state) {
4452                         dm_resume(adev);
4453                         drm_kms_helper_hotplug_event(adev_to_drm(adev));
4454                 } else
4455                         dm_suspend(adev);
4456         }
4457
4458         return ret == 0 ? count : 0;
4459 }
4460
4461 DEVICE_ATTR_WO(s3_debug);
4462
4463 #endif
4464
4465 static int dm_early_init(void *handle)
4466 {
4467         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4468
4469         switch (adev->asic_type) {
4470 #if defined(CONFIG_DRM_AMD_DC_SI)
4471         case CHIP_TAHITI:
4472         case CHIP_PITCAIRN:
4473         case CHIP_VERDE:
4474                 adev->mode_info.num_crtc = 6;
4475                 adev->mode_info.num_hpd = 6;
4476                 adev->mode_info.num_dig = 6;
4477                 break;
4478         case CHIP_OLAND:
4479                 adev->mode_info.num_crtc = 2;
4480                 adev->mode_info.num_hpd = 2;
4481                 adev->mode_info.num_dig = 2;
4482                 break;
4483 #endif
4484         case CHIP_BONAIRE:
4485         case CHIP_HAWAII:
4486                 adev->mode_info.num_crtc = 6;
4487                 adev->mode_info.num_hpd = 6;
4488                 adev->mode_info.num_dig = 6;
4489                 break;
4490         case CHIP_KAVERI:
4491                 adev->mode_info.num_crtc = 4;
4492                 adev->mode_info.num_hpd = 6;
4493                 adev->mode_info.num_dig = 7;
4494                 break;
4495         case CHIP_KABINI:
4496         case CHIP_MULLINS:
4497                 adev->mode_info.num_crtc = 2;
4498                 adev->mode_info.num_hpd = 6;
4499                 adev->mode_info.num_dig = 6;
4500                 break;
4501         case CHIP_FIJI:
4502         case CHIP_TONGA:
4503                 adev->mode_info.num_crtc = 6;
4504                 adev->mode_info.num_hpd = 6;
4505                 adev->mode_info.num_dig = 7;
4506                 break;
4507         case CHIP_CARRIZO:
4508                 adev->mode_info.num_crtc = 3;
4509                 adev->mode_info.num_hpd = 6;
4510                 adev->mode_info.num_dig = 9;
4511                 break;
4512         case CHIP_STONEY:
4513                 adev->mode_info.num_crtc = 2;
4514                 adev->mode_info.num_hpd = 6;
4515                 adev->mode_info.num_dig = 9;
4516                 break;
4517         case CHIP_POLARIS11:
4518         case CHIP_POLARIS12:
4519                 adev->mode_info.num_crtc = 5;
4520                 adev->mode_info.num_hpd = 5;
4521                 adev->mode_info.num_dig = 5;
4522                 break;
4523         case CHIP_POLARIS10:
4524         case CHIP_VEGAM:
4525                 adev->mode_info.num_crtc = 6;
4526                 adev->mode_info.num_hpd = 6;
4527                 adev->mode_info.num_dig = 6;
4528                 break;
4529         case CHIP_VEGA10:
4530         case CHIP_VEGA12:
4531         case CHIP_VEGA20:
4532                 adev->mode_info.num_crtc = 6;
4533                 adev->mode_info.num_hpd = 6;
4534                 adev->mode_info.num_dig = 6;
4535                 break;
4536         default:
4537
4538                 switch (adev->ip_versions[DCE_HWIP][0]) {
4539                 case IP_VERSION(2, 0, 2):
4540                 case IP_VERSION(3, 0, 0):
4541                         adev->mode_info.num_crtc = 6;
4542                         adev->mode_info.num_hpd = 6;
4543                         adev->mode_info.num_dig = 6;
4544                         break;
4545                 case IP_VERSION(2, 0, 0):
4546                 case IP_VERSION(3, 0, 2):
4547                         adev->mode_info.num_crtc = 5;
4548                         adev->mode_info.num_hpd = 5;
4549                         adev->mode_info.num_dig = 5;
4550                         break;
4551                 case IP_VERSION(2, 0, 3):
4552                 case IP_VERSION(3, 0, 3):
4553                         adev->mode_info.num_crtc = 2;
4554                         adev->mode_info.num_hpd = 2;
4555                         adev->mode_info.num_dig = 2;
4556                         break;
4557                 case IP_VERSION(1, 0, 0):
4558                 case IP_VERSION(1, 0, 1):
4559                 case IP_VERSION(3, 0, 1):
4560                 case IP_VERSION(2, 1, 0):
4561                 case IP_VERSION(3, 1, 2):
4562                 case IP_VERSION(3, 1, 3):
4563                 case IP_VERSION(3, 1, 4):
4564                 case IP_VERSION(3, 1, 5):
4565                 case IP_VERSION(3, 1, 6):
4566                 case IP_VERSION(3, 2, 0):
4567                 case IP_VERSION(3, 2, 1):
4568                         adev->mode_info.num_crtc = 4;
4569                         adev->mode_info.num_hpd = 4;
4570                         adev->mode_info.num_dig = 4;
4571                         break;
4572                 default:
4573                         DRM_ERROR("Unsupported DCE IP versions: 0x%x\n",
4574                                         adev->ip_versions[DCE_HWIP][0]);
4575                         return -EINVAL;
4576                 }
4577                 break;
4578         }
4579
4580         amdgpu_dm_set_irq_funcs(adev);
4581
4582         if (adev->mode_info.funcs == NULL)
4583                 adev->mode_info.funcs = &dm_display_funcs;
4584
4585         /*
4586          * Note: Do NOT change adev->audio_endpt_rreg and
4587          * adev->audio_endpt_wreg because they are initialised in
4588          * amdgpu_device_init()
4589          */
4590 #if defined(CONFIG_DEBUG_KERNEL_DC)
4591         device_create_file(
4592                 adev_to_drm(adev)->dev,
4593                 &dev_attr_s3_debug);
4594 #endif
4595
4596         return 0;
4597 }
4598
4599 static bool modereset_required(struct drm_crtc_state *crtc_state)
4600 {
4601         return !crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state);
4602 }
4603
4604 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
4605 {
4606         drm_encoder_cleanup(encoder);
4607         kfree(encoder);
4608 }
4609
4610 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
4611         .destroy = amdgpu_dm_encoder_destroy,
4612 };
4613
4614 static int
4615 fill_plane_color_attributes(const struct drm_plane_state *plane_state,
4616                             const enum surface_pixel_format format,
4617                             enum dc_color_space *color_space)
4618 {
4619         bool full_range;
4620
4621         *color_space = COLOR_SPACE_SRGB;
4622
4623         /* DRM color properties only affect non-RGB formats. */
4624         if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
4625                 return 0;
4626
4627         full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE);
4628
4629         switch (plane_state->color_encoding) {
4630         case DRM_COLOR_YCBCR_BT601:
4631                 if (full_range)
4632                         *color_space = COLOR_SPACE_YCBCR601;
4633                 else
4634                         *color_space = COLOR_SPACE_YCBCR601_LIMITED;
4635                 break;
4636
4637         case DRM_COLOR_YCBCR_BT709:
4638                 if (full_range)
4639                         *color_space = COLOR_SPACE_YCBCR709;
4640                 else
4641                         *color_space = COLOR_SPACE_YCBCR709_LIMITED;
4642                 break;
4643
4644         case DRM_COLOR_YCBCR_BT2020:
4645                 if (full_range)
4646                         *color_space = COLOR_SPACE_2020_YCBCR;
4647                 else
4648                         return -EINVAL;
4649                 break;
4650
4651         default:
4652                 return -EINVAL;
4653         }
4654
4655         return 0;
4656 }
4657
4658 static int
4659 fill_dc_plane_info_and_addr(struct amdgpu_device *adev,
4660                             const struct drm_plane_state *plane_state,
4661                             const uint64_t tiling_flags,
4662                             struct dc_plane_info *plane_info,
4663                             struct dc_plane_address *address,
4664                             bool tmz_surface,
4665                             bool force_disable_dcc)
4666 {
4667         const struct drm_framebuffer *fb = plane_state->fb;
4668         const struct amdgpu_framebuffer *afb =
4669                 to_amdgpu_framebuffer(plane_state->fb);
4670         int ret;
4671
4672         memset(plane_info, 0, sizeof(*plane_info));
4673
4674         switch (fb->format->format) {
4675         case DRM_FORMAT_C8:
4676                 plane_info->format =
4677                         SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
4678                 break;
4679         case DRM_FORMAT_RGB565:
4680                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
4681                 break;
4682         case DRM_FORMAT_XRGB8888:
4683         case DRM_FORMAT_ARGB8888:
4684                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
4685                 break;
4686         case DRM_FORMAT_XRGB2101010:
4687         case DRM_FORMAT_ARGB2101010:
4688                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
4689                 break;
4690         case DRM_FORMAT_XBGR2101010:
4691         case DRM_FORMAT_ABGR2101010:
4692                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
4693                 break;
4694         case DRM_FORMAT_XBGR8888:
4695         case DRM_FORMAT_ABGR8888:
4696                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888;
4697                 break;
4698         case DRM_FORMAT_NV21:
4699                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
4700                 break;
4701         case DRM_FORMAT_NV12:
4702                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
4703                 break;
4704         case DRM_FORMAT_P010:
4705                 plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb;
4706                 break;
4707         case DRM_FORMAT_XRGB16161616F:
4708         case DRM_FORMAT_ARGB16161616F:
4709                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F;
4710                 break;
4711         case DRM_FORMAT_XBGR16161616F:
4712         case DRM_FORMAT_ABGR16161616F:
4713                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F;
4714                 break;
4715         case DRM_FORMAT_XRGB16161616:
4716         case DRM_FORMAT_ARGB16161616:
4717                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616;
4718                 break;
4719         case DRM_FORMAT_XBGR16161616:
4720         case DRM_FORMAT_ABGR16161616:
4721                 plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616;
4722                 break;
4723         default:
4724                 DRM_ERROR(
4725                         "Unsupported screen format %p4cc\n",
4726                         &fb->format->format);
4727                 return -EINVAL;
4728         }
4729
4730         switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
4731         case DRM_MODE_ROTATE_0:
4732                 plane_info->rotation = ROTATION_ANGLE_0;
4733                 break;
4734         case DRM_MODE_ROTATE_90:
4735                 plane_info->rotation = ROTATION_ANGLE_90;
4736                 break;
4737         case DRM_MODE_ROTATE_180:
4738                 plane_info->rotation = ROTATION_ANGLE_180;
4739                 break;
4740         case DRM_MODE_ROTATE_270:
4741                 plane_info->rotation = ROTATION_ANGLE_270;
4742                 break;
4743         default:
4744                 plane_info->rotation = ROTATION_ANGLE_0;
4745                 break;
4746         }
4747
4748
4749         plane_info->visible = true;
4750         plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE;
4751
4752         plane_info->layer_index = plane_state->normalized_zpos;
4753
4754         ret = fill_plane_color_attributes(plane_state, plane_info->format,
4755                                           &plane_info->color_space);
4756         if (ret)
4757                 return ret;
4758
4759         ret = fill_plane_buffer_attributes(adev, afb, plane_info->format,
4760                                            plane_info->rotation, tiling_flags,
4761                                            &plane_info->tiling_info,
4762                                            &plane_info->plane_size,
4763                                            &plane_info->dcc, address,
4764                                            tmz_surface, force_disable_dcc);
4765         if (ret)
4766                 return ret;
4767
4768         fill_blending_from_plane_state(
4769                 plane_state, &plane_info->per_pixel_alpha, &plane_info->pre_multiplied_alpha,
4770                 &plane_info->global_alpha, &plane_info->global_alpha_value);
4771
4772         return 0;
4773 }
4774
4775 static int fill_dc_plane_attributes(struct amdgpu_device *adev,
4776                                     struct dc_plane_state *dc_plane_state,
4777                                     struct drm_plane_state *plane_state,
4778                                     struct drm_crtc_state *crtc_state)
4779 {
4780         struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
4781         struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)plane_state->fb;
4782         struct dc_scaling_info scaling_info;
4783         struct dc_plane_info plane_info;
4784         int ret;
4785         bool force_disable_dcc = false;
4786
4787         ret = fill_dc_scaling_info(adev, plane_state, &scaling_info);
4788         if (ret)
4789                 return ret;
4790
4791         dc_plane_state->src_rect = scaling_info.src_rect;
4792         dc_plane_state->dst_rect = scaling_info.dst_rect;
4793         dc_plane_state->clip_rect = scaling_info.clip_rect;
4794         dc_plane_state->scaling_quality = scaling_info.scaling_quality;
4795
4796         force_disable_dcc = adev->asic_type == CHIP_RAVEN && adev->in_suspend;
4797         ret = fill_dc_plane_info_and_addr(adev, plane_state,
4798                                           afb->tiling_flags,
4799                                           &plane_info,
4800                                           &dc_plane_state->address,
4801                                           afb->tmz_surface,
4802                                           force_disable_dcc);
4803         if (ret)
4804                 return ret;
4805
4806         dc_plane_state->format = plane_info.format;
4807         dc_plane_state->color_space = plane_info.color_space;
4808         dc_plane_state->format = plane_info.format;
4809         dc_plane_state->plane_size = plane_info.plane_size;
4810         dc_plane_state->rotation = plane_info.rotation;
4811         dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror;
4812         dc_plane_state->stereo_format = plane_info.stereo_format;
4813         dc_plane_state->tiling_info = plane_info.tiling_info;
4814         dc_plane_state->visible = plane_info.visible;
4815         dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha;
4816         dc_plane_state->pre_multiplied_alpha = plane_info.pre_multiplied_alpha;
4817         dc_plane_state->global_alpha = plane_info.global_alpha;
4818         dc_plane_state->global_alpha_value = plane_info.global_alpha_value;
4819         dc_plane_state->dcc = plane_info.dcc;
4820         dc_plane_state->layer_index = plane_info.layer_index;
4821         dc_plane_state->flip_int_enabled = true;
4822
4823         /*
4824          * Always set input transfer function, since plane state is refreshed
4825          * every time.
4826          */
4827         ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dc_plane_state);
4828         if (ret)
4829                 return ret;
4830
4831         return 0;
4832 }
4833
4834 /**
4835  * fill_dc_dirty_rects() - Fill DC dirty regions for PSR selective updates
4836  *
4837  * @plane: DRM plane containing dirty regions that need to be flushed to the eDP
4838  *         remote fb
4839  * @old_plane_state: Old state of @plane
4840  * @new_plane_state: New state of @plane
4841  * @crtc_state: New state of CRTC connected to the @plane
4842  * @flip_addrs: DC flip tracking struct, which also tracts dirty rects
4843  *
4844  * For PSR SU, DC informs the DMUB uController of dirty rectangle regions
4845  * (referred to as "damage clips" in DRM nomenclature) that require updating on
4846  * the eDP remote buffer. The responsibility of specifying the dirty regions is
4847  * amdgpu_dm's.
4848  *
4849  * A damage-aware DRM client should fill the FB_DAMAGE_CLIPS property on the
4850  * plane with regions that require flushing to the eDP remote buffer. In
4851  * addition, certain use cases - such as cursor and multi-plane overlay (MPO) -
4852  * implicitly provide damage clips without any client support via the plane
4853  * bounds.
4854  *
4855  * Today, amdgpu_dm only supports the MPO and cursor usecase.
4856  *
4857  * TODO: Also enable for FB_DAMAGE_CLIPS
4858  */
4859 static void fill_dc_dirty_rects(struct drm_plane *plane,
4860                                 struct drm_plane_state *old_plane_state,
4861                                 struct drm_plane_state *new_plane_state,
4862                                 struct drm_crtc_state *crtc_state,
4863                                 struct dc_flip_addrs *flip_addrs)
4864 {
4865         struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
4866         struct rect *dirty_rects = flip_addrs->dirty_rects;
4867         uint32_t num_clips;
4868         bool bb_changed;
4869         bool fb_changed;
4870         uint32_t i = 0;
4871
4872         flip_addrs->dirty_rect_count = 0;
4873
4874         /*
4875          * Cursor plane has it's own dirty rect update interface. See
4876          * dcn10_dmub_update_cursor_data and dmub_cmd_update_cursor_info_data
4877          */
4878         if (plane->type == DRM_PLANE_TYPE_CURSOR)
4879                 return;
4880
4881         /*
4882          * Today, we only consider MPO use-case for PSR SU. If MPO not
4883          * requested, and there is a plane update, do FFU.
4884          */
4885         if (!dm_crtc_state->mpo_requested) {
4886                 dirty_rects[0].x = 0;
4887                 dirty_rects[0].y = 0;
4888                 dirty_rects[0].width = dm_crtc_state->base.mode.crtc_hdisplay;
4889                 dirty_rects[0].height = dm_crtc_state->base.mode.crtc_vdisplay;
4890                 flip_addrs->dirty_rect_count = 1;
4891                 DRM_DEBUG_DRIVER("[PLANE:%d] PSR FFU dirty rect size (%d, %d)\n",
4892                                  new_plane_state->plane->base.id,
4893                                  dm_crtc_state->base.mode.crtc_hdisplay,
4894                                  dm_crtc_state->base.mode.crtc_vdisplay);
4895                 return;
4896         }
4897
4898         /*
4899          * MPO is requested. Add entire plane bounding box to dirty rects if
4900          * flipped to or damaged.
4901          *
4902          * If plane is moved or resized, also add old bounding box to dirty
4903          * rects.
4904          */
4905         num_clips = drm_plane_get_damage_clips_count(new_plane_state);
4906         fb_changed = old_plane_state->fb->base.id !=
4907                      new_plane_state->fb->base.id;
4908         bb_changed = (old_plane_state->crtc_x != new_plane_state->crtc_x ||
4909                       old_plane_state->crtc_y != new_plane_state->crtc_y ||
4910                       old_plane_state->crtc_w != new_plane_state->crtc_w ||
4911                       old_plane_state->crtc_h != new_plane_state->crtc_h);
4912
4913         DRM_DEBUG_DRIVER("[PLANE:%d] PSR bb_changed:%d fb_changed:%d num_clips:%d\n",
4914                          new_plane_state->plane->base.id,
4915                          bb_changed, fb_changed, num_clips);
4916
4917         if (num_clips || fb_changed || bb_changed) {
4918                 dirty_rects[i].x = new_plane_state->crtc_x;
4919                 dirty_rects[i].y = new_plane_state->crtc_y;
4920                 dirty_rects[i].width = new_plane_state->crtc_w;
4921                 dirty_rects[i].height = new_plane_state->crtc_h;
4922                 DRM_DEBUG_DRIVER("[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)\n",
4923                                  new_plane_state->plane->base.id,
4924                                  dirty_rects[i].x, dirty_rects[i].y,
4925                                  dirty_rects[i].width, dirty_rects[i].height);
4926                 i += 1;
4927         }
4928
4929         /* Add old plane bounding-box if plane is moved or resized */
4930         if (bb_changed) {
4931                 dirty_rects[i].x = old_plane_state->crtc_x;
4932                 dirty_rects[i].y = old_plane_state->crtc_y;
4933                 dirty_rects[i].width = old_plane_state->crtc_w;
4934                 dirty_rects[i].height = old_plane_state->crtc_h;
4935                 DRM_DEBUG_DRIVER("[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)\n",
4936                                 old_plane_state->plane->base.id,
4937                                 dirty_rects[i].x, dirty_rects[i].y,
4938                                 dirty_rects[i].width, dirty_rects[i].height);
4939                 i += 1;
4940         }
4941
4942         flip_addrs->dirty_rect_count = i;
4943 }
4944
4945 static void update_stream_scaling_settings(const struct drm_display_mode *mode,
4946                                            const struct dm_connector_state *dm_state,
4947                                            struct dc_stream_state *stream)
4948 {
4949         enum amdgpu_rmx_type rmx_type;
4950
4951         struct rect src = { 0 }; /* viewport in composition space*/
4952         struct rect dst = { 0 }; /* stream addressable area */
4953
4954         /* no mode. nothing to be done */
4955         if (!mode)
4956                 return;
4957
4958         /* Full screen scaling by default */
4959         src.width = mode->hdisplay;
4960         src.height = mode->vdisplay;
4961         dst.width = stream->timing.h_addressable;
4962         dst.height = stream->timing.v_addressable;
4963
4964         if (dm_state) {
4965                 rmx_type = dm_state->scaling;
4966                 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
4967                         if (src.width * dst.height <
4968                                         src.height * dst.width) {
4969                                 /* height needs less upscaling/more downscaling */
4970                                 dst.width = src.width *
4971                                                 dst.height / src.height;
4972                         } else {
4973                                 /* width needs less upscaling/more downscaling */
4974                                 dst.height = src.height *
4975                                                 dst.width / src.width;
4976                         }
4977                 } else if (rmx_type == RMX_CENTER) {
4978                         dst = src;
4979                 }
4980
4981                 dst.x = (stream->timing.h_addressable - dst.width) / 2;
4982                 dst.y = (stream->timing.v_addressable - dst.height) / 2;
4983
4984                 if (dm_state->underscan_enable) {
4985                         dst.x += dm_state->underscan_hborder / 2;
4986                         dst.y += dm_state->underscan_vborder / 2;
4987                         dst.width -= dm_state->underscan_hborder;
4988                         dst.height -= dm_state->underscan_vborder;
4989                 }
4990         }
4991
4992         stream->src = src;
4993         stream->dst = dst;
4994
4995         DRM_DEBUG_KMS("Destination Rectangle x:%d  y:%d  width:%d  height:%d\n",
4996                       dst.x, dst.y, dst.width, dst.height);
4997
4998 }
4999
5000 static enum dc_color_depth
5001 convert_color_depth_from_display_info(const struct drm_connector *connector,
5002                                       bool is_y420, int requested_bpc)
5003 {
5004         uint8_t bpc;
5005
5006         if (is_y420) {
5007                 bpc = 8;
5008
5009                 /* Cap display bpc based on HDMI 2.0 HF-VSDB */
5010                 if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48)
5011                         bpc = 16;
5012                 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36)
5013                         bpc = 12;
5014                 else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30)
5015                         bpc = 10;
5016         } else {
5017                 bpc = (uint8_t)connector->display_info.bpc;
5018                 /* Assume 8 bpc by default if no bpc is specified. */
5019                 bpc = bpc ? bpc : 8;
5020         }
5021
5022         if (requested_bpc > 0) {
5023                 /*
5024                  * Cap display bpc based on the user requested value.
5025                  *
5026                  * The value for state->max_bpc may not correctly updated
5027                  * depending on when the connector gets added to the state
5028                  * or if this was called outside of atomic check, so it
5029                  * can't be used directly.
5030                  */
5031                 bpc = min_t(u8, bpc, requested_bpc);
5032
5033                 /* Round down to the nearest even number. */
5034                 bpc = bpc - (bpc & 1);
5035         }
5036
5037         switch (bpc) {
5038         case 0:
5039                 /*
5040                  * Temporary Work around, DRM doesn't parse color depth for
5041                  * EDID revision before 1.4
5042                  * TODO: Fix edid parsing
5043                  */
5044                 return COLOR_DEPTH_888;
5045         case 6:
5046                 return COLOR_DEPTH_666;
5047         case 8:
5048                 return COLOR_DEPTH_888;
5049         case 10:
5050                 return COLOR_DEPTH_101010;
5051         case 12:
5052                 return COLOR_DEPTH_121212;
5053         case 14:
5054                 return COLOR_DEPTH_141414;
5055         case 16:
5056                 return COLOR_DEPTH_161616;
5057         default:
5058                 return COLOR_DEPTH_UNDEFINED;
5059         }
5060 }
5061
5062 static enum dc_aspect_ratio
5063 get_aspect_ratio(const struct drm_display_mode *mode_in)
5064 {
5065         /* 1-1 mapping, since both enums follow the HDMI spec. */
5066         return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio;
5067 }
5068
5069 static enum dc_color_space
5070 get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
5071 {
5072         enum dc_color_space color_space = COLOR_SPACE_SRGB;
5073
5074         switch (dc_crtc_timing->pixel_encoding) {
5075         case PIXEL_ENCODING_YCBCR422:
5076         case PIXEL_ENCODING_YCBCR444:
5077         case PIXEL_ENCODING_YCBCR420:
5078         {
5079                 /*
5080                  * 27030khz is the separation point between HDTV and SDTV
5081                  * according to HDMI spec, we use YCbCr709 and YCbCr601
5082                  * respectively
5083                  */
5084                 if (dc_crtc_timing->pix_clk_100hz > 270300) {
5085                         if (dc_crtc_timing->flags.Y_ONLY)
5086                                 color_space =
5087                                         COLOR_SPACE_YCBCR709_LIMITED;
5088                         else
5089                                 color_space = COLOR_SPACE_YCBCR709;
5090                 } else {
5091                         if (dc_crtc_timing->flags.Y_ONLY)
5092                                 color_space =
5093                                         COLOR_SPACE_YCBCR601_LIMITED;
5094                         else
5095                                 color_space = COLOR_SPACE_YCBCR601;
5096                 }
5097
5098         }
5099         break;
5100         case PIXEL_ENCODING_RGB:
5101                 color_space = COLOR_SPACE_SRGB;
5102                 break;
5103
5104         default:
5105                 WARN_ON(1);
5106                 break;
5107         }
5108
5109         return color_space;
5110 }
5111
5112 static bool adjust_colour_depth_from_display_info(
5113         struct dc_crtc_timing *timing_out,
5114         const struct drm_display_info *info)
5115 {
5116         enum dc_color_depth depth = timing_out->display_color_depth;
5117         int normalized_clk;
5118         do {
5119                 normalized_clk = timing_out->pix_clk_100hz / 10;
5120                 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */
5121                 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
5122                         normalized_clk /= 2;
5123                 /* Adjusting pix clock following on HDMI spec based on colour depth */
5124                 switch (depth) {
5125                 case COLOR_DEPTH_888:
5126                         break;
5127                 case COLOR_DEPTH_101010:
5128                         normalized_clk = (normalized_clk * 30) / 24;
5129                         break;
5130                 case COLOR_DEPTH_121212:
5131                         normalized_clk = (normalized_clk * 36) / 24;
5132                         break;
5133                 case COLOR_DEPTH_161616:
5134                         normalized_clk = (normalized_clk * 48) / 24;
5135                         break;
5136                 default:
5137                         /* The above depths are the only ones valid for HDMI. */
5138                         return false;
5139                 }
5140                 if (normalized_clk <= info->max_tmds_clock) {
5141                         timing_out->display_color_depth = depth;
5142                         return true;
5143                 }
5144         } while (--depth > COLOR_DEPTH_666);
5145         return false;
5146 }
5147
5148 static void fill_stream_properties_from_drm_display_mode(
5149         struct dc_stream_state *stream,
5150         const struct drm_display_mode *mode_in,
5151         const struct drm_connector *connector,
5152         const struct drm_connector_state *connector_state,
5153         const struct dc_stream_state *old_stream,
5154         int requested_bpc)
5155 {
5156         struct dc_crtc_timing *timing_out = &stream->timing;
5157         const struct drm_display_info *info = &connector->display_info;
5158         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
5159         struct hdmi_vendor_infoframe hv_frame;
5160         struct hdmi_avi_infoframe avi_frame;
5161
5162         memset(&hv_frame, 0, sizeof(hv_frame));
5163         memset(&avi_frame, 0, sizeof(avi_frame));
5164
5165         timing_out->h_border_left = 0;
5166         timing_out->h_border_right = 0;
5167         timing_out->v_border_top = 0;
5168         timing_out->v_border_bottom = 0;
5169         /* TODO: un-hardcode */
5170         if (drm_mode_is_420_only(info, mode_in)
5171                         && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5172                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5173         else if (drm_mode_is_420_also(info, mode_in)
5174                         && aconnector->force_yuv420_output)
5175                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5176         else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR444)
5177                         && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5178                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
5179         else
5180                 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
5181
5182         timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
5183         timing_out->display_color_depth = convert_color_depth_from_display_info(
5184                 connector,
5185                 (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420),
5186                 requested_bpc);
5187         timing_out->scan_type = SCANNING_TYPE_NODATA;
5188         timing_out->hdmi_vic = 0;
5189
5190         if (old_stream) {
5191                 timing_out->vic = old_stream->timing.vic;
5192                 timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY;
5193                 timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY;
5194         } else {
5195                 timing_out->vic = drm_match_cea_mode(mode_in);
5196                 if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
5197                         timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
5198                 if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
5199                         timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
5200         }
5201
5202         if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
5203                 drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, (struct drm_connector *)connector, mode_in);
5204                 timing_out->vic = avi_frame.video_code;
5205                 drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, (struct drm_connector *)connector, mode_in);
5206                 timing_out->hdmi_vic = hv_frame.vic;
5207         }
5208
5209         if (is_freesync_video_mode(mode_in, aconnector)) {
5210                 timing_out->h_addressable = mode_in->hdisplay;
5211                 timing_out->h_total = mode_in->htotal;
5212                 timing_out->h_sync_width = mode_in->hsync_end - mode_in->hsync_start;
5213                 timing_out->h_front_porch = mode_in->hsync_start - mode_in->hdisplay;
5214                 timing_out->v_total = mode_in->vtotal;
5215                 timing_out->v_addressable = mode_in->vdisplay;
5216                 timing_out->v_front_porch = mode_in->vsync_start - mode_in->vdisplay;
5217                 timing_out->v_sync_width = mode_in->vsync_end - mode_in->vsync_start;
5218                 timing_out->pix_clk_100hz = mode_in->clock * 10;
5219         } else {
5220                 timing_out->h_addressable = mode_in->crtc_hdisplay;
5221                 timing_out->h_total = mode_in->crtc_htotal;
5222                 timing_out->h_sync_width = mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
5223                 timing_out->h_front_porch = mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
5224                 timing_out->v_total = mode_in->crtc_vtotal;
5225                 timing_out->v_addressable = mode_in->crtc_vdisplay;
5226                 timing_out->v_front_porch = mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
5227                 timing_out->v_sync_width = mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
5228                 timing_out->pix_clk_100hz = mode_in->crtc_clock * 10;
5229         }
5230
5231         timing_out->aspect_ratio = get_aspect_ratio(mode_in);
5232
5233         stream->output_color_space = get_output_color_space(timing_out);
5234
5235         stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
5236         stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
5237         if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
5238                 if (!adjust_colour_depth_from_display_info(timing_out, info) &&
5239                     drm_mode_is_420_also(info, mode_in) &&
5240                     timing_out->pixel_encoding != PIXEL_ENCODING_YCBCR420) {
5241                         timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
5242                         adjust_colour_depth_from_display_info(timing_out, info);
5243                 }
5244         }
5245 }
5246
5247 static void fill_audio_info(struct audio_info *audio_info,
5248                             const struct drm_connector *drm_connector,
5249                             const struct dc_sink *dc_sink)
5250 {
5251         int i = 0;
5252         int cea_revision = 0;
5253         const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
5254
5255         audio_info->manufacture_id = edid_caps->manufacturer_id;
5256         audio_info->product_id = edid_caps->product_id;
5257
5258         cea_revision = drm_connector->display_info.cea_rev;
5259
5260         strscpy(audio_info->display_name,
5261                 edid_caps->display_name,
5262                 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
5263
5264         if (cea_revision >= 3) {
5265                 audio_info->mode_count = edid_caps->audio_mode_count;
5266
5267                 for (i = 0; i < audio_info->mode_count; ++i) {
5268                         audio_info->modes[i].format_code =
5269                                         (enum audio_format_code)
5270                                         (edid_caps->audio_modes[i].format_code);
5271                         audio_info->modes[i].channel_count =
5272                                         edid_caps->audio_modes[i].channel_count;
5273                         audio_info->modes[i].sample_rates.all =
5274                                         edid_caps->audio_modes[i].sample_rate;
5275                         audio_info->modes[i].sample_size =
5276                                         edid_caps->audio_modes[i].sample_size;
5277                 }
5278         }
5279
5280         audio_info->flags.all = edid_caps->speaker_flags;
5281
5282         /* TODO: We only check for the progressive mode, check for interlace mode too */
5283         if (drm_connector->latency_present[0]) {
5284                 audio_info->video_latency = drm_connector->video_latency[0];
5285                 audio_info->audio_latency = drm_connector->audio_latency[0];
5286         }
5287
5288         /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
5289
5290 }
5291
5292 static void
5293 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
5294                                       struct drm_display_mode *dst_mode)
5295 {
5296         dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
5297         dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
5298         dst_mode->crtc_clock = src_mode->crtc_clock;
5299         dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
5300         dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
5301         dst_mode->crtc_hsync_start =  src_mode->crtc_hsync_start;
5302         dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
5303         dst_mode->crtc_htotal = src_mode->crtc_htotal;
5304         dst_mode->crtc_hskew = src_mode->crtc_hskew;
5305         dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
5306         dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
5307         dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
5308         dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
5309         dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
5310 }
5311
5312 static void
5313 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
5314                                         const struct drm_display_mode *native_mode,
5315                                         bool scale_enabled)
5316 {
5317         if (scale_enabled) {
5318                 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
5319         } else if (native_mode->clock == drm_mode->clock &&
5320                         native_mode->htotal == drm_mode->htotal &&
5321                         native_mode->vtotal == drm_mode->vtotal) {
5322                 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
5323         } else {
5324                 /* no scaling nor amdgpu inserted, no need to patch */
5325         }
5326 }
5327
5328 static struct dc_sink *
5329 create_fake_sink(struct amdgpu_dm_connector *aconnector)
5330 {
5331         struct dc_sink_init_data sink_init_data = { 0 };
5332         struct dc_sink *sink = NULL;
5333         sink_init_data.link = aconnector->dc_link;
5334         sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
5335
5336         sink = dc_sink_create(&sink_init_data);
5337         if (!sink) {
5338                 DRM_ERROR("Failed to create sink!\n");
5339                 return NULL;
5340         }
5341         sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
5342
5343         return sink;
5344 }
5345
5346 static void set_multisync_trigger_params(
5347                 struct dc_stream_state *stream)
5348 {
5349         struct dc_stream_state *master = NULL;
5350
5351         if (stream->triggered_crtc_reset.enabled) {
5352                 master = stream->triggered_crtc_reset.event_source;
5353                 stream->triggered_crtc_reset.event =
5354                         master->timing.flags.VSYNC_POSITIVE_POLARITY ?
5355                         CRTC_EVENT_VSYNC_RISING : CRTC_EVENT_VSYNC_FALLING;
5356                 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_PIXEL;
5357         }
5358 }
5359
5360 static void set_master_stream(struct dc_stream_state *stream_set[],
5361                               int stream_count)
5362 {
5363         int j, highest_rfr = 0, master_stream = 0;
5364
5365         for (j = 0;  j < stream_count; j++) {
5366                 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
5367                         int refresh_rate = 0;
5368
5369                         refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/
5370                                 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
5371                         if (refresh_rate > highest_rfr) {
5372                                 highest_rfr = refresh_rate;
5373                                 master_stream = j;
5374                         }
5375                 }
5376         }
5377         for (j = 0;  j < stream_count; j++) {
5378                 if (stream_set[j])
5379                         stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
5380         }
5381 }
5382
5383 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
5384 {
5385         int i = 0;
5386         struct dc_stream_state *stream;
5387
5388         if (context->stream_count < 2)
5389                 return;
5390         for (i = 0; i < context->stream_count ; i++) {
5391                 if (!context->streams[i])
5392                         continue;
5393                 /*
5394                  * TODO: add a function to read AMD VSDB bits and set
5395                  * crtc_sync_master.multi_sync_enabled flag
5396                  * For now it's set to false
5397                  */
5398         }
5399
5400         set_master_stream(context->streams, context->stream_count);
5401
5402         for (i = 0; i < context->stream_count ; i++) {
5403                 stream = context->streams[i];
5404
5405                 if (!stream)
5406                         continue;
5407
5408                 set_multisync_trigger_params(stream);
5409         }
5410 }
5411
5412 /**
5413  * DOC: FreeSync Video
5414  *
5415  * When a userspace application wants to play a video, the content follows a
5416  * standard format definition that usually specifies the FPS for that format.
5417  * The below list illustrates some video format and the expected FPS,
5418  * respectively:
5419  *
5420  * - TV/NTSC (23.976 FPS)
5421  * - Cinema (24 FPS)
5422  * - TV/PAL (25 FPS)
5423  * - TV/NTSC (29.97 FPS)
5424  * - TV/NTSC (30 FPS)
5425  * - Cinema HFR (48 FPS)
5426  * - TV/PAL (50 FPS)
5427  * - Commonly used (60 FPS)
5428  * - Multiples of 24 (48,72,96 FPS)
5429  *
5430  * The list of standards video format is not huge and can be added to the
5431  * connector modeset list beforehand. With that, userspace can leverage
5432  * FreeSync to extends the front porch in order to attain the target refresh
5433  * rate. Such a switch will happen seamlessly, without screen blanking or
5434  * reprogramming of the output in any other way. If the userspace requests a
5435  * modesetting change compatible with FreeSync modes that only differ in the
5436  * refresh rate, DC will skip the full update and avoid blink during the
5437  * transition. For example, the video player can change the modesetting from
5438  * 60Hz to 30Hz for playing TV/NTSC content when it goes full screen without
5439  * causing any display blink. This same concept can be applied to a mode
5440  * setting change.
5441  */
5442 static struct drm_display_mode *
5443 get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector,
5444                 bool use_probed_modes)
5445 {
5446         struct drm_display_mode *m, *m_pref = NULL;
5447         u16 current_refresh, highest_refresh;
5448         struct list_head *list_head = use_probed_modes ?
5449                 &aconnector->base.probed_modes :
5450                 &aconnector->base.modes;
5451
5452         if (aconnector->freesync_vid_base.clock != 0)
5453                 return &aconnector->freesync_vid_base;
5454
5455         /* Find the preferred mode */
5456         list_for_each_entry (m, list_head, head) {
5457                 if (m->type & DRM_MODE_TYPE_PREFERRED) {
5458                         m_pref = m;
5459                         break;
5460                 }
5461         }
5462
5463         if (!m_pref) {
5464                 /* Probably an EDID with no preferred mode. Fallback to first entry */
5465                 m_pref = list_first_entry_or_null(
5466                                 &aconnector->base.modes, struct drm_display_mode, head);
5467                 if (!m_pref) {
5468                         DRM_DEBUG_DRIVER("No preferred mode found in EDID\n");
5469                         return NULL;
5470                 }
5471         }
5472
5473         highest_refresh = drm_mode_vrefresh(m_pref);
5474
5475         /*
5476          * Find the mode with highest refresh rate with same resolution.
5477          * For some monitors, preferred mode is not the mode with highest
5478          * supported refresh rate.
5479          */
5480         list_for_each_entry (m, list_head, head) {
5481                 current_refresh  = drm_mode_vrefresh(m);
5482
5483                 if (m->hdisplay == m_pref->hdisplay &&
5484                     m->vdisplay == m_pref->vdisplay &&
5485                     highest_refresh < current_refresh) {
5486                         highest_refresh = current_refresh;
5487                         m_pref = m;
5488                 }
5489         }
5490
5491         drm_mode_copy(&aconnector->freesync_vid_base, m_pref);
5492         return m_pref;
5493 }
5494
5495 static bool is_freesync_video_mode(const struct drm_display_mode *mode,
5496                 struct amdgpu_dm_connector *aconnector)
5497 {
5498         struct drm_display_mode *high_mode;
5499         int timing_diff;
5500
5501         high_mode = get_highest_refresh_rate_mode(aconnector, false);
5502         if (!high_mode || !mode)
5503                 return false;
5504
5505         timing_diff = high_mode->vtotal - mode->vtotal;
5506
5507         if (high_mode->clock == 0 || high_mode->clock != mode->clock ||
5508             high_mode->hdisplay != mode->hdisplay ||
5509             high_mode->vdisplay != mode->vdisplay ||
5510             high_mode->hsync_start != mode->hsync_start ||
5511             high_mode->hsync_end != mode->hsync_end ||
5512             high_mode->htotal != mode->htotal ||
5513             high_mode->hskew != mode->hskew ||
5514             high_mode->vscan != mode->vscan ||
5515             high_mode->vsync_start - mode->vsync_start != timing_diff ||
5516             high_mode->vsync_end - mode->vsync_end != timing_diff)
5517                 return false;
5518         else
5519                 return true;
5520 }
5521
5522 #if defined(CONFIG_DRM_AMD_DC_DCN)
5523 static void update_dsc_caps(struct amdgpu_dm_connector *aconnector,
5524                             struct dc_sink *sink, struct dc_stream_state *stream,
5525                             struct dsc_dec_dpcd_caps *dsc_caps)
5526 {
5527         stream->timing.flags.DSC = 0;
5528         dsc_caps->is_dsc_supported = false;
5529
5530         if (aconnector->dc_link && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT ||
5531             sink->sink_signal == SIGNAL_TYPE_EDP)) {
5532                 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE ||
5533                         sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER)
5534                         dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
5535                                 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
5536                                 aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
5537                                 dsc_caps);
5538         }
5539 }
5540
5541
5542 static void apply_dsc_policy_for_edp(struct amdgpu_dm_connector *aconnector,
5543                                     struct dc_sink *sink, struct dc_stream_state *stream,
5544                                     struct dsc_dec_dpcd_caps *dsc_caps,
5545                                     uint32_t max_dsc_target_bpp_limit_override)
5546 {
5547         const struct dc_link_settings *verified_link_cap = NULL;
5548         uint32_t link_bw_in_kbps;
5549         uint32_t edp_min_bpp_x16, edp_max_bpp_x16;
5550         struct dc *dc = sink->ctx->dc;
5551         struct dc_dsc_bw_range bw_range = {0};
5552         struct dc_dsc_config dsc_cfg = {0};
5553
5554         verified_link_cap = dc_link_get_link_cap(stream->link);
5555         link_bw_in_kbps = dc_link_bandwidth_kbps(stream->link, verified_link_cap);
5556         edp_min_bpp_x16 = 8 * 16;
5557         edp_max_bpp_x16 = 8 * 16;
5558
5559         if (edp_max_bpp_x16 > dsc_caps->edp_max_bits_per_pixel)
5560                 edp_max_bpp_x16 = dsc_caps->edp_max_bits_per_pixel;
5561
5562         if (edp_max_bpp_x16 < edp_min_bpp_x16)
5563                 edp_min_bpp_x16 = edp_max_bpp_x16;
5564
5565         if (dc_dsc_compute_bandwidth_range(dc->res_pool->dscs[0],
5566                                 dc->debug.dsc_min_slice_height_override,
5567                                 edp_min_bpp_x16, edp_max_bpp_x16,
5568                                 dsc_caps,
5569                                 &stream->timing,
5570                                 &bw_range)) {
5571
5572                 if (bw_range.max_kbps < link_bw_in_kbps) {
5573                         if (dc_dsc_compute_config(dc->res_pool->dscs[0],
5574                                         dsc_caps,
5575                                         dc->debug.dsc_min_slice_height_override,
5576                                         max_dsc_target_bpp_limit_override,
5577                                         0,
5578                                         &stream->timing,
5579                                         &dsc_cfg)) {
5580                                 stream->timing.dsc_cfg = dsc_cfg;
5581                                 stream->timing.flags.DSC = 1;
5582                                 stream->timing.dsc_cfg.bits_per_pixel = edp_max_bpp_x16;
5583                         }
5584                         return;
5585                 }
5586         }
5587
5588         if (dc_dsc_compute_config(dc->res_pool->dscs[0],
5589                                 dsc_caps,
5590                                 dc->debug.dsc_min_slice_height_override,
5591                                 max_dsc_target_bpp_limit_override,
5592                                 link_bw_in_kbps,
5593                                 &stream->timing,
5594                                 &dsc_cfg)) {
5595                 stream->timing.dsc_cfg = dsc_cfg;
5596                 stream->timing.flags.DSC = 1;
5597         }
5598 }
5599
5600
5601 static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector,
5602                                         struct dc_sink *sink, struct dc_stream_state *stream,
5603                                         struct dsc_dec_dpcd_caps *dsc_caps)
5604 {
5605         struct drm_connector *drm_connector = &aconnector->base;
5606         uint32_t link_bandwidth_kbps;
5607         uint32_t max_dsc_target_bpp_limit_override = 0;
5608         struct dc *dc = sink->ctx->dc;
5609         uint32_t max_supported_bw_in_kbps, timing_bw_in_kbps;
5610         uint32_t dsc_max_supported_bw_in_kbps;
5611
5612         link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
5613                                                         dc_link_get_link_cap(aconnector->dc_link));
5614         if (stream->link && stream->link->local_sink)
5615                 max_dsc_target_bpp_limit_override =
5616                         stream->link->local_sink->edid_caps.panel_patch.max_dsc_target_bpp_limit;
5617
5618         /* Set DSC policy according to dsc_clock_en */
5619         dc_dsc_policy_set_enable_dsc_when_not_needed(
5620                 aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE);
5621
5622         if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_EDP &&
5623             !aconnector->dc_link->panel_config.dsc.disable_dsc_edp &&
5624             dc->caps.edp_dsc_support && aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE) {
5625
5626                 apply_dsc_policy_for_edp(aconnector, sink, stream, dsc_caps, max_dsc_target_bpp_limit_override);
5627
5628         } else if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) {
5629                 if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) {
5630                         if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
5631                                                 dsc_caps,
5632                                                 aconnector->dc_link->ctx->dc->debug.dsc_min_slice_height_override,
5633                                                 max_dsc_target_bpp_limit_override,
5634                                                 link_bandwidth_kbps,
5635                                                 &stream->timing,
5636                                                 &stream->timing.dsc_cfg)) {
5637                                 stream->timing.flags.DSC = 1;
5638                                 DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from SST RX\n", __func__, drm_connector->name);
5639                         }
5640                 } else if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) {
5641                         timing_bw_in_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing);
5642                         max_supported_bw_in_kbps = link_bandwidth_kbps;
5643                         dsc_max_supported_bw_in_kbps = link_bandwidth_kbps;
5644
5645                         if (timing_bw_in_kbps > max_supported_bw_in_kbps &&
5646                                         max_supported_bw_in_kbps > 0 &&
5647                                         dsc_max_supported_bw_in_kbps > 0)
5648                                 if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
5649                                                 dsc_caps,
5650                                                 aconnector->dc_link->ctx->dc->debug.dsc_min_slice_height_override,
5651                                                 max_dsc_target_bpp_limit_override,
5652                                                 dsc_max_supported_bw_in_kbps,
5653                                                 &stream->timing,
5654                                                 &stream->timing.dsc_cfg)) {
5655                                         stream->timing.flags.DSC = 1;
5656                                         DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from DP-HDMI PCON\n",
5657                                                                          __func__, drm_connector->name);
5658                                 }
5659                 }
5660         }
5661
5662         /* Overwrite the stream flag if DSC is enabled through debugfs */
5663         if (aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE)
5664                 stream->timing.flags.DSC = 1;
5665
5666         if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_h)
5667                 stream->timing.dsc_cfg.num_slices_h = aconnector->dsc_settings.dsc_num_slices_h;
5668
5669         if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_v)
5670                 stream->timing.dsc_cfg.num_slices_v = aconnector->dsc_settings.dsc_num_slices_v;
5671
5672         if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_bits_per_pixel)
5673                 stream->timing.dsc_cfg.bits_per_pixel = aconnector->dsc_settings.dsc_bits_per_pixel;
5674 }
5675 #endif /* CONFIG_DRM_AMD_DC_DCN */
5676
5677 static struct dc_stream_state *
5678 create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
5679                        const struct drm_display_mode *drm_mode,
5680                        const struct dm_connector_state *dm_state,
5681                        const struct dc_stream_state *old_stream,
5682                        int requested_bpc)
5683 {
5684         struct drm_display_mode *preferred_mode = NULL;
5685         struct drm_connector *drm_connector;
5686         const struct drm_connector_state *con_state =
5687                 dm_state ? &dm_state->base : NULL;
5688         struct dc_stream_state *stream = NULL;
5689         struct drm_display_mode mode = *drm_mode;
5690         struct drm_display_mode saved_mode;
5691         struct drm_display_mode *freesync_mode = NULL;
5692         bool native_mode_found = false;
5693         bool recalculate_timing = false;
5694         bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false;
5695         int mode_refresh;
5696         int preferred_refresh = 0;
5697 #if defined(CONFIG_DRM_AMD_DC_DCN)
5698         struct dsc_dec_dpcd_caps dsc_caps;
5699 #endif
5700
5701         struct dc_sink *sink = NULL;
5702
5703         memset(&saved_mode, 0, sizeof(saved_mode));
5704
5705         if (aconnector == NULL) {
5706                 DRM_ERROR("aconnector is NULL!\n");
5707                 return stream;
5708         }
5709
5710         drm_connector = &aconnector->base;
5711
5712         if (!aconnector->dc_sink) {
5713                 sink = create_fake_sink(aconnector);
5714                 if (!sink)
5715                         return stream;
5716         } else {
5717                 sink = aconnector->dc_sink;
5718                 dc_sink_retain(sink);
5719         }
5720
5721         stream = dc_create_stream_for_sink(sink);
5722
5723         if (stream == NULL) {
5724                 DRM_ERROR("Failed to create stream for sink!\n");
5725                 goto finish;
5726         }
5727
5728         stream->dm_stream_context = aconnector;
5729
5730         stream->timing.flags.LTE_340MCSC_SCRAMBLE =
5731                 drm_connector->display_info.hdmi.scdc.scrambling.low_rates;
5732
5733         list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
5734                 /* Search for preferred mode */
5735                 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
5736                         native_mode_found = true;
5737                         break;
5738                 }
5739         }
5740         if (!native_mode_found)
5741                 preferred_mode = list_first_entry_or_null(
5742                                 &aconnector->base.modes,
5743                                 struct drm_display_mode,
5744                                 head);
5745
5746         mode_refresh = drm_mode_vrefresh(&mode);
5747
5748         if (preferred_mode == NULL) {
5749                 /*
5750                  * This may not be an error, the use case is when we have no
5751                  * usermode calls to reset and set mode upon hotplug. In this
5752                  * case, we call set mode ourselves to restore the previous mode
5753                  * and the modelist may not be filled in in time.
5754                  */
5755                 DRM_DEBUG_DRIVER("No preferred mode found\n");
5756         } else {
5757                 recalculate_timing = is_freesync_video_mode(&mode, aconnector);
5758                 if (recalculate_timing) {
5759                         freesync_mode = get_highest_refresh_rate_mode(aconnector, false);
5760                         drm_mode_copy(&saved_mode, &mode);
5761                         drm_mode_copy(&mode, freesync_mode);
5762                 } else {
5763                         decide_crtc_timing_for_drm_display_mode(
5764                                         &mode, preferred_mode, scale);
5765
5766                         preferred_refresh = drm_mode_vrefresh(preferred_mode);
5767                 }
5768         }
5769
5770         if (recalculate_timing)
5771                 drm_mode_set_crtcinfo(&saved_mode, 0);
5772         else if (!dm_state)
5773                 drm_mode_set_crtcinfo(&mode, 0);
5774
5775         /*
5776         * If scaling is enabled and refresh rate didn't change
5777         * we copy the vic and polarities of the old timings
5778         */
5779         if (!scale || mode_refresh != preferred_refresh)
5780                 fill_stream_properties_from_drm_display_mode(
5781                         stream, &mode, &aconnector->base, con_state, NULL,
5782                         requested_bpc);
5783         else
5784                 fill_stream_properties_from_drm_display_mode(
5785                         stream, &mode, &aconnector->base, con_state, old_stream,
5786                         requested_bpc);
5787
5788 #if defined(CONFIG_DRM_AMD_DC_DCN)
5789         /* SST DSC determination policy */
5790         update_dsc_caps(aconnector, sink, stream, &dsc_caps);
5791         if (aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE && dsc_caps.is_dsc_supported)
5792                 apply_dsc_policy_for_stream(aconnector, sink, stream, &dsc_caps);
5793 #endif
5794
5795         update_stream_scaling_settings(&mode, dm_state, stream);
5796
5797         fill_audio_info(
5798                 &stream->audio_info,
5799                 drm_connector,
5800                 sink);
5801
5802         update_stream_signal(stream, sink);
5803
5804         if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
5805                 mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket);
5806
5807         if (stream->link->psr_settings.psr_feature_enabled) {
5808                 //
5809                 // should decide stream support vsc sdp colorimetry capability
5810                 // before building vsc info packet
5811                 //
5812                 stream->use_vsc_sdp_for_colorimetry = false;
5813                 if (aconnector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
5814                         stream->use_vsc_sdp_for_colorimetry =
5815                                 aconnector->dc_sink->is_vsc_sdp_colorimetry_supported;
5816                 } else {
5817                         if (stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED)
5818                                 stream->use_vsc_sdp_for_colorimetry = true;
5819                 }
5820                 mod_build_vsc_infopacket(stream, &stream->vsc_infopacket, stream->output_color_space);
5821                 aconnector->psr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY;
5822
5823         }
5824 finish:
5825         dc_sink_release(sink);
5826
5827         return stream;
5828 }
5829
5830 static enum drm_connector_status
5831 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
5832 {
5833         bool connected;
5834         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
5835
5836         /*
5837          * Notes:
5838          * 1. This interface is NOT called in context of HPD irq.
5839          * 2. This interface *is called* in context of user-mode ioctl. Which
5840          * makes it a bad place for *any* MST-related activity.
5841          */
5842
5843         if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
5844             !aconnector->fake_enable)
5845                 connected = (aconnector->dc_sink != NULL);
5846         else
5847                 connected = (aconnector->base.force == DRM_FORCE_ON ||
5848                                 aconnector->base.force == DRM_FORCE_ON_DIGITAL);
5849
5850         update_subconnector_property(aconnector);
5851
5852         return (connected ? connector_status_connected :
5853                         connector_status_disconnected);
5854 }
5855
5856 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
5857                                             struct drm_connector_state *connector_state,
5858                                             struct drm_property *property,
5859                                             uint64_t val)
5860 {
5861         struct drm_device *dev = connector->dev;
5862         struct amdgpu_device *adev = drm_to_adev(dev);
5863         struct dm_connector_state *dm_old_state =
5864                 to_dm_connector_state(connector->state);
5865         struct dm_connector_state *dm_new_state =
5866                 to_dm_connector_state(connector_state);
5867
5868         int ret = -EINVAL;
5869
5870         if (property == dev->mode_config.scaling_mode_property) {
5871                 enum amdgpu_rmx_type rmx_type;
5872
5873                 switch (val) {
5874                 case DRM_MODE_SCALE_CENTER:
5875                         rmx_type = RMX_CENTER;
5876                         break;
5877                 case DRM_MODE_SCALE_ASPECT:
5878                         rmx_type = RMX_ASPECT;
5879                         break;
5880                 case DRM_MODE_SCALE_FULLSCREEN:
5881                         rmx_type = RMX_FULL;
5882                         break;
5883                 case DRM_MODE_SCALE_NONE:
5884                 default:
5885                         rmx_type = RMX_OFF;
5886                         break;
5887                 }
5888
5889                 if (dm_old_state->scaling == rmx_type)
5890                         return 0;
5891
5892                 dm_new_state->scaling = rmx_type;
5893                 ret = 0;
5894         } else if (property == adev->mode_info.underscan_hborder_property) {
5895                 dm_new_state->underscan_hborder = val;
5896                 ret = 0;
5897         } else if (property == adev->mode_info.underscan_vborder_property) {
5898                 dm_new_state->underscan_vborder = val;
5899                 ret = 0;
5900         } else if (property == adev->mode_info.underscan_property) {
5901                 dm_new_state->underscan_enable = val;
5902                 ret = 0;
5903         } else if (property == adev->mode_info.abm_level_property) {
5904                 dm_new_state->abm_level = val;
5905                 ret = 0;
5906         }
5907
5908         return ret;
5909 }
5910
5911 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
5912                                             const struct drm_connector_state *state,
5913                                             struct drm_property *property,
5914                                             uint64_t *val)
5915 {
5916         struct drm_device *dev = connector->dev;
5917         struct amdgpu_device *adev = drm_to_adev(dev);
5918         struct dm_connector_state *dm_state =
5919                 to_dm_connector_state(state);
5920         int ret = -EINVAL;
5921
5922         if (property == dev->mode_config.scaling_mode_property) {
5923                 switch (dm_state->scaling) {
5924                 case RMX_CENTER:
5925                         *val = DRM_MODE_SCALE_CENTER;
5926                         break;
5927                 case RMX_ASPECT:
5928                         *val = DRM_MODE_SCALE_ASPECT;
5929                         break;
5930                 case RMX_FULL:
5931                         *val = DRM_MODE_SCALE_FULLSCREEN;
5932                         break;
5933                 case RMX_OFF:
5934                 default:
5935                         *val = DRM_MODE_SCALE_NONE;
5936                         break;
5937                 }
5938                 ret = 0;
5939         } else if (property == adev->mode_info.underscan_hborder_property) {
5940                 *val = dm_state->underscan_hborder;
5941                 ret = 0;
5942         } else if (property == adev->mode_info.underscan_vborder_property) {
5943                 *val = dm_state->underscan_vborder;
5944                 ret = 0;
5945         } else if (property == adev->mode_info.underscan_property) {
5946                 *val = dm_state->underscan_enable;
5947                 ret = 0;
5948         } else if (property == adev->mode_info.abm_level_property) {
5949                 *val = dm_state->abm_level;
5950                 ret = 0;
5951         }
5952
5953         return ret;
5954 }
5955
5956 static void amdgpu_dm_connector_unregister(struct drm_connector *connector)
5957 {
5958         struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector);
5959
5960         drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux);
5961 }
5962
5963 static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
5964 {
5965         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
5966         const struct dc_link *link = aconnector->dc_link;
5967         struct amdgpu_device *adev = drm_to_adev(connector->dev);
5968         struct amdgpu_display_manager *dm = &adev->dm;
5969         int i;
5970
5971         /*
5972          * Call only if mst_mgr was initialized before since it's not done
5973          * for all connector types.
5974          */
5975         if (aconnector->mst_mgr.dev)
5976                 drm_dp_mst_topology_mgr_destroy(&aconnector->mst_mgr);
5977
5978 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
5979         defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
5980         for (i = 0; i < dm->num_of_edps; i++) {
5981                 if ((link == dm->backlight_link[i]) && dm->backlight_dev[i]) {
5982                         backlight_device_unregister(dm->backlight_dev[i]);
5983                         dm->backlight_dev[i] = NULL;
5984                 }
5985         }
5986 #endif
5987
5988         if (aconnector->dc_em_sink)
5989                 dc_sink_release(aconnector->dc_em_sink);
5990         aconnector->dc_em_sink = NULL;
5991         if (aconnector->dc_sink)
5992                 dc_sink_release(aconnector->dc_sink);
5993         aconnector->dc_sink = NULL;
5994
5995         drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux);
5996         drm_connector_unregister(connector);
5997         drm_connector_cleanup(connector);
5998         if (aconnector->i2c) {
5999                 i2c_del_adapter(&aconnector->i2c->base);
6000                 kfree(aconnector->i2c);
6001         }
6002         kfree(aconnector->dm_dp_aux.aux.name);
6003
6004         kfree(connector);
6005 }
6006
6007 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
6008 {
6009         struct dm_connector_state *state =
6010                 to_dm_connector_state(connector->state);
6011
6012         if (connector->state)
6013                 __drm_atomic_helper_connector_destroy_state(connector->state);
6014
6015         kfree(state);
6016
6017         state = kzalloc(sizeof(*state), GFP_KERNEL);
6018
6019         if (state) {
6020                 state->scaling = RMX_OFF;
6021                 state->underscan_enable = false;
6022                 state->underscan_hborder = 0;
6023                 state->underscan_vborder = 0;
6024                 state->base.max_requested_bpc = 8;
6025                 state->vcpi_slots = 0;
6026                 state->pbn = 0;
6027
6028                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
6029                         state->abm_level = amdgpu_dm_abm_level;
6030
6031                 __drm_atomic_helper_connector_reset(connector, &state->base);
6032         }
6033 }
6034
6035 struct drm_connector_state *
6036 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
6037 {
6038         struct dm_connector_state *state =
6039                 to_dm_connector_state(connector->state);
6040
6041         struct dm_connector_state *new_state =
6042                         kmemdup(state, sizeof(*state), GFP_KERNEL);
6043
6044         if (!new_state)
6045                 return NULL;
6046
6047         __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
6048
6049         new_state->freesync_capable = state->freesync_capable;
6050         new_state->abm_level = state->abm_level;
6051         new_state->scaling = state->scaling;
6052         new_state->underscan_enable = state->underscan_enable;
6053         new_state->underscan_hborder = state->underscan_hborder;
6054         new_state->underscan_vborder = state->underscan_vborder;
6055         new_state->vcpi_slots = state->vcpi_slots;
6056         new_state->pbn = state->pbn;
6057         return &new_state->base;
6058 }
6059
6060 static int
6061 amdgpu_dm_connector_late_register(struct drm_connector *connector)
6062 {
6063         struct amdgpu_dm_connector *amdgpu_dm_connector =
6064                 to_amdgpu_dm_connector(connector);
6065         int r;
6066
6067         if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
6068             (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
6069                 amdgpu_dm_connector->dm_dp_aux.aux.dev = connector->kdev;
6070                 r = drm_dp_aux_register(&amdgpu_dm_connector->dm_dp_aux.aux);
6071                 if (r)
6072                         return r;
6073         }
6074
6075 #if defined(CONFIG_DEBUG_FS)
6076         connector_debugfs_init(amdgpu_dm_connector);
6077 #endif
6078
6079         return 0;
6080 }
6081
6082 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
6083         .reset = amdgpu_dm_connector_funcs_reset,
6084         .detect = amdgpu_dm_connector_detect,
6085         .fill_modes = drm_helper_probe_single_connector_modes,
6086         .destroy = amdgpu_dm_connector_destroy,
6087         .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
6088         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
6089         .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
6090         .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
6091         .late_register = amdgpu_dm_connector_late_register,
6092         .early_unregister = amdgpu_dm_connector_unregister
6093 };
6094
6095 static int get_modes(struct drm_connector *connector)
6096 {
6097         return amdgpu_dm_connector_get_modes(connector);
6098 }
6099
6100 static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
6101 {
6102         struct dc_sink_init_data init_params = {
6103                         .link = aconnector->dc_link,
6104                         .sink_signal = SIGNAL_TYPE_VIRTUAL
6105         };
6106         struct edid *edid;
6107
6108         if (!aconnector->base.edid_blob_ptr) {
6109                 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
6110                                 aconnector->base.name);
6111
6112                 aconnector->base.force = DRM_FORCE_OFF;
6113                 aconnector->base.override_edid = false;
6114                 return;
6115         }
6116
6117         edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
6118
6119         aconnector->edid = edid;
6120
6121         aconnector->dc_em_sink = dc_link_add_remote_sink(
6122                 aconnector->dc_link,
6123                 (uint8_t *)edid,
6124                 (edid->extensions + 1) * EDID_LENGTH,
6125                 &init_params);
6126
6127         if (aconnector->base.force == DRM_FORCE_ON) {
6128                 aconnector->dc_sink = aconnector->dc_link->local_sink ?
6129                 aconnector->dc_link->local_sink :
6130                 aconnector->dc_em_sink;
6131                 dc_sink_retain(aconnector->dc_sink);
6132         }
6133 }
6134
6135 static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
6136 {
6137         struct dc_link *link = (struct dc_link *)aconnector->dc_link;
6138
6139         /*
6140          * In case of headless boot with force on for DP managed connector
6141          * Those settings have to be != 0 to get initial modeset
6142          */
6143         if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
6144                 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
6145                 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
6146         }
6147
6148
6149         aconnector->base.override_edid = true;
6150         create_eml_sink(aconnector);
6151 }
6152
6153 struct dc_stream_state *
6154 create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector,
6155                                 const struct drm_display_mode *drm_mode,
6156                                 const struct dm_connector_state *dm_state,
6157                                 const struct dc_stream_state *old_stream)
6158 {
6159         struct drm_connector *connector = &aconnector->base;
6160         struct amdgpu_device *adev = drm_to_adev(connector->dev);
6161         struct dc_stream_state *stream;
6162         const struct drm_connector_state *drm_state = dm_state ? &dm_state->base : NULL;
6163         int requested_bpc = drm_state ? drm_state->max_requested_bpc : 8;
6164         enum dc_status dc_result = DC_OK;
6165
6166         do {
6167                 stream = create_stream_for_sink(aconnector, drm_mode,
6168                                                 dm_state, old_stream,
6169                                                 requested_bpc);
6170                 if (stream == NULL) {
6171                         DRM_ERROR("Failed to create stream for sink!\n");
6172                         break;
6173                 }
6174
6175                 dc_result = dc_validate_stream(adev->dm.dc, stream);
6176                 if (dc_result == DC_OK && stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
6177                         dc_result = dm_dp_mst_is_port_support_mode(aconnector, stream);
6178
6179                 if (dc_result != DC_OK) {
6180                         DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n",
6181                                       drm_mode->hdisplay,
6182                                       drm_mode->vdisplay,
6183                                       drm_mode->clock,
6184                                       dc_result,
6185                                       dc_status_to_str(dc_result));
6186
6187                         dc_stream_release(stream);
6188                         stream = NULL;
6189                         requested_bpc -= 2; /* lower bpc to retry validation */
6190                 }
6191
6192         } while (stream == NULL && requested_bpc >= 6);
6193
6194         if (dc_result == DC_FAIL_ENC_VALIDATE && !aconnector->force_yuv420_output) {
6195                 DRM_DEBUG_KMS("Retry forcing YCbCr420 encoding\n");
6196
6197                 aconnector->force_yuv420_output = true;
6198                 stream = create_validate_stream_for_sink(aconnector, drm_mode,
6199                                                 dm_state, old_stream);
6200                 aconnector->force_yuv420_output = false;
6201         }
6202
6203         return stream;
6204 }
6205
6206 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
6207                                    struct drm_display_mode *mode)
6208 {
6209         int result = MODE_ERROR;
6210         struct dc_sink *dc_sink;
6211         /* TODO: Unhardcode stream count */
6212         struct dc_stream_state *stream;
6213         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6214
6215         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
6216                         (mode->flags & DRM_MODE_FLAG_DBLSCAN))
6217                 return result;
6218
6219         /*
6220          * Only run this the first time mode_valid is called to initilialize
6221          * EDID mgmt
6222          */
6223         if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
6224                 !aconnector->dc_em_sink)
6225                 handle_edid_mgmt(aconnector);
6226
6227         dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
6228
6229         if (dc_sink == NULL && aconnector->base.force != DRM_FORCE_ON_DIGITAL &&
6230                                 aconnector->base.force != DRM_FORCE_ON) {
6231                 DRM_ERROR("dc_sink is NULL!\n");
6232                 goto fail;
6233         }
6234
6235         stream = create_validate_stream_for_sink(aconnector, mode, NULL, NULL);
6236         if (stream) {
6237                 dc_stream_release(stream);
6238                 result = MODE_OK;
6239         }
6240
6241 fail:
6242         /* TODO: error handling*/
6243         return result;
6244 }
6245
6246 static int fill_hdr_info_packet(const struct drm_connector_state *state,
6247                                 struct dc_info_packet *out)
6248 {
6249         struct hdmi_drm_infoframe frame;
6250         unsigned char buf[30]; /* 26 + 4 */
6251         ssize_t len;
6252         int ret, i;
6253
6254         memset(out, 0, sizeof(*out));
6255
6256         if (!state->hdr_output_metadata)
6257                 return 0;
6258
6259         ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state);
6260         if (ret)
6261                 return ret;
6262
6263         len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf));
6264         if (len < 0)
6265                 return (int)len;
6266
6267         /* Static metadata is a fixed 26 bytes + 4 byte header. */
6268         if (len != 30)
6269                 return -EINVAL;
6270
6271         /* Prepare the infopacket for DC. */
6272         switch (state->connector->connector_type) {
6273         case DRM_MODE_CONNECTOR_HDMIA:
6274                 out->hb0 = 0x87; /* type */
6275                 out->hb1 = 0x01; /* version */
6276                 out->hb2 = 0x1A; /* length */
6277                 out->sb[0] = buf[3]; /* checksum */
6278                 i = 1;
6279                 break;
6280
6281         case DRM_MODE_CONNECTOR_DisplayPort:
6282         case DRM_MODE_CONNECTOR_eDP:
6283                 out->hb0 = 0x00; /* sdp id, zero */
6284                 out->hb1 = 0x87; /* type */
6285                 out->hb2 = 0x1D; /* payload len - 1 */
6286                 out->hb3 = (0x13 << 2); /* sdp version */
6287                 out->sb[0] = 0x01; /* version */
6288                 out->sb[1] = 0x1A; /* length */
6289                 i = 2;
6290                 break;
6291
6292         default:
6293                 return -EINVAL;
6294         }
6295
6296         memcpy(&out->sb[i], &buf[4], 26);
6297         out->valid = true;
6298
6299         print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb,
6300                        sizeof(out->sb), false);
6301
6302         return 0;
6303 }
6304
6305 static int
6306 amdgpu_dm_connector_atomic_check(struct drm_connector *conn,
6307                                  struct drm_atomic_state *state)
6308 {
6309         struct drm_connector_state *new_con_state =
6310                 drm_atomic_get_new_connector_state(state, conn);
6311         struct drm_connector_state *old_con_state =
6312                 drm_atomic_get_old_connector_state(state, conn);
6313         struct drm_crtc *crtc = new_con_state->crtc;
6314         struct drm_crtc_state *new_crtc_state;
6315         struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(conn);
6316         int ret;
6317
6318         trace_amdgpu_dm_connector_atomic_check(new_con_state);
6319
6320         if (conn->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
6321                 ret = drm_dp_mst_root_conn_atomic_check(new_con_state, &aconn->mst_mgr);
6322                 if (ret < 0)
6323                         return ret;
6324         }
6325
6326         if (!crtc)
6327                 return 0;
6328
6329         if (!drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state)) {
6330                 struct dc_info_packet hdr_infopacket;
6331
6332                 ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket);
6333                 if (ret)
6334                         return ret;
6335
6336                 new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
6337                 if (IS_ERR(new_crtc_state))
6338                         return PTR_ERR(new_crtc_state);
6339
6340                 /*
6341                  * DC considers the stream backends changed if the
6342                  * static metadata changes. Forcing the modeset also
6343                  * gives a simple way for userspace to switch from
6344                  * 8bpc to 10bpc when setting the metadata to enter
6345                  * or exit HDR.
6346                  *
6347                  * Changing the static metadata after it's been
6348                  * set is permissible, however. So only force a
6349                  * modeset if we're entering or exiting HDR.
6350                  */
6351                 new_crtc_state->mode_changed =
6352                         !old_con_state->hdr_output_metadata ||
6353                         !new_con_state->hdr_output_metadata;
6354         }
6355
6356         return 0;
6357 }
6358
6359 static const struct drm_connector_helper_funcs
6360 amdgpu_dm_connector_helper_funcs = {
6361         /*
6362          * If hotplugging a second bigger display in FB Con mode, bigger resolution
6363          * modes will be filtered by drm_mode_validate_size(), and those modes
6364          * are missing after user start lightdm. So we need to renew modes list.
6365          * in get_modes call back, not just return the modes count
6366          */
6367         .get_modes = get_modes,
6368         .mode_valid = amdgpu_dm_connector_mode_valid,
6369         .atomic_check = amdgpu_dm_connector_atomic_check,
6370 };
6371
6372 static void dm_encoder_helper_disable(struct drm_encoder *encoder)
6373 {
6374
6375 }
6376
6377 int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth)
6378 {
6379         switch (display_color_depth) {
6380         case COLOR_DEPTH_666:
6381                 return 6;
6382         case COLOR_DEPTH_888:
6383                 return 8;
6384         case COLOR_DEPTH_101010:
6385                 return 10;
6386         case COLOR_DEPTH_121212:
6387                 return 12;
6388         case COLOR_DEPTH_141414:
6389                 return 14;
6390         case COLOR_DEPTH_161616:
6391                 return 16;
6392         default:
6393                 break;
6394         }
6395         return 0;
6396 }
6397
6398 static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
6399                                           struct drm_crtc_state *crtc_state,
6400                                           struct drm_connector_state *conn_state)
6401 {
6402         struct drm_atomic_state *state = crtc_state->state;
6403         struct drm_connector *connector = conn_state->connector;
6404         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
6405         struct dm_connector_state *dm_new_connector_state = to_dm_connector_state(conn_state);
6406         const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
6407         struct drm_dp_mst_topology_mgr *mst_mgr;
6408         struct drm_dp_mst_port *mst_port;
6409         struct drm_dp_mst_topology_state *mst_state;
6410         enum dc_color_depth color_depth;
6411         int clock, bpp = 0;
6412         bool is_y420 = false;
6413
6414         if (!aconnector->port || !aconnector->dc_sink)
6415                 return 0;
6416
6417         mst_port = aconnector->port;
6418         mst_mgr = &aconnector->mst_port->mst_mgr;
6419
6420         if (!crtc_state->connectors_changed && !crtc_state->mode_changed)
6421                 return 0;
6422
6423         mst_state = drm_atomic_get_mst_topology_state(state, mst_mgr);
6424         if (IS_ERR(mst_state))
6425                 return PTR_ERR(mst_state);
6426
6427         if (!mst_state->pbn_div)
6428                 mst_state->pbn_div = dm_mst_get_pbn_divider(aconnector->mst_port->dc_link);
6429
6430         if (!state->duplicated) {
6431                 int max_bpc = conn_state->max_requested_bpc;
6432                 is_y420 = drm_mode_is_420_also(&connector->display_info, adjusted_mode) &&
6433                           aconnector->force_yuv420_output;
6434                 color_depth = convert_color_depth_from_display_info(connector,
6435                                                                     is_y420,
6436                                                                     max_bpc);
6437                 bpp = convert_dc_color_depth_into_bpc(color_depth) * 3;
6438                 clock = adjusted_mode->clock;
6439                 dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp, false);
6440         }
6441
6442         dm_new_connector_state->vcpi_slots =
6443                 drm_dp_atomic_find_time_slots(state, mst_mgr, mst_port,
6444                                               dm_new_connector_state->pbn);
6445         if (dm_new_connector_state->vcpi_slots < 0) {
6446                 DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots);
6447                 return dm_new_connector_state->vcpi_slots;
6448         }
6449         return 0;
6450 }
6451
6452 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
6453         .disable = dm_encoder_helper_disable,
6454         .atomic_check = dm_encoder_helper_atomic_check
6455 };
6456
6457 #if defined(CONFIG_DRM_AMD_DC_DCN)
6458 static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state,
6459                                             struct dc_state *dc_state,
6460                                             struct dsc_mst_fairness_vars *vars)
6461 {
6462         struct dc_stream_state *stream = NULL;
6463         struct drm_connector *connector;
6464         struct drm_connector_state *new_con_state;
6465         struct amdgpu_dm_connector *aconnector;
6466         struct dm_connector_state *dm_conn_state;
6467         int i, j;
6468         int vcpi, pbn_div, pbn, slot_num = 0;
6469
6470         for_each_new_connector_in_state(state, connector, new_con_state, i) {
6471
6472                 aconnector = to_amdgpu_dm_connector(connector);
6473
6474                 if (!aconnector->port)
6475                         continue;
6476
6477                 if (!new_con_state || !new_con_state->crtc)
6478                         continue;
6479
6480                 dm_conn_state = to_dm_connector_state(new_con_state);
6481
6482                 for (j = 0; j < dc_state->stream_count; j++) {
6483                         stream = dc_state->streams[j];
6484                         if (!stream)
6485                                 continue;
6486
6487                         if ((struct amdgpu_dm_connector *)stream->dm_stream_context == aconnector)
6488                                 break;
6489
6490                         stream = NULL;
6491                 }
6492
6493                 if (!stream)
6494                         continue;
6495
6496                 pbn_div = dm_mst_get_pbn_divider(stream->link);
6497                 /* pbn is calculated by compute_mst_dsc_configs_for_state*/
6498                 for (j = 0; j < dc_state->stream_count; j++) {
6499                         if (vars[j].aconnector == aconnector) {
6500                                 pbn = vars[j].pbn;
6501                                 break;
6502                         }
6503                 }
6504
6505                 if (j == dc_state->stream_count)
6506                         continue;
6507
6508                 slot_num = DIV_ROUND_UP(pbn, pbn_div);
6509
6510                 if (stream->timing.flags.DSC != 1) {
6511                         dm_conn_state->pbn = pbn;
6512                         dm_conn_state->vcpi_slots = slot_num;
6513
6514                         drm_dp_mst_atomic_enable_dsc(state, aconnector->port, dm_conn_state->pbn,
6515                                                      false);
6516                         continue;
6517                 }
6518
6519                 vcpi = drm_dp_mst_atomic_enable_dsc(state, aconnector->port, pbn, true);
6520                 if (vcpi < 0)
6521                         return vcpi;
6522
6523                 dm_conn_state->pbn = pbn;
6524                 dm_conn_state->vcpi_slots = vcpi;
6525         }
6526         return 0;
6527 }
6528 #endif
6529
6530 static int to_drm_connector_type(enum signal_type st)
6531 {
6532         switch (st) {
6533         case SIGNAL_TYPE_HDMI_TYPE_A:
6534                 return DRM_MODE_CONNECTOR_HDMIA;
6535         case SIGNAL_TYPE_EDP:
6536                 return DRM_MODE_CONNECTOR_eDP;
6537         case SIGNAL_TYPE_LVDS:
6538                 return DRM_MODE_CONNECTOR_LVDS;
6539         case SIGNAL_TYPE_RGB:
6540                 return DRM_MODE_CONNECTOR_VGA;
6541         case SIGNAL_TYPE_DISPLAY_PORT:
6542         case SIGNAL_TYPE_DISPLAY_PORT_MST:
6543                 return DRM_MODE_CONNECTOR_DisplayPort;
6544         case SIGNAL_TYPE_DVI_DUAL_LINK:
6545         case SIGNAL_TYPE_DVI_SINGLE_LINK:
6546                 return DRM_MODE_CONNECTOR_DVID;
6547         case SIGNAL_TYPE_VIRTUAL:
6548                 return DRM_MODE_CONNECTOR_VIRTUAL;
6549
6550         default:
6551                 return DRM_MODE_CONNECTOR_Unknown;
6552         }
6553 }
6554
6555 static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector)
6556 {
6557         struct drm_encoder *encoder;
6558
6559         /* There is only one encoder per connector */
6560         drm_connector_for_each_possible_encoder(connector, encoder)
6561                 return encoder;
6562
6563         return NULL;
6564 }
6565
6566 static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
6567 {
6568         struct drm_encoder *encoder;
6569         struct amdgpu_encoder *amdgpu_encoder;
6570
6571         encoder = amdgpu_dm_connector_to_encoder(connector);
6572
6573         if (encoder == NULL)
6574                 return;
6575
6576         amdgpu_encoder = to_amdgpu_encoder(encoder);
6577
6578         amdgpu_encoder->native_mode.clock = 0;
6579
6580         if (!list_empty(&connector->probed_modes)) {
6581                 struct drm_display_mode *preferred_mode = NULL;
6582
6583                 list_for_each_entry(preferred_mode,
6584                                     &connector->probed_modes,
6585                                     head) {
6586                         if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
6587                                 amdgpu_encoder->native_mode = *preferred_mode;
6588
6589                         break;
6590                 }
6591
6592         }
6593 }
6594
6595 static struct drm_display_mode *
6596 amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
6597                              char *name,
6598                              int hdisplay, int vdisplay)
6599 {
6600         struct drm_device *dev = encoder->dev;
6601         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
6602         struct drm_display_mode *mode = NULL;
6603         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
6604
6605         mode = drm_mode_duplicate(dev, native_mode);
6606
6607         if (mode == NULL)
6608                 return NULL;
6609
6610         mode->hdisplay = hdisplay;
6611         mode->vdisplay = vdisplay;
6612         mode->type &= ~DRM_MODE_TYPE_PREFERRED;
6613         strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
6614
6615         return mode;
6616
6617 }
6618
6619 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
6620                                                  struct drm_connector *connector)
6621 {
6622         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
6623         struct drm_display_mode *mode = NULL;
6624         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
6625         struct amdgpu_dm_connector *amdgpu_dm_connector =
6626                                 to_amdgpu_dm_connector(connector);
6627         int i;
6628         int n;
6629         struct mode_size {
6630                 char name[DRM_DISPLAY_MODE_LEN];
6631                 int w;
6632                 int h;
6633         } common_modes[] = {
6634                 {  "640x480",  640,  480},
6635                 {  "800x600",  800,  600},
6636                 { "1024x768", 1024,  768},
6637                 { "1280x720", 1280,  720},
6638                 { "1280x800", 1280,  800},
6639                 {"1280x1024", 1280, 1024},
6640                 { "1440x900", 1440,  900},
6641                 {"1680x1050", 1680, 1050},
6642                 {"1600x1200", 1600, 1200},
6643                 {"1920x1080", 1920, 1080},
6644                 {"1920x1200", 1920, 1200}
6645         };
6646
6647         n = ARRAY_SIZE(common_modes);
6648
6649         for (i = 0; i < n; i++) {
6650                 struct drm_display_mode *curmode = NULL;
6651                 bool mode_existed = false;
6652
6653                 if (common_modes[i].w > native_mode->hdisplay ||
6654                     common_modes[i].h > native_mode->vdisplay ||
6655                    (common_modes[i].w == native_mode->hdisplay &&
6656                     common_modes[i].h == native_mode->vdisplay))
6657                         continue;
6658
6659                 list_for_each_entry(curmode, &connector->probed_modes, head) {
6660                         if (common_modes[i].w == curmode->hdisplay &&
6661                             common_modes[i].h == curmode->vdisplay) {
6662                                 mode_existed = true;
6663                                 break;
6664                         }
6665                 }
6666
6667                 if (mode_existed)
6668                         continue;
6669
6670                 mode = amdgpu_dm_create_common_mode(encoder,
6671                                 common_modes[i].name, common_modes[i].w,
6672                                 common_modes[i].h);
6673                 if (!mode)
6674                         continue;
6675
6676                 drm_mode_probed_add(connector, mode);
6677                 amdgpu_dm_connector->num_modes++;
6678         }
6679 }
6680
6681 static void amdgpu_set_panel_orientation(struct drm_connector *connector)
6682 {
6683         struct drm_encoder *encoder;
6684         struct amdgpu_encoder *amdgpu_encoder;
6685         const struct drm_display_mode *native_mode;
6686
6687         if (connector->connector_type != DRM_MODE_CONNECTOR_eDP &&
6688             connector->connector_type != DRM_MODE_CONNECTOR_LVDS)
6689                 return;
6690
6691         mutex_lock(&connector->dev->mode_config.mutex);
6692         amdgpu_dm_connector_get_modes(connector);
6693         mutex_unlock(&connector->dev->mode_config.mutex);
6694
6695         encoder = amdgpu_dm_connector_to_encoder(connector);
6696         if (!encoder)
6697                 return;
6698
6699         amdgpu_encoder = to_amdgpu_encoder(encoder);
6700
6701         native_mode = &amdgpu_encoder->native_mode;
6702         if (native_mode->hdisplay == 0 || native_mode->vdisplay == 0)
6703                 return;
6704
6705         drm_connector_set_panel_orientation_with_quirk(connector,
6706                                                        DRM_MODE_PANEL_ORIENTATION_UNKNOWN,
6707                                                        native_mode->hdisplay,
6708                                                        native_mode->vdisplay);
6709 }
6710
6711 static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
6712                                               struct edid *edid)
6713 {
6714         struct amdgpu_dm_connector *amdgpu_dm_connector =
6715                         to_amdgpu_dm_connector(connector);
6716
6717         if (edid) {
6718                 /* empty probed_modes */
6719                 INIT_LIST_HEAD(&connector->probed_modes);
6720                 amdgpu_dm_connector->num_modes =
6721                                 drm_add_edid_modes(connector, edid);
6722
6723                 /* sorting the probed modes before calling function
6724                  * amdgpu_dm_get_native_mode() since EDID can have
6725                  * more than one preferred mode. The modes that are
6726                  * later in the probed mode list could be of higher
6727                  * and preferred resolution. For example, 3840x2160
6728                  * resolution in base EDID preferred timing and 4096x2160
6729                  * preferred resolution in DID extension block later.
6730                  */
6731                 drm_mode_sort(&connector->probed_modes);
6732                 amdgpu_dm_get_native_mode(connector);
6733
6734                 /* Freesync capabilities are reset by calling
6735                  * drm_add_edid_modes() and need to be
6736                  * restored here.
6737                  */
6738                 amdgpu_dm_update_freesync_caps(connector, edid);
6739         } else {
6740                 amdgpu_dm_connector->num_modes = 0;
6741         }
6742 }
6743
6744 static bool is_duplicate_mode(struct amdgpu_dm_connector *aconnector,
6745                               struct drm_display_mode *mode)
6746 {
6747         struct drm_display_mode *m;
6748
6749         list_for_each_entry (m, &aconnector->base.probed_modes, head) {
6750                 if (drm_mode_equal(m, mode))
6751                         return true;
6752         }
6753
6754         return false;
6755 }
6756
6757 static uint add_fs_modes(struct amdgpu_dm_connector *aconnector)
6758 {
6759         const struct drm_display_mode *m;
6760         struct drm_display_mode *new_mode;
6761         uint i;
6762         uint32_t new_modes_count = 0;
6763
6764         /* Standard FPS values
6765          *
6766          * 23.976       - TV/NTSC
6767          * 24           - Cinema
6768          * 25           - TV/PAL
6769          * 29.97        - TV/NTSC
6770          * 30           - TV/NTSC
6771          * 48           - Cinema HFR
6772          * 50           - TV/PAL
6773          * 60           - Commonly used
6774          * 48,72,96,120 - Multiples of 24
6775          */
6776         static const uint32_t common_rates[] = {
6777                 23976, 24000, 25000, 29970, 30000,
6778                 48000, 50000, 60000, 72000, 96000, 120000
6779         };
6780
6781         /*
6782          * Find mode with highest refresh rate with the same resolution
6783          * as the preferred mode. Some monitors report a preferred mode
6784          * with lower resolution than the highest refresh rate supported.
6785          */
6786
6787         m = get_highest_refresh_rate_mode(aconnector, true);
6788         if (!m)
6789                 return 0;
6790
6791         for (i = 0; i < ARRAY_SIZE(common_rates); i++) {
6792                 uint64_t target_vtotal, target_vtotal_diff;
6793                 uint64_t num, den;
6794
6795                 if (drm_mode_vrefresh(m) * 1000 < common_rates[i])
6796                         continue;
6797
6798                 if (common_rates[i] < aconnector->min_vfreq * 1000 ||
6799                     common_rates[i] > aconnector->max_vfreq * 1000)
6800                         continue;
6801
6802                 num = (unsigned long long)m->clock * 1000 * 1000;
6803                 den = common_rates[i] * (unsigned long long)m->htotal;
6804                 target_vtotal = div_u64(num, den);
6805                 target_vtotal_diff = target_vtotal - m->vtotal;
6806
6807                 /* Check for illegal modes */
6808                 if (m->vsync_start + target_vtotal_diff < m->vdisplay ||
6809                     m->vsync_end + target_vtotal_diff < m->vsync_start ||
6810                     m->vtotal + target_vtotal_diff < m->vsync_end)
6811                         continue;
6812
6813                 new_mode = drm_mode_duplicate(aconnector->base.dev, m);
6814                 if (!new_mode)
6815                         goto out;
6816
6817                 new_mode->vtotal += (u16)target_vtotal_diff;
6818                 new_mode->vsync_start += (u16)target_vtotal_diff;
6819                 new_mode->vsync_end += (u16)target_vtotal_diff;
6820                 new_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
6821                 new_mode->type |= DRM_MODE_TYPE_DRIVER;
6822
6823                 if (!is_duplicate_mode(aconnector, new_mode)) {
6824                         drm_mode_probed_add(&aconnector->base, new_mode);
6825                         new_modes_count += 1;
6826                 } else
6827                         drm_mode_destroy(aconnector->base.dev, new_mode);
6828         }
6829  out:
6830         return new_modes_count;
6831 }
6832
6833 static void amdgpu_dm_connector_add_freesync_modes(struct drm_connector *connector,
6834                                                    struct edid *edid)
6835 {
6836         struct amdgpu_dm_connector *amdgpu_dm_connector =
6837                 to_amdgpu_dm_connector(connector);
6838
6839         if (!edid)
6840                 return;
6841
6842         if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
6843                 amdgpu_dm_connector->num_modes +=
6844                         add_fs_modes(amdgpu_dm_connector);
6845 }
6846
6847 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
6848 {
6849         struct amdgpu_dm_connector *amdgpu_dm_connector =
6850                         to_amdgpu_dm_connector(connector);
6851         struct drm_encoder *encoder;
6852         struct edid *edid = amdgpu_dm_connector->edid;
6853
6854         encoder = amdgpu_dm_connector_to_encoder(connector);
6855
6856         if (!drm_edid_is_valid(edid)) {
6857                 amdgpu_dm_connector->num_modes =
6858                                 drm_add_modes_noedid(connector, 640, 480);
6859         } else {
6860                 amdgpu_dm_connector_ddc_get_modes(connector, edid);
6861                 amdgpu_dm_connector_add_common_modes(encoder, connector);
6862                 amdgpu_dm_connector_add_freesync_modes(connector, edid);
6863         }
6864         amdgpu_dm_fbc_init(connector);
6865
6866         return amdgpu_dm_connector->num_modes;
6867 }
6868
6869 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
6870                                      struct amdgpu_dm_connector *aconnector,
6871                                      int connector_type,
6872                                      struct dc_link *link,
6873                                      int link_index)
6874 {
6875         struct amdgpu_device *adev = drm_to_adev(dm->ddev);
6876
6877         /*
6878          * Some of the properties below require access to state, like bpc.
6879          * Allocate some default initial connector state with our reset helper.
6880          */
6881         if (aconnector->base.funcs->reset)
6882                 aconnector->base.funcs->reset(&aconnector->base);
6883
6884         aconnector->connector_id = link_index;
6885         aconnector->dc_link = link;
6886         aconnector->base.interlace_allowed = false;
6887         aconnector->base.doublescan_allowed = false;
6888         aconnector->base.stereo_allowed = false;
6889         aconnector->base.dpms = DRM_MODE_DPMS_OFF;
6890         aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
6891         aconnector->audio_inst = -1;
6892         mutex_init(&aconnector->hpd_lock);
6893
6894         /*
6895          * configure support HPD hot plug connector_>polled default value is 0
6896          * which means HPD hot plug not supported
6897          */
6898         switch (connector_type) {
6899         case DRM_MODE_CONNECTOR_HDMIA:
6900                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
6901                 aconnector->base.ycbcr_420_allowed =
6902                         link->link_enc->features.hdmi_ycbcr420_supported ? true : false;
6903                 break;
6904         case DRM_MODE_CONNECTOR_DisplayPort:
6905                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
6906                 link->link_enc = link_enc_cfg_get_link_enc(link);
6907                 ASSERT(link->link_enc);
6908                 if (link->link_enc)
6909                         aconnector->base.ycbcr_420_allowed =
6910                         link->link_enc->features.dp_ycbcr420_supported ? true : false;
6911                 break;
6912         case DRM_MODE_CONNECTOR_DVID:
6913                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
6914                 break;
6915         default:
6916                 break;
6917         }
6918
6919         drm_object_attach_property(&aconnector->base.base,
6920                                 dm->ddev->mode_config.scaling_mode_property,
6921                                 DRM_MODE_SCALE_NONE);
6922
6923         drm_object_attach_property(&aconnector->base.base,
6924                                 adev->mode_info.underscan_property,
6925                                 UNDERSCAN_OFF);
6926         drm_object_attach_property(&aconnector->base.base,
6927                                 adev->mode_info.underscan_hborder_property,
6928                                 0);
6929         drm_object_attach_property(&aconnector->base.base,
6930                                 adev->mode_info.underscan_vborder_property,
6931                                 0);
6932
6933         if (!aconnector->mst_port)
6934                 drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16);
6935
6936         /* This defaults to the max in the range, but we want 8bpc for non-edp. */
6937         aconnector->base.state->max_bpc = (connector_type == DRM_MODE_CONNECTOR_eDP) ? 16 : 8;
6938         aconnector->base.state->max_requested_bpc = aconnector->base.state->max_bpc;
6939
6940         if (connector_type == DRM_MODE_CONNECTOR_eDP &&
6941             (dc_is_dmcu_initialized(adev->dm.dc) || adev->dm.dc->ctx->dmub_srv)) {
6942                 drm_object_attach_property(&aconnector->base.base,
6943                                 adev->mode_info.abm_level_property, 0);
6944         }
6945
6946         if (connector_type == DRM_MODE_CONNECTOR_HDMIA ||
6947             connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
6948             connector_type == DRM_MODE_CONNECTOR_eDP) {
6949                 drm_connector_attach_hdr_output_metadata_property(&aconnector->base);
6950
6951                 if (!aconnector->mst_port)
6952                         drm_connector_attach_vrr_capable_property(&aconnector->base);
6953
6954 #ifdef CONFIG_DRM_AMD_DC_HDCP
6955                 if (adev->dm.hdcp_workqueue)
6956                         drm_connector_attach_content_protection_property(&aconnector->base, true);
6957 #endif
6958         }
6959 }
6960
6961 static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
6962                               struct i2c_msg *msgs, int num)
6963 {
6964         struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
6965         struct ddc_service *ddc_service = i2c->ddc_service;
6966         struct i2c_command cmd;
6967         int i;
6968         int result = -EIO;
6969
6970         cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
6971
6972         if (!cmd.payloads)
6973                 return result;
6974
6975         cmd.number_of_payloads = num;
6976         cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
6977         cmd.speed = 100;
6978
6979         for (i = 0; i < num; i++) {
6980                 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
6981                 cmd.payloads[i].address = msgs[i].addr;
6982                 cmd.payloads[i].length = msgs[i].len;
6983                 cmd.payloads[i].data = msgs[i].buf;
6984         }
6985
6986         if (dc_submit_i2c(
6987                         ddc_service->ctx->dc,
6988                         ddc_service->link->link_index,
6989                         &cmd))
6990                 result = num;
6991
6992         kfree(cmd.payloads);
6993         return result;
6994 }
6995
6996 static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
6997 {
6998         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
6999 }
7000
7001 static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
7002         .master_xfer = amdgpu_dm_i2c_xfer,
7003         .functionality = amdgpu_dm_i2c_func,
7004 };
7005
7006 static struct amdgpu_i2c_adapter *
7007 create_i2c(struct ddc_service *ddc_service,
7008            int link_index,
7009            int *res)
7010 {
7011         struct amdgpu_device *adev = ddc_service->ctx->driver_context;
7012         struct amdgpu_i2c_adapter *i2c;
7013
7014         i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
7015         if (!i2c)
7016                 return NULL;
7017         i2c->base.owner = THIS_MODULE;
7018         i2c->base.class = I2C_CLASS_DDC;
7019         i2c->base.dev.parent = &adev->pdev->dev;
7020         i2c->base.algo = &amdgpu_dm_i2c_algo;
7021         snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
7022         i2c_set_adapdata(&i2c->base, i2c);
7023         i2c->ddc_service = ddc_service;
7024
7025         return i2c;
7026 }
7027
7028
7029 /*
7030  * Note: this function assumes that dc_link_detect() was called for the
7031  * dc_link which will be represented by this aconnector.
7032  */
7033 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
7034                                     struct amdgpu_dm_connector *aconnector,
7035                                     uint32_t link_index,
7036                                     struct amdgpu_encoder *aencoder)
7037 {
7038         int res = 0;
7039         int connector_type;
7040         struct dc *dc = dm->dc;
7041         struct dc_link *link = dc_get_link_at_index(dc, link_index);
7042         struct amdgpu_i2c_adapter *i2c;
7043
7044         link->priv = aconnector;
7045
7046         DRM_DEBUG_DRIVER("%s()\n", __func__);
7047
7048         i2c = create_i2c(link->ddc, link->link_index, &res);
7049         if (!i2c) {
7050                 DRM_ERROR("Failed to create i2c adapter data\n");
7051                 return -ENOMEM;
7052         }
7053
7054         aconnector->i2c = i2c;
7055         res = i2c_add_adapter(&i2c->base);
7056
7057         if (res) {
7058                 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
7059                 goto out_free;
7060         }
7061
7062         connector_type = to_drm_connector_type(link->connector_signal);
7063
7064         res = drm_connector_init_with_ddc(
7065                         dm->ddev,
7066                         &aconnector->base,
7067                         &amdgpu_dm_connector_funcs,
7068                         connector_type,
7069                         &i2c->base);
7070
7071         if (res) {
7072                 DRM_ERROR("connector_init failed\n");
7073                 aconnector->connector_id = -1;
7074                 goto out_free;
7075         }
7076
7077         drm_connector_helper_add(
7078                         &aconnector->base,
7079                         &amdgpu_dm_connector_helper_funcs);
7080
7081         amdgpu_dm_connector_init_helper(
7082                 dm,
7083                 aconnector,
7084                 connector_type,
7085                 link,
7086                 link_index);
7087
7088         drm_connector_attach_encoder(
7089                 &aconnector->base, &aencoder->base);
7090
7091         if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
7092                 || connector_type == DRM_MODE_CONNECTOR_eDP)
7093                 amdgpu_dm_initialize_dp_connector(dm, aconnector, link->link_index);
7094
7095 out_free:
7096         if (res) {
7097                 kfree(i2c);
7098                 aconnector->i2c = NULL;
7099         }
7100         return res;
7101 }
7102
7103 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
7104 {
7105         switch (adev->mode_info.num_crtc) {
7106         case 1:
7107                 return 0x1;
7108         case 2:
7109                 return 0x3;
7110         case 3:
7111                 return 0x7;
7112         case 4:
7113                 return 0xf;
7114         case 5:
7115                 return 0x1f;
7116         case 6:
7117         default:
7118                 return 0x3f;
7119         }
7120 }
7121
7122 static int amdgpu_dm_encoder_init(struct drm_device *dev,
7123                                   struct amdgpu_encoder *aencoder,
7124                                   uint32_t link_index)
7125 {
7126         struct amdgpu_device *adev = drm_to_adev(dev);
7127
7128         int res = drm_encoder_init(dev,
7129                                    &aencoder->base,
7130                                    &amdgpu_dm_encoder_funcs,
7131                                    DRM_MODE_ENCODER_TMDS,
7132                                    NULL);
7133
7134         aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
7135
7136         if (!res)
7137                 aencoder->encoder_id = link_index;
7138         else
7139                 aencoder->encoder_id = -1;
7140
7141         drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
7142
7143         return res;
7144 }
7145
7146 static void manage_dm_interrupts(struct amdgpu_device *adev,
7147                                  struct amdgpu_crtc *acrtc,
7148                                  bool enable)
7149 {
7150         /*
7151          * We have no guarantee that the frontend index maps to the same
7152          * backend index - some even map to more than one.
7153          *
7154          * TODO: Use a different interrupt or check DC itself for the mapping.
7155          */
7156         int irq_type =
7157                 amdgpu_display_crtc_idx_to_irq_type(
7158                         adev,
7159                         acrtc->crtc_id);
7160
7161         if (enable) {
7162                 drm_crtc_vblank_on(&acrtc->base);
7163                 amdgpu_irq_get(
7164                         adev,
7165                         &adev->pageflip_irq,
7166                         irq_type);
7167 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
7168                 amdgpu_irq_get(
7169                         adev,
7170                         &adev->vline0_irq,
7171                         irq_type);
7172 #endif
7173         } else {
7174 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
7175                 amdgpu_irq_put(
7176                         adev,
7177                         &adev->vline0_irq,
7178                         irq_type);
7179 #endif
7180                 amdgpu_irq_put(
7181                         adev,
7182                         &adev->pageflip_irq,
7183                         irq_type);
7184                 drm_crtc_vblank_off(&acrtc->base);
7185         }
7186 }
7187
7188 static void dm_update_pflip_irq_state(struct amdgpu_device *adev,
7189                                       struct amdgpu_crtc *acrtc)
7190 {
7191         int irq_type =
7192                 amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id);
7193
7194         /**
7195          * This reads the current state for the IRQ and force reapplies
7196          * the setting to hardware.
7197          */
7198         amdgpu_irq_update(adev, &adev->pageflip_irq, irq_type);
7199 }
7200
7201 static bool
7202 is_scaling_state_different(const struct dm_connector_state *dm_state,
7203                            const struct dm_connector_state *old_dm_state)
7204 {
7205         if (dm_state->scaling != old_dm_state->scaling)
7206                 return true;
7207         if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
7208                 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
7209                         return true;
7210         } else  if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
7211                 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
7212                         return true;
7213         } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
7214                    dm_state->underscan_vborder != old_dm_state->underscan_vborder)
7215                 return true;
7216         return false;
7217 }
7218
7219 #ifdef CONFIG_DRM_AMD_DC_HDCP
7220 static bool is_content_protection_different(struct drm_connector_state *state,
7221                                             const struct drm_connector_state *old_state,
7222                                             const struct drm_connector *connector, struct hdcp_workqueue *hdcp_w)
7223 {
7224         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
7225         struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
7226
7227         /* Handle: Type0/1 change */
7228         if (old_state->hdcp_content_type != state->hdcp_content_type &&
7229             state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
7230                 state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7231                 return true;
7232         }
7233
7234         /* CP is being re enabled, ignore this
7235          *
7236          * Handles:     ENABLED -> DESIRED
7237          */
7238         if (old_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED &&
7239             state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7240                 state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED;
7241                 return false;
7242         }
7243
7244         /* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED
7245          *
7246          * Handles:     UNDESIRED -> ENABLED
7247          */
7248         if (old_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED &&
7249             state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
7250                 state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
7251
7252         /* Stream removed and re-enabled
7253          *
7254          * Can sometimes overlap with the HPD case,
7255          * thus set update_hdcp to false to avoid
7256          * setting HDCP multiple times.
7257          *
7258          * Handles:     DESIRED -> DESIRED (Special case)
7259          */
7260         if (!(old_state->crtc && old_state->crtc->enabled) &&
7261                 state->crtc && state->crtc->enabled &&
7262                 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
7263                 dm_con_state->update_hdcp = false;
7264                 return true;
7265         }
7266
7267         /* Hot-plug, headless s3, dpms
7268          *
7269          * Only start HDCP if the display is connected/enabled.
7270          * update_hdcp flag will be set to false until the next
7271          * HPD comes in.
7272          *
7273          * Handles:     DESIRED -> DESIRED (Special case)
7274          */
7275         if (dm_con_state->update_hdcp && state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED &&
7276             connector->dpms == DRM_MODE_DPMS_ON && aconnector->dc_sink != NULL) {
7277                 dm_con_state->update_hdcp = false;
7278                 return true;
7279         }
7280
7281         /*
7282          * Handles:     UNDESIRED -> UNDESIRED
7283          *              DESIRED -> DESIRED
7284          *              ENABLED -> ENABLED
7285          */
7286         if (old_state->content_protection == state->content_protection)
7287                 return false;
7288
7289         /*
7290          * Handles:     UNDESIRED -> DESIRED
7291          *              DESIRED -> UNDESIRED
7292          *              ENABLED -> UNDESIRED
7293          */
7294         if (state->content_protection != DRM_MODE_CONTENT_PROTECTION_ENABLED)
7295                 return true;
7296
7297         /*
7298          * Handles:     DESIRED -> ENABLED
7299          */
7300         return false;
7301 }
7302
7303 #endif
7304 static void remove_stream(struct amdgpu_device *adev,
7305                           struct amdgpu_crtc *acrtc,
7306                           struct dc_stream_state *stream)
7307 {
7308         /* this is the update mode case */
7309
7310         acrtc->otg_inst = -1;
7311         acrtc->enabled = false;
7312 }
7313
7314 static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
7315 {
7316
7317         assert_spin_locked(&acrtc->base.dev->event_lock);
7318         WARN_ON(acrtc->event);
7319
7320         acrtc->event = acrtc->base.state->event;
7321
7322         /* Set the flip status */
7323         acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
7324
7325         /* Mark this event as consumed */
7326         acrtc->base.state->event = NULL;
7327
7328         DC_LOG_PFLIP("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
7329                      acrtc->crtc_id);
7330 }
7331
7332 static void update_freesync_state_on_stream(
7333         struct amdgpu_display_manager *dm,
7334         struct dm_crtc_state *new_crtc_state,
7335         struct dc_stream_state *new_stream,
7336         struct dc_plane_state *surface,
7337         u32 flip_timestamp_in_us)
7338 {
7339         struct mod_vrr_params vrr_params;
7340         struct dc_info_packet vrr_infopacket = {0};
7341         struct amdgpu_device *adev = dm->adev;
7342         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
7343         unsigned long flags;
7344         bool pack_sdp_v1_3 = false;
7345
7346         if (!new_stream)
7347                 return;
7348
7349         /*
7350          * TODO: Determine why min/max totals and vrefresh can be 0 here.
7351          * For now it's sufficient to just guard against these conditions.
7352          */
7353
7354         if (!new_stream->timing.h_total || !new_stream->timing.v_total)
7355                 return;
7356
7357         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
7358         vrr_params = acrtc->dm_irq_params.vrr_params;
7359
7360         if (surface) {
7361                 mod_freesync_handle_preflip(
7362                         dm->freesync_module,
7363                         surface,
7364                         new_stream,
7365                         flip_timestamp_in_us,
7366                         &vrr_params);
7367
7368                 if (adev->family < AMDGPU_FAMILY_AI &&
7369                     amdgpu_dm_vrr_active(new_crtc_state)) {
7370                         mod_freesync_handle_v_update(dm->freesync_module,
7371                                                      new_stream, &vrr_params);
7372
7373                         /* Need to call this before the frame ends. */
7374                         dc_stream_adjust_vmin_vmax(dm->dc,
7375                                                    new_crtc_state->stream,
7376                                                    &vrr_params.adjust);
7377                 }
7378         }
7379
7380         mod_freesync_build_vrr_infopacket(
7381                 dm->freesync_module,
7382                 new_stream,
7383                 &vrr_params,
7384                 PACKET_TYPE_VRR,
7385                 TRANSFER_FUNC_UNKNOWN,
7386                 &vrr_infopacket,
7387                 pack_sdp_v1_3);
7388
7389         new_crtc_state->freesync_vrr_info_changed |=
7390                 (memcmp(&new_crtc_state->vrr_infopacket,
7391                         &vrr_infopacket,
7392                         sizeof(vrr_infopacket)) != 0);
7393
7394         acrtc->dm_irq_params.vrr_params = vrr_params;
7395         new_crtc_state->vrr_infopacket = vrr_infopacket;
7396
7397         new_stream->vrr_infopacket = vrr_infopacket;
7398
7399         if (new_crtc_state->freesync_vrr_info_changed)
7400                 DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d",
7401                               new_crtc_state->base.crtc->base.id,
7402                               (int)new_crtc_state->base.vrr_enabled,
7403                               (int)vrr_params.state);
7404
7405         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
7406 }
7407
7408 static void update_stream_irq_parameters(
7409         struct amdgpu_display_manager *dm,
7410         struct dm_crtc_state *new_crtc_state)
7411 {
7412         struct dc_stream_state *new_stream = new_crtc_state->stream;
7413         struct mod_vrr_params vrr_params;
7414         struct mod_freesync_config config = new_crtc_state->freesync_config;
7415         struct amdgpu_device *adev = dm->adev;
7416         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc);
7417         unsigned long flags;
7418
7419         if (!new_stream)
7420                 return;
7421
7422         /*
7423          * TODO: Determine why min/max totals and vrefresh can be 0 here.
7424          * For now it's sufficient to just guard against these conditions.
7425          */
7426         if (!new_stream->timing.h_total || !new_stream->timing.v_total)
7427                 return;
7428
7429         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
7430         vrr_params = acrtc->dm_irq_params.vrr_params;
7431
7432         if (new_crtc_state->vrr_supported &&
7433             config.min_refresh_in_uhz &&
7434             config.max_refresh_in_uhz) {
7435                 /*
7436                  * if freesync compatible mode was set, config.state will be set
7437                  * in atomic check
7438                  */
7439                 if (config.state == VRR_STATE_ACTIVE_FIXED && config.fixed_refresh_in_uhz &&
7440                     (!drm_atomic_crtc_needs_modeset(&new_crtc_state->base) ||
7441                      new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)) {
7442                         vrr_params.max_refresh_in_uhz = config.max_refresh_in_uhz;
7443                         vrr_params.min_refresh_in_uhz = config.min_refresh_in_uhz;
7444                         vrr_params.fixed_refresh_in_uhz = config.fixed_refresh_in_uhz;
7445                         vrr_params.state = VRR_STATE_ACTIVE_FIXED;
7446                 } else {
7447                         config.state = new_crtc_state->base.vrr_enabled ?
7448                                                      VRR_STATE_ACTIVE_VARIABLE :
7449                                                      VRR_STATE_INACTIVE;
7450                 }
7451         } else {
7452                 config.state = VRR_STATE_UNSUPPORTED;
7453         }
7454
7455         mod_freesync_build_vrr_params(dm->freesync_module,
7456                                       new_stream,
7457                                       &config, &vrr_params);
7458
7459         new_crtc_state->freesync_config = config;
7460         /* Copy state for access from DM IRQ handler */
7461         acrtc->dm_irq_params.freesync_config = config;
7462         acrtc->dm_irq_params.active_planes = new_crtc_state->active_planes;
7463         acrtc->dm_irq_params.vrr_params = vrr_params;
7464         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
7465 }
7466
7467 static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state,
7468                                             struct dm_crtc_state *new_state)
7469 {
7470         bool old_vrr_active = amdgpu_dm_vrr_active(old_state);
7471         bool new_vrr_active = amdgpu_dm_vrr_active(new_state);
7472
7473         if (!old_vrr_active && new_vrr_active) {
7474                 /* Transition VRR inactive -> active:
7475                  * While VRR is active, we must not disable vblank irq, as a
7476                  * reenable after disable would compute bogus vblank/pflip
7477                  * timestamps if it likely happened inside display front-porch.
7478                  *
7479                  * We also need vupdate irq for the actual core vblank handling
7480                  * at end of vblank.
7481                  */
7482                 dm_set_vupdate_irq(new_state->base.crtc, true);
7483                 drm_crtc_vblank_get(new_state->base.crtc);
7484                 DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n",
7485                                  __func__, new_state->base.crtc->base.id);
7486         } else if (old_vrr_active && !new_vrr_active) {
7487                 /* Transition VRR active -> inactive:
7488                  * Allow vblank irq disable again for fixed refresh rate.
7489                  */
7490                 dm_set_vupdate_irq(new_state->base.crtc, false);
7491                 drm_crtc_vblank_put(new_state->base.crtc);
7492                 DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n",
7493                                  __func__, new_state->base.crtc->base.id);
7494         }
7495 }
7496
7497 static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state)
7498 {
7499         struct drm_plane *plane;
7500         struct drm_plane_state *old_plane_state;
7501         int i;
7502
7503         /*
7504          * TODO: Make this per-stream so we don't issue redundant updates for
7505          * commits with multiple streams.
7506          */
7507         for_each_old_plane_in_state(state, plane, old_plane_state, i)
7508                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
7509                         handle_cursor_update(plane, old_plane_state);
7510 }
7511
7512 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
7513                                     struct dc_state *dc_state,
7514                                     struct drm_device *dev,
7515                                     struct amdgpu_display_manager *dm,
7516                                     struct drm_crtc *pcrtc,
7517                                     bool wait_for_vblank)
7518 {
7519         uint32_t i;
7520         uint64_t timestamp_ns;
7521         struct drm_plane *plane;
7522         struct drm_plane_state *old_plane_state, *new_plane_state;
7523         struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
7524         struct drm_crtc_state *new_pcrtc_state =
7525                         drm_atomic_get_new_crtc_state(state, pcrtc);
7526         struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
7527         struct dm_crtc_state *dm_old_crtc_state =
7528                         to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc));
7529         int planes_count = 0, vpos, hpos;
7530         unsigned long flags;
7531         uint32_t target_vblank, last_flip_vblank;
7532         bool vrr_active = amdgpu_dm_vrr_active(acrtc_state);
7533         bool cursor_update = false;
7534         bool pflip_present = false;
7535         struct {
7536                 struct dc_surface_update surface_updates[MAX_SURFACES];
7537                 struct dc_plane_info plane_infos[MAX_SURFACES];
7538                 struct dc_scaling_info scaling_infos[MAX_SURFACES];
7539                 struct dc_flip_addrs flip_addrs[MAX_SURFACES];
7540                 struct dc_stream_update stream_update;
7541         } *bundle;
7542
7543         bundle = kzalloc(sizeof(*bundle), GFP_KERNEL);
7544
7545         if (!bundle) {
7546                 dm_error("Failed to allocate update bundle\n");
7547                 goto cleanup;
7548         }
7549
7550         /*
7551          * Disable the cursor first if we're disabling all the planes.
7552          * It'll remain on the screen after the planes are re-enabled
7553          * if we don't.
7554          */
7555         if (acrtc_state->active_planes == 0)
7556                 amdgpu_dm_commit_cursors(state);
7557
7558         /* update planes when needed */
7559         for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
7560                 struct drm_crtc *crtc = new_plane_state->crtc;
7561                 struct drm_crtc_state *new_crtc_state;
7562                 struct drm_framebuffer *fb = new_plane_state->fb;
7563                 struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)fb;
7564                 bool plane_needs_flip;
7565                 struct dc_plane_state *dc_plane;
7566                 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
7567
7568                 /* Cursor plane is handled after stream updates */
7569                 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
7570                         if ((fb && crtc == pcrtc) ||
7571                             (old_plane_state->fb && old_plane_state->crtc == pcrtc))
7572                                 cursor_update = true;
7573
7574                         continue;
7575                 }
7576
7577                 if (!fb || !crtc || pcrtc != crtc)
7578                         continue;
7579
7580                 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
7581                 if (!new_crtc_state->active)
7582                         continue;
7583
7584                 dc_plane = dm_new_plane_state->dc_state;
7585
7586                 bundle->surface_updates[planes_count].surface = dc_plane;
7587                 if (new_pcrtc_state->color_mgmt_changed) {
7588                         bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction;
7589                         bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func;
7590                         bundle->surface_updates[planes_count].gamut_remap_matrix = &dc_plane->gamut_remap_matrix;
7591                 }
7592
7593                 fill_dc_scaling_info(dm->adev, new_plane_state,
7594                                      &bundle->scaling_infos[planes_count]);
7595
7596                 bundle->surface_updates[planes_count].scaling_info =
7597                         &bundle->scaling_infos[planes_count];
7598
7599                 plane_needs_flip = old_plane_state->fb && new_plane_state->fb;
7600
7601                 pflip_present = pflip_present || plane_needs_flip;
7602
7603                 if (!plane_needs_flip) {
7604                         planes_count += 1;
7605                         continue;
7606                 }
7607
7608                 fill_dc_plane_info_and_addr(
7609                         dm->adev, new_plane_state,
7610                         afb->tiling_flags,
7611                         &bundle->plane_infos[planes_count],
7612                         &bundle->flip_addrs[planes_count].address,
7613                         afb->tmz_surface, false);
7614
7615                 drm_dbg_state(state->dev, "plane: id=%d dcc_en=%d\n",
7616                                  new_plane_state->plane->index,
7617                                  bundle->plane_infos[planes_count].dcc.enable);
7618
7619                 bundle->surface_updates[planes_count].plane_info =
7620                         &bundle->plane_infos[planes_count];
7621
7622                 fill_dc_dirty_rects(plane, old_plane_state, new_plane_state,
7623                                     new_crtc_state,
7624                                     &bundle->flip_addrs[planes_count]);
7625
7626                 /*
7627                  * Only allow immediate flips for fast updates that don't
7628                  * change FB pitch, DCC state, rotation or mirroing.
7629                  */
7630                 bundle->flip_addrs[planes_count].flip_immediate =
7631                         crtc->state->async_flip &&
7632                         acrtc_state->update_type == UPDATE_TYPE_FAST;
7633
7634                 timestamp_ns = ktime_get_ns();
7635                 bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000);
7636                 bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count];
7637                 bundle->surface_updates[planes_count].surface = dc_plane;
7638
7639                 if (!bundle->surface_updates[planes_count].surface) {
7640                         DRM_ERROR("No surface for CRTC: id=%d\n",
7641                                         acrtc_attach->crtc_id);
7642                         continue;
7643                 }
7644
7645                 if (plane == pcrtc->primary)
7646                         update_freesync_state_on_stream(
7647                                 dm,
7648                                 acrtc_state,
7649                                 acrtc_state->stream,
7650                                 dc_plane,
7651                                 bundle->flip_addrs[planes_count].flip_timestamp_in_us);
7652
7653                 drm_dbg_state(state->dev, "%s Flipping to hi: 0x%x, low: 0x%x\n",
7654                                  __func__,
7655                                  bundle->flip_addrs[planes_count].address.grph.addr.high_part,
7656                                  bundle->flip_addrs[planes_count].address.grph.addr.low_part);
7657
7658                 planes_count += 1;
7659
7660         }
7661
7662         if (pflip_present) {
7663                 if (!vrr_active) {
7664                         /* Use old throttling in non-vrr fixed refresh rate mode
7665                          * to keep flip scheduling based on target vblank counts
7666                          * working in a backwards compatible way, e.g., for
7667                          * clients using the GLX_OML_sync_control extension or
7668                          * DRI3/Present extension with defined target_msc.
7669                          */
7670                         last_flip_vblank = amdgpu_get_vblank_counter_kms(pcrtc);
7671                 }
7672                 else {
7673                         /* For variable refresh rate mode only:
7674                          * Get vblank of last completed flip to avoid > 1 vrr
7675                          * flips per video frame by use of throttling, but allow
7676                          * flip programming anywhere in the possibly large
7677                          * variable vrr vblank interval for fine-grained flip
7678                          * timing control and more opportunity to avoid stutter
7679                          * on late submission of flips.
7680                          */
7681                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
7682                         last_flip_vblank = acrtc_attach->dm_irq_params.last_flip_vblank;
7683                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
7684                 }
7685
7686                 target_vblank = last_flip_vblank + wait_for_vblank;
7687
7688                 /*
7689                  * Wait until we're out of the vertical blank period before the one
7690                  * targeted by the flip
7691                  */
7692                 while ((acrtc_attach->enabled &&
7693                         (amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id,
7694                                                             0, &vpos, &hpos, NULL,
7695                                                             NULL, &pcrtc->hwmode)
7696                          & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
7697                         (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
7698                         (int)(target_vblank -
7699                           amdgpu_get_vblank_counter_kms(pcrtc)) > 0)) {
7700                         usleep_range(1000, 1100);
7701                 }
7702
7703                 /**
7704                  * Prepare the flip event for the pageflip interrupt to handle.
7705                  *
7706                  * This only works in the case where we've already turned on the
7707                  * appropriate hardware blocks (eg. HUBP) so in the transition case
7708                  * from 0 -> n planes we have to skip a hardware generated event
7709                  * and rely on sending it from software.
7710                  */
7711                 if (acrtc_attach->base.state->event &&
7712                     acrtc_state->active_planes > 0) {
7713                         drm_crtc_vblank_get(pcrtc);
7714
7715                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
7716
7717                         WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE);
7718                         prepare_flip_isr(acrtc_attach);
7719
7720                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
7721                 }
7722
7723                 if (acrtc_state->stream) {
7724                         if (acrtc_state->freesync_vrr_info_changed)
7725                                 bundle->stream_update.vrr_infopacket =
7726                                         &acrtc_state->stream->vrr_infopacket;
7727                 }
7728         } else if (cursor_update && acrtc_state->active_planes > 0 &&
7729                    acrtc_attach->base.state->event) {
7730                 drm_crtc_vblank_get(pcrtc);
7731
7732                 spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
7733
7734                 acrtc_attach->event = acrtc_attach->base.state->event;
7735                 acrtc_attach->base.state->event = NULL;
7736
7737                 spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
7738         }
7739
7740         /* Update the planes if changed or disable if we don't have any. */
7741         if ((planes_count || acrtc_state->active_planes == 0) &&
7742                 acrtc_state->stream) {
7743                 /*
7744                  * If PSR or idle optimizations are enabled then flush out
7745                  * any pending work before hardware programming.
7746                  */
7747                 if (dm->vblank_control_workqueue)
7748                         flush_workqueue(dm->vblank_control_workqueue);
7749
7750                 bundle->stream_update.stream = acrtc_state->stream;
7751                 if (new_pcrtc_state->mode_changed) {
7752                         bundle->stream_update.src = acrtc_state->stream->src;
7753                         bundle->stream_update.dst = acrtc_state->stream->dst;
7754                 }
7755
7756                 if (new_pcrtc_state->color_mgmt_changed) {
7757                         /*
7758                          * TODO: This isn't fully correct since we've actually
7759                          * already modified the stream in place.
7760                          */
7761                         bundle->stream_update.gamut_remap =
7762                                 &acrtc_state->stream->gamut_remap_matrix;
7763                         bundle->stream_update.output_csc_transform =
7764                                 &acrtc_state->stream->csc_color_matrix;
7765                         bundle->stream_update.out_transfer_func =
7766                                 acrtc_state->stream->out_transfer_func;
7767                 }
7768
7769                 acrtc_state->stream->abm_level = acrtc_state->abm_level;
7770                 if (acrtc_state->abm_level != dm_old_crtc_state->abm_level)
7771                         bundle->stream_update.abm_level = &acrtc_state->abm_level;
7772
7773                 /*
7774                  * If FreeSync state on the stream has changed then we need to
7775                  * re-adjust the min/max bounds now that DC doesn't handle this
7776                  * as part of commit.
7777                  */
7778                 if (is_dc_timing_adjust_needed(dm_old_crtc_state, acrtc_state)) {
7779                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
7780                         dc_stream_adjust_vmin_vmax(
7781                                 dm->dc, acrtc_state->stream,
7782                                 &acrtc_attach->dm_irq_params.vrr_params.adjust);
7783                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
7784                 }
7785                 mutex_lock(&dm->dc_lock);
7786                 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
7787                                 acrtc_state->stream->link->psr_settings.psr_allow_active)
7788                         amdgpu_dm_psr_disable(acrtc_state->stream);
7789
7790                 dc_commit_updates_for_stream(dm->dc,
7791                                                      bundle->surface_updates,
7792                                                      planes_count,
7793                                                      acrtc_state->stream,
7794                                                      &bundle->stream_update,
7795                                                      dc_state);
7796
7797                 /**
7798                  * Enable or disable the interrupts on the backend.
7799                  *
7800                  * Most pipes are put into power gating when unused.
7801                  *
7802                  * When power gating is enabled on a pipe we lose the
7803                  * interrupt enablement state when power gating is disabled.
7804                  *
7805                  * So we need to update the IRQ control state in hardware
7806                  * whenever the pipe turns on (since it could be previously
7807                  * power gated) or off (since some pipes can't be power gated
7808                  * on some ASICs).
7809                  */
7810                 if (dm_old_crtc_state->active_planes != acrtc_state->active_planes)
7811                         dm_update_pflip_irq_state(drm_to_adev(dev),
7812                                                   acrtc_attach);
7813
7814                 if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
7815                                 acrtc_state->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED &&
7816                                 !acrtc_state->stream->link->psr_settings.psr_feature_enabled)
7817                         amdgpu_dm_link_setup_psr(acrtc_state->stream);
7818
7819                 /* Decrement skip count when PSR is enabled and we're doing fast updates. */
7820                 if (acrtc_state->update_type == UPDATE_TYPE_FAST &&
7821                     acrtc_state->stream->link->psr_settings.psr_feature_enabled) {
7822                         struct amdgpu_dm_connector *aconn =
7823                                 (struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context;
7824
7825                         if (aconn->psr_skip_count > 0)
7826                                 aconn->psr_skip_count--;
7827
7828                         /* Allow PSR when skip count is 0. */
7829                         acrtc_attach->dm_irq_params.allow_psr_entry = !aconn->psr_skip_count;
7830
7831                         /*
7832                          * If sink supports PSR SU, there is no need to rely on
7833                          * a vblank event disable request to enable PSR. PSR SU
7834                          * can be enabled immediately once OS demonstrates an
7835                          * adequate number of fast atomic commits to notify KMD
7836                          * of update events. See `vblank_control_worker()`.
7837                          */
7838                         if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
7839                             acrtc_attach->dm_irq_params.allow_psr_entry &&
7840                             !acrtc_state->stream->link->psr_settings.psr_allow_active)
7841                                 amdgpu_dm_psr_enable(acrtc_state->stream);
7842                 } else {
7843                         acrtc_attach->dm_irq_params.allow_psr_entry = false;
7844                 }
7845
7846                 mutex_unlock(&dm->dc_lock);
7847         }
7848
7849         /*
7850          * Update cursor state *after* programming all the planes.
7851          * This avoids redundant programming in the case where we're going
7852          * to be disabling a single plane - those pipes are being disabled.
7853          */
7854         if (acrtc_state->active_planes)
7855                 amdgpu_dm_commit_cursors(state);
7856
7857 cleanup:
7858         kfree(bundle);
7859 }
7860
7861 static void amdgpu_dm_commit_audio(struct drm_device *dev,
7862                                    struct drm_atomic_state *state)
7863 {
7864         struct amdgpu_device *adev = drm_to_adev(dev);
7865         struct amdgpu_dm_connector *aconnector;
7866         struct drm_connector *connector;
7867         struct drm_connector_state *old_con_state, *new_con_state;
7868         struct drm_crtc_state *new_crtc_state;
7869         struct dm_crtc_state *new_dm_crtc_state;
7870         const struct dc_stream_status *status;
7871         int i, inst;
7872
7873         /* Notify device removals. */
7874         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
7875                 if (old_con_state->crtc != new_con_state->crtc) {
7876                         /* CRTC changes require notification. */
7877                         goto notify;
7878                 }
7879
7880                 if (!new_con_state->crtc)
7881                         continue;
7882
7883                 new_crtc_state = drm_atomic_get_new_crtc_state(
7884                         state, new_con_state->crtc);
7885
7886                 if (!new_crtc_state)
7887                         continue;
7888
7889                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
7890                         continue;
7891
7892         notify:
7893                 aconnector = to_amdgpu_dm_connector(connector);
7894
7895                 mutex_lock(&adev->dm.audio_lock);
7896                 inst = aconnector->audio_inst;
7897                 aconnector->audio_inst = -1;
7898                 mutex_unlock(&adev->dm.audio_lock);
7899
7900                 amdgpu_dm_audio_eld_notify(adev, inst);
7901         }
7902
7903         /* Notify audio device additions. */
7904         for_each_new_connector_in_state(state, connector, new_con_state, i) {
7905                 if (!new_con_state->crtc)
7906                         continue;
7907
7908                 new_crtc_state = drm_atomic_get_new_crtc_state(
7909                         state, new_con_state->crtc);
7910
7911                 if (!new_crtc_state)
7912                         continue;
7913
7914                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
7915                         continue;
7916
7917                 new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
7918                 if (!new_dm_crtc_state->stream)
7919                         continue;
7920
7921                 status = dc_stream_get_status(new_dm_crtc_state->stream);
7922                 if (!status)
7923                         continue;
7924
7925                 aconnector = to_amdgpu_dm_connector(connector);
7926
7927                 mutex_lock(&adev->dm.audio_lock);
7928                 inst = status->audio_inst;
7929                 aconnector->audio_inst = inst;
7930                 mutex_unlock(&adev->dm.audio_lock);
7931
7932                 amdgpu_dm_audio_eld_notify(adev, inst);
7933         }
7934 }
7935
7936 /*
7937  * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
7938  * @crtc_state: the DRM CRTC state
7939  * @stream_state: the DC stream state.
7940  *
7941  * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
7942  * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
7943  */
7944 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
7945                                                 struct dc_stream_state *stream_state)
7946 {
7947         stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state);
7948 }
7949
7950 /**
7951  * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation.
7952  * @state: The atomic state to commit
7953  *
7954  * This will tell DC to commit the constructed DC state from atomic_check,
7955  * programming the hardware. Any failures here implies a hardware failure, since
7956  * atomic check should have filtered anything non-kosher.
7957  */
7958 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
7959 {
7960         struct drm_device *dev = state->dev;
7961         struct amdgpu_device *adev = drm_to_adev(dev);
7962         struct amdgpu_display_manager *dm = &adev->dm;
7963         struct dm_atomic_state *dm_state;
7964         struct dc_state *dc_state = NULL, *dc_state_temp = NULL;
7965         uint32_t i, j;
7966         struct drm_crtc *crtc;
7967         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
7968         unsigned long flags;
7969         bool wait_for_vblank = true;
7970         struct drm_connector *connector;
7971         struct drm_connector_state *old_con_state, *new_con_state;
7972         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
7973         int crtc_disable_count = 0;
7974         bool mode_set_reset_required = false;
7975         int r;
7976
7977         trace_amdgpu_dm_atomic_commit_tail_begin(state);
7978
7979         r = drm_atomic_helper_wait_for_fences(dev, state, false);
7980         if (unlikely(r))
7981                 DRM_ERROR("Waiting for fences timed out!");
7982
7983         drm_atomic_helper_update_legacy_modeset_state(dev, state);
7984         drm_dp_mst_atomic_wait_for_dependencies(state);
7985
7986         dm_state = dm_atomic_get_new_state(state);
7987         if (dm_state && dm_state->context) {
7988                 dc_state = dm_state->context;
7989         } else {
7990                 /* No state changes, retain current state. */
7991                 dc_state_temp = dc_create_state(dm->dc);
7992                 ASSERT(dc_state_temp);
7993                 dc_state = dc_state_temp;
7994                 dc_resource_state_copy_construct_current(dm->dc, dc_state);
7995         }
7996
7997         for_each_oldnew_crtc_in_state (state, crtc, old_crtc_state,
7998                                        new_crtc_state, i) {
7999                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8000
8001                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8002
8003                 if (old_crtc_state->active &&
8004                     (!new_crtc_state->active ||
8005                      drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8006                         manage_dm_interrupts(adev, acrtc, false);
8007                         dc_stream_release(dm_old_crtc_state->stream);
8008                 }
8009         }
8010
8011         drm_atomic_helper_calc_timestamping_constants(state);
8012
8013         /* update changed items */
8014         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
8015                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8016
8017                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8018                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8019
8020                 drm_dbg_state(state->dev,
8021                         "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
8022                         "planes_changed:%d, mode_changed:%d,active_changed:%d,"
8023                         "connectors_changed:%d\n",
8024                         acrtc->crtc_id,
8025                         new_crtc_state->enable,
8026                         new_crtc_state->active,
8027                         new_crtc_state->planes_changed,
8028                         new_crtc_state->mode_changed,
8029                         new_crtc_state->active_changed,
8030                         new_crtc_state->connectors_changed);
8031
8032                 /* Disable cursor if disabling crtc */
8033                 if (old_crtc_state->active && !new_crtc_state->active) {
8034                         struct dc_cursor_position position;
8035
8036                         memset(&position, 0, sizeof(position));
8037                         mutex_lock(&dm->dc_lock);
8038                         dc_stream_set_cursor_position(dm_old_crtc_state->stream, &position);
8039                         mutex_unlock(&dm->dc_lock);
8040                 }
8041
8042                 /* Copy all transient state flags into dc state */
8043                 if (dm_new_crtc_state->stream) {
8044                         amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
8045                                                             dm_new_crtc_state->stream);
8046                 }
8047
8048                 /* handles headless hotplug case, updating new_state and
8049                  * aconnector as needed
8050                  */
8051
8052                 if (modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
8053
8054                         DRM_DEBUG_ATOMIC("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
8055
8056                         if (!dm_new_crtc_state->stream) {
8057                                 /*
8058                                  * this could happen because of issues with
8059                                  * userspace notifications delivery.
8060                                  * In this case userspace tries to set mode on
8061                                  * display which is disconnected in fact.
8062                                  * dc_sink is NULL in this case on aconnector.
8063                                  * We expect reset mode will come soon.
8064                                  *
8065                                  * This can also happen when unplug is done
8066                                  * during resume sequence ended
8067                                  *
8068                                  * In this case, we want to pretend we still
8069                                  * have a sink to keep the pipe running so that
8070                                  * hw state is consistent with the sw state
8071                                  */
8072                                 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
8073                                                 __func__, acrtc->base.base.id);
8074                                 continue;
8075                         }
8076
8077                         if (dm_old_crtc_state->stream)
8078                                 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
8079
8080                         pm_runtime_get_noresume(dev->dev);
8081
8082                         acrtc->enabled = true;
8083                         acrtc->hw_mode = new_crtc_state->mode;
8084                         crtc->hwmode = new_crtc_state->mode;
8085                         mode_set_reset_required = true;
8086                 } else if (modereset_required(new_crtc_state)) {
8087                         DRM_DEBUG_ATOMIC("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
8088                         /* i.e. reset mode */
8089                         if (dm_old_crtc_state->stream)
8090                                 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
8091
8092                         mode_set_reset_required = true;
8093                 }
8094         } /* for_each_crtc_in_state() */
8095
8096         if (dc_state) {
8097                 /* if there mode set or reset, disable eDP PSR */
8098                 if (mode_set_reset_required) {
8099                         if (dm->vblank_control_workqueue)
8100                                 flush_workqueue(dm->vblank_control_workqueue);
8101
8102                         amdgpu_dm_psr_disable_all(dm);
8103                 }
8104
8105                 dm_enable_per_frame_crtc_master_sync(dc_state);
8106                 mutex_lock(&dm->dc_lock);
8107                 WARN_ON(!dc_commit_state(dm->dc, dc_state));
8108
8109                 /* Allow idle optimization when vblank count is 0 for display off */
8110                 if (dm->active_vblank_irq_count == 0)
8111                         dc_allow_idle_optimizations(dm->dc, true);
8112                 mutex_unlock(&dm->dc_lock);
8113         }
8114
8115         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
8116                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8117
8118                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8119
8120                 if (dm_new_crtc_state->stream != NULL) {
8121                         const struct dc_stream_status *status =
8122                                         dc_stream_get_status(dm_new_crtc_state->stream);
8123
8124                         if (!status)
8125                                 status = dc_stream_get_status_from_state(dc_state,
8126                                                                          dm_new_crtc_state->stream);
8127                         if (!status)
8128                                 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc);
8129                         else
8130                                 acrtc->otg_inst = status->primary_otg_inst;
8131                 }
8132         }
8133 #ifdef CONFIG_DRM_AMD_DC_HDCP
8134         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8135                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8136                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8137                 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8138
8139                 new_crtc_state = NULL;
8140
8141                 if (acrtc)
8142                         new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8143
8144                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8145
8146                 if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL &&
8147                     connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) {
8148                         hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
8149                         new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
8150                         dm_new_con_state->update_hdcp = true;
8151                         continue;
8152                 }
8153
8154                 if (is_content_protection_different(new_con_state, old_con_state, connector, adev->dm.hdcp_workqueue))
8155                         hdcp_update_display(
8156                                 adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector,
8157                                 new_con_state->hdcp_content_type,
8158                                 new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED);
8159         }
8160 #endif
8161
8162         /* Handle connector state changes */
8163         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
8164                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
8165                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
8166                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
8167                 struct dc_surface_update dummy_updates[MAX_SURFACES];
8168                 struct dc_stream_update stream_update;
8169                 struct dc_info_packet hdr_packet;
8170                 struct dc_stream_status *status = NULL;
8171                 bool abm_changed, hdr_changed, scaling_changed;
8172
8173                 memset(&dummy_updates, 0, sizeof(dummy_updates));
8174                 memset(&stream_update, 0, sizeof(stream_update));
8175
8176                 if (acrtc) {
8177                         new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
8178                         old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
8179                 }
8180
8181                 /* Skip any modesets/resets */
8182                 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
8183                         continue;
8184
8185                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8186                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8187
8188                 scaling_changed = is_scaling_state_different(dm_new_con_state,
8189                                                              dm_old_con_state);
8190
8191                 abm_changed = dm_new_crtc_state->abm_level !=
8192                               dm_old_crtc_state->abm_level;
8193
8194                 hdr_changed =
8195                         !drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state);
8196
8197                 if (!scaling_changed && !abm_changed && !hdr_changed)
8198                         continue;
8199
8200                 stream_update.stream = dm_new_crtc_state->stream;
8201                 if (scaling_changed) {
8202                         update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
8203                                         dm_new_con_state, dm_new_crtc_state->stream);
8204
8205                         stream_update.src = dm_new_crtc_state->stream->src;
8206                         stream_update.dst = dm_new_crtc_state->stream->dst;
8207                 }
8208
8209                 if (abm_changed) {
8210                         dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level;
8211
8212                         stream_update.abm_level = &dm_new_crtc_state->abm_level;
8213                 }
8214
8215                 if (hdr_changed) {
8216                         fill_hdr_info_packet(new_con_state, &hdr_packet);
8217                         stream_update.hdr_static_metadata = &hdr_packet;
8218                 }
8219
8220                 status = dc_stream_get_status(dm_new_crtc_state->stream);
8221
8222                 if (WARN_ON(!status))
8223                         continue;
8224
8225                 WARN_ON(!status->plane_count);
8226
8227                 /*
8228                  * TODO: DC refuses to perform stream updates without a dc_surface_update.
8229                  * Here we create an empty update on each plane.
8230                  * To fix this, DC should permit updating only stream properties.
8231                  */
8232                 for (j = 0; j < status->plane_count; j++)
8233                         dummy_updates[j].surface = status->plane_states[0];
8234
8235
8236                 mutex_lock(&dm->dc_lock);
8237                 dc_commit_updates_for_stream(dm->dc,
8238                                                      dummy_updates,
8239                                                      status->plane_count,
8240                                                      dm_new_crtc_state->stream,
8241                                                      &stream_update,
8242                                                      dc_state);
8243                 mutex_unlock(&dm->dc_lock);
8244         }
8245
8246         /* Count number of newly disabled CRTCs for dropping PM refs later. */
8247         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
8248                                       new_crtc_state, i) {
8249                 if (old_crtc_state->active && !new_crtc_state->active)
8250                         crtc_disable_count++;
8251
8252                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8253                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8254
8255                 /* For freesync config update on crtc state and params for irq */
8256                 update_stream_irq_parameters(dm, dm_new_crtc_state);
8257
8258                 /* Handle vrr on->off / off->on transitions */
8259                 amdgpu_dm_handle_vrr_transition(dm_old_crtc_state,
8260                                                 dm_new_crtc_state);
8261         }
8262
8263         /**
8264          * Enable interrupts for CRTCs that are newly enabled or went through
8265          * a modeset. It was intentionally deferred until after the front end
8266          * state was modified to wait until the OTG was on and so the IRQ
8267          * handlers didn't access stale or invalid state.
8268          */
8269         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
8270                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
8271 #ifdef CONFIG_DEBUG_FS
8272                 bool configure_crc = false;
8273                 enum amdgpu_dm_pipe_crc_source cur_crc_src;
8274 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
8275                 struct crc_rd_work *crc_rd_wrk = dm->crc_rd_wrk;
8276 #endif
8277                 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8278                 cur_crc_src = acrtc->dm_irq_params.crc_src;
8279                 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8280 #endif
8281                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8282
8283                 if (new_crtc_state->active &&
8284                     (!old_crtc_state->active ||
8285                      drm_atomic_crtc_needs_modeset(new_crtc_state))) {
8286                         dc_stream_retain(dm_new_crtc_state->stream);
8287                         acrtc->dm_irq_params.stream = dm_new_crtc_state->stream;
8288                         manage_dm_interrupts(adev, acrtc, true);
8289
8290 #ifdef CONFIG_DEBUG_FS
8291                         /**
8292                          * Frontend may have changed so reapply the CRC capture
8293                          * settings for the stream.
8294                          */
8295                         dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8296
8297                         if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) {
8298                                 configure_crc = true;
8299 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
8300                                 if (amdgpu_dm_crc_window_is_activated(crtc)) {
8301                                         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8302                                         acrtc->dm_irq_params.crc_window.update_win = true;
8303                                         acrtc->dm_irq_params.crc_window.skip_frame_cnt = 2;
8304                                         spin_lock_irq(&crc_rd_wrk->crc_rd_work_lock);
8305                                         crc_rd_wrk->crtc = crtc;
8306                                         spin_unlock_irq(&crc_rd_wrk->crc_rd_work_lock);
8307                                         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8308                                 }
8309 #endif
8310                         }
8311
8312                         if (configure_crc)
8313                                 if (amdgpu_dm_crtc_configure_crc_source(
8314                                         crtc, dm_new_crtc_state, cur_crc_src))
8315                                         DRM_DEBUG_DRIVER("Failed to configure crc source");
8316 #endif
8317                 }
8318         }
8319
8320         for_each_new_crtc_in_state(state, crtc, new_crtc_state, j)
8321                 if (new_crtc_state->async_flip)
8322                         wait_for_vblank = false;
8323
8324         /* update planes when needed per crtc*/
8325         for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
8326                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8327
8328                 if (dm_new_crtc_state->stream)
8329                         amdgpu_dm_commit_planes(state, dc_state, dev,
8330                                                 dm, crtc, wait_for_vblank);
8331         }
8332
8333         /* Update audio instances for each connector. */
8334         amdgpu_dm_commit_audio(dev, state);
8335
8336         /* restore the backlight level */
8337         for (i = 0; i < dm->num_of_edps; i++) {
8338                 if (dm->backlight_dev[i] &&
8339                     (dm->actual_brightness[i] != dm->brightness[i]))
8340                         amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]);
8341         }
8342
8343         /*
8344          * send vblank event on all events not handled in flip and
8345          * mark consumed event for drm_atomic_helper_commit_hw_done
8346          */
8347         spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
8348         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
8349
8350                 if (new_crtc_state->event)
8351                         drm_send_event_locked(dev, &new_crtc_state->event->base);
8352
8353                 new_crtc_state->event = NULL;
8354         }
8355         spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
8356
8357         /* Signal HW programming completion */
8358         drm_atomic_helper_commit_hw_done(state);
8359
8360         if (wait_for_vblank)
8361                 drm_atomic_helper_wait_for_flip_done(dev, state);
8362
8363         drm_atomic_helper_cleanup_planes(dev, state);
8364
8365         /* return the stolen vga memory back to VRAM */
8366         if (!adev->mman.keep_stolen_vga_memory)
8367                 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
8368         amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
8369
8370         /*
8371          * Finally, drop a runtime PM reference for each newly disabled CRTC,
8372          * so we can put the GPU into runtime suspend if we're not driving any
8373          * displays anymore
8374          */
8375         for (i = 0; i < crtc_disable_count; i++)
8376                 pm_runtime_put_autosuspend(dev->dev);
8377         pm_runtime_mark_last_busy(dev->dev);
8378
8379         if (dc_state_temp)
8380                 dc_release_state(dc_state_temp);
8381 }
8382
8383 static int dm_force_atomic_commit(struct drm_connector *connector)
8384 {
8385         int ret = 0;
8386         struct drm_device *ddev = connector->dev;
8387         struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
8388         struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
8389         struct drm_plane *plane = disconnected_acrtc->base.primary;
8390         struct drm_connector_state *conn_state;
8391         struct drm_crtc_state *crtc_state;
8392         struct drm_plane_state *plane_state;
8393
8394         if (!state)
8395                 return -ENOMEM;
8396
8397         state->acquire_ctx = ddev->mode_config.acquire_ctx;
8398
8399         /* Construct an atomic state to restore previous display setting */
8400
8401         /*
8402          * Attach connectors to drm_atomic_state
8403          */
8404         conn_state = drm_atomic_get_connector_state(state, connector);
8405
8406         ret = PTR_ERR_OR_ZERO(conn_state);
8407         if (ret)
8408                 goto out;
8409
8410         /* Attach crtc to drm_atomic_state*/
8411         crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
8412
8413         ret = PTR_ERR_OR_ZERO(crtc_state);
8414         if (ret)
8415                 goto out;
8416
8417         /* force a restore */
8418         crtc_state->mode_changed = true;
8419
8420         /* Attach plane to drm_atomic_state */
8421         plane_state = drm_atomic_get_plane_state(state, plane);
8422
8423         ret = PTR_ERR_OR_ZERO(plane_state);
8424         if (ret)
8425                 goto out;
8426
8427         /* Call commit internally with the state we just constructed */
8428         ret = drm_atomic_commit(state);
8429
8430 out:
8431         drm_atomic_state_put(state);
8432         if (ret)
8433                 DRM_ERROR("Restoring old state failed with %i\n", ret);
8434
8435         return ret;
8436 }
8437
8438 /*
8439  * This function handles all cases when set mode does not come upon hotplug.
8440  * This includes when a display is unplugged then plugged back into the
8441  * same port and when running without usermode desktop manager supprot
8442  */
8443 void dm_restore_drm_connector_state(struct drm_device *dev,
8444                                     struct drm_connector *connector)
8445 {
8446         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
8447         struct amdgpu_crtc *disconnected_acrtc;
8448         struct dm_crtc_state *acrtc_state;
8449
8450         if (!aconnector->dc_sink || !connector->state || !connector->encoder)
8451                 return;
8452
8453         disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
8454         if (!disconnected_acrtc)
8455                 return;
8456
8457         acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
8458         if (!acrtc_state->stream)
8459                 return;
8460
8461         /*
8462          * If the previous sink is not released and different from the current,
8463          * we deduce we are in a state where we can not rely on usermode call
8464          * to turn on the display, so we do it here
8465          */
8466         if (acrtc_state->stream->sink != aconnector->dc_sink)
8467                 dm_force_atomic_commit(&aconnector->base);
8468 }
8469
8470 /*
8471  * Grabs all modesetting locks to serialize against any blocking commits,
8472  * Waits for completion of all non blocking commits.
8473  */
8474 static int do_aquire_global_lock(struct drm_device *dev,
8475                                  struct drm_atomic_state *state)
8476 {
8477         struct drm_crtc *crtc;
8478         struct drm_crtc_commit *commit;
8479         long ret;
8480
8481         /*
8482          * Adding all modeset locks to aquire_ctx will
8483          * ensure that when the framework release it the
8484          * extra locks we are locking here will get released to
8485          */
8486         ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
8487         if (ret)
8488                 return ret;
8489
8490         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8491                 spin_lock(&crtc->commit_lock);
8492                 commit = list_first_entry_or_null(&crtc->commit_list,
8493                                 struct drm_crtc_commit, commit_entry);
8494                 if (commit)
8495                         drm_crtc_commit_get(commit);
8496                 spin_unlock(&crtc->commit_lock);
8497
8498                 if (!commit)
8499                         continue;
8500
8501                 /*
8502                  * Make sure all pending HW programming completed and
8503                  * page flips done
8504                  */
8505                 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
8506
8507                 if (ret > 0)
8508                         ret = wait_for_completion_interruptible_timeout(
8509                                         &commit->flip_done, 10*HZ);
8510
8511                 if (ret == 0)
8512                         DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
8513                                   "timed out\n", crtc->base.id, crtc->name);
8514
8515                 drm_crtc_commit_put(commit);
8516         }
8517
8518         return ret < 0 ? ret : 0;
8519 }
8520
8521 static void get_freesync_config_for_crtc(
8522         struct dm_crtc_state *new_crtc_state,
8523         struct dm_connector_state *new_con_state)
8524 {
8525         struct mod_freesync_config config = {0};
8526         struct amdgpu_dm_connector *aconnector =
8527                         to_amdgpu_dm_connector(new_con_state->base.connector);
8528         struct drm_display_mode *mode = &new_crtc_state->base.mode;
8529         int vrefresh = drm_mode_vrefresh(mode);
8530         bool fs_vid_mode = false;
8531
8532         new_crtc_state->vrr_supported = new_con_state->freesync_capable &&
8533                                         vrefresh >= aconnector->min_vfreq &&
8534                                         vrefresh <= aconnector->max_vfreq;
8535
8536         if (new_crtc_state->vrr_supported) {
8537                 new_crtc_state->stream->ignore_msa_timing_param = true;
8538                 fs_vid_mode = new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
8539
8540                 config.min_refresh_in_uhz = aconnector->min_vfreq * 1000000;
8541                 config.max_refresh_in_uhz = aconnector->max_vfreq * 1000000;
8542                 config.vsif_supported = true;
8543                 config.btr = true;
8544
8545                 if (fs_vid_mode) {
8546                         config.state = VRR_STATE_ACTIVE_FIXED;
8547                         config.fixed_refresh_in_uhz = new_crtc_state->freesync_config.fixed_refresh_in_uhz;
8548                         goto out;
8549                 } else if (new_crtc_state->base.vrr_enabled) {
8550                         config.state = VRR_STATE_ACTIVE_VARIABLE;
8551                 } else {
8552                         config.state = VRR_STATE_INACTIVE;
8553                 }
8554         }
8555 out:
8556         new_crtc_state->freesync_config = config;
8557 }
8558
8559 static void reset_freesync_config_for_crtc(
8560         struct dm_crtc_state *new_crtc_state)
8561 {
8562         new_crtc_state->vrr_supported = false;
8563
8564         memset(&new_crtc_state->vrr_infopacket, 0,
8565                sizeof(new_crtc_state->vrr_infopacket));
8566 }
8567
8568 static bool
8569 is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
8570                                  struct drm_crtc_state *new_crtc_state)
8571 {
8572         const struct drm_display_mode *old_mode, *new_mode;
8573
8574         if (!old_crtc_state || !new_crtc_state)
8575                 return false;
8576
8577         old_mode = &old_crtc_state->mode;
8578         new_mode = &new_crtc_state->mode;
8579
8580         if (old_mode->clock       == new_mode->clock &&
8581             old_mode->hdisplay    == new_mode->hdisplay &&
8582             old_mode->vdisplay    == new_mode->vdisplay &&
8583             old_mode->htotal      == new_mode->htotal &&
8584             old_mode->vtotal      != new_mode->vtotal &&
8585             old_mode->hsync_start == new_mode->hsync_start &&
8586             old_mode->vsync_start != new_mode->vsync_start &&
8587             old_mode->hsync_end   == new_mode->hsync_end &&
8588             old_mode->vsync_end   != new_mode->vsync_end &&
8589             old_mode->hskew       == new_mode->hskew &&
8590             old_mode->vscan       == new_mode->vscan &&
8591             (old_mode->vsync_end - old_mode->vsync_start) ==
8592             (new_mode->vsync_end - new_mode->vsync_start))
8593                 return true;
8594
8595         return false;
8596 }
8597
8598 static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state) {
8599         uint64_t num, den, res;
8600         struct drm_crtc_state *new_crtc_state = &dm_new_crtc_state->base;
8601
8602         dm_new_crtc_state->freesync_config.state = VRR_STATE_ACTIVE_FIXED;
8603
8604         num = (unsigned long long)new_crtc_state->mode.clock * 1000 * 1000000;
8605         den = (unsigned long long)new_crtc_state->mode.htotal *
8606               (unsigned long long)new_crtc_state->mode.vtotal;
8607
8608         res = div_u64(num, den);
8609         dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = res;
8610 }
8611
8612 static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
8613                          struct drm_atomic_state *state,
8614                          struct drm_crtc *crtc,
8615                          struct drm_crtc_state *old_crtc_state,
8616                          struct drm_crtc_state *new_crtc_state,
8617                          bool enable,
8618                          bool *lock_and_validation_needed)
8619 {
8620         struct dm_atomic_state *dm_state = NULL;
8621         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
8622         struct dc_stream_state *new_stream;
8623         int ret = 0;
8624
8625         /*
8626          * TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set
8627          * update changed items
8628          */
8629         struct amdgpu_crtc *acrtc = NULL;
8630         struct amdgpu_dm_connector *aconnector = NULL;
8631         struct drm_connector_state *drm_new_conn_state = NULL, *drm_old_conn_state = NULL;
8632         struct dm_connector_state *dm_new_conn_state = NULL, *dm_old_conn_state = NULL;
8633
8634         new_stream = NULL;
8635
8636         dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
8637         dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
8638         acrtc = to_amdgpu_crtc(crtc);
8639         aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
8640
8641         /* TODO This hack should go away */
8642         if (aconnector && enable) {
8643                 /* Make sure fake sink is created in plug-in scenario */
8644                 drm_new_conn_state = drm_atomic_get_new_connector_state(state,
8645                                                             &aconnector->base);
8646                 drm_old_conn_state = drm_atomic_get_old_connector_state(state,
8647                                                             &aconnector->base);
8648
8649                 if (IS_ERR(drm_new_conn_state)) {
8650                         ret = PTR_ERR_OR_ZERO(drm_new_conn_state);
8651                         goto fail;
8652                 }
8653
8654                 dm_new_conn_state = to_dm_connector_state(drm_new_conn_state);
8655                 dm_old_conn_state = to_dm_connector_state(drm_old_conn_state);
8656
8657                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8658                         goto skip_modeset;
8659
8660                 new_stream = create_validate_stream_for_sink(aconnector,
8661                                                              &new_crtc_state->mode,
8662                                                              dm_new_conn_state,
8663                                                              dm_old_crtc_state->stream);
8664
8665                 /*
8666                  * we can have no stream on ACTION_SET if a display
8667                  * was disconnected during S3, in this case it is not an
8668                  * error, the OS will be updated after detection, and
8669                  * will do the right thing on next atomic commit
8670                  */
8671
8672                 if (!new_stream) {
8673                         DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
8674                                         __func__, acrtc->base.base.id);
8675                         ret = -ENOMEM;
8676                         goto fail;
8677                 }
8678
8679                 /*
8680                  * TODO: Check VSDB bits to decide whether this should
8681                  * be enabled or not.
8682                  */
8683                 new_stream->triggered_crtc_reset.enabled =
8684                         dm->force_timing_sync;
8685
8686                 dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
8687
8688                 ret = fill_hdr_info_packet(drm_new_conn_state,
8689                                            &new_stream->hdr_static_metadata);
8690                 if (ret)
8691                         goto fail;
8692
8693                 /*
8694                  * If we already removed the old stream from the context
8695                  * (and set the new stream to NULL) then we can't reuse
8696                  * the old stream even if the stream and scaling are unchanged.
8697                  * We'll hit the BUG_ON and black screen.
8698                  *
8699                  * TODO: Refactor this function to allow this check to work
8700                  * in all conditions.
8701                  */
8702                 if (dm_new_crtc_state->stream &&
8703                     is_timing_unchanged_for_freesync(new_crtc_state, old_crtc_state))
8704                         goto skip_modeset;
8705
8706                 if (dm_new_crtc_state->stream &&
8707                     dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
8708                     dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
8709                         new_crtc_state->mode_changed = false;
8710                         DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
8711                                          new_crtc_state->mode_changed);
8712                 }
8713         }
8714
8715         /* mode_changed flag may get updated above, need to check again */
8716         if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
8717                 goto skip_modeset;
8718
8719         drm_dbg_state(state->dev,
8720                 "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
8721                 "planes_changed:%d, mode_changed:%d,active_changed:%d,"
8722                 "connectors_changed:%d\n",
8723                 acrtc->crtc_id,
8724                 new_crtc_state->enable,
8725                 new_crtc_state->active,
8726                 new_crtc_state->planes_changed,
8727                 new_crtc_state->mode_changed,
8728                 new_crtc_state->active_changed,
8729                 new_crtc_state->connectors_changed);
8730
8731         /* Remove stream for any changed/disabled CRTC */
8732         if (!enable) {
8733
8734                 if (!dm_old_crtc_state->stream)
8735                         goto skip_modeset;
8736
8737                 if (dm_new_crtc_state->stream &&
8738                     is_timing_unchanged_for_freesync(new_crtc_state,
8739                                                      old_crtc_state)) {
8740                         new_crtc_state->mode_changed = false;
8741                         DRM_DEBUG_DRIVER(
8742                                 "Mode change not required for front porch change, "
8743                                 "setting mode_changed to %d",
8744                                 new_crtc_state->mode_changed);
8745
8746                         set_freesync_fixed_config(dm_new_crtc_state);
8747
8748                         goto skip_modeset;
8749                 } else if (aconnector &&
8750                            is_freesync_video_mode(&new_crtc_state->mode,
8751                                                   aconnector)) {
8752                         struct drm_display_mode *high_mode;
8753
8754                         high_mode = get_highest_refresh_rate_mode(aconnector, false);
8755                         if (!drm_mode_equal(&new_crtc_state->mode, high_mode)) {
8756                                 set_freesync_fixed_config(dm_new_crtc_state);
8757                         }
8758                 }
8759
8760                 ret = dm_atomic_get_state(state, &dm_state);
8761                 if (ret)
8762                         goto fail;
8763
8764                 DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
8765                                 crtc->base.id);
8766
8767                 /* i.e. reset mode */
8768                 if (dc_remove_stream_from_ctx(
8769                                 dm->dc,
8770                                 dm_state->context,
8771                                 dm_old_crtc_state->stream) != DC_OK) {
8772                         ret = -EINVAL;
8773                         goto fail;
8774                 }
8775
8776                 dc_stream_release(dm_old_crtc_state->stream);
8777                 dm_new_crtc_state->stream = NULL;
8778
8779                 reset_freesync_config_for_crtc(dm_new_crtc_state);
8780
8781                 *lock_and_validation_needed = true;
8782
8783         } else {/* Add stream for any updated/enabled CRTC */
8784                 /*
8785                  * Quick fix to prevent NULL pointer on new_stream when
8786                  * added MST connectors not found in existing crtc_state in the chained mode
8787                  * TODO: need to dig out the root cause of that
8788                  */
8789                 if (!aconnector)
8790                         goto skip_modeset;
8791
8792                 if (modereset_required(new_crtc_state))
8793                         goto skip_modeset;
8794
8795                 if (modeset_required(new_crtc_state, new_stream,
8796                                      dm_old_crtc_state->stream)) {
8797
8798                         WARN_ON(dm_new_crtc_state->stream);
8799
8800                         ret = dm_atomic_get_state(state, &dm_state);
8801                         if (ret)
8802                                 goto fail;
8803
8804                         dm_new_crtc_state->stream = new_stream;
8805
8806                         dc_stream_retain(new_stream);
8807
8808                         DRM_DEBUG_ATOMIC("Enabling DRM crtc: %d\n",
8809                                          crtc->base.id);
8810
8811                         if (dc_add_stream_to_ctx(
8812                                         dm->dc,
8813                                         dm_state->context,
8814                                         dm_new_crtc_state->stream) != DC_OK) {
8815                                 ret = -EINVAL;
8816                                 goto fail;
8817                         }
8818
8819                         *lock_and_validation_needed = true;
8820                 }
8821         }
8822
8823 skip_modeset:
8824         /* Release extra reference */
8825         if (new_stream)
8826                  dc_stream_release(new_stream);
8827
8828         /*
8829          * We want to do dc stream updates that do not require a
8830          * full modeset below.
8831          */
8832         if (!(enable && aconnector && new_crtc_state->active))
8833                 return 0;
8834         /*
8835          * Given above conditions, the dc state cannot be NULL because:
8836          * 1. We're in the process of enabling CRTCs (just been added
8837          *    to the dc context, or already is on the context)
8838          * 2. Has a valid connector attached, and
8839          * 3. Is currently active and enabled.
8840          * => The dc stream state currently exists.
8841          */
8842         BUG_ON(dm_new_crtc_state->stream == NULL);
8843
8844         /* Scaling or underscan settings */
8845         if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state) ||
8846                                 drm_atomic_crtc_needs_modeset(new_crtc_state))
8847                 update_stream_scaling_settings(
8848                         &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);
8849
8850         /* ABM settings */
8851         dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;
8852
8853         /*
8854          * Color management settings. We also update color properties
8855          * when a modeset is needed, to ensure it gets reprogrammed.
8856          */
8857         if (dm_new_crtc_state->base.color_mgmt_changed ||
8858             drm_atomic_crtc_needs_modeset(new_crtc_state)) {
8859                 ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state);
8860                 if (ret)
8861                         goto fail;
8862         }
8863
8864         /* Update Freesync settings. */
8865         get_freesync_config_for_crtc(dm_new_crtc_state,
8866                                      dm_new_conn_state);
8867
8868         return ret;
8869
8870 fail:
8871         if (new_stream)
8872                 dc_stream_release(new_stream);
8873         return ret;
8874 }
8875
8876 static bool should_reset_plane(struct drm_atomic_state *state,
8877                                struct drm_plane *plane,
8878                                struct drm_plane_state *old_plane_state,
8879                                struct drm_plane_state *new_plane_state)
8880 {
8881         struct drm_plane *other;
8882         struct drm_plane_state *old_other_state, *new_other_state;
8883         struct drm_crtc_state *new_crtc_state;
8884         int i;
8885
8886         /*
8887          * TODO: Remove this hack once the checks below are sufficient
8888          * enough to determine when we need to reset all the planes on
8889          * the stream.
8890          */
8891         if (state->allow_modeset)
8892                 return true;
8893
8894         /* Exit early if we know that we're adding or removing the plane. */
8895         if (old_plane_state->crtc != new_plane_state->crtc)
8896                 return true;
8897
8898         /* old crtc == new_crtc == NULL, plane not in context. */
8899         if (!new_plane_state->crtc)
8900                 return false;
8901
8902         new_crtc_state =
8903                 drm_atomic_get_new_crtc_state(state, new_plane_state->crtc);
8904
8905         if (!new_crtc_state)
8906                 return true;
8907
8908         /* CRTC Degamma changes currently require us to recreate planes. */
8909         if (new_crtc_state->color_mgmt_changed)
8910                 return true;
8911
8912         if (drm_atomic_crtc_needs_modeset(new_crtc_state))
8913                 return true;
8914
8915         /*
8916          * If there are any new primary or overlay planes being added or
8917          * removed then the z-order can potentially change. To ensure
8918          * correct z-order and pipe acquisition the current DC architecture
8919          * requires us to remove and recreate all existing planes.
8920          *
8921          * TODO: Come up with a more elegant solution for this.
8922          */
8923         for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) {
8924                 struct amdgpu_framebuffer *old_afb, *new_afb;
8925                 if (other->type == DRM_PLANE_TYPE_CURSOR)
8926                         continue;
8927
8928                 if (old_other_state->crtc != new_plane_state->crtc &&
8929                     new_other_state->crtc != new_plane_state->crtc)
8930                         continue;
8931
8932                 if (old_other_state->crtc != new_other_state->crtc)
8933                         return true;
8934
8935                 /* Src/dst size and scaling updates. */
8936                 if (old_other_state->src_w != new_other_state->src_w ||
8937                     old_other_state->src_h != new_other_state->src_h ||
8938                     old_other_state->crtc_w != new_other_state->crtc_w ||
8939                     old_other_state->crtc_h != new_other_state->crtc_h)
8940                         return true;
8941
8942                 /* Rotation / mirroring updates. */
8943                 if (old_other_state->rotation != new_other_state->rotation)
8944                         return true;
8945
8946                 /* Blending updates. */
8947                 if (old_other_state->pixel_blend_mode !=
8948                     new_other_state->pixel_blend_mode)
8949                         return true;
8950
8951                 /* Alpha updates. */
8952                 if (old_other_state->alpha != new_other_state->alpha)
8953                         return true;
8954
8955                 /* Colorspace changes. */
8956                 if (old_other_state->color_range != new_other_state->color_range ||
8957                     old_other_state->color_encoding != new_other_state->color_encoding)
8958                         return true;
8959
8960                 /* Framebuffer checks fall at the end. */
8961                 if (!old_other_state->fb || !new_other_state->fb)
8962                         continue;
8963
8964                 /* Pixel format changes can require bandwidth updates. */
8965                 if (old_other_state->fb->format != new_other_state->fb->format)
8966                         return true;
8967
8968                 old_afb = (struct amdgpu_framebuffer *)old_other_state->fb;
8969                 new_afb = (struct amdgpu_framebuffer *)new_other_state->fb;
8970
8971                 /* Tiling and DCC changes also require bandwidth updates. */
8972                 if (old_afb->tiling_flags != new_afb->tiling_flags ||
8973                     old_afb->base.modifier != new_afb->base.modifier)
8974                         return true;
8975         }
8976
8977         return false;
8978 }
8979
8980 static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc,
8981                               struct drm_plane_state *new_plane_state,
8982                               struct drm_framebuffer *fb)
8983 {
8984         struct amdgpu_device *adev = drm_to_adev(new_acrtc->base.dev);
8985         struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
8986         unsigned int pitch;
8987         bool linear;
8988
8989         if (fb->width > new_acrtc->max_cursor_width ||
8990             fb->height > new_acrtc->max_cursor_height) {
8991                 DRM_DEBUG_ATOMIC("Bad cursor FB size %dx%d\n",
8992                                  new_plane_state->fb->width,
8993                                  new_plane_state->fb->height);
8994                 return -EINVAL;
8995         }
8996         if (new_plane_state->src_w != fb->width << 16 ||
8997             new_plane_state->src_h != fb->height << 16) {
8998                 DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
8999                 return -EINVAL;
9000         }
9001
9002         /* Pitch in pixels */
9003         pitch = fb->pitches[0] / fb->format->cpp[0];
9004
9005         if (fb->width != pitch) {
9006                 DRM_DEBUG_ATOMIC("Cursor FB width %d doesn't match pitch %d",
9007                                  fb->width, pitch);
9008                 return -EINVAL;
9009         }
9010
9011         switch (pitch) {
9012         case 64:
9013         case 128:
9014         case 256:
9015                 /* FB pitch is supported by cursor plane */
9016                 break;
9017         default:
9018                 DRM_DEBUG_ATOMIC("Bad cursor FB pitch %d px\n", pitch);
9019                 return -EINVAL;
9020         }
9021
9022         /* Core DRM takes care of checking FB modifiers, so we only need to
9023          * check tiling flags when the FB doesn't have a modifier. */
9024         if (!(fb->flags & DRM_MODE_FB_MODIFIERS)) {
9025                 if (adev->family < AMDGPU_FAMILY_AI) {
9026                         linear = AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_2D_TILED_THIN1 &&
9027                                  AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 &&
9028                                  AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE) == 0;
9029                 } else {
9030                         linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0;
9031                 }
9032                 if (!linear) {
9033                         DRM_DEBUG_ATOMIC("Cursor FB not linear");
9034                         return -EINVAL;
9035                 }
9036         }
9037
9038         return 0;
9039 }
9040
9041 static int dm_update_plane_state(struct dc *dc,
9042                                  struct drm_atomic_state *state,
9043                                  struct drm_plane *plane,
9044                                  struct drm_plane_state *old_plane_state,
9045                                  struct drm_plane_state *new_plane_state,
9046                                  bool enable,
9047                                  bool *lock_and_validation_needed)
9048 {
9049
9050         struct dm_atomic_state *dm_state = NULL;
9051         struct drm_crtc *new_plane_crtc, *old_plane_crtc;
9052         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
9053         struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
9054         struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
9055         struct amdgpu_crtc *new_acrtc;
9056         bool needs_reset;
9057         int ret = 0;
9058
9059
9060         new_plane_crtc = new_plane_state->crtc;
9061         old_plane_crtc = old_plane_state->crtc;
9062         dm_new_plane_state = to_dm_plane_state(new_plane_state);
9063         dm_old_plane_state = to_dm_plane_state(old_plane_state);
9064
9065         if (plane->type == DRM_PLANE_TYPE_CURSOR) {
9066                 if (!enable || !new_plane_crtc ||
9067                         drm_atomic_plane_disabling(plane->state, new_plane_state))
9068                         return 0;
9069
9070                 new_acrtc = to_amdgpu_crtc(new_plane_crtc);
9071
9072                 if (new_plane_state->src_x != 0 || new_plane_state->src_y != 0) {
9073                         DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
9074                         return -EINVAL;
9075                 }
9076
9077                 if (new_plane_state->fb) {
9078                         ret = dm_check_cursor_fb(new_acrtc, new_plane_state,
9079                                                  new_plane_state->fb);
9080                         if (ret)
9081                                 return ret;
9082                 }
9083
9084                 return 0;
9085         }
9086
9087         needs_reset = should_reset_plane(state, plane, old_plane_state,
9088                                          new_plane_state);
9089
9090         /* Remove any changed/removed planes */
9091         if (!enable) {
9092                 if (!needs_reset)
9093                         return 0;
9094
9095                 if (!old_plane_crtc)
9096                         return 0;
9097
9098                 old_crtc_state = drm_atomic_get_old_crtc_state(
9099                                 state, old_plane_crtc);
9100                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9101
9102                 if (!dm_old_crtc_state->stream)
9103                         return 0;
9104
9105                 DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",
9106                                 plane->base.id, old_plane_crtc->base.id);
9107
9108                 ret = dm_atomic_get_state(state, &dm_state);
9109                 if (ret)
9110                         return ret;
9111
9112                 if (!dc_remove_plane_from_context(
9113                                 dc,
9114                                 dm_old_crtc_state->stream,
9115                                 dm_old_plane_state->dc_state,
9116                                 dm_state->context)) {
9117
9118                         return -EINVAL;
9119                 }
9120
9121
9122                 dc_plane_state_release(dm_old_plane_state->dc_state);
9123                 dm_new_plane_state->dc_state = NULL;
9124
9125                 *lock_and_validation_needed = true;
9126
9127         } else { /* Add new planes */
9128                 struct dc_plane_state *dc_new_plane_state;
9129
9130                 if (drm_atomic_plane_disabling(plane->state, new_plane_state))
9131                         return 0;
9132
9133                 if (!new_plane_crtc)
9134                         return 0;
9135
9136                 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
9137                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9138
9139                 if (!dm_new_crtc_state->stream)
9140                         return 0;
9141
9142                 if (!needs_reset)
9143                         return 0;
9144
9145                 ret = dm_plane_helper_check_state(new_plane_state, new_crtc_state);
9146                 if (ret)
9147                         return ret;
9148
9149                 WARN_ON(dm_new_plane_state->dc_state);
9150
9151                 dc_new_plane_state = dc_create_plane_state(dc);
9152                 if (!dc_new_plane_state)
9153                         return -ENOMEM;
9154
9155                 DRM_DEBUG_ATOMIC("Enabling DRM plane: %d on DRM crtc %d\n",
9156                                  plane->base.id, new_plane_crtc->base.id);
9157
9158                 ret = fill_dc_plane_attributes(
9159                         drm_to_adev(new_plane_crtc->dev),
9160                         dc_new_plane_state,
9161                         new_plane_state,
9162                         new_crtc_state);
9163                 if (ret) {
9164                         dc_plane_state_release(dc_new_plane_state);
9165                         return ret;
9166                 }
9167
9168                 ret = dm_atomic_get_state(state, &dm_state);
9169                 if (ret) {
9170                         dc_plane_state_release(dc_new_plane_state);
9171                         return ret;
9172                 }
9173
9174                 /*
9175                  * Any atomic check errors that occur after this will
9176                  * not need a release. The plane state will be attached
9177                  * to the stream, and therefore part of the atomic
9178                  * state. It'll be released when the atomic state is
9179                  * cleaned.
9180                  */
9181                 if (!dc_add_plane_to_context(
9182                                 dc,
9183                                 dm_new_crtc_state->stream,
9184                                 dc_new_plane_state,
9185                                 dm_state->context)) {
9186
9187                         dc_plane_state_release(dc_new_plane_state);
9188                         return -EINVAL;
9189                 }
9190
9191                 dm_new_plane_state->dc_state = dc_new_plane_state;
9192
9193                 dm_new_crtc_state->mpo_requested |= (plane->type == DRM_PLANE_TYPE_OVERLAY);
9194
9195                 /* Tell DC to do a full surface update every time there
9196                  * is a plane change. Inefficient, but works for now.
9197                  */
9198                 dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
9199
9200                 *lock_and_validation_needed = true;
9201         }
9202
9203
9204         return ret;
9205 }
9206
9207 static void dm_get_oriented_plane_size(struct drm_plane_state *plane_state,
9208                                        int *src_w, int *src_h)
9209 {
9210         switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
9211         case DRM_MODE_ROTATE_90:
9212         case DRM_MODE_ROTATE_270:
9213                 *src_w = plane_state->src_h >> 16;
9214                 *src_h = plane_state->src_w >> 16;
9215                 break;
9216         case DRM_MODE_ROTATE_0:
9217         case DRM_MODE_ROTATE_180:
9218         default:
9219                 *src_w = plane_state->src_w >> 16;
9220                 *src_h = plane_state->src_h >> 16;
9221                 break;
9222         }
9223 }
9224
9225 static int dm_check_crtc_cursor(struct drm_atomic_state *state,
9226                                 struct drm_crtc *crtc,
9227                                 struct drm_crtc_state *new_crtc_state)
9228 {
9229         struct drm_plane *cursor = crtc->cursor, *underlying;
9230         struct drm_plane_state *new_cursor_state, *new_underlying_state;
9231         int i;
9232         int cursor_scale_w, cursor_scale_h, underlying_scale_w, underlying_scale_h;
9233         int cursor_src_w, cursor_src_h;
9234         int underlying_src_w, underlying_src_h;
9235
9236         /* On DCE and DCN there is no dedicated hardware cursor plane. We get a
9237          * cursor per pipe but it's going to inherit the scaling and
9238          * positioning from the underlying pipe. Check the cursor plane's
9239          * blending properties match the underlying planes'. */
9240
9241         new_cursor_state = drm_atomic_get_new_plane_state(state, cursor);
9242         if (!new_cursor_state || !new_cursor_state->fb) {
9243                 return 0;
9244         }
9245
9246         dm_get_oriented_plane_size(new_cursor_state, &cursor_src_w, &cursor_src_h);
9247         cursor_scale_w = new_cursor_state->crtc_w * 1000 / cursor_src_w;
9248         cursor_scale_h = new_cursor_state->crtc_h * 1000 / cursor_src_h;
9249
9250         for_each_new_plane_in_state_reverse(state, underlying, new_underlying_state, i) {
9251                 /* Narrow down to non-cursor planes on the same CRTC as the cursor */
9252                 if (new_underlying_state->crtc != crtc || underlying == crtc->cursor)
9253                         continue;
9254
9255                 /* Ignore disabled planes */
9256                 if (!new_underlying_state->fb)
9257                         continue;
9258
9259                 dm_get_oriented_plane_size(new_underlying_state,
9260                                            &underlying_src_w, &underlying_src_h);
9261                 underlying_scale_w = new_underlying_state->crtc_w * 1000 / underlying_src_w;
9262                 underlying_scale_h = new_underlying_state->crtc_h * 1000 / underlying_src_h;
9263
9264                 if (cursor_scale_w != underlying_scale_w ||
9265                     cursor_scale_h != underlying_scale_h) {
9266                         drm_dbg_atomic(crtc->dev,
9267                                        "Cursor [PLANE:%d:%s] scaling doesn't match underlying [PLANE:%d:%s]\n",
9268                                        cursor->base.id, cursor->name, underlying->base.id, underlying->name);
9269                         return -EINVAL;
9270                 }
9271
9272                 /* If this plane covers the whole CRTC, no need to check planes underneath */
9273                 if (new_underlying_state->crtc_x <= 0 &&
9274                     new_underlying_state->crtc_y <= 0 &&
9275                     new_underlying_state->crtc_x + new_underlying_state->crtc_w >= new_crtc_state->mode.hdisplay &&
9276                     new_underlying_state->crtc_y + new_underlying_state->crtc_h >= new_crtc_state->mode.vdisplay)
9277                         break;
9278         }
9279
9280         return 0;
9281 }
9282
9283 #if defined(CONFIG_DRM_AMD_DC_DCN)
9284 static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc)
9285 {
9286         struct drm_connector *connector;
9287         struct drm_connector_state *conn_state, *old_conn_state;
9288         struct amdgpu_dm_connector *aconnector = NULL;
9289         int i;
9290         for_each_oldnew_connector_in_state(state, connector, old_conn_state, conn_state, i) {
9291                 if (!conn_state->crtc)
9292                         conn_state = old_conn_state;
9293
9294                 if (conn_state->crtc != crtc)
9295                         continue;
9296
9297                 aconnector = to_amdgpu_dm_connector(connector);
9298                 if (!aconnector->port || !aconnector->mst_port)
9299                         aconnector = NULL;
9300                 else
9301                         break;
9302         }
9303
9304         if (!aconnector)
9305                 return 0;
9306
9307         return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_port->mst_mgr);
9308 }
9309 #endif
9310
9311 /**
9312  * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.
9313  *
9314  * @dev: The DRM device
9315  * @state: The atomic state to commit
9316  *
9317  * Validate that the given atomic state is programmable by DC into hardware.
9318  * This involves constructing a &struct dc_state reflecting the new hardware
9319  * state we wish to commit, then querying DC to see if it is programmable. It's
9320  * important not to modify the existing DC state. Otherwise, atomic_check
9321  * may unexpectedly commit hardware changes.
9322  *
9323  * When validating the DC state, it's important that the right locks are
9324  * acquired. For full updates case which removes/adds/updates streams on one
9325  * CRTC while flipping on another CRTC, acquiring global lock will guarantee
9326  * that any such full update commit will wait for completion of any outstanding
9327  * flip using DRMs synchronization events.
9328  *
9329  * Note that DM adds the affected connectors for all CRTCs in state, when that
9330  * might not seem necessary. This is because DC stream creation requires the
9331  * DC sink, which is tied to the DRM connector state. Cleaning this up should
9332  * be possible but non-trivial - a possible TODO item.
9333  *
9334  * Return: -Error code if validation failed.
9335  */
9336 static int amdgpu_dm_atomic_check(struct drm_device *dev,
9337                                   struct drm_atomic_state *state)
9338 {
9339         struct amdgpu_device *adev = drm_to_adev(dev);
9340         struct dm_atomic_state *dm_state = NULL;
9341         struct dc *dc = adev->dm.dc;
9342         struct drm_connector *connector;
9343         struct drm_connector_state *old_con_state, *new_con_state;
9344         struct drm_crtc *crtc;
9345         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
9346         struct drm_plane *plane;
9347         struct drm_plane_state *old_plane_state, *new_plane_state;
9348         enum dc_status status;
9349         int ret, i;
9350         bool lock_and_validation_needed = false;
9351         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
9352 #if defined(CONFIG_DRM_AMD_DC_DCN)
9353         struct dsc_mst_fairness_vars vars[MAX_PIPES];
9354 #endif
9355
9356         trace_amdgpu_dm_atomic_check_begin(state);
9357
9358         ret = drm_atomic_helper_check_modeset(dev, state);
9359         if (ret) {
9360                 DRM_DEBUG_DRIVER("drm_atomic_helper_check_modeset() failed\n");
9361                 goto fail;
9362         }
9363
9364         /* Check connector changes */
9365         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
9366                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
9367                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
9368
9369                 /* Skip connectors that are disabled or part of modeset already. */
9370                 if (!new_con_state->crtc)
9371                         continue;
9372
9373                 new_crtc_state = drm_atomic_get_crtc_state(state, new_con_state->crtc);
9374                 if (IS_ERR(new_crtc_state)) {
9375                         DRM_DEBUG_DRIVER("drm_atomic_get_crtc_state() failed\n");
9376                         ret = PTR_ERR(new_crtc_state);
9377                         goto fail;
9378                 }
9379
9380                 if (dm_old_con_state->abm_level !=
9381                     dm_new_con_state->abm_level)
9382                         new_crtc_state->connectors_changed = true;
9383         }
9384
9385 #if defined(CONFIG_DRM_AMD_DC_DCN)
9386         if (dc_resource_is_dsc_encoding_supported(dc)) {
9387                 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
9388                         if (drm_atomic_crtc_needs_modeset(new_crtc_state)) {
9389                                 ret = add_affected_mst_dsc_crtcs(state, crtc);
9390                                 if (ret) {
9391                                         DRM_DEBUG_DRIVER("add_affected_mst_dsc_crtcs() failed\n");
9392                                         goto fail;
9393                                 }
9394                         }
9395                 }
9396                 if (!pre_validate_dsc(state, &dm_state, vars)) {
9397                         ret = -EINVAL;
9398                         goto fail;
9399                 }
9400         }
9401 #endif
9402         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
9403                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
9404
9405                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
9406                     !new_crtc_state->color_mgmt_changed &&
9407                     old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled &&
9408                         dm_old_crtc_state->dsc_force_changed == false)
9409                         continue;
9410
9411                 ret = amdgpu_dm_verify_lut_sizes(new_crtc_state);
9412                 if (ret) {
9413                         DRM_DEBUG_DRIVER("amdgpu_dm_verify_lut_sizes() failed\n");
9414                         goto fail;
9415                 }
9416
9417                 if (!new_crtc_state->enable)
9418                         continue;
9419
9420                 ret = drm_atomic_add_affected_connectors(state, crtc);
9421                 if (ret) {
9422                         DRM_DEBUG_DRIVER("drm_atomic_add_affected_connectors() failed\n");
9423                         goto fail;
9424                 }
9425
9426                 ret = drm_atomic_add_affected_planes(state, crtc);
9427                 if (ret) {
9428                         DRM_DEBUG_DRIVER("drm_atomic_add_affected_planes() failed\n");
9429                         goto fail;
9430                 }
9431
9432                 if (dm_old_crtc_state->dsc_force_changed)
9433                         new_crtc_state->mode_changed = true;
9434         }
9435
9436         /*
9437          * Add all primary and overlay planes on the CRTC to the state
9438          * whenever a plane is enabled to maintain correct z-ordering
9439          * and to enable fast surface updates.
9440          */
9441         drm_for_each_crtc(crtc, dev) {
9442                 bool modified = false;
9443
9444                 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
9445                         if (plane->type == DRM_PLANE_TYPE_CURSOR)
9446                                 continue;
9447
9448                         if (new_plane_state->crtc == crtc ||
9449                             old_plane_state->crtc == crtc) {
9450                                 modified = true;
9451                                 break;
9452                         }
9453                 }
9454
9455                 if (!modified)
9456                         continue;
9457
9458                 drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask) {
9459                         if (plane->type == DRM_PLANE_TYPE_CURSOR)
9460                                 continue;
9461
9462                         new_plane_state =
9463                                 drm_atomic_get_plane_state(state, plane);
9464
9465                         if (IS_ERR(new_plane_state)) {
9466                                 ret = PTR_ERR(new_plane_state);
9467                                 DRM_DEBUG_DRIVER("new_plane_state is BAD\n");
9468                                 goto fail;
9469                         }
9470                 }
9471         }
9472
9473         /*
9474          * DC consults the zpos (layer_index in DC terminology) to determine the
9475          * hw plane on which to enable the hw cursor (see
9476          * `dcn10_can_pipe_disable_cursor`). By now, all modified planes are in
9477          * atomic state, so call drm helper to normalize zpos.
9478          */
9479         drm_atomic_normalize_zpos(dev, state);
9480
9481         /* Remove exiting planes if they are modified */
9482         for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
9483                 ret = dm_update_plane_state(dc, state, plane,
9484                                             old_plane_state,
9485                                             new_plane_state,
9486                                             false,
9487                                             &lock_and_validation_needed);
9488                 if (ret) {
9489                         DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n");
9490                         goto fail;
9491                 }
9492         }
9493
9494         /* Disable all crtcs which require disable */
9495         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
9496                 ret = dm_update_crtc_state(&adev->dm, state, crtc,
9497                                            old_crtc_state,
9498                                            new_crtc_state,
9499                                            false,
9500                                            &lock_and_validation_needed);
9501                 if (ret) {
9502                         DRM_DEBUG_DRIVER("DISABLE: dm_update_crtc_state() failed\n");
9503                         goto fail;
9504                 }
9505         }
9506
9507         /* Enable all crtcs which require enable */
9508         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
9509                 ret = dm_update_crtc_state(&adev->dm, state, crtc,
9510                                            old_crtc_state,
9511                                            new_crtc_state,
9512                                            true,
9513                                            &lock_and_validation_needed);
9514                 if (ret) {
9515                         DRM_DEBUG_DRIVER("ENABLE: dm_update_crtc_state() failed\n");
9516                         goto fail;
9517                 }
9518         }
9519
9520         /* Add new/modified planes */
9521         for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
9522                 ret = dm_update_plane_state(dc, state, plane,
9523                                             old_plane_state,
9524                                             new_plane_state,
9525                                             true,
9526                                             &lock_and_validation_needed);
9527                 if (ret) {
9528                         DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n");
9529                         goto fail;
9530                 }
9531         }
9532
9533         /* Run this here since we want to validate the streams we created */
9534         ret = drm_atomic_helper_check_planes(dev, state);
9535         if (ret) {
9536                 DRM_DEBUG_DRIVER("drm_atomic_helper_check_planes() failed\n");
9537                 goto fail;
9538         }
9539
9540         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
9541                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
9542                 if (dm_new_crtc_state->mpo_requested)
9543                         DRM_DEBUG_DRIVER("MPO enablement requested on crtc:[%p]\n", crtc);
9544         }
9545
9546         /* Check cursor planes scaling */
9547         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
9548                 ret = dm_check_crtc_cursor(state, crtc, new_crtc_state);
9549                 if (ret) {
9550                         DRM_DEBUG_DRIVER("dm_check_crtc_cursor() failed\n");
9551                         goto fail;
9552                 }
9553         }
9554
9555         if (state->legacy_cursor_update) {
9556                 /*
9557                  * This is a fast cursor update coming from the plane update
9558                  * helper, check if it can be done asynchronously for better
9559                  * performance.
9560                  */
9561                 state->async_update =
9562                         !drm_atomic_helper_async_check(dev, state);
9563
9564                 /*
9565                  * Skip the remaining global validation if this is an async
9566                  * update. Cursor updates can be done without affecting
9567                  * state or bandwidth calcs and this avoids the performance
9568                  * penalty of locking the private state object and
9569                  * allocating a new dc_state.
9570                  */
9571                 if (state->async_update)
9572                         return 0;
9573         }
9574
9575         /* Check scaling and underscan changes*/
9576         /* TODO Removed scaling changes validation due to inability to commit
9577          * new stream into context w\o causing full reset. Need to
9578          * decide how to handle.
9579          */
9580         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
9581                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
9582                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
9583                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
9584
9585                 /* Skip any modesets/resets */
9586                 if (!acrtc || drm_atomic_crtc_needs_modeset(
9587                                 drm_atomic_get_new_crtc_state(state, &acrtc->base)))
9588                         continue;
9589
9590                 /* Skip any thing not scale or underscan changes */
9591                 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
9592                         continue;
9593
9594                 lock_and_validation_needed = true;
9595         }
9596
9597         /**
9598          * Streams and planes are reset when there are changes that affect
9599          * bandwidth. Anything that affects bandwidth needs to go through
9600          * DC global validation to ensure that the configuration can be applied
9601          * to hardware.
9602          *
9603          * We have to currently stall out here in atomic_check for outstanding
9604          * commits to finish in this case because our IRQ handlers reference
9605          * DRM state directly - we can end up disabling interrupts too early
9606          * if we don't.
9607          *
9608          * TODO: Remove this stall and drop DM state private objects.
9609          */
9610         if (lock_and_validation_needed) {
9611                 ret = dm_atomic_get_state(state, &dm_state);
9612                 if (ret) {
9613                         DRM_DEBUG_DRIVER("dm_atomic_get_state() failed\n");
9614                         goto fail;
9615                 }
9616
9617                 ret = do_aquire_global_lock(dev, state);
9618                 if (ret) {
9619                         DRM_DEBUG_DRIVER("do_aquire_global_lock() failed\n");
9620                         goto fail;
9621                 }
9622
9623 #if defined(CONFIG_DRM_AMD_DC_DCN)
9624                 if (!compute_mst_dsc_configs_for_state(state, dm_state->context, vars)) {
9625                         DRM_DEBUG_DRIVER("compute_mst_dsc_configs_for_state() failed\n");
9626                         ret = -EINVAL;
9627                         goto fail;
9628                 }
9629
9630                 ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context, vars);
9631                 if (ret) {
9632                         DRM_DEBUG_DRIVER("dm_update_mst_vcpi_slots_for_dsc() failed\n");
9633                         goto fail;
9634                 }
9635 #endif
9636
9637                 /*
9638                  * Perform validation of MST topology in the state:
9639                  * We need to perform MST atomic check before calling
9640                  * dc_validate_global_state(), or there is a chance
9641                  * to get stuck in an infinite loop and hang eventually.
9642                  */
9643                 ret = drm_dp_mst_atomic_check(state);
9644                 if (ret) {
9645                         DRM_DEBUG_DRIVER("drm_dp_mst_atomic_check() failed\n");
9646                         goto fail;
9647                 }
9648                 status = dc_validate_global_state(dc, dm_state->context, true);
9649                 if (status != DC_OK) {
9650                         DRM_DEBUG_DRIVER("DC global validation failure: %s (%d)",
9651                                        dc_status_to_str(status), status);
9652                         ret = -EINVAL;
9653                         goto fail;
9654                 }
9655         } else {
9656                 /*
9657                  * The commit is a fast update. Fast updates shouldn't change
9658                  * the DC context, affect global validation, and can have their
9659                  * commit work done in parallel with other commits not touching
9660                  * the same resource. If we have a new DC context as part of
9661                  * the DM atomic state from validation we need to free it and
9662                  * retain the existing one instead.
9663                  *
9664                  * Furthermore, since the DM atomic state only contains the DC
9665                  * context and can safely be annulled, we can free the state
9666                  * and clear the associated private object now to free
9667                  * some memory and avoid a possible use-after-free later.
9668                  */
9669
9670                 for (i = 0; i < state->num_private_objs; i++) {
9671                         struct drm_private_obj *obj = state->private_objs[i].ptr;
9672
9673                         if (obj->funcs == adev->dm.atomic_obj.funcs) {
9674                                 int j = state->num_private_objs-1;
9675
9676                                 dm_atomic_destroy_state(obj,
9677                                                 state->private_objs[i].state);
9678
9679                                 /* If i is not at the end of the array then the
9680                                  * last element needs to be moved to where i was
9681                                  * before the array can safely be truncated.
9682                                  */
9683                                 if (i != j)
9684                                         state->private_objs[i] =
9685                                                 state->private_objs[j];
9686
9687                                 state->private_objs[j].ptr = NULL;
9688                                 state->private_objs[j].state = NULL;
9689                                 state->private_objs[j].old_state = NULL;
9690                                 state->private_objs[j].new_state = NULL;
9691
9692                                 state->num_private_objs = j;
9693                                 break;
9694                         }
9695                 }
9696         }
9697
9698         /* Store the overall update type for use later in atomic check. */
9699         for_each_new_crtc_in_state (state, crtc, new_crtc_state, i) {
9700                 struct dm_crtc_state *dm_new_crtc_state =
9701                         to_dm_crtc_state(new_crtc_state);
9702
9703                 dm_new_crtc_state->update_type = lock_and_validation_needed ?
9704                                                          UPDATE_TYPE_FULL :
9705                                                          UPDATE_TYPE_FAST;
9706         }
9707
9708         /* Must be success */
9709         WARN_ON(ret);
9710
9711         trace_amdgpu_dm_atomic_check_finish(state, ret);
9712
9713         return ret;
9714
9715 fail:
9716         if (ret == -EDEADLK)
9717                 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
9718         else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
9719                 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
9720         else
9721                 DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret);
9722
9723         trace_amdgpu_dm_atomic_check_finish(state, ret);
9724
9725         return ret;
9726 }
9727
9728 static bool is_dp_capable_without_timing_msa(struct dc *dc,
9729                                              struct amdgpu_dm_connector *amdgpu_dm_connector)
9730 {
9731         uint8_t dpcd_data;
9732         bool capable = false;
9733
9734         if (amdgpu_dm_connector->dc_link &&
9735                 dm_helpers_dp_read_dpcd(
9736                                 NULL,
9737                                 amdgpu_dm_connector->dc_link,
9738                                 DP_DOWN_STREAM_PORT_COUNT,
9739                                 &dpcd_data,
9740                                 sizeof(dpcd_data))) {
9741                 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
9742         }
9743
9744         return capable;
9745 }
9746
9747 static bool dm_edid_parser_send_cea(struct amdgpu_display_manager *dm,
9748                 unsigned int offset,
9749                 unsigned int total_length,
9750                 uint8_t *data,
9751                 unsigned int length,
9752                 struct amdgpu_hdmi_vsdb_info *vsdb)
9753 {
9754         bool res;
9755         union dmub_rb_cmd cmd;
9756         struct dmub_cmd_send_edid_cea *input;
9757         struct dmub_cmd_edid_cea_output *output;
9758
9759         if (length > DMUB_EDID_CEA_DATA_CHUNK_BYTES)
9760                 return false;
9761
9762         memset(&cmd, 0, sizeof(cmd));
9763
9764         input = &cmd.edid_cea.data.input;
9765
9766         cmd.edid_cea.header.type = DMUB_CMD__EDID_CEA;
9767         cmd.edid_cea.header.sub_type = 0;
9768         cmd.edid_cea.header.payload_bytes =
9769                 sizeof(cmd.edid_cea) - sizeof(cmd.edid_cea.header);
9770         input->offset = offset;
9771         input->length = length;
9772         input->cea_total_length = total_length;
9773         memcpy(input->payload, data, length);
9774
9775         res = dc_dmub_srv_cmd_with_reply_data(dm->dc->ctx->dmub_srv, &cmd);
9776         if (!res) {
9777                 DRM_ERROR("EDID CEA parser failed\n");
9778                 return false;
9779         }
9780
9781         output = &cmd.edid_cea.data.output;
9782
9783         if (output->type == DMUB_CMD__EDID_CEA_ACK) {
9784                 if (!output->ack.success) {
9785                         DRM_ERROR("EDID CEA ack failed at offset %d\n",
9786                                         output->ack.offset);
9787                 }
9788         } else if (output->type == DMUB_CMD__EDID_CEA_AMD_VSDB) {
9789                 if (!output->amd_vsdb.vsdb_found)
9790                         return false;
9791
9792                 vsdb->freesync_supported = output->amd_vsdb.freesync_supported;
9793                 vsdb->amd_vsdb_version = output->amd_vsdb.amd_vsdb_version;
9794                 vsdb->min_refresh_rate_hz = output->amd_vsdb.min_frame_rate;
9795                 vsdb->max_refresh_rate_hz = output->amd_vsdb.max_frame_rate;
9796         } else {
9797                 DRM_WARN("Unknown EDID CEA parser results\n");
9798                 return false;
9799         }
9800
9801         return true;
9802 }
9803
9804 static bool parse_edid_cea_dmcu(struct amdgpu_display_manager *dm,
9805                 uint8_t *edid_ext, int len,
9806                 struct amdgpu_hdmi_vsdb_info *vsdb_info)
9807 {
9808         int i;
9809
9810         /* send extension block to DMCU for parsing */
9811         for (i = 0; i < len; i += 8) {
9812                 bool res;
9813                 int offset;
9814
9815                 /* send 8 bytes a time */
9816                 if (!dc_edid_parser_send_cea(dm->dc, i, len, &edid_ext[i], 8))
9817                         return false;
9818
9819                 if (i+8 == len) {
9820                         /* EDID block sent completed, expect result */
9821                         int version, min_rate, max_rate;
9822
9823                         res = dc_edid_parser_recv_amd_vsdb(dm->dc, &version, &min_rate, &max_rate);
9824                         if (res) {
9825                                 /* amd vsdb found */
9826                                 vsdb_info->freesync_supported = 1;
9827                                 vsdb_info->amd_vsdb_version = version;
9828                                 vsdb_info->min_refresh_rate_hz = min_rate;
9829                                 vsdb_info->max_refresh_rate_hz = max_rate;
9830                                 return true;
9831                         }
9832                         /* not amd vsdb */
9833                         return false;
9834                 }
9835
9836                 /* check for ack*/
9837                 res = dc_edid_parser_recv_cea_ack(dm->dc, &offset);
9838                 if (!res)
9839                         return false;
9840         }
9841
9842         return false;
9843 }
9844
9845 static bool parse_edid_cea_dmub(struct amdgpu_display_manager *dm,
9846                 uint8_t *edid_ext, int len,
9847                 struct amdgpu_hdmi_vsdb_info *vsdb_info)
9848 {
9849         int i;
9850
9851         /* send extension block to DMCU for parsing */
9852         for (i = 0; i < len; i += 8) {
9853                 /* send 8 bytes a time */
9854                 if (!dm_edid_parser_send_cea(dm, i, len, &edid_ext[i], 8, vsdb_info))
9855                         return false;
9856         }
9857
9858         return vsdb_info->freesync_supported;
9859 }
9860
9861 static bool parse_edid_cea(struct amdgpu_dm_connector *aconnector,
9862                 uint8_t *edid_ext, int len,
9863                 struct amdgpu_hdmi_vsdb_info *vsdb_info)
9864 {
9865         struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev);
9866
9867         if (adev->dm.dmub_srv)
9868                 return parse_edid_cea_dmub(&adev->dm, edid_ext, len, vsdb_info);
9869         else
9870                 return parse_edid_cea_dmcu(&adev->dm, edid_ext, len, vsdb_info);
9871 }
9872
9873 static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector,
9874                 struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info)
9875 {
9876         uint8_t *edid_ext = NULL;
9877         int i;
9878         bool valid_vsdb_found = false;
9879
9880         /*----- drm_find_cea_extension() -----*/
9881         /* No EDID or EDID extensions */
9882         if (edid == NULL || edid->extensions == 0)
9883                 return -ENODEV;
9884
9885         /* Find CEA extension */
9886         for (i = 0; i < edid->extensions; i++) {
9887                 edid_ext = (uint8_t *)edid + EDID_LENGTH * (i + 1);
9888                 if (edid_ext[0] == CEA_EXT)
9889                         break;
9890         }
9891
9892         if (i == edid->extensions)
9893                 return -ENODEV;
9894
9895         /*----- cea_db_offsets() -----*/
9896         if (edid_ext[0] != CEA_EXT)
9897                 return -ENODEV;
9898
9899         valid_vsdb_found = parse_edid_cea(aconnector, edid_ext, EDID_LENGTH, vsdb_info);
9900
9901         return valid_vsdb_found ? i : -ENODEV;
9902 }
9903
9904 /**
9905  * amdgpu_dm_update_freesync_caps - Update Freesync capabilities
9906  *
9907  * @connector: Connector to query.
9908  * @edid: EDID from monitor
9909  *
9910  * Amdgpu supports Freesync in DP and HDMI displays, and it is required to keep
9911  * track of some of the display information in the internal data struct used by
9912  * amdgpu_dm. This function checks which type of connector we need to set the
9913  * FreeSync parameters.
9914  */
9915 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
9916                                     struct edid *edid)
9917 {
9918         int i = 0;
9919         struct detailed_timing *timing;
9920         struct detailed_non_pixel *data;
9921         struct detailed_data_monitor_range *range;
9922         struct amdgpu_dm_connector *amdgpu_dm_connector =
9923                         to_amdgpu_dm_connector(connector);
9924         struct dm_connector_state *dm_con_state = NULL;
9925         struct dc_sink *sink;
9926
9927         struct drm_device *dev = connector->dev;
9928         struct amdgpu_device *adev = drm_to_adev(dev);
9929         struct amdgpu_hdmi_vsdb_info vsdb_info = {0};
9930         bool freesync_capable = false;
9931
9932         if (!connector->state) {
9933                 DRM_ERROR("%s - Connector has no state", __func__);
9934                 goto update;
9935         }
9936
9937         sink = amdgpu_dm_connector->dc_sink ?
9938                 amdgpu_dm_connector->dc_sink :
9939                 amdgpu_dm_connector->dc_em_sink;
9940
9941         if (!edid || !sink) {
9942                 dm_con_state = to_dm_connector_state(connector->state);
9943
9944                 amdgpu_dm_connector->min_vfreq = 0;
9945                 amdgpu_dm_connector->max_vfreq = 0;
9946                 amdgpu_dm_connector->pixel_clock_mhz = 0;
9947                 connector->display_info.monitor_range.min_vfreq = 0;
9948                 connector->display_info.monitor_range.max_vfreq = 0;
9949                 freesync_capable = false;
9950
9951                 goto update;
9952         }
9953
9954         dm_con_state = to_dm_connector_state(connector->state);
9955
9956         if (!adev->dm.freesync_module)
9957                 goto update;
9958
9959         if (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
9960                 || sink->sink_signal == SIGNAL_TYPE_EDP) {
9961                 bool edid_check_required = false;
9962
9963                 if (edid) {
9964                         edid_check_required = is_dp_capable_without_timing_msa(
9965                                                 adev->dm.dc,
9966                                                 amdgpu_dm_connector);
9967                 }
9968
9969                 if (edid_check_required == true && (edid->version > 1 ||
9970                    (edid->version == 1 && edid->revision > 1))) {
9971                         for (i = 0; i < 4; i++) {
9972
9973                                 timing  = &edid->detailed_timings[i];
9974                                 data    = &timing->data.other_data;
9975                                 range   = &data->data.range;
9976                                 /*
9977                                  * Check if monitor has continuous frequency mode
9978                                  */
9979                                 if (data->type != EDID_DETAIL_MONITOR_RANGE)
9980                                         continue;
9981                                 /*
9982                                  * Check for flag range limits only. If flag == 1 then
9983                                  * no additional timing information provided.
9984                                  * Default GTF, GTF Secondary curve and CVT are not
9985                                  * supported
9986                                  */
9987                                 if (range->flags != 1)
9988                                         continue;
9989
9990                                 amdgpu_dm_connector->min_vfreq = range->min_vfreq;
9991                                 amdgpu_dm_connector->max_vfreq = range->max_vfreq;
9992                                 amdgpu_dm_connector->pixel_clock_mhz =
9993                                         range->pixel_clock_mhz * 10;
9994
9995                                 connector->display_info.monitor_range.min_vfreq = range->min_vfreq;
9996                                 connector->display_info.monitor_range.max_vfreq = range->max_vfreq;
9997
9998                                 break;
9999                         }
10000
10001                         if (amdgpu_dm_connector->max_vfreq -
10002                             amdgpu_dm_connector->min_vfreq > 10) {
10003
10004                                 freesync_capable = true;
10005                         }
10006                 }
10007         } else if (edid && sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) {
10008                 i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
10009                 if (i >= 0 && vsdb_info.freesync_supported) {
10010                         timing  = &edid->detailed_timings[i];
10011                         data    = &timing->data.other_data;
10012
10013                         amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
10014                         amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
10015                         if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
10016                                 freesync_capable = true;
10017
10018                         connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz;
10019                         connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz;
10020                 }
10021         }
10022
10023 update:
10024         if (dm_con_state)
10025                 dm_con_state->freesync_capable = freesync_capable;
10026
10027         if (connector->vrr_capable_property)
10028                 drm_connector_set_vrr_capable_property(connector,
10029                                                        freesync_capable);
10030 }
10031
10032 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev)
10033 {
10034         struct amdgpu_device *adev = drm_to_adev(dev);
10035         struct dc *dc = adev->dm.dc;
10036         int i;
10037
10038         mutex_lock(&adev->dm.dc_lock);
10039         if (dc->current_state) {
10040                 for (i = 0; i < dc->current_state->stream_count; ++i)
10041                         dc->current_state->streams[i]
10042                                 ->triggered_crtc_reset.enabled =
10043                                 adev->dm.force_timing_sync;
10044
10045                 dm_enable_per_frame_crtc_master_sync(dc->current_state);
10046                 dc_trigger_sync(dc, dc->current_state);
10047         }
10048         mutex_unlock(&adev->dm.dc_lock);
10049 }
10050
10051 void dm_write_reg_func(const struct dc_context *ctx, uint32_t address,
10052                        uint32_t value, const char *func_name)
10053 {
10054 #ifdef DM_CHECK_ADDR_0
10055         if (address == 0) {
10056                 DC_ERR("invalid register write. address = 0");
10057                 return;
10058         }
10059 #endif
10060         cgs_write_register(ctx->cgs_device, address, value);
10061         trace_amdgpu_dc_wreg(&ctx->perf_trace->write_count, address, value);
10062 }
10063
10064 uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address,
10065                           const char *func_name)
10066 {
10067         uint32_t value;
10068 #ifdef DM_CHECK_ADDR_0
10069         if (address == 0) {
10070                 DC_ERR("invalid register read; address = 0\n");
10071                 return 0;
10072         }
10073 #endif
10074
10075         if (ctx->dmub_srv &&
10076             ctx->dmub_srv->reg_helper_offload.gather_in_progress &&
10077             !ctx->dmub_srv->reg_helper_offload.should_burst_write) {
10078                 ASSERT(false);
10079                 return 0;
10080         }
10081
10082         value = cgs_read_register(ctx->cgs_device, address);
10083
10084         trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address, value);
10085
10086         return value;
10087 }
10088
10089 static int amdgpu_dm_set_dmub_async_sync_status(bool is_cmd_aux,
10090                                                 struct dc_context *ctx,
10091                                                 uint8_t status_type,
10092                                                 uint32_t *operation_result)
10093 {
10094         struct amdgpu_device *adev = ctx->driver_context;
10095         int return_status = -1;
10096         struct dmub_notification *p_notify = adev->dm.dmub_notify;
10097
10098         if (is_cmd_aux) {
10099                 if (status_type == DMUB_ASYNC_TO_SYNC_ACCESS_SUCCESS) {
10100                         return_status = p_notify->aux_reply.length;
10101                         *operation_result = p_notify->result;
10102                 } else if (status_type == DMUB_ASYNC_TO_SYNC_ACCESS_TIMEOUT) {
10103                         *operation_result = AUX_RET_ERROR_TIMEOUT;
10104                 } else if (status_type == DMUB_ASYNC_TO_SYNC_ACCESS_FAIL) {
10105                         *operation_result = AUX_RET_ERROR_ENGINE_ACQUIRE;
10106                 } else {
10107                         *operation_result = AUX_RET_ERROR_UNKNOWN;
10108                 }
10109         } else {
10110                 if (status_type == DMUB_ASYNC_TO_SYNC_ACCESS_SUCCESS) {
10111                         return_status = 0;
10112                         *operation_result = p_notify->sc_status;
10113                 } else {
10114                         *operation_result = SET_CONFIG_UNKNOWN_ERROR;
10115                 }
10116         }
10117
10118         return return_status;
10119 }
10120
10121 int amdgpu_dm_process_dmub_aux_transfer_sync(bool is_cmd_aux, struct dc_context *ctx,
10122         unsigned int link_index, void *cmd_payload, void *operation_result)
10123 {
10124         struct amdgpu_device *adev = ctx->driver_context;
10125         int ret = 0;
10126
10127         if (is_cmd_aux) {
10128                 dc_process_dmub_aux_transfer_async(ctx->dc,
10129                         link_index, (struct aux_payload *)cmd_payload);
10130         } else if (dc_process_dmub_set_config_async(ctx->dc, link_index,
10131                                         (struct set_config_cmd_payload *)cmd_payload,
10132                                         adev->dm.dmub_notify)) {
10133                 return amdgpu_dm_set_dmub_async_sync_status(is_cmd_aux,
10134                                         ctx, DMUB_ASYNC_TO_SYNC_ACCESS_SUCCESS,
10135                                         (uint32_t *)operation_result);
10136         }
10137
10138         ret = wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZ);
10139         if (ret == 0) {
10140                 DRM_ERROR("wait_for_completion_timeout timeout!");
10141                 return amdgpu_dm_set_dmub_async_sync_status(is_cmd_aux,
10142                                 ctx, DMUB_ASYNC_TO_SYNC_ACCESS_TIMEOUT,
10143                                 (uint32_t *)operation_result);
10144         }
10145
10146         if (is_cmd_aux) {
10147                 if (adev->dm.dmub_notify->result == AUX_RET_SUCCESS) {
10148                         struct aux_payload *payload = (struct aux_payload *)cmd_payload;
10149
10150                         payload->reply[0] = adev->dm.dmub_notify->aux_reply.command;
10151                         if (!payload->write && adev->dm.dmub_notify->aux_reply.length &&
10152                             payload->reply[0] == AUX_TRANSACTION_REPLY_AUX_ACK) {
10153                                 memcpy(payload->data, adev->dm.dmub_notify->aux_reply.data,
10154                                        adev->dm.dmub_notify->aux_reply.length);
10155                         }
10156                 }
10157         }
10158
10159         return amdgpu_dm_set_dmub_async_sync_status(is_cmd_aux,
10160                         ctx, DMUB_ASYNC_TO_SYNC_ACCESS_SUCCESS,
10161                         (uint32_t *)operation_result);
10162 }
10163
10164 /*
10165  * Check whether seamless boot is supported.
10166  *
10167  * So far we only support seamless boot on CHIP_VANGOGH.
10168  * If everything goes well, we may consider expanding
10169  * seamless boot to other ASICs.
10170  */
10171 bool check_seamless_boot_capability(struct amdgpu_device *adev)
10172 {
10173         switch (adev->asic_type) {
10174         case CHIP_VANGOGH:
10175                 if (!adev->mman.keep_stolen_vga_memory)
10176                         return true;
10177                 break;
10178         default:
10179                 break;
10180         }
10181
10182         return false;
10183 }