drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dm_services_types.h"
  27 #include "dc.h"
  28 #include "dc/inc/core_types.h"
  29
  30 #include "vid.h"
  31 #include "amdgpu.h"
  32 #include "amdgpu_display.h"
  33 #include "atom.h"
  34 #include "amdgpu_dm.h"
  35 #include "amdgpu_pm.h"
  36
  37 #include "amd_shared.h"
  38 #include "amdgpu_dm_irq.h"
  39 #include "dm_helpers.h"
  40 #include "dm_services_types.h"
  41 #include "amdgpu_dm_mst_types.h"
  42
  43 #include "ivsrcid/ivsrcid_vislands30.h"
  44
  45 #include <linux/module.h>
  46 #include <linux/moduleparam.h>
  47 #include <linux/version.h>
  48 #include <linux/types.h>
  49
  50 #include <drm/drmP.h>
  51 #include <drm/drm_atomic.h>
  52 #include <drm/drm_atomic_helper.h>
  53 #include <drm/drm_dp_mst_helper.h>
  54 #include <drm/drm_fb_helper.h>
  55 #include <drm/drm_edid.h>
  56
  57 #include "modules/inc/mod_freesync.h"
  58
  59 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
  60 #include "ivsrcid/irqsrcs_dcn_1_0.h"
  61
  62 #include "dcn/dcn_1_0_offset.h"
  63 #include "dcn/dcn_1_0_sh_mask.h"
  64 #include "soc15_hw_ip.h"
  65 #include "vega10_ip_offset.h"
  66
  67 #include "soc15_common.h"
  68 #endif
  69
  70 #include "modules/inc/mod_freesync.h"
  71
  72 #include "i2caux_interface.h"
  73
  74 /* basic init/fini API */
  75 static int amdgpu_dm_init(struct amdgpu_device *adev);
  76 static void amdgpu_dm_fini(struct amdgpu_device *adev);
  77
  78 /* initializes drm_device display related structures, based on the information
  79  * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
  80  * drm_encoder, drm_mode_config
  81  *
  82  * Returns 0 on success
  83  */
  84 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
  85 /* removes and deallocates the drm structures, created by the above function */
  86 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
  87
  88 static void
  89 amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector);
  90
  91 static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
  92                                 struct amdgpu_plane *aplane,
  93                                 unsigned long possible_crtcs);
  94 static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
  95                                struct drm_plane *plane,
  96                                uint32_t link_index);
  97 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
  98                                     struct amdgpu_dm_connector *amdgpu_dm_connector,
  99                                     uint32_t link_index,
 100                                     struct amdgpu_encoder *amdgpu_encoder);
 101 static int amdgpu_dm_encoder_init(struct drm_device *dev,
 102                                   struct amdgpu_encoder *aencoder,
 103                                   uint32_t link_index);
 104
 105 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
 106
 107 static int amdgpu_dm_atomic_commit(struct drm_device *dev,
 108                                    struct drm_atomic_state *state,
 109                                    bool nonblock);
 110
 111 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
 112
 113 static int amdgpu_dm_atomic_check(struct drm_device *dev,
 114                                   struct drm_atomic_state *state);
 115
 116
 117
 118
 119 static const enum drm_plane_type dm_plane_type_default[AMDGPU_MAX_PLANES] = {
 120         DRM_PLANE_TYPE_PRIMARY,
 121         DRM_PLANE_TYPE_PRIMARY,
 122         DRM_PLANE_TYPE_PRIMARY,
 123         DRM_PLANE_TYPE_PRIMARY,
 124         DRM_PLANE_TYPE_PRIMARY,
 125         DRM_PLANE_TYPE_PRIMARY,
 126 };
 127
 128 static const enum drm_plane_type dm_plane_type_carizzo[AMDGPU_MAX_PLANES] = {
 129         DRM_PLANE_TYPE_PRIMARY,
 130         DRM_PLANE_TYPE_PRIMARY,
 131         DRM_PLANE_TYPE_PRIMARY,
 132         DRM_PLANE_TYPE_OVERLAY,/* YUV Capable Underlay */
 133 };
 134
 135 static const enum drm_plane_type dm_plane_type_stoney[AMDGPU_MAX_PLANES] = {
 136         DRM_PLANE_TYPE_PRIMARY,
 137         DRM_PLANE_TYPE_PRIMARY,
 138         DRM_PLANE_TYPE_OVERLAY, /* YUV Capable Underlay */
 139 };
 140
 141 /*
 142  * dm_vblank_get_counter
 143  *
 144  * @brief
 145  * Get counter for number of vertical blanks
 146  *
 147  * @param
 148  * struct amdgpu_device *adev - [in] desired amdgpu device
 149  * int disp_idx - [in] which CRTC to get the counter from
 150  *
 151  * @return
 152  * Counter for vertical blanks
 153  */
 154 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
 155 {
 156         if (crtc >= adev->mode_info.num_crtc)
 157                 return 0;
 158         else {
 159                 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
 160                 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
 161                                 acrtc->base.state);
 162
 163
 164                 if (acrtc_state->stream == NULL) {
 165                         DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
 166                                   crtc);
 167                         return 0;
 168                 }
 169
 170                 return dc_stream_get_vblank_counter(acrtc_state->stream);
 171         }
 172 }
 173
 174 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
 175                                   u32 *vbl, u32 *position)
 176 {
 177         uint32_t v_blank_start, v_blank_end, h_position, v_position;
 178
 179         if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
 180                 return -EINVAL;
 181         else {
 182                 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
 183                 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
 184                                                 acrtc->base.state);
 185
 186                 if (acrtc_state->stream ==  NULL) {
 187                         DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
 188                                   crtc);
 189                         return 0;
 190                 }
 191
 192                 /*
 193                  * TODO rework base driver to use values directly.
 194                  * for now parse it back into reg-format
 195                  */
 196                 dc_stream_get_scanoutpos(acrtc_state->stream,
 197                                          &v_blank_start,
 198                                          &v_blank_end,
 199                                          &h_position,
 200                                          &v_position);
 201
 202                 *position = v_position | (h_position << 16);
 203                 *vbl = v_blank_start | (v_blank_end << 16);
 204         }
 205
 206         return 0;
 207 }
 208
 209 static bool dm_is_idle(void *handle)
 210 {
 211         /* XXX todo */
 212         return true;
 213 }
 214
 215 static int dm_wait_for_idle(void *handle)
 216 {
 217         /* XXX todo */
 218         return 0;
 219 }
 220
 221 static bool dm_check_soft_reset(void *handle)
 222 {
 223         return false;
 224 }
 225
 226 static int dm_soft_reset(void *handle)
 227 {
 228         /* XXX todo */
 229         return 0;
 230 }
 231
 232 static struct amdgpu_crtc *
 233 get_crtc_by_otg_inst(struct amdgpu_device *adev,
 234                      int otg_inst)
 235 {
 236         struct drm_device *dev = adev->ddev;
 237         struct drm_crtc *crtc;
 238         struct amdgpu_crtc *amdgpu_crtc;
 239
 240         /*
 241          * following if is check inherited from both functions where this one is
 242          * used now. Need to be checked why it could happen.
 243          */
 244         if (otg_inst == -1) {
 245                 WARN_ON(1);
 246                 return adev->mode_info.crtcs[0];
 247         }
 248
 249         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 250                 amdgpu_crtc = to_amdgpu_crtc(crtc);
 251
 252                 if (amdgpu_crtc->otg_inst == otg_inst)
 253                         return amdgpu_crtc;
 254         }
 255
 256         return NULL;
 257 }
 258
 259 static void dm_pflip_high_irq(void *interrupt_params)
 260 {
 261         struct amdgpu_crtc *amdgpu_crtc;
 262         struct common_irq_params *irq_params = interrupt_params;
 263         struct amdgpu_device *adev = irq_params->adev;
 264         unsigned long flags;
 265
 266         amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
 267
 268         /* IRQ could occur when in initial stage */
 269         /*TODO work and BO cleanup */
 270         if (amdgpu_crtc == NULL) {
 271                 DRM_DEBUG_DRIVER("CRTC is null, returning.\n");
 272                 return;
 273         }
 274
 275         spin_lock_irqsave(&adev->ddev->event_lock, flags);
 276
 277         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
 278                 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
 279                                                  amdgpu_crtc->pflip_status,
 280                                                  AMDGPU_FLIP_SUBMITTED,
 281                                                  amdgpu_crtc->crtc_id,
 282                                                  amdgpu_crtc);
 283                 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
 284                 return;
 285         }
 286
 287
 288         /* wakeup usersapce */
 289         if (amdgpu_crtc->event) {
 290                 /* Update to correct count/ts if racing with vblank irq */
 291                 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
 292
 293                 drm_crtc_send_vblank_event(&amdgpu_crtc->base, amdgpu_crtc->event);
 294
 295                 /* page flip completed. clean up */
 296                 amdgpu_crtc->event = NULL;
 297
 298         } else
 299                 WARN_ON(1);
 300
 301         amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
 302         spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
 303
 304         DRM_DEBUG_DRIVER("%s - crtc :%d[%p], pflip_stat:AMDGPU_FLIP_NONE\n",
 305                                         __func__, amdgpu_crtc->crtc_id, amdgpu_crtc);
 306
 307         drm_crtc_vblank_put(&amdgpu_crtc->base);
 308 }
 309
 310 static void dm_crtc_high_irq(void *interrupt_params)
 311 {
 312         struct common_irq_params *irq_params = interrupt_params;
 313         struct amdgpu_device *adev = irq_params->adev;
 314         uint8_t crtc_index = 0;
 315         struct amdgpu_crtc *acrtc;
 316
 317         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
 318
 319         if (acrtc)
 320                 crtc_index = acrtc->crtc_id;
 321
 322         drm_handle_vblank(adev->ddev, crtc_index);
 323         amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
 324 }
 325
 326 static int dm_set_clockgating_state(void *handle,
 327                   enum amd_clockgating_state state)
 328 {
 329         return 0;
 330 }
 331
 332 static int dm_set_powergating_state(void *handle,
 333                   enum amd_powergating_state state)
 334 {
 335         return 0;
 336 }
 337
 338 /* Prototypes of private functions */
 339 static int dm_early_init(void* handle);
 340
 341 static void hotplug_notify_work_func(struct work_struct *work)
 342 {
 343         struct amdgpu_display_manager *dm = container_of(work, struct amdgpu_display_manager, mst_hotplug_work);
 344         struct drm_device *dev = dm->ddev;
 345
 346         drm_kms_helper_hotplug_event(dev);
 347 }
 348
 349 #if defined(CONFIG_DRM_AMD_DC_FBC)
 350 /* Allocate memory for FBC compressed data  */
 351 static void amdgpu_dm_fbc_init(struct drm_connector *connector)
 352 {
 353         struct drm_device *dev = connector->dev;
 354         struct amdgpu_device *adev = dev->dev_private;
 355         struct dm_comressor_info *compressor = &adev->dm.compressor;
 356         struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
 357         struct drm_display_mode *mode;
 358         unsigned long max_size = 0;
 359
 360         if (adev->dm.dc->fbc_compressor == NULL)
 361                 return;
 362
 363         if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
 364                 return;
 365
 366         if (compressor->bo_ptr)
 367                 return;
 368
 369
 370         list_for_each_entry(mode, &connector->modes, head) {
 371                 if (max_size < mode->htotal * mode->vtotal)
 372                         max_size = mode->htotal * mode->vtotal;
 373         }
 374
 375         if (max_size) {
 376                 int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,
 377                             AMDGPU_GEM_DOMAIN_VRAM, &compressor->bo_ptr,
 378                             &compressor->gpu_addr, &compressor->cpu_addr);
 379
 380                 if (r)
 381                         DRM_ERROR("DM: Failed to initialize FBC\n");
 382                 else {
 383                         adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
 384                         DRM_INFO("DM: FBC alloc %lu\n", max_size*4);
 385                 }
 386
 387         }
 388
 389 }
 390 #endif
 391
 392
 393 /* Init display KMS
 394  *
 395  * Returns 0 on success
 396  */
 397 static int amdgpu_dm_init(struct amdgpu_device *adev)
 398 {
 399         struct dc_init_data init_data;
 400         adev->dm.ddev = adev->ddev;
 401         adev->dm.adev = adev;
 402
 403         /* Zero all the fields */
 404         memset(&init_data, 0, sizeof(init_data));
 405
 406         if(amdgpu_dm_irq_init(adev)) {
 407                 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
 408                 goto error;
 409         }
 410
 411         init_data.asic_id.chip_family = adev->family;
 412
 413         init_data.asic_id.pci_revision_id = adev->rev_id;
 414         init_data.asic_id.hw_internal_rev = adev->external_rev_id;
 415
 416         init_data.asic_id.vram_width = adev->gmc.vram_width;
 417         /* TODO: initialize init_data.asic_id.vram_type here!!!! */
 418         init_data.asic_id.atombios_base_address =
 419                 adev->mode_info.atom_context->bios;
 420
 421         init_data.driver = adev;
 422
 423         adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
 424
 425         if (!adev->dm.cgs_device) {
 426                 DRM_ERROR("amdgpu: failed to create cgs device.\n");
 427                 goto error;
 428         }
 429
 430         init_data.cgs_device = adev->dm.cgs_device;
 431
 432         adev->dm.dal = NULL;
 433
 434         init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
 435
 436         if (amdgpu_dc_log)
 437                 init_data.log_mask = DC_DEFAULT_LOG_MASK;
 438         else
 439                 init_data.log_mask = DC_MIN_LOG_MASK;
 440
 441         /*
 442          * TODO debug why this doesn't work on Raven
 443          */
 444         if (adev->flags & AMD_IS_APU &&
 445             adev->asic_type >= CHIP_CARRIZO &&
 446             adev->asic_type < CHIP_RAVEN)
 447                 init_data.flags.gpu_vm_support = true;
 448
 449         /* Display Core create. */
 450         adev->dm.dc = dc_create(&init_data);
 451
 452         if (adev->dm.dc) {
 453                 DRM_INFO("Display Core initialized with v%s!\n", DC_VER);
 454         } else {
 455                 DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER);
 456                 goto error;
 457         }
 458
 459         INIT_WORK(&adev->dm.mst_hotplug_work, hotplug_notify_work_func);
 460
 461         adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
 462         if (!adev->dm.freesync_module) {
 463                 DRM_ERROR(
 464                 "amdgpu: failed to initialize freesync_module.\n");
 465         } else
 466                 DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
 467                                 adev->dm.freesync_module);
 468
 469         amdgpu_dm_init_color_mod();
 470
 471         if (amdgpu_dm_initialize_drm_device(adev)) {
 472                 DRM_ERROR(
 473                 "amdgpu: failed to initialize sw for display support.\n");
 474                 goto error;
 475         }
 476
 477         /* Update the actual used number of crtc */
 478         adev->mode_info.num_crtc = adev->dm.display_indexes_num;
 479
 480         /* TODO: Add_display_info? */
 481
 482         /* TODO use dynamic cursor width */
 483         adev->ddev->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
 484         adev->ddev->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
 485
 486         if (drm_vblank_init(adev->ddev, adev->dm.display_indexes_num)) {
 487                 DRM_ERROR(
 488                 "amdgpu: failed to initialize sw for display support.\n");
 489                 goto error;
 490         }
 491
 492         DRM_DEBUG_DRIVER("KMS initialized.\n");
 493
 494         return 0;
 495 error:
 496         amdgpu_dm_fini(adev);
 497
 498         return -1;
 499 }
 500
 501 static void amdgpu_dm_fini(struct amdgpu_device *adev)
 502 {
 503         amdgpu_dm_destroy_drm_device(&adev->dm);
 504         /*
 505          * TODO: pageflip, vlank interrupt
 506          *
 507          * amdgpu_dm_irq_fini(adev);
 508          */
 509
 510         if (adev->dm.cgs_device) {
 511                 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
 512                 adev->dm.cgs_device = NULL;
 513         }
 514         if (adev->dm.freesync_module) {
 515                 mod_freesync_destroy(adev->dm.freesync_module);
 516                 adev->dm.freesync_module = NULL;
 517         }
 518         /* DC Destroy TODO: Replace destroy DAL */
 519         if (adev->dm.dc)
 520                 dc_destroy(&adev->dm.dc);
 521         return;
 522 }
 523
 524 static int dm_sw_init(void *handle)
 525 {
 526         return 0;
 527 }
 528
 529 static int dm_sw_fini(void *handle)
 530 {
 531         return 0;
 532 }
 533
 534 static int detect_mst_link_for_all_connectors(struct drm_device *dev)
 535 {
 536         struct amdgpu_dm_connector *aconnector;
 537         struct drm_connector *connector;
 538         int ret = 0;
 539
 540         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
 541
 542         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 543                 aconnector = to_amdgpu_dm_connector(connector);
 544                 if (aconnector->dc_link->type == dc_connection_mst_branch &&
 545                     aconnector->mst_mgr.aux) {
 546                         DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
 547                                         aconnector, aconnector->base.base.id);
 548
 549                         ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
 550                         if (ret < 0) {
 551                                 DRM_ERROR("DM_MST: Failed to start MST\n");
 552                                 ((struct dc_link *)aconnector->dc_link)->type = dc_connection_single;
 553                                 return ret;
 554                                 }
 555                         }
 556         }
 557
 558         drm_modeset_unlock(&dev->mode_config.connection_mutex);
 559         return ret;
 560 }
 561
 562 static int dm_late_init(void *handle)
 563 {
 564         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 565
 566         return detect_mst_link_for_all_connectors(adev->ddev);
 567 }
 568
 569 static void s3_handle_mst(struct drm_device *dev, bool suspend)
 570 {
 571         struct amdgpu_dm_connector *aconnector;
 572         struct drm_connector *connector;
 573
 574         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
 575
 576         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 577                    aconnector = to_amdgpu_dm_connector(connector);
 578                    if (aconnector->dc_link->type == dc_connection_mst_branch &&
 579                                    !aconnector->mst_port) {
 580
 581                            if (suspend)
 582                                    drm_dp_mst_topology_mgr_suspend(&aconnector->mst_mgr);
 583                            else
 584                                    drm_dp_mst_topology_mgr_resume(&aconnector->mst_mgr);
 585                    }
 586         }
 587
 588         drm_modeset_unlock(&dev->mode_config.connection_mutex);
 589 }
 590
 591 static int dm_hw_init(void *handle)
 592 {
 593         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 594         /* Create DAL display manager */
 595         amdgpu_dm_init(adev);
 596         amdgpu_dm_hpd_init(adev);
 597
 598         return 0;
 599 }
 600
 601 static int dm_hw_fini(void *handle)
 602 {
 603         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 604
 605         amdgpu_dm_hpd_fini(adev);
 606
 607         amdgpu_dm_irq_fini(adev);
 608         amdgpu_dm_fini(adev);
 609         return 0;
 610 }
 611
 612 static int dm_suspend(void *handle)
 613 {
 614         struct amdgpu_device *adev = handle;
 615         struct amdgpu_display_manager *dm = &adev->dm;
 616         int ret = 0;
 617
 618         s3_handle_mst(adev->ddev, true);
 619
 620         amdgpu_dm_irq_suspend(adev);
 621
 622         WARN_ON(adev->dm.cached_state);
 623         adev->dm.cached_state = drm_atomic_helper_suspend(adev->ddev);
 624
 625         dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
 626
 627         return ret;
 628 }
 629
 630 static struct amdgpu_dm_connector *
 631 amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
 632                                              struct drm_crtc *crtc)
 633 {
 634         uint32_t i;
 635         struct drm_connector_state *new_con_state;
 636         struct drm_connector *connector;
 637         struct drm_crtc *crtc_from_state;
 638
 639         for_each_new_connector_in_state(state, connector, new_con_state, i) {
 640                 crtc_from_state = new_con_state->crtc;
 641
 642                 if (crtc_from_state == crtc)
 643                         return to_amdgpu_dm_connector(connector);
 644         }
 645
 646         return NULL;
 647 }
 648
 649 static int dm_resume(void *handle)
 650 {
 651         struct amdgpu_device *adev = handle;
 652         struct amdgpu_display_manager *dm = &adev->dm;
 653         int ret = 0;
 654
 655         /* power on hardware */
 656         dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
 657
 658         ret = amdgpu_dm_display_resume(adev);
 659         return ret;
 660 }
 661
 662 int amdgpu_dm_display_resume(struct amdgpu_device *adev)
 663 {
 664         struct drm_device *ddev = adev->ddev;
 665         struct amdgpu_display_manager *dm = &adev->dm;
 666         struct amdgpu_dm_connector *aconnector;
 667         struct drm_connector *connector;
 668         struct drm_crtc *crtc;
 669         struct drm_crtc_state *new_crtc_state;
 670         struct dm_crtc_state *dm_new_crtc_state;
 671         struct drm_plane *plane;
 672         struct drm_plane_state *new_plane_state;
 673         struct dm_plane_state *dm_new_plane_state;
 674
 675         int ret = 0;
 676         int i;
 677
 678         /* program HPD filter */
 679         dc_resume(dm->dc);
 680
 681         /* On resume we need to  rewrite the MSTM control bits to enamble MST*/
 682         s3_handle_mst(ddev, false);
 683
 684         /*
 685          * early enable HPD Rx IRQ, should be done before set mode as short
 686          * pulse interrupts are used for MST
 687          */
 688         amdgpu_dm_irq_resume_early(adev);
 689
 690         /* Do detection*/
 691         list_for_each_entry(connector,
 692                         &ddev->mode_config.connector_list, head) {
 693                 aconnector = to_amdgpu_dm_connector(connector);
 694
 695                 /*
 696                  * this is the case when traversing through already created
 697                  * MST connectors, should be skipped
 698                  */
 699                 if (aconnector->mst_port)
 700                         continue;
 701
 702                 mutex_lock(&aconnector->hpd_lock);
 703                 dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
 704
 705                 if (aconnector->fake_enable && aconnector->dc_link->local_sink)
 706                         aconnector->fake_enable = false;
 707
 708                 aconnector->dc_sink = NULL;
 709                 amdgpu_dm_update_connector_after_detect(aconnector);
 710                 mutex_unlock(&aconnector->hpd_lock);
 711         }
 712
 713         /* Force mode set in atomic comit */
 714         for_each_new_crtc_in_state(adev->dm.cached_state, crtc, new_crtc_state, i)
 715                 new_crtc_state->active_changed = true;
 716
 717         /*
 718          * atomic_check is expected to create the dc states. We need to release
 719          * them here, since they were duplicated as part of the suspend
 720          * procedure.
 721          */
 722         for_each_new_crtc_in_state(adev->dm.cached_state, crtc, new_crtc_state, i) {
 723                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
 724                 if (dm_new_crtc_state->stream) {
 725                         WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
 726                         dc_stream_release(dm_new_crtc_state->stream);
 727                         dm_new_crtc_state->stream = NULL;
 728                 }
 729         }
 730
 731         for_each_new_plane_in_state(adev->dm.cached_state, plane, new_plane_state, i) {
 732                 dm_new_plane_state = to_dm_plane_state(new_plane_state);
 733                 if (dm_new_plane_state->dc_state) {
 734                         WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
 735                         dc_plane_state_release(dm_new_plane_state->dc_state);
 736                         dm_new_plane_state->dc_state = NULL;
 737                 }
 738         }
 739
 740         ret = drm_atomic_helper_resume(ddev, adev->dm.cached_state);
 741
 742         adev->dm.cached_state = NULL;
 743
 744         amdgpu_dm_irq_resume_late(adev);
 745
 746         return ret;
 747 }
 748
 749 static const struct amd_ip_funcs amdgpu_dm_funcs = {
 750         .name = "dm",
 751         .early_init = dm_early_init,
 752         .late_init = dm_late_init,
 753         .sw_init = dm_sw_init,
 754         .sw_fini = dm_sw_fini,
 755         .hw_init = dm_hw_init,
 756         .hw_fini = dm_hw_fini,
 757         .suspend = dm_suspend,
 758         .resume = dm_resume,
 759         .is_idle = dm_is_idle,
 760         .wait_for_idle = dm_wait_for_idle,
 761         .check_soft_reset = dm_check_soft_reset,
 762         .soft_reset = dm_soft_reset,
 763         .set_clockgating_state = dm_set_clockgating_state,
 764         .set_powergating_state = dm_set_powergating_state,
 765 };
 766
 767 const struct amdgpu_ip_block_version dm_ip_block =
 768 {
 769         .type = AMD_IP_BLOCK_TYPE_DCE,
 770         .major = 1,
 771         .minor = 0,
 772         .rev = 0,
 773         .funcs = &amdgpu_dm_funcs,
 774 };
 775
 776
 777 static struct drm_atomic_state *
 778 dm_atomic_state_alloc(struct drm_device *dev)
 779 {
 780         struct dm_atomic_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
 781
 782         if (!state)
 783                 return NULL;
 784
 785         if (drm_atomic_state_init(dev, &state->base) < 0)
 786                 goto fail;
 787
 788         return &state->base;
 789
 790 fail:
 791         kfree(state);
 792         return NULL;
 793 }
 794
 795 static void
 796 dm_atomic_state_clear(struct drm_atomic_state *state)
 797 {
 798         struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
 799
 800         if (dm_state->context) {
 801                 dc_release_state(dm_state->context);
 802                 dm_state->context = NULL;
 803         }
 804
 805         drm_atomic_state_default_clear(state);
 806 }
 807
 808 static void
 809 dm_atomic_state_alloc_free(struct drm_atomic_state *state)
 810 {
 811         struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
 812         drm_atomic_state_default_release(state);
 813         kfree(dm_state);
 814 }
 815
 816 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
 817         .fb_create = amdgpu_display_user_framebuffer_create,
 818         .output_poll_changed = drm_fb_helper_output_poll_changed,
 819         .atomic_check = amdgpu_dm_atomic_check,
 820         .atomic_commit = amdgpu_dm_atomic_commit,
 821         .atomic_state_alloc = dm_atomic_state_alloc,
 822         .atomic_state_clear = dm_atomic_state_clear,
 823         .atomic_state_free = dm_atomic_state_alloc_free
 824 };
 825
 826 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
 827         .atomic_commit_tail = amdgpu_dm_atomic_commit_tail
 828 };
 829
 830 static void
 831 amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector)
 832 {
 833         struct drm_connector *connector = &aconnector->base;
 834         struct drm_device *dev = connector->dev;
 835         struct dc_sink *sink;
 836
 837         /* MST handled by drm_mst framework */
 838         if (aconnector->mst_mgr.mst_state == true)
 839                 return;
 840
 841
 842         sink = aconnector->dc_link->local_sink;
 843
 844         /* Edid mgmt connector gets first update only in mode_valid hook and then
 845          * the connector sink is set to either fake or physical sink depends on link status.
 846          * don't do it here if u are during boot
 847          */
 848         if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
 849                         && aconnector->dc_em_sink) {
 850
 851                 /* For S3 resume with headless use eml_sink to fake stream
 852                  * because on resume connecotr->sink is set ti NULL
 853                  */
 854                 mutex_lock(&dev->mode_config.mutex);
 855
 856                 if (sink) {
 857                         if (aconnector->dc_sink) {
 858                                 amdgpu_dm_remove_sink_from_freesync_module(
 859                                                                 connector);
 860                                 /* retain and release bellow are used for
 861                                  * bump up refcount for sink because the link don't point
 862                                  * to it anymore after disconnect so on next crtc to connector
 863                                  * reshuffle by UMD we will get into unwanted dc_sink release
 864                                  */
 865                                 if (aconnector->dc_sink != aconnector->dc_em_sink)
 866                                         dc_sink_release(aconnector->dc_sink);
 867                         }
 868                         aconnector->dc_sink = sink;
 869                         amdgpu_dm_add_sink_to_freesync_module(
 870                                                 connector, aconnector->edid);
 871                 } else {
 872                         amdgpu_dm_remove_sink_from_freesync_module(connector);
 873                         if (!aconnector->dc_sink)
 874                                 aconnector->dc_sink = aconnector->dc_em_sink;
 875                         else if (aconnector->dc_sink != aconnector->dc_em_sink)
 876                                 dc_sink_retain(aconnector->dc_sink);
 877                 }
 878
 879                 mutex_unlock(&dev->mode_config.mutex);
 880                 return;
 881         }
 882
 883         /*
 884          * TODO: temporary guard to look for proper fix
 885          * if this sink is MST sink, we should not do anything
 886          */
 887         if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
 888                 return;
 889
 890         if (aconnector->dc_sink == sink) {
 891                 /* We got a DP short pulse (Link Loss, DP CTS, etc...).
 892                  * Do nothing!! */
 893                 DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
 894                                 aconnector->connector_id);
 895                 return;
 896         }
 897
 898         DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
 899                 aconnector->connector_id, aconnector->dc_sink, sink);
 900
 901         mutex_lock(&dev->mode_config.mutex);
 902
 903         /* 1. Update status of the drm connector
 904          * 2. Send an event and let userspace tell us what to do */
 905         if (sink) {
 906                 /* TODO: check if we still need the S3 mode update workaround.
 907                  * If yes, put it here. */
 908                 if (aconnector->dc_sink)
 909                         amdgpu_dm_remove_sink_from_freesync_module(
 910                                                         connector);
 911
 912                 aconnector->dc_sink = sink;
 913                 if (sink->dc_edid.length == 0) {
 914                         aconnector->edid = NULL;
 915                 } else {
 916                         aconnector->edid =
 917                                 (struct edid *) sink->dc_edid.raw_edid;
 918
 919
 920                         drm_mode_connector_update_edid_property(connector,
 921                                         aconnector->edid);
 922                 }
 923                 amdgpu_dm_add_sink_to_freesync_module(connector, aconnector->edid);
 924
 925         } else {
 926                 amdgpu_dm_remove_sink_from_freesync_module(connector);
 927                 drm_mode_connector_update_edid_property(connector, NULL);
 928                 aconnector->num_modes = 0;
 929                 aconnector->dc_sink = NULL;
 930         }
 931
 932         mutex_unlock(&dev->mode_config.mutex);
 933 }
 934
 935 static void handle_hpd_irq(void *param)
 936 {
 937         struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
 938         struct drm_connector *connector = &aconnector->base;
 939         struct drm_device *dev = connector->dev;
 940
 941         /* In case of failure or MST no need to update connector status or notify the OS
 942          * since (for MST case) MST does this in it's own context.
 943          */
 944         mutex_lock(&aconnector->hpd_lock);
 945
 946         if (aconnector->fake_enable)
 947                 aconnector->fake_enable = false;
 948
 949         if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) {
 950                 amdgpu_dm_update_connector_after_detect(aconnector);
 951
 952
 953                 drm_modeset_lock_all(dev);
 954                 dm_restore_drm_connector_state(dev, connector);
 955                 drm_modeset_unlock_all(dev);
 956
 957                 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
 958                         drm_kms_helper_hotplug_event(dev);
 959         }
 960         mutex_unlock(&aconnector->hpd_lock);
 961
 962 }
 963
 964 static void dm_handle_hpd_rx_irq(struct amdgpu_dm_connector *aconnector)
 965 {
 966         uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
 967         uint8_t dret;
 968         bool new_irq_handled = false;
 969         int dpcd_addr;
 970         int dpcd_bytes_to_read;
 971
 972         const int max_process_count = 30;
 973         int process_count = 0;
 974
 975         const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
 976
 977         if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
 978                 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
 979                 /* DPCD 0x200 - 0x201 for downstream IRQ */
 980                 dpcd_addr = DP_SINK_COUNT;
 981         } else {
 982                 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
 983                 /* DPCD 0x2002 - 0x2005 for downstream IRQ */
 984                 dpcd_addr = DP_SINK_COUNT_ESI;
 985         }
 986
 987         dret = drm_dp_dpcd_read(
 988                 &aconnector->dm_dp_aux.aux,
 989                 dpcd_addr,
 990                 esi,
 991                 dpcd_bytes_to_read);
 992
 993         while (dret == dpcd_bytes_to_read &&
 994                 process_count < max_process_count) {
 995                 uint8_t retry;
 996                 dret = 0;
 997
 998                 process_count++;
 999
1000                 DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
1001                 /* handle HPD short pulse irq */
1002                 if (aconnector->mst_mgr.mst_state)
1003                         drm_dp_mst_hpd_irq(
1004                                 &aconnector->mst_mgr,
1005                                 esi,
1006                                 &new_irq_handled);
1007
1008                 if (new_irq_handled) {
1009                         /* ACK at DPCD to notify down stream */
1010                         const int ack_dpcd_bytes_to_write =
1011                                 dpcd_bytes_to_read - 1;
1012
1013                         for (retry = 0; retry < 3; retry++) {
1014                                 uint8_t wret;
1015
1016                                 wret = drm_dp_dpcd_write(
1017                                         &aconnector->dm_dp_aux.aux,
1018                                         dpcd_addr + 1,
1019                                         &esi[1],
1020                                         ack_dpcd_bytes_to_write);
1021                                 if (wret == ack_dpcd_bytes_to_write)
1022                                         break;
1023                         }
1024
1025                         /* check if there is new irq to be handle */
1026                         dret = drm_dp_dpcd_read(
1027                                 &aconnector->dm_dp_aux.aux,
1028                                 dpcd_addr,
1029                                 esi,
1030                                 dpcd_bytes_to_read);
1031
1032                         new_irq_handled = false;
1033                 } else {
1034                         break;
1035                 }
1036         }
1037
1038         if (process_count == max_process_count)
1039                 DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
1040 }
1041
1042 static void handle_hpd_rx_irq(void *param)
1043 {
1044         struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
1045         struct drm_connector *connector = &aconnector->base;
1046         struct drm_device *dev = connector->dev;
1047         struct dc_link *dc_link = aconnector->dc_link;
1048         bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
1049
1050         /* TODO:Temporary add mutex to protect hpd interrupt not have a gpio
1051          * conflict, after implement i2c helper, this mutex should be
1052          * retired.
1053          */
1054         if (dc_link->type != dc_connection_mst_branch)
1055                 mutex_lock(&aconnector->hpd_lock);
1056
1057         if (dc_link_handle_hpd_rx_irq(dc_link, NULL) &&
1058                         !is_mst_root_connector) {
1059                 /* Downstream Port status changed. */
1060                 if (dc_link_detect(dc_link, DETECT_REASON_HPDRX)) {
1061                         amdgpu_dm_update_connector_after_detect(aconnector);
1062
1063
1064                         drm_modeset_lock_all(dev);
1065                         dm_restore_drm_connector_state(dev, connector);
1066                         drm_modeset_unlock_all(dev);
1067
1068                         drm_kms_helper_hotplug_event(dev);
1069                 }
1070         }
1071         if ((dc_link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
1072             (dc_link->type == dc_connection_mst_branch))
1073                 dm_handle_hpd_rx_irq(aconnector);
1074
1075         if (dc_link->type != dc_connection_mst_branch)
1076                 mutex_unlock(&aconnector->hpd_lock);
1077 }
1078
1079 static void register_hpd_handlers(struct amdgpu_device *adev)
1080 {
1081         struct drm_device *dev = adev->ddev;
1082         struct drm_connector *connector;
1083         struct amdgpu_dm_connector *aconnector;
1084         const struct dc_link *dc_link;
1085         struct dc_interrupt_params int_params = {0};
1086
1087         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1088         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1089
1090         list_for_each_entry(connector,
1091                         &dev->mode_config.connector_list, head) {
1092
1093                 aconnector = to_amdgpu_dm_connector(connector);
1094                 dc_link = aconnector->dc_link;
1095
1096                 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
1097                         int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1098                         int_params.irq_source = dc_link->irq_source_hpd;
1099
1100                         amdgpu_dm_irq_register_interrupt(adev, &int_params,
1101                                         handle_hpd_irq,
1102                                         (void *) aconnector);
1103                 }
1104
1105                 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
1106
1107                         /* Also register for DP short pulse (hpd_rx). */
1108                         int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1109                         int_params.irq_source = dc_link->irq_source_hpd_rx;
1110
1111                         amdgpu_dm_irq_register_interrupt(adev, &int_params,
1112                                         handle_hpd_rx_irq,
1113                                         (void *) aconnector);
1114                 }
1115         }
1116 }
1117
1118 /* Register IRQ sources and initialize IRQ callbacks */
1119 static int dce110_register_irq_handlers(struct amdgpu_device *adev)
1120 {
1121         struct dc *dc = adev->dm.dc;
1122         struct common_irq_params *c_irq_params;
1123         struct dc_interrupt_params int_params = {0};
1124         int r;
1125         int i;
1126         unsigned client_id = AMDGPU_IH_CLIENTID_LEGACY;
1127
1128         if (adev->asic_type == CHIP_VEGA10 ||
1129             adev->asic_type == CHIP_RAVEN)
1130                 client_id = AMDGPU_IH_CLIENTID_DCE;
1131
1132         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1133         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1134
1135         /* Actions of amdgpu_irq_add_id():
1136          * 1. Register a set() function with base driver.
1137          *    Base driver will call set() function to enable/disable an
1138          *    interrupt in DC hardware.
1139          * 2. Register amdgpu_dm_irq_handler().
1140          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1141          *    coming from DC hardware.
1142          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1143          *    for acknowledging and handling. */
1144
1145         /* Use VBLANK interrupt */
1146         for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
1147                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
1148                 if (r) {
1149                         DRM_ERROR("Failed to add crtc irq id!\n");
1150                         return r;
1151                 }
1152
1153                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1154                 int_params.irq_source =
1155                         dc_interrupt_to_irq_source(dc, i, 0);
1156
1157                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
1158
1159                 c_irq_params->adev = adev;
1160                 c_irq_params->irq_src = int_params.irq_source;
1161
1162                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1163                                 dm_crtc_high_irq, c_irq_params);
1164         }
1165
1166         /* Use GRPH_PFLIP interrupt */
1167         for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
1168                         i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
1169                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
1170                 if (r) {
1171                         DRM_ERROR("Failed to add page flip irq id!\n");
1172                         return r;
1173                 }
1174
1175                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1176                 int_params.irq_source =
1177                         dc_interrupt_to_irq_source(dc, i, 0);
1178
1179                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1180
1181                 c_irq_params->adev = adev;
1182                 c_irq_params->irq_src = int_params.irq_source;
1183
1184                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1185                                 dm_pflip_high_irq, c_irq_params);
1186
1187         }
1188
1189         /* HPD */
1190         r = amdgpu_irq_add_id(adev, client_id,
1191                         VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
1192         if (r) {
1193                 DRM_ERROR("Failed to add hpd irq id!\n");
1194                 return r;
1195         }
1196
1197         register_hpd_handlers(adev);
1198
1199         return 0;
1200 }
1201
1202 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1203 /* Register IRQ sources and initialize IRQ callbacks */
1204 static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
1205 {
1206         struct dc *dc = adev->dm.dc;
1207         struct common_irq_params *c_irq_params;
1208         struct dc_interrupt_params int_params = {0};
1209         int r;
1210         int i;
1211
1212         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1213         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1214
1215         /* Actions of amdgpu_irq_add_id():
1216          * 1. Register a set() function with base driver.
1217          *    Base driver will call set() function to enable/disable an
1218          *    interrupt in DC hardware.
1219          * 2. Register amdgpu_dm_irq_handler().
1220          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1221          *    coming from DC hardware.
1222          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1223          *    for acknowledging and handling.
1224          * */
1225
1226         /* Use VSTARTUP interrupt */
1227         for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
1228                         i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
1229                         i++) {
1230                 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_DCE, i, &adev->crtc_irq);
1231
1232                 if (r) {
1233                         DRM_ERROR("Failed to add crtc irq id!\n");
1234                         return r;
1235                 }
1236
1237                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1238                 int_params.irq_source =
1239                         dc_interrupt_to_irq_source(dc, i, 0);
1240
1241                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
1242
1243                 c_irq_params->adev = adev;
1244                 c_irq_params->irq_src = int_params.irq_source;
1245
1246                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1247                                 dm_crtc_high_irq, c_irq_params);
1248         }
1249
1250         /* Use GRPH_PFLIP interrupt */
1251         for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
1252                         i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1;
1253                         i++) {
1254                 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
1255                 if (r) {
1256                         DRM_ERROR("Failed to add page flip irq id!\n");
1257                         return r;
1258                 }
1259
1260                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1261                 int_params.irq_source =
1262                         dc_interrupt_to_irq_source(dc, i, 0);
1263
1264                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1265
1266                 c_irq_params->adev = adev;
1267                 c_irq_params->irq_src = int_params.irq_source;
1268
1269                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1270                                 dm_pflip_high_irq, c_irq_params);
1271
1272         }
1273
1274         /* HPD */
1275         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
1276                         &adev->hpd_irq);
1277         if (r) {
1278                 DRM_ERROR("Failed to add hpd irq id!\n");
1279                 return r;
1280         }
1281
1282         register_hpd_handlers(adev);
1283
1284         return 0;
1285 }
1286 #endif
1287
1288 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
1289 {
1290         int r;
1291
1292         adev->mode_info.mode_config_initialized = true;
1293
1294         adev->ddev->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
1295         adev->ddev->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
1296
1297         adev->ddev->mode_config.max_width = 16384;
1298         adev->ddev->mode_config.max_height = 16384;
1299
1300         adev->ddev->mode_config.preferred_depth = 24;
1301         adev->ddev->mode_config.prefer_shadow = 1;
1302         /* indicate support of immediate flip */
1303         adev->ddev->mode_config.async_page_flip = true;
1304
1305         adev->ddev->mode_config.fb_base = adev->gmc.aper_base;
1306
1307         r = amdgpu_display_modeset_create_props(adev);
1308         if (r)
1309                 return r;
1310
1311         return 0;
1312 }
1313
1314 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
1315         defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
1316
1317 static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
1318 {
1319         struct amdgpu_display_manager *dm = bl_get_data(bd);
1320
1321         if (dc_link_set_backlight_level(dm->backlight_link,
1322                         bd->props.brightness, 0, 0))
1323                 return 0;
1324         else
1325                 return 1;
1326 }
1327
1328 static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
1329 {
1330         return bd->props.brightness;
1331 }
1332
1333 static const struct backlight_ops amdgpu_dm_backlight_ops = {
1334         .get_brightness = amdgpu_dm_backlight_get_brightness,
1335         .update_status  = amdgpu_dm_backlight_update_status,
1336 };
1337
1338 static void
1339 amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm)
1340 {
1341         char bl_name[16];
1342         struct backlight_properties props = { 0 };
1343
1344         props.max_brightness = AMDGPU_MAX_BL_LEVEL;
1345         props.type = BACKLIGHT_RAW;
1346
1347         snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
1348                         dm->adev->ddev->primary->index);
1349
1350         dm->backlight_dev = backlight_device_register(bl_name,
1351                         dm->adev->ddev->dev,
1352                         dm,
1353                         &amdgpu_dm_backlight_ops,
1354                         &props);
1355
1356         if (IS_ERR(dm->backlight_dev))
1357                 DRM_ERROR("DM: Backlight registration failed!\n");
1358         else
1359                 DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
1360 }
1361
1362 #endif
1363
1364 /* In this architecture, the association
1365  * connector -> encoder -> crtc
1366  * id not really requried. The crtc and connector will hold the
1367  * display_index as an abstraction to use with DAL component
1368  *
1369  * Returns 0 on success
1370  */
1371 static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
1372 {
1373         struct amdgpu_display_manager *dm = &adev->dm;
1374         uint32_t i;
1375         struct amdgpu_dm_connector *aconnector = NULL;
1376         struct amdgpu_encoder *aencoder = NULL;
1377         struct amdgpu_mode_info *mode_info = &adev->mode_info;
1378         uint32_t link_cnt;
1379         unsigned long possible_crtcs;
1380
1381         link_cnt = dm->dc->caps.max_links;
1382         if (amdgpu_dm_mode_config_init(dm->adev)) {
1383                 DRM_ERROR("DM: Failed to initialize mode config\n");
1384                 return -1;
1385         }
1386
1387         for (i = 0; i < dm->dc->caps.max_planes; i++) {
1388                 struct amdgpu_plane *plane;
1389
1390                 plane = kzalloc(sizeof(struct amdgpu_plane), GFP_KERNEL);
1391                 mode_info->planes[i] = plane;
1392
1393                 if (!plane) {
1394                         DRM_ERROR("KMS: Failed to allocate plane\n");
1395                         goto fail;
1396                 }
1397                 plane->base.type = mode_info->plane_type[i];
1398
1399                 /*
1400                  * HACK: IGT tests expect that each plane can only have one
1401                  * one possible CRTC. For now, set one CRTC for each
1402                  * plane that is not an underlay, but still allow multiple
1403                  * CRTCs for underlay planes.
1404                  */
1405                 possible_crtcs = 1 << i;
1406                 if (i >= dm->dc->caps.max_streams)
1407                         possible_crtcs = 0xff;
1408
1409                 if (amdgpu_dm_plane_init(dm, mode_info->planes[i], possible_crtcs)) {
1410                         DRM_ERROR("KMS: Failed to initialize plane\n");
1411                         goto fail;
1412                 }
1413         }
1414
1415         for (i = 0; i < dm->dc->caps.max_streams; i++)
1416                 if (amdgpu_dm_crtc_init(dm, &mode_info->planes[i]->base, i)) {
1417                         DRM_ERROR("KMS: Failed to initialize crtc\n");
1418                         goto fail;
1419                 }
1420
1421         dm->display_indexes_num = dm->dc->caps.max_streams;
1422
1423         /* loops over all connectors on the board */
1424         for (i = 0; i < link_cnt; i++) {
1425
1426                 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
1427                         DRM_ERROR(
1428                                 "KMS: Cannot support more than %d display indexes\n",
1429                                         AMDGPU_DM_MAX_DISPLAY_INDEX);
1430                         continue;
1431                 }
1432
1433                 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
1434                 if (!aconnector)
1435                         goto fail;
1436
1437                 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
1438                 if (!aencoder)
1439                         goto fail;
1440
1441                 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
1442                         DRM_ERROR("KMS: Failed to initialize encoder\n");
1443                         goto fail;
1444                 }
1445
1446                 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
1447                         DRM_ERROR("KMS: Failed to initialize connector\n");
1448                         goto fail;
1449                 }
1450
1451                 if (dc_link_detect(dc_get_link_at_index(dm->dc, i),
1452                                 DETECT_REASON_BOOT))
1453                         amdgpu_dm_update_connector_after_detect(aconnector);
1454         }
1455
1456         /* Software is initialized. Now we can register interrupt handlers. */
1457         switch (adev->asic_type) {
1458         case CHIP_BONAIRE:
1459         case CHIP_HAWAII:
1460         case CHIP_KAVERI:
1461         case CHIP_KABINI:
1462         case CHIP_MULLINS:
1463         case CHIP_TONGA:
1464         case CHIP_FIJI:
1465         case CHIP_CARRIZO:
1466         case CHIP_STONEY:
1467         case CHIP_POLARIS11:
1468         case CHIP_POLARIS10:
1469         case CHIP_POLARIS12:
1470         case CHIP_VEGA10:
1471                 if (dce110_register_irq_handlers(dm->adev)) {
1472                         DRM_ERROR("DM: Failed to initialize IRQ\n");
1473                         goto fail;
1474                 }
1475                 break;
1476 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1477         case CHIP_RAVEN:
1478                 if (dcn10_register_irq_handlers(dm->adev)) {
1479                         DRM_ERROR("DM: Failed to initialize IRQ\n");
1480                         goto fail;
1481                 }
1482                 /*
1483                  * Temporary disable until pplib/smu interaction is implemented
1484                  */
1485                 dm->dc->debug.disable_stutter = true;
1486                 break;
1487 #endif
1488         default:
1489                 DRM_ERROR("Usupported ASIC type: 0x%X\n", adev->asic_type);
1490                 goto fail;
1491         }
1492
1493         return 0;
1494 fail:
1495         kfree(aencoder);
1496         kfree(aconnector);
1497         for (i = 0; i < dm->dc->caps.max_planes; i++)
1498                 kfree(mode_info->planes[i]);
1499         return -1;
1500 }
1501
1502 static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
1503 {
1504         drm_mode_config_cleanup(dm->ddev);
1505         return;
1506 }
1507
1508 /******************************************************************************
1509  * amdgpu_display_funcs functions
1510  *****************************************************************************/
1511
1512 /**
1513  * dm_bandwidth_update - program display watermarks
1514  *
1515  * @adev: amdgpu_device pointer
1516  *
1517  * Calculate and program the display watermarks and line buffer allocation.
1518  */
1519 static void dm_bandwidth_update(struct amdgpu_device *adev)
1520 {
1521         /* TODO: implement later */
1522 }
1523
1524 static void dm_set_backlight_level(struct amdgpu_encoder *amdgpu_encoder,
1525                                      u8 level)
1526 {
1527         /* TODO: translate amdgpu_encoder to display_index and call DAL */
1528 }
1529
1530 static u8 dm_get_backlight_level(struct amdgpu_encoder *amdgpu_encoder)
1531 {
1532         /* TODO: translate amdgpu_encoder to display_index and call DAL */
1533         return 0;
1534 }
1535
1536 static int amdgpu_notify_freesync(struct drm_device *dev, void *data,
1537                                 struct drm_file *filp)
1538 {
1539         struct mod_freesync_params freesync_params;
1540         uint8_t num_streams;
1541         uint8_t i;
1542
1543         struct amdgpu_device *adev = dev->dev_private;
1544         int r = 0;
1545
1546         /* Get freesync enable flag from DRM */
1547
1548         num_streams = dc_get_current_stream_count(adev->dm.dc);
1549
1550         for (i = 0; i < num_streams; i++) {
1551                 struct dc_stream_state *stream;
1552                 stream = dc_get_stream_at_index(adev->dm.dc, i);
1553
1554                 mod_freesync_update_state(adev->dm.freesync_module,
1555                                           &stream, 1, &freesync_params);
1556         }
1557
1558         return r;
1559 }
1560
1561 static const struct amdgpu_display_funcs dm_display_funcs = {
1562         .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
1563         .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
1564         .backlight_set_level =
1565                 dm_set_backlight_level,/* called unconditionally */
1566         .backlight_get_level =
1567                 dm_get_backlight_level,/* called unconditionally */
1568         .hpd_sense = NULL,/* called unconditionally */
1569         .hpd_set_polarity = NULL, /* called unconditionally */
1570         .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
1571         .page_flip_get_scanoutpos =
1572                 dm_crtc_get_scanoutpos,/* called unconditionally */
1573         .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
1574         .add_connector = NULL, /* VBIOS parsing. DAL does it. */
1575         .notify_freesync = amdgpu_notify_freesync,
1576
1577 };
1578
1579 #if defined(CONFIG_DEBUG_KERNEL_DC)
1580
1581 static ssize_t s3_debug_store(struct device *device,
1582                               struct device_attribute *attr,
1583                               const char *buf,
1584                               size_t count)
1585 {
1586         int ret;
1587         int s3_state;
1588         struct pci_dev *pdev = to_pci_dev(device);
1589         struct drm_device *drm_dev = pci_get_drvdata(pdev);
1590         struct amdgpu_device *adev = drm_dev->dev_private;
1591
1592         ret = kstrtoint(buf, 0, &s3_state);
1593
1594         if (ret == 0) {
1595                 if (s3_state) {
1596                         dm_resume(adev);
1597                         amdgpu_dm_display_resume(adev);
1598                         drm_kms_helper_hotplug_event(adev->ddev);
1599                 } else
1600                         dm_suspend(adev);
1601         }
1602
1603         return ret == 0 ? count : 0;
1604 }
1605
1606 DEVICE_ATTR_WO(s3_debug);
1607
1608 #endif
1609
1610 static int dm_early_init(void *handle)
1611 {
1612         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1613
1614         switch (adev->asic_type) {
1615         case CHIP_BONAIRE:
1616         case CHIP_HAWAII:
1617                 adev->mode_info.num_crtc = 6;
1618                 adev->mode_info.num_hpd = 6;
1619                 adev->mode_info.num_dig = 6;
1620                 adev->mode_info.plane_type = dm_plane_type_default;
1621                 break;
1622         case CHIP_KAVERI:
1623                 adev->mode_info.num_crtc = 4;
1624                 adev->mode_info.num_hpd = 6;
1625                 adev->mode_info.num_dig = 7;
1626                 adev->mode_info.plane_type = dm_plane_type_default;
1627                 break;
1628         case CHIP_KABINI:
1629         case CHIP_MULLINS:
1630                 adev->mode_info.num_crtc = 2;
1631                 adev->mode_info.num_hpd = 6;
1632                 adev->mode_info.num_dig = 6;
1633                 adev->mode_info.plane_type = dm_plane_type_default;
1634                 break;
1635         case CHIP_FIJI:
1636         case CHIP_TONGA:
1637                 adev->mode_info.num_crtc = 6;
1638                 adev->mode_info.num_hpd = 6;
1639                 adev->mode_info.num_dig = 7;
1640                 adev->mode_info.plane_type = dm_plane_type_default;
1641                 break;
1642         case CHIP_CARRIZO:
1643                 adev->mode_info.num_crtc = 3;
1644                 adev->mode_info.num_hpd = 6;
1645                 adev->mode_info.num_dig = 9;
1646                 adev->mode_info.plane_type = dm_plane_type_carizzo;
1647                 break;
1648         case CHIP_STONEY:
1649                 adev->mode_info.num_crtc = 2;
1650                 adev->mode_info.num_hpd = 6;
1651                 adev->mode_info.num_dig = 9;
1652                 adev->mode_info.plane_type = dm_plane_type_stoney;
1653                 break;
1654         case CHIP_POLARIS11:
1655         case CHIP_POLARIS12:
1656                 adev->mode_info.num_crtc = 5;
1657                 adev->mode_info.num_hpd = 5;
1658                 adev->mode_info.num_dig = 5;
1659                 adev->mode_info.plane_type = dm_plane_type_default;
1660                 break;
1661         case CHIP_POLARIS10:
1662                 adev->mode_info.num_crtc = 6;
1663                 adev->mode_info.num_hpd = 6;
1664                 adev->mode_info.num_dig = 6;
1665                 adev->mode_info.plane_type = dm_plane_type_default;
1666                 break;
1667         case CHIP_VEGA10:
1668                 adev->mode_info.num_crtc = 6;
1669                 adev->mode_info.num_hpd = 6;
1670                 adev->mode_info.num_dig = 6;
1671                 adev->mode_info.plane_type = dm_plane_type_default;
1672                 break;
1673 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1674         case CHIP_RAVEN:
1675                 adev->mode_info.num_crtc = 4;
1676                 adev->mode_info.num_hpd = 4;
1677                 adev->mode_info.num_dig = 4;
1678                 adev->mode_info.plane_type = dm_plane_type_default;
1679                 break;
1680 #endif
1681         default:
1682                 DRM_ERROR("Usupported ASIC type: 0x%X\n", adev->asic_type);
1683                 return -EINVAL;
1684         }
1685
1686         amdgpu_dm_set_irq_funcs(adev);
1687
1688         if (adev->mode_info.funcs == NULL)
1689                 adev->mode_info.funcs = &dm_display_funcs;
1690
1691         /* Note: Do NOT change adev->audio_endpt_rreg and
1692          * adev->audio_endpt_wreg because they are initialised in
1693          * amdgpu_device_init() */
1694 #if defined(CONFIG_DEBUG_KERNEL_DC)
1695         device_create_file(
1696                 adev->ddev->dev,
1697                 &dev_attr_s3_debug);
1698 #endif
1699
1700         return 0;
1701 }
1702
1703 static bool modeset_required(struct drm_crtc_state *crtc_state,
1704                              struct dc_stream_state *new_stream,
1705                              struct dc_stream_state *old_stream)
1706 {
1707         if (!drm_atomic_crtc_needs_modeset(crtc_state))
1708                 return false;
1709
1710         if (!crtc_state->enable)
1711                 return false;
1712
1713         return crtc_state->active;
1714 }
1715
1716 static bool modereset_required(struct drm_crtc_state *crtc_state)
1717 {
1718         if (!drm_atomic_crtc_needs_modeset(crtc_state))
1719                 return false;
1720
1721         return !crtc_state->enable || !crtc_state->active;
1722 }
1723
1724 static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
1725 {
1726         drm_encoder_cleanup(encoder);
1727         kfree(encoder);
1728 }
1729
1730 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
1731         .destroy = amdgpu_dm_encoder_destroy,
1732 };
1733
1734 static bool fill_rects_from_plane_state(const struct drm_plane_state *state,
1735                                         struct dc_plane_state *plane_state)
1736 {
1737         plane_state->src_rect.x = state->src_x >> 16;
1738         plane_state->src_rect.y = state->src_y >> 16;
1739         /*we ignore for now mantissa and do not to deal with floating pixels :(*/
1740         plane_state->src_rect.width = state->src_w >> 16;
1741
1742         if (plane_state->src_rect.width == 0)
1743                 return false;
1744
1745         plane_state->src_rect.height = state->src_h >> 16;
1746         if (plane_state->src_rect.height == 0)
1747                 return false;
1748
1749         plane_state->dst_rect.x = state->crtc_x;
1750         plane_state->dst_rect.y = state->crtc_y;
1751
1752         if (state->crtc_w == 0)
1753                 return false;
1754
1755         plane_state->dst_rect.width = state->crtc_w;
1756
1757         if (state->crtc_h == 0)
1758                 return false;
1759
1760         plane_state->dst_rect.height = state->crtc_h;
1761
1762         plane_state->clip_rect = plane_state->dst_rect;
1763
1764         switch (state->rotation & DRM_MODE_ROTATE_MASK) {
1765         case DRM_MODE_ROTATE_0:
1766                 plane_state->rotation = ROTATION_ANGLE_0;
1767                 break;
1768         case DRM_MODE_ROTATE_90:
1769                 plane_state->rotation = ROTATION_ANGLE_90;
1770                 break;
1771         case DRM_MODE_ROTATE_180:
1772                 plane_state->rotation = ROTATION_ANGLE_180;
1773                 break;
1774         case DRM_MODE_ROTATE_270:
1775                 plane_state->rotation = ROTATION_ANGLE_270;
1776                 break;
1777         default:
1778                 plane_state->rotation = ROTATION_ANGLE_0;
1779                 break;
1780         }
1781
1782         return true;
1783 }
1784 static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,
1785                        uint64_t *tiling_flags)
1786 {
1787         struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
1788         int r = amdgpu_bo_reserve(rbo, false);
1789
1790         if (unlikely(r)) {
1791                 // Don't show error msg. when return -ERESTARTSYS
1792                 if (r != -ERESTARTSYS)
1793                         DRM_ERROR("Unable to reserve buffer: %d\n", r);
1794                 return r;
1795         }
1796
1797         if (tiling_flags)
1798                 amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
1799
1800         amdgpu_bo_unreserve(rbo);
1801
1802         return r;
1803 }
1804
1805 static int fill_plane_attributes_from_fb(struct amdgpu_device *adev,
1806                                          struct dc_plane_state *plane_state,
1807                                          const struct amdgpu_framebuffer *amdgpu_fb)
1808 {
1809         uint64_t tiling_flags;
1810         unsigned int awidth;
1811         const struct drm_framebuffer *fb = &amdgpu_fb->base;
1812         int ret = 0;
1813         struct drm_format_name_buf format_name;
1814
1815         ret = get_fb_info(
1816                 amdgpu_fb,
1817                 &tiling_flags);
1818
1819         if (ret)
1820                 return ret;
1821
1822         switch (fb->format->format) {
1823         case DRM_FORMAT_C8:
1824                 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
1825                 break;
1826         case DRM_FORMAT_RGB565:
1827                 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
1828                 break;
1829         case DRM_FORMAT_XRGB8888:
1830         case DRM_FORMAT_ARGB8888:
1831                 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
1832                 break;
1833         case DRM_FORMAT_XRGB2101010:
1834         case DRM_FORMAT_ARGB2101010:
1835                 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
1836                 break;
1837         case DRM_FORMAT_XBGR2101010:
1838         case DRM_FORMAT_ABGR2101010:
1839                 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
1840                 break;
1841         case DRM_FORMAT_NV21:
1842                 plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
1843                 break;
1844         case DRM_FORMAT_NV12:
1845                 plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
1846                 break;
1847         default:
1848                 DRM_ERROR("Unsupported screen format %s\n",
1849                           drm_get_format_name(fb->format->format, &format_name));
1850                 return -EINVAL;
1851         }
1852
1853         if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
1854                 plane_state->address.type = PLN_ADDR_TYPE_GRAPHICS;
1855                 plane_state->plane_size.grph.surface_size.x = 0;
1856                 plane_state->plane_size.grph.surface_size.y = 0;
1857                 plane_state->plane_size.grph.surface_size.width = fb->width;
1858                 plane_state->plane_size.grph.surface_size.height = fb->height;
1859                 plane_state->plane_size.grph.surface_pitch =
1860                                 fb->pitches[0] / fb->format->cpp[0];
1861                 /* TODO: unhardcode */
1862                 plane_state->color_space = COLOR_SPACE_SRGB;
1863
1864         } else {
1865                 awidth = ALIGN(fb->width, 64);
1866                 plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
1867                 plane_state->plane_size.video.luma_size.x = 0;
1868                 plane_state->plane_size.video.luma_size.y = 0;
1869                 plane_state->plane_size.video.luma_size.width = awidth;
1870                 plane_state->plane_size.video.luma_size.height = fb->height;
1871                 /* TODO: unhardcode */
1872                 plane_state->plane_size.video.luma_pitch = awidth;
1873
1874                 plane_state->plane_size.video.chroma_size.x = 0;
1875                 plane_state->plane_size.video.chroma_size.y = 0;
1876                 plane_state->plane_size.video.chroma_size.width = awidth;
1877                 plane_state->plane_size.video.chroma_size.height = fb->height;
1878                 plane_state->plane_size.video.chroma_pitch = awidth / 2;
1879
1880                 /* TODO: unhardcode */
1881                 plane_state->color_space = COLOR_SPACE_YCBCR709;
1882         }
1883
1884         memset(&plane_state->tiling_info, 0, sizeof(plane_state->tiling_info));
1885
1886         /* Fill GFX8 params */
1887         if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) {
1888                 unsigned int bankw, bankh, mtaspect, tile_split, num_banks;
1889
1890                 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
1891                 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
1892                 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
1893                 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
1894                 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
1895
1896                 /* XXX fix me for VI */
1897                 plane_state->tiling_info.gfx8.num_banks = num_banks;
1898                 plane_state->tiling_info.gfx8.array_mode =
1899                                 DC_ARRAY_2D_TILED_THIN1;
1900                 plane_state->tiling_info.gfx8.tile_split = tile_split;
1901                 plane_state->tiling_info.gfx8.bank_width = bankw;
1902                 plane_state->tiling_info.gfx8.bank_height = bankh;
1903                 plane_state->tiling_info.gfx8.tile_aspect = mtaspect;
1904                 plane_state->tiling_info.gfx8.tile_mode =
1905                                 DC_ADDR_SURF_MICRO_TILING_DISPLAY;
1906         } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)
1907                         == DC_ARRAY_1D_TILED_THIN1) {
1908                 plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1;
1909         }
1910
1911         plane_state->tiling_info.gfx8.pipe_config =
1912                         AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1913
1914         if (adev->asic_type == CHIP_VEGA10 ||
1915             adev->asic_type == CHIP_RAVEN) {
1916                 /* Fill GFX9 params */
1917                 plane_state->tiling_info.gfx9.num_pipes =
1918                         adev->gfx.config.gb_addr_config_fields.num_pipes;
1919                 plane_state->tiling_info.gfx9.num_banks =
1920                         adev->gfx.config.gb_addr_config_fields.num_banks;
1921                 plane_state->tiling_info.gfx9.pipe_interleave =
1922                         adev->gfx.config.gb_addr_config_fields.pipe_interleave_size;
1923                 plane_state->tiling_info.gfx9.num_shader_engines =
1924                         adev->gfx.config.gb_addr_config_fields.num_se;
1925                 plane_state->tiling_info.gfx9.max_compressed_frags =
1926                         adev->gfx.config.gb_addr_config_fields.max_compress_frags;
1927                 plane_state->tiling_info.gfx9.num_rb_per_se =
1928                         adev->gfx.config.gb_addr_config_fields.num_rb_per_se;
1929                 plane_state->tiling_info.gfx9.swizzle =
1930                         AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE);
1931                 plane_state->tiling_info.gfx9.shaderEnable = 1;
1932         }
1933
1934         plane_state->visible = true;
1935         plane_state->scaling_quality.h_taps_c = 0;
1936         plane_state->scaling_quality.v_taps_c = 0;
1937
1938         /* is this needed? is plane_state zeroed at allocation? */
1939         plane_state->scaling_quality.h_taps = 0;
1940         plane_state->scaling_quality.v_taps = 0;
1941         plane_state->stereo_format = PLANE_STEREO_FORMAT_NONE;
1942
1943         return ret;
1944
1945 }
1946
1947 static int fill_plane_attributes(struct amdgpu_device *adev,
1948                                  struct dc_plane_state *dc_plane_state,
1949                                  struct drm_plane_state *plane_state,
1950                                  struct drm_crtc_state *crtc_state)
1951 {
1952         const struct amdgpu_framebuffer *amdgpu_fb =
1953                 to_amdgpu_framebuffer(plane_state->fb);
1954         const struct drm_crtc *crtc = plane_state->crtc;
1955         struct dc_transfer_func *input_tf;
1956         int ret = 0;
1957
1958         if (!fill_rects_from_plane_state(plane_state, dc_plane_state))
1959                 return -EINVAL;
1960
1961         ret = fill_plane_attributes_from_fb(
1962                 crtc->dev->dev_private,
1963                 dc_plane_state,
1964                 amdgpu_fb);
1965
1966         if (ret)
1967                 return ret;
1968
1969         input_tf = dc_create_transfer_func();
1970
1971         if (input_tf == NULL)
1972                 return -ENOMEM;
1973
1974         dc_plane_state->in_transfer_func = input_tf;
1975
1976         /*
1977          * Always set input transfer function, since plane state is refreshed
1978          * every time.
1979          */
1980         ret = amdgpu_dm_set_degamma_lut(crtc_state, dc_plane_state);
1981
1982         return ret;
1983 }
1984
1985 /*****************************************************************************/
1986
1987 static void update_stream_scaling_settings(const struct drm_display_mode *mode,
1988                                            const struct dm_connector_state *dm_state,
1989                                            struct dc_stream_state *stream)
1990 {
1991         enum amdgpu_rmx_type rmx_type;
1992
1993         struct rect src = { 0 }; /* viewport in composition space*/
1994         struct rect dst = { 0 }; /* stream addressable area */
1995
1996         /* no mode. nothing to be done */
1997         if (!mode)
1998                 return;
1999
2000         /* Full screen scaling by default */
2001         src.width = mode->hdisplay;
2002         src.height = mode->vdisplay;
2003         dst.width = stream->timing.h_addressable;
2004         dst.height = stream->timing.v_addressable;
2005
2006         if (dm_state) {
2007                 rmx_type = dm_state->scaling;
2008                 if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
2009                         if (src.width * dst.height <
2010                                         src.height * dst.width) {
2011                                 /* height needs less upscaling/more downscaling */
2012                                 dst.width = src.width *
2013                                                 dst.height / src.height;
2014                         } else {
2015                                 /* width needs less upscaling/more downscaling */
2016                                 dst.height = src.height *
2017                                                 dst.width / src.width;
2018                         }
2019                 } else if (rmx_type == RMX_CENTER) {
2020                         dst = src;
2021                 }
2022
2023                 dst.x = (stream->timing.h_addressable - dst.width) / 2;
2024                 dst.y = (stream->timing.v_addressable - dst.height) / 2;
2025
2026                 if (dm_state->underscan_enable) {
2027                         dst.x += dm_state->underscan_hborder / 2;
2028                         dst.y += dm_state->underscan_vborder / 2;
2029                         dst.width -= dm_state->underscan_hborder;
2030                         dst.height -= dm_state->underscan_vborder;
2031                 }
2032         }
2033
2034         stream->src = src;
2035         stream->dst = dst;
2036
2037         DRM_DEBUG_DRIVER("Destination Rectangle x:%d  y:%d  width:%d  height:%d\n",
2038                         dst.x, dst.y, dst.width, dst.height);
2039
2040 }
2041
2042 static enum dc_color_depth
2043 convert_color_depth_from_display_info(const struct drm_connector *connector)
2044 {
2045         uint32_t bpc = connector->display_info.bpc;
2046
2047         /* Limited color depth to 8bit
2048          * TODO: Still need to handle deep color
2049          */
2050         if (bpc > 8)
2051                 bpc = 8;
2052
2053         switch (bpc) {
2054         case 0:
2055                 /* Temporary Work around, DRM don't parse color depth for
2056                  * EDID revision before 1.4
2057                  * TODO: Fix edid parsing
2058                  */
2059                 return COLOR_DEPTH_888;
2060         case 6:
2061                 return COLOR_DEPTH_666;
2062         case 8:
2063                 return COLOR_DEPTH_888;
2064         case 10:
2065                 return COLOR_DEPTH_101010;
2066         case 12:
2067                 return COLOR_DEPTH_121212;
2068         case 14:
2069                 return COLOR_DEPTH_141414;
2070         case 16:
2071                 return COLOR_DEPTH_161616;
2072         default:
2073                 return COLOR_DEPTH_UNDEFINED;
2074         }
2075 }
2076
2077 static enum dc_aspect_ratio
2078 get_aspect_ratio(const struct drm_display_mode *mode_in)
2079 {
2080         int32_t width = mode_in->crtc_hdisplay * 9;
2081         int32_t height = mode_in->crtc_vdisplay * 16;
2082
2083         if ((width - height) < 10 && (width - height) > -10)
2084                 return ASPECT_RATIO_16_9;
2085         else
2086                 return ASPECT_RATIO_4_3;
2087 }
2088
2089 static enum dc_color_space
2090 get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
2091 {
2092         enum dc_color_space color_space = COLOR_SPACE_SRGB;
2093
2094         switch (dc_crtc_timing->pixel_encoding) {
2095         case PIXEL_ENCODING_YCBCR422:
2096         case PIXEL_ENCODING_YCBCR444:
2097         case PIXEL_ENCODING_YCBCR420:
2098         {
2099                 /*
2100                  * 27030khz is the separation point between HDTV and SDTV
2101                  * according to HDMI spec, we use YCbCr709 and YCbCr601
2102                  * respectively
2103                  */
2104                 if (dc_crtc_timing->pix_clk_khz > 27030) {
2105                         if (dc_crtc_timing->flags.Y_ONLY)
2106                                 color_space =
2107                                         COLOR_SPACE_YCBCR709_LIMITED;
2108                         else
2109                                 color_space = COLOR_SPACE_YCBCR709;
2110                 } else {
2111                         if (dc_crtc_timing->flags.Y_ONLY)
2112                                 color_space =
2113                                         COLOR_SPACE_YCBCR601_LIMITED;
2114                         else
2115                                 color_space = COLOR_SPACE_YCBCR601;
2116                 }
2117
2118         }
2119         break;
2120         case PIXEL_ENCODING_RGB:
2121                 color_space = COLOR_SPACE_SRGB;
2122                 break;
2123
2124         default:
2125                 WARN_ON(1);
2126                 break;
2127         }
2128
2129         return color_space;
2130 }
2131
2132 /*****************************************************************************/
2133
2134 static void
2135 fill_stream_properties_from_drm_display_mode(struct dc_stream_state *stream,
2136                                              const struct drm_display_mode *mode_in,
2137                                              const struct drm_connector *connector)
2138 {
2139         struct dc_crtc_timing *timing_out = &stream->timing;
2140         struct dc_transfer_func *tf = dc_create_transfer_func();
2141
2142         memset(timing_out, 0, sizeof(struct dc_crtc_timing));
2143
2144         timing_out->h_border_left = 0;
2145         timing_out->h_border_right = 0;
2146         timing_out->v_border_top = 0;
2147         timing_out->v_border_bottom = 0;
2148         /* TODO: un-hardcode */
2149
2150         if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444)
2151                         && stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A)
2152                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
2153         else
2154                 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
2155
2156         timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
2157         timing_out->display_color_depth = convert_color_depth_from_display_info(
2158                         connector);
2159         timing_out->scan_type = SCANNING_TYPE_NODATA;
2160         timing_out->hdmi_vic = 0;
2161         timing_out->vic = drm_match_cea_mode(mode_in);
2162
2163         timing_out->h_addressable = mode_in->crtc_hdisplay;
2164         timing_out->h_total = mode_in->crtc_htotal;
2165         timing_out->h_sync_width =
2166                 mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
2167         timing_out->h_front_porch =
2168                 mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
2169         timing_out->v_total = mode_in->crtc_vtotal;
2170         timing_out->v_addressable = mode_in->crtc_vdisplay;
2171         timing_out->v_front_porch =
2172                 mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
2173         timing_out->v_sync_width =
2174                 mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
2175         timing_out->pix_clk_khz = mode_in->crtc_clock;
2176         timing_out->aspect_ratio = get_aspect_ratio(mode_in);
2177         if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
2178                 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
2179         if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
2180                 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
2181
2182         stream->output_color_space = get_output_color_space(timing_out);
2183
2184         tf->type = TF_TYPE_PREDEFINED;
2185         tf->tf = TRANSFER_FUNCTION_SRGB;
2186         stream->out_transfer_func = tf;
2187 }
2188
2189 static void fill_audio_info(struct audio_info *audio_info,
2190                             const struct drm_connector *drm_connector,
2191                             const struct dc_sink *dc_sink)
2192 {
2193         int i = 0;
2194         int cea_revision = 0;
2195         const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
2196
2197         audio_info->manufacture_id = edid_caps->manufacturer_id;
2198         audio_info->product_id = edid_caps->product_id;
2199
2200         cea_revision = drm_connector->display_info.cea_rev;
2201
2202         strncpy(audio_info->display_name,
2203                 edid_caps->display_name,
2204                 AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS - 1);
2205
2206         if (cea_revision >= 3) {
2207                 audio_info->mode_count = edid_caps->audio_mode_count;
2208
2209                 for (i = 0; i < audio_info->mode_count; ++i) {
2210                         audio_info->modes[i].format_code =
2211                                         (enum audio_format_code)
2212                                         (edid_caps->audio_modes[i].format_code);
2213                         audio_info->modes[i].channel_count =
2214                                         edid_caps->audio_modes[i].channel_count;
2215                         audio_info->modes[i].sample_rates.all =
2216                                         edid_caps->audio_modes[i].sample_rate;
2217                         audio_info->modes[i].sample_size =
2218                                         edid_caps->audio_modes[i].sample_size;
2219                 }
2220         }
2221
2222         audio_info->flags.all = edid_caps->speaker_flags;
2223
2224         /* TODO: We only check for the progressive mode, check for interlace mode too */
2225         if (drm_connector->latency_present[0]) {
2226                 audio_info->video_latency = drm_connector->video_latency[0];
2227                 audio_info->audio_latency = drm_connector->audio_latency[0];
2228         }
2229
2230         /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
2231
2232 }
2233
2234 static void
2235 copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
2236                                       struct drm_display_mode *dst_mode)
2237 {
2238         dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
2239         dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
2240         dst_mode->crtc_clock = src_mode->crtc_clock;
2241         dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
2242         dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
2243         dst_mode->crtc_hsync_start =  src_mode->crtc_hsync_start;
2244         dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
2245         dst_mode->crtc_htotal = src_mode->crtc_htotal;
2246         dst_mode->crtc_hskew = src_mode->crtc_hskew;
2247         dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
2248         dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
2249         dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
2250         dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
2251         dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
2252 }
2253
2254 static void
2255 decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
2256                                         const struct drm_display_mode *native_mode,
2257                                         bool scale_enabled)
2258 {
2259         if (scale_enabled) {
2260                 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
2261         } else if (native_mode->clock == drm_mode->clock &&
2262                         native_mode->htotal == drm_mode->htotal &&
2263                         native_mode->vtotal == drm_mode->vtotal) {
2264                 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
2265         } else {
2266                 /* no scaling nor amdgpu inserted, no need to patch */
2267         }
2268 }
2269
2270 static int create_fake_sink(struct amdgpu_dm_connector *aconnector)
2271 {
2272         struct dc_sink *sink = NULL;
2273         struct dc_sink_init_data sink_init_data = { 0 };
2274
2275         sink_init_data.link = aconnector->dc_link;
2276         sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
2277
2278         sink = dc_sink_create(&sink_init_data);
2279         if (!sink) {
2280                 DRM_ERROR("Failed to create sink!\n");
2281                 return -ENOMEM;
2282         }
2283
2284         sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
2285         aconnector->fake_enable = true;
2286
2287         aconnector->dc_sink = sink;
2288         aconnector->dc_link->local_sink = sink;
2289
2290         return 0;
2291 }
2292
2293 static void set_multisync_trigger_params(
2294                 struct dc_stream_state *stream)
2295 {
2296         if (stream->triggered_crtc_reset.enabled) {
2297                 stream->triggered_crtc_reset.event = CRTC_EVENT_VSYNC_RISING;
2298                 stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_LINE;
2299         }
2300 }
2301
2302 static void set_master_stream(struct dc_stream_state *stream_set[],
2303                               int stream_count)
2304 {
2305         int j, highest_rfr = 0, master_stream = 0;
2306
2307         for (j = 0;  j < stream_count; j++) {
2308                 if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
2309                         int refresh_rate = 0;
2310
2311                         refresh_rate = (stream_set[j]->timing.pix_clk_khz*1000)/
2312                                 (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
2313                         if (refresh_rate > highest_rfr) {
2314                                 highest_rfr = refresh_rate;
2315                                 master_stream = j;
2316                         }
2317                 }
2318         }
2319         for (j = 0;  j < stream_count; j++) {
2320                 if (stream_set[j])
2321                         stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
2322         }
2323 }
2324
2325 static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
2326 {
2327         int i = 0;
2328
2329         if (context->stream_count < 2)
2330                 return;
2331         for (i = 0; i < context->stream_count ; i++) {
2332                 if (!context->streams[i])
2333                         continue;
2334                 /* TODO: add a function to read AMD VSDB bits and will set
2335                  * crtc_sync_master.multi_sync_enabled flag
2336                  * For now its set to false
2337                  */
2338                 set_multisync_trigger_params(context->streams[i]);
2339         }
2340         set_master_stream(context->streams, context->stream_count);
2341 }
2342
2343 static struct dc_stream_state *
2344 create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
2345                        const struct drm_display_mode *drm_mode,
2346                        const struct dm_connector_state *dm_state)
2347 {
2348         struct drm_display_mode *preferred_mode = NULL;
2349         struct drm_connector *drm_connector;
2350         struct dc_stream_state *stream = NULL;
2351         struct drm_display_mode mode = *drm_mode;
2352         bool native_mode_found = false;
2353
2354         if (aconnector == NULL) {
2355                 DRM_ERROR("aconnector is NULL!\n");
2356                 return stream;
2357         }
2358
2359         drm_connector = &aconnector->base;
2360
2361         if (!aconnector->dc_sink) {
2362                 /*
2363                  * Create dc_sink when necessary to MST
2364                  * Don't apply fake_sink to MST
2365                  */
2366                 if (aconnector->mst_port) {
2367                         dm_dp_mst_dc_sink_create(drm_connector);
2368                         return stream;
2369                 }
2370
2371                 if (create_fake_sink(aconnector))
2372                         return stream;
2373         }
2374
2375         stream = dc_create_stream_for_sink(aconnector->dc_sink);
2376
2377         if (stream == NULL) {
2378                 DRM_ERROR("Failed to create stream for sink!\n");
2379                 return stream;
2380         }
2381
2382         list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
2383                 /* Search for preferred mode */
2384                 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
2385                         native_mode_found = true;
2386                         break;
2387                 }
2388         }
2389         if (!native_mode_found)
2390                 preferred_mode = list_first_entry_or_null(
2391                                 &aconnector->base.modes,
2392                                 struct drm_display_mode,
2393                                 head);
2394
2395         if (preferred_mode == NULL) {
2396                 /* This may not be an error, the use case is when we we have no
2397                  * usermode calls to reset and set mode upon hotplug. In this
2398                  * case, we call set mode ourselves to restore the previous mode
2399                  * and the modelist may not be filled in in time.
2400                  */
2401                 DRM_DEBUG_DRIVER("No preferred mode found\n");
2402         } else {
2403                 decide_crtc_timing_for_drm_display_mode(
2404                                 &mode, preferred_mode,
2405                                 dm_state ? (dm_state->scaling != RMX_OFF) : false);
2406         }
2407
2408         if (!dm_state)
2409                 drm_mode_set_crtcinfo(&mode, 0);
2410
2411         fill_stream_properties_from_drm_display_mode(stream,
2412                         &mode, &aconnector->base);
2413         update_stream_scaling_settings(&mode, dm_state, stream);
2414
2415         fill_audio_info(
2416                 &stream->audio_info,
2417                 drm_connector,
2418                 aconnector->dc_sink);
2419
2420         update_stream_signal(stream);
2421
2422         return stream;
2423 }
2424
2425 static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
2426 {
2427         drm_crtc_cleanup(crtc);
2428         kfree(crtc);
2429 }
2430
2431 static void dm_crtc_destroy_state(struct drm_crtc *crtc,
2432                                   struct drm_crtc_state *state)
2433 {
2434         struct dm_crtc_state *cur = to_dm_crtc_state(state);
2435
2436         /* TODO Destroy dc_stream objects are stream object is flattened */
2437         if (cur->stream)
2438                 dc_stream_release(cur->stream);
2439
2440
2441         __drm_atomic_helper_crtc_destroy_state(state);
2442
2443
2444         kfree(state);
2445 }
2446
2447 static void dm_crtc_reset_state(struct drm_crtc *crtc)
2448 {
2449         struct dm_crtc_state *state;
2450
2451         if (crtc->state)
2452                 dm_crtc_destroy_state(crtc, crtc->state);
2453
2454         state = kzalloc(sizeof(*state), GFP_KERNEL);
2455         if (WARN_ON(!state))
2456                 return;
2457
2458         crtc->state = &state->base;
2459         crtc->state->crtc = crtc;
2460
2461 }
2462
2463 static struct drm_crtc_state *
2464 dm_crtc_duplicate_state(struct drm_crtc *crtc)
2465 {
2466         struct dm_crtc_state *state, *cur;
2467
2468         cur = to_dm_crtc_state(crtc->state);
2469
2470         if (WARN_ON(!crtc->state))
2471                 return NULL;
2472
2473         state = kzalloc(sizeof(*state), GFP_KERNEL);
2474         if (!state)
2475                 return NULL;
2476
2477         __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
2478
2479         if (cur->stream) {
2480                 state->stream = cur->stream;
2481                 dc_stream_retain(state->stream);
2482         }
2483
2484         /* TODO Duplicate dc_stream after objects are stream object is flattened */
2485
2486         return &state->base;
2487 }
2488
2489 /* Implemented only the options currently availible for the driver */
2490 static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
2491         .reset = dm_crtc_reset_state,
2492         .destroy = amdgpu_dm_crtc_destroy,
2493         .gamma_set = drm_atomic_helper_legacy_gamma_set,
2494         .set_config = drm_atomic_helper_set_config,
2495         .page_flip = drm_atomic_helper_page_flip,
2496         .atomic_duplicate_state = dm_crtc_duplicate_state,
2497         .atomic_destroy_state = dm_crtc_destroy_state,
2498         .set_crc_source = amdgpu_dm_crtc_set_crc_source,
2499 };
2500
2501 static enum drm_connector_status
2502 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
2503 {
2504         bool connected;
2505         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
2506
2507         /* Notes:
2508          * 1. This interface is NOT called in context of HPD irq.
2509          * 2. This interface *is called* in context of user-mode ioctl. Which
2510          * makes it a bad place for *any* MST-related activit. */
2511
2512         if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
2513             !aconnector->fake_enable)
2514                 connected = (aconnector->dc_sink != NULL);
2515         else
2516                 connected = (aconnector->base.force == DRM_FORCE_ON);
2517
2518         return (connected ? connector_status_connected :
2519                         connector_status_disconnected);
2520 }
2521
2522 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
2523                                             struct drm_connector_state *connector_state,
2524                                             struct drm_property *property,
2525                                             uint64_t val)
2526 {
2527         struct drm_device *dev = connector->dev;
2528         struct amdgpu_device *adev = dev->dev_private;
2529         struct dm_connector_state *dm_old_state =
2530                 to_dm_connector_state(connector->state);
2531         struct dm_connector_state *dm_new_state =
2532                 to_dm_connector_state(connector_state);
2533
2534         int ret = -EINVAL;
2535
2536         if (property == dev->mode_config.scaling_mode_property) {
2537                 enum amdgpu_rmx_type rmx_type;
2538
2539                 switch (val) {
2540                 case DRM_MODE_SCALE_CENTER:
2541                         rmx_type = RMX_CENTER;
2542                         break;
2543                 case DRM_MODE_SCALE_ASPECT:
2544                         rmx_type = RMX_ASPECT;
2545                         break;
2546                 case DRM_MODE_SCALE_FULLSCREEN:
2547                         rmx_type = RMX_FULL;
2548                         break;
2549                 case DRM_MODE_SCALE_NONE:
2550                 default:
2551                         rmx_type = RMX_OFF;
2552                         break;
2553                 }
2554
2555                 if (dm_old_state->scaling == rmx_type)
2556                         return 0;
2557
2558                 dm_new_state->scaling = rmx_type;
2559                 ret = 0;
2560         } else if (property == adev->mode_info.underscan_hborder_property) {
2561                 dm_new_state->underscan_hborder = val;
2562                 ret = 0;
2563         } else if (property == adev->mode_info.underscan_vborder_property) {
2564                 dm_new_state->underscan_vborder = val;
2565                 ret = 0;
2566         } else if (property == adev->mode_info.underscan_property) {
2567                 dm_new_state->underscan_enable = val;
2568                 ret = 0;
2569         }
2570
2571         return ret;
2572 }
2573
2574 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
2575                                             const struct drm_connector_state *state,
2576                                             struct drm_property *property,
2577                                             uint64_t *val)
2578 {
2579         struct drm_device *dev = connector->dev;
2580         struct amdgpu_device *adev = dev->dev_private;
2581         struct dm_connector_state *dm_state =
2582                 to_dm_connector_state(state);
2583         int ret = -EINVAL;
2584
2585         if (property == dev->mode_config.scaling_mode_property) {
2586                 switch (dm_state->scaling) {
2587                 case RMX_CENTER:
2588                         *val = DRM_MODE_SCALE_CENTER;
2589                         break;
2590                 case RMX_ASPECT:
2591                         *val = DRM_MODE_SCALE_ASPECT;
2592                         break;
2593                 case RMX_FULL:
2594                         *val = DRM_MODE_SCALE_FULLSCREEN;
2595                         break;
2596                 case RMX_OFF:
2597                 default:
2598                         *val = DRM_MODE_SCALE_NONE;
2599                         break;
2600                 }
2601                 ret = 0;
2602         } else if (property == adev->mode_info.underscan_hborder_property) {
2603                 *val = dm_state->underscan_hborder;
2604                 ret = 0;
2605         } else if (property == adev->mode_info.underscan_vborder_property) {
2606                 *val = dm_state->underscan_vborder;
2607                 ret = 0;
2608         } else if (property == adev->mode_info.underscan_property) {
2609                 *val = dm_state->underscan_enable;
2610                 ret = 0;
2611         }
2612         return ret;
2613 }
2614
2615 static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
2616 {
2617         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
2618         const struct dc_link *link = aconnector->dc_link;
2619         struct amdgpu_device *adev = connector->dev->dev_private;
2620         struct amdgpu_display_manager *dm = &adev->dm;
2621 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
2622         defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
2623
2624         if (link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) {
2625                 amdgpu_dm_register_backlight_device(dm);
2626
2627                 if (dm->backlight_dev) {
2628                         backlight_device_unregister(dm->backlight_dev);
2629                         dm->backlight_dev = NULL;
2630                 }
2631
2632         }
2633 #endif
2634         drm_connector_unregister(connector);
2635         drm_connector_cleanup(connector);
2636         kfree(connector);
2637 }
2638
2639 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
2640 {
2641         struct dm_connector_state *state =
2642                 to_dm_connector_state(connector->state);
2643
2644         kfree(state);
2645
2646         state = kzalloc(sizeof(*state), GFP_KERNEL);
2647
2648         if (state) {
2649                 state->scaling = RMX_OFF;
2650                 state->underscan_enable = false;
2651                 state->underscan_hborder = 0;
2652                 state->underscan_vborder = 0;
2653
2654                 connector->state = &state->base;
2655                 connector->state->connector = connector;
2656         }
2657 }
2658
2659 struct drm_connector_state *
2660 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
2661 {
2662         struct dm_connector_state *state =
2663                 to_dm_connector_state(connector->state);
2664
2665         struct dm_connector_state *new_state =
2666                         kmemdup(state, sizeof(*state), GFP_KERNEL);
2667
2668         if (new_state) {
2669                 __drm_atomic_helper_connector_duplicate_state(connector,
2670                                                               &new_state->base);
2671                 return &new_state->base;
2672         }
2673
2674         return NULL;
2675 }
2676
2677 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
2678         .reset = amdgpu_dm_connector_funcs_reset,
2679         .detect = amdgpu_dm_connector_detect,
2680         .fill_modes = drm_helper_probe_single_connector_modes,
2681         .destroy = amdgpu_dm_connector_destroy,
2682         .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
2683         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2684         .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
2685         .atomic_get_property = amdgpu_dm_connector_atomic_get_property
2686 };
2687
2688 static struct drm_encoder *best_encoder(struct drm_connector *connector)
2689 {
2690         int enc_id = connector->encoder_ids[0];
2691         struct drm_mode_object *obj;
2692         struct drm_encoder *encoder;
2693
2694         DRM_DEBUG_DRIVER("Finding the best encoder\n");
2695
2696         /* pick the encoder ids */
2697         if (enc_id) {
2698                 obj = drm_mode_object_find(connector->dev, NULL, enc_id, DRM_MODE_OBJECT_ENCODER);
2699                 if (!obj) {
2700                         DRM_ERROR("Couldn't find a matching encoder for our connector\n");
2701                         return NULL;
2702                 }
2703                 encoder = obj_to_encoder(obj);
2704                 return encoder;
2705         }
2706         DRM_ERROR("No encoder id\n");
2707         return NULL;
2708 }
2709
2710 static int get_modes(struct drm_connector *connector)
2711 {
2712         return amdgpu_dm_connector_get_modes(connector);
2713 }
2714
2715 static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
2716 {
2717         struct dc_sink_init_data init_params = {
2718                         .link = aconnector->dc_link,
2719                         .sink_signal = SIGNAL_TYPE_VIRTUAL
2720         };
2721         struct edid *edid;
2722
2723         if (!aconnector->base.edid_blob_ptr) {
2724                 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
2725                                 aconnector->base.name);
2726
2727                 aconnector->base.force = DRM_FORCE_OFF;
2728                 aconnector->base.override_edid = false;
2729                 return;
2730         }
2731
2732         edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
2733
2734         aconnector->edid = edid;
2735
2736         aconnector->dc_em_sink = dc_link_add_remote_sink(
2737                 aconnector->dc_link,
2738                 (uint8_t *)edid,
2739                 (edid->extensions + 1) * EDID_LENGTH,
2740                 &init_params);
2741
2742         if (aconnector->base.force == DRM_FORCE_ON)
2743                 aconnector->dc_sink = aconnector->dc_link->local_sink ?
2744                 aconnector->dc_link->local_sink :
2745                 aconnector->dc_em_sink;
2746 }
2747
2748 static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
2749 {
2750         struct dc_link *link = (struct dc_link *)aconnector->dc_link;
2751
2752         /* In case of headless boot with force on for DP managed connector
2753          * Those settings have to be != 0 to get initial modeset
2754          */
2755         if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
2756                 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
2757                 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
2758         }
2759
2760
2761         aconnector->base.override_edid = true;
2762         create_eml_sink(aconnector);
2763 }
2764
2765 int amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
2766                                    struct drm_display_mode *mode)
2767 {
2768         int result = MODE_ERROR;
2769         struct dc_sink *dc_sink;
2770         struct amdgpu_device *adev = connector->dev->dev_private;
2771         /* TODO: Unhardcode stream count */
2772         struct dc_stream_state *stream;
2773         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
2774         enum dc_status dc_result = DC_OK;
2775
2776         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
2777                         (mode->flags & DRM_MODE_FLAG_DBLSCAN))
2778                 return result;
2779
2780         /* Only run this the first time mode_valid is called to initilialize
2781          * EDID mgmt
2782          */
2783         if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
2784                 !aconnector->dc_em_sink)
2785                 handle_edid_mgmt(aconnector);
2786
2787         dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
2788
2789         if (dc_sink == NULL) {
2790                 DRM_ERROR("dc_sink is NULL!\n");
2791                 goto fail;
2792         }
2793
2794         stream = create_stream_for_sink(aconnector, mode, NULL);
2795         if (stream == NULL) {
2796                 DRM_ERROR("Failed to create stream for sink!\n");
2797                 goto fail;
2798         }
2799
2800         dc_result = dc_validate_stream(adev->dm.dc, stream);
2801
2802         if (dc_result == DC_OK)
2803                 result = MODE_OK;
2804         else
2805                 DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d\n",
2806                               mode->vdisplay,
2807                               mode->hdisplay,
2808                               mode->clock,
2809                               dc_result);
2810
2811         dc_stream_release(stream);
2812
2813 fail:
2814         /* TODO: error handling*/
2815         return result;
2816 }
2817
2818 static const struct drm_connector_helper_funcs
2819 amdgpu_dm_connector_helper_funcs = {
2820         /*
2821          * If hotplug a second bigger display in FB Con mode, bigger resolution
2822          * modes will be filtered by drm_mode_validate_size(), and those modes
2823          * is missing after user start lightdm. So we need to renew modes list.
2824          * in get_modes call back, not just return the modes count
2825          */
2826         .get_modes = get_modes,
2827         .mode_valid = amdgpu_dm_connector_mode_valid,
2828         .best_encoder = best_encoder
2829 };
2830
2831 static void dm_crtc_helper_disable(struct drm_crtc *crtc)
2832 {
2833 }
2834
2835 static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc,
2836                                        struct drm_crtc_state *state)
2837 {
2838         struct amdgpu_device *adev = crtc->dev->dev_private;
2839         struct dc *dc = adev->dm.dc;
2840         struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(state);
2841         int ret = -EINVAL;
2842
2843         if (unlikely(!dm_crtc_state->stream &&
2844                      modeset_required(state, NULL, dm_crtc_state->stream))) {
2845                 WARN_ON(1);
2846                 return ret;
2847         }
2848
2849         /* In some use cases, like reset, no stream  is attached */
2850         if (!dm_crtc_state->stream)
2851                 return 0;
2852
2853         if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK)
2854                 return 0;
2855
2856         return ret;
2857 }
2858
2859 static bool dm_crtc_helper_mode_fixup(struct drm_crtc *crtc,
2860                                       const struct drm_display_mode *mode,
2861                                       struct drm_display_mode *adjusted_mode)
2862 {
2863         return true;
2864 }
2865
2866 static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = {
2867         .disable = dm_crtc_helper_disable,
2868         .atomic_check = dm_crtc_helper_atomic_check,
2869         .mode_fixup = dm_crtc_helper_mode_fixup
2870 };
2871
2872 static void dm_encoder_helper_disable(struct drm_encoder *encoder)
2873 {
2874
2875 }
2876
2877 static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
2878                                           struct drm_crtc_state *crtc_state,
2879                                           struct drm_connector_state *conn_state)
2880 {
2881         return 0;
2882 }
2883
2884 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
2885         .disable = dm_encoder_helper_disable,
2886         .atomic_check = dm_encoder_helper_atomic_check
2887 };
2888
2889 static void dm_drm_plane_reset(struct drm_plane *plane)
2890 {
2891         struct dm_plane_state *amdgpu_state = NULL;
2892
2893         if (plane->state)
2894                 plane->funcs->atomic_destroy_state(plane, plane->state);
2895
2896         amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL);
2897         WARN_ON(amdgpu_state == NULL);
2898
2899         if (amdgpu_state) {
2900                 plane->state = &amdgpu_state->base;
2901                 plane->state->plane = plane;
2902                 plane->state->rotation = DRM_MODE_ROTATE_0;
2903         }
2904 }
2905
2906 static struct drm_plane_state *
2907 dm_drm_plane_duplicate_state(struct drm_plane *plane)
2908 {
2909         struct dm_plane_state *dm_plane_state, *old_dm_plane_state;
2910
2911         old_dm_plane_state = to_dm_plane_state(plane->state);
2912         dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL);
2913         if (!dm_plane_state)
2914                 return NULL;
2915
2916         __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base);
2917
2918         if (old_dm_plane_state->dc_state) {
2919                 dm_plane_state->dc_state = old_dm_plane_state->dc_state;
2920                 dc_plane_state_retain(dm_plane_state->dc_state);
2921         }
2922
2923         return &dm_plane_state->base;
2924 }
2925
2926 void dm_drm_plane_destroy_state(struct drm_plane *plane,
2927                                 struct drm_plane_state *state)
2928 {
2929         struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
2930
2931         if (dm_plane_state->dc_state)
2932                 dc_plane_state_release(dm_plane_state->dc_state);
2933
2934         drm_atomic_helper_plane_destroy_state(plane, state);
2935 }
2936
2937 static const struct drm_plane_funcs dm_plane_funcs = {
2938         .update_plane   = drm_atomic_helper_update_plane,
2939         .disable_plane  = drm_atomic_helper_disable_plane,
2940         .destroy        = drm_plane_cleanup,
2941         .reset = dm_drm_plane_reset,
2942         .atomic_duplicate_state = dm_drm_plane_duplicate_state,
2943         .atomic_destroy_state = dm_drm_plane_destroy_state,
2944 };
2945
2946 static int dm_plane_helper_prepare_fb(struct drm_plane *plane,
2947                                       struct drm_plane_state *new_state)
2948 {
2949         struct amdgpu_framebuffer *afb;
2950         struct drm_gem_object *obj;
2951         struct amdgpu_device *adev;
2952         struct amdgpu_bo *rbo;
2953         uint64_t chroma_addr = 0;
2954         struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old;
2955         unsigned int awidth;
2956         uint32_t domain;
2957         int r;
2958
2959         dm_plane_state_old = to_dm_plane_state(plane->state);
2960         dm_plane_state_new = to_dm_plane_state(new_state);
2961
2962         if (!new_state->fb) {
2963                 DRM_DEBUG_DRIVER("No FB bound\n");
2964                 return 0;
2965         }
2966
2967         afb = to_amdgpu_framebuffer(new_state->fb);
2968
2969         obj = afb->obj;
2970         rbo = gem_to_amdgpu_bo(obj);
2971         adev = amdgpu_ttm_adev(rbo->tbo.bdev);
2972         r = amdgpu_bo_reserve(rbo, false);
2973         if (unlikely(r != 0))
2974                 return r;
2975
2976         if (plane->type != DRM_PLANE_TYPE_CURSOR)
2977                 domain = amdgpu_display_framebuffer_domains(adev);
2978         else
2979                 domain = AMDGPU_GEM_DOMAIN_VRAM;
2980
2981         r = amdgpu_bo_pin(rbo, domain, &afb->address);
2982
2983         amdgpu_bo_unreserve(rbo);
2984
2985         if (unlikely(r != 0)) {
2986                 if (r != -ERESTARTSYS)
2987                         DRM_ERROR("Failed to pin framebuffer with error %d\n", r);
2988                 return r;
2989         }
2990
2991         amdgpu_bo_ref(rbo);
2992
2993         if (dm_plane_state_new->dc_state &&
2994                         dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) {
2995                 struct dc_plane_state *plane_state = dm_plane_state_new->dc_state;
2996
2997                 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
2998                         plane_state->address.grph.addr.low_part = lower_32_bits(afb->address);
2999                         plane_state->address.grph.addr.high_part = upper_32_bits(afb->address);
3000                 } else {
3001                         awidth = ALIGN(new_state->fb->width, 64);
3002                         plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
3003                         plane_state->address.video_progressive.luma_addr.low_part
3004                                                         = lower_32_bits(afb->address);
3005                         plane_state->address.video_progressive.luma_addr.high_part
3006                                                         = upper_32_bits(afb->address);
3007                         chroma_addr = afb->address + (u64)awidth * new_state->fb->height;
3008                         plane_state->address.video_progressive.chroma_addr.low_part
3009                                                         = lower_32_bits(chroma_addr);
3010                         plane_state->address.video_progressive.chroma_addr.high_part
3011                                                         = upper_32_bits(chroma_addr);
3012                 }
3013         }
3014
3015         /* It's a hack for s3 since in 4.9 kernel filter out cursor buffer
3016          * prepare and cleanup in drm_atomic_helper_prepare_planes
3017          * and drm_atomic_helper_cleanup_planes because fb doens't in s3.
3018          * IN 4.10 kernel this code should be removed and amdgpu_device_suspend
3019          * code touching fram buffers should be avoided for DC.
3020          */
3021         if (plane->type == DRM_PLANE_TYPE_CURSOR) {
3022                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_state->crtc);
3023
3024                 acrtc->cursor_bo = obj;
3025         }
3026         return 0;
3027 }
3028
3029 static void dm_plane_helper_cleanup_fb(struct drm_plane *plane,
3030                                        struct drm_plane_state *old_state)
3031 {
3032         struct amdgpu_bo *rbo;
3033         struct amdgpu_framebuffer *afb;
3034         int r;
3035
3036         if (!old_state->fb)
3037                 return;
3038
3039         afb = to_amdgpu_framebuffer(old_state->fb);
3040         rbo = gem_to_amdgpu_bo(afb->obj);
3041         r = amdgpu_bo_reserve(rbo, false);
3042         if (unlikely(r)) {
3043                 DRM_ERROR("failed to reserve rbo before unpin\n");
3044                 return;
3045         }
3046
3047         amdgpu_bo_unpin(rbo);
3048         amdgpu_bo_unreserve(rbo);
3049         amdgpu_bo_unref(&rbo);
3050 }
3051
3052 static int dm_plane_atomic_check(struct drm_plane *plane,
3053                                  struct drm_plane_state *state)
3054 {
3055         struct amdgpu_device *adev = plane->dev->dev_private;
3056         struct dc *dc = adev->dm.dc;
3057         struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
3058
3059         if (!dm_plane_state->dc_state)
3060                 return 0;
3061
3062         if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK)
3063                 return 0;
3064
3065         return -EINVAL;
3066 }
3067
3068 static const struct drm_plane_helper_funcs dm_plane_helper_funcs = {
3069         .prepare_fb = dm_plane_helper_prepare_fb,
3070         .cleanup_fb = dm_plane_helper_cleanup_fb,
3071         .atomic_check = dm_plane_atomic_check,
3072 };
3073
3074 /*
3075  * TODO: these are currently initialized to rgb formats only.
3076  * For future use cases we should either initialize them dynamically based on
3077  * plane capabilities, or initialize this array to all formats, so internal drm
3078  * check will succeed, and let DC to implement proper check
3079  */
3080 static const uint32_t rgb_formats[] = {
3081         DRM_FORMAT_RGB888,
3082         DRM_FORMAT_XRGB8888,
3083         DRM_FORMAT_ARGB8888,
3084         DRM_FORMAT_RGBA8888,
3085         DRM_FORMAT_XRGB2101010,
3086         DRM_FORMAT_XBGR2101010,
3087         DRM_FORMAT_ARGB2101010,
3088         DRM_FORMAT_ABGR2101010,
3089 };
3090
3091 static const uint32_t yuv_formats[] = {
3092         DRM_FORMAT_NV12,
3093         DRM_FORMAT_NV21,
3094 };
3095
3096 static const u32 cursor_formats[] = {
3097         DRM_FORMAT_ARGB8888
3098 };
3099
3100 static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
3101                                 struct amdgpu_plane *aplane,
3102                                 unsigned long possible_crtcs)
3103 {
3104         int res = -EPERM;
3105
3106         switch (aplane->base.type) {
3107         case DRM_PLANE_TYPE_PRIMARY:
3108                 aplane->base.format_default = true;
3109
3110                 res = drm_universal_plane_init(
3111                                 dm->adev->ddev,
3112                                 &aplane->base,
3113                                 possible_crtcs,
3114                                 &dm_plane_funcs,
3115                                 rgb_formats,
3116                                 ARRAY_SIZE(rgb_formats),
3117                                 NULL, aplane->base.type, NULL);
3118                 break;
3119         case DRM_PLANE_TYPE_OVERLAY:
3120                 res = drm_universal_plane_init(
3121                                 dm->adev->ddev,
3122                                 &aplane->base,
3123                                 possible_crtcs,
3124                                 &dm_plane_funcs,
3125                                 yuv_formats,
3126                                 ARRAY_SIZE(yuv_formats),
3127                                 NULL, aplane->base.type, NULL);
3128                 break;
3129         case DRM_PLANE_TYPE_CURSOR:
3130                 res = drm_universal_plane_init(
3131                                 dm->adev->ddev,
3132                                 &aplane->base,
3133                                 possible_crtcs,
3134                                 &dm_plane_funcs,
3135                                 cursor_formats,
3136                                 ARRAY_SIZE(cursor_formats),
3137                                 NULL, aplane->base.type, NULL);
3138                 break;
3139         }
3140
3141         drm_plane_helper_add(&aplane->base, &dm_plane_helper_funcs);
3142
3143         /* Create (reset) the plane state */
3144         if (aplane->base.funcs->reset)
3145                 aplane->base.funcs->reset(&aplane->base);
3146
3147
3148         return res;
3149 }
3150
3151 static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
3152                                struct drm_plane *plane,
3153                                uint32_t crtc_index)
3154 {
3155         struct amdgpu_crtc *acrtc = NULL;
3156         struct amdgpu_plane *cursor_plane;
3157
3158         int res = -ENOMEM;
3159
3160         cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL);
3161         if (!cursor_plane)
3162                 goto fail;
3163
3164         cursor_plane->base.type = DRM_PLANE_TYPE_CURSOR;
3165         res = amdgpu_dm_plane_init(dm, cursor_plane, 0);
3166
3167         acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
3168         if (!acrtc)
3169                 goto fail;
3170
3171         res = drm_crtc_init_with_planes(
3172                         dm->ddev,
3173                         &acrtc->base,
3174                         plane,
3175                         &cursor_plane->base,
3176                         &amdgpu_dm_crtc_funcs, NULL);
3177
3178         if (res)
3179                 goto fail;
3180
3181         drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs);
3182
3183         /* Create (reset) the plane state */
3184         if (acrtc->base.funcs->reset)
3185                 acrtc->base.funcs->reset(&acrtc->base);
3186
3187         acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;
3188         acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;
3189
3190         acrtc->crtc_id = crtc_index;
3191         acrtc->base.enabled = false;
3192
3193         dm->adev->mode_info.crtcs[crtc_index] = acrtc;
3194         drm_crtc_enable_color_mgmt(&acrtc->base, MAX_COLOR_LUT_ENTRIES,
3195                                    true, MAX_COLOR_LUT_ENTRIES);
3196         drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LUT_ENTRIES);
3197
3198         return 0;
3199
3200 fail:
3201         kfree(acrtc);
3202         kfree(cursor_plane);
3203         return res;
3204 }
3205
3206
3207 static int to_drm_connector_type(enum signal_type st)
3208 {
3209         switch (st) {
3210         case SIGNAL_TYPE_HDMI_TYPE_A:
3211                 return DRM_MODE_CONNECTOR_HDMIA;
3212         case SIGNAL_TYPE_EDP:
3213                 return DRM_MODE_CONNECTOR_eDP;
3214         case SIGNAL_TYPE_RGB:
3215                 return DRM_MODE_CONNECTOR_VGA;
3216         case SIGNAL_TYPE_DISPLAY_PORT:
3217         case SIGNAL_TYPE_DISPLAY_PORT_MST:
3218                 return DRM_MODE_CONNECTOR_DisplayPort;
3219         case SIGNAL_TYPE_DVI_DUAL_LINK:
3220         case SIGNAL_TYPE_DVI_SINGLE_LINK:
3221                 return DRM_MODE_CONNECTOR_DVID;
3222         case SIGNAL_TYPE_VIRTUAL:
3223                 return DRM_MODE_CONNECTOR_VIRTUAL;
3224
3225         default:
3226                 return DRM_MODE_CONNECTOR_Unknown;
3227         }
3228 }
3229
3230 static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
3231 {
3232         const struct drm_connector_helper_funcs *helper =
3233                 connector->helper_private;
3234         struct drm_encoder *encoder;
3235         struct amdgpu_encoder *amdgpu_encoder;
3236
3237         encoder = helper->best_encoder(connector);
3238
3239         if (encoder == NULL)
3240                 return;
3241
3242         amdgpu_encoder = to_amdgpu_encoder(encoder);
3243
3244         amdgpu_encoder->native_mode.clock = 0;
3245
3246         if (!list_empty(&connector->probed_modes)) {
3247                 struct drm_display_mode *preferred_mode = NULL;
3248
3249                 list_for_each_entry(preferred_mode,
3250                                     &connector->probed_modes,
3251                                     head) {
3252                         if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
3253                                 amdgpu_encoder->native_mode = *preferred_mode;
3254
3255                         break;
3256                 }
3257
3258         }
3259 }
3260
3261 static struct drm_display_mode *
3262 amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
3263                              char *name,
3264                              int hdisplay, int vdisplay)
3265 {
3266         struct drm_device *dev = encoder->dev;
3267         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3268         struct drm_display_mode *mode = NULL;
3269         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
3270
3271         mode = drm_mode_duplicate(dev, native_mode);
3272
3273         if (mode == NULL)
3274                 return NULL;
3275
3276         mode->hdisplay = hdisplay;
3277         mode->vdisplay = vdisplay;
3278         mode->type &= ~DRM_MODE_TYPE_PREFERRED;
3279         strncpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
3280
3281         return mode;
3282
3283 }
3284
3285 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
3286                                                  struct drm_connector *connector)
3287 {
3288         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3289         struct drm_display_mode *mode = NULL;
3290         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
3291         struct amdgpu_dm_connector *amdgpu_dm_connector =
3292                                 to_amdgpu_dm_connector(connector);
3293         int i;
3294         int n;
3295         struct mode_size {
3296                 char name[DRM_DISPLAY_MODE_LEN];
3297                 int w;
3298                 int h;
3299         } common_modes[] = {
3300                 {  "640x480",  640,  480},
3301                 {  "800x600",  800,  600},
3302                 { "1024x768", 1024,  768},
3303                 { "1280x720", 1280,  720},
3304                 { "1280x800", 1280,  800},
3305                 {"1280x1024", 1280, 1024},
3306                 { "1440x900", 1440,  900},
3307                 {"1680x1050", 1680, 1050},
3308                 {"1600x1200", 1600, 1200},
3309                 {"1920x1080", 1920, 1080},
3310                 {"1920x1200", 1920, 1200}
3311         };
3312
3313         n = ARRAY_SIZE(common_modes);
3314
3315         for (i = 0; i < n; i++) {
3316                 struct drm_display_mode *curmode = NULL;
3317                 bool mode_existed = false;
3318
3319                 if (common_modes[i].w > native_mode->hdisplay ||
3320                     common_modes[i].h > native_mode->vdisplay ||
3321                    (common_modes[i].w == native_mode->hdisplay &&
3322                     common_modes[i].h == native_mode->vdisplay))
3323                         continue;
3324
3325                 list_for_each_entry(curmode, &connector->probed_modes, head) {
3326                         if (common_modes[i].w == curmode->hdisplay &&
3327                             common_modes[i].h == curmode->vdisplay) {
3328                                 mode_existed = true;
3329                                 break;
3330                         }
3331                 }
3332
3333                 if (mode_existed)
3334                         continue;
3335
3336                 mode = amdgpu_dm_create_common_mode(encoder,
3337                                 common_modes[i].name, common_modes[i].w,
3338                                 common_modes[i].h);
3339                 drm_mode_probed_add(connector, mode);
3340                 amdgpu_dm_connector->num_modes++;
3341         }
3342 }
3343
3344 static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
3345                                               struct edid *edid)
3346 {
3347         struct amdgpu_dm_connector *amdgpu_dm_connector =
3348                         to_amdgpu_dm_connector(connector);
3349
3350         if (edid) {
3351                 /* empty probed_modes */
3352                 INIT_LIST_HEAD(&connector->probed_modes);
3353                 amdgpu_dm_connector->num_modes =
3354                                 drm_add_edid_modes(connector, edid);
3355
3356                 amdgpu_dm_get_native_mode(connector);
3357         } else {
3358                 amdgpu_dm_connector->num_modes = 0;
3359         }
3360 }
3361
3362 static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
3363 {
3364         const struct drm_connector_helper_funcs *helper =
3365                         connector->helper_private;
3366         struct amdgpu_dm_connector *amdgpu_dm_connector =
3367                         to_amdgpu_dm_connector(connector);
3368         struct drm_encoder *encoder;
3369         struct edid *edid = amdgpu_dm_connector->edid;
3370
3371         encoder = helper->best_encoder(connector);
3372         amdgpu_dm_connector_ddc_get_modes(connector, edid);
3373         amdgpu_dm_connector_add_common_modes(encoder, connector);
3374
3375 #if defined(CONFIG_DRM_AMD_DC_FBC)
3376         amdgpu_dm_fbc_init(connector);
3377 #endif
3378         return amdgpu_dm_connector->num_modes;
3379 }
3380
3381 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
3382                                      struct amdgpu_dm_connector *aconnector,
3383                                      int connector_type,
3384                                      struct dc_link *link,
3385                                      int link_index)
3386 {
3387         struct amdgpu_device *adev = dm->ddev->dev_private;
3388
3389         aconnector->connector_id = link_index;
3390         aconnector->dc_link = link;
3391         aconnector->base.interlace_allowed = false;
3392         aconnector->base.doublescan_allowed = false;
3393         aconnector->base.stereo_allowed = false;
3394         aconnector->base.dpms = DRM_MODE_DPMS_OFF;
3395         aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
3396
3397         mutex_init(&aconnector->hpd_lock);
3398
3399         /* configure support HPD hot plug connector_>polled default value is 0
3400          * which means HPD hot plug not supported
3401          */
3402         switch (connector_type) {
3403         case DRM_MODE_CONNECTOR_HDMIA:
3404                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
3405                 break;
3406         case DRM_MODE_CONNECTOR_DisplayPort:
3407                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
3408                 break;
3409         case DRM_MODE_CONNECTOR_DVID:
3410                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
3411                 break;
3412         default:
3413                 break;
3414         }
3415
3416         drm_object_attach_property(&aconnector->base.base,
3417                                 dm->ddev->mode_config.scaling_mode_property,
3418                                 DRM_MODE_SCALE_NONE);
3419
3420         drm_object_attach_property(&aconnector->base.base,
3421                                 adev->mode_info.underscan_property,
3422                                 UNDERSCAN_OFF);
3423         drm_object_attach_property(&aconnector->base.base,
3424                                 adev->mode_info.underscan_hborder_property,
3425                                 0);
3426         drm_object_attach_property(&aconnector->base.base,
3427                                 adev->mode_info.underscan_vborder_property,
3428                                 0);
3429
3430 }
3431
3432 static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
3433                               struct i2c_msg *msgs, int num)
3434 {
3435         struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
3436         struct ddc_service *ddc_service = i2c->ddc_service;
3437         struct i2c_command cmd;
3438         int i;
3439         int result = -EIO;
3440
3441         cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
3442
3443         if (!cmd.payloads)
3444                 return result;
3445
3446         cmd.number_of_payloads = num;
3447         cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
3448         cmd.speed = 100;
3449
3450         for (i = 0; i < num; i++) {
3451                 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
3452                 cmd.payloads[i].address = msgs[i].addr;
3453                 cmd.payloads[i].length = msgs[i].len;
3454                 cmd.payloads[i].data = msgs[i].buf;
3455         }
3456
3457         if (dal_i2caux_submit_i2c_command(
3458                         ddc_service->ctx->i2caux,
3459                         ddc_service->ddc_pin,
3460                         &cmd))
3461                 result = num;
3462
3463         kfree(cmd.payloads);
3464         return result;
3465 }
3466
3467 static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
3468 {
3469         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
3470 }
3471
3472 static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
3473         .master_xfer = amdgpu_dm_i2c_xfer,
3474         .functionality = amdgpu_dm_i2c_func,
3475 };
3476
3477 static struct amdgpu_i2c_adapter *
3478 create_i2c(struct ddc_service *ddc_service,
3479            int link_index,
3480            int *res)
3481 {
3482         struct amdgpu_device *adev = ddc_service->ctx->driver_context;
3483         struct amdgpu_i2c_adapter *i2c;
3484
3485         i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
3486         if (!i2c)
3487                 return NULL;
3488         i2c->base.owner = THIS_MODULE;
3489         i2c->base.class = I2C_CLASS_DDC;
3490         i2c->base.dev.parent = &adev->pdev->dev;
3491         i2c->base.algo = &amdgpu_dm_i2c_algo;
3492         snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
3493         i2c_set_adapdata(&i2c->base, i2c);
3494         i2c->ddc_service = ddc_service;
3495
3496         return i2c;
3497 }
3498
3499 /* Note: this function assumes that dc_link_detect() was called for the
3500  * dc_link which will be represented by this aconnector.
3501  */
3502 static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
3503                                     struct amdgpu_dm_connector *aconnector,
3504                                     uint32_t link_index,
3505                                     struct amdgpu_encoder *aencoder)
3506 {
3507         int res = 0;
3508         int connector_type;
3509         struct dc *dc = dm->dc;
3510         struct dc_link *link = dc_get_link_at_index(dc, link_index);
3511         struct amdgpu_i2c_adapter *i2c;
3512
3513         link->priv = aconnector;
3514
3515         DRM_DEBUG_DRIVER("%s()\n", __func__);
3516
3517         i2c = create_i2c(link->ddc, link->link_index, &res);
3518         if (!i2c) {
3519                 DRM_ERROR("Failed to create i2c adapter data\n");
3520                 return -ENOMEM;
3521         }
3522
3523         aconnector->i2c = i2c;
3524         res = i2c_add_adapter(&i2c->base);
3525
3526         if (res) {
3527                 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
3528                 goto out_free;
3529         }
3530
3531         connector_type = to_drm_connector_type(link->connector_signal);
3532
3533         res = drm_connector_init(
3534                         dm->ddev,
3535                         &aconnector->base,
3536                         &amdgpu_dm_connector_funcs,
3537                         connector_type);
3538
3539         if (res) {
3540                 DRM_ERROR("connector_init failed\n");
3541                 aconnector->connector_id = -1;
3542                 goto out_free;
3543         }
3544
3545         drm_connector_helper_add(
3546                         &aconnector->base,
3547                         &amdgpu_dm_connector_helper_funcs);
3548
3549         if (aconnector->base.funcs->reset)
3550                 aconnector->base.funcs->reset(&aconnector->base);
3551
3552         amdgpu_dm_connector_init_helper(
3553                 dm,
3554                 aconnector,
3555                 connector_type,
3556                 link,
3557                 link_index);
3558
3559         drm_mode_connector_attach_encoder(
3560                 &aconnector->base, &aencoder->base);
3561
3562         drm_connector_register(&aconnector->base);
3563
3564         if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
3565                 || connector_type == DRM_MODE_CONNECTOR_eDP)
3566                 amdgpu_dm_initialize_dp_connector(dm, aconnector);
3567
3568 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
3569         defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
3570
3571         /* NOTE: this currently will create backlight device even if a panel
3572          * is not connected to the eDP/LVDS connector.
3573          *
3574          * This is less than ideal but we don't have sink information at this
3575          * stage since detection happens after. We can't do detection earlier
3576          * since MST detection needs connectors to be created first.
3577          */
3578         if (link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) {
3579                 /* Event if registration failed, we should continue with
3580                  * DM initialization because not having a backlight control
3581                  * is better then a black screen.
3582                  */
3583                 amdgpu_dm_register_backlight_device(dm);
3584
3585                 if (dm->backlight_dev)
3586                         dm->backlight_link = link;
3587         }
3588 #endif
3589
3590 out_free:
3591         if (res) {
3592                 kfree(i2c);
3593                 aconnector->i2c = NULL;
3594         }
3595         return res;
3596 }
3597
3598 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
3599 {
3600         switch (adev->mode_info.num_crtc) {
3601         case 1:
3602                 return 0x1;
3603         case 2:
3604                 return 0x3;
3605         case 3:
3606                 return 0x7;
3607         case 4:
3608                 return 0xf;
3609         case 5:
3610                 return 0x1f;
3611         case 6:
3612         default:
3613                 return 0x3f;
3614         }
3615 }
3616
3617 static int amdgpu_dm_encoder_init(struct drm_device *dev,
3618                                   struct amdgpu_encoder *aencoder,
3619                                   uint32_t link_index)
3620 {
3621         struct amdgpu_device *adev = dev->dev_private;
3622
3623         int res = drm_encoder_init(dev,
3624                                    &aencoder->base,
3625                                    &amdgpu_dm_encoder_funcs,
3626                                    DRM_MODE_ENCODER_TMDS,
3627                                    NULL);
3628
3629         aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
3630
3631         if (!res)
3632                 aencoder->encoder_id = link_index;
3633         else
3634                 aencoder->encoder_id = -1;
3635
3636         drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
3637
3638         return res;
3639 }
3640
3641 static void manage_dm_interrupts(struct amdgpu_device *adev,
3642                                  struct amdgpu_crtc *acrtc,
3643                                  bool enable)
3644 {
3645         /*
3646          * this is not correct translation but will work as soon as VBLANK
3647          * constant is the same as PFLIP
3648          */
3649         int irq_type =
3650                 amdgpu_display_crtc_idx_to_irq_type(
3651                         adev,
3652                         acrtc->crtc_id);
3653
3654         if (enable) {
3655                 drm_crtc_vblank_on(&acrtc->base);
3656                 amdgpu_irq_get(
3657                         adev,
3658                         &adev->pageflip_irq,
3659                         irq_type);
3660         } else {
3661
3662                 amdgpu_irq_put(
3663                         adev,
3664                         &adev->pageflip_irq,
3665                         irq_type);
3666                 drm_crtc_vblank_off(&acrtc->base);
3667         }
3668 }
3669
3670 static bool
3671 is_scaling_state_different(const struct dm_connector_state *dm_state,
3672                            const struct dm_connector_state *old_dm_state)
3673 {
3674         if (dm_state->scaling != old_dm_state->scaling)
3675                 return true;
3676         if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
3677                 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
3678                         return true;
3679         } else  if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
3680                 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
3681                         return true;
3682         } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
3683                    dm_state->underscan_vborder != old_dm_state->underscan_vborder)
3684                 return true;
3685         return false;
3686 }
3687
3688 static void remove_stream(struct amdgpu_device *adev,
3689                           struct amdgpu_crtc *acrtc,
3690                           struct dc_stream_state *stream)
3691 {
3692         /* this is the update mode case */
3693         if (adev->dm.freesync_module)
3694                 mod_freesync_remove_stream(adev->dm.freesync_module, stream);
3695
3696         acrtc->otg_inst = -1;
3697         acrtc->enabled = false;
3698 }
3699
3700 static int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc,
3701                                struct dc_cursor_position *position)
3702 {
3703         struct amdgpu_crtc *amdgpu_crtc = amdgpu_crtc = to_amdgpu_crtc(crtc);
3704         int x, y;
3705         int xorigin = 0, yorigin = 0;
3706
3707         if (!crtc || !plane->state->fb) {
3708                 position->enable = false;
3709                 position->x = 0;
3710                 position->y = 0;
3711                 return 0;
3712         }
3713
3714         if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) ||
3715             (plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) {
3716                 DRM_ERROR("%s: bad cursor width or height %d x %d\n",
3717                           __func__,
3718                           plane->state->crtc_w,
3719                           plane->state->crtc_h);
3720                 return -EINVAL;
3721         }
3722
3723         x = plane->state->crtc_x;
3724         y = plane->state->crtc_y;
3725         /* avivo cursor are offset into the total surface */
3726         x += crtc->primary->state->src_x >> 16;
3727         y += crtc->primary->state->src_y >> 16;
3728         if (x < 0) {
3729                 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
3730                 x = 0;
3731         }
3732         if (y < 0) {
3733                 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
3734                 y = 0;
3735         }
3736         position->enable = true;
3737         position->x = x;
3738         position->y = y;
3739         position->x_hotspot = xorigin;
3740         position->y_hotspot = yorigin;
3741
3742         return 0;
3743 }
3744
3745 static void handle_cursor_update(struct drm_plane *plane,
3746                                  struct drm_plane_state *old_plane_state)
3747 {
3748         struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb);
3749         struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc;
3750         struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL;
3751         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
3752         uint64_t address = afb ? afb->address : 0;
3753         struct dc_cursor_position position;
3754         struct dc_cursor_attributes attributes;
3755         int ret;
3756
3757         if (!plane->state->fb && !old_plane_state->fb)
3758                 return;
3759
3760         DRM_DEBUG_DRIVER("%s: crtc_id=%d with size %d to %d\n",
3761                          __func__,
3762                          amdgpu_crtc->crtc_id,
3763                          plane->state->crtc_w,
3764                          plane->state->crtc_h);
3765
3766         ret = get_cursor_position(plane, crtc, &position);
3767         if (ret)
3768                 return;
3769
3770         if (!position.enable) {
3771                 /* turn off cursor */
3772                 if (crtc_state && crtc_state->stream)
3773                         dc_stream_set_cursor_position(crtc_state->stream,
3774                                                       &position);
3775                 return;
3776         }
3777
3778         amdgpu_crtc->cursor_width = plane->state->crtc_w;
3779         amdgpu_crtc->cursor_height = plane->state->crtc_h;
3780
3781         attributes.address.high_part = upper_32_bits(address);
3782         attributes.address.low_part  = lower_32_bits(address);
3783         attributes.width             = plane->state->crtc_w;
3784         attributes.height            = plane->state->crtc_h;
3785         attributes.color_format      = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA;
3786         attributes.rotation_angle    = 0;
3787         attributes.attribute_flags.value = 0;
3788
3789         attributes.pitch = attributes.width;
3790
3791         if (crtc_state->stream) {
3792                 if (!dc_stream_set_cursor_attributes(crtc_state->stream,
3793                                                          &attributes))
3794                         DRM_ERROR("DC failed to set cursor attributes\n");
3795
3796                 if (!dc_stream_set_cursor_position(crtc_state->stream,
3797                                                    &position))
3798                         DRM_ERROR("DC failed to set cursor position\n");
3799         }
3800 }
3801
3802 static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
3803 {
3804
3805         assert_spin_locked(&acrtc->base.dev->event_lock);
3806         WARN_ON(acrtc->event);
3807
3808         acrtc->event = acrtc->base.state->event;
3809
3810         /* Set the flip status */
3811         acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
3812
3813         /* Mark this event as consumed */
3814         acrtc->base.state->event = NULL;
3815
3816         DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
3817                                                  acrtc->crtc_id);
3818 }
3819
3820 /*
3821  * Executes flip
3822  *
3823  * Waits on all BO's fences and for proper vblank count
3824  */
3825 static void amdgpu_dm_do_flip(struct drm_crtc *crtc,
3826                               struct drm_framebuffer *fb,
3827                               uint32_t target,
3828                               struct dc_state *state)
3829 {
3830         unsigned long flags;
3831         uint32_t target_vblank;
3832         int r, vpos, hpos;
3833         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3834         struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
3835         struct amdgpu_bo *abo = gem_to_amdgpu_bo(afb->obj);
3836         struct amdgpu_device *adev = crtc->dev->dev_private;
3837         bool async_flip = (crtc->state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
3838         struct dc_flip_addrs addr = { {0} };
3839         /* TODO eliminate or rename surface_update */
3840         struct dc_surface_update surface_updates[1] = { {0} };
3841         struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
3842
3843
3844         /* Prepare wait for target vblank early - before the fence-waits */
3845         target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) +
3846                         amdgpu_get_vblank_counter_kms(crtc->dev, acrtc->crtc_id);
3847
3848         /* TODO This might fail and hence better not used, wait
3849          * explicitly on fences instead
3850          * and in general should be called for
3851          * blocking commit to as per framework helpers
3852          */
3853         r = amdgpu_bo_reserve(abo, true);
3854         if (unlikely(r != 0)) {
3855                 DRM_ERROR("failed to reserve buffer before flip\n");
3856                 WARN_ON(1);
3857         }
3858
3859         /* Wait for all fences on this FB */
3860         WARN_ON(reservation_object_wait_timeout_rcu(abo->tbo.resv, true, false,
3861                                                                     MAX_SCHEDULE_TIMEOUT) < 0);
3862
3863         amdgpu_bo_unreserve(abo);
3864
3865         /* Wait until we're out of the vertical blank period before the one
3866          * targeted by the flip
3867          */
3868         while ((acrtc->enabled &&
3869                 (amdgpu_display_get_crtc_scanoutpos(adev->ddev, acrtc->crtc_id,
3870                                                     0, &vpos, &hpos, NULL,
3871                                                     NULL, &crtc->hwmode)
3872                  & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
3873                 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
3874                 (int)(target_vblank -
3875                   amdgpu_get_vblank_counter_kms(adev->ddev, acrtc->crtc_id)) > 0)) {
3876                 usleep_range(1000, 1100);
3877         }
3878
3879         /* Flip */
3880         spin_lock_irqsave(&crtc->dev->event_lock, flags);
3881         /* update crtc fb */
3882         crtc->primary->fb = fb;
3883
3884         WARN_ON(acrtc->pflip_status != AMDGPU_FLIP_NONE);
3885         WARN_ON(!acrtc_state->stream);
3886
3887         addr.address.grph.addr.low_part = lower_32_bits(afb->address);
3888         addr.address.grph.addr.high_part = upper_32_bits(afb->address);
3889         addr.flip_immediate = async_flip;
3890
3891
3892         if (acrtc->base.state->event)
3893                 prepare_flip_isr(acrtc);
3894
3895         surface_updates->surface = dc_stream_get_status(acrtc_state->stream)->plane_states[0];
3896         surface_updates->flip_addr = &addr;
3897
3898
3899         dc_commit_updates_for_stream(adev->dm.dc,
3900                                              surface_updates,
3901                                              1,
3902                                              acrtc_state->stream,
3903                                              NULL,
3904                                              &surface_updates->surface,
3905                                              state);
3906
3907         DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x \n",
3908                          __func__,
3909                          addr.address.grph.addr.high_part,
3910                          addr.address.grph.addr.low_part);
3911
3912
3913         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
3914 }
3915
3916 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
3917                                     struct drm_device *dev,
3918                                     struct amdgpu_display_manager *dm,
3919                                     struct drm_crtc *pcrtc,
3920                                     bool *wait_for_vblank)
3921 {
3922         uint32_t i;
3923         struct drm_plane *plane;
3924         struct drm_plane_state *old_plane_state, *new_plane_state;
3925         struct dc_stream_state *dc_stream_attach;
3926         struct dc_plane_state *plane_states_constructed[MAX_SURFACES];
3927         struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
3928         struct drm_crtc_state *new_pcrtc_state =
3929                         drm_atomic_get_new_crtc_state(state, pcrtc);
3930         struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state);
3931         struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
3932         int planes_count = 0;
3933         unsigned long flags;
3934
3935         /* update planes when needed */
3936         for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
3937                 struct drm_crtc *crtc = new_plane_state->crtc;
3938                 struct drm_crtc_state *new_crtc_state;
3939                 struct drm_framebuffer *fb = new_plane_state->fb;
3940                 bool pflip_needed;
3941                 struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
3942
3943                 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
3944                         handle_cursor_update(plane, old_plane_state);
3945                         continue;
3946                 }
3947
3948                 if (!fb || !crtc || pcrtc != crtc)
3949                         continue;
3950
3951                 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
3952                 if (!new_crtc_state->active)
3953                         continue;
3954
3955                 pflip_needed = !state->allow_modeset;
3956
3957                 spin_lock_irqsave(&crtc->dev->event_lock, flags);
3958                 if (acrtc_attach->pflip_status != AMDGPU_FLIP_NONE) {
3959                         DRM_ERROR("%s: acrtc %d, already busy\n",
3960                                   __func__,
3961                                   acrtc_attach->crtc_id);
3962                         /* In commit tail framework this cannot happen */
3963                         WARN_ON(1);
3964                 }
3965                 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
3966
3967                 if (!pflip_needed) {
3968                         WARN_ON(!dm_new_plane_state->dc_state);
3969
3970                         plane_states_constructed[planes_count] = dm_new_plane_state->dc_state;
3971
3972                         dc_stream_attach = acrtc_state->stream;
3973                         planes_count++;
3974
3975                 } else if (new_crtc_state->planes_changed) {
3976                         /* Assume even ONE crtc with immediate flip means
3977                          * entire can't wait for VBLANK
3978                          * TODO Check if it's correct
3979                          */
3980                         *wait_for_vblank =
3981                                         new_pcrtc_state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC ?
3982                                 false : true;
3983
3984                         /* TODO: Needs rework for multiplane flip */
3985                         if (plane->type == DRM_PLANE_TYPE_PRIMARY)
3986                                 drm_crtc_vblank_get(crtc);
3987
3988                         amdgpu_dm_do_flip(
3989                                 crtc,
3990                                 fb,
3991                                 (uint32_t)drm_crtc_vblank_count(crtc) + *wait_for_vblank,
3992                                 dm_state->context);
3993                 }
3994
3995         }
3996
3997         if (planes_count) {
3998                 unsigned long flags;
3999
4000                 if (new_pcrtc_state->event) {
4001
4002                         drm_crtc_vblank_get(pcrtc);
4003
4004                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
4005                         prepare_flip_isr(acrtc_attach);
4006                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
4007                 }
4008
4009                 if (false == dc_commit_planes_to_stream(dm->dc,
4010                                                         plane_states_constructed,
4011                                                         planes_count,
4012                                                         dc_stream_attach,
4013                                                         dm_state->context))
4014                         dm_error("%s: Failed to attach plane!\n", __func__);
4015         } else {
4016                 /*TODO BUG Here should go disable planes on CRTC. */
4017         }
4018 }
4019
4020 /**
4021  * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
4022  * @crtc_state: the DRM CRTC state
4023  * @stream_state: the DC stream state.
4024  *
4025  * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
4026  * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
4027  */
4028 static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
4029                                                 struct dc_stream_state *stream_state)
4030 {
4031         stream_state->mode_changed = crtc_state->mode_changed;
4032 }
4033
4034 static int amdgpu_dm_atomic_commit(struct drm_device *dev,
4035                                    struct drm_atomic_state *state,
4036                                    bool nonblock)
4037 {
4038         struct drm_crtc *crtc;
4039         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
4040         struct amdgpu_device *adev = dev->dev_private;
4041         int i;
4042
4043         /*
4044          * We evade vblanks and pflips on crtc that
4045          * should be changed. We do it here to flush & disable
4046          * interrupts before drm_swap_state is called in drm_atomic_helper_commit
4047          * it will update crtc->dm_crtc_state->stream pointer which is used in
4048          * the ISRs.
4049          */
4050         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
4051                 struct dm_crtc_state *dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
4052                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
4053
4054                 if (drm_atomic_crtc_needs_modeset(new_crtc_state) && dm_old_crtc_state->stream)
4055                         manage_dm_interrupts(adev, acrtc, false);
4056         }
4057         /* Add check here for SoC's that support hardware cursor plane, to
4058          * unset legacy_cursor_update */
4059
4060         return drm_atomic_helper_commit(dev, state, nonblock);
4061
4062         /*TODO Handle EINTR, reenable IRQ*/
4063 }
4064
4065 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
4066 {
4067         struct drm_device *dev = state->dev;
4068         struct amdgpu_device *adev = dev->dev_private;
4069         struct amdgpu_display_manager *dm = &adev->dm;
4070         struct dm_atomic_state *dm_state;
4071         uint32_t i, j;
4072         struct drm_crtc *crtc;
4073         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
4074         unsigned long flags;
4075         bool wait_for_vblank = true;
4076         struct drm_connector *connector;
4077         struct drm_connector_state *old_con_state, *new_con_state;
4078         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
4079
4080         drm_atomic_helper_update_legacy_modeset_state(dev, state);
4081
4082         dm_state = to_dm_atomic_state(state);
4083
4084         /* update changed items */
4085         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
4086                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
4087
4088                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
4089                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
4090
4091                 DRM_DEBUG_DRIVER(
4092                         "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
4093                         "planes_changed:%d, mode_changed:%d,active_changed:%d,"
4094                         "connectors_changed:%d\n",
4095                         acrtc->crtc_id,
4096                         new_crtc_state->enable,
4097                         new_crtc_state->active,
4098                         new_crtc_state->planes_changed,
4099                         new_crtc_state->mode_changed,
4100                         new_crtc_state->active_changed,
4101                         new_crtc_state->connectors_changed);
4102
4103                 /* Copy all transient state flags into dc state */
4104                 if (dm_new_crtc_state->stream) {
4105                         amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
4106                                                             dm_new_crtc_state->stream);
4107                 }
4108
4109                 /* handles headless hotplug case, updating new_state and
4110                  * aconnector as needed
4111                  */
4112
4113                 if (modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {
4114
4115                         DRM_DEBUG_DRIVER("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
4116
4117                         if (!dm_new_crtc_state->stream) {
4118                                 /*
4119                                  * this could happen because of issues with
4120                                  * userspace notifications delivery.
4121                                  * In this case userspace tries to set mode on
4122                                  * display which is disconnect in fact.
4123                                  * dc_sink in NULL in this case on aconnector.
4124                                  * We expect reset mode will come soon.
4125                                  *
4126                                  * This can also happen when unplug is done
4127                                  * during resume sequence ended
4128                                  *
4129                                  * In this case, we want to pretend we still
4130                                  * have a sink to keep the pipe running so that
4131                                  * hw state is consistent with the sw state
4132                                  */
4133                                 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
4134                                                 __func__, acrtc->base.base.id);
4135                                 continue;
4136                         }
4137
4138                         if (dm_old_crtc_state->stream)
4139                                 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
4140
4141                         acrtc->enabled = true;
4142                         acrtc->hw_mode = new_crtc_state->mode;
4143                         crtc->hwmode = new_crtc_state->mode;
4144                 } else if (modereset_required(new_crtc_state)) {
4145                         DRM_DEBUG_DRIVER("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
4146
4147                         /* i.e. reset mode */
4148                         if (dm_old_crtc_state->stream)
4149                                 remove_stream(adev, acrtc, dm_old_crtc_state->stream);
4150                 }
4151         } /* for_each_crtc_in_state() */
4152
4153         /*
4154          * Add streams after required streams from new and replaced streams
4155          * are removed from freesync module
4156          */
4157         if (adev->dm.freesync_module) {
4158                 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
4159                                               new_crtc_state, i) {
4160                         struct amdgpu_dm_connector *aconnector = NULL;
4161                         struct dm_connector_state *dm_new_con_state = NULL;
4162                         struct amdgpu_crtc *acrtc = NULL;
4163                         bool modeset_needed;
4164
4165                         dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
4166                         dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
4167                         modeset_needed = modeset_required(
4168                                         new_crtc_state,
4169                                         dm_new_crtc_state->stream,
4170                                         dm_old_crtc_state->stream);
4171                         /* We add stream to freesync if:
4172                          * 1. Said stream is not null, and
4173                          * 2. A modeset is requested. This means that the
4174                          *    stream was removed previously, and needs to be
4175                          *    replaced.
4176                          */
4177                         if (dm_new_crtc_state->stream == NULL ||
4178                                         !modeset_needed)
4179                                 continue;
4180
4181                         acrtc = to_amdgpu_crtc(crtc);
4182
4183                         aconnector =
4184                                 amdgpu_dm_find_first_crtc_matching_connector(
4185                                         state, crtc);
4186                         if (!aconnector) {
4187                                 DRM_DEBUG_DRIVER("Atomic commit: Failed to "
4188                                                  "find connector for acrtc "
4189                                                  "id:%d skipping freesync "
4190                                                  "init\n",
4191                                                  acrtc->crtc_id);
4192                                 continue;
4193                         }
4194
4195                         mod_freesync_add_stream(adev->dm.freesync_module,
4196                                                 dm_new_crtc_state->stream,
4197                                                 &aconnector->caps);
4198                         new_con_state = drm_atomic_get_new_connector_state(
4199                                         state, &aconnector->base);
4200                         dm_new_con_state = to_dm_connector_state(new_con_state);
4201
4202                         mod_freesync_set_user_enable(adev->dm.freesync_module,
4203                                                      &dm_new_crtc_state->stream,
4204                                                      1,
4205                                                      &dm_new_con_state->user_enable);
4206                 }
4207         }
4208
4209         if (dm_state->context) {
4210                 dm_enable_per_frame_crtc_master_sync(dm_state->context);
4211                 WARN_ON(!dc_commit_state(dm->dc, dm_state->context));
4212         }
4213
4214         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
4215                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
4216
4217                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
4218
4219                 if (dm_new_crtc_state->stream != NULL) {
4220                         const struct dc_stream_status *status =
4221                                         dc_stream_get_status(dm_new_crtc_state->stream);
4222
4223                         if (!status)
4224                                 DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc);
4225                         else
4226                                 acrtc->otg_inst = status->primary_otg_inst;
4227                 }
4228         }
4229
4230         /* Handle scaling and underscan changes*/
4231         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
4232                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
4233                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
4234                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
4235                 struct dc_stream_status *status = NULL;
4236
4237                 if (acrtc)
4238                         new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
4239
4240                 /* Skip any modesets/resets */
4241                 if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
4242                         continue;
4243
4244                 /* Skip any thing not scale or underscan changes */
4245                 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
4246                         continue;
4247
4248                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
4249
4250                 update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
4251                                 dm_new_con_state, (struct dc_stream_state *)dm_new_crtc_state->stream);
4252
4253                 if (!dm_new_crtc_state->stream)
4254                         continue;
4255
4256                 status = dc_stream_get_status(dm_new_crtc_state->stream);
4257                 WARN_ON(!status);
4258                 WARN_ON(!status->plane_count);
4259
4260                 /*TODO How it works with MPO ?*/
4261                 if (!dc_commit_planes_to_stream(
4262                                 dm->dc,
4263                                 status->plane_states,
4264                                 status->plane_count,
4265                                 dm_new_crtc_state->stream,
4266                                 dm_state->context))
4267                         dm_error("%s: Failed to update stream scaling!\n", __func__);
4268         }
4269
4270         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
4271                         new_crtc_state, i) {
4272                 /*
4273                  * loop to enable interrupts on newly arrived crtc
4274                  */
4275                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
4276                 bool modeset_needed;
4277
4278                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
4279                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
4280                 modeset_needed = modeset_required(
4281                                 new_crtc_state,
4282                                 dm_new_crtc_state->stream,
4283                                 dm_old_crtc_state->stream);
4284
4285                 if (dm_new_crtc_state->stream == NULL || !modeset_needed)
4286                         continue;
4287
4288                 if (adev->dm.freesync_module)
4289                         mod_freesync_notify_mode_change(
4290                                 adev->dm.freesync_module,
4291                                 &dm_new_crtc_state->stream, 1);
4292
4293                 manage_dm_interrupts(adev, acrtc, true);
4294         }
4295
4296         /* update planes when needed per crtc*/
4297         for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
4298                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
4299
4300                 if (dm_new_crtc_state->stream)
4301                         amdgpu_dm_commit_planes(state, dev, dm, crtc, &wait_for_vblank);
4302         }
4303
4304
4305         /*
4306          * send vblank event on all events not handled in flip and
4307          * mark consumed event for drm_atomic_helper_commit_hw_done
4308          */
4309         spin_lock_irqsave(&adev->ddev->event_lock, flags);
4310         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
4311
4312                 if (new_crtc_state->event)
4313                         drm_send_event_locked(dev, &new_crtc_state->event->base);
4314
4315                 new_crtc_state->event = NULL;
4316         }
4317         spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
4318
4319         /* Signal HW programming completion */
4320         drm_atomic_helper_commit_hw_done(state);
4321
4322         if (wait_for_vblank)
4323                 drm_atomic_helper_wait_for_flip_done(dev, state);
4324
4325         drm_atomic_helper_cleanup_planes(dev, state);
4326 }
4327
4328
4329 static int dm_force_atomic_commit(struct drm_connector *connector)
4330 {
4331         int ret = 0;
4332         struct drm_device *ddev = connector->dev;
4333         struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
4334         struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
4335         struct drm_plane *plane = disconnected_acrtc->base.primary;
4336         struct drm_connector_state *conn_state;
4337         struct drm_crtc_state *crtc_state;
4338         struct drm_plane_state *plane_state;
4339
4340         if (!state)
4341                 return -ENOMEM;
4342
4343         state->acquire_ctx = ddev->mode_config.acquire_ctx;
4344
4345         /* Construct an atomic state to restore previous display setting */
4346
4347         /*
4348          * Attach connectors to drm_atomic_state
4349          */
4350         conn_state = drm_atomic_get_connector_state(state, connector);
4351
4352         ret = PTR_ERR_OR_ZERO(conn_state);
4353         if (ret)
4354                 goto err;
4355
4356         /* Attach crtc to drm_atomic_state*/
4357         crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
4358
4359         ret = PTR_ERR_OR_ZERO(crtc_state);
4360         if (ret)
4361                 goto err;
4362
4363         /* force a restore */
4364         crtc_state->mode_changed = true;
4365
4366         /* Attach plane to drm_atomic_state */
4367         plane_state = drm_atomic_get_plane_state(state, plane);
4368
4369         ret = PTR_ERR_OR_ZERO(plane_state);
4370         if (ret)
4371                 goto err;
4372
4373
4374         /* Call commit internally with the state we just constructed */
4375         ret = drm_atomic_commit(state);
4376         if (!ret)
4377                 return 0;
4378
4379 err:
4380         DRM_ERROR("Restoring old state failed with %i\n", ret);
4381         drm_atomic_state_put(state);
4382
4383         return ret;
4384 }
4385
4386 /*
4387  * This functions handle all cases when set mode does not come upon hotplug.
4388  * This include when the same display is unplugged then plugged back into the
4389  * same port and when we are running without usermode desktop manager supprot
4390  */
4391 void dm_restore_drm_connector_state(struct drm_device *dev,
4392                                     struct drm_connector *connector)
4393 {
4394         struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
4395         struct amdgpu_crtc *disconnected_acrtc;
4396         struct dm_crtc_state *acrtc_state;
4397
4398         if (!aconnector->dc_sink || !connector->state || !connector->encoder)
4399                 return;
4400
4401         disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
4402         if (!disconnected_acrtc)
4403                 return;
4404
4405         acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
4406         if (!acrtc_state->stream)
4407                 return;
4408
4409         /*
4410          * If the previous sink is not released and different from the current,
4411          * we deduce we are in a state where we can not rely on usermode call
4412          * to turn on the display, so we do it here
4413          */
4414         if (acrtc_state->stream->sink != aconnector->dc_sink)
4415                 dm_force_atomic_commit(&aconnector->base);
4416 }
4417
4418 /*`
4419  * Grabs all modesetting locks to serialize against any blocking commits,
4420  * Waits for completion of all non blocking commits.
4421  */
4422 static int do_aquire_global_lock(struct drm_device *dev,
4423                                  struct drm_atomic_state *state)
4424 {
4425         struct drm_crtc *crtc;
4426         struct drm_crtc_commit *commit;
4427         long ret;
4428
4429         /* Adding all modeset locks to aquire_ctx will
4430          * ensure that when the framework release it the
4431          * extra locks we are locking here will get released to
4432          */
4433         ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
4434         if (ret)
4435                 return ret;
4436
4437         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4438                 spin_lock(&crtc->commit_lock);
4439                 commit = list_first_entry_or_null(&crtc->commit_list,
4440                                 struct drm_crtc_commit, commit_entry);
4441                 if (commit)
4442                         drm_crtc_commit_get(commit);
4443                 spin_unlock(&crtc->commit_lock);
4444
4445                 if (!commit)
4446                         continue;
4447
4448                 /* Make sure all pending HW programming completed and
4449                  * page flips done
4450                  */
4451                 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
4452
4453                 if (ret > 0)
4454                         ret = wait_for_completion_interruptible_timeout(
4455                                         &commit->flip_done, 10*HZ);
4456
4457                 if (ret == 0)
4458                         DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
4459                                   "timed out\n", crtc->base.id, crtc->name);
4460
4461                 drm_crtc_commit_put(commit);
4462         }
4463
4464         return ret < 0 ? ret : 0;
4465 }
4466
4467 static int dm_update_crtcs_state(struct dc *dc,
4468                                  struct drm_atomic_state *state,
4469                                  bool enable,
4470                                  bool *lock_and_validation_needed)
4471 {
4472         struct drm_crtc *crtc;
4473         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
4474         int i;
4475         struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
4476         struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
4477         struct dc_stream_state *new_stream;
4478         int ret = 0;
4479
4480         /*TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set */
4481         /* update changed items */
4482         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
4483                 struct amdgpu_crtc *acrtc = NULL;
4484                 struct amdgpu_dm_connector *aconnector = NULL;
4485                 struct drm_connector_state *new_con_state = NULL;
4486                 struct dm_connector_state *dm_conn_state = NULL;
4487
4488                 new_stream = NULL;
4489
4490                 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
4491                 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
4492                 acrtc = to_amdgpu_crtc(crtc);
4493
4494                 aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
4495
4496                 /* TODO This hack should go away */
4497                 if (aconnector && enable) {
4498                         // Make sure fake sink is created in plug-in scenario
4499                         new_con_state = drm_atomic_get_connector_state(state,
4500                                                                     &aconnector->base);
4501
4502                         if (IS_ERR(new_con_state)) {
4503                                 ret = PTR_ERR_OR_ZERO(new_con_state);
4504                                 break;
4505                         }
4506
4507                         dm_conn_state = to_dm_connector_state(new_con_state);
4508
4509                         new_stream = create_stream_for_sink(aconnector,
4510                                                              &new_crtc_state->mode,
4511                                                             dm_conn_state);
4512
4513                         /*
4514                          * we can have no stream on ACTION_SET if a display
4515                          * was disconnected during S3, in this case it not and
4516                          * error, the OS will be updated after detection, and
4517                          * do the right thing on next atomic commit
4518                          */
4519
4520                         if (!new_stream) {
4521                                 DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",
4522                                                 __func__, acrtc->base.base.id);
4523                                 break;
4524                         }
4525
4526                         if (dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
4527                             dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
4528                                 new_crtc_state->mode_changed = false;
4529                                 DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",
4530                                                  new_crtc_state->mode_changed);
4531                         }
4532                 }
4533
4534                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
4535                         goto next_crtc;
4536
4537                 DRM_DEBUG_DRIVER(
4538                         "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
4539                         "planes_changed:%d, mode_changed:%d,active_changed:%d,"
4540                         "connectors_changed:%d\n",
4541                         acrtc->crtc_id,
4542                         new_crtc_state->enable,
4543                         new_crtc_state->active,
4544                         new_crtc_state->planes_changed,
4545                         new_crtc_state->mode_changed,
4546                         new_crtc_state->active_changed,
4547                         new_crtc_state->connectors_changed);
4548
4549                 /* Remove stream for any changed/disabled CRTC */
4550                 if (!enable) {
4551
4552                         if (!dm_old_crtc_state->stream)
4553                                 goto next_crtc;
4554
4555                         DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",
4556                                         crtc->base.id);
4557
4558                         /* i.e. reset mode */
4559                         if (dc_remove_stream_from_ctx(
4560                                         dc,
4561                                         dm_state->context,
4562                                         dm_old_crtc_state->stream) != DC_OK) {
4563                                 ret = -EINVAL;
4564                                 goto fail;
4565                         }
4566
4567                         dc_stream_release(dm_old_crtc_state->stream);
4568                         dm_new_crtc_state->stream = NULL;
4569
4570                         *lock_and_validation_needed = true;
4571
4572                 } else {/* Add stream for any updated/enabled CRTC */
4573                         /*
4574                          * Quick fix to prevent NULL pointer on new_stream when
4575                          * added MST connectors not found in existing crtc_state in the chained mode
4576                          * TODO: need to dig out the root cause of that
4577                          */
4578                         if (!aconnector || (!aconnector->dc_sink && aconnector->mst_port))
4579                                 goto next_crtc;
4580
4581                         if (modereset_required(new_crtc_state))
4582                                 goto next_crtc;
4583
4584                         if (modeset_required(new_crtc_state, new_stream,
4585                                              dm_old_crtc_state->stream)) {
4586
4587                                 WARN_ON(dm_new_crtc_state->stream);
4588
4589                                 dm_new_crtc_state->stream = new_stream;
4590
4591                                 dc_stream_retain(new_stream);
4592
4593                                 DRM_DEBUG_DRIVER("Enabling DRM crtc: %d\n",
4594                                                         crtc->base.id);
4595
4596                                 if (dc_add_stream_to_ctx(
4597                                                 dc,
4598                                                 dm_state->context,
4599                                                 dm_new_crtc_state->stream) != DC_OK) {
4600                                         ret = -EINVAL;
4601                                         goto fail;
4602                                 }
4603
4604                                 *lock_and_validation_needed = true;
4605                         }
4606                 }
4607
4608 next_crtc:
4609                 /* Release extra reference */
4610                 if (new_stream)
4611                          dc_stream_release(new_stream);
4612
4613                 /*
4614                  * We want to do dc stream updates that do not require a
4615                  * full modeset below.
4616                  */
4617                 if (!enable || !aconnector || modereset_required(new_crtc_state))
4618                         continue;
4619                 /*
4620                  * Given above conditions, the dc state cannot be NULL because:
4621                  * 1. We're attempting to enable a CRTC. Which has a...
4622                  * 2. Valid connector attached, and
4623                  * 3. User does not want to reset it (disable or mark inactive,
4624                  *    which can happen on a CRTC that's already disabled).
4625                  * => It currently exists.
4626                  */
4627                 BUG_ON(dm_new_crtc_state->stream == NULL);
4628
4629                 /* Color managment settings */
4630                 if (dm_new_crtc_state->base.color_mgmt_changed) {
4631                         ret = amdgpu_dm_set_regamma_lut(dm_new_crtc_state);
4632                         if (ret)
4633                                 goto fail;
4634                         amdgpu_dm_set_ctm(dm_new_crtc_state);
4635                 }
4636         }
4637
4638         return ret;
4639
4640 fail:
4641         if (new_stream)
4642                 dc_stream_release(new_stream);
4643         return ret;
4644 }
4645
4646 static int dm_update_planes_state(struct dc *dc,
4647                                   struct drm_atomic_state *state,
4648                                   bool enable,
4649                                   bool *lock_and_validation_needed)
4650 {
4651         struct drm_crtc *new_plane_crtc, *old_plane_crtc;
4652         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
4653         struct drm_plane *plane;
4654         struct drm_plane_state *old_plane_state, *new_plane_state;
4655         struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
4656         struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
4657         struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
4658         int i ;
4659         /* TODO return page_flip_needed() function */
4660         bool pflip_needed  = !state->allow_modeset;
4661         int ret = 0;
4662
4663         if (pflip_needed)
4664                 return ret;
4665
4666         /* Add new planes */
4667         for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
4668                 new_plane_crtc = new_plane_state->crtc;
4669                 old_plane_crtc = old_plane_state->crtc;
4670                 dm_new_plane_state = to_dm_plane_state(new_plane_state);
4671                 dm_old_plane_state = to_dm_plane_state(old_plane_state);
4672
4673                 /*TODO Implement atomic check for cursor plane */
4674                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
4675                         continue;
4676
4677                 /* Remove any changed/removed planes */
4678                 if (!enable) {
4679
4680                         if (!old_plane_crtc)
4681                                 continue;
4682
4683                         old_crtc_state = drm_atomic_get_old_crtc_state(
4684                                         state, old_plane_crtc);
4685                         dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
4686
4687                         if (!dm_old_crtc_state->stream)
4688                                 continue;
4689
4690                         DRM_DEBUG_DRIVER("Disabling DRM plane: %d on DRM crtc %d\n",
4691                                         plane->base.id, old_plane_crtc->base.id);
4692
4693                         if (!dc_remove_plane_from_context(
4694                                         dc,
4695                                         dm_old_crtc_state->stream,
4696                                         dm_old_plane_state->dc_state,
4697                                         dm_state->context)) {
4698
4699                                 ret = EINVAL;
4700                                 return ret;
4701                         }
4702
4703
4704                         dc_plane_state_release(dm_old_plane_state->dc_state);
4705                         dm_new_plane_state->dc_state = NULL;
4706
4707                         *lock_and_validation_needed = true;
4708
4709                 } else { /* Add new planes */
4710
4711                         if (drm_atomic_plane_disabling(plane->state, new_plane_state))
4712                                 continue;
4713
4714                         if (!new_plane_crtc)
4715                                 continue;
4716
4717                         new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
4718                         dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
4719
4720                         if (!dm_new_crtc_state->stream)
4721                                 continue;
4722
4723
4724                         WARN_ON(dm_new_plane_state->dc_state);
4725
4726                         dm_new_plane_state->dc_state = dc_create_plane_state(dc);
4727
4728                         DRM_DEBUG_DRIVER("Enabling DRM plane: %d on DRM crtc %d\n",
4729                                         plane->base.id, new_plane_crtc->base.id);
4730
4731                         if (!dm_new_plane_state->dc_state) {
4732                                 ret = -EINVAL;
4733                                 return ret;
4734                         }
4735
4736                         ret = fill_plane_attributes(
4737                                 new_plane_crtc->dev->dev_private,
4738                                 dm_new_plane_state->dc_state,
4739                                 new_plane_state,
4740                                 new_crtc_state);
4741                         if (ret)
4742                                 return ret;
4743
4744                         if (!dc_add_plane_to_context(
4745                                         dc,
4746                                         dm_new_crtc_state->stream,
4747                                         dm_new_plane_state->dc_state,
4748                                         dm_state->context)) {
4749
4750                                 ret = -EINVAL;
4751                                 return ret;
4752                         }
4753
4754                         /* Tell DC to do a full surface update every time there
4755                          * is a plane change. Inefficient, but works for now.
4756                          */
4757                         dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
4758
4759                         *lock_and_validation_needed = true;
4760                 }
4761         }
4762
4763
4764         return ret;
4765 }
4766
4767 static int amdgpu_dm_atomic_check(struct drm_device *dev,
4768                                   struct drm_atomic_state *state)
4769 {
4770         struct amdgpu_device *adev = dev->dev_private;
4771         struct dc *dc = adev->dm.dc;
4772         struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
4773         struct drm_connector *connector;
4774         struct drm_connector_state *old_con_state, *new_con_state;
4775         struct drm_crtc *crtc;
4776         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
4777         int ret, i;
4778
4779         /*
4780          * This bool will be set for true for any modeset/reset
4781          * or plane update which implies non fast surface update.
4782          */
4783         bool lock_and_validation_needed = false;
4784
4785         ret = drm_atomic_helper_check_modeset(dev, state);
4786         if (ret)
4787                 goto fail;
4788
4789         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
4790                 if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
4791                     !new_crtc_state->color_mgmt_changed)
4792                         continue;
4793
4794                 if (!new_crtc_state->enable)
4795                         continue;
4796
4797                 ret = drm_atomic_add_affected_connectors(state, crtc);
4798                 if (ret)
4799                         return ret;
4800
4801                 ret = drm_atomic_add_affected_planes(state, crtc);
4802                 if (ret)
4803                         goto fail;
4804         }
4805
4806         dm_state->context = dc_create_state();
4807         ASSERT(dm_state->context);
4808         dc_resource_state_copy_construct_current(dc, dm_state->context);
4809
4810         /* Remove exiting planes if they are modified */
4811         ret = dm_update_planes_state(dc, state, false, &lock_and_validation_needed);
4812         if (ret) {
4813                 goto fail;
4814         }
4815
4816         /* Disable all crtcs which require disable */
4817         ret = dm_update_crtcs_state(dc, state, false, &lock_and_validation_needed);
4818         if (ret) {
4819                 goto fail;
4820         }
4821
4822         /* Enable all crtcs which require enable */
4823         ret = dm_update_crtcs_state(dc, state, true, &lock_and_validation_needed);
4824         if (ret) {
4825                 goto fail;
4826         }
4827
4828         /* Add new/modified planes */
4829         ret = dm_update_planes_state(dc, state, true, &lock_and_validation_needed);
4830         if (ret) {
4831                 goto fail;
4832         }
4833
4834         /* Run this here since we want to validate the streams we created */
4835         ret = drm_atomic_helper_check_planes(dev, state);
4836         if (ret)
4837                 goto fail;
4838
4839         /* Check scaling and underscan changes*/
4840         /*TODO Removed scaling changes validation due to inability to commit
4841          * new stream into context w\o causing full reset. Need to
4842          * decide how to handle.
4843          */
4844         for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
4845                 struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
4846                 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
4847                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
4848
4849                 /* Skip any modesets/resets */
4850                 if (!acrtc || drm_atomic_crtc_needs_modeset(
4851                                 drm_atomic_get_new_crtc_state(state, &acrtc->base)))
4852                         continue;
4853
4854                 /* Skip any thing not scale or underscan changes */
4855                 if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
4856                         continue;
4857
4858                 lock_and_validation_needed = true;
4859         }
4860
4861         /*
4862          * For full updates case when
4863          * removing/adding/updating  streams on once CRTC while flipping
4864          * on another CRTC,
4865          * acquiring global lock  will guarantee that any such full
4866          * update commit
4867          * will wait for completion of any outstanding flip using DRMs
4868          * synchronization events.
4869          */
4870
4871         if (lock_and_validation_needed) {
4872
4873                 ret = do_aquire_global_lock(dev, state);
4874                 if (ret)
4875                         goto fail;
4876
4877                 if (dc_validate_global_state(dc, dm_state->context) != DC_OK) {
4878                         ret = -EINVAL;
4879                         goto fail;
4880                 }
4881         }
4882
4883         /* Must be success */
4884         WARN_ON(ret);
4885         return ret;
4886
4887 fail:
4888         if (ret == -EDEADLK)
4889                 DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n");
4890         else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
4891                 DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n");
4892         else
4893                 DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret);
4894
4895         return ret;
4896 }
4897
4898 static bool is_dp_capable_without_timing_msa(struct dc *dc,
4899                                              struct amdgpu_dm_connector *amdgpu_dm_connector)
4900 {
4901         uint8_t dpcd_data;
4902         bool capable = false;
4903
4904         if (amdgpu_dm_connector->dc_link &&
4905                 dm_helpers_dp_read_dpcd(
4906                                 NULL,
4907                                 amdgpu_dm_connector->dc_link,
4908                                 DP_DOWN_STREAM_PORT_COUNT,
4909                                 &dpcd_data,
4910                                 sizeof(dpcd_data))) {
4911                 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
4912         }
4913
4914         return capable;
4915 }
4916 void amdgpu_dm_add_sink_to_freesync_module(struct drm_connector *connector,
4917                                            struct edid *edid)
4918 {
4919         int i;
4920         uint64_t val_capable;
4921         bool edid_check_required;
4922         struct detailed_timing *timing;
4923         struct detailed_non_pixel *data;
4924         struct detailed_data_monitor_range *range;
4925         struct amdgpu_dm_connector *amdgpu_dm_connector =
4926                         to_amdgpu_dm_connector(connector);
4927
4928         struct drm_device *dev = connector->dev;
4929         struct amdgpu_device *adev = dev->dev_private;
4930
4931         edid_check_required = false;
4932         if (!amdgpu_dm_connector->dc_sink) {
4933                 DRM_ERROR("dc_sink NULL, could not add free_sync module.\n");
4934                 return;
4935         }
4936         if (!adev->dm.freesync_module)
4937                 return;
4938         /*
4939          * if edid non zero restrict freesync only for dp and edp
4940          */
4941         if (edid) {
4942                 if (amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
4943                         || amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) {
4944                         edid_check_required = is_dp_capable_without_timing_msa(
4945                                                 adev->dm.dc,
4946                                                 amdgpu_dm_connector);
4947                 }
4948         }
4949         val_capable = 0;
4950         if (edid_check_required == true && (edid->version > 1 ||
4951            (edid->version == 1 && edid->revision > 1))) {
4952                 for (i = 0; i < 4; i++) {
4953
4954                         timing  = &edid->detailed_timings[i];
4955                         data    = &timing->data.other_data;
4956                         range   = &data->data.range;
4957                         /*
4958                          * Check if monitor has continuous frequency mode
4959                          */
4960                         if (data->type != EDID_DETAIL_MONITOR_RANGE)
4961                                 continue;
4962                         /*
4963                          * Check for flag range limits only. If flag == 1 then
4964                          * no additional timing information provided.
4965                          * Default GTF, GTF Secondary curve and CVT are not
4966                          * supported
4967                          */
4968                         if (range->flags != 1)
4969                                 continue;
4970
4971                         amdgpu_dm_connector->min_vfreq = range->min_vfreq;
4972                         amdgpu_dm_connector->max_vfreq = range->max_vfreq;
4973                         amdgpu_dm_connector->pixel_clock_mhz =
4974                                 range->pixel_clock_mhz * 10;
4975                         break;
4976                 }
4977
4978                 if (amdgpu_dm_connector->max_vfreq -
4979                                 amdgpu_dm_connector->min_vfreq > 10) {
4980                         amdgpu_dm_connector->caps.supported = true;
4981                         amdgpu_dm_connector->caps.min_refresh_in_micro_hz =
4982                                         amdgpu_dm_connector->min_vfreq * 1000000;
4983                         amdgpu_dm_connector->caps.max_refresh_in_micro_hz =
4984                                         amdgpu_dm_connector->max_vfreq * 1000000;
4985                                 val_capable = 1;
4986                 }
4987         }
4988
4989         /*
4990          * TODO figure out how to notify user-mode or DRM of freesync caps
4991          * once we figure out how to deal with freesync in an upstreamable
4992          * fashion
4993          */
4994
4995 }
4996
4997 void amdgpu_dm_remove_sink_from_freesync_module(struct drm_connector *connector)
4998 {
4999         /*
5000          * TODO fill in once we figure out how to deal with freesync in
5001          * an upstreamable fashion
5002          */
5003 }