drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dm_services_types.h"
  27 #include "dc.h"
  28
  29 #include "vid.h"
  30 #include "amdgpu.h"
  31 #include "amdgpu_display.h"
  32 #include "atom.h"
  33 #include "amdgpu_dm.h"
  34 #include "amdgpu_pm.h"
  35
  36 #include "amd_shared.h"
  37 #include "amdgpu_dm_irq.h"
  38 #include "dm_helpers.h"
  39 #include "dm_services_types.h"
  40 #include "amdgpu_dm_mst_types.h"
  41
  42 #include "ivsrcid/ivsrcid_vislands30.h"
  43
  44 #include <linux/module.h>
  45 #include <linux/moduleparam.h>
  46 #include <linux/version.h>
  47 #include <linux/types.h>
  48
  49 #include <drm/drmP.h>
  50 #include <drm/drm_atomic.h>
  51 #include <drm/drm_atomic_helper.h>
  52 #include <drm/drm_dp_mst_helper.h>
  53 #include <drm/drm_fb_helper.h>
  54 #include <drm/drm_edid.h>
  55
  56 #include "modules/inc/mod_freesync.h"
  57
  58 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
  59 #include "ivsrcid/irqsrcs_dcn_1_0.h"
  60
  61 #include "raven1/DCN/dcn_1_0_offset.h"
  62 #include "raven1/DCN/dcn_1_0_sh_mask.h"
  63 #include "vega10/soc15ip.h"
  64
  65 #include "soc15_common.h"
  66 #endif
  67
  68 #include "modules/inc/mod_freesync.h"
  69
  70 #include "i2caux_interface.h"
  71
  72
  73 static enum drm_plane_type dm_plane_type_default[AMDGPU_MAX_PLANES] = {
  74         DRM_PLANE_TYPE_PRIMARY,
  75         DRM_PLANE_TYPE_PRIMARY,
  76         DRM_PLANE_TYPE_PRIMARY,
  77         DRM_PLANE_TYPE_PRIMARY,
  78         DRM_PLANE_TYPE_PRIMARY,
  79         DRM_PLANE_TYPE_PRIMARY,
  80 };
  81
  82 static enum drm_plane_type dm_plane_type_carizzo[AMDGPU_MAX_PLANES] = {
  83         DRM_PLANE_TYPE_PRIMARY,
  84         DRM_PLANE_TYPE_PRIMARY,
  85         DRM_PLANE_TYPE_PRIMARY,
  86         DRM_PLANE_TYPE_OVERLAY,/* YUV Capable Underlay */
  87 };
  88
  89 static enum drm_plane_type dm_plane_type_stoney[AMDGPU_MAX_PLANES] = {
  90         DRM_PLANE_TYPE_PRIMARY,
  91         DRM_PLANE_TYPE_PRIMARY,
  92         DRM_PLANE_TYPE_OVERLAY, /* YUV Capable Underlay */
  93 };
  94
  95 /*
  96  * dm_vblank_get_counter
  97  *
  98  * @brief
  99  * Get counter for number of vertical blanks
 100  *
 101  * @param
 102  * struct amdgpu_device *adev - [in] desired amdgpu device
 103  * int disp_idx - [in] which CRTC to get the counter from
 104  *
 105  * @return
 106  * Counter for vertical blanks
 107  */
 108 static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
 109 {
 110         if (crtc >= adev->mode_info.num_crtc)
 111                 return 0;
 112         else {
 113                 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
 114                 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
 115                                 acrtc->base.state);
 116
 117
 118                 if (acrtc_state->stream == NULL) {
 119                         DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
 120                                   crtc);
 121                         return 0;
 122                 }
 123
 124                 return dc_stream_get_vblank_counter(acrtc_state->stream);
 125         }
 126 }
 127
 128 static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
 129                                         u32 *vbl, u32 *position)
 130 {
 131         uint32_t v_blank_start, v_blank_end, h_position, v_position;
 132
 133         if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
 134                 return -EINVAL;
 135         else {
 136                 struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
 137                 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
 138                                                 acrtc->base.state);
 139
 140                 if (acrtc_state->stream ==  NULL) {
 141                         DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
 142                                   crtc);
 143                         return 0;
 144                 }
 145
 146                 /*
 147                  * TODO rework base driver to use values directly.
 148                  * for now parse it back into reg-format
 149                  */
 150                 dc_stream_get_scanoutpos(acrtc_state->stream,
 151                                          &v_blank_start,
 152                                          &v_blank_end,
 153                                          &h_position,
 154                                          &v_position);
 155
 156                 *position = v_position | (h_position << 16);
 157                 *vbl = v_blank_start | (v_blank_end << 16);
 158         }
 159
 160         return 0;
 161 }
 162
 163 static bool dm_is_idle(void *handle)
 164 {
 165         /* XXX todo */
 166         return true;
 167 }
 168
 169 static int dm_wait_for_idle(void *handle)
 170 {
 171         /* XXX todo */
 172         return 0;
 173 }
 174
 175 static bool dm_check_soft_reset(void *handle)
 176 {
 177         return false;
 178 }
 179
 180 static int dm_soft_reset(void *handle)
 181 {
 182         /* XXX todo */
 183         return 0;
 184 }
 185
 186 static struct amdgpu_crtc *get_crtc_by_otg_inst(
 187         struct amdgpu_device *adev,
 188         int otg_inst)
 189 {
 190         struct drm_device *dev = adev->ddev;
 191         struct drm_crtc *crtc;
 192         struct amdgpu_crtc *amdgpu_crtc;
 193
 194         /*
 195          * following if is check inherited from both functions where this one is
 196          * used now. Need to be checked why it could happen.
 197          */
 198         if (otg_inst == -1) {
 199                 WARN_ON(1);
 200                 return adev->mode_info.crtcs[0];
 201         }
 202
 203         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 204                 amdgpu_crtc = to_amdgpu_crtc(crtc);
 205
 206                 if (amdgpu_crtc->otg_inst == otg_inst)
 207                         return amdgpu_crtc;
 208         }
 209
 210         return NULL;
 211 }
 212
 213 static void dm_pflip_high_irq(void *interrupt_params)
 214 {
 215         struct amdgpu_crtc *amdgpu_crtc;
 216         struct common_irq_params *irq_params = interrupt_params;
 217         struct amdgpu_device *adev = irq_params->adev;
 218         unsigned long flags;
 219
 220         amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
 221
 222         /* IRQ could occur when in initial stage */
 223         /*TODO work and BO cleanup */
 224         if (amdgpu_crtc == NULL) {
 225                 DRM_DEBUG_DRIVER("CRTC is null, returning.\n");
 226                 return;
 227         }
 228
 229         spin_lock_irqsave(&adev->ddev->event_lock, flags);
 230
 231         if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
 232                 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
 233                                                  amdgpu_crtc->pflip_status,
 234                                                  AMDGPU_FLIP_SUBMITTED,
 235                                                  amdgpu_crtc->crtc_id,
 236                                                  amdgpu_crtc);
 237                 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
 238                 return;
 239         }
 240
 241
 242         /* wakeup usersapce */
 243         if (amdgpu_crtc->event) {
 244                 /* Update to correct count/ts if racing with vblank irq */
 245                 drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
 246
 247                 drm_crtc_send_vblank_event(&amdgpu_crtc->base, amdgpu_crtc->event);
 248
 249                 /* page flip completed. clean up */
 250                 amdgpu_crtc->event = NULL;
 251
 252         } else
 253                 WARN_ON(1);
 254
 255         amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
 256         spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
 257
 258         DRM_DEBUG_DRIVER("%s - crtc :%d[%p], pflip_stat:AMDGPU_FLIP_NONE\n",
 259                                         __func__, amdgpu_crtc->crtc_id, amdgpu_crtc);
 260
 261         drm_crtc_vblank_put(&amdgpu_crtc->base);
 262 }
 263
 264 static void dm_crtc_high_irq(void *interrupt_params)
 265 {
 266         struct common_irq_params *irq_params = interrupt_params;
 267         struct amdgpu_device *adev = irq_params->adev;
 268         uint8_t crtc_index = 0;
 269         struct amdgpu_crtc *acrtc;
 270
 271         acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
 272
 273         if (acrtc)
 274                 crtc_index = acrtc->crtc_id;
 275
 276         drm_handle_vblank(adev->ddev, crtc_index);
 277 }
 278
 279 static int dm_set_clockgating_state(void *handle,
 280                   enum amd_clockgating_state state)
 281 {
 282         return 0;
 283 }
 284
 285 static int dm_set_powergating_state(void *handle,
 286                   enum amd_powergating_state state)
 287 {
 288         return 0;
 289 }
 290
 291 /* Prototypes of private functions */
 292 static int dm_early_init(void* handle);
 293
 294 static void hotplug_notify_work_func(struct work_struct *work)
 295 {
 296         struct amdgpu_display_manager *dm = container_of(work, struct amdgpu_display_manager, mst_hotplug_work);
 297         struct drm_device *dev = dm->ddev;
 298
 299         drm_kms_helper_hotplug_event(dev);
 300 }
 301
 302 #ifdef ENABLE_FBC
 303 #include "dal_asic_id.h"
 304 /* Allocate memory for FBC compressed data  */
 305 /* TODO: Dynamic allocation */
 306 #define AMDGPU_FBC_SIZE    (3840 * 2160 * 4)
 307
 308 void amdgpu_dm_initialize_fbc(struct amdgpu_device *adev)
 309 {
 310         int r;
 311         struct dm_comressor_info *compressor = &adev->dm.compressor;
 312
 313         if (!compressor->bo_ptr) {
 314                 r = amdgpu_bo_create_kernel(adev, AMDGPU_FBC_SIZE, PAGE_SIZE,
 315                                 AMDGPU_GEM_DOMAIN_VRAM, &compressor->bo_ptr,
 316                                 &compressor->gpu_addr, &compressor->cpu_addr);
 317
 318                 if (r)
 319                         DRM_ERROR("DM: Failed to initialize fbc\n");
 320         }
 321
 322 }
 323 #endif
 324
 325
 326 /* Init display KMS
 327  *
 328  * Returns 0 on success
 329  */
 330 int amdgpu_dm_init(struct amdgpu_device *adev)
 331 {
 332         struct dc_init_data init_data;
 333         adev->dm.ddev = adev->ddev;
 334         adev->dm.adev = adev;
 335
 336         DRM_INFO("DAL is enabled\n");
 337         /* Zero all the fields */
 338         memset(&init_data, 0, sizeof(init_data));
 339
 340         /* initialize DAL's lock (for SYNC context use) */
 341         spin_lock_init(&adev->dm.dal_lock);
 342
 343         /* initialize DAL's mutex */
 344         mutex_init(&adev->dm.dal_mutex);
 345
 346         if(amdgpu_dm_irq_init(adev)) {
 347                 DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
 348                 goto error;
 349         }
 350
 351         init_data.asic_id.chip_family = adev->family;
 352
 353         init_data.asic_id.pci_revision_id = adev->rev_id;
 354         init_data.asic_id.hw_internal_rev = adev->external_rev_id;
 355
 356         init_data.asic_id.vram_width = adev->mc.vram_width;
 357         /* TODO: initialize init_data.asic_id.vram_type here!!!! */
 358         init_data.asic_id.atombios_base_address =
 359                 adev->mode_info.atom_context->bios;
 360
 361         init_data.driver = adev;
 362
 363         adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
 364
 365         if (!adev->dm.cgs_device) {
 366                 DRM_ERROR("amdgpu: failed to create cgs device.\n");
 367                 goto error;
 368         }
 369
 370         init_data.cgs_device = adev->dm.cgs_device;
 371
 372         adev->dm.dal = NULL;
 373
 374         init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
 375
 376 #ifdef ENABLE_FBC
 377         if (adev->family == FAMILY_CZ)
 378                 amdgpu_dm_initialize_fbc(adev);
 379         init_data.fbc_gpu_addr = adev->dm.compressor.gpu_addr;
 380 #endif
 381         /* Display Core create. */
 382         adev->dm.dc = dc_create(&init_data);
 383
 384         if (!adev->dm.dc)
 385                 DRM_INFO("Display Core failed to initialize!\n");
 386
 387         INIT_WORK(&adev->dm.mst_hotplug_work, hotplug_notify_work_func);
 388
 389         adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
 390         if (!adev->dm.freesync_module) {
 391                 DRM_ERROR(
 392                 "amdgpu: failed to initialize freesync_module.\n");
 393         } else
 394                 DRM_INFO("amdgpu: freesync_module init done %p.\n",
 395                                 adev->dm.freesync_module);
 396
 397         if (amdgpu_dm_initialize_drm_device(adev)) {
 398                 DRM_ERROR(
 399                 "amdgpu: failed to initialize sw for display support.\n");
 400                 goto error;
 401         }
 402
 403         /* Update the actual used number of crtc */
 404         adev->mode_info.num_crtc = adev->dm.display_indexes_num;
 405
 406         /* TODO: Add_display_info? */
 407
 408         /* TODO use dynamic cursor width */
 409         adev->ddev->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
 410         adev->ddev->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
 411
 412         if (drm_vblank_init(adev->ddev, adev->dm.display_indexes_num)) {
 413                 DRM_ERROR(
 414                 "amdgpu: failed to initialize sw for display support.\n");
 415                 goto error;
 416         }
 417
 418         DRM_INFO("KMS initialized.\n");
 419
 420         return 0;
 421 error:
 422         amdgpu_dm_fini(adev);
 423
 424         return -1;
 425 }
 426
 427 void amdgpu_dm_fini(struct amdgpu_device *adev)
 428 {
 429         amdgpu_dm_destroy_drm_device(&adev->dm);
 430         /*
 431          * TODO: pageflip, vlank interrupt
 432          *
 433          * amdgpu_dm_irq_fini(adev);
 434          */
 435
 436         if (adev->dm.cgs_device) {
 437                 amdgpu_cgs_destroy_device(adev->dm.cgs_device);
 438                 adev->dm.cgs_device = NULL;
 439         }
 440         if (adev->dm.freesync_module) {
 441                 mod_freesync_destroy(adev->dm.freesync_module);
 442                 adev->dm.freesync_module = NULL;
 443         }
 444         /* DC Destroy TODO: Replace destroy DAL */
 445         if (adev->dm.dc)
 446                 dc_destroy(&adev->dm.dc);
 447         return;
 448 }
 449
 450 /* moved from amdgpu_dm_kms.c */
 451 void amdgpu_dm_destroy()
 452 {
 453 }
 454
 455 static int dm_sw_init(void *handle)
 456 {
 457         return 0;
 458 }
 459
 460 static int dm_sw_fini(void *handle)
 461 {
 462         return 0;
 463 }
 464
 465 static int detect_mst_link_for_all_connectors(struct drm_device *dev)
 466 {
 467         struct amdgpu_connector *aconnector;
 468         struct drm_connector *connector;
 469         int ret = 0;
 470
 471         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
 472
 473         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 474                    aconnector = to_amdgpu_connector(connector);
 475                 if (aconnector->dc_link->type == dc_connection_mst_branch) {
 476                         DRM_INFO("DM_MST: starting TM on aconnector: %p [id: %d]\n",
 477                                         aconnector, aconnector->base.base.id);
 478
 479                         ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
 480                         if (ret < 0) {
 481                                 DRM_ERROR("DM_MST: Failed to start MST\n");
 482                                 ((struct dc_link *)aconnector->dc_link)->type = dc_connection_single;
 483                                 return ret;
 484                                 }
 485                         }
 486         }
 487
 488         drm_modeset_unlock(&dev->mode_config.connection_mutex);
 489         return ret;
 490 }
 491
 492 static int dm_late_init(void *handle)
 493 {
 494         struct drm_device *dev = ((struct amdgpu_device *)handle)->ddev;
 495         int r = detect_mst_link_for_all_connectors(dev);
 496
 497         return r;
 498 }
 499
 500 static void s3_handle_mst(struct drm_device *dev, bool suspend)
 501 {
 502         struct amdgpu_connector *aconnector;
 503         struct drm_connector *connector;
 504
 505         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
 506
 507         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 508                    aconnector = to_amdgpu_connector(connector);
 509                    if (aconnector->dc_link->type == dc_connection_mst_branch &&
 510                                    !aconnector->mst_port) {
 511
 512                            if (suspend)
 513                                    drm_dp_mst_topology_mgr_suspend(&aconnector->mst_mgr);
 514                            else
 515                                    drm_dp_mst_topology_mgr_resume(&aconnector->mst_mgr);
 516                    }
 517         }
 518
 519         drm_modeset_unlock(&dev->mode_config.connection_mutex);
 520 }
 521
 522 static int dm_hw_init(void *handle)
 523 {
 524         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 525         /* Create DAL display manager */
 526         amdgpu_dm_init(adev);
 527         amdgpu_dm_hpd_init(adev);
 528
 529         return 0;
 530 }
 531
 532 static int dm_hw_fini(void *handle)
 533 {
 534         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 535
 536         amdgpu_dm_hpd_fini(adev);
 537
 538         amdgpu_dm_irq_fini(adev);
 539         amdgpu_dm_fini(adev);
 540         return 0;
 541 }
 542
 543 static int dm_suspend(void *handle)
 544 {
 545         struct amdgpu_device *adev = handle;
 546         struct amdgpu_display_manager *dm = &adev->dm;
 547         int ret = 0;
 548
 549         s3_handle_mst(adev->ddev, true);
 550
 551         amdgpu_dm_irq_suspend(adev);
 552
 553         WARN_ON(adev->dm.cached_state);
 554         adev->dm.cached_state = drm_atomic_helper_suspend(adev->ddev);
 555
 556         dc_set_power_state(
 557                 dm->dc,
 558                 DC_ACPI_CM_POWER_STATE_D3
 559                 );
 560
 561         return ret;
 562 }
 563
 564 struct amdgpu_connector *amdgpu_dm_find_first_crct_matching_connector(
 565         struct drm_atomic_state *state,
 566         struct drm_crtc *crtc,
 567         bool from_state_var)
 568 {
 569         uint32_t i;
 570         struct drm_connector_state *conn_state;
 571         struct drm_connector *connector;
 572         struct drm_crtc *crtc_from_state;
 573
 574         for_each_connector_in_state(
 575                 state,
 576                 connector,
 577                 conn_state,
 578                 i) {
 579                 crtc_from_state =
 580                         from_state_var ?
 581                                 conn_state->crtc :
 582                                 connector->state->crtc;
 583
 584                 if (crtc_from_state == crtc)
 585                         return to_amdgpu_connector(connector);
 586         }
 587
 588         return NULL;
 589 }
 590
 591 static int dm_resume(void *handle)
 592 {
 593         struct amdgpu_device *adev = handle;
 594         struct amdgpu_display_manager *dm = &adev->dm;
 595
 596         /* power on hardware */
 597         dc_set_power_state(
 598                 dm->dc,
 599                 DC_ACPI_CM_POWER_STATE_D0
 600                 );
 601
 602         return 0;
 603 }
 604
 605 int amdgpu_dm_display_resume(struct amdgpu_device *adev )
 606 {
 607         struct drm_device *ddev = adev->ddev;
 608         struct amdgpu_display_manager *dm = &adev->dm;
 609         struct amdgpu_connector *aconnector;
 610         struct drm_connector *connector;
 611         struct drm_crtc *crtc;
 612         struct drm_crtc_state *crtc_state;
 613         int ret = 0;
 614         int i;
 615
 616         /* program HPD filter */
 617         dc_resume(dm->dc);
 618
 619         /* On resume we need to  rewrite the MSTM control bits to enamble MST*/
 620         s3_handle_mst(ddev, false);
 621
 622         /*
 623          * early enable HPD Rx IRQ, should be done before set mode as short
 624          * pulse interrupts are used for MST
 625          */
 626         amdgpu_dm_irq_resume_early(adev);
 627
 628         /* Do detection*/
 629         list_for_each_entry(connector,
 630                         &ddev->mode_config.connector_list, head) {
 631                 aconnector = to_amdgpu_connector(connector);
 632
 633                 /*
 634                  * this is the case when traversing through already created
 635                  * MST connectors, should be skipped
 636                  */
 637                 if (aconnector->mst_port)
 638                         continue;
 639
 640                 mutex_lock(&aconnector->hpd_lock);
 641                 dc_link_detect(aconnector->dc_link, false);
 642                 aconnector->dc_sink = NULL;
 643                 amdgpu_dm_update_connector_after_detect(aconnector);
 644                 mutex_unlock(&aconnector->hpd_lock);
 645         }
 646
 647         /* Force mode set in atomic comit */
 648         for_each_crtc_in_state(adev->dm.cached_state, crtc, crtc_state, i)
 649                         crtc_state->active_changed = true;
 650
 651         ret = drm_atomic_helper_resume(ddev, adev->dm.cached_state);
 652
 653         drm_atomic_state_put(adev->dm.cached_state);
 654         adev->dm.cached_state = NULL;
 655
 656         amdgpu_dm_irq_resume_late(adev);
 657
 658         return ret;
 659 }
 660
 661 static const struct amd_ip_funcs amdgpu_dm_funcs = {
 662         .name = "dm",
 663         .early_init = dm_early_init,
 664         .late_init = dm_late_init,
 665         .sw_init = dm_sw_init,
 666         .sw_fini = dm_sw_fini,
 667         .hw_init = dm_hw_init,
 668         .hw_fini = dm_hw_fini,
 669         .suspend = dm_suspend,
 670         .resume = dm_resume,
 671         .is_idle = dm_is_idle,
 672         .wait_for_idle = dm_wait_for_idle,
 673         .check_soft_reset = dm_check_soft_reset,
 674         .soft_reset = dm_soft_reset,
 675         .set_clockgating_state = dm_set_clockgating_state,
 676         .set_powergating_state = dm_set_powergating_state,
 677 };
 678
 679 const struct amdgpu_ip_block_version dm_ip_block =
 680 {
 681         .type = AMD_IP_BLOCK_TYPE_DCE,
 682         .major = 1,
 683         .minor = 0,
 684         .rev = 0,
 685         .funcs = &amdgpu_dm_funcs,
 686 };
 687
 688
 689 struct drm_atomic_state *
 690 dm_atomic_state_alloc(struct drm_device *dev)
 691 {
 692         struct dm_atomic_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
 693
 694         if (!state || drm_atomic_state_init(dev, &state->base) < 0) {
 695                 kfree(state);
 696                 return NULL;
 697         }
 698
 699         return &state->base;
 700 }
 701
 702 static void
 703 dm_atomic_state_clear(struct drm_atomic_state *state)
 704 {
 705         struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
 706
 707         if (dm_state->context) {
 708                 dc_release_validate_context(dm_state->context);
 709                 dm_state->context = NULL;
 710         }
 711
 712         drm_atomic_state_default_clear(state);
 713 }
 714
 715 static void
 716 dm_atomic_state_alloc_free(struct drm_atomic_state *state)
 717 {
 718         struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
 719         drm_atomic_state_default_release(state);
 720         kfree(dm_state);
 721 }
 722
 723 static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
 724         .fb_create = amdgpu_user_framebuffer_create,
 725         .output_poll_changed = amdgpu_output_poll_changed,
 726         .atomic_check = amdgpu_dm_atomic_check,
 727         .atomic_commit = amdgpu_dm_atomic_commit,
 728         .atomic_state_alloc = dm_atomic_state_alloc,
 729         .atomic_state_clear = dm_atomic_state_clear,
 730         .atomic_state_free = dm_atomic_state_alloc_free
 731 };
 732
 733 static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
 734         .atomic_commit_tail = amdgpu_dm_atomic_commit_tail
 735 };
 736
 737 void amdgpu_dm_update_connector_after_detect(
 738         struct amdgpu_connector *aconnector)
 739 {
 740         struct drm_connector *connector = &aconnector->base;
 741         struct drm_device *dev = connector->dev;
 742         struct dc_sink *sink;
 743
 744         /* MST handled by drm_mst framework */
 745         if (aconnector->mst_mgr.mst_state == true)
 746                 return;
 747
 748
 749         sink = aconnector->dc_link->local_sink;
 750
 751         /* Edid mgmt connector gets first update only in mode_valid hook and then
 752          * the connector sink is set to either fake or physical sink depends on link status.
 753          * don't do it here if u are during boot
 754          */
 755         if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
 756                         && aconnector->dc_em_sink) {
 757
 758                 /* For S3 resume with headless use eml_sink to fake stream
 759                  * because on resume connecotr->sink is set ti NULL
 760                  */
 761                 mutex_lock(&dev->mode_config.mutex);
 762
 763                 if (sink) {
 764                         if (aconnector->dc_sink) {
 765                                 amdgpu_dm_remove_sink_from_freesync_module(
 766                                                                 connector);
 767                                 /* retain and release bellow are used for
 768                                  * bump up refcount for sink because the link don't point
 769                                  * to it anymore after disconnect so on next crtc to connector
 770                                  * reshuffle by UMD we will get into unwanted dc_sink release
 771                                  */
 772                                 if (aconnector->dc_sink != aconnector->dc_em_sink)
 773                                         dc_sink_release(aconnector->dc_sink);
 774                         }
 775                         aconnector->dc_sink = sink;
 776                         amdgpu_dm_add_sink_to_freesync_module(
 777                                                 connector, aconnector->edid);
 778                 } else {
 779                         amdgpu_dm_remove_sink_from_freesync_module(connector);
 780                         if (!aconnector->dc_sink)
 781                                 aconnector->dc_sink = aconnector->dc_em_sink;
 782                         else if (aconnector->dc_sink != aconnector->dc_em_sink)
 783                                 dc_sink_retain(aconnector->dc_sink);
 784                 }
 785
 786                 mutex_unlock(&dev->mode_config.mutex);
 787                 return;
 788         }
 789
 790         /*
 791          * TODO: temporary guard to look for proper fix
 792          * if this sink is MST sink, we should not do anything
 793          */
 794         if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
 795                 return;
 796
 797         if (aconnector->dc_sink == sink) {
 798                 /* We got a DP short pulse (Link Loss, DP CTS, etc...).
 799                  * Do nothing!! */
 800                 DRM_INFO("DCHPD: connector_id=%d: dc_sink didn't change.\n",
 801                                 aconnector->connector_id);
 802                 return;
 803         }
 804
 805         DRM_INFO("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
 806                 aconnector->connector_id, aconnector->dc_sink, sink);
 807
 808         mutex_lock(&dev->mode_config.mutex);
 809
 810         /* 1. Update status of the drm connector
 811          * 2. Send an event and let userspace tell us what to do */
 812         if (sink) {
 813                 /* TODO: check if we still need the S3 mode update workaround.
 814                  * If yes, put it here. */
 815                 if (aconnector->dc_sink)
 816                         amdgpu_dm_remove_sink_from_freesync_module(
 817                                                         connector);
 818
 819                 aconnector->dc_sink = sink;
 820                 if (sink->dc_edid.length == 0)
 821                         aconnector->edid = NULL;
 822                 else {
 823                         aconnector->edid =
 824                                 (struct edid *) sink->dc_edid.raw_edid;
 825
 826
 827                         drm_mode_connector_update_edid_property(connector,
 828                                         aconnector->edid);
 829                 }
 830                 amdgpu_dm_add_sink_to_freesync_module(connector, aconnector->edid);
 831
 832         } else {
 833                 amdgpu_dm_remove_sink_from_freesync_module(connector);
 834                 drm_mode_connector_update_edid_property(connector, NULL);
 835                 aconnector->num_modes = 0;
 836                 aconnector->dc_sink = NULL;
 837         }
 838
 839         mutex_unlock(&dev->mode_config.mutex);
 840 }
 841
 842 static void handle_hpd_irq(void *param)
 843 {
 844         struct amdgpu_connector *aconnector = (struct amdgpu_connector *)param;
 845         struct drm_connector *connector = &aconnector->base;
 846         struct drm_device *dev = connector->dev;
 847
 848         /* In case of failure or MST no need to update connector status or notify the OS
 849          * since (for MST case) MST does this in it's own context.
 850          */
 851         mutex_lock(&aconnector->hpd_lock);
 852         if (dc_link_detect(aconnector->dc_link, false)) {
 853                 amdgpu_dm_update_connector_after_detect(aconnector);
 854
 855
 856                 drm_modeset_lock_all(dev);
 857                 dm_restore_drm_connector_state(dev, connector);
 858                 drm_modeset_unlock_all(dev);
 859
 860                 if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
 861                         drm_kms_helper_hotplug_event(dev);
 862         }
 863         mutex_unlock(&aconnector->hpd_lock);
 864
 865 }
 866
 867 static void dm_handle_hpd_rx_irq(struct amdgpu_connector *aconnector)
 868 {
 869         uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
 870         uint8_t dret;
 871         bool new_irq_handled = false;
 872         int dpcd_addr;
 873         int dpcd_bytes_to_read;
 874
 875         const int max_process_count = 30;
 876         int process_count = 0;
 877
 878         const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
 879
 880         if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
 881                 dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
 882                 /* DPCD 0x200 - 0x201 for downstream IRQ */
 883                 dpcd_addr = DP_SINK_COUNT;
 884         } else {
 885                 dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
 886                 /* DPCD 0x2002 - 0x2005 for downstream IRQ */
 887                 dpcd_addr = DP_SINK_COUNT_ESI;
 888         }
 889
 890         dret = drm_dp_dpcd_read(
 891                 &aconnector->dm_dp_aux.aux,
 892                 dpcd_addr,
 893                 esi,
 894                 dpcd_bytes_to_read);
 895
 896         while (dret == dpcd_bytes_to_read &&
 897                 process_count < max_process_count) {
 898                 uint8_t retry;
 899                 dret = 0;
 900
 901                 process_count++;
 902
 903                 DRM_DEBUG_KMS("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
 904                 /* handle HPD short pulse irq */
 905                 if (aconnector->mst_mgr.mst_state)
 906                         drm_dp_mst_hpd_irq(
 907                                 &aconnector->mst_mgr,
 908                                 esi,
 909                                 &new_irq_handled);
 910
 911                 if (new_irq_handled) {
 912                         /* ACK at DPCD to notify down stream */
 913                         const int ack_dpcd_bytes_to_write =
 914                                 dpcd_bytes_to_read - 1;
 915
 916                         for (retry = 0; retry < 3; retry++) {
 917                                 uint8_t wret;
 918
 919                                 wret = drm_dp_dpcd_write(
 920                                         &aconnector->dm_dp_aux.aux,
 921                                         dpcd_addr + 1,
 922                                         &esi[1],
 923                                         ack_dpcd_bytes_to_write);
 924                                 if (wret == ack_dpcd_bytes_to_write)
 925                                         break;
 926                         }
 927
 928                         /* check if there is new irq to be handle */
 929                         dret = drm_dp_dpcd_read(
 930                                 &aconnector->dm_dp_aux.aux,
 931                                 dpcd_addr,
 932                                 esi,
 933                                 dpcd_bytes_to_read);
 934
 935                         new_irq_handled = false;
 936                 } else
 937                         break;
 938         }
 939
 940         if (process_count == max_process_count)
 941                 DRM_DEBUG_KMS("Loop exceeded max iterations\n");
 942 }
 943
 944 static void handle_hpd_rx_irq(void *param)
 945 {
 946         struct amdgpu_connector *aconnector = (struct amdgpu_connector *)param;
 947         struct drm_connector *connector = &aconnector->base;
 948         struct drm_device *dev = connector->dev;
 949         const struct dc_link *dc_link = aconnector->dc_link;
 950         bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
 951
 952         /* TODO:Temporary add mutex to protect hpd interrupt not have a gpio
 953          * conflict, after implement i2c helper, this mutex should be
 954          * retired.
 955          */
 956         if (aconnector->dc_link->type != dc_connection_mst_branch)
 957                 mutex_lock(&aconnector->hpd_lock);
 958
 959         if (dc_link_handle_hpd_rx_irq(aconnector->dc_link, NULL) &&
 960                         !is_mst_root_connector) {
 961                 /* Downstream Port status changed. */
 962                 if (dc_link_detect(aconnector->dc_link, false)) {
 963                         amdgpu_dm_update_connector_after_detect(aconnector);
 964
 965
 966                         drm_modeset_lock_all(dev);
 967                         dm_restore_drm_connector_state(dev, connector);
 968                         drm_modeset_unlock_all(dev);
 969
 970                         drm_kms_helper_hotplug_event(dev);
 971                 }
 972         }
 973         if ((dc_link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
 974                                 (dc_link->type == dc_connection_mst_branch))
 975                 dm_handle_hpd_rx_irq(aconnector);
 976
 977         if (aconnector->dc_link->type != dc_connection_mst_branch)
 978                 mutex_unlock(&aconnector->hpd_lock);
 979 }
 980
 981 static void register_hpd_handlers(struct amdgpu_device *adev)
 982 {
 983         struct drm_device *dev = adev->ddev;
 984         struct drm_connector *connector;
 985         struct amdgpu_connector *aconnector;
 986         const struct dc_link *dc_link;
 987         struct dc_interrupt_params int_params = {0};
 988
 989         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
 990         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
 991
 992         list_for_each_entry(connector,
 993                         &dev->mode_config.connector_list, head) {
 994
 995                 aconnector = to_amdgpu_connector(connector);
 996                 dc_link = aconnector->dc_link;
 997
 998                 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
 999                         int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1000                         int_params.irq_source = dc_link->irq_source_hpd;
1001
1002                         amdgpu_dm_irq_register_interrupt(adev, &int_params,
1003                                         handle_hpd_irq,
1004                                         (void *) aconnector);
1005                 }
1006
1007                 if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
1008
1009                         /* Also register for DP short pulse (hpd_rx). */
1010                         int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1011                         int_params.irq_source = dc_link->irq_source_hpd_rx;
1012
1013                         amdgpu_dm_irq_register_interrupt(adev, &int_params,
1014                                         handle_hpd_rx_irq,
1015                                         (void *) aconnector);
1016                 }
1017         }
1018 }
1019
1020 /* Register IRQ sources and initialize IRQ callbacks */
1021 static int dce110_register_irq_handlers(struct amdgpu_device *adev)
1022 {
1023         struct dc *dc = adev->dm.dc;
1024         struct common_irq_params *c_irq_params;
1025         struct dc_interrupt_params int_params = {0};
1026         int r;
1027         int i;
1028         unsigned client_id = AMDGPU_IH_CLIENTID_LEGACY;
1029
1030         if (adev->asic_type == CHIP_VEGA10 ||
1031             adev->asic_type == CHIP_RAVEN)
1032                 client_id = AMDGPU_IH_CLIENTID_DCE;
1033
1034         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1035         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1036
1037         /* Actions of amdgpu_irq_add_id():
1038          * 1. Register a set() function with base driver.
1039          *    Base driver will call set() function to enable/disable an
1040          *    interrupt in DC hardware.
1041          * 2. Register amdgpu_dm_irq_handler().
1042          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1043          *    coming from DC hardware.
1044          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1045          *    for acknowledging and handling. */
1046
1047         /* Use VBLANK interrupt */
1048         for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
1049                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
1050                 if (r) {
1051                         DRM_ERROR("Failed to add crtc irq id!\n");
1052                         return r;
1053                 }
1054
1055                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1056                 int_params.irq_source =
1057                         dc_interrupt_to_irq_source(dc, i, 0);
1058
1059                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
1060
1061                 c_irq_params->adev = adev;
1062                 c_irq_params->irq_src = int_params.irq_source;
1063
1064                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1065                                 dm_crtc_high_irq, c_irq_params);
1066         }
1067
1068         /* Use GRPH_PFLIP interrupt */
1069         for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
1070                         i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
1071                 r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
1072                 if (r) {
1073                         DRM_ERROR("Failed to add page flip irq id!\n");
1074                         return r;
1075                 }
1076
1077                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1078                 int_params.irq_source =
1079                         dc_interrupt_to_irq_source(dc, i, 0);
1080
1081                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1082
1083                 c_irq_params->adev = adev;
1084                 c_irq_params->irq_src = int_params.irq_source;
1085
1086                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1087                                 dm_pflip_high_irq, c_irq_params);
1088
1089         }
1090
1091         /* HPD */
1092         r = amdgpu_irq_add_id(adev, client_id,
1093                         VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
1094         if (r) {
1095                 DRM_ERROR("Failed to add hpd irq id!\n");
1096                 return r;
1097         }
1098
1099         register_hpd_handlers(adev);
1100
1101         return 0;
1102 }
1103
1104 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1105 /* Register IRQ sources and initialize IRQ callbacks */
1106 static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
1107 {
1108         struct dc *dc = adev->dm.dc;
1109         struct common_irq_params *c_irq_params;
1110         struct dc_interrupt_params int_params = {0};
1111         int r;
1112         int i;
1113
1114         int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1115         int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1116
1117         /* Actions of amdgpu_irq_add_id():
1118          * 1. Register a set() function with base driver.
1119          *    Base driver will call set() function to enable/disable an
1120          *    interrupt in DC hardware.
1121          * 2. Register amdgpu_dm_irq_handler().
1122          *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1123          *    coming from DC hardware.
1124          *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1125          *    for acknowledging and handling.
1126          * */
1127
1128         /* Use VSTARTUP interrupt */
1129         for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
1130                         i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
1131                         i++) {
1132                 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_DCE, i, &adev->crtc_irq);
1133
1134                 if (r) {
1135                         DRM_ERROR("Failed to add crtc irq id!\n");
1136                         return r;
1137                 }
1138
1139                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1140                 int_params.irq_source =
1141                         dc_interrupt_to_irq_source(dc, i, 0);
1142
1143                 c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
1144
1145                 c_irq_params->adev = adev;
1146                 c_irq_params->irq_src = int_params.irq_source;
1147
1148                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1149                                 dm_crtc_high_irq, c_irq_params);
1150         }
1151
1152         /* Use GRPH_PFLIP interrupt */
1153         for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
1154                         i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1;
1155                         i++) {
1156                 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
1157                 if (r) {
1158                         DRM_ERROR("Failed to add page flip irq id!\n");
1159                         return r;
1160                 }
1161
1162                 int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1163                 int_params.irq_source =
1164                         dc_interrupt_to_irq_source(dc, i, 0);
1165
1166                 c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1167
1168                 c_irq_params->adev = adev;
1169                 c_irq_params->irq_src = int_params.irq_source;
1170
1171                 amdgpu_dm_irq_register_interrupt(adev, &int_params,
1172                                 dm_pflip_high_irq, c_irq_params);
1173
1174         }
1175
1176         /* HPD */
1177         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
1178                         &adev->hpd_irq);
1179         if (r) {
1180                 DRM_ERROR("Failed to add hpd irq id!\n");
1181                 return r;
1182         }
1183
1184         register_hpd_handlers(adev);
1185
1186         return 0;
1187 }
1188 #endif
1189
1190 static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
1191 {
1192         int r;
1193
1194         adev->mode_info.mode_config_initialized = true;
1195
1196         adev->ddev->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
1197         adev->ddev->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
1198
1199         adev->ddev->mode_config.max_width = 16384;
1200         adev->ddev->mode_config.max_height = 16384;
1201
1202         adev->ddev->mode_config.preferred_depth = 24;
1203         adev->ddev->mode_config.prefer_shadow = 1;
1204         /* indicate support of immediate flip */
1205         adev->ddev->mode_config.async_page_flip = true;
1206
1207         adev->ddev->mode_config.fb_base = adev->mc.aper_base;
1208
1209         r = amdgpu_modeset_create_props(adev);
1210         if (r)
1211                 return r;
1212
1213         return 0;
1214 }
1215
1216 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
1217         defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
1218
1219 static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
1220 {
1221         struct amdgpu_display_manager *dm = bl_get_data(bd);
1222
1223         if (dc_link_set_backlight_level(dm->backlight_link,
1224                         bd->props.brightness, 0, 0))
1225                 return 0;
1226         else
1227                 return 1;
1228 }
1229
1230 static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
1231 {
1232         return bd->props.brightness;
1233 }
1234
1235 static const struct backlight_ops amdgpu_dm_backlight_ops = {
1236         .get_brightness = amdgpu_dm_backlight_get_brightness,
1237         .update_status  = amdgpu_dm_backlight_update_status,
1238 };
1239
1240 void amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm)
1241 {
1242         char bl_name[16];
1243         struct backlight_properties props = { 0 };
1244
1245         props.max_brightness = AMDGPU_MAX_BL_LEVEL;
1246         props.type = BACKLIGHT_RAW;
1247
1248         snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
1249                         dm->adev->ddev->primary->index);
1250
1251         dm->backlight_dev = backlight_device_register(bl_name,
1252                         dm->adev->ddev->dev,
1253                         dm,
1254                         &amdgpu_dm_backlight_ops,
1255                         &props);
1256
1257         if (NULL == dm->backlight_dev)
1258                 DRM_ERROR("DM: Backlight registration failed!\n");
1259         else
1260                 DRM_INFO("DM: Registered Backlight device: %s\n", bl_name);
1261 }
1262
1263 #endif
1264
1265 /* In this architecture, the association
1266  * connector -> encoder -> crtc
1267  * id not really requried. The crtc and connector will hold the
1268  * display_index as an abstraction to use with DAL component
1269  *
1270  * Returns 0 on success
1271  */
1272 int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
1273 {
1274         struct amdgpu_display_manager *dm = &adev->dm;
1275         uint32_t i;
1276         struct amdgpu_connector *aconnector = NULL;
1277         struct amdgpu_encoder *aencoder = NULL;
1278         struct amdgpu_mode_info *mode_info = &adev->mode_info;
1279         uint32_t link_cnt;
1280         unsigned long possible_crtcs;
1281
1282         link_cnt = dm->dc->caps.max_links;
1283         if (amdgpu_dm_mode_config_init(dm->adev)) {
1284                 DRM_ERROR("DM: Failed to initialize mode config\n");
1285                 return -1;
1286         }
1287
1288         for (i = 0; i < dm->dc->caps.max_planes; i++) {
1289                 mode_info->planes[i] = kzalloc(sizeof(struct amdgpu_plane),
1290                                                                  GFP_KERNEL);
1291                 if (!mode_info->planes[i]) {
1292                         DRM_ERROR("KMS: Failed to allocate plane\n");
1293                         goto fail_free_planes;
1294                 }
1295                 mode_info->planes[i]->base.type = mode_info->plane_type[i];
1296
1297                 /*
1298                  * HACK: IGT tests expect that each plane can only have one
1299                  * one possible CRTC. For now, set one CRTC for each
1300                  * plane that is not an underlay, but still allow multiple
1301                  * CRTCs for underlay planes.
1302                  */
1303                 possible_crtcs = 1 << i;
1304                 if (i >= dm->dc->caps.max_streams)
1305                         possible_crtcs = 0xff;
1306
1307                 if (amdgpu_dm_plane_init(dm, mode_info->planes[i], possible_crtcs)) {
1308                         DRM_ERROR("KMS: Failed to initialize plane\n");
1309                         goto fail_free_planes;
1310                 }
1311         }
1312
1313         for (i = 0; i < dm->dc->caps.max_streams; i++)
1314                 if (amdgpu_dm_crtc_init(dm, &mode_info->planes[i]->base, i)) {
1315                         DRM_ERROR("KMS: Failed to initialize crtc\n");
1316                         goto fail_free_planes;
1317                 }
1318
1319         dm->display_indexes_num = dm->dc->caps.max_streams;
1320
1321         /* loops over all connectors on the board */
1322         for (i = 0; i < link_cnt; i++) {
1323
1324                 if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
1325                         DRM_ERROR(
1326                                 "KMS: Cannot support more than %d display indexes\n",
1327                                         AMDGPU_DM_MAX_DISPLAY_INDEX);
1328                         continue;
1329                 }
1330
1331                 aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
1332                 if (!aconnector)
1333                         goto fail_free_planes;
1334
1335                 aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
1336                 if (!aencoder) {
1337                         goto fail_free_connector;
1338                 }
1339
1340                 if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
1341                         DRM_ERROR("KMS: Failed to initialize encoder\n");
1342                         goto fail_free_encoder;
1343                 }
1344
1345                 if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
1346                         DRM_ERROR("KMS: Failed to initialize connector\n");
1347                         goto fail_free_encoder;
1348                 }
1349
1350                 if (dc_link_detect(dc_get_link_at_index(dm->dc, i), true))
1351                         amdgpu_dm_update_connector_after_detect(aconnector);
1352         }
1353
1354         /* Software is initialized. Now we can register interrupt handlers. */
1355         switch (adev->asic_type) {
1356         case CHIP_BONAIRE:
1357         case CHIP_HAWAII:
1358         case CHIP_TONGA:
1359         case CHIP_FIJI:
1360         case CHIP_CARRIZO:
1361         case CHIP_STONEY:
1362         case CHIP_POLARIS11:
1363         case CHIP_POLARIS10:
1364         case CHIP_POLARIS12:
1365         case CHIP_VEGA10:
1366                 if (dce110_register_irq_handlers(dm->adev)) {
1367                         DRM_ERROR("DM: Failed to initialize IRQ\n");
1368                         goto fail_free_encoder;
1369                 }
1370                 break;
1371 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1372         case CHIP_RAVEN:
1373                 if (dcn10_register_irq_handlers(dm->adev)) {
1374                         DRM_ERROR("DM: Failed to initialize IRQ\n");
1375                         goto fail_free_encoder;
1376                 }
1377                 break;
1378 #endif
1379         default:
1380                 DRM_ERROR("Usupported ASIC type: 0x%X\n", adev->asic_type);
1381                 goto fail_free_encoder;
1382         }
1383
1384         drm_mode_config_reset(dm->ddev);
1385
1386         return 0;
1387 fail_free_encoder:
1388         kfree(aencoder);
1389 fail_free_connector:
1390         kfree(aconnector);
1391 fail_free_planes:
1392         for (i = 0; i < dm->dc->caps.max_planes; i++)
1393                 kfree(mode_info->planes[i]);
1394         return -1;
1395 }
1396
1397 void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
1398 {
1399         drm_mode_config_cleanup(dm->ddev);
1400         return;
1401 }
1402
1403 /******************************************************************************
1404  * amdgpu_display_funcs functions
1405  *****************************************************************************/
1406
1407 /**
1408  * dm_bandwidth_update - program display watermarks
1409  *
1410  * @adev: amdgpu_device pointer
1411  *
1412  * Calculate and program the display watermarks and line buffer allocation.
1413  */
1414 static void dm_bandwidth_update(struct amdgpu_device *adev)
1415 {
1416         /* TODO: implement later */
1417 }
1418
1419 static void dm_set_backlight_level(struct amdgpu_encoder *amdgpu_encoder,
1420                                      u8 level)
1421 {
1422         /* TODO: translate amdgpu_encoder to display_index and call DAL */
1423 }
1424
1425 static u8 dm_get_backlight_level(struct amdgpu_encoder *amdgpu_encoder)
1426 {
1427         /* TODO: translate amdgpu_encoder to display_index and call DAL */
1428         return 0;
1429 }
1430
1431 static int amdgpu_notify_freesync(struct drm_device *dev, void *data,
1432                                 struct drm_file *filp)
1433 {
1434         struct mod_freesync_params freesync_params;
1435         uint8_t num_streams;
1436         uint8_t i;
1437
1438         struct amdgpu_device *adev = dev->dev_private;
1439         int r = 0;
1440
1441         /* Get freesync enable flag from DRM */
1442
1443         num_streams = dc_get_current_stream_count(adev->dm.dc);
1444
1445         for (i = 0; i < num_streams; i++) {
1446                 struct dc_stream_state *stream;
1447                 stream = dc_get_stream_at_index(adev->dm.dc, i);
1448
1449                 mod_freesync_update_state(adev->dm.freesync_module,
1450                                           &stream, 1, &freesync_params);
1451         }
1452
1453         return r;
1454 }
1455
1456 static const struct amdgpu_display_funcs dm_display_funcs = {
1457         .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
1458         .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
1459         .vblank_wait = NULL,
1460         .backlight_set_level =
1461                 dm_set_backlight_level,/* called unconditionally */
1462         .backlight_get_level =
1463                 dm_get_backlight_level,/* called unconditionally */
1464         .hpd_sense = NULL,/* called unconditionally */
1465         .hpd_set_polarity = NULL, /* called unconditionally */
1466         .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
1467         .page_flip_get_scanoutpos =
1468                 dm_crtc_get_scanoutpos,/* called unconditionally */
1469         .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
1470         .add_connector = NULL, /* VBIOS parsing. DAL does it. */
1471         .notify_freesync = amdgpu_notify_freesync,
1472
1473 };
1474
1475
1476 #if defined(CONFIG_DEBUG_KERNEL_DC)
1477
1478 static ssize_t s3_debug_store(
1479         struct device *device,
1480         struct device_attribute *attr,
1481         const char *buf,
1482         size_t count)
1483 {
1484         int ret;
1485         int s3_state;
1486         struct pci_dev *pdev = to_pci_dev(device);
1487         struct drm_device *drm_dev = pci_get_drvdata(pdev);
1488         struct amdgpu_device *adev = drm_dev->dev_private;
1489
1490         ret = kstrtoint(buf, 0, &s3_state);
1491
1492         if (ret == 0) {
1493                 if (s3_state) {
1494                         dm_resume(adev);
1495                         amdgpu_dm_display_resume(adev);
1496                         drm_kms_helper_hotplug_event(adev->ddev);
1497                 } else
1498                         dm_suspend(adev);
1499         }
1500
1501         return ret == 0 ? count : 0;
1502 }
1503
1504 DEVICE_ATTR_WO(s3_debug);
1505
1506 #endif
1507
1508 static int dm_early_init(void *handle)
1509 {
1510         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1511
1512         adev->ddev->driver->driver_features |= DRIVER_ATOMIC;
1513         amdgpu_dm_set_irq_funcs(adev);
1514
1515         switch (adev->asic_type) {
1516         case CHIP_BONAIRE:
1517         case CHIP_HAWAII:
1518                 adev->mode_info.num_crtc = 6;
1519                 adev->mode_info.num_hpd = 6;
1520                 adev->mode_info.num_dig = 6;
1521                 adev->mode_info.plane_type = dm_plane_type_default;
1522                 break;
1523         case CHIP_FIJI:
1524         case CHIP_TONGA:
1525                 adev->mode_info.num_crtc = 6;
1526                 adev->mode_info.num_hpd = 6;
1527                 adev->mode_info.num_dig = 7;
1528                 adev->mode_info.plane_type = dm_plane_type_default;
1529                 break;
1530         case CHIP_CARRIZO:
1531                 adev->mode_info.num_crtc = 3;
1532                 adev->mode_info.num_hpd = 6;
1533                 adev->mode_info.num_dig = 9;
1534                 adev->mode_info.plane_type = dm_plane_type_carizzo;
1535                 break;
1536         case CHIP_STONEY:
1537                 adev->mode_info.num_crtc = 2;
1538                 adev->mode_info.num_hpd = 6;
1539                 adev->mode_info.num_dig = 9;
1540                 adev->mode_info.plane_type = dm_plane_type_stoney;
1541                 break;
1542         case CHIP_POLARIS11:
1543         case CHIP_POLARIS12:
1544                 adev->mode_info.num_crtc = 5;
1545                 adev->mode_info.num_hpd = 5;
1546                 adev->mode_info.num_dig = 5;
1547                 adev->mode_info.plane_type = dm_plane_type_default;
1548                 break;
1549         case CHIP_POLARIS10:
1550                 adev->mode_info.num_crtc = 6;
1551                 adev->mode_info.num_hpd = 6;
1552                 adev->mode_info.num_dig = 6;
1553                 adev->mode_info.plane_type = dm_plane_type_default;
1554                 break;
1555         case CHIP_VEGA10:
1556                 adev->mode_info.num_crtc = 6;
1557                 adev->mode_info.num_hpd = 6;
1558                 adev->mode_info.num_dig = 6;
1559                 adev->mode_info.plane_type = dm_plane_type_default;
1560                 break;
1561 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1562         case CHIP_RAVEN:
1563                 adev->mode_info.num_crtc = 4;
1564                 adev->mode_info.num_hpd = 4;
1565                 adev->mode_info.num_dig = 4;
1566                 adev->mode_info.plane_type = dm_plane_type_default;
1567                 break;
1568 #endif
1569         default:
1570                 DRM_ERROR("Usupported ASIC type: 0x%X\n", adev->asic_type);
1571                 return -EINVAL;
1572         }
1573
1574         if (adev->mode_info.funcs == NULL)
1575                 adev->mode_info.funcs = &dm_display_funcs;
1576
1577         /* Note: Do NOT change adev->audio_endpt_rreg and
1578          * adev->audio_endpt_wreg because they are initialised in
1579          * amdgpu_device_init() */
1580 #if defined(CONFIG_DEBUG_KERNEL_DC)
1581         device_create_file(
1582                 adev->ddev->dev,
1583                 &dev_attr_s3_debug);
1584 #endif
1585
1586         return 0;
1587 }
1588
1589 bool amdgpu_dm_acquire_dal_lock(struct amdgpu_display_manager *dm)
1590 {
1591         /* TODO */
1592         return true;
1593 }
1594
1595 bool amdgpu_dm_release_dal_lock(struct amdgpu_display_manager *dm)
1596 {
1597         /* TODO */      return true;
1598 }
1599
1600
1601 struct dm_connector_state {
1602         struct drm_connector_state base;
1603
1604         enum amdgpu_rmx_type scaling;
1605         uint8_t underscan_vborder;
1606         uint8_t underscan_hborder;
1607         bool underscan_enable;
1608 };
1609
1610 #define to_dm_connector_state(x)\
1611         container_of((x), struct dm_connector_state, base)
1612
1613 static bool modeset_required(struct drm_crtc_state *crtc_state,
1614                              struct dc_stream_state *new_stream,
1615                              struct dc_stream_state *old_stream)
1616 {
1617         if (dc_is_stream_unchanged(new_stream, old_stream)) {
1618                 crtc_state->mode_changed = false;
1619                 DRM_DEBUG_KMS("Mode change not required, setting mode_changed to %d",
1620                               crtc_state->mode_changed);
1621         }
1622
1623         if (!drm_atomic_crtc_needs_modeset(crtc_state))
1624                 return false;
1625
1626         if (!crtc_state->enable)
1627                 return false;
1628
1629         return crtc_state->active;
1630 }
1631
1632 static bool modereset_required(struct drm_crtc_state *crtc_state)
1633 {
1634         if (!drm_atomic_crtc_needs_modeset(crtc_state))
1635                 return false;
1636
1637         return !crtc_state->enable || !crtc_state->active;
1638 }
1639
1640 void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
1641 {
1642         drm_encoder_cleanup(encoder);
1643         kfree(encoder);
1644 }
1645
1646 static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
1647         .destroy = amdgpu_dm_encoder_destroy,
1648 };
1649
1650 static void dm_set_cursor(
1651         struct amdgpu_crtc *amdgpu_crtc,
1652         uint64_t gpu_addr,
1653         uint32_t width,
1654         uint32_t height)
1655 {
1656         struct dc_cursor_attributes attributes;
1657         struct dc_cursor_position position;
1658         struct drm_crtc *crtc = &amdgpu_crtc->base;
1659         int x, y;
1660         int xorigin = 0, yorigin = 0;
1661         struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
1662
1663         amdgpu_crtc->cursor_width = width;
1664         amdgpu_crtc->cursor_height = height;
1665
1666         attributes.address.high_part = upper_32_bits(gpu_addr);
1667         attributes.address.low_part  = lower_32_bits(gpu_addr);
1668         attributes.width             = width;
1669         attributes.height            = height;
1670         attributes.color_format      = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA;
1671         attributes.rotation_angle    = 0;
1672         attributes.attribute_flags.value = 0;
1673
1674         attributes.pitch = attributes.width;
1675
1676         x = amdgpu_crtc->cursor_x;
1677         y = amdgpu_crtc->cursor_y;
1678
1679         /* avivo cursor are offset into the total surface */
1680         x += crtc->primary->state->src_x >> 16;
1681         y += crtc->primary->state->src_y >> 16;
1682
1683         if (x < 0) {
1684                 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
1685                 x = 0;
1686         }
1687         if (y < 0) {
1688                 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
1689                 y = 0;
1690         }
1691
1692         position.enable = true;
1693         position.x = x;
1694         position.y = y;
1695
1696         position.x_hotspot = xorigin;
1697         position.y_hotspot = yorigin;
1698
1699         if (!dc_stream_set_cursor_attributes(
1700                                 acrtc_state->stream,
1701                                 &attributes)) {
1702                 DRM_ERROR("DC failed to set cursor attributes\n");
1703         }
1704
1705         if (!dc_stream_set_cursor_position(
1706                                 acrtc_state->stream,
1707                                 &position)) {
1708                 DRM_ERROR("DC failed to set cursor position\n");
1709         }
1710 }
1711
1712 static int dm_crtc_cursor_set(
1713         struct drm_crtc *crtc,
1714         uint64_t address,
1715         uint32_t width,
1716         uint32_t height)
1717 {
1718         struct dc_cursor_position position;
1719         struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
1720
1721         int ret;
1722
1723         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1724         ret = EINVAL;
1725
1726         DRM_DEBUG_KMS("%s: crtc_id=%d with size %d to %d \n",
1727                       __func__,
1728                       amdgpu_crtc->crtc_id,
1729                       width,
1730                       height);
1731
1732         if (!address) {
1733                 /* turn off cursor */
1734                 position.enable = false;
1735                 position.x = 0;
1736                 position.y = 0;
1737
1738                 if (acrtc_state->stream) {
1739                         /*set cursor visible false*/
1740                         dc_stream_set_cursor_position(
1741                                 acrtc_state->stream,
1742                                 &position);
1743                 }
1744                 goto release;
1745
1746         }
1747
1748         if ((width > amdgpu_crtc->max_cursor_width) ||
1749                 (height > amdgpu_crtc->max_cursor_height)) {
1750                 DRM_ERROR(
1751                         "%s: bad cursor width or height %d x %d\n",
1752                         __func__,
1753                         width,
1754                         height);
1755                 goto release;
1756         }
1757
1758         /*program new cursor bo to hardware*/
1759         dm_set_cursor(amdgpu_crtc, address, width, height);
1760
1761 release:
1762         return ret;
1763
1764 }
1765
1766 static int dm_crtc_cursor_move(struct drm_crtc *crtc,
1767                                      int x, int y)
1768 {
1769         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1770         int xorigin = 0, yorigin = 0;
1771         struct dc_cursor_position position;
1772         struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
1773
1774         amdgpu_crtc->cursor_x = x;
1775         amdgpu_crtc->cursor_y = y;
1776
1777         /* avivo cursor are offset into the total surface */
1778         x += crtc->primary->state->src_x >> 16;
1779         y += crtc->primary->state->src_y >> 16;
1780
1781         /*
1782          * TODO: for cursor debugging unguard the following
1783          */
1784 #if 0
1785         DRM_DEBUG_KMS(
1786                 "%s: x %d y %d c->x %d c->y %d\n",
1787                 __func__,
1788                 x,
1789                 y,
1790                 crtc->x,
1791                 crtc->y);
1792 #endif
1793
1794         if (x < 0) {
1795                 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
1796                 x = 0;
1797         }
1798         if (y < 0) {
1799                 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
1800                 y = 0;
1801         }
1802
1803         position.enable = true;
1804         position.x = x;
1805         position.y = y;
1806
1807         position.x_hotspot = xorigin;
1808         position.y_hotspot = yorigin;
1809
1810         if (acrtc_state->stream) {
1811                 if (!dc_stream_set_cursor_position(
1812                                         acrtc_state->stream,
1813                                         &position)) {
1814                         DRM_ERROR("DC failed to set cursor position\n");
1815                         return -EINVAL;
1816                 }
1817         }
1818
1819         return 0;
1820 }
1821
1822 static bool fill_rects_from_plane_state(
1823         const struct drm_plane_state *state,
1824         struct dc_plane_state *plane_state)
1825 {
1826         plane_state->src_rect.x = state->src_x >> 16;
1827         plane_state->src_rect.y = state->src_y >> 16;
1828         /*we ignore for now mantissa and do not to deal with floating pixels :(*/
1829         plane_state->src_rect.width = state->src_w >> 16;
1830
1831         if (plane_state->src_rect.width == 0)
1832                 return false;
1833
1834         plane_state->src_rect.height = state->src_h >> 16;
1835         if (plane_state->src_rect.height == 0)
1836                 return false;
1837
1838         plane_state->dst_rect.x = state->crtc_x;
1839         plane_state->dst_rect.y = state->crtc_y;
1840
1841         if (state->crtc_w == 0)
1842                 return false;
1843
1844         plane_state->dst_rect.width = state->crtc_w;
1845
1846         if (state->crtc_h == 0)
1847                 return false;
1848
1849         plane_state->dst_rect.height = state->crtc_h;
1850
1851         plane_state->clip_rect = plane_state->dst_rect;
1852
1853         switch (state->rotation & DRM_MODE_ROTATE_MASK) {
1854         case DRM_MODE_ROTATE_0:
1855                 plane_state->rotation = ROTATION_ANGLE_0;
1856                 break;
1857         case DRM_MODE_ROTATE_90:
1858                 plane_state->rotation = ROTATION_ANGLE_90;
1859                 break;
1860         case DRM_MODE_ROTATE_180:
1861                 plane_state->rotation = ROTATION_ANGLE_180;
1862                 break;
1863         case DRM_MODE_ROTATE_270:
1864                 plane_state->rotation = ROTATION_ANGLE_270;
1865                 break;
1866         default:
1867                 plane_state->rotation = ROTATION_ANGLE_0;
1868                 break;
1869         }
1870
1871         return true;
1872 }
1873 static int get_fb_info(
1874         const struct amdgpu_framebuffer *amdgpu_fb,
1875         uint64_t *tiling_flags,
1876         uint64_t *fb_location)
1877 {
1878         struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->obj);
1879         int r = amdgpu_bo_reserve(rbo, false);
1880
1881         if (unlikely(r)) {
1882                 DRM_ERROR("Unable to reserve buffer\n");
1883                 return r;
1884         }
1885
1886         if (fb_location)
1887                 *fb_location = amdgpu_bo_gpu_offset(rbo);
1888
1889         if (tiling_flags)
1890                 amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
1891
1892         amdgpu_bo_unreserve(rbo);
1893
1894         return r;
1895 }
1896
1897 static int fill_plane_attributes_from_fb(
1898         struct amdgpu_device *adev,
1899         struct dc_plane_state *plane_state,
1900         const struct amdgpu_framebuffer *amdgpu_fb, bool addReq)
1901 {
1902         uint64_t tiling_flags;
1903         uint64_t fb_location = 0;
1904         unsigned int awidth;
1905         const struct drm_framebuffer *fb = &amdgpu_fb->base;
1906         int ret = 0;
1907         struct drm_format_name_buf format_name;
1908
1909         ret = get_fb_info(
1910                 amdgpu_fb,
1911                 &tiling_flags,
1912                 addReq == true ? &fb_location:NULL);
1913
1914         if (ret)
1915                 return ret;
1916
1917         switch (fb->format->format) {
1918         case DRM_FORMAT_C8:
1919                 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
1920                 break;
1921         case DRM_FORMAT_RGB565:
1922                 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
1923                 break;
1924         case DRM_FORMAT_XRGB8888:
1925         case DRM_FORMAT_ARGB8888:
1926                 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
1927                 break;
1928         case DRM_FORMAT_XRGB2101010:
1929         case DRM_FORMAT_ARGB2101010:
1930                 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
1931                 break;
1932         case DRM_FORMAT_XBGR2101010:
1933         case DRM_FORMAT_ABGR2101010:
1934                 plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
1935                 break;
1936         case DRM_FORMAT_NV21:
1937                 plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
1938                 break;
1939         case DRM_FORMAT_NV12:
1940                 plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
1941                 break;
1942         default:
1943                 DRM_ERROR("Unsupported screen format %s\n",
1944                           drm_get_format_name(fb->format->format, &format_name));
1945                 return -EINVAL;
1946         }
1947
1948         if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
1949                 plane_state->address.type = PLN_ADDR_TYPE_GRAPHICS;
1950                 plane_state->address.grph.addr.low_part = lower_32_bits(fb_location);
1951                 plane_state->address.grph.addr.high_part = upper_32_bits(fb_location);
1952                 plane_state->plane_size.grph.surface_size.x = 0;
1953                 plane_state->plane_size.grph.surface_size.y = 0;
1954                 plane_state->plane_size.grph.surface_size.width = fb->width;
1955                 plane_state->plane_size.grph.surface_size.height = fb->height;
1956                 plane_state->plane_size.grph.surface_pitch =
1957                                 fb->pitches[0] / fb->format->cpp[0];
1958                 /* TODO: unhardcode */
1959                 plane_state->color_space = COLOR_SPACE_SRGB;
1960
1961         } else {
1962                 awidth = ALIGN(fb->width, 64);
1963                 plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
1964                 plane_state->address.video_progressive.luma_addr.low_part
1965                                                 = lower_32_bits(fb_location);
1966                 plane_state->address.video_progressive.chroma_addr.low_part
1967                                                 = lower_32_bits(fb_location) +
1968                                                         (awidth * fb->height);
1969                 plane_state->plane_size.video.luma_size.x = 0;
1970                 plane_state->plane_size.video.luma_size.y = 0;
1971                 plane_state->plane_size.video.luma_size.width = awidth;
1972                 plane_state->plane_size.video.luma_size.height = fb->height;
1973                 /* TODO: unhardcode */
1974                 plane_state->plane_size.video.luma_pitch = awidth;
1975
1976                 plane_state->plane_size.video.chroma_size.x = 0;
1977                 plane_state->plane_size.video.chroma_size.y = 0;
1978                 plane_state->plane_size.video.chroma_size.width = awidth;
1979                 plane_state->plane_size.video.chroma_size.height = fb->height;
1980                 plane_state->plane_size.video.chroma_pitch = awidth / 2;
1981
1982                 /* TODO: unhardcode */
1983                 plane_state->color_space = COLOR_SPACE_YCBCR709;
1984         }
1985
1986         memset(&plane_state->tiling_info, 0, sizeof(plane_state->tiling_info));
1987
1988         /* Fill GFX8 params */
1989         if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) {
1990                 unsigned int bankw, bankh, mtaspect, tile_split, num_banks;
1991
1992                 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
1993                 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
1994                 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
1995                 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
1996                 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
1997
1998                 /* XXX fix me for VI */
1999                 plane_state->tiling_info.gfx8.num_banks = num_banks;
2000                 plane_state->tiling_info.gfx8.array_mode =
2001                                 DC_ARRAY_2D_TILED_THIN1;
2002                 plane_state->tiling_info.gfx8.tile_split = tile_split;
2003                 plane_state->tiling_info.gfx8.bank_width = bankw;
2004                 plane_state->tiling_info.gfx8.bank_height = bankh;
2005                 plane_state->tiling_info.gfx8.tile_aspect = mtaspect;
2006                 plane_state->tiling_info.gfx8.tile_mode =
2007                                 DC_ADDR_SURF_MICRO_TILING_DISPLAY;
2008         } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)
2009                         == DC_ARRAY_1D_TILED_THIN1) {
2010                 plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1;
2011         }
2012
2013         plane_state->tiling_info.gfx8.pipe_config =
2014                         AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2015
2016         if (adev->asic_type == CHIP_VEGA10 ||
2017             adev->asic_type == CHIP_RAVEN) {
2018                 /* Fill GFX9 params */
2019                 plane_state->tiling_info.gfx9.num_pipes =
2020                         adev->gfx.config.gb_addr_config_fields.num_pipes;
2021                 plane_state->tiling_info.gfx9.num_banks =
2022                         adev->gfx.config.gb_addr_config_fields.num_banks;
2023                 plane_state->tiling_info.gfx9.pipe_interleave =
2024                         adev->gfx.config.gb_addr_config_fields.pipe_interleave_size;
2025                 plane_state->tiling_info.gfx9.num_shader_engines =
2026                         adev->gfx.config.gb_addr_config_fields.num_se;
2027                 plane_state->tiling_info.gfx9.max_compressed_frags =
2028                         adev->gfx.config.gb_addr_config_fields.max_compress_frags;
2029                 plane_state->tiling_info.gfx9.num_rb_per_se =
2030                         adev->gfx.config.gb_addr_config_fields.num_rb_per_se;
2031                 plane_state->tiling_info.gfx9.swizzle =
2032                         AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE);
2033                 plane_state->tiling_info.gfx9.shaderEnable = 1;
2034         }
2035
2036         plane_state->visible = true;
2037         plane_state->scaling_quality.h_taps_c = 0;
2038         plane_state->scaling_quality.v_taps_c = 0;
2039
2040         /* is this needed? is plane_state zeroed at allocation? */
2041         plane_state->scaling_quality.h_taps = 0;
2042         plane_state->scaling_quality.v_taps = 0;
2043         plane_state->stereo_format = PLANE_STEREO_FORMAT_NONE;
2044
2045         return ret;
2046
2047 }
2048
2049 #define NUM_OF_RAW_GAMMA_RAMP_RGB_256 256
2050
2051 static void fill_gamma_from_crtc_state(
2052         const struct drm_crtc_state *crtc_state,
2053         struct dc_plane_state *plane_state)
2054 {
2055         int i;
2056         struct dc_gamma *gamma;
2057         struct drm_color_lut *lut = (struct drm_color_lut *) crtc_state->gamma_lut->data;
2058
2059         gamma = dc_create_gamma();
2060
2061         if (gamma == NULL) {
2062                 WARN_ON(1);
2063                 return;
2064         }
2065
2066         for (i = 0; i < NUM_OF_RAW_GAMMA_RAMP_RGB_256; i++) {
2067                 gamma->red[i] = lut[i].red;
2068                 gamma->green[i] = lut[i].green;
2069                 gamma->blue[i] = lut[i].blue;
2070         }
2071
2072         plane_state->gamma_correction = gamma;
2073 }
2074
2075 static int fill_plane_attributes(
2076                         struct amdgpu_device *adev,
2077                         struct dc_plane_state *dc_plane_state,
2078                         struct drm_plane_state *plane_state,
2079                         struct drm_crtc_state *crtc_state,
2080                         bool addrReq)
2081 {
2082         const struct amdgpu_framebuffer *amdgpu_fb =
2083                 to_amdgpu_framebuffer(plane_state->fb);
2084         const struct drm_crtc *crtc = plane_state->crtc;
2085         struct dc_transfer_func *input_tf;
2086         int ret = 0;
2087
2088         if (!fill_rects_from_plane_state(plane_state, dc_plane_state))
2089                 return -EINVAL;
2090
2091         ret = fill_plane_attributes_from_fb(
2092                 crtc->dev->dev_private,
2093                 dc_plane_state,
2094                 amdgpu_fb,
2095                 addrReq);
2096
2097         if (ret)
2098                 return ret;
2099
2100         input_tf = dc_create_transfer_func();
2101
2102         if (input_tf == NULL)
2103                 return -ENOMEM;
2104
2105         input_tf->type = TF_TYPE_PREDEFINED;
2106         input_tf->tf = TRANSFER_FUNCTION_SRGB;
2107
2108         dc_plane_state->in_transfer_func = input_tf;
2109
2110         /* In case of gamma set, update gamma value */
2111         if (crtc_state->gamma_lut)
2112                 fill_gamma_from_crtc_state(crtc_state, dc_plane_state);
2113
2114         return ret;
2115 }
2116
2117 /*****************************************************************************/
2118
2119 struct amdgpu_connector *aconnector_from_drm_crtc_id(
2120                 const struct drm_crtc *crtc)
2121 {
2122         struct drm_device *dev = crtc->dev;
2123         struct drm_connector *connector;
2124         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2125         struct amdgpu_connector *aconnector;
2126
2127         list_for_each_entry(connector,
2128                         &dev->mode_config.connector_list, head) {
2129
2130                 aconnector = to_amdgpu_connector(connector);
2131
2132                 if (aconnector->base.state->crtc != &acrtc->base)
2133                         continue;
2134
2135                 /* Found the connector */
2136                 return aconnector;
2137         }
2138
2139         /* If we get here, not found. */
2140         return NULL;
2141 }
2142
2143 static void update_stream_scaling_settings(
2144                 const struct drm_display_mode *mode,
2145                 const struct dm_connector_state *dm_state,
2146                 struct dc_stream_state *stream)
2147 {
2148         enum amdgpu_rmx_type rmx_type;
2149
2150         struct rect src = { 0 }; /* viewport in composition space*/
2151         struct rect dst = { 0 }; /* stream addressable area */
2152
2153         /* no mode. nothing to be done */
2154         if (!mode)
2155                 return;
2156
2157         /* Full screen scaling by default */
2158         src.width = mode->hdisplay;
2159         src.height = mode->vdisplay;
2160         dst.width = stream->timing.h_addressable;
2161         dst.height = stream->timing.v_addressable;
2162
2163         rmx_type = dm_state->scaling;
2164         if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
2165                 if (src.width * dst.height <
2166                                 src.height * dst.width) {
2167                         /* height needs less upscaling/more downscaling */
2168                         dst.width = src.width *
2169                                         dst.height / src.height;
2170                 } else {
2171                         /* width needs less upscaling/more downscaling */
2172                         dst.height = src.height *
2173                                         dst.width / src.width;
2174                 }
2175         } else if (rmx_type == RMX_CENTER) {
2176                 dst = src;
2177         }
2178
2179         dst.x = (stream->timing.h_addressable - dst.width) / 2;
2180         dst.y = (stream->timing.v_addressable - dst.height) / 2;
2181
2182         if (dm_state->underscan_enable) {
2183                 dst.x += dm_state->underscan_hborder / 2;
2184                 dst.y += dm_state->underscan_vborder / 2;
2185                 dst.width -= dm_state->underscan_hborder;
2186                 dst.height -= dm_state->underscan_vborder;
2187         }
2188
2189         stream->src = src;
2190         stream->dst = dst;
2191
2192         DRM_DEBUG_KMS("Destination Rectangle x:%d  y:%d  width:%d  height:%d\n",
2193                         dst.x, dst.y, dst.width, dst.height);
2194
2195 }
2196
2197 static enum dc_color_depth convert_color_depth_from_display_info(
2198                 const struct drm_connector *connector)
2199 {
2200         uint32_t bpc = connector->display_info.bpc;
2201
2202         /* Limited color depth to 8bit
2203          * TODO: Still need to handle deep color
2204          */
2205         if (bpc > 8)
2206                 bpc = 8;
2207
2208         switch (bpc) {
2209         case 0:
2210                 /* Temporary Work around, DRM don't parse color depth for
2211                  * EDID revision before 1.4
2212                  * TODO: Fix edid parsing
2213                  */
2214                 return COLOR_DEPTH_888;
2215         case 6:
2216                 return COLOR_DEPTH_666;
2217         case 8:
2218                 return COLOR_DEPTH_888;
2219         case 10:
2220                 return COLOR_DEPTH_101010;
2221         case 12:
2222                 return COLOR_DEPTH_121212;
2223         case 14:
2224                 return COLOR_DEPTH_141414;
2225         case 16:
2226                 return COLOR_DEPTH_161616;
2227         default:
2228                 return COLOR_DEPTH_UNDEFINED;
2229         }
2230 }
2231
2232 static enum dc_aspect_ratio get_aspect_ratio(
2233                 const struct drm_display_mode *mode_in)
2234 {
2235         int32_t width = mode_in->crtc_hdisplay * 9;
2236         int32_t height = mode_in->crtc_vdisplay * 16;
2237
2238         if ((width - height) < 10 && (width - height) > -10)
2239                 return ASPECT_RATIO_16_9;
2240         else
2241                 return ASPECT_RATIO_4_3;
2242 }
2243
2244 static enum dc_color_space get_output_color_space(
2245                                 const struct dc_crtc_timing *dc_crtc_timing)
2246 {
2247         enum dc_color_space color_space = COLOR_SPACE_SRGB;
2248
2249         switch (dc_crtc_timing->pixel_encoding) {
2250         case PIXEL_ENCODING_YCBCR422:
2251         case PIXEL_ENCODING_YCBCR444:
2252         case PIXEL_ENCODING_YCBCR420:
2253         {
2254                 /*
2255                  * 27030khz is the separation point between HDTV and SDTV
2256                  * according to HDMI spec, we use YCbCr709 and YCbCr601
2257                  * respectively
2258                  */
2259                 if (dc_crtc_timing->pix_clk_khz > 27030) {
2260                         if (dc_crtc_timing->flags.Y_ONLY)
2261                                 color_space =
2262                                         COLOR_SPACE_YCBCR709_LIMITED;
2263                         else
2264                                 color_space = COLOR_SPACE_YCBCR709;
2265                 } else {
2266                         if (dc_crtc_timing->flags.Y_ONLY)
2267                                 color_space =
2268                                         COLOR_SPACE_YCBCR601_LIMITED;
2269                         else
2270                                 color_space = COLOR_SPACE_YCBCR601;
2271                 }
2272
2273         }
2274         break;
2275         case PIXEL_ENCODING_RGB:
2276                 color_space = COLOR_SPACE_SRGB;
2277                 break;
2278
2279         default:
2280                 WARN_ON(1);
2281                 break;
2282         }
2283
2284         return color_space;
2285 }
2286
2287 /*****************************************************************************/
2288
2289 static void fill_stream_properties_from_drm_display_mode(
2290         struct dc_stream_state *stream,
2291         const struct drm_display_mode *mode_in,
2292         const struct drm_connector *connector)
2293 {
2294         struct dc_crtc_timing *timing_out = &stream->timing;
2295
2296         memset(timing_out, 0, sizeof(struct dc_crtc_timing));
2297
2298         timing_out->h_border_left = 0;
2299         timing_out->h_border_right = 0;
2300         timing_out->v_border_top = 0;
2301         timing_out->v_border_bottom = 0;
2302         /* TODO: un-hardcode */
2303
2304         if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444)
2305                         && stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A)
2306                 timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
2307         else
2308                 timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
2309
2310         timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
2311         timing_out->display_color_depth = convert_color_depth_from_display_info(
2312                         connector);
2313         timing_out->scan_type = SCANNING_TYPE_NODATA;
2314         timing_out->hdmi_vic = 0;
2315         timing_out->vic = drm_match_cea_mode(mode_in);
2316
2317         timing_out->h_addressable = mode_in->crtc_hdisplay;
2318         timing_out->h_total = mode_in->crtc_htotal;
2319         timing_out->h_sync_width =
2320                 mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
2321         timing_out->h_front_porch =
2322                 mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
2323         timing_out->v_total = mode_in->crtc_vtotal;
2324         timing_out->v_addressable = mode_in->crtc_vdisplay;
2325         timing_out->v_front_porch =
2326                 mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
2327         timing_out->v_sync_width =
2328                 mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
2329         timing_out->pix_clk_khz = mode_in->crtc_clock;
2330         timing_out->aspect_ratio = get_aspect_ratio(mode_in);
2331         if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
2332                 timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
2333         if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
2334                 timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
2335
2336         stream->output_color_space = get_output_color_space(timing_out);
2337
2338         {
2339                 struct dc_transfer_func *tf = dc_create_transfer_func();
2340
2341                 tf->type = TF_TYPE_PREDEFINED;
2342                 tf->tf = TRANSFER_FUNCTION_SRGB;
2343                 stream->out_transfer_func = tf;
2344         }
2345 }
2346
2347 static void fill_audio_info(
2348         struct audio_info *audio_info,
2349         const struct drm_connector *drm_connector,
2350         const struct dc_sink *dc_sink)
2351 {
2352         int i = 0;
2353         int cea_revision = 0;
2354         const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
2355
2356         audio_info->manufacture_id = edid_caps->manufacturer_id;
2357         audio_info->product_id = edid_caps->product_id;
2358
2359         cea_revision = drm_connector->display_info.cea_rev;
2360
2361         while (i < AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS &&
2362                 edid_caps->display_name[i]) {
2363                 audio_info->display_name[i] = edid_caps->display_name[i];
2364                 i++;
2365         }
2366
2367         if (cea_revision >= 3) {
2368                 audio_info->mode_count = edid_caps->audio_mode_count;
2369
2370                 for (i = 0; i < audio_info->mode_count; ++i) {
2371                         audio_info->modes[i].format_code =
2372                                         (enum audio_format_code)
2373                                         (edid_caps->audio_modes[i].format_code);
2374                         audio_info->modes[i].channel_count =
2375                                         edid_caps->audio_modes[i].channel_count;
2376                         audio_info->modes[i].sample_rates.all =
2377                                         edid_caps->audio_modes[i].sample_rate;
2378                         audio_info->modes[i].sample_size =
2379                                         edid_caps->audio_modes[i].sample_size;
2380                 }
2381         }
2382
2383         audio_info->flags.all = edid_caps->speaker_flags;
2384
2385         /* TODO: We only check for the progressive mode, check for interlace mode too */
2386         if (drm_connector->latency_present[0]) {
2387                 audio_info->video_latency = drm_connector->video_latency[0];
2388                 audio_info->audio_latency = drm_connector->audio_latency[0];
2389         }
2390
2391         /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
2392
2393 }
2394
2395 static void copy_crtc_timing_for_drm_display_mode(
2396                 const struct drm_display_mode *src_mode,
2397                 struct drm_display_mode *dst_mode)
2398 {
2399         dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
2400         dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
2401         dst_mode->crtc_clock = src_mode->crtc_clock;
2402         dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
2403         dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
2404         dst_mode->crtc_hsync_start =  src_mode->crtc_hsync_start;
2405         dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
2406         dst_mode->crtc_htotal = src_mode->crtc_htotal;
2407         dst_mode->crtc_hskew = src_mode->crtc_hskew;
2408         dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
2409         dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
2410         dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
2411         dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
2412         dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
2413 }
2414
2415 static void decide_crtc_timing_for_drm_display_mode(
2416                 struct drm_display_mode *drm_mode,
2417                 const struct drm_display_mode *native_mode,
2418                 bool scale_enabled)
2419 {
2420         if (scale_enabled) {
2421                 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
2422         } else if (native_mode->clock == drm_mode->clock &&
2423                         native_mode->htotal == drm_mode->htotal &&
2424                         native_mode->vtotal == drm_mode->vtotal) {
2425                 copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
2426         } else {
2427                 /* no scaling nor amdgpu inserted, no need to patch */
2428         }
2429 }
2430
2431 static struct dc_stream_state *create_stream_for_sink(
2432                 struct amdgpu_connector *aconnector,
2433                 const struct drm_display_mode *drm_mode,
2434                 const struct dm_connector_state *dm_state)
2435 {
2436         struct drm_display_mode *preferred_mode = NULL;
2437         const struct drm_connector *drm_connector;
2438         struct dc_stream_state *stream = NULL;
2439         struct drm_display_mode mode = *drm_mode;
2440         bool native_mode_found = false;
2441
2442         if (aconnector == NULL) {
2443                 DRM_ERROR("aconnector is NULL!\n");
2444                 goto drm_connector_null;
2445         }
2446
2447         if (dm_state == NULL) {
2448                 DRM_ERROR("dm_state is NULL!\n");
2449                 goto dm_state_null;
2450         }
2451
2452         drm_connector = &aconnector->base;
2453         stream = dc_create_stream_for_sink(aconnector->dc_sink);
2454
2455         if (stream == NULL) {
2456                 DRM_ERROR("Failed to create stream for sink!\n");
2457                 goto stream_create_fail;
2458         }
2459
2460         list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
2461                 /* Search for preferred mode */
2462                 if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
2463                         native_mode_found = true;
2464                         break;
2465                 }
2466         }
2467         if (!native_mode_found)
2468                 preferred_mode = list_first_entry_or_null(
2469                                 &aconnector->base.modes,
2470                                 struct drm_display_mode,
2471                                 head);
2472
2473         if (preferred_mode == NULL) {
2474                 /* This may not be an error, the use case is when we we have no
2475                  * usermode calls to reset and set mode upon hotplug. In this
2476                  * case, we call set mode ourselves to restore the previous mode
2477                  * and the modelist may not be filled in in time.
2478                  */
2479                 DRM_INFO("No preferred mode found\n");
2480         } else {
2481                 decide_crtc_timing_for_drm_display_mode(
2482                                 &mode, preferred_mode,
2483                                 dm_state->scaling != RMX_OFF);
2484         }
2485
2486         fill_stream_properties_from_drm_display_mode(stream,
2487                         &mode, &aconnector->base);
2488         update_stream_scaling_settings(&mode, dm_state, stream);
2489
2490         fill_audio_info(
2491                 &stream->audio_info,
2492                 drm_connector,
2493                 aconnector->dc_sink);
2494
2495 stream_create_fail:
2496 dm_state_null:
2497 drm_connector_null:
2498         return stream;
2499 }
2500
2501 void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
2502 {
2503         drm_crtc_cleanup(crtc);
2504         kfree(crtc);
2505 }
2506
2507 static void dm_crtc_destroy_state(struct drm_crtc *crtc,
2508                                            struct drm_crtc_state *state)
2509 {
2510         struct dm_crtc_state *cur = to_dm_crtc_state(state);
2511
2512         /* TODO Destroy dc_stream objects are stream object is flattened */
2513         if (cur->stream)
2514                 dc_stream_release(cur->stream);
2515
2516
2517         __drm_atomic_helper_crtc_destroy_state(state);
2518
2519
2520         kfree(state);
2521 }
2522
2523 static void dm_crtc_reset_state(struct drm_crtc *crtc)
2524 {
2525         struct dm_crtc_state *state;
2526
2527         if (crtc->state)
2528                 dm_crtc_destroy_state(crtc, crtc->state);
2529
2530         state = kzalloc(sizeof(*state), GFP_KERNEL);
2531         if (WARN_ON(!state))
2532                 return;
2533
2534         crtc->state = &state->base;
2535         crtc->state->crtc = crtc;
2536
2537 }
2538
2539 static struct drm_crtc_state *
2540 dm_crtc_duplicate_state(struct drm_crtc *crtc)
2541 {
2542         struct dm_crtc_state *state, *cur;
2543
2544         cur = to_dm_crtc_state(crtc->state);
2545
2546         if (WARN_ON(!crtc->state))
2547                 return NULL;
2548
2549         state = dm_alloc(sizeof(*state));
2550
2551         __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
2552
2553         if (cur->stream) {
2554                 state->stream = cur->stream;
2555                 dc_stream_retain(state->stream);
2556         }
2557
2558         /* TODO Duplicate dc_stream after objects are stream object is flattened */
2559
2560         return &state->base;
2561 }
2562
2563 /* Implemented only the options currently availible for the driver */
2564 static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
2565         .reset = dm_crtc_reset_state,
2566         .destroy = amdgpu_dm_crtc_destroy,
2567         .gamma_set = drm_atomic_helper_legacy_gamma_set,
2568         .set_config = drm_atomic_helper_set_config,
2569         .page_flip = drm_atomic_helper_page_flip,
2570         .atomic_duplicate_state = dm_crtc_duplicate_state,
2571         .atomic_destroy_state = dm_crtc_destroy_state,
2572 };
2573
2574 static enum drm_connector_status
2575 amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
2576 {
2577         bool connected;
2578         struct amdgpu_connector *aconnector = to_amdgpu_connector(connector);
2579
2580         /* Notes:
2581          * 1. This interface is NOT called in context of HPD irq.
2582          * 2. This interface *is called* in context of user-mode ioctl. Which
2583          * makes it a bad place for *any* MST-related activit. */
2584
2585         if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
2586                 connected = (aconnector->dc_sink != NULL);
2587         else
2588                 connected = (aconnector->base.force == DRM_FORCE_ON);
2589
2590         return (connected ? connector_status_connected :
2591                         connector_status_disconnected);
2592 }
2593
2594 int amdgpu_dm_connector_atomic_set_property(
2595         struct drm_connector *connector,
2596         struct drm_connector_state *connector_state,
2597         struct drm_property *property,
2598         uint64_t val)
2599 {
2600         struct drm_device *dev = connector->dev;
2601         struct amdgpu_device *adev = dev->dev_private;
2602         struct dm_connector_state *dm_old_state =
2603                 to_dm_connector_state(connector->state);
2604         struct dm_connector_state *dm_new_state =
2605                 to_dm_connector_state(connector_state);
2606
2607         int ret = -EINVAL;
2608
2609         if (property == dev->mode_config.scaling_mode_property) {
2610                 enum amdgpu_rmx_type rmx_type;
2611
2612                 switch (val) {
2613                 case DRM_MODE_SCALE_CENTER:
2614                         rmx_type = RMX_CENTER;
2615                         break;
2616                 case DRM_MODE_SCALE_ASPECT:
2617                         rmx_type = RMX_ASPECT;
2618                         break;
2619                 case DRM_MODE_SCALE_FULLSCREEN:
2620                         rmx_type = RMX_FULL;
2621                         break;
2622                 case DRM_MODE_SCALE_NONE:
2623                 default:
2624                         rmx_type = RMX_OFF;
2625                         break;
2626                 }
2627
2628                 if (dm_old_state->scaling == rmx_type)
2629                         return 0;
2630
2631                 dm_new_state->scaling = rmx_type;
2632                 ret = 0;
2633         } else if (property == adev->mode_info.underscan_hborder_property) {
2634                 dm_new_state->underscan_hborder = val;
2635                 ret = 0;
2636         } else if (property == adev->mode_info.underscan_vborder_property) {
2637                 dm_new_state->underscan_vborder = val;
2638                 ret = 0;
2639         } else if (property == adev->mode_info.underscan_property) {
2640                 dm_new_state->underscan_enable = val;
2641                 ret = 0;
2642         }
2643
2644         return ret;
2645 }
2646
2647 int amdgpu_dm_connector_atomic_get_property(
2648         struct drm_connector *connector,
2649         const struct drm_connector_state *state,
2650         struct drm_property *property,
2651         uint64_t *val)
2652 {
2653         struct drm_device *dev = connector->dev;
2654         struct amdgpu_device *adev = dev->dev_private;
2655         struct dm_connector_state *dm_state =
2656                 to_dm_connector_state(state);
2657         int ret = -EINVAL;
2658
2659         if (property == dev->mode_config.scaling_mode_property) {
2660                 switch (dm_state->scaling) {
2661                 case RMX_CENTER:
2662                         *val = DRM_MODE_SCALE_CENTER;
2663                         break;
2664                 case RMX_ASPECT:
2665                         *val = DRM_MODE_SCALE_ASPECT;
2666                         break;
2667                 case RMX_FULL:
2668                         *val = DRM_MODE_SCALE_FULLSCREEN;
2669                         break;
2670                 case RMX_OFF:
2671                 default:
2672                         *val = DRM_MODE_SCALE_NONE;
2673                         break;
2674                 }
2675                 ret = 0;
2676         } else if (property == adev->mode_info.underscan_hborder_property) {
2677                 *val = dm_state->underscan_hborder;
2678                 ret = 0;
2679         } else if (property == adev->mode_info.underscan_vborder_property) {
2680                 *val = dm_state->underscan_vborder;
2681                 ret = 0;
2682         } else if (property == adev->mode_info.underscan_property) {
2683                 *val = dm_state->underscan_enable;
2684                 ret = 0;
2685         }
2686         return ret;
2687 }
2688
2689 void amdgpu_dm_connector_destroy(struct drm_connector *connector)
2690 {
2691         struct amdgpu_connector *aconnector = to_amdgpu_connector(connector);
2692         const struct dc_link *link = aconnector->dc_link;
2693         struct amdgpu_device *adev = connector->dev->dev_private;
2694         struct amdgpu_display_manager *dm = &adev->dm;
2695 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
2696         defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
2697
2698         if (link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) {
2699                 amdgpu_dm_register_backlight_device(dm);
2700
2701                 if (dm->backlight_dev) {
2702                         backlight_device_unregister(dm->backlight_dev);
2703                         dm->backlight_dev = NULL;
2704                 }
2705
2706         }
2707 #endif
2708         drm_connector_unregister(connector);
2709         drm_connector_cleanup(connector);
2710         kfree(connector);
2711 }
2712
2713 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
2714 {
2715         struct dm_connector_state *state =
2716                 to_dm_connector_state(connector->state);
2717
2718         kfree(state);
2719
2720         state = kzalloc(sizeof(*state), GFP_KERNEL);
2721
2722         if (state) {
2723                 state->scaling = RMX_OFF;
2724                 state->underscan_enable = false;
2725                 state->underscan_hborder = 0;
2726                 state->underscan_vborder = 0;
2727
2728                 connector->state = &state->base;
2729                 connector->state->connector = connector;
2730         }
2731 }
2732
2733 struct drm_connector_state *amdgpu_dm_connector_atomic_duplicate_state(
2734         struct drm_connector *connector)
2735 {
2736         struct dm_connector_state *state =
2737                 to_dm_connector_state(connector->state);
2738
2739         struct dm_connector_state *new_state =
2740                         kmemdup(state, sizeof(*state), GFP_KERNEL);
2741
2742         if (new_state) {
2743                 __drm_atomic_helper_connector_duplicate_state(connector,
2744                                                                       &new_state->base);
2745                 return &new_state->base;
2746         }
2747
2748         return NULL;
2749 }
2750
2751 static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
2752         .reset = amdgpu_dm_connector_funcs_reset,
2753         .detect = amdgpu_dm_connector_detect,
2754         .fill_modes = drm_helper_probe_single_connector_modes,
2755         .destroy = amdgpu_dm_connector_destroy,
2756         .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
2757         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2758         .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
2759         .atomic_get_property = amdgpu_dm_connector_atomic_get_property
2760 };
2761
2762 static struct drm_encoder *best_encoder(struct drm_connector *connector)
2763 {
2764         int enc_id = connector->encoder_ids[0];
2765         struct drm_mode_object *obj;
2766         struct drm_encoder *encoder;
2767
2768         DRM_DEBUG_KMS("Finding the best encoder\n");
2769
2770         /* pick the encoder ids */
2771         if (enc_id) {
2772                 obj = drm_mode_object_find(connector->dev, enc_id, DRM_MODE_OBJECT_ENCODER);
2773                 if (!obj) {
2774                         DRM_ERROR("Couldn't find a matching encoder for our connector\n");
2775                         return NULL;
2776                 }
2777                 encoder = obj_to_encoder(obj);
2778                 return encoder;
2779         }
2780         DRM_ERROR("No encoder id\n");
2781         return NULL;
2782 }
2783
2784 static int get_modes(struct drm_connector *connector)
2785 {
2786         return amdgpu_dm_connector_get_modes(connector);
2787 }
2788
2789 static void create_eml_sink(struct amdgpu_connector *aconnector)
2790 {
2791         struct dc_sink_init_data init_params = {
2792                         .link = aconnector->dc_link,
2793                         .sink_signal = SIGNAL_TYPE_VIRTUAL
2794         };
2795         struct edid *edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
2796
2797         if (!aconnector->base.edid_blob_ptr ||
2798                 !aconnector->base.edid_blob_ptr->data) {
2799                 DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
2800                                 aconnector->base.name);
2801
2802                 aconnector->base.force = DRM_FORCE_OFF;
2803                 aconnector->base.override_edid = false;
2804                 return;
2805         }
2806
2807         aconnector->edid = edid;
2808
2809         aconnector->dc_em_sink = dc_link_add_remote_sink(
2810                 aconnector->dc_link,
2811                 (uint8_t *)edid,
2812                 (edid->extensions + 1) * EDID_LENGTH,
2813                 &init_params);
2814
2815         if (aconnector->base.force
2816                                         == DRM_FORCE_ON)
2817                 aconnector->dc_sink = aconnector->dc_link->local_sink ?
2818                 aconnector->dc_link->local_sink :
2819                 aconnector->dc_em_sink;
2820 }
2821
2822 static void handle_edid_mgmt(struct amdgpu_connector *aconnector)
2823 {
2824         struct dc_link *link = (struct dc_link *)aconnector->dc_link;
2825
2826         /* In case of headless boot with force on for DP managed connector
2827          * Those settings have to be != 0 to get initial modeset
2828          */
2829         if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
2830                 link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
2831                 link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
2832         }
2833
2834
2835         aconnector->base.override_edid = true;
2836         create_eml_sink(aconnector);
2837 }
2838
2839 int amdgpu_dm_connector_mode_valid(
2840                 struct drm_connector *connector,
2841                 struct drm_display_mode *mode)
2842 {
2843         int result = MODE_ERROR;
2844         struct dc_sink *dc_sink;
2845         struct amdgpu_device *adev = connector->dev->dev_private;
2846         /* TODO: Unhardcode stream count */
2847         struct dc_stream_state *stream;
2848         struct amdgpu_connector *aconnector = to_amdgpu_connector(connector);
2849
2850         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
2851                         (mode->flags & DRM_MODE_FLAG_DBLSCAN))
2852                 return result;
2853
2854         /* Only run this the first time mode_valid is called to initilialize
2855          * EDID mgmt
2856          */
2857         if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
2858                 !aconnector->dc_em_sink)
2859                 handle_edid_mgmt(aconnector);
2860
2861         dc_sink = to_amdgpu_connector(connector)->dc_sink;
2862
2863         if (dc_sink == NULL) {
2864                 DRM_ERROR("dc_sink is NULL!\n");
2865                 goto fail;
2866         }
2867
2868         stream = dc_create_stream_for_sink(dc_sink);
2869         if (stream == NULL) {
2870                 DRM_ERROR("Failed to create stream for sink!\n");
2871                 goto fail;
2872         }
2873
2874         drm_mode_set_crtcinfo(mode, 0);
2875         fill_stream_properties_from_drm_display_mode(stream, mode, connector);
2876
2877         stream->src.width = mode->hdisplay;
2878         stream->src.height = mode->vdisplay;
2879         stream->dst = stream->src;
2880
2881         if (dc_validate_stream(adev->dm.dc, stream))
2882                 result = MODE_OK;
2883
2884         dc_stream_release(stream);
2885
2886 fail:
2887         /* TODO: error handling*/
2888         return result;
2889 }
2890
2891 static const struct drm_connector_helper_funcs
2892 amdgpu_dm_connector_helper_funcs = {
2893         /*
2894          * If hotplug a second bigger display in FB Con mode, bigger resolution
2895          * modes will be filtered by drm_mode_validate_size(), and those modes
2896          * is missing after user start lightdm. So we need to renew modes list.
2897          * in get_modes call back, not just return the modes count
2898          */
2899         .get_modes = get_modes,
2900         .mode_valid = amdgpu_dm_connector_mode_valid,
2901         .best_encoder = best_encoder
2902 };
2903
2904 static void dm_crtc_helper_disable(struct drm_crtc *crtc)
2905 {
2906 }
2907
2908 static int dm_crtc_helper_atomic_check(
2909         struct drm_crtc *crtc,
2910         struct drm_crtc_state *state)
2911 {
2912         struct amdgpu_device *adev = crtc->dev->dev_private;
2913         struct dc *dc = adev->dm.dc;
2914         struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(state);
2915         int ret = -EINVAL;
2916
2917         if (unlikely(!dm_crtc_state->stream &&
2918                      modeset_required(state, NULL, dm_crtc_state->stream))) {
2919                 WARN_ON(1);
2920                 return ret;
2921         }
2922
2923         /* In some use cases, like reset, no stream  is attached */
2924         if (!dm_crtc_state->stream)
2925                 return 0;
2926
2927         if (dc_validate_stream(dc, dm_crtc_state->stream))
2928                 return 0;
2929
2930         return ret;
2931 }
2932
2933 static bool dm_crtc_helper_mode_fixup(
2934         struct drm_crtc *crtc,
2935         const struct drm_display_mode *mode,
2936         struct drm_display_mode *adjusted_mode)
2937 {
2938         return true;
2939 }
2940
2941 static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = {
2942         .disable = dm_crtc_helper_disable,
2943         .atomic_check = dm_crtc_helper_atomic_check,
2944         .mode_fixup = dm_crtc_helper_mode_fixup
2945 };
2946
2947 static void dm_encoder_helper_disable(struct drm_encoder *encoder)
2948 {
2949
2950 }
2951
2952 static int dm_encoder_helper_atomic_check(
2953         struct drm_encoder *encoder,
2954         struct drm_crtc_state *crtc_state,
2955         struct drm_connector_state *conn_state)
2956 {
2957         return 0;
2958 }
2959
2960 const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
2961         .disable = dm_encoder_helper_disable,
2962         .atomic_check = dm_encoder_helper_atomic_check
2963 };
2964
2965 static void dm_drm_plane_reset(struct drm_plane *plane)
2966 {
2967         struct dm_plane_state *amdgpu_state = NULL;
2968
2969         if (plane->state)
2970                 plane->funcs->atomic_destroy_state(plane, plane->state);
2971
2972         amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL);
2973
2974         if (amdgpu_state) {
2975                 plane->state = &amdgpu_state->base;
2976                 plane->state->plane = plane;
2977                 plane->state->rotation = DRM_MODE_ROTATE_0;
2978         } else
2979                 WARN_ON(1);
2980 }
2981
2982 static struct drm_plane_state *
2983 dm_drm_plane_duplicate_state(struct drm_plane *plane)
2984 {
2985         struct dm_plane_state *dm_plane_state, *old_dm_plane_state;
2986
2987         old_dm_plane_state = to_dm_plane_state(plane->state);
2988         dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL);
2989         if (!dm_plane_state)
2990                 return NULL;
2991
2992         __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base);
2993
2994         if (old_dm_plane_state->dc_state) {
2995                 dm_plane_state->dc_state = old_dm_plane_state->dc_state;
2996                 dc_plane_state_retain(dm_plane_state->dc_state);
2997         }
2998
2999         return &dm_plane_state->base;
3000 }
3001
3002 void dm_drm_plane_destroy_state(struct drm_plane *plane,
3003                                            struct drm_plane_state *state)
3004 {
3005         struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
3006
3007         if (dm_plane_state->dc_state)
3008                 dc_plane_state_release(dm_plane_state->dc_state);
3009
3010         __drm_atomic_helper_plane_destroy_state(state);
3011         kfree(dm_plane_state);
3012 }
3013
3014 static const struct drm_plane_funcs dm_plane_funcs = {
3015         .update_plane   = drm_atomic_helper_update_plane,
3016         .disable_plane  = drm_atomic_helper_disable_plane,
3017         .destroy        = drm_plane_cleanup,
3018         .reset = dm_drm_plane_reset,
3019         .atomic_duplicate_state = dm_drm_plane_duplicate_state,
3020         .atomic_destroy_state = dm_drm_plane_destroy_state,
3021 };
3022
3023 static int dm_plane_helper_prepare_fb(
3024         struct drm_plane *plane,
3025         struct drm_plane_state *new_state)
3026 {
3027         struct amdgpu_framebuffer *afb;
3028         struct drm_gem_object *obj;
3029         struct amdgpu_bo *rbo;
3030         int r;
3031         struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old;
3032         unsigned int awidth;
3033
3034         dm_plane_state_old = to_dm_plane_state(plane->state);
3035         dm_plane_state_new = to_dm_plane_state(new_state);
3036
3037         if (!new_state->fb) {
3038                 DRM_DEBUG_KMS("No FB bound\n");
3039                 return 0;
3040         }
3041
3042         afb = to_amdgpu_framebuffer(new_state->fb);
3043
3044         obj = afb->obj;
3045         rbo = gem_to_amdgpu_bo(obj);
3046         r = amdgpu_bo_reserve(rbo, false);
3047         if (unlikely(r != 0))
3048                 return r;
3049
3050         r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &afb->address);
3051
3052
3053         amdgpu_bo_unreserve(rbo);
3054
3055         if (unlikely(r != 0)) {
3056                 DRM_ERROR("Failed to pin framebuffer\n");
3057                 return r;
3058         }
3059
3060         amdgpu_bo_ref(rbo);
3061
3062         if (dm_plane_state_new->dc_state &&
3063                         dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) {
3064                 struct dc_plane_state *plane_state = dm_plane_state_new->dc_state;
3065
3066                 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
3067                         plane_state->address.grph.addr.low_part = lower_32_bits(afb->address);
3068                         plane_state->address.grph.addr.high_part = upper_32_bits(afb->address);
3069                 } else {
3070                         awidth = ALIGN(new_state->fb->width, 64);
3071                         plane_state->address.video_progressive.luma_addr.low_part
3072                                                         = lower_32_bits(afb->address);
3073                         plane_state->address.video_progressive.chroma_addr.low_part
3074                                                         = lower_32_bits(afb->address) +
3075                                                                 (awidth * new_state->fb->height);
3076                 }
3077         }
3078
3079         /* It's a hack for s3 since in 4.9 kernel filter out cursor buffer
3080          * prepare and cleanup in drm_atomic_helper_prepare_planes
3081          * and drm_atomic_helper_cleanup_planes because fb doens't in s3.
3082          * IN 4.10 kernel this code should be removed and amdgpu_device_suspend
3083          * code touching fram buffers should be avoided for DC.
3084          */
3085         if (plane->type == DRM_PLANE_TYPE_CURSOR) {
3086                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_state->crtc);
3087
3088                 acrtc->cursor_bo = obj;
3089         }
3090         return 0;
3091 }
3092
3093 static void dm_plane_helper_cleanup_fb(
3094         struct drm_plane *plane,
3095         struct drm_plane_state *old_state)
3096 {
3097         struct amdgpu_bo *rbo;
3098         struct amdgpu_framebuffer *afb;
3099         int r;
3100
3101         if (!old_state->fb)
3102                 return;
3103
3104         afb = to_amdgpu_framebuffer(old_state->fb);
3105         rbo = gem_to_amdgpu_bo(afb->obj);
3106         r = amdgpu_bo_reserve(rbo, false);
3107         if (unlikely(r)) {
3108                 DRM_ERROR("failed to reserve rbo before unpin\n");
3109                 return;
3110         }
3111
3112         amdgpu_bo_unpin(rbo);
3113         amdgpu_bo_unreserve(rbo);
3114         amdgpu_bo_unref(&rbo);
3115 }
3116
3117 int dm_create_validation_set_for_connector(struct drm_connector *connector,
3118                 struct drm_display_mode *mode, struct dc_validation_set *val_set)
3119 {
3120         int result = MODE_ERROR;
3121         struct dc_sink *dc_sink =
3122                         to_amdgpu_connector(connector)->dc_sink;
3123         /* TODO: Unhardcode stream count */
3124         struct dc_stream_state *stream;
3125
3126         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
3127                         (mode->flags & DRM_MODE_FLAG_DBLSCAN))
3128                 return result;
3129
3130         if (dc_sink == NULL) {
3131                 DRM_ERROR("dc_sink is NULL!\n");
3132                 return result;
3133         }
3134
3135         stream = dc_create_stream_for_sink(dc_sink);
3136
3137         if (stream == NULL) {
3138                 DRM_ERROR("Failed to create stream for sink!\n");
3139                 return result;
3140         }
3141
3142         drm_mode_set_crtcinfo(mode, 0);
3143
3144         fill_stream_properties_from_drm_display_mode(stream, mode, connector);
3145
3146         val_set->stream = stream;
3147
3148         stream->src.width = mode->hdisplay;
3149         stream->src.height = mode->vdisplay;
3150         stream->dst = stream->src;
3151
3152         return MODE_OK;
3153 }
3154
3155 int dm_plane_atomic_check(struct drm_plane *plane,
3156                             struct drm_plane_state *state)
3157 {
3158         struct amdgpu_device *adev = plane->dev->dev_private;
3159         struct dc *dc = adev->dm.dc;
3160         struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
3161
3162         if (!dm_plane_state->dc_state)
3163                 return 0;
3164
3165         if (dc_validate_plane(dc, dm_plane_state->dc_state))
3166                 return 0;
3167
3168         return -EINVAL;
3169 }
3170
3171 static const struct drm_plane_helper_funcs dm_plane_helper_funcs = {
3172         .prepare_fb = dm_plane_helper_prepare_fb,
3173         .cleanup_fb = dm_plane_helper_cleanup_fb,
3174         .atomic_check = dm_plane_atomic_check,
3175 };
3176
3177 /*
3178  * TODO: these are currently initialized to rgb formats only.
3179  * For future use cases we should either initialize them dynamically based on
3180  * plane capabilities, or initialize this array to all formats, so internal drm
3181  * check will succeed, and let DC to implement proper check
3182  */
3183 static uint32_t rgb_formats[] = {
3184         DRM_FORMAT_RGB888,
3185         DRM_FORMAT_XRGB8888,
3186         DRM_FORMAT_ARGB8888,
3187         DRM_FORMAT_RGBA8888,
3188         DRM_FORMAT_XRGB2101010,
3189         DRM_FORMAT_XBGR2101010,
3190         DRM_FORMAT_ARGB2101010,
3191         DRM_FORMAT_ABGR2101010,
3192 };
3193
3194 static uint32_t yuv_formats[] = {
3195         DRM_FORMAT_NV12,
3196         DRM_FORMAT_NV21,
3197 };
3198
3199 static const u32 cursor_formats[] = {
3200         DRM_FORMAT_ARGB8888
3201 };
3202
3203 int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
3204                         struct amdgpu_plane *aplane,
3205                         unsigned long possible_crtcs)
3206 {
3207         int res = -EPERM;
3208
3209         switch (aplane->base.type) {
3210         case DRM_PLANE_TYPE_PRIMARY:
3211                 aplane->base.format_default = true;
3212
3213                 res = drm_universal_plane_init(
3214                                 dm->adev->ddev,
3215                                 &aplane->base,
3216                                 possible_crtcs,
3217                                 &dm_plane_funcs,
3218                                 rgb_formats,
3219                                 ARRAY_SIZE(rgb_formats),
3220                                 NULL, aplane->base.type, NULL);
3221                 break;
3222         case DRM_PLANE_TYPE_OVERLAY:
3223                 res = drm_universal_plane_init(
3224                                 dm->adev->ddev,
3225                                 &aplane->base,
3226                                 possible_crtcs,
3227                                 &dm_plane_funcs,
3228                                 yuv_formats,
3229                                 ARRAY_SIZE(yuv_formats),
3230                                 NULL, aplane->base.type, NULL);
3231                 break;
3232         case DRM_PLANE_TYPE_CURSOR:
3233                 res = drm_universal_plane_init(
3234                                 dm->adev->ddev,
3235                                 &aplane->base,
3236                                 possible_crtcs,
3237                                 &dm_plane_funcs,
3238                                 cursor_formats,
3239                                 ARRAY_SIZE(cursor_formats),
3240                                 NULL, aplane->base.type, NULL);
3241                 break;
3242         }
3243
3244         drm_plane_helper_add(&aplane->base, &dm_plane_helper_funcs);
3245
3246         return res;
3247 }
3248
3249 int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
3250                         struct drm_plane *plane,
3251                         uint32_t crtc_index)
3252 {
3253         struct amdgpu_crtc *acrtc = NULL;
3254         struct amdgpu_plane *cursor_plane;
3255
3256         int res = -ENOMEM;
3257
3258         cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL);
3259         if (!cursor_plane)
3260                 goto fail;
3261
3262         cursor_plane->base.type = DRM_PLANE_TYPE_CURSOR;
3263         res = amdgpu_dm_plane_init(dm, cursor_plane, 0);
3264
3265         acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
3266         if (!acrtc)
3267                 goto fail;
3268
3269         res = drm_crtc_init_with_planes(
3270                         dm->ddev,
3271                         &acrtc->base,
3272                         plane,
3273                         &cursor_plane->base,
3274                         &amdgpu_dm_crtc_funcs, NULL);
3275
3276         if (res)
3277                 goto fail;
3278
3279         drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs);
3280
3281         acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;
3282         acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;
3283
3284         acrtc->crtc_id = crtc_index;
3285         acrtc->base.enabled = false;
3286
3287         dm->adev->mode_info.crtcs[crtc_index] = acrtc;
3288         drm_mode_crtc_set_gamma_size(&acrtc->base, 256);
3289
3290         return 0;
3291
3292 fail:
3293         kfree(acrtc);
3294         kfree(cursor_plane);
3295         acrtc->crtc_id = -1;
3296         return res;
3297 }
3298
3299
3300 static int to_drm_connector_type(enum signal_type st)
3301 {
3302         switch (st) {
3303         case SIGNAL_TYPE_HDMI_TYPE_A:
3304                 return DRM_MODE_CONNECTOR_HDMIA;
3305         case SIGNAL_TYPE_EDP:
3306                 return DRM_MODE_CONNECTOR_eDP;
3307         case SIGNAL_TYPE_RGB:
3308                 return DRM_MODE_CONNECTOR_VGA;
3309         case SIGNAL_TYPE_DISPLAY_PORT:
3310         case SIGNAL_TYPE_DISPLAY_PORT_MST:
3311                 return DRM_MODE_CONNECTOR_DisplayPort;
3312         case SIGNAL_TYPE_DVI_DUAL_LINK:
3313         case SIGNAL_TYPE_DVI_SINGLE_LINK:
3314                 return DRM_MODE_CONNECTOR_DVID;
3315         case SIGNAL_TYPE_VIRTUAL:
3316                 return DRM_MODE_CONNECTOR_VIRTUAL;
3317
3318         default:
3319                 return DRM_MODE_CONNECTOR_Unknown;
3320         }
3321 }
3322
3323 static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
3324 {
3325         const struct drm_connector_helper_funcs *helper =
3326                 connector->helper_private;
3327         struct drm_encoder *encoder;
3328         struct amdgpu_encoder *amdgpu_encoder;
3329
3330         encoder = helper->best_encoder(connector);
3331
3332         if (encoder == NULL)
3333                 return;
3334
3335         amdgpu_encoder = to_amdgpu_encoder(encoder);
3336
3337         amdgpu_encoder->native_mode.clock = 0;
3338
3339         if (!list_empty(&connector->probed_modes)) {
3340                 struct drm_display_mode *preferred_mode = NULL;
3341
3342                 list_for_each_entry(preferred_mode,
3343                                     &connector->probed_modes,
3344                                     head) {
3345                         if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED)
3346                                 amdgpu_encoder->native_mode = *preferred_mode;
3347
3348                         break;
3349                 }
3350
3351         }
3352 }
3353
3354 static struct drm_display_mode *amdgpu_dm_create_common_mode(
3355                 struct drm_encoder *encoder, char *name,
3356                 int hdisplay, int vdisplay)
3357 {
3358         struct drm_device *dev = encoder->dev;
3359         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3360         struct drm_display_mode *mode = NULL;
3361         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
3362
3363         mode = drm_mode_duplicate(dev, native_mode);
3364
3365         if (mode == NULL)
3366                 return NULL;
3367
3368         mode->hdisplay = hdisplay;
3369         mode->vdisplay = vdisplay;
3370         mode->type &= ~DRM_MODE_TYPE_PREFERRED;
3371         strncpy(mode->name, name, DRM_DISPLAY_MODE_LEN);
3372
3373         return mode;
3374
3375 }
3376
3377 static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
3378                                         struct drm_connector *connector)
3379 {
3380         struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3381         struct drm_display_mode *mode = NULL;
3382         struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
3383         struct amdgpu_connector *amdgpu_connector =
3384                                 to_amdgpu_connector(connector);
3385         int i;
3386         int n;
3387         struct mode_size {
3388                 char name[DRM_DISPLAY_MODE_LEN];
3389                 int w;
3390                 int h;
3391         } common_modes[] = {
3392                 {  "640x480",  640,  480},
3393                 {  "800x600",  800,  600},
3394                 { "1024x768", 1024,  768},
3395                 { "1280x720", 1280,  720},
3396                 { "1280x800", 1280,  800},
3397                 {"1280x1024", 1280, 1024},
3398                 { "1440x900", 1440,  900},
3399                 {"1680x1050", 1680, 1050},
3400                 {"1600x1200", 1600, 1200},
3401                 {"1920x1080", 1920, 1080},
3402                 {"1920x1200", 1920, 1200}
3403         };
3404
3405         n = ARRAY_SIZE(common_modes);
3406
3407         for (i = 0; i < n; i++) {
3408                 struct drm_display_mode *curmode = NULL;
3409                 bool mode_existed = false;
3410
3411                 if (common_modes[i].w > native_mode->hdisplay ||
3412                     common_modes[i].h > native_mode->vdisplay ||
3413                    (common_modes[i].w == native_mode->hdisplay &&
3414                     common_modes[i].h == native_mode->vdisplay))
3415                         continue;
3416
3417                 list_for_each_entry(curmode, &connector->probed_modes, head) {
3418                         if (common_modes[i].w == curmode->hdisplay &&
3419                             common_modes[i].h == curmode->vdisplay) {
3420                                 mode_existed = true;
3421                                 break;
3422                         }
3423                 }
3424
3425                 if (mode_existed)
3426                         continue;
3427
3428                 mode = amdgpu_dm_create_common_mode(encoder,
3429                                 common_modes[i].name, common_modes[i].w,
3430                                 common_modes[i].h);
3431                 drm_mode_probed_add(connector, mode);
3432                 amdgpu_connector->num_modes++;
3433         }
3434 }
3435
3436 static void amdgpu_dm_connector_ddc_get_modes(
3437         struct drm_connector *connector,
3438         struct edid *edid)
3439 {
3440         struct amdgpu_connector *amdgpu_connector =
3441                         to_amdgpu_connector(connector);
3442
3443         if (edid) {
3444                 /* empty probed_modes */
3445                 INIT_LIST_HEAD(&connector->probed_modes);
3446                 amdgpu_connector->num_modes =
3447                                 drm_add_edid_modes(connector, edid);
3448
3449                 drm_edid_to_eld(connector, edid);
3450
3451                 amdgpu_dm_get_native_mode(connector);
3452         } else
3453                 amdgpu_connector->num_modes = 0;
3454 }
3455
3456 int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
3457 {
3458         const struct drm_connector_helper_funcs *helper =
3459                         connector->helper_private;
3460         struct amdgpu_connector *amdgpu_connector =
3461                         to_amdgpu_connector(connector);
3462         struct drm_encoder *encoder;
3463         struct edid *edid = amdgpu_connector->edid;
3464
3465         encoder = helper->best_encoder(connector);
3466
3467         amdgpu_dm_connector_ddc_get_modes(connector, edid);
3468         amdgpu_dm_connector_add_common_modes(encoder, connector);
3469         return amdgpu_connector->num_modes;
3470 }
3471
3472 void amdgpu_dm_connector_init_helper(
3473         struct amdgpu_display_manager *dm,
3474         struct amdgpu_connector *aconnector,
3475         int connector_type,
3476         struct dc_link *link,
3477         int link_index)
3478 {
3479         struct amdgpu_device *adev = dm->ddev->dev_private;
3480
3481         aconnector->connector_id = link_index;
3482         aconnector->dc_link = link;
3483         aconnector->base.interlace_allowed = false;
3484         aconnector->base.doublescan_allowed = false;
3485         aconnector->base.stereo_allowed = false;
3486         aconnector->base.dpms = DRM_MODE_DPMS_OFF;
3487         aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
3488
3489         mutex_init(&aconnector->hpd_lock);
3490
3491         /* configure support HPD hot plug connector_>polled default value is 0
3492          * which means HPD hot plug not supported
3493          */
3494         switch (connector_type) {
3495         case DRM_MODE_CONNECTOR_HDMIA:
3496                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
3497                 break;
3498         case DRM_MODE_CONNECTOR_DisplayPort:
3499                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
3500                 break;
3501         case DRM_MODE_CONNECTOR_DVID:
3502                 aconnector->base.polled = DRM_CONNECTOR_POLL_HPD;
3503                 break;
3504         default:
3505                 break;
3506         }
3507
3508         drm_object_attach_property(&aconnector->base.base,
3509                                 dm->ddev->mode_config.scaling_mode_property,
3510                                 DRM_MODE_SCALE_NONE);
3511
3512         drm_object_attach_property(&aconnector->base.base,
3513                                 adev->mode_info.underscan_property,
3514                                 UNDERSCAN_OFF);
3515         drm_object_attach_property(&aconnector->base.base,
3516                                 adev->mode_info.underscan_hborder_property,
3517                                 0);
3518         drm_object_attach_property(&aconnector->base.base,
3519                                 adev->mode_info.underscan_vborder_property,
3520                                 0);
3521
3522 }
3523
3524 int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
3525                       struct i2c_msg *msgs, int num)
3526 {
3527         struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
3528         struct ddc_service *ddc_service = i2c->ddc_service;
3529         struct i2c_command cmd;
3530         int i;
3531         int result = -EIO;
3532
3533         cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL);
3534
3535         if (!cmd.payloads)
3536                 return result;
3537
3538         cmd.number_of_payloads = num;
3539         cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
3540         cmd.speed = 100;
3541
3542         for (i = 0; i < num; i++) {
3543                 cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD);
3544                 cmd.payloads[i].address = msgs[i].addr;
3545                 cmd.payloads[i].length = msgs[i].len;
3546                 cmd.payloads[i].data = msgs[i].buf;
3547         }
3548
3549         if (dal_i2caux_submit_i2c_command(
3550                         ddc_service->ctx->i2caux,
3551                         ddc_service->ddc_pin,
3552                         &cmd))
3553                 result = num;
3554
3555         kfree(cmd.payloads);
3556         return result;
3557 }
3558
3559 u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
3560 {
3561         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
3562 }
3563
3564 static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
3565         .master_xfer = amdgpu_dm_i2c_xfer,
3566         .functionality = amdgpu_dm_i2c_func,
3567 };
3568
3569 static struct amdgpu_i2c_adapter *create_i2c(
3570                 struct ddc_service *ddc_service,
3571                 int link_index,
3572                 int *res)
3573 {
3574         struct amdgpu_device *adev = ddc_service->ctx->driver_context;
3575         struct amdgpu_i2c_adapter *i2c;
3576
3577         i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL);
3578         i2c->base.owner = THIS_MODULE;
3579         i2c->base.class = I2C_CLASS_DDC;
3580         i2c->base.dev.parent = &adev->pdev->dev;
3581         i2c->base.algo = &amdgpu_dm_i2c_algo;
3582         snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
3583         i2c_set_adapdata(&i2c->base, i2c);
3584         i2c->ddc_service = ddc_service;
3585
3586         return i2c;
3587 }
3588
3589 /* Note: this function assumes that dc_link_detect() was called for the
3590  * dc_link which will be represented by this aconnector.
3591  */
3592 int amdgpu_dm_connector_init(
3593         struct amdgpu_display_manager *dm,
3594         struct amdgpu_connector *aconnector,
3595         uint32_t link_index,
3596         struct amdgpu_encoder *aencoder)
3597 {
3598         int res = 0;
3599         int connector_type;
3600         struct dc *dc = dm->dc;
3601         struct dc_link *link = dc_get_link_at_index(dc, link_index);
3602         struct amdgpu_i2c_adapter *i2c;
3603         ((struct dc_link *)link)->priv = aconnector;
3604
3605         DRM_DEBUG_KMS("%s()\n", __func__);
3606
3607         i2c = create_i2c(link->ddc, link->link_index, &res);
3608         aconnector->i2c = i2c;
3609         res = i2c_add_adapter(&i2c->base);
3610
3611         if (res) {
3612                 DRM_ERROR("Failed to register hw i2c %d\n", link->link_index);
3613                 goto out_free;
3614         }
3615
3616         connector_type = to_drm_connector_type(link->connector_signal);
3617
3618         res = drm_connector_init(
3619                         dm->ddev,
3620                         &aconnector->base,
3621                         &amdgpu_dm_connector_funcs,
3622                         connector_type);
3623
3624         if (res) {
3625                 DRM_ERROR("connector_init failed\n");
3626                 aconnector->connector_id = -1;
3627                 goto out_free;
3628         }
3629
3630         drm_connector_helper_add(
3631                         &aconnector->base,
3632                         &amdgpu_dm_connector_helper_funcs);
3633
3634         amdgpu_dm_connector_init_helper(
3635                 dm,
3636                 aconnector,
3637                 connector_type,
3638                 link,
3639                 link_index);
3640
3641         drm_mode_connector_attach_encoder(
3642                 &aconnector->base, &aencoder->base);
3643
3644         drm_connector_register(&aconnector->base);
3645
3646         if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
3647                 || connector_type == DRM_MODE_CONNECTOR_eDP)
3648                 amdgpu_dm_initialize_dp_connector(dm, aconnector);
3649
3650 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
3651         defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
3652
3653         /* NOTE: this currently will create backlight device even if a panel
3654          * is not connected to the eDP/LVDS connector.
3655          *
3656          * This is less than ideal but we don't have sink information at this
3657          * stage since detection happens after. We can't do detection earlier
3658          * since MST detection needs connectors to be created first.
3659          */
3660         if (link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) {
3661                 /* Event if registration failed, we should continue with
3662                  * DM initialization because not having a backlight control
3663                  * is better then a black screen.
3664                  */
3665                 amdgpu_dm_register_backlight_device(dm);
3666
3667                 if (dm->backlight_dev)
3668                         dm->backlight_link = link;
3669         }
3670 #endif
3671
3672 out_free:
3673         if (res) {
3674                 kfree(i2c);
3675                 aconnector->i2c = NULL;
3676         }
3677         return res;
3678 }
3679
3680 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
3681 {
3682         switch (adev->mode_info.num_crtc) {
3683         case 1:
3684                 return 0x1;
3685         case 2:
3686                 return 0x3;
3687         case 3:
3688                 return 0x7;
3689         case 4:
3690                 return 0xf;
3691         case 5:
3692                 return 0x1f;
3693         case 6:
3694         default:
3695                 return 0x3f;
3696         }
3697 }
3698
3699 int amdgpu_dm_encoder_init(
3700         struct drm_device *dev,
3701         struct amdgpu_encoder *aencoder,
3702         uint32_t link_index)
3703 {
3704         struct amdgpu_device *adev = dev->dev_private;
3705
3706         int res = drm_encoder_init(dev,
3707                                    &aencoder->base,
3708                                    &amdgpu_dm_encoder_funcs,
3709                                    DRM_MODE_ENCODER_TMDS,
3710                                    NULL);
3711
3712         aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);
3713
3714         if (!res)
3715                 aencoder->encoder_id = link_index;
3716         else
3717                 aencoder->encoder_id = -1;
3718
3719         drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);
3720
3721         return res;
3722 }
3723
3724 static void manage_dm_interrupts(
3725         struct amdgpu_device *adev,
3726         struct amdgpu_crtc *acrtc,
3727         bool enable)
3728 {
3729         /*
3730          * this is not correct translation but will work as soon as VBLANK
3731          * constant is the same as PFLIP
3732          */
3733         int irq_type =
3734                 amdgpu_crtc_idx_to_irq_type(
3735                         adev,
3736                         acrtc->crtc_id);
3737
3738         if (enable) {
3739                 drm_crtc_vblank_on(&acrtc->base);
3740                 amdgpu_irq_get(
3741                         adev,
3742                         &adev->pageflip_irq,
3743                         irq_type);
3744         } else {
3745
3746                 amdgpu_irq_put(
3747                         adev,
3748                         &adev->pageflip_irq,
3749                         irq_type);
3750                 drm_crtc_vblank_off(&acrtc->base);
3751         }
3752 }
3753
3754 static bool is_scaling_state_different(
3755                 const struct dm_connector_state *dm_state,
3756                 const struct dm_connector_state *old_dm_state)
3757 {
3758         if (dm_state->scaling != old_dm_state->scaling)
3759                 return true;
3760         if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
3761                 if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
3762                         return true;
3763         } else  if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
3764                 if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
3765                         return true;
3766         } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
3767                    dm_state->underscan_vborder != old_dm_state->underscan_vborder)
3768                 return true;
3769         return false;
3770 }
3771
3772 static void remove_stream(
3773                 struct amdgpu_device *adev,
3774                 struct amdgpu_crtc *acrtc,
3775                 struct dc_stream_state *stream)
3776 {
3777         /* this is the update mode case */
3778         if (adev->dm.freesync_module)
3779                 mod_freesync_remove_stream(adev->dm.freesync_module, stream);
3780
3781         acrtc->otg_inst = -1;
3782         acrtc->enabled = false;
3783 }
3784
3785 static void handle_cursor_update(
3786                 struct drm_plane *plane,
3787                 struct drm_plane_state *old_plane_state)
3788 {
3789         if (!plane->state->fb && !old_plane_state->fb)
3790                 return;
3791
3792         /* Check if it's a cursor on/off update or just cursor move*/
3793         if (plane->state->fb == old_plane_state->fb)
3794                 dm_crtc_cursor_move(
3795                                 plane->state->crtc,
3796                                 plane->state->crtc_x,
3797                                 plane->state->crtc_y);
3798         else {
3799                 struct amdgpu_framebuffer *afb =
3800                                 to_amdgpu_framebuffer(plane->state->fb);
3801                 dm_crtc_cursor_set(
3802                                 (!!plane->state->fb) ?
3803                                                 plane->state->crtc :
3804                                                 old_plane_state->crtc,
3805                                 (!!plane->state->fb) ?
3806                                                 afb->address :
3807                                                 0,
3808                                 plane->state->crtc_w,
3809                                 plane->state->crtc_h);
3810         }
3811 }
3812
3813
3814 static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
3815 {
3816
3817         assert_spin_locked(&acrtc->base.dev->event_lock);
3818         WARN_ON(acrtc->event);
3819
3820         acrtc->event = acrtc->base.state->event;
3821
3822         /* Set the flip status */
3823         acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
3824
3825         /* Mark this event as consumed */
3826         acrtc->base.state->event = NULL;
3827
3828         DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",
3829                                                  acrtc->crtc_id);
3830 }
3831
3832 /*
3833  * Executes flip
3834  *
3835  * Waits on all BO's fences and for proper vblank count
3836  */
3837 static void amdgpu_dm_do_flip(
3838                                 struct drm_crtc *crtc,
3839                                 struct drm_framebuffer *fb,
3840                                 uint32_t target)
3841 {
3842         unsigned long flags;
3843         uint32_t target_vblank;
3844         int r, vpos, hpos;
3845         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3846         struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb);
3847         struct amdgpu_bo *abo = gem_to_amdgpu_bo(afb->obj);
3848         struct amdgpu_device *adev = crtc->dev->dev_private;
3849         bool async_flip = (acrtc->flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0;
3850         struct dc_flip_addrs addr = { {0} };
3851         /* TODO eliminate or rename surface_update */
3852         struct dc_surface_update surface_updates[1] = { {0} };
3853         struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
3854
3855
3856         /* Prepare wait for target vblank early - before the fence-waits */
3857         target_vblank = target - drm_crtc_vblank_count(crtc) +
3858                         amdgpu_get_vblank_counter_kms(crtc->dev, acrtc->crtc_id);
3859
3860         /* TODO This might fail and hence better not used, wait
3861          * explicitly on fences instead
3862          * and in general should be called for
3863          * blocking commit to as per framework helpers
3864          */
3865         r = amdgpu_bo_reserve(abo, true);
3866         if (unlikely(r != 0)) {
3867                 DRM_ERROR("failed to reserve buffer before flip\n");
3868                 WARN_ON(1);
3869         }
3870
3871         /* Wait for all fences on this FB */
3872         WARN_ON(reservation_object_wait_timeout_rcu(abo->tbo.resv, true, false,
3873                                                                     MAX_SCHEDULE_TIMEOUT) < 0);
3874
3875         amdgpu_bo_unreserve(abo);
3876
3877         /* Wait until we're out of the vertical blank period before the one
3878          * targeted by the flip
3879          */
3880         while ((acrtc->enabled &&
3881                 (amdgpu_get_crtc_scanoutpos(adev->ddev, acrtc->crtc_id, 0,
3882                                         &vpos, &hpos, NULL, NULL,
3883                                         &crtc->hwmode)
3884                  & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) ==
3885                 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) &&
3886                 (int)(target_vblank -
3887                   amdgpu_get_vblank_counter_kms(adev->ddev, acrtc->crtc_id)) > 0)) {
3888                 usleep_range(1000, 1100);
3889         }
3890
3891         /* Flip */
3892         spin_lock_irqsave(&crtc->dev->event_lock, flags);
3893         /* update crtc fb */
3894         crtc->primary->fb = fb;
3895
3896         WARN_ON(acrtc->pflip_status != AMDGPU_FLIP_NONE);
3897         WARN_ON(!acrtc_state->stream);
3898
3899         addr.address.grph.addr.low_part = lower_32_bits(afb->address);
3900         addr.address.grph.addr.high_part = upper_32_bits(afb->address);
3901         addr.flip_immediate = async_flip;
3902
3903
3904         if (acrtc->base.state->event)
3905                 prepare_flip_isr(acrtc);
3906
3907         surface_updates->surface = dc_stream_get_status(acrtc_state->stream)->plane_states[0];
3908         surface_updates->flip_addr = &addr;
3909
3910
3911         dc_update_planes_and_stream(adev->dm.dc, surface_updates, 1, acrtc_state->stream, NULL);
3912
3913         DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x \n",
3914                          __func__,
3915                          addr.address.grph.addr.high_part,
3916                          addr.address.grph.addr.low_part);
3917
3918
3919         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
3920 }
3921
3922 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
3923                         struct drm_device *dev,
3924                         struct amdgpu_display_manager *dm,
3925                         struct drm_crtc *pcrtc,
3926                         bool *wait_for_vblank)
3927 {
3928         uint32_t i;
3929         struct drm_plane *plane;
3930         struct drm_plane_state *old_plane_state;
3931         struct dc_stream_state *dc_stream_attach;
3932         struct dc_plane_state *plane_states_constructed[MAX_SURFACES];
3933         struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
3934         struct dm_crtc_state *acrtc_state = to_dm_crtc_state(pcrtc->state);
3935         int planes_count = 0;
3936         unsigned long flags;
3937
3938         /* update planes when needed */
3939         for_each_plane_in_state(state, plane, old_plane_state, i) {
3940                 struct drm_plane_state *plane_state = plane->state;
3941                 struct drm_crtc *crtc = plane_state->crtc;
3942                 struct drm_framebuffer *fb = plane_state->fb;
3943                 bool pflip_needed;
3944                 struct dm_plane_state *dm_plane_state = to_dm_plane_state(plane_state);
3945
3946                 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
3947                         handle_cursor_update(plane, old_plane_state);
3948                         continue;
3949                 }
3950
3951                 if (!fb || !crtc || pcrtc != crtc || !crtc->state->active ||
3952                                 (!crtc->state->planes_changed &&
3953                                                 !pcrtc->state->color_mgmt_changed))
3954                         continue;
3955
3956                 pflip_needed = !state->allow_modeset;
3957
3958                 spin_lock_irqsave(&crtc->dev->event_lock, flags);
3959                 if (acrtc_attach->pflip_status != AMDGPU_FLIP_NONE) {
3960                         DRM_ERROR("%s: acrtc %d, already busy\n",
3961                                   __func__,
3962                                   acrtc_attach->crtc_id);
3963                         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
3964                         /* In commit tail framework this cannot happen */
3965                         WARN_ON(1);
3966                 }
3967                 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
3968
3969                 if (!pflip_needed) {
3970                         WARN_ON(!dm_plane_state->dc_state);
3971
3972                         plane_states_constructed[planes_count] = dm_plane_state->dc_state;
3973
3974                         dc_stream_attach = acrtc_state->stream;
3975                         planes_count++;
3976
3977                 } else if (crtc->state->planes_changed) {
3978                         /* Assume even ONE crtc with immediate flip means
3979                          * entire can't wait for VBLANK
3980                          * TODO Check if it's correct
3981                          */
3982                         *wait_for_vblank =
3983                                 acrtc_attach->flip_flags & DRM_MODE_PAGE_FLIP_ASYNC ?
3984                                 false : true;
3985
3986                         /* TODO: Needs rework for multiplane flip */
3987                         if (plane->type == DRM_PLANE_TYPE_PRIMARY)
3988                                 drm_crtc_vblank_get(crtc);
3989
3990                         amdgpu_dm_do_flip(
3991                                 crtc,
3992                                 fb,
3993                                 drm_crtc_vblank_count(crtc) + *wait_for_vblank);
3994
3995                         /*TODO BUG remove ASAP in 4.12 to avoid race between worker and flip IOCTL */
3996
3997                         /*clean up the flags for next usage*/
3998                         acrtc_attach->flip_flags = 0;
3999                 }
4000
4001         }
4002
4003         if (planes_count) {
4004                 unsigned long flags;
4005
4006                 if (pcrtc->state->event) {
4007
4008                         drm_crtc_vblank_get(pcrtc);
4009
4010                         spin_lock_irqsave(&pcrtc->dev->event_lock, flags);
4011                         prepare_flip_isr(acrtc_attach);
4012                         spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags);
4013                 }
4014
4015                 if (false == dc_commit_planes_to_stream(dm->dc,
4016                                                         plane_states_constructed,
4017                                                         planes_count,
4018                                                         dc_stream_attach))
4019                         dm_error("%s: Failed to attach plane!\n", __func__);
4020         } else {
4021                 /*TODO BUG Here should go disable planes on CRTC. */
4022         }
4023 }
4024
4025
4026 int amdgpu_dm_atomic_commit(
4027                 struct drm_device *dev,
4028                 struct drm_atomic_state *state,
4029                 bool nonblock)
4030 {
4031         struct drm_crtc *crtc;
4032         struct drm_crtc_state *new_state;
4033         struct amdgpu_device *adev = dev->dev_private;
4034         int i;
4035
4036         /*
4037          * We evade vblanks and pflips on crtc that
4038          * should be changed. We do it here to flush & disable
4039          * interrupts before drm_swap_state is called in drm_atomic_helper_commit
4040          * it will update crtc->dm_crtc_state->stream pointer which is used in
4041          * the ISRs.
4042          */
4043         for_each_crtc_in_state(state, crtc, new_state, i) {
4044                 struct dm_crtc_state *old_acrtc_state = to_dm_crtc_state(crtc->state);
4045                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
4046
4047                 if (drm_atomic_crtc_needs_modeset(new_state) && old_acrtc_state->stream)
4048                         manage_dm_interrupts(adev, acrtc, false);
4049         }
4050
4051         return drm_atomic_helper_commit(dev, state, nonblock);
4052
4053         /*TODO Handle EINTR, reenable IRQ*/
4054 }
4055
4056 void amdgpu_dm_atomic_commit_tail(
4057         struct drm_atomic_state *state)
4058 {
4059         struct drm_device *dev = state->dev;
4060         struct amdgpu_device *adev = dev->dev_private;
4061         struct amdgpu_display_manager *dm = &adev->dm;
4062         struct dm_atomic_state *dm_state;
4063         uint32_t i, j;
4064         uint32_t new_crtcs_count = 0;
4065         struct drm_crtc *crtc, *pcrtc;
4066         struct drm_crtc_state *old_crtc_state;
4067         struct amdgpu_crtc *new_crtcs[MAX_STREAMS];
4068         struct dc_stream_state *new_stream = NULL;
4069         unsigned long flags;
4070         bool wait_for_vblank = true;
4071         struct drm_connector *connector;
4072         struct drm_connector_state *old_conn_state;
4073         struct dm_crtc_state *old_acrtc_state, *new_acrtc_state;
4074
4075         drm_atomic_helper_update_legacy_modeset_state(dev, state);
4076
4077         dm_state = to_dm_atomic_state(state);
4078
4079         /* update changed items */
4080         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
4081                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
4082                 struct drm_crtc_state *new_state = crtc->state;
4083
4084                 new_acrtc_state = to_dm_crtc_state(new_state);
4085                 old_acrtc_state = to_dm_crtc_state(old_crtc_state);
4086
4087                 DRM_DEBUG_KMS(
4088                         "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
4089                         "planes_changed:%d, mode_changed:%d,active_changed:%d,"
4090                         "connectors_changed:%d\n",
4091                         acrtc->crtc_id,
4092                         new_state->enable,
4093                         new_state->active,
4094                         new_state->planes_changed,
4095                         new_state->mode_changed,
4096                         new_state->active_changed,
4097                         new_state->connectors_changed);
4098
4099                 /* handles headless hotplug case, updating new_state and
4100                  * aconnector as needed
4101                  */
4102
4103                 if (modeset_required(new_state, new_acrtc_state->stream, old_acrtc_state->stream)) {
4104
4105                         DRM_INFO("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc);
4106
4107                         if (!new_acrtc_state->stream) {
4108                                 /*
4109                                  * this could happen because of issues with
4110                                  * userspace notifications delivery.
4111                                  * In this case userspace tries to set mode on
4112                                  * display which is disconnect in fact.
4113                                  * dc_sink in NULL in this case on aconnector.
4114                                  * We expect reset mode will come soon.
4115                                  *
4116                                  * This can also happen when unplug is done
4117                                  * during resume sequence ended
4118                                  *
4119                                  * In this case, we want to pretend we still
4120                                  * have a sink to keep the pipe running so that
4121                                  * hw state is consistent with the sw state
4122                                  */
4123                                 DRM_DEBUG_KMS("%s: Failed to create new stream for crtc %d\n",
4124                                                 __func__, acrtc->base.base.id);
4125                                 continue;
4126                         }
4127
4128
4129                         if (old_acrtc_state->stream)
4130                                 remove_stream(adev, acrtc, old_acrtc_state->stream);
4131
4132
4133                         /*
4134                          * this loop saves set mode crtcs
4135                          * we needed to enable vblanks once all
4136                          * resources acquired in dc after dc_commit_streams
4137                          */
4138
4139                         /*TODO move all this into dm_crtc_state, get rid of
4140                          * new_crtcs array and use old and new atomic states
4141                          * instead
4142                          */
4143                         new_crtcs[new_crtcs_count] = acrtc;
4144                         new_crtcs_count++;
4145
4146                         acrtc->enabled = true;
4147                         acrtc->hw_mode = crtc->state->mode;
4148                         crtc->hwmode = crtc->state->mode;
4149                 } else if (modereset_required(new_state)) {
4150                         DRM_INFO("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc);
4151
4152                         /* i.e. reset mode */
4153                         if (old_acrtc_state->stream)
4154                                 remove_stream(adev, acrtc, old_acrtc_state->stream);
4155                 }
4156         } /* for_each_crtc_in_state() */
4157
4158         /*
4159          * Add streams after required streams from new and replaced streams
4160          * are removed from freesync module
4161          */
4162         if (adev->dm.freesync_module) {
4163                 for (i = 0; i < new_crtcs_count; i++) {
4164                         struct amdgpu_connector *aconnector = NULL;
4165
4166                         new_acrtc_state = to_dm_crtc_state(new_crtcs[i]->base.state);
4167
4168                         new_stream = new_acrtc_state->stream;
4169                         aconnector =
4170                                 amdgpu_dm_find_first_crct_matching_connector(
4171                                         state,
4172                                         &new_crtcs[i]->base,
4173                                         false);
4174                         if (!aconnector) {
4175                                 DRM_INFO("Atomic commit: Failed to find connector for acrtc id:%d "
4176                                          "skipping freesync init\n",
4177                                          new_crtcs[i]->crtc_id);
4178                                 continue;
4179                         }
4180
4181                         mod_freesync_add_stream(adev->dm.freesync_module,
4182                                                 new_stream, &aconnector->caps);
4183                 }
4184         }
4185
4186         if (dm_state->context)
4187                 WARN_ON(!dc_commit_context(dm->dc, dm_state->context));
4188
4189
4190         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4191                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
4192
4193                 new_acrtc_state = to_dm_crtc_state(crtc->state);
4194
4195                 if (new_acrtc_state->stream != NULL) {
4196                         const struct dc_stream_status *status =
4197                                         dc_stream_get_status(new_acrtc_state->stream);
4198
4199                         if (!status)
4200                                 DC_ERR("got no status for stream %p on acrtc%p\n", new_acrtc_state->stream, acrtc);
4201                         else
4202                                 acrtc->otg_inst = status->primary_otg_inst;
4203                 }
4204         }
4205
4206         /* Handle scaling and undersacn changes*/
4207         for_each_connector_in_state(state, connector, old_conn_state, i) {
4208                 struct amdgpu_connector *aconnector = to_amdgpu_connector(connector);
4209                 struct dm_connector_state *con_new_state =
4210                                 to_dm_connector_state(aconnector->base.state);
4211                 struct dm_connector_state *con_old_state =
4212                                 to_dm_connector_state(old_conn_state);
4213                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(con_new_state->base.crtc);
4214                 struct dc_stream_status *status = NULL;
4215
4216                 /* Skip any modesets/resets */
4217                 if (!acrtc || drm_atomic_crtc_needs_modeset(acrtc->base.state))
4218                         continue;
4219
4220                 /* Skip any thing not scale or underscan changes */
4221                 if (!is_scaling_state_different(con_new_state, con_old_state))
4222                         continue;
4223
4224                 new_acrtc_state = to_dm_crtc_state(acrtc->base.state);
4225
4226                 update_stream_scaling_settings(&con_new_state->base.crtc->mode,
4227                                 con_new_state, (struct dc_stream_state *)new_acrtc_state->stream);
4228
4229                 status = dc_stream_get_status(new_acrtc_state->stream);
4230                 WARN_ON(!status);
4231                 WARN_ON(!status->plane_count);
4232
4233                 if (!new_acrtc_state->stream)
4234                         continue;
4235
4236                 /*TODO How it works with MPO ?*/
4237                 if (!dc_commit_planes_to_stream(
4238                                 dm->dc,
4239                                 status->plane_states,
4240                                 status->plane_count,
4241                                 new_acrtc_state->stream))
4242                         dm_error("%s: Failed to update stream scaling!\n", __func__);
4243         }
4244
4245         for (i = 0; i < new_crtcs_count; i++) {
4246                 /*
4247                  * loop to enable interrupts on newly arrived crtc
4248                  */
4249                 struct amdgpu_crtc *acrtc = new_crtcs[i];
4250
4251                 new_acrtc_state = to_dm_crtc_state(acrtc->base.state);
4252
4253                 if (adev->dm.freesync_module)
4254                         mod_freesync_notify_mode_change(
4255                                 adev->dm.freesync_module, &new_acrtc_state->stream, 1);
4256
4257                 manage_dm_interrupts(adev, acrtc, true);
4258         }
4259
4260         /* update planes when needed per crtc*/
4261         for_each_crtc_in_state(state, pcrtc, old_crtc_state, j) {
4262                 new_acrtc_state = to_dm_crtc_state(pcrtc->state);
4263
4264                 if (new_acrtc_state->stream)
4265                         amdgpu_dm_commit_planes(state, dev, dm, pcrtc, &wait_for_vblank);
4266         }
4267
4268
4269         /*
4270          * send vblank event on all events not handled in flip and
4271          * mark consumed event for drm_atomic_helper_commit_hw_done
4272          */
4273         spin_lock_irqsave(&adev->ddev->event_lock, flags);
4274         for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
4275                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
4276
4277                 if (acrtc->base.state->event)
4278                         drm_send_event_locked(dev, &crtc->state->event->base);
4279
4280                 acrtc->base.state->event = NULL;
4281         }
4282         spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
4283
4284         /* Signal HW programming completion */
4285         drm_atomic_helper_commit_hw_done(state);
4286
4287         if (wait_for_vblank)
4288                 drm_atomic_helper_wait_for_vblanks(dev, state);
4289
4290         drm_atomic_helper_cleanup_planes(dev, state);
4291 }
4292
4293
4294 static int dm_force_atomic_commit(struct drm_connector *connector)
4295 {
4296         int ret = 0;
4297         struct drm_device *ddev = connector->dev;
4298         struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
4299         struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
4300         struct drm_plane *plane = disconnected_acrtc->base.primary;
4301         struct drm_connector_state *conn_state;
4302         struct drm_crtc_state *crtc_state;
4303         struct drm_plane_state *plane_state;
4304
4305         if (!state)
4306                 return -ENOMEM;
4307
4308         state->acquire_ctx = ddev->mode_config.acquire_ctx;
4309
4310         /* Construct an atomic state to restore previous display setting */
4311
4312         /*
4313          * Attach connectors to drm_atomic_state
4314          */
4315         conn_state = drm_atomic_get_connector_state(state, connector);
4316
4317         ret = PTR_ERR_OR_ZERO(conn_state);
4318         if (ret)
4319                 goto err;
4320
4321         /* Attach crtc to drm_atomic_state*/
4322         crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);
4323
4324         ret = PTR_ERR_OR_ZERO(crtc_state);
4325         if (ret)
4326                 goto err;
4327
4328         /* force a restore */
4329         crtc_state->mode_changed = true;
4330
4331         /* Attach plane to drm_atomic_state */
4332         plane_state = drm_atomic_get_plane_state(state, plane);
4333
4334         ret = PTR_ERR_OR_ZERO(plane_state);
4335         if (ret)
4336                 goto err;
4337
4338
4339         /* Call commit internally with the state we just constructed */
4340         ret = drm_atomic_commit(state);
4341         if (!ret)
4342                 return 0;
4343
4344 err:
4345         DRM_ERROR("Restoring old state failed with %i\n", ret);
4346         drm_atomic_state_put(state);
4347
4348         return ret;
4349 }
4350
4351 /*
4352  * This functions handle all cases when set mode does not come upon hotplug.
4353  * This include when the same display is unplugged then plugged back into the
4354  * same port and when we are running without usermode desktop manager supprot
4355  */
4356 void dm_restore_drm_connector_state(struct drm_device *dev, struct drm_connector *connector)
4357 {
4358         struct amdgpu_connector *aconnector = to_amdgpu_connector(connector);
4359         struct amdgpu_crtc *disconnected_acrtc;
4360         struct dm_crtc_state *acrtc_state;
4361
4362         if (!aconnector->dc_sink || !connector->state || !connector->encoder)
4363                 return;
4364
4365         disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc);
4366         acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state);
4367
4368         if (!disconnected_acrtc || !acrtc_state->stream)
4369                 return;
4370
4371         /*
4372          * If the previous sink is not released and different from the current,
4373          * we deduce we are in a state where we can not rely on usermode call
4374          * to turn on the display, so we do it here
4375          */
4376         if (acrtc_state->stream->sink != aconnector->dc_sink)
4377                 dm_force_atomic_commit(&aconnector->base);
4378 }
4379
4380 static uint32_t add_val_sets_plane(
4381         struct dc_validation_set *val_sets,
4382         uint32_t set_count,
4383         const struct dc_stream_state *stream,
4384         struct dc_plane_state *plane_state)
4385 {
4386         uint32_t i = 0, j = 0;
4387
4388         while (i < set_count) {
4389                 if (val_sets[i].stream == stream) {
4390                         while (val_sets[i].plane_states[j])
4391                                 j++;
4392                         break;
4393                 }
4394                 ++i;
4395         }
4396
4397         val_sets[i].plane_states[j] = plane_state;
4398         val_sets[i].plane_count++;
4399
4400         return val_sets[i].plane_count;
4401 }
4402
4403 static uint32_t update_in_val_sets_stream(
4404         struct dc_validation_set *val_sets,
4405         uint32_t set_count,
4406         struct dc_stream_state *old_stream,
4407         struct dc_stream_state *new_stream,
4408         struct drm_crtc *crtc)
4409 {
4410         uint32_t i = 0;
4411
4412         while (i < set_count) {
4413                 if (val_sets[i].stream == old_stream)
4414                         break;
4415                 ++i;
4416         }
4417
4418         val_sets[i].stream = new_stream;
4419
4420         if (i == set_count)
4421                 /* nothing found. add new one to the end */
4422                 return set_count + 1;
4423
4424         return set_count;
4425 }
4426
4427 static uint32_t remove_from_val_sets(
4428         struct dc_validation_set *val_sets,
4429         uint32_t set_count,
4430         const struct dc_stream_state *stream)
4431 {
4432         int i;
4433
4434         for (i = 0; i < set_count; i++)
4435                 if (val_sets[i].stream == stream)
4436                         break;
4437
4438         if (i == set_count) {
4439                 /* nothing found */
4440                 return set_count;
4441         }
4442
4443         set_count--;
4444
4445         for (; i < set_count; i++)
4446                 val_sets[i] = val_sets[i + 1];
4447
4448         return set_count;
4449 }
4450
4451 /*`
4452  * Grabs all modesetting locks to serialize against any blocking commits,
4453  * Waits for completion of all non blocking commits.
4454  */
4455 static int do_aquire_global_lock(
4456                 struct drm_device *dev,
4457                 struct drm_atomic_state *state)
4458 {
4459         struct drm_crtc *crtc;
4460         struct drm_crtc_commit *commit;
4461         long ret;
4462
4463         /* Adding all modeset locks to aquire_ctx will
4464          * ensure that when the framework release it the
4465          * extra locks we are locking here will get released to
4466          */
4467         ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
4468         if (ret)
4469                 return ret;
4470
4471         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4472                 spin_lock(&crtc->commit_lock);
4473                 commit = list_first_entry_or_null(&crtc->commit_list,
4474                                 struct drm_crtc_commit, commit_entry);
4475                 if (commit)
4476                         drm_crtc_commit_get(commit);
4477                 spin_unlock(&crtc->commit_lock);
4478
4479                 if (!commit)
4480                         continue;
4481
4482                 /* Make sure all pending HW programming completed and
4483                  * page flips done
4484                  */
4485                 ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ);
4486
4487                 if (ret > 0)
4488                         ret = wait_for_completion_interruptible_timeout(
4489                                         &commit->flip_done, 10*HZ);
4490
4491                 if (ret == 0)
4492                         DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "
4493                                   "timed out\n", crtc->base.id, crtc->name);
4494
4495                 drm_crtc_commit_put(commit);
4496         }
4497
4498         return ret < 0 ? ret : 0;
4499 }
4500
4501 int amdgpu_dm_atomic_check(struct drm_device *dev,
4502                         struct drm_atomic_state *state)
4503 {
4504         struct dm_atomic_state *dm_state;
4505         struct drm_crtc *crtc;
4506         struct drm_crtc_state *crtc_state;
4507         struct drm_plane *plane;
4508         struct drm_plane_state *plane_state;
4509         int i, j;
4510         int ret;
4511         struct amdgpu_device *adev = dev->dev_private;
4512         struct dc *dc = adev->dm.dc;
4513         struct drm_connector *connector;
4514         struct drm_connector_state *conn_state;
4515         int set_count;
4516         struct dc_validation_set set[MAX_STREAMS] = { { 0 } };
4517         struct dm_crtc_state *old_acrtc_state, *new_acrtc_state;
4518
4519         /*
4520          * This bool will be set for true for any modeset/reset
4521          * or plane update which implies non fast surface update.
4522          */
4523         bool lock_and_validation_needed = false;
4524
4525         ret = drm_atomic_helper_check_modeset(dev, state);
4526
4527         if (ret) {
4528                 DRM_ERROR("Atomic state validation failed with error :%d !\n", ret);
4529                 return ret;
4530         }
4531
4532         dm_state = to_dm_atomic_state(state);
4533
4534         /* copy existing configuration */
4535         set_count = 0;
4536         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4537
4538                 old_acrtc_state = to_dm_crtc_state(crtc->state);
4539
4540                 if (old_acrtc_state->stream) {
4541                         dc_stream_retain(old_acrtc_state->stream);
4542                         set[set_count].stream = old_acrtc_state->stream;
4543                         ++set_count;
4544                 }
4545         }
4546
4547         /*TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set */
4548         /* update changed items */
4549         for_each_crtc_in_state(state, crtc, crtc_state, i) {
4550                 struct amdgpu_crtc *acrtc = NULL;
4551                 struct amdgpu_connector *aconnector = NULL;
4552                 struct dc_stream_state *new_stream = NULL;
4553                 struct drm_connector_state *conn_state = NULL;
4554                 struct dm_connector_state *dm_conn_state = NULL;
4555
4556                 old_acrtc_state = to_dm_crtc_state(crtc->state);
4557                 new_acrtc_state = to_dm_crtc_state(crtc_state);
4558                 acrtc = to_amdgpu_crtc(crtc);
4559
4560                 aconnector = amdgpu_dm_find_first_crct_matching_connector(state, crtc, true);
4561
4562                 DRM_DEBUG_KMS(
4563                         "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "
4564                         "planes_changed:%d, mode_changed:%d,active_changed:%d,"
4565                         "connectors_changed:%d\n",
4566                         acrtc->crtc_id,
4567                         crtc_state->enable,
4568                         crtc_state->active,
4569                         crtc_state->planes_changed,
4570                         crtc_state->mode_changed,
4571                         crtc_state->active_changed,
4572                         crtc_state->connectors_changed);
4573
4574                 if (modereset_required(crtc_state)) {
4575
4576                                         /* i.e. reset mode */
4577                         if (new_acrtc_state->stream) {
4578                                 set_count = remove_from_val_sets(
4579                                                 set,
4580                                                 set_count,
4581                                                 new_acrtc_state->stream);
4582
4583                                 dc_stream_release(new_acrtc_state->stream);
4584                                 new_acrtc_state->stream = NULL;
4585
4586                                 lock_and_validation_needed = true;
4587                         }
4588
4589                 } else {
4590
4591                         if (aconnector) {
4592                                 conn_state = drm_atomic_get_connector_state(state,
4593                                                                             &aconnector->base);
4594
4595                                 if (IS_ERR(conn_state)) {
4596                                         ret = PTR_ERR_OR_ZERO(conn_state);
4597                                         goto fail;
4598                                 }
4599
4600                                 dm_conn_state = to_dm_connector_state(conn_state);
4601
4602                                 new_stream = create_stream_for_sink(aconnector,
4603                                                                     &crtc_state->mode,
4604                                                                     dm_conn_state);
4605
4606                                 if (!new_stream) {
4607                                         DRM_DEBUG_KMS("%s: Failed to create new stream for crtc %d\n",
4608                                                         __func__, acrtc->base.base.id);
4609                                         break;
4610                                 }
4611
4612
4613                         }
4614
4615                         if (modeset_required(crtc_state, new_stream,
4616                                              old_acrtc_state->stream)) {
4617
4618
4619                         /*
4620                          * we can have no stream on ACTION_SET if a display
4621                          * was disconnected during S3, in this case it not and
4622                          * error, the OS will be updated after detection, and
4623                          * do the right thing on next atomic commit
4624                          */
4625
4626                                 if (new_acrtc_state->stream)
4627                                         dc_stream_release(new_acrtc_state->stream);
4628
4629                                 new_acrtc_state->stream = new_stream;
4630
4631                                 set_count = update_in_val_sets_stream(
4632                                                 set,
4633                                                 set_count,
4634                                                 old_acrtc_state->stream,
4635                                                 new_acrtc_state->stream,
4636                                                 crtc);
4637
4638                                 lock_and_validation_needed = true;
4639                         } else {
4640                                 /*
4641                                  * The new stream is unused, so we release it
4642                                  */
4643                                 if (new_stream)
4644                                         dc_stream_release(new_stream);
4645
4646                         }
4647                 }
4648
4649
4650                 /*
4651                  * Hack: Commit needs planes right now, specifically for gamma
4652                  * TODO rework commit to check CRTC for gamma change
4653                  */
4654                 if (crtc_state->color_mgmt_changed) {
4655
4656                         ret = drm_atomic_add_affected_planes(state, crtc);
4657                         if (ret)
4658                                 goto fail;
4659                 }
4660         }
4661
4662         /* Check scaling and undersacn changes*/
4663         /*TODO Removed scaling changes validation due to inability to commit
4664          * new stream into context w\o causing full reset. Need to
4665          * decide how to handle.
4666          */
4667         for_each_connector_in_state(state, connector, conn_state, i) {
4668                 struct amdgpu_connector *aconnector = to_amdgpu_connector(connector);
4669                 struct dm_connector_state *con_old_state =
4670                                 to_dm_connector_state(aconnector->base.state);
4671                 struct dm_connector_state *con_new_state =
4672                                                 to_dm_connector_state(conn_state);
4673                 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(con_new_state->base.crtc);
4674
4675                 /* Skip any modesets/resets */
4676                 if (!acrtc || drm_atomic_crtc_needs_modeset(acrtc->base.state))
4677                         continue;
4678
4679                 /* Skip any thing not scale or underscan changes */
4680                 if (!is_scaling_state_different(con_new_state, con_old_state))
4681                         continue;
4682
4683                 lock_and_validation_needed = true;
4684         }
4685
4686         for_each_crtc_in_state(state, crtc, crtc_state, i) {
4687                 new_acrtc_state = to_dm_crtc_state(crtc_state);
4688
4689                 for_each_plane_in_state(state, plane, plane_state, j) {
4690                         struct drm_crtc *plane_crtc = plane_state->crtc;
4691                         struct drm_framebuffer *fb = plane_state->fb;
4692                         bool pflip_needed;
4693                         struct dm_plane_state *dm_plane_state = to_dm_plane_state(plane_state);
4694
4695                         /*TODO Implement atomic check for cursor plane */
4696                         if (plane->type == DRM_PLANE_TYPE_CURSOR)
4697                                 continue;
4698
4699                         if (!fb || !plane_crtc || crtc != plane_crtc || !crtc_state->active)
4700                                 continue;
4701
4702                         WARN_ON(!new_acrtc_state->stream);
4703
4704                         pflip_needed = !state->allow_modeset;
4705                         if (!pflip_needed) {
4706                                 struct dc_plane_state *dc_plane_state;
4707
4708                                 dc_plane_state = dc_create_plane_state(dc);
4709
4710                                 if (dm_plane_state->dc_state)
4711                                         dc_plane_state_release(dm_plane_state->dc_state);
4712
4713                                 dm_plane_state->dc_state = dc_plane_state;
4714
4715                                 ret = fill_plane_attributes(
4716                                         plane_crtc->dev->dev_private,
4717                                         dc_plane_state,
4718                                         plane_state,
4719                                         crtc_state,
4720                                         false);
4721                                 if (ret)
4722                                         goto fail;
4723
4724                                 add_val_sets_plane(set,
4725                                                      set_count,
4726                                                      new_acrtc_state->stream,
4727                                                      dc_plane_state);
4728
4729                                 lock_and_validation_needed = true;
4730                         }
4731                 }
4732         }
4733
4734         /* Run this here since we want to validate the streams we created */
4735         ret = drm_atomic_helper_check_planes(dev, state);
4736         if (ret)
4737                 goto fail;
4738
4739         /*
4740          * For full updates case when
4741          * removing/adding/updating  streams on once CRTC while flipping
4742          * on another CRTC,
4743          * acquiring global lock  will guarantee that any such full
4744          * update commit
4745          * will wait for completion of any outstanding flip using DRMs
4746          * synchronization events.
4747          */
4748
4749         if (lock_and_validation_needed) {
4750
4751                 ret = do_aquire_global_lock(dev, state);
4752                 if (ret)
4753                         goto fail;
4754                 WARN_ON(dm_state->context);
4755                 dm_state->context = dc_get_validate_context(dc, set, set_count);
4756                 if (!dm_state->context) {
4757                         ret = -EINVAL;
4758                         goto fail;
4759                 }
4760         }
4761
4762         /* Must be success */
4763         WARN_ON(ret);
4764         return ret;
4765
4766 fail:
4767         if (ret == -EDEADLK)
4768                 DRM_DEBUG_KMS("Atomic check stopped due to to deadlock.\n");
4769         else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS)
4770                 DRM_DEBUG_KMS("Atomic check stopped due to to signal.\n");
4771         else
4772                 DRM_ERROR("Atomic check failed with err: %d .\n", ret);
4773
4774         return ret;
4775 }
4776
4777 static bool is_dp_capable_without_timing_msa(
4778                 struct dc *dc,
4779                 struct amdgpu_connector *amdgpu_connector)
4780 {
4781         uint8_t dpcd_data;
4782         bool capable = false;
4783
4784         if (amdgpu_connector->dc_link &&
4785                 dm_helpers_dp_read_dpcd(
4786                                 NULL,
4787                                 amdgpu_connector->dc_link,
4788                                 DP_DOWN_STREAM_PORT_COUNT,
4789                                 &dpcd_data,
4790                                 sizeof(dpcd_data))) {
4791                 capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
4792         }
4793
4794         return capable;
4795 }
4796 void amdgpu_dm_add_sink_to_freesync_module(
4797                 struct drm_connector *connector,
4798                 struct edid *edid)
4799 {
4800         int i;
4801         uint64_t val_capable;
4802         bool edid_check_required;
4803         struct detailed_timing *timing;
4804         struct detailed_non_pixel *data;
4805         struct detailed_data_monitor_range *range;
4806         struct amdgpu_connector *amdgpu_connector =
4807                         to_amdgpu_connector(connector);
4808
4809         struct drm_device *dev = connector->dev;
4810         struct amdgpu_device *adev = dev->dev_private;
4811
4812         edid_check_required = false;
4813         if (!amdgpu_connector->dc_sink) {
4814                 DRM_ERROR("dc_sink NULL, could not add free_sync module.\n");
4815                 return;
4816         }
4817         if (!adev->dm.freesync_module)
4818                 return;
4819         /*
4820          * if edid non zero restrict freesync only for dp and edp
4821          */
4822         if (edid) {
4823                 if (amdgpu_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
4824                         || amdgpu_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) {
4825                         edid_check_required = is_dp_capable_without_timing_msa(
4826                                                 adev->dm.dc,
4827                                                 amdgpu_connector);
4828                 }
4829         }
4830         val_capable = 0;
4831         if (edid_check_required == true && (edid->version > 1 ||
4832            (edid->version == 1 && edid->revision > 1))) {
4833                 for (i = 0; i < 4; i++) {
4834
4835                         timing  = &edid->detailed_timings[i];
4836                         data    = &timing->data.other_data;
4837                         range   = &data->data.range;
4838                         /*
4839                          * Check if monitor has continuous frequency mode
4840                          */
4841                         if (data->type != EDID_DETAIL_MONITOR_RANGE)
4842                                 continue;
4843                         /*
4844                          * Check for flag range limits only. If flag == 1 then
4845                          * no additional timing information provided.
4846                          * Default GTF, GTF Secondary curve and CVT are not
4847                          * supported
4848                          */
4849                         if (range->flags != 1)
4850                                 continue;
4851
4852                         amdgpu_connector->min_vfreq = range->min_vfreq;
4853                         amdgpu_connector->max_vfreq = range->max_vfreq;
4854                         amdgpu_connector->pixel_clock_mhz =
4855                                 range->pixel_clock_mhz * 10;
4856                         break;
4857                 }
4858
4859                 if (amdgpu_connector->max_vfreq -
4860                                 amdgpu_connector->min_vfreq > 10) {
4861                         amdgpu_connector->caps.supported = true;
4862                         amdgpu_connector->caps.min_refresh_in_micro_hz =
4863                                         amdgpu_connector->min_vfreq * 1000000;
4864                         amdgpu_connector->caps.max_refresh_in_micro_hz =
4865                                         amdgpu_connector->max_vfreq * 1000000;
4866                                 val_capable = 1;
4867                 }
4868         }
4869
4870         /*
4871          * TODO figure out how to notify user-mode or DRM of freesync caps
4872          * once we figure out how to deal with freesync in an upstreamable
4873          * fashion
4874          */
4875
4876 }
4877
4878 void amdgpu_dm_remove_sink_from_freesync_module(
4879                 struct drm_connector *connector)
4880 {
4881         /*
4882          * TODO fill in once we figure out how to deal with freesync in
4883          * an upstreamable fashion
4884          */
4885 }