1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * Copyright 2014-2022 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/types.h>
25 #include <linux/kernel.h>
26 #include <linux/pci.h>
27 #include <linux/errno.h>
28 #include <linux/acpi.h>
29 #include <linux/hash.h>
30 #include <linux/cpufreq.h>
31 #include <linux/log2.h>
32 #include <linux/dmi.h>
33 #include <linux/atomic.h>
37 #include "kfd_topology.h"
38 #include "kfd_device_queue_manager.h"
40 #include "kfd_debug.h"
41 #include "amdgpu_amdkfd.h"
42 #include "amdgpu_ras.h"
45 /* topology_device_list - Master list of all topology devices */
46 static struct list_head topology_device_list;
47 static struct kfd_system_properties sys_props;
49 static DECLARE_RWSEM(topology_lock);
50 static uint32_t topology_crat_proximity_domain;
52 struct kfd_topology_device *kfd_topology_device_by_proximity_domain_no_lock(
53 uint32_t proximity_domain)
55 struct kfd_topology_device *top_dev;
56 struct kfd_topology_device *device = NULL;
58 list_for_each_entry(top_dev, &topology_device_list, list)
59 if (top_dev->proximity_domain == proximity_domain) {
67 struct kfd_topology_device *kfd_topology_device_by_proximity_domain(
68 uint32_t proximity_domain)
70 struct kfd_topology_device *device = NULL;
72 down_read(&topology_lock);
74 device = kfd_topology_device_by_proximity_domain_no_lock(
76 up_read(&topology_lock);
81 struct kfd_topology_device *kfd_topology_device_by_id(uint32_t gpu_id)
83 struct kfd_topology_device *top_dev = NULL;
84 struct kfd_topology_device *ret = NULL;
86 down_read(&topology_lock);
88 list_for_each_entry(top_dev, &topology_device_list, list)
89 if (top_dev->gpu_id == gpu_id) {
94 up_read(&topology_lock);
99 struct kfd_node *kfd_device_by_id(uint32_t gpu_id)
101 struct kfd_topology_device *top_dev;
103 top_dev = kfd_topology_device_by_id(gpu_id);
110 struct kfd_node *kfd_device_by_pci_dev(const struct pci_dev *pdev)
112 struct kfd_topology_device *top_dev;
113 struct kfd_node *device = NULL;
115 down_read(&topology_lock);
117 list_for_each_entry(top_dev, &topology_device_list, list)
118 if (top_dev->gpu && top_dev->gpu->adev->pdev == pdev) {
119 device = top_dev->gpu;
123 up_read(&topology_lock);
128 /* Called with write topology_lock acquired */
129 static void kfd_release_topology_device(struct kfd_topology_device *dev)
131 struct kfd_mem_properties *mem;
132 struct kfd_cache_properties *cache;
133 struct kfd_iolink_properties *iolink;
134 struct kfd_iolink_properties *p2plink;
135 struct kfd_perf_properties *perf;
137 list_del(&dev->list);
139 while (dev->mem_props.next != &dev->mem_props) {
140 mem = container_of(dev->mem_props.next,
141 struct kfd_mem_properties, list);
142 list_del(&mem->list);
146 while (dev->cache_props.next != &dev->cache_props) {
147 cache = container_of(dev->cache_props.next,
148 struct kfd_cache_properties, list);
149 list_del(&cache->list);
153 while (dev->io_link_props.next != &dev->io_link_props) {
154 iolink = container_of(dev->io_link_props.next,
155 struct kfd_iolink_properties, list);
156 list_del(&iolink->list);
160 while (dev->p2p_link_props.next != &dev->p2p_link_props) {
161 p2plink = container_of(dev->p2p_link_props.next,
162 struct kfd_iolink_properties, list);
163 list_del(&p2plink->list);
167 while (dev->perf_props.next != &dev->perf_props) {
168 perf = container_of(dev->perf_props.next,
169 struct kfd_perf_properties, list);
170 list_del(&perf->list);
177 void kfd_release_topology_device_list(struct list_head *device_list)
179 struct kfd_topology_device *dev;
181 while (!list_empty(device_list)) {
182 dev = list_first_entry(device_list,
183 struct kfd_topology_device, list);
184 kfd_release_topology_device(dev);
188 static void kfd_release_live_view(void)
190 kfd_release_topology_device_list(&topology_device_list);
191 memset(&sys_props, 0, sizeof(sys_props));
194 struct kfd_topology_device *kfd_create_topology_device(
195 struct list_head *device_list)
197 struct kfd_topology_device *dev;
199 dev = kfd_alloc_struct(dev);
201 pr_err("No memory to allocate a topology device");
205 INIT_LIST_HEAD(&dev->mem_props);
206 INIT_LIST_HEAD(&dev->cache_props);
207 INIT_LIST_HEAD(&dev->io_link_props);
208 INIT_LIST_HEAD(&dev->p2p_link_props);
209 INIT_LIST_HEAD(&dev->perf_props);
211 list_add_tail(&dev->list, device_list);
217 #define sysfs_show_gen_prop(buffer, offs, fmt, ...) \
218 (offs += snprintf(buffer+offs, PAGE_SIZE-offs, \
220 #define sysfs_show_32bit_prop(buffer, offs, name, value) \
221 sysfs_show_gen_prop(buffer, offs, "%s %u\n", name, value)
222 #define sysfs_show_64bit_prop(buffer, offs, name, value) \
223 sysfs_show_gen_prop(buffer, offs, "%s %llu\n", name, value)
224 #define sysfs_show_32bit_val(buffer, offs, value) \
225 sysfs_show_gen_prop(buffer, offs, "%u\n", value)
226 #define sysfs_show_str_val(buffer, offs, value) \
227 sysfs_show_gen_prop(buffer, offs, "%s\n", value)
229 static ssize_t sysprops_show(struct kobject *kobj, struct attribute *attr,
234 /* Making sure that the buffer is an empty string */
237 if (attr == &sys_props.attr_genid) {
238 sysfs_show_32bit_val(buffer, offs,
239 sys_props.generation_count);
240 } else if (attr == &sys_props.attr_props) {
241 sysfs_show_64bit_prop(buffer, offs, "platform_oem",
242 sys_props.platform_oem);
243 sysfs_show_64bit_prop(buffer, offs, "platform_id",
244 sys_props.platform_id);
245 sysfs_show_64bit_prop(buffer, offs, "platform_rev",
246 sys_props.platform_rev);
254 static void kfd_topology_kobj_release(struct kobject *kobj)
259 static const struct sysfs_ops sysprops_ops = {
260 .show = sysprops_show,
263 static const struct kobj_type sysprops_type = {
264 .release = kfd_topology_kobj_release,
265 .sysfs_ops = &sysprops_ops,
268 static ssize_t iolink_show(struct kobject *kobj, struct attribute *attr,
272 struct kfd_iolink_properties *iolink;
274 /* Making sure that the buffer is an empty string */
277 iolink = container_of(attr, struct kfd_iolink_properties, attr);
278 if (iolink->gpu && kfd_devcgroup_check_permission(iolink->gpu))
280 sysfs_show_32bit_prop(buffer, offs, "type", iolink->iolink_type);
281 sysfs_show_32bit_prop(buffer, offs, "version_major", iolink->ver_maj);
282 sysfs_show_32bit_prop(buffer, offs, "version_minor", iolink->ver_min);
283 sysfs_show_32bit_prop(buffer, offs, "node_from", iolink->node_from);
284 sysfs_show_32bit_prop(buffer, offs, "node_to", iolink->node_to);
285 sysfs_show_32bit_prop(buffer, offs, "weight", iolink->weight);
286 sysfs_show_32bit_prop(buffer, offs, "min_latency", iolink->min_latency);
287 sysfs_show_32bit_prop(buffer, offs, "max_latency", iolink->max_latency);
288 sysfs_show_32bit_prop(buffer, offs, "min_bandwidth",
289 iolink->min_bandwidth);
290 sysfs_show_32bit_prop(buffer, offs, "max_bandwidth",
291 iolink->max_bandwidth);
292 sysfs_show_32bit_prop(buffer, offs, "recommended_transfer_size",
293 iolink->rec_transfer_size);
294 sysfs_show_32bit_prop(buffer, offs, "flags", iolink->flags);
299 static const struct sysfs_ops iolink_ops = {
303 static const struct kobj_type iolink_type = {
304 .release = kfd_topology_kobj_release,
305 .sysfs_ops = &iolink_ops,
308 static ssize_t mem_show(struct kobject *kobj, struct attribute *attr,
312 struct kfd_mem_properties *mem;
314 /* Making sure that the buffer is an empty string */
317 mem = container_of(attr, struct kfd_mem_properties, attr);
318 if (mem->gpu && kfd_devcgroup_check_permission(mem->gpu))
320 sysfs_show_32bit_prop(buffer, offs, "heap_type", mem->heap_type);
321 sysfs_show_64bit_prop(buffer, offs, "size_in_bytes",
323 sysfs_show_32bit_prop(buffer, offs, "flags", mem->flags);
324 sysfs_show_32bit_prop(buffer, offs, "width", mem->width);
325 sysfs_show_32bit_prop(buffer, offs, "mem_clk_max",
331 static const struct sysfs_ops mem_ops = {
335 static const struct kobj_type mem_type = {
336 .release = kfd_topology_kobj_release,
337 .sysfs_ops = &mem_ops,
340 static ssize_t kfd_cache_show(struct kobject *kobj, struct attribute *attr,
345 struct kfd_cache_properties *cache;
347 /* Making sure that the buffer is an empty string */
349 cache = container_of(attr, struct kfd_cache_properties, attr);
350 if (cache->gpu && kfd_devcgroup_check_permission(cache->gpu))
352 sysfs_show_32bit_prop(buffer, offs, "processor_id_low",
353 cache->processor_id_low);
354 sysfs_show_32bit_prop(buffer, offs, "level", cache->cache_level);
355 sysfs_show_32bit_prop(buffer, offs, "size", cache->cache_size);
356 sysfs_show_32bit_prop(buffer, offs, "cache_line_size",
357 cache->cacheline_size);
358 sysfs_show_32bit_prop(buffer, offs, "cache_lines_per_tag",
359 cache->cachelines_per_tag);
360 sysfs_show_32bit_prop(buffer, offs, "association", cache->cache_assoc);
361 sysfs_show_32bit_prop(buffer, offs, "latency", cache->cache_latency);
362 sysfs_show_32bit_prop(buffer, offs, "type", cache->cache_type);
364 offs += snprintf(buffer+offs, PAGE_SIZE-offs, "sibling_map ");
365 for (i = 0; i < cache->sibling_map_size; i++)
366 for (j = 0; j < sizeof(cache->sibling_map[0])*8; j++)
368 offs += snprintf(buffer+offs, PAGE_SIZE-offs, "%d,",
369 (cache->sibling_map[i] >> j) & 1);
371 /* Replace the last "," with end of line */
372 buffer[offs-1] = '\n';
376 static const struct sysfs_ops cache_ops = {
377 .show = kfd_cache_show,
380 static const struct kobj_type cache_type = {
381 .release = kfd_topology_kobj_release,
382 .sysfs_ops = &cache_ops,
385 /****** Sysfs of Performance Counters ******/
387 struct kfd_perf_attr {
388 struct kobj_attribute attr;
392 static ssize_t perf_show(struct kobject *kobj, struct kobj_attribute *attrs,
396 struct kfd_perf_attr *attr;
399 attr = container_of(attrs, struct kfd_perf_attr, attr);
400 if (!attr->data) /* invalid data for PMC */
403 return sysfs_show_32bit_val(buf, offs, attr->data);
406 #define KFD_PERF_DESC(_name, _data) \
408 .attr = __ATTR(_name, 0444, perf_show, NULL), \
412 static struct kfd_perf_attr perf_attr_iommu[] = {
413 KFD_PERF_DESC(max_concurrent, 0),
414 KFD_PERF_DESC(num_counters, 0),
415 KFD_PERF_DESC(counter_ids, 0),
417 /****************************************/
419 static ssize_t node_show(struct kobject *kobj, struct attribute *attr,
423 struct kfd_topology_device *dev;
424 uint32_t log_max_watch_addr;
426 /* Making sure that the buffer is an empty string */
429 if (strcmp(attr->name, "gpu_id") == 0) {
430 dev = container_of(attr, struct kfd_topology_device,
432 if (dev->gpu && kfd_devcgroup_check_permission(dev->gpu))
434 return sysfs_show_32bit_val(buffer, offs, dev->gpu_id);
437 if (strcmp(attr->name, "name") == 0) {
438 dev = container_of(attr, struct kfd_topology_device,
441 if (dev->gpu && kfd_devcgroup_check_permission(dev->gpu))
443 return sysfs_show_str_val(buffer, offs, dev->node_props.name);
446 dev = container_of(attr, struct kfd_topology_device,
448 if (dev->gpu && kfd_devcgroup_check_permission(dev->gpu))
450 sysfs_show_32bit_prop(buffer, offs, "cpu_cores_count",
451 dev->node_props.cpu_cores_count);
452 sysfs_show_32bit_prop(buffer, offs, "simd_count",
453 dev->gpu ? (dev->node_props.simd_count *
454 NUM_XCC(dev->gpu->xcc_mask)) : 0);
455 sysfs_show_32bit_prop(buffer, offs, "mem_banks_count",
456 dev->node_props.mem_banks_count);
457 sysfs_show_32bit_prop(buffer, offs, "caches_count",
458 dev->node_props.caches_count);
459 sysfs_show_32bit_prop(buffer, offs, "io_links_count",
460 dev->node_props.io_links_count);
461 sysfs_show_32bit_prop(buffer, offs, "p2p_links_count",
462 dev->node_props.p2p_links_count);
463 sysfs_show_32bit_prop(buffer, offs, "cpu_core_id_base",
464 dev->node_props.cpu_core_id_base);
465 sysfs_show_32bit_prop(buffer, offs, "simd_id_base",
466 dev->node_props.simd_id_base);
467 sysfs_show_32bit_prop(buffer, offs, "max_waves_per_simd",
468 dev->node_props.max_waves_per_simd);
469 sysfs_show_32bit_prop(buffer, offs, "lds_size_in_kb",
470 dev->node_props.lds_size_in_kb);
471 sysfs_show_32bit_prop(buffer, offs, "gds_size_in_kb",
472 dev->node_props.gds_size_in_kb);
473 sysfs_show_32bit_prop(buffer, offs, "num_gws",
474 dev->node_props.num_gws);
475 sysfs_show_32bit_prop(buffer, offs, "wave_front_size",
476 dev->node_props.wave_front_size);
477 sysfs_show_32bit_prop(buffer, offs, "array_count",
478 dev->gpu ? (dev->node_props.array_count *
479 NUM_XCC(dev->gpu->xcc_mask)) : 0);
480 sysfs_show_32bit_prop(buffer, offs, "simd_arrays_per_engine",
481 dev->node_props.simd_arrays_per_engine);
482 sysfs_show_32bit_prop(buffer, offs, "cu_per_simd_array",
483 dev->node_props.cu_per_simd_array);
484 sysfs_show_32bit_prop(buffer, offs, "simd_per_cu",
485 dev->node_props.simd_per_cu);
486 sysfs_show_32bit_prop(buffer, offs, "max_slots_scratch_cu",
487 dev->node_props.max_slots_scratch_cu);
488 sysfs_show_32bit_prop(buffer, offs, "gfx_target_version",
489 dev->node_props.gfx_target_version);
490 sysfs_show_32bit_prop(buffer, offs, "vendor_id",
491 dev->node_props.vendor_id);
492 sysfs_show_32bit_prop(buffer, offs, "device_id",
493 dev->node_props.device_id);
494 sysfs_show_32bit_prop(buffer, offs, "location_id",
495 dev->node_props.location_id);
496 sysfs_show_32bit_prop(buffer, offs, "domain",
497 dev->node_props.domain);
498 sysfs_show_32bit_prop(buffer, offs, "drm_render_minor",
499 dev->node_props.drm_render_minor);
500 sysfs_show_64bit_prop(buffer, offs, "hive_id",
501 dev->node_props.hive_id);
502 sysfs_show_32bit_prop(buffer, offs, "num_sdma_engines",
503 dev->node_props.num_sdma_engines);
504 sysfs_show_32bit_prop(buffer, offs, "num_sdma_xgmi_engines",
505 dev->node_props.num_sdma_xgmi_engines);
506 sysfs_show_32bit_prop(buffer, offs, "num_sdma_queues_per_engine",
507 dev->node_props.num_sdma_queues_per_engine);
508 sysfs_show_32bit_prop(buffer, offs, "num_cp_queues",
509 dev->node_props.num_cp_queues);
513 __ilog2_u32(dev->gpu->kfd->device_info.num_of_watch_points);
515 if (log_max_watch_addr) {
516 dev->node_props.capability |=
517 HSA_CAP_WATCH_POINTS_SUPPORTED;
519 dev->node_props.capability |=
520 ((log_max_watch_addr <<
521 HSA_CAP_WATCH_POINTS_TOTALBITS_SHIFT) &
522 HSA_CAP_WATCH_POINTS_TOTALBITS_MASK);
525 if (dev->gpu->adev->asic_type == CHIP_TONGA)
526 dev->node_props.capability |=
527 HSA_CAP_AQL_QUEUE_DOUBLE_MAP;
529 sysfs_show_32bit_prop(buffer, offs, "max_engine_clk_fcompute",
530 dev->node_props.max_engine_clk_fcompute);
532 sysfs_show_64bit_prop(buffer, offs, "local_mem_size", 0ULL);
534 sysfs_show_32bit_prop(buffer, offs, "fw_version",
535 dev->gpu->kfd->mec_fw_version);
536 sysfs_show_32bit_prop(buffer, offs, "capability",
537 dev->node_props.capability);
538 sysfs_show_64bit_prop(buffer, offs, "debug_prop",
539 dev->node_props.debug_prop);
540 sysfs_show_32bit_prop(buffer, offs, "sdma_fw_version",
541 dev->gpu->kfd->sdma_fw_version);
542 sysfs_show_64bit_prop(buffer, offs, "unique_id",
543 dev->gpu->adev->unique_id);
544 sysfs_show_32bit_prop(buffer, offs, "num_xcc",
545 NUM_XCC(dev->gpu->xcc_mask));
548 return sysfs_show_32bit_prop(buffer, offs, "max_engine_clk_ccompute",
549 cpufreq_quick_get_max(0)/1000);
552 static const struct sysfs_ops node_ops = {
556 static const struct kobj_type node_type = {
557 .release = kfd_topology_kobj_release,
558 .sysfs_ops = &node_ops,
561 static void kfd_remove_sysfs_file(struct kobject *kobj, struct attribute *attr)
563 sysfs_remove_file(kobj, attr);
568 static void kfd_remove_sysfs_node_entry(struct kfd_topology_device *dev)
570 struct kfd_iolink_properties *p2plink;
571 struct kfd_iolink_properties *iolink;
572 struct kfd_cache_properties *cache;
573 struct kfd_mem_properties *mem;
574 struct kfd_perf_properties *perf;
576 if (dev->kobj_iolink) {
577 list_for_each_entry(iolink, &dev->io_link_props, list)
579 kfd_remove_sysfs_file(iolink->kobj,
583 kobject_del(dev->kobj_iolink);
584 kobject_put(dev->kobj_iolink);
585 dev->kobj_iolink = NULL;
588 if (dev->kobj_p2plink) {
589 list_for_each_entry(p2plink, &dev->p2p_link_props, list)
591 kfd_remove_sysfs_file(p2plink->kobj,
593 p2plink->kobj = NULL;
595 kobject_del(dev->kobj_p2plink);
596 kobject_put(dev->kobj_p2plink);
597 dev->kobj_p2plink = NULL;
600 if (dev->kobj_cache) {
601 list_for_each_entry(cache, &dev->cache_props, list)
603 kfd_remove_sysfs_file(cache->kobj,
607 kobject_del(dev->kobj_cache);
608 kobject_put(dev->kobj_cache);
609 dev->kobj_cache = NULL;
613 list_for_each_entry(mem, &dev->mem_props, list)
615 kfd_remove_sysfs_file(mem->kobj, &mem->attr);
618 kobject_del(dev->kobj_mem);
619 kobject_put(dev->kobj_mem);
620 dev->kobj_mem = NULL;
623 if (dev->kobj_perf) {
624 list_for_each_entry(perf, &dev->perf_props, list) {
625 kfree(perf->attr_group);
626 perf->attr_group = NULL;
628 kobject_del(dev->kobj_perf);
629 kobject_put(dev->kobj_perf);
630 dev->kobj_perf = NULL;
633 if (dev->kobj_node) {
634 sysfs_remove_file(dev->kobj_node, &dev->attr_gpuid);
635 sysfs_remove_file(dev->kobj_node, &dev->attr_name);
636 sysfs_remove_file(dev->kobj_node, &dev->attr_props);
637 kobject_del(dev->kobj_node);
638 kobject_put(dev->kobj_node);
639 dev->kobj_node = NULL;
643 static int kfd_build_sysfs_node_entry(struct kfd_topology_device *dev,
646 struct kfd_iolink_properties *p2plink;
647 struct kfd_iolink_properties *iolink;
648 struct kfd_cache_properties *cache;
649 struct kfd_mem_properties *mem;
650 struct kfd_perf_properties *perf;
652 uint32_t i, num_attrs;
653 struct attribute **attrs;
655 if (WARN_ON(dev->kobj_node))
659 * Creating the sysfs folders
661 dev->kobj_node = kfd_alloc_struct(dev->kobj_node);
665 ret = kobject_init_and_add(dev->kobj_node, &node_type,
666 sys_props.kobj_nodes, "%d", id);
668 kobject_put(dev->kobj_node);
672 dev->kobj_mem = kobject_create_and_add("mem_banks", dev->kobj_node);
676 dev->kobj_cache = kobject_create_and_add("caches", dev->kobj_node);
677 if (!dev->kobj_cache)
680 dev->kobj_iolink = kobject_create_and_add("io_links", dev->kobj_node);
681 if (!dev->kobj_iolink)
684 dev->kobj_p2plink = kobject_create_and_add("p2p_links", dev->kobj_node);
685 if (!dev->kobj_p2plink)
688 dev->kobj_perf = kobject_create_and_add("perf", dev->kobj_node);
693 * Creating sysfs files for node properties
695 dev->attr_gpuid.name = "gpu_id";
696 dev->attr_gpuid.mode = KFD_SYSFS_FILE_MODE;
697 sysfs_attr_init(&dev->attr_gpuid);
698 dev->attr_name.name = "name";
699 dev->attr_name.mode = KFD_SYSFS_FILE_MODE;
700 sysfs_attr_init(&dev->attr_name);
701 dev->attr_props.name = "properties";
702 dev->attr_props.mode = KFD_SYSFS_FILE_MODE;
703 sysfs_attr_init(&dev->attr_props);
704 ret = sysfs_create_file(dev->kobj_node, &dev->attr_gpuid);
707 ret = sysfs_create_file(dev->kobj_node, &dev->attr_name);
710 ret = sysfs_create_file(dev->kobj_node, &dev->attr_props);
715 list_for_each_entry(mem, &dev->mem_props, list) {
716 mem->kobj = kzalloc(sizeof(struct kobject), GFP_KERNEL);
719 ret = kobject_init_and_add(mem->kobj, &mem_type,
720 dev->kobj_mem, "%d", i);
722 kobject_put(mem->kobj);
726 mem->attr.name = "properties";
727 mem->attr.mode = KFD_SYSFS_FILE_MODE;
728 sysfs_attr_init(&mem->attr);
729 ret = sysfs_create_file(mem->kobj, &mem->attr);
736 list_for_each_entry(cache, &dev->cache_props, list) {
737 cache->kobj = kzalloc(sizeof(struct kobject), GFP_KERNEL);
740 ret = kobject_init_and_add(cache->kobj, &cache_type,
741 dev->kobj_cache, "%d", i);
743 kobject_put(cache->kobj);
747 cache->attr.name = "properties";
748 cache->attr.mode = KFD_SYSFS_FILE_MODE;
749 sysfs_attr_init(&cache->attr);
750 ret = sysfs_create_file(cache->kobj, &cache->attr);
757 list_for_each_entry(iolink, &dev->io_link_props, list) {
758 iolink->kobj = kzalloc(sizeof(struct kobject), GFP_KERNEL);
761 ret = kobject_init_and_add(iolink->kobj, &iolink_type,
762 dev->kobj_iolink, "%d", i);
764 kobject_put(iolink->kobj);
768 iolink->attr.name = "properties";
769 iolink->attr.mode = KFD_SYSFS_FILE_MODE;
770 sysfs_attr_init(&iolink->attr);
771 ret = sysfs_create_file(iolink->kobj, &iolink->attr);
778 list_for_each_entry(p2plink, &dev->p2p_link_props, list) {
779 p2plink->kobj = kzalloc(sizeof(struct kobject), GFP_KERNEL);
782 ret = kobject_init_and_add(p2plink->kobj, &iolink_type,
783 dev->kobj_p2plink, "%d", i);
785 kobject_put(p2plink->kobj);
789 p2plink->attr.name = "properties";
790 p2plink->attr.mode = KFD_SYSFS_FILE_MODE;
791 sysfs_attr_init(&p2plink->attr);
792 ret = sysfs_create_file(p2plink->kobj, &p2plink->attr);
798 /* All hardware blocks have the same number of attributes. */
799 num_attrs = ARRAY_SIZE(perf_attr_iommu);
800 list_for_each_entry(perf, &dev->perf_props, list) {
801 perf->attr_group = kzalloc(sizeof(struct kfd_perf_attr)
802 * num_attrs + sizeof(struct attribute_group),
804 if (!perf->attr_group)
807 attrs = (struct attribute **)(perf->attr_group + 1);
808 if (!strcmp(perf->block_name, "iommu")) {
809 /* Information of IOMMU's num_counters and counter_ids is shown
810 * under /sys/bus/event_source/devices/amd_iommu. We don't
813 perf_attr_iommu[0].data = perf->max_concurrent;
814 for (i = 0; i < num_attrs; i++)
815 attrs[i] = &perf_attr_iommu[i].attr.attr;
817 perf->attr_group->name = perf->block_name;
818 perf->attr_group->attrs = attrs;
819 ret = sysfs_create_group(dev->kobj_perf, perf->attr_group);
827 /* Called with write topology lock acquired */
828 static int kfd_build_sysfs_node_tree(void)
830 struct kfd_topology_device *dev;
834 list_for_each_entry(dev, &topology_device_list, list) {
835 ret = kfd_build_sysfs_node_entry(dev, i);
844 /* Called with write topology lock acquired */
845 static void kfd_remove_sysfs_node_tree(void)
847 struct kfd_topology_device *dev;
849 list_for_each_entry(dev, &topology_device_list, list)
850 kfd_remove_sysfs_node_entry(dev);
853 static int kfd_topology_update_sysfs(void)
857 if (!sys_props.kobj_topology) {
858 sys_props.kobj_topology =
859 kfd_alloc_struct(sys_props.kobj_topology);
860 if (!sys_props.kobj_topology)
863 ret = kobject_init_and_add(sys_props.kobj_topology,
864 &sysprops_type, &kfd_device->kobj,
867 kobject_put(sys_props.kobj_topology);
871 sys_props.kobj_nodes = kobject_create_and_add("nodes",
872 sys_props.kobj_topology);
873 if (!sys_props.kobj_nodes)
876 sys_props.attr_genid.name = "generation_id";
877 sys_props.attr_genid.mode = KFD_SYSFS_FILE_MODE;
878 sysfs_attr_init(&sys_props.attr_genid);
879 ret = sysfs_create_file(sys_props.kobj_topology,
880 &sys_props.attr_genid);
884 sys_props.attr_props.name = "system_properties";
885 sys_props.attr_props.mode = KFD_SYSFS_FILE_MODE;
886 sysfs_attr_init(&sys_props.attr_props);
887 ret = sysfs_create_file(sys_props.kobj_topology,
888 &sys_props.attr_props);
893 kfd_remove_sysfs_node_tree();
895 return kfd_build_sysfs_node_tree();
898 static void kfd_topology_release_sysfs(void)
900 kfd_remove_sysfs_node_tree();
901 if (sys_props.kobj_topology) {
902 sysfs_remove_file(sys_props.kobj_topology,
903 &sys_props.attr_genid);
904 sysfs_remove_file(sys_props.kobj_topology,
905 &sys_props.attr_props);
906 if (sys_props.kobj_nodes) {
907 kobject_del(sys_props.kobj_nodes);
908 kobject_put(sys_props.kobj_nodes);
909 sys_props.kobj_nodes = NULL;
911 kobject_del(sys_props.kobj_topology);
912 kobject_put(sys_props.kobj_topology);
913 sys_props.kobj_topology = NULL;
917 /* Called with write topology_lock acquired */
918 static void kfd_topology_update_device_list(struct list_head *temp_list,
919 struct list_head *master_list)
921 while (!list_empty(temp_list)) {
922 list_move_tail(temp_list->next, master_list);
923 sys_props.num_devices++;
927 static void kfd_debug_print_topology(void)
929 struct kfd_topology_device *dev;
931 down_read(&topology_lock);
933 dev = list_last_entry(&topology_device_list,
934 struct kfd_topology_device, list);
936 if (dev->node_props.cpu_cores_count &&
937 dev->node_props.simd_count) {
938 pr_info("Topology: Add APU node [0x%0x:0x%0x]\n",
939 dev->node_props.device_id,
940 dev->node_props.vendor_id);
941 } else if (dev->node_props.cpu_cores_count)
942 pr_info("Topology: Add CPU node\n");
943 else if (dev->node_props.simd_count)
944 pr_info("Topology: Add dGPU node [0x%0x:0x%0x]\n",
945 dev->node_props.device_id,
946 dev->node_props.vendor_id);
948 up_read(&topology_lock);
951 /* Helper function for intializing platform_xx members of
952 * kfd_system_properties. Uses OEM info from the last CPU/APU node.
954 static void kfd_update_system_properties(void)
956 struct kfd_topology_device *dev;
958 down_read(&topology_lock);
959 dev = list_last_entry(&topology_device_list,
960 struct kfd_topology_device, list);
962 sys_props.platform_id =
963 (*((uint64_t *)dev->oem_id)) & CRAT_OEMID_64BIT_MASK;
964 sys_props.platform_oem = *((uint64_t *)dev->oem_table_id);
965 sys_props.platform_rev = dev->oem_revision;
967 up_read(&topology_lock);
970 static void find_system_memory(const struct dmi_header *dm,
973 struct kfd_mem_properties *mem;
974 u16 mem_width, mem_clock;
975 struct kfd_topology_device *kdev =
976 (struct kfd_topology_device *)private;
977 const u8 *dmi_data = (const u8 *)(dm + 1);
979 if (dm->type == DMI_ENTRY_MEM_DEVICE && dm->length >= 0x15) {
980 mem_width = (u16)(*(const u16 *)(dmi_data + 0x6));
981 mem_clock = (u16)(*(const u16 *)(dmi_data + 0x11));
982 list_for_each_entry(mem, &kdev->mem_props, list) {
983 if (mem_width != 0xFFFF && mem_width != 0)
984 mem->width = mem_width;
986 mem->mem_clk_max = mem_clock;
991 /* kfd_add_non_crat_information - Add information that is not currently
992 * defined in CRAT but is necessary for KFD topology
993 * @dev - topology device to which addition info is added
995 static void kfd_add_non_crat_information(struct kfd_topology_device *kdev)
997 /* Check if CPU only node. */
999 /* Add system memory information */
1000 dmi_walk(find_system_memory, kdev);
1002 /* TODO: For GPU node, rearrange code from kfd_topology_add_device */
1005 int kfd_topology_init(void)
1007 void *crat_image = NULL;
1008 size_t image_size = 0;
1010 struct list_head temp_topology_device_list;
1011 int cpu_only_node = 0;
1012 struct kfd_topology_device *kdev;
1013 int proximity_domain;
1015 /* topology_device_list - Master list of all topology devices
1016 * temp_topology_device_list - temporary list created while parsing CRAT
1017 * or VCRAT. Once parsing is complete the contents of list is moved to
1018 * topology_device_list
1021 /* Initialize the head for the both the lists */
1022 INIT_LIST_HEAD(&topology_device_list);
1023 INIT_LIST_HEAD(&temp_topology_device_list);
1024 init_rwsem(&topology_lock);
1026 memset(&sys_props, 0, sizeof(sys_props));
1028 /* Proximity domains in ACPI CRAT tables start counting at
1029 * 0. The same should be true for virtual CRAT tables created
1030 * at this stage. GPUs added later in kfd_topology_add_device
1033 proximity_domain = 0;
1035 ret = kfd_create_crat_image_virtual(&crat_image, &image_size,
1036 COMPUTE_UNIT_CPU, NULL,
1040 pr_err("Error creating VCRAT table for CPU\n");
1044 ret = kfd_parse_crat_table(crat_image,
1045 &temp_topology_device_list,
1048 pr_err("Error parsing VCRAT table for CPU\n");
1052 kdev = list_first_entry(&temp_topology_device_list,
1053 struct kfd_topology_device, list);
1055 down_write(&topology_lock);
1056 kfd_topology_update_device_list(&temp_topology_device_list,
1057 &topology_device_list);
1058 topology_crat_proximity_domain = sys_props.num_devices-1;
1059 ret = kfd_topology_update_sysfs();
1060 up_write(&topology_lock);
1063 sys_props.generation_count++;
1064 kfd_update_system_properties();
1065 kfd_debug_print_topology();
1067 pr_err("Failed to update topology in sysfs ret=%d\n", ret);
1069 /* For nodes with GPU, this information gets added
1070 * when GPU is detected (kfd_topology_add_device).
1072 if (cpu_only_node) {
1073 /* Add additional information to CPU only node created above */
1074 down_write(&topology_lock);
1075 kdev = list_first_entry(&topology_device_list,
1076 struct kfd_topology_device, list);
1077 up_write(&topology_lock);
1078 kfd_add_non_crat_information(kdev);
1082 kfd_destroy_crat_image(crat_image);
1086 void kfd_topology_shutdown(void)
1088 down_write(&topology_lock);
1089 kfd_topology_release_sysfs();
1090 kfd_release_live_view();
1091 up_write(&topology_lock);
1094 static uint32_t kfd_generate_gpu_id(struct kfd_node *gpu)
1098 uint64_t local_mem_size;
1104 local_mem_size = gpu->local_mem_info.local_mem_size_private +
1105 gpu->local_mem_info.local_mem_size_public;
1106 buf[0] = gpu->adev->pdev->devfn;
1107 buf[1] = gpu->adev->pdev->subsystem_vendor |
1108 (gpu->adev->pdev->subsystem_device << 16);
1109 buf[2] = pci_domain_nr(gpu->adev->pdev->bus);
1110 buf[3] = gpu->adev->pdev->device;
1111 buf[4] = gpu->adev->pdev->bus->number;
1112 buf[5] = lower_32_bits(local_mem_size);
1113 buf[6] = upper_32_bits(local_mem_size);
1114 buf[7] = (ffs(gpu->xcc_mask) - 1) | (NUM_XCC(gpu->xcc_mask) << 16);
1116 for (i = 0, hashout = 0; i < 8; i++)
1117 hashout ^= hash_32(buf[i], KFD_GPU_ID_HASH_WIDTH);
1121 /* kfd_assign_gpu - Attach @gpu to the correct kfd topology device. If
1122 * the GPU device is not already present in the topology device
1123 * list then return NULL. This means a new topology device has to
1124 * be created for this GPU.
1126 static struct kfd_topology_device *kfd_assign_gpu(struct kfd_node *gpu)
1128 struct kfd_topology_device *dev;
1129 struct kfd_topology_device *out_dev = NULL;
1130 struct kfd_mem_properties *mem;
1131 struct kfd_cache_properties *cache;
1132 struct kfd_iolink_properties *iolink;
1133 struct kfd_iolink_properties *p2plink;
1135 list_for_each_entry(dev, &topology_device_list, list) {
1136 /* Discrete GPUs need their own topology device list
1137 * entries. Don't assign them to CPU/APU nodes.
1139 if (dev->node_props.cpu_cores_count)
1142 if (!dev->gpu && (dev->node_props.simd_count > 0)) {
1146 list_for_each_entry(mem, &dev->mem_props, list)
1147 mem->gpu = dev->gpu;
1148 list_for_each_entry(cache, &dev->cache_props, list)
1149 cache->gpu = dev->gpu;
1150 list_for_each_entry(iolink, &dev->io_link_props, list)
1151 iolink->gpu = dev->gpu;
1152 list_for_each_entry(p2plink, &dev->p2p_link_props, list)
1153 p2plink->gpu = dev->gpu;
1160 static void kfd_notify_gpu_change(uint32_t gpu_id, int arrival)
1163 * TODO: Generate an event for thunk about the arrival/removal
1168 /* kfd_fill_mem_clk_max_info - Since CRAT doesn't have memory clock info,
1169 * patch this after CRAT parsing.
1171 static void kfd_fill_mem_clk_max_info(struct kfd_topology_device *dev)
1173 struct kfd_mem_properties *mem;
1174 struct kfd_local_mem_info local_mem_info;
1179 /* Currently, amdgpu driver (amdgpu_mc) deals only with GPUs with
1180 * single bank of VRAM local memory.
1181 * for dGPUs - VCRAT reports only one bank of Local Memory
1182 * for APUs - If CRAT from ACPI reports more than one bank, then
1183 * all the banks will report the same mem_clk_max information
1185 amdgpu_amdkfd_get_local_mem_info(dev->gpu->adev, &local_mem_info,
1188 list_for_each_entry(mem, &dev->mem_props, list)
1189 mem->mem_clk_max = local_mem_info.mem_clk_max;
1192 static void kfd_set_iolink_no_atomics(struct kfd_topology_device *dev,
1193 struct kfd_topology_device *target_gpu_dev,
1194 struct kfd_iolink_properties *link)
1196 /* xgmi always supports atomics between links. */
1197 if (link->iolink_type == CRAT_IOLINK_TYPE_XGMI)
1200 /* check pcie support to set cpu(dev) flags for target_gpu_dev link. */
1201 if (target_gpu_dev) {
1204 pcie_capability_read_dword(target_gpu_dev->gpu->adev->pdev,
1205 PCI_EXP_DEVCAP2, &cap);
1207 if (!(cap & (PCI_EXP_DEVCAP2_ATOMIC_COMP32 |
1208 PCI_EXP_DEVCAP2_ATOMIC_COMP64)))
1209 link->flags |= CRAT_IOLINK_FLAGS_NO_ATOMICS_32_BIT |
1210 CRAT_IOLINK_FLAGS_NO_ATOMICS_64_BIT;
1211 /* set gpu (dev) flags. */
1213 if (!dev->gpu->kfd->pci_atomic_requested ||
1214 dev->gpu->adev->asic_type == CHIP_HAWAII)
1215 link->flags |= CRAT_IOLINK_FLAGS_NO_ATOMICS_32_BIT |
1216 CRAT_IOLINK_FLAGS_NO_ATOMICS_64_BIT;
1220 static void kfd_set_iolink_non_coherent(struct kfd_topology_device *to_dev,
1221 struct kfd_iolink_properties *outbound_link,
1222 struct kfd_iolink_properties *inbound_link)
1224 /* CPU -> GPU with PCIe */
1226 inbound_link->iolink_type == CRAT_IOLINK_TYPE_PCIEXPRESS)
1227 inbound_link->flags |= CRAT_IOLINK_FLAGS_NON_COHERENT;
1230 /* GPU <-> GPU with PCIe and
1233 if (inbound_link->iolink_type == CRAT_IOLINK_TYPE_PCIEXPRESS ||
1234 (inbound_link->iolink_type == CRAT_IOLINK_TYPE_XGMI &&
1235 KFD_GC_VERSION(to_dev->gpu) == IP_VERSION(9, 4, 0))) {
1236 outbound_link->flags |= CRAT_IOLINK_FLAGS_NON_COHERENT;
1237 inbound_link->flags |= CRAT_IOLINK_FLAGS_NON_COHERENT;
1242 static void kfd_fill_iolink_non_crat_info(struct kfd_topology_device *dev)
1244 struct kfd_iolink_properties *link, *inbound_link;
1245 struct kfd_topology_device *peer_dev;
1247 if (!dev || !dev->gpu)
1250 /* GPU only creates direct links so apply flags setting to all */
1251 list_for_each_entry(link, &dev->io_link_props, list) {
1252 link->flags = CRAT_IOLINK_FLAGS_ENABLED;
1253 kfd_set_iolink_no_atomics(dev, NULL, link);
1254 peer_dev = kfd_topology_device_by_proximity_domain(
1260 /* Include the CPU peer in GPU hive if connected over xGMI. */
1261 if (!peer_dev->gpu &&
1262 link->iolink_type == CRAT_IOLINK_TYPE_XGMI) {
1264 * If the GPU is not part of a GPU hive, use its pci
1265 * device location as the hive ID to bind with the CPU.
1267 if (!dev->node_props.hive_id)
1268 dev->node_props.hive_id = pci_dev_id(dev->gpu->adev->pdev);
1269 peer_dev->node_props.hive_id = dev->node_props.hive_id;
1272 list_for_each_entry(inbound_link, &peer_dev->io_link_props,
1274 if (inbound_link->node_to != link->node_from)
1277 inbound_link->flags = CRAT_IOLINK_FLAGS_ENABLED;
1278 kfd_set_iolink_no_atomics(peer_dev, dev, inbound_link);
1279 kfd_set_iolink_non_coherent(peer_dev, link, inbound_link);
1283 /* Create indirect links so apply flags setting to all */
1284 list_for_each_entry(link, &dev->p2p_link_props, list) {
1285 link->flags = CRAT_IOLINK_FLAGS_ENABLED;
1286 kfd_set_iolink_no_atomics(dev, NULL, link);
1287 peer_dev = kfd_topology_device_by_proximity_domain(
1293 list_for_each_entry(inbound_link, &peer_dev->p2p_link_props,
1295 if (inbound_link->node_to != link->node_from)
1298 inbound_link->flags = CRAT_IOLINK_FLAGS_ENABLED;
1299 kfd_set_iolink_no_atomics(peer_dev, dev, inbound_link);
1300 kfd_set_iolink_non_coherent(peer_dev, link, inbound_link);
1305 static int kfd_build_p2p_node_entry(struct kfd_topology_device *dev,
1306 struct kfd_iolink_properties *p2plink)
1310 p2plink->kobj = kzalloc(sizeof(struct kobject), GFP_KERNEL);
1314 ret = kobject_init_and_add(p2plink->kobj, &iolink_type,
1315 dev->kobj_p2plink, "%d", dev->node_props.p2p_links_count - 1);
1317 kobject_put(p2plink->kobj);
1321 p2plink->attr.name = "properties";
1322 p2plink->attr.mode = KFD_SYSFS_FILE_MODE;
1323 sysfs_attr_init(&p2plink->attr);
1324 ret = sysfs_create_file(p2plink->kobj, &p2plink->attr);
1331 static int kfd_create_indirect_link_prop(struct kfd_topology_device *kdev, int gpu_node)
1333 struct kfd_iolink_properties *gpu_link, *tmp_link, *cpu_link;
1334 struct kfd_iolink_properties *props = NULL, *props2 = NULL;
1335 struct kfd_topology_device *cpu_dev;
1340 list_for_each_entry(cpu_dev, &topology_device_list, list) {
1346 gpu_link = list_first_entry(&kdev->io_link_props,
1347 struct kfd_iolink_properties, list);
1351 for (i = 0; i < num_cpu; i++) {
1353 if (gpu_link->node_to == i)
1356 /* find CPU <--> CPU links */
1358 cpu_dev = kfd_topology_device_by_proximity_domain(i);
1360 list_for_each_entry(tmp_link,
1361 &cpu_dev->io_link_props, list) {
1362 if (tmp_link->node_to == gpu_link->node_to) {
1363 cpu_link = tmp_link;
1372 /* CPU <--> CPU <--> GPU, GPU node*/
1373 props = kfd_alloc_struct(props);
1377 memcpy(props, gpu_link, sizeof(struct kfd_iolink_properties));
1378 props->weight = gpu_link->weight + cpu_link->weight;
1379 props->min_latency = gpu_link->min_latency + cpu_link->min_latency;
1380 props->max_latency = gpu_link->max_latency + cpu_link->max_latency;
1381 props->min_bandwidth = min(gpu_link->min_bandwidth, cpu_link->min_bandwidth);
1382 props->max_bandwidth = min(gpu_link->max_bandwidth, cpu_link->max_bandwidth);
1384 props->node_from = gpu_node;
1386 kdev->node_props.p2p_links_count++;
1387 list_add_tail(&props->list, &kdev->p2p_link_props);
1388 ret = kfd_build_p2p_node_entry(kdev, props);
1392 /* for small Bar, no CPU --> GPU in-direct links */
1393 if (kfd_dev_is_large_bar(kdev->gpu)) {
1394 /* CPU <--> CPU <--> GPU, CPU node*/
1395 props2 = kfd_alloc_struct(props2);
1399 memcpy(props2, props, sizeof(struct kfd_iolink_properties));
1400 props2->node_from = i;
1401 props2->node_to = gpu_node;
1402 props2->kobj = NULL;
1403 cpu_dev->node_props.p2p_links_count++;
1404 list_add_tail(&props2->list, &cpu_dev->p2p_link_props);
1405 ret = kfd_build_p2p_node_entry(cpu_dev, props2);
1413 #if defined(CONFIG_HSA_AMD_P2P)
1414 static int kfd_add_peer_prop(struct kfd_topology_device *kdev,
1415 struct kfd_topology_device *peer, int from, int to)
1417 struct kfd_iolink_properties *props = NULL;
1418 struct kfd_iolink_properties *iolink1, *iolink2, *iolink3;
1419 struct kfd_topology_device *cpu_dev;
1422 if (!amdgpu_device_is_peer_accessible(
1427 iolink1 = list_first_entry(&kdev->io_link_props,
1428 struct kfd_iolink_properties, list);
1432 iolink2 = list_first_entry(&peer->io_link_props,
1433 struct kfd_iolink_properties, list);
1437 props = kfd_alloc_struct(props);
1441 memcpy(props, iolink1, sizeof(struct kfd_iolink_properties));
1443 props->weight = iolink1->weight + iolink2->weight;
1444 props->min_latency = iolink1->min_latency + iolink2->min_latency;
1445 props->max_latency = iolink1->max_latency + iolink2->max_latency;
1446 props->min_bandwidth = min(iolink1->min_bandwidth, iolink2->min_bandwidth);
1447 props->max_bandwidth = min(iolink2->max_bandwidth, iolink2->max_bandwidth);
1449 if (iolink1->node_to != iolink2->node_to) {
1451 cpu_dev = kfd_topology_device_by_proximity_domain(iolink1->node_to);
1453 list_for_each_entry(iolink3, &cpu_dev->io_link_props, list)
1454 if (iolink3->node_to == iolink2->node_to)
1457 props->weight += iolink3->weight;
1458 props->min_latency += iolink3->min_latency;
1459 props->max_latency += iolink3->max_latency;
1460 props->min_bandwidth = min(props->min_bandwidth,
1461 iolink3->min_bandwidth);
1462 props->max_bandwidth = min(props->max_bandwidth,
1463 iolink3->max_bandwidth);
1465 WARN(1, "CPU node not found");
1469 props->node_from = from;
1470 props->node_to = to;
1471 peer->node_props.p2p_links_count++;
1472 list_add_tail(&props->list, &peer->p2p_link_props);
1473 ret = kfd_build_p2p_node_entry(peer, props);
1479 static int kfd_dev_create_p2p_links(void)
1481 struct kfd_topology_device *dev;
1482 struct kfd_topology_device *new_dev;
1483 #if defined(CONFIG_HSA_AMD_P2P)
1490 list_for_each_entry(dev, &topology_device_list, list)
1495 new_dev = list_last_entry(&topology_device_list, struct kfd_topology_device, list);
1496 if (WARN_ON(!new_dev->gpu))
1501 /* create in-direct links */
1502 ret = kfd_create_indirect_link_prop(new_dev, k);
1506 /* create p2p links */
1507 #if defined(CONFIG_HSA_AMD_P2P)
1509 list_for_each_entry(dev, &topology_device_list, list) {
1512 if (!dev->gpu || !dev->gpu->adev ||
1513 (dev->gpu->kfd->hive_id &&
1514 dev->gpu->kfd->hive_id == new_dev->gpu->kfd->hive_id))
1517 /* check if node(s) is/are peer accessible in one direction or bi-direction */
1518 ret = kfd_add_peer_prop(new_dev, dev, i, k);
1522 ret = kfd_add_peer_prop(dev, new_dev, k, i);
1534 /* Helper function. See kfd_fill_gpu_cache_info for parameter description */
1535 static int fill_in_l1_pcache(struct kfd_cache_properties **props_ext,
1536 struct kfd_gpu_cache_info *pcache_info,
1537 struct kfd_cu_info *cu_info,
1539 int cache_type, unsigned int cu_processor_id,
1542 unsigned int cu_sibling_map_mask;
1543 int first_active_cu;
1544 struct kfd_cache_properties *pcache = NULL;
1546 cu_sibling_map_mask = cu_bitmask;
1547 cu_sibling_map_mask >>= cu_block;
1548 cu_sibling_map_mask &= ((1 << pcache_info[cache_type].num_cu_shared) - 1);
1549 first_active_cu = ffs(cu_sibling_map_mask);
1551 /* CU could be inactive. In case of shared cache find the first active
1552 * CU. and incase of non-shared cache check if the CU is inactive. If
1553 * inactive active skip it
1555 if (first_active_cu) {
1556 pcache = kfd_alloc_struct(pcache);
1560 memset(pcache, 0, sizeof(struct kfd_cache_properties));
1561 pcache->processor_id_low = cu_processor_id + (first_active_cu - 1);
1562 pcache->cache_level = pcache_info[cache_type].cache_level;
1563 pcache->cache_size = pcache_info[cache_type].cache_size;
1565 if (pcache_info[cache_type].flags & CRAT_CACHE_FLAGS_DATA_CACHE)
1566 pcache->cache_type |= HSA_CACHE_TYPE_DATA;
1567 if (pcache_info[cache_type].flags & CRAT_CACHE_FLAGS_INST_CACHE)
1568 pcache->cache_type |= HSA_CACHE_TYPE_INSTRUCTION;
1569 if (pcache_info[cache_type].flags & CRAT_CACHE_FLAGS_CPU_CACHE)
1570 pcache->cache_type |= HSA_CACHE_TYPE_CPU;
1571 if (pcache_info[cache_type].flags & CRAT_CACHE_FLAGS_SIMD_CACHE)
1572 pcache->cache_type |= HSA_CACHE_TYPE_HSACU;
1574 /* Sibling map is w.r.t processor_id_low, so shift out
1577 cu_sibling_map_mask =
1578 cu_sibling_map_mask >> (first_active_cu - 1);
1580 pcache->sibling_map[0] = (uint8_t)(cu_sibling_map_mask & 0xFF);
1581 pcache->sibling_map[1] =
1582 (uint8_t)((cu_sibling_map_mask >> 8) & 0xFF);
1583 pcache->sibling_map[2] =
1584 (uint8_t)((cu_sibling_map_mask >> 16) & 0xFF);
1585 pcache->sibling_map[3] =
1586 (uint8_t)((cu_sibling_map_mask >> 24) & 0xFF);
1588 pcache->sibling_map_size = 4;
1589 *props_ext = pcache;
1596 /* Helper function. See kfd_fill_gpu_cache_info for parameter description */
1597 static int fill_in_l2_l3_pcache(struct kfd_cache_properties **props_ext,
1598 struct kfd_gpu_cache_info *pcache_info,
1599 struct kfd_cu_info *cu_info,
1600 int cache_type, unsigned int cu_processor_id)
1602 unsigned int cu_sibling_map_mask;
1603 int first_active_cu;
1605 struct kfd_cache_properties *pcache = NULL;
1607 cu_sibling_map_mask = cu_info->cu_bitmap[0][0];
1608 cu_sibling_map_mask &=
1609 ((1 << pcache_info[cache_type].num_cu_shared) - 1);
1610 first_active_cu = ffs(cu_sibling_map_mask);
1612 /* CU could be inactive. In case of shared cache find the first active
1613 * CU. and incase of non-shared cache check if the CU is inactive. If
1614 * inactive active skip it
1616 if (first_active_cu) {
1617 pcache = kfd_alloc_struct(pcache);
1621 memset(pcache, 0, sizeof(struct kfd_cache_properties));
1622 pcache->processor_id_low = cu_processor_id
1623 + (first_active_cu - 1);
1624 pcache->cache_level = pcache_info[cache_type].cache_level;
1625 pcache->cache_size = pcache_info[cache_type].cache_size;
1627 if (pcache_info[cache_type].flags & CRAT_CACHE_FLAGS_DATA_CACHE)
1628 pcache->cache_type |= HSA_CACHE_TYPE_DATA;
1629 if (pcache_info[cache_type].flags & CRAT_CACHE_FLAGS_INST_CACHE)
1630 pcache->cache_type |= HSA_CACHE_TYPE_INSTRUCTION;
1631 if (pcache_info[cache_type].flags & CRAT_CACHE_FLAGS_CPU_CACHE)
1632 pcache->cache_type |= HSA_CACHE_TYPE_CPU;
1633 if (pcache_info[cache_type].flags & CRAT_CACHE_FLAGS_SIMD_CACHE)
1634 pcache->cache_type |= HSA_CACHE_TYPE_HSACU;
1636 /* Sibling map is w.r.t processor_id_low, so shift out
1639 cu_sibling_map_mask = cu_sibling_map_mask >> (first_active_cu - 1);
1642 for (i = 0; i < cu_info->num_shader_engines; i++) {
1643 for (j = 0; j < cu_info->num_shader_arrays_per_engine; j++) {
1644 pcache->sibling_map[k] = (uint8_t)(cu_sibling_map_mask & 0xFF);
1645 pcache->sibling_map[k+1] = (uint8_t)((cu_sibling_map_mask >> 8) & 0xFF);
1646 pcache->sibling_map[k+2] = (uint8_t)((cu_sibling_map_mask >> 16) & 0xFF);
1647 pcache->sibling_map[k+3] = (uint8_t)((cu_sibling_map_mask >> 24) & 0xFF);
1650 cu_sibling_map_mask = cu_info->cu_bitmap[i % 4][j + i / 4];
1651 cu_sibling_map_mask &= ((1 << pcache_info[cache_type].num_cu_shared) - 1);
1654 pcache->sibling_map_size = k;
1655 *props_ext = pcache;
1661 #define KFD_MAX_CACHE_TYPES 6
1663 /* kfd_fill_cache_non_crat_info - Fill GPU cache info using kfd_gpu_cache_info
1666 static void kfd_fill_cache_non_crat_info(struct kfd_topology_device *dev, struct kfd_node *kdev)
1668 struct kfd_gpu_cache_info *pcache_info = NULL;
1671 unsigned int cu_processor_id;
1673 unsigned int num_cu_shared;
1674 struct kfd_cu_info cu_info;
1675 struct kfd_cu_info *pcu_info;
1676 int gpu_processor_id;
1677 struct kfd_cache_properties *props_ext;
1678 int num_of_entries = 0;
1679 int num_of_cache_types = 0;
1680 struct kfd_gpu_cache_info cache_info[KFD_MAX_CACHE_TYPES];
1682 amdgpu_amdkfd_get_cu_info(kdev->adev, &cu_info);
1683 pcu_info = &cu_info;
1685 gpu_processor_id = dev->node_props.simd_id_base;
1687 pcache_info = cache_info;
1688 num_of_cache_types = kfd_get_gpu_cache_info(kdev, &pcache_info);
1689 if (!num_of_cache_types) {
1690 pr_warn("no cache info found\n");
1694 /* For each type of cache listed in the kfd_gpu_cache_info table,
1695 * go through all available Compute Units.
1696 * The [i,j,k] loop will
1697 * if kfd_gpu_cache_info.num_cu_shared = 1
1698 * will parse through all available CU
1699 * If (kfd_gpu_cache_info.num_cu_shared != 1)
1700 * then it will consider only one CU from
1703 for (ct = 0; ct < num_of_cache_types; ct++) {
1704 cu_processor_id = gpu_processor_id;
1705 if (pcache_info[ct].cache_level == 1) {
1706 for (i = 0; i < pcu_info->num_shader_engines; i++) {
1707 for (j = 0; j < pcu_info->num_shader_arrays_per_engine; j++) {
1708 for (k = 0; k < pcu_info->num_cu_per_sh; k += pcache_info[ct].num_cu_shared) {
1710 ret = fill_in_l1_pcache(&props_ext, pcache_info, pcu_info,
1711 pcu_info->cu_bitmap[i % 4][j + i / 4], ct,
1712 cu_processor_id, k);
1719 list_add_tail(&props_ext->list, &dev->cache_props);
1722 /* Move to next CU block */
1723 num_cu_shared = ((k + pcache_info[ct].num_cu_shared) <=
1724 pcu_info->num_cu_per_sh) ?
1725 pcache_info[ct].num_cu_shared :
1726 (pcu_info->num_cu_per_sh - k);
1727 cu_processor_id += num_cu_shared;
1732 ret = fill_in_l2_l3_pcache(&props_ext, pcache_info,
1733 pcu_info, ct, cu_processor_id);
1740 list_add_tail(&props_ext->list, &dev->cache_props);
1744 dev->node_props.caches_count += num_of_entries;
1745 pr_debug("Added [%d] GPU cache entries\n", num_of_entries);
1748 static int kfd_topology_add_device_locked(struct kfd_node *gpu, uint32_t gpu_id,
1749 struct kfd_topology_device **dev)
1751 int proximity_domain = ++topology_crat_proximity_domain;
1752 struct list_head temp_topology_device_list;
1753 void *crat_image = NULL;
1754 size_t image_size = 0;
1757 res = kfd_create_crat_image_virtual(&crat_image, &image_size,
1758 COMPUTE_UNIT_GPU, gpu,
1761 pr_err("Error creating VCRAT for GPU (ID: 0x%x)\n",
1763 topology_crat_proximity_domain--;
1767 INIT_LIST_HEAD(&temp_topology_device_list);
1769 res = kfd_parse_crat_table(crat_image,
1770 &temp_topology_device_list,
1773 pr_err("Error parsing VCRAT for GPU (ID: 0x%x)\n",
1775 topology_crat_proximity_domain--;
1779 kfd_topology_update_device_list(&temp_topology_device_list,
1780 &topology_device_list);
1782 *dev = kfd_assign_gpu(gpu);
1783 if (WARN_ON(!*dev)) {
1788 /* Fill the cache affinity information here for the GPUs
1791 kfd_fill_cache_non_crat_info(*dev, gpu);
1793 /* Update the SYSFS tree, since we added another topology
1796 res = kfd_topology_update_sysfs();
1798 sys_props.generation_count++;
1800 pr_err("Failed to update GPU (ID: 0x%x) to sysfs topology. res=%d\n",
1804 kfd_destroy_crat_image(crat_image);
1808 static void kfd_topology_set_dbg_firmware_support(struct kfd_topology_device *dev)
1810 bool firmware_supported = true;
1812 if (KFD_GC_VERSION(dev->gpu) >= IP_VERSION(11, 0, 0) &&
1813 KFD_GC_VERSION(dev->gpu) < IP_VERSION(12, 0, 0)) {
1814 uint32_t mes_api_rev = (dev->gpu->adev->mes.sched_version &
1815 AMDGPU_MES_API_VERSION_MASK) >>
1816 AMDGPU_MES_API_VERSION_SHIFT;
1817 uint32_t mes_rev = dev->gpu->adev->mes.sched_version &
1818 AMDGPU_MES_VERSION_MASK;
1820 firmware_supported = (mes_api_rev >= 14) && (mes_rev >= 64);
1825 * Note: Any unlisted devices here are assumed to support exception handling.
1826 * Add additional checks here as needed.
1828 switch (KFD_GC_VERSION(dev->gpu)) {
1829 case IP_VERSION(9, 0, 1):
1830 firmware_supported = dev->gpu->kfd->mec_fw_version >= 459 + 32768;
1832 case IP_VERSION(9, 1, 0):
1833 case IP_VERSION(9, 2, 1):
1834 case IP_VERSION(9, 2, 2):
1835 case IP_VERSION(9, 3, 0):
1836 case IP_VERSION(9, 4, 0):
1837 firmware_supported = dev->gpu->kfd->mec_fw_version >= 459;
1839 case IP_VERSION(9, 4, 1):
1840 firmware_supported = dev->gpu->kfd->mec_fw_version >= 60;
1842 case IP_VERSION(9, 4, 2):
1843 firmware_supported = dev->gpu->kfd->mec_fw_version >= 51;
1845 case IP_VERSION(10, 1, 10):
1846 case IP_VERSION(10, 1, 2):
1847 case IP_VERSION(10, 1, 1):
1848 firmware_supported = dev->gpu->kfd->mec_fw_version >= 144;
1850 case IP_VERSION(10, 3, 0):
1851 case IP_VERSION(10, 3, 2):
1852 case IP_VERSION(10, 3, 1):
1853 case IP_VERSION(10, 3, 4):
1854 case IP_VERSION(10, 3, 5):
1855 firmware_supported = dev->gpu->kfd->mec_fw_version >= 89;
1857 case IP_VERSION(10, 1, 3):
1858 case IP_VERSION(10, 3, 3):
1859 firmware_supported = false;
1866 if (firmware_supported)
1867 dev->node_props.capability |= HSA_CAP_TRAP_DEBUG_FIRMWARE_SUPPORTED;
1870 static void kfd_topology_set_capabilities(struct kfd_topology_device *dev)
1872 dev->node_props.capability |= ((HSA_CAP_DOORBELL_TYPE_2_0 <<
1873 HSA_CAP_DOORBELL_TYPE_TOTALBITS_SHIFT) &
1874 HSA_CAP_DOORBELL_TYPE_TOTALBITS_MASK);
1876 dev->node_props.capability |= HSA_CAP_TRAP_DEBUG_SUPPORT |
1877 HSA_CAP_TRAP_DEBUG_WAVE_LAUNCH_TRAP_OVERRIDE_SUPPORTED |
1878 HSA_CAP_TRAP_DEBUG_WAVE_LAUNCH_MODE_SUPPORTED;
1880 if (kfd_dbg_has_ttmps_always_setup(dev->gpu))
1881 dev->node_props.debug_prop |= HSA_DBG_DISPATCH_INFO_ALWAYS_VALID;
1883 if (KFD_GC_VERSION(dev->gpu) < IP_VERSION(10, 0, 0)) {
1884 if (KFD_GC_VERSION(dev->gpu) == IP_VERSION(9, 4, 3))
1885 dev->node_props.debug_prop |=
1886 HSA_DBG_WATCH_ADDR_MASK_LO_BIT_GFX9_4_3 |
1887 HSA_DBG_WATCH_ADDR_MASK_HI_BIT_GFX9_4_3;
1889 dev->node_props.debug_prop |=
1890 HSA_DBG_WATCH_ADDR_MASK_LO_BIT_GFX9 |
1891 HSA_DBG_WATCH_ADDR_MASK_HI_BIT;
1893 if (KFD_GC_VERSION(dev->gpu) >= IP_VERSION(9, 4, 2))
1894 dev->node_props.capability |=
1895 HSA_CAP_TRAP_DEBUG_PRECISE_MEMORY_OPERATIONS_SUPPORTED;
1897 dev->node_props.debug_prop |= HSA_DBG_WATCH_ADDR_MASK_LO_BIT_GFX10 |
1898 HSA_DBG_WATCH_ADDR_MASK_HI_BIT;
1900 if (KFD_GC_VERSION(dev->gpu) >= IP_VERSION(11, 0, 0))
1901 dev->node_props.capability |=
1902 HSA_CAP_TRAP_DEBUG_PRECISE_MEMORY_OPERATIONS_SUPPORTED;
1905 kfd_topology_set_dbg_firmware_support(dev);
1908 int kfd_topology_add_device(struct kfd_node *gpu)
1911 struct kfd_topology_device *dev;
1912 struct kfd_cu_info cu_info;
1915 const char *asic_name = amdgpu_asic_name[gpu->adev->asic_type];
1917 gpu_id = kfd_generate_gpu_id(gpu);
1918 if (gpu->xcp && !gpu->xcp->ddev) {
1919 dev_warn(gpu->adev->dev,
1920 "Won't add GPU (ID: 0x%x) to topology since it has no drm node assigned.",
1924 pr_debug("Adding new GPU (ID: 0x%x) to topology\n", gpu_id);
1927 /* Check to see if this gpu device exists in the topology_device_list.
1928 * If so, assign the gpu to that device,
1929 * else create a Virtual CRAT for this gpu device and then parse that
1930 * CRAT to create a new topology device. Once created assign the gpu to
1931 * that topology device
1933 down_write(&topology_lock);
1934 dev = kfd_assign_gpu(gpu);
1936 res = kfd_topology_add_device_locked(gpu, gpu_id, &dev);
1937 up_write(&topology_lock);
1941 dev->gpu_id = gpu_id;
1944 kfd_dev_create_p2p_links();
1946 /* TODO: Move the following lines to function
1947 * kfd_add_non_crat_information
1950 /* Fill-in additional information that is not available in CRAT but
1951 * needed for the topology
1954 amdgpu_amdkfd_get_cu_info(dev->gpu->adev, &cu_info);
1956 for (i = 0; i < KFD_TOPOLOGY_PUBLIC_NAME_SIZE-1; i++) {
1957 dev->node_props.name[i] = __tolower(asic_name[i]);
1958 if (asic_name[i] == '\0')
1961 dev->node_props.name[i] = '\0';
1963 dev->node_props.simd_arrays_per_engine =
1964 cu_info.num_shader_arrays_per_engine;
1966 dev->node_props.gfx_target_version =
1967 gpu->kfd->device_info.gfx_target_version;
1968 dev->node_props.vendor_id = gpu->adev->pdev->vendor;
1969 dev->node_props.device_id = gpu->adev->pdev->device;
1970 dev->node_props.capability |=
1971 ((dev->gpu->adev->rev_id << HSA_CAP_ASIC_REVISION_SHIFT) &
1972 HSA_CAP_ASIC_REVISION_MASK);
1974 dev->node_props.location_id = pci_dev_id(gpu->adev->pdev);
1975 if (KFD_GC_VERSION(dev->gpu->kfd) == IP_VERSION(9, 4, 3))
1976 dev->node_props.location_id |= dev->gpu->node_id;
1978 dev->node_props.domain = pci_domain_nr(gpu->adev->pdev->bus);
1979 dev->node_props.max_engine_clk_fcompute =
1980 amdgpu_amdkfd_get_max_engine_clock_in_mhz(dev->gpu->adev);
1981 dev->node_props.max_engine_clk_ccompute =
1982 cpufreq_quick_get_max(0) / 1000;
1985 dev->node_props.drm_render_minor = gpu->xcp->ddev->render->index;
1987 dev->node_props.drm_render_minor =
1988 gpu->kfd->shared_resources.drm_render_minor;
1990 dev->node_props.hive_id = gpu->kfd->hive_id;
1991 dev->node_props.num_sdma_engines = kfd_get_num_sdma_engines(gpu);
1992 dev->node_props.num_sdma_xgmi_engines =
1993 kfd_get_num_xgmi_sdma_engines(gpu);
1994 dev->node_props.num_sdma_queues_per_engine =
1995 gpu->kfd->device_info.num_sdma_queues_per_engine -
1996 gpu->kfd->device_info.num_reserved_sdma_queues_per_engine;
1997 dev->node_props.num_gws = (dev->gpu->gws &&
1998 dev->gpu->dqm->sched_policy != KFD_SCHED_POLICY_NO_HWS) ?
1999 dev->gpu->adev->gds.gws_size : 0;
2000 dev->node_props.num_cp_queues = get_cp_queues_num(dev->gpu->dqm);
2002 kfd_fill_mem_clk_max_info(dev);
2003 kfd_fill_iolink_non_crat_info(dev);
2005 switch (dev->gpu->adev->asic_type) {
2009 dev->node_props.capability |= ((HSA_CAP_DOORBELL_TYPE_PRE_1_0 <<
2010 HSA_CAP_DOORBELL_TYPE_TOTALBITS_SHIFT) &
2011 HSA_CAP_DOORBELL_TYPE_TOTALBITS_MASK);
2015 case CHIP_POLARIS10:
2016 case CHIP_POLARIS11:
2017 case CHIP_POLARIS12:
2019 pr_debug("Adding doorbell packet type capability\n");
2020 dev->node_props.capability |= ((HSA_CAP_DOORBELL_TYPE_1_0 <<
2021 HSA_CAP_DOORBELL_TYPE_TOTALBITS_SHIFT) &
2022 HSA_CAP_DOORBELL_TYPE_TOTALBITS_MASK);
2025 if (KFD_GC_VERSION(dev->gpu) < IP_VERSION(9, 0, 1))
2026 WARN(1, "Unexpected ASIC family %u",
2027 dev->gpu->adev->asic_type);
2029 kfd_topology_set_capabilities(dev);
2033 * Overwrite ATS capability according to needs_iommu_device to fix
2034 * potential missing corresponding bit in CRAT of BIOS.
2036 dev->node_props.capability &= ~HSA_CAP_ATS_PRESENT;
2038 /* Fix errors in CZ CRAT.
2039 * simd_count: Carrizo CRAT reports wrong simd_count, probably
2040 * because it doesn't consider masked out CUs
2041 * max_waves_per_simd: Carrizo reports wrong max_waves_per_simd
2043 if (dev->gpu->adev->asic_type == CHIP_CARRIZO) {
2044 dev->node_props.simd_count =
2045 cu_info.simd_per_cu * cu_info.cu_active_number;
2046 dev->node_props.max_waves_per_simd = 10;
2049 /* kfd only concerns sram ecc on GFX and HBM ecc on UMC */
2050 dev->node_props.capability |=
2051 ((dev->gpu->adev->ras_enabled & BIT(AMDGPU_RAS_BLOCK__GFX)) != 0) ?
2052 HSA_CAP_SRAM_EDCSUPPORTED : 0;
2053 dev->node_props.capability |=
2054 ((dev->gpu->adev->ras_enabled & BIT(AMDGPU_RAS_BLOCK__UMC)) != 0) ?
2055 HSA_CAP_MEM_EDCSUPPORTED : 0;
2057 if (KFD_GC_VERSION(dev->gpu) != IP_VERSION(9, 0, 1))
2058 dev->node_props.capability |= (dev->gpu->adev->ras_enabled != 0) ?
2059 HSA_CAP_RASEVENTNOTIFY : 0;
2061 if (KFD_IS_SVM_API_SUPPORTED(dev->gpu->adev))
2062 dev->node_props.capability |= HSA_CAP_SVMAPI_SUPPORTED;
2064 if (dev->gpu->adev->gmc.is_app_apu ||
2065 dev->gpu->adev->gmc.xgmi.connected_to_cpu)
2066 dev->node_props.capability |= HSA_CAP_FLAGS_COHERENTHOSTACCESS;
2068 kfd_debug_print_topology();
2070 kfd_notify_gpu_change(gpu_id, 1);
2076 * kfd_topology_update_io_links() - Update IO links after device removal.
2077 * @proximity_domain: Proximity domain value of the dev being removed.
2079 * The topology list currently is arranged in increasing order of
2082 * Two things need to be done when a device is removed:
2083 * 1. All the IO links to this device need to be removed.
2084 * 2. All nodes after the current device node need to move
2085 * up once this device node is removed from the topology
2086 * list. As a result, the proximity domain values for
2087 * all nodes after the node being deleted reduce by 1.
2088 * This would also cause the proximity domain values for
2089 * io links to be updated based on new proximity domain
2092 * Context: The caller must hold write topology_lock.
2094 static void kfd_topology_update_io_links(int proximity_domain)
2096 struct kfd_topology_device *dev;
2097 struct kfd_iolink_properties *iolink, *p2plink, *tmp;
2099 list_for_each_entry(dev, &topology_device_list, list) {
2100 if (dev->proximity_domain > proximity_domain)
2101 dev->proximity_domain--;
2103 list_for_each_entry_safe(iolink, tmp, &dev->io_link_props, list) {
2105 * If there is an io link to the dev being deleted
2106 * then remove that IO link also.
2108 if (iolink->node_to == proximity_domain) {
2109 list_del(&iolink->list);
2110 dev->node_props.io_links_count--;
2112 if (iolink->node_from > proximity_domain)
2113 iolink->node_from--;
2114 if (iolink->node_to > proximity_domain)
2119 list_for_each_entry_safe(p2plink, tmp, &dev->p2p_link_props, list) {
2121 * If there is a p2p link to the dev being deleted
2122 * then remove that p2p link also.
2124 if (p2plink->node_to == proximity_domain) {
2125 list_del(&p2plink->list);
2126 dev->node_props.p2p_links_count--;
2128 if (p2plink->node_from > proximity_domain)
2129 p2plink->node_from--;
2130 if (p2plink->node_to > proximity_domain)
2137 int kfd_topology_remove_device(struct kfd_node *gpu)
2139 struct kfd_topology_device *dev, *tmp;
2144 down_write(&topology_lock);
2146 list_for_each_entry_safe(dev, tmp, &topology_device_list, list) {
2147 if (dev->gpu == gpu) {
2148 gpu_id = dev->gpu_id;
2149 kfd_remove_sysfs_node_entry(dev);
2150 kfd_release_topology_device(dev);
2151 sys_props.num_devices--;
2152 kfd_topology_update_io_links(i);
2153 topology_crat_proximity_domain = sys_props.num_devices-1;
2154 sys_props.generation_count++;
2156 if (kfd_topology_update_sysfs() < 0)
2157 kfd_topology_release_sysfs();
2163 up_write(&topology_lock);
2166 kfd_notify_gpu_change(gpu_id, 0);
2171 /* kfd_topology_enum_kfd_devices - Enumerate through all devices in KFD
2172 * topology. If GPU device is found @idx, then valid kfd_dev pointer is
2173 * returned through @kdev
2174 * Return - 0: On success (@kdev will be NULL for non GPU nodes)
2175 * -1: If end of list
2177 int kfd_topology_enum_kfd_devices(uint8_t idx, struct kfd_node **kdev)
2180 struct kfd_topology_device *top_dev;
2181 uint8_t device_idx = 0;
2184 down_read(&topology_lock);
2186 list_for_each_entry(top_dev, &topology_device_list, list) {
2187 if (device_idx == idx) {
2188 *kdev = top_dev->gpu;
2189 up_read(&topology_lock);
2196 up_read(&topology_lock);
2202 static int kfd_cpumask_to_apic_id(const struct cpumask *cpumask)
2204 int first_cpu_of_numa_node;
2206 if (!cpumask || cpumask == cpu_none_mask)
2208 first_cpu_of_numa_node = cpumask_first(cpumask);
2209 if (first_cpu_of_numa_node >= nr_cpu_ids)
2211 #ifdef CONFIG_X86_64
2212 return cpu_data(first_cpu_of_numa_node).apicid;
2214 return first_cpu_of_numa_node;
2218 /* kfd_numa_node_to_apic_id - Returns the APIC ID of the first logical processor
2219 * of the given NUMA node (numa_node_id)
2220 * Return -1 on failure
2222 int kfd_numa_node_to_apic_id(int numa_node_id)
2224 if (numa_node_id == -1) {
2225 pr_warn("Invalid NUMA Node. Use online CPU mask\n");
2226 return kfd_cpumask_to_apic_id(cpu_online_mask);
2228 return kfd_cpumask_to_apic_id(cpumask_of_node(numa_node_id));
2231 #if defined(CONFIG_DEBUG_FS)
2233 int kfd_debugfs_hqds_by_device(struct seq_file *m, void *data)
2235 struct kfd_topology_device *dev;
2239 down_read(&topology_lock);
2241 list_for_each_entry(dev, &topology_device_list, list) {
2247 seq_printf(m, "Node %u, gpu_id %x:\n", i++, dev->gpu->id);
2248 r = dqm_debugfs_hqds(m, dev->gpu->dqm);
2253 up_read(&topology_lock);
2258 int kfd_debugfs_rls_by_device(struct seq_file *m, void *data)
2260 struct kfd_topology_device *dev;
2264 down_read(&topology_lock);
2266 list_for_each_entry(dev, &topology_device_list, list) {
2272 seq_printf(m, "Node %u, gpu_id %x:\n", i++, dev->gpu->id);
2273 r = pm_debugfs_runlist(m, &dev->gpu->dqm->packet_mgr);
2278 up_read(&topology_lock);