drivers/gpu/drm/amd/amdgpu/vi.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/slab.h>
  24 #include "drmP.h"
  25 #include "amdgpu.h"
  26 #include "amdgpu_atombios.h"
  27 #include "amdgpu_ih.h"
  28 #include "amdgpu_uvd.h"
  29 #include "amdgpu_vce.h"
  30 #include "amdgpu_ucode.h"
  31 #include "atom.h"
  32 #include "amd_pcie.h"
  33
  34 #include "gmc/gmc_8_1_d.h"
  35 #include "gmc/gmc_8_1_sh_mask.h"
  36
  37 #include "oss/oss_3_0_d.h"
  38 #include "oss/oss_3_0_sh_mask.h"
  39
  40 #include "bif/bif_5_0_d.h"
  41 #include "bif/bif_5_0_sh_mask.h"
  42
  43 #include "gca/gfx_8_0_d.h"
  44 #include "gca/gfx_8_0_sh_mask.h"
  45
  46 #include "smu/smu_7_1_1_d.h"
  47 #include "smu/smu_7_1_1_sh_mask.h"
  48
  49 #include "uvd/uvd_5_0_d.h"
  50 #include "uvd/uvd_5_0_sh_mask.h"
  51
  52 #include "vce/vce_3_0_d.h"
  53 #include "vce/vce_3_0_sh_mask.h"
  54
  55 #include "dce/dce_10_0_d.h"
  56 #include "dce/dce_10_0_sh_mask.h"
  57
  58 #include "vid.h"
  59 #include "vi.h"
  60 #include "vi_dpm.h"
  61 #include "gmc_v8_0.h"
  62 #include "gmc_v7_0.h"
  63 #include "gfx_v8_0.h"
  64 #include "sdma_v2_4.h"
  65 #include "sdma_v3_0.h"
  66 #include "dce_v10_0.h"
  67 #include "dce_v11_0.h"
  68 #include "iceland_ih.h"
  69 #include "tonga_ih.h"
  70 #include "cz_ih.h"
  71 #include "uvd_v5_0.h"
  72 #include "uvd_v6_0.h"
  73 #include "vce_v3_0.h"
  74 #include "amdgpu_powerplay.h"
  75 #if defined(CONFIG_DRM_AMD_ACP)
  76 #include "amdgpu_acp.h"
  77 #endif
  78 #include "dce_virtual.h"
  79 #include "mxgpu_vi.h"
  80
  81 /*
  82  * Indirect registers accessor
  83  */
  84 static u32 vi_pcie_rreg(struct amdgpu_device *adev, u32 reg)
  85 {
  86         unsigned long flags;
  87         u32 r;
  88
  89         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
  90         WREG32(mmPCIE_INDEX, reg);
  91         (void)RREG32(mmPCIE_INDEX);
  92         r = RREG32(mmPCIE_DATA);
  93         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
  94         return r;
  95 }
  96
  97 static void vi_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
  98 {
  99         unsigned long flags;
 100
 101         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 102         WREG32(mmPCIE_INDEX, reg);
 103         (void)RREG32(mmPCIE_INDEX);
 104         WREG32(mmPCIE_DATA, v);
 105         (void)RREG32(mmPCIE_DATA);
 106         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 107 }
 108
 109 static u32 vi_smc_rreg(struct amdgpu_device *adev, u32 reg)
 110 {
 111         unsigned long flags;
 112         u32 r;
 113
 114         spin_lock_irqsave(&adev->smc_idx_lock, flags);
 115         WREG32(mmSMC_IND_INDEX_11, (reg));
 116         r = RREG32(mmSMC_IND_DATA_11);
 117         spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
 118         return r;
 119 }
 120
 121 static void vi_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 122 {
 123         unsigned long flags;
 124
 125         spin_lock_irqsave(&adev->smc_idx_lock, flags);
 126         WREG32(mmSMC_IND_INDEX_11, (reg));
 127         WREG32(mmSMC_IND_DATA_11, (v));
 128         spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
 129 }
 130
 131 /* smu_8_0_d.h */
 132 #define mmMP0PUB_IND_INDEX                                                      0x180
 133 #define mmMP0PUB_IND_DATA                                                       0x181
 134
 135 static u32 cz_smc_rreg(struct amdgpu_device *adev, u32 reg)
 136 {
 137         unsigned long flags;
 138         u32 r;
 139
 140         spin_lock_irqsave(&adev->smc_idx_lock, flags);
 141         WREG32(mmMP0PUB_IND_INDEX, (reg));
 142         r = RREG32(mmMP0PUB_IND_DATA);
 143         spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
 144         return r;
 145 }
 146
 147 static void cz_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 148 {
 149         unsigned long flags;
 150
 151         spin_lock_irqsave(&adev->smc_idx_lock, flags);
 152         WREG32(mmMP0PUB_IND_INDEX, (reg));
 153         WREG32(mmMP0PUB_IND_DATA, (v));
 154         spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
 155 }
 156
 157 static u32 vi_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
 158 {
 159         unsigned long flags;
 160         u32 r;
 161
 162         spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
 163         WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
 164         r = RREG32(mmUVD_CTX_DATA);
 165         spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
 166         return r;
 167 }
 168
 169 static void vi_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 170 {
 171         unsigned long flags;
 172
 173         spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
 174         WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
 175         WREG32(mmUVD_CTX_DATA, (v));
 176         spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
 177 }
 178
 179 static u32 vi_didt_rreg(struct amdgpu_device *adev, u32 reg)
 180 {
 181         unsigned long flags;
 182         u32 r;
 183
 184         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 185         WREG32(mmDIDT_IND_INDEX, (reg));
 186         r = RREG32(mmDIDT_IND_DATA);
 187         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 188         return r;
 189 }
 190
 191 static void vi_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 192 {
 193         unsigned long flags;
 194
 195         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 196         WREG32(mmDIDT_IND_INDEX, (reg));
 197         WREG32(mmDIDT_IND_DATA, (v));
 198         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 199 }
 200
 201 static u32 vi_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)
 202 {
 203         unsigned long flags;
 204         u32 r;
 205
 206         spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
 207         WREG32(mmGC_CAC_IND_INDEX, (reg));
 208         r = RREG32(mmGC_CAC_IND_DATA);
 209         spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
 210         return r;
 211 }
 212
 213 static void vi_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 214 {
 215         unsigned long flags;
 216
 217         spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
 218         WREG32(mmGC_CAC_IND_INDEX, (reg));
 219         WREG32(mmGC_CAC_IND_DATA, (v));
 220         spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
 221 }
 222
 223
 224 static const u32 tonga_mgcg_cgcg_init[] =
 225 {
 226         mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
 227         mmPCIE_INDEX, 0xffffffff, 0x0140001c,
 228         mmPCIE_DATA, 0x000f0000, 0x00000000,
 229         mmSMC_IND_INDEX_4, 0xffffffff, 0xC060000C,
 230         mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100,
 231         mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
 232         mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
 233 };
 234
 235 static const u32 fiji_mgcg_cgcg_init[] =
 236 {
 237         mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
 238         mmPCIE_INDEX, 0xffffffff, 0x0140001c,
 239         mmPCIE_DATA, 0x000f0000, 0x00000000,
 240         mmSMC_IND_INDEX_4, 0xffffffff, 0xC060000C,
 241         mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100,
 242         mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
 243         mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
 244 };
 245
 246 static const u32 iceland_mgcg_cgcg_init[] =
 247 {
 248         mmPCIE_INDEX, 0xffffffff, ixPCIE_CNTL2,
 249         mmPCIE_DATA, 0x000f0000, 0x00000000,
 250         mmSMC_IND_INDEX_4, 0xffffffff, ixCGTT_ROM_CLK_CTRL0,
 251         mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100,
 252         mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
 253 };
 254
 255 static const u32 cz_mgcg_cgcg_init[] =
 256 {
 257         mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
 258         mmPCIE_INDEX, 0xffffffff, 0x0140001c,
 259         mmPCIE_DATA, 0x000f0000, 0x00000000,
 260         mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
 261         mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
 262 };
 263
 264 static const u32 stoney_mgcg_cgcg_init[] =
 265 {
 266         mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00000100,
 267         mmHDP_XDP_CGTT_BLK_CTRL, 0xffffffff, 0x00000104,
 268         mmHDP_HOST_PATH_CNTL, 0xffffffff, 0x0f000027,
 269 };
 270
 271 static void vi_init_golden_registers(struct amdgpu_device *adev)
 272 {
 273         /* Some of the registers might be dependent on GRBM_GFX_INDEX */
 274         mutex_lock(&adev->grbm_idx_mutex);
 275
 276         if (amdgpu_sriov_vf(adev)) {
 277                 xgpu_vi_init_golden_registers(adev);
 278                 mutex_unlock(&adev->grbm_idx_mutex);
 279                 return;
 280         }
 281
 282         switch (adev->asic_type) {
 283         case CHIP_TOPAZ:
 284                 amdgpu_program_register_sequence(adev,
 285                                                  iceland_mgcg_cgcg_init,
 286                                                  (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
 287                 break;
 288         case CHIP_FIJI:
 289                 amdgpu_program_register_sequence(adev,
 290                                                  fiji_mgcg_cgcg_init,
 291                                                  (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
 292                 break;
 293         case CHIP_TONGA:
 294                 amdgpu_program_register_sequence(adev,
 295                                                  tonga_mgcg_cgcg_init,
 296                                                  (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
 297                 break;
 298         case CHIP_CARRIZO:
 299                 amdgpu_program_register_sequence(adev,
 300                                                  cz_mgcg_cgcg_init,
 301                                                  (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
 302                 break;
 303         case CHIP_STONEY:
 304                 amdgpu_program_register_sequence(adev,
 305                                                  stoney_mgcg_cgcg_init,
 306                                                  (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
 307                 break;
 308         case CHIP_POLARIS11:
 309         case CHIP_POLARIS10:
 310         case CHIP_POLARIS12:
 311         default:
 312                 break;
 313         }
 314         mutex_unlock(&adev->grbm_idx_mutex);
 315 }
 316
 317 /**
 318  * vi_get_xclk - get the xclk
 319  *
 320  * @adev: amdgpu_device pointer
 321  *
 322  * Returns the reference clock used by the gfx engine
 323  * (VI).
 324  */
 325 static u32 vi_get_xclk(struct amdgpu_device *adev)
 326 {
 327         u32 reference_clock = adev->clock.spll.reference_freq;
 328         u32 tmp;
 329
 330         if (adev->flags & AMD_IS_APU)
 331                 return reference_clock;
 332
 333         tmp = RREG32_SMC(ixCG_CLKPIN_CNTL_2);
 334         if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK))
 335                 return 1000;
 336
 337         tmp = RREG32_SMC(ixCG_CLKPIN_CNTL);
 338         if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL, XTALIN_DIVIDE))
 339                 return reference_clock / 4;
 340
 341         return reference_clock;
 342 }
 343
 344 /**
 345  * vi_srbm_select - select specific register instances
 346  *
 347  * @adev: amdgpu_device pointer
 348  * @me: selected ME (micro engine)
 349  * @pipe: pipe
 350  * @queue: queue
 351  * @vmid: VMID
 352  *
 353  * Switches the currently active registers instances.  Some
 354  * registers are instanced per VMID, others are instanced per
 355  * me/pipe/queue combination.
 356  */
 357 void vi_srbm_select(struct amdgpu_device *adev,
 358                      u32 me, u32 pipe, u32 queue, u32 vmid)
 359 {
 360         u32 srbm_gfx_cntl = 0;
 361         srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, PIPEID, pipe);
 362         srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, MEID, me);
 363         srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, vmid);
 364         srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, QUEUEID, queue);
 365         WREG32(mmSRBM_GFX_CNTL, srbm_gfx_cntl);
 366 }
 367
 368 static void vi_vga_set_state(struct amdgpu_device *adev, bool state)
 369 {
 370         /* todo */
 371 }
 372
 373 static bool vi_read_disabled_bios(struct amdgpu_device *adev)
 374 {
 375         u32 bus_cntl;
 376         u32 d1vga_control = 0;
 377         u32 d2vga_control = 0;
 378         u32 vga_render_control = 0;
 379         u32 rom_cntl;
 380         bool r;
 381
 382         bus_cntl = RREG32(mmBUS_CNTL);
 383         if (adev->mode_info.num_crtc) {
 384                 d1vga_control = RREG32(mmD1VGA_CONTROL);
 385                 d2vga_control = RREG32(mmD2VGA_CONTROL);
 386                 vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
 387         }
 388         rom_cntl = RREG32_SMC(ixROM_CNTL);
 389
 390         /* enable the rom */
 391         WREG32(mmBUS_CNTL, (bus_cntl & ~BUS_CNTL__BIOS_ROM_DIS_MASK));
 392         if (adev->mode_info.num_crtc) {
 393                 /* Disable VGA mode */
 394                 WREG32(mmD1VGA_CONTROL,
 395                        (d1vga_control & ~(D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK |
 396                                           D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK)));
 397                 WREG32(mmD2VGA_CONTROL,
 398                        (d2vga_control & ~(D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK |
 399                                           D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK)));
 400                 WREG32(mmVGA_RENDER_CONTROL,
 401                        (vga_render_control & ~VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK));
 402         }
 403         WREG32_SMC(ixROM_CNTL, rom_cntl | ROM_CNTL__SCK_OVERWRITE_MASK);
 404
 405         r = amdgpu_read_bios(adev);
 406
 407         /* restore regs */
 408         WREG32(mmBUS_CNTL, bus_cntl);
 409         if (adev->mode_info.num_crtc) {
 410                 WREG32(mmD1VGA_CONTROL, d1vga_control);
 411                 WREG32(mmD2VGA_CONTROL, d2vga_control);
 412                 WREG32(mmVGA_RENDER_CONTROL, vga_render_control);
 413         }
 414         WREG32_SMC(ixROM_CNTL, rom_cntl);
 415         return r;
 416 }
 417
 418 static bool vi_read_bios_from_rom(struct amdgpu_device *adev,
 419                                   u8 *bios, u32 length_bytes)
 420 {
 421         u32 *dw_ptr;
 422         unsigned long flags;
 423         u32 i, length_dw;
 424
 425         if (bios == NULL)
 426                 return false;
 427         if (length_bytes == 0)
 428                 return false;
 429         /* APU vbios image is part of sbios image */
 430         if (adev->flags & AMD_IS_APU)
 431                 return false;
 432
 433         dw_ptr = (u32 *)bios;
 434         length_dw = ALIGN(length_bytes, 4) / 4;
 435         /* take the smc lock since we are using the smc index */
 436         spin_lock_irqsave(&adev->smc_idx_lock, flags);
 437         /* set rom index to 0 */
 438         WREG32(mmSMC_IND_INDEX_11, ixROM_INDEX);
 439         WREG32(mmSMC_IND_DATA_11, 0);
 440         /* set index to data for continous read */
 441         WREG32(mmSMC_IND_INDEX_11, ixROM_DATA);
 442         for (i = 0; i < length_dw; i++)
 443                 dw_ptr[i] = RREG32(mmSMC_IND_DATA_11);
 444         spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
 445
 446         return true;
 447 }
 448
 449 static void vi_detect_hw_virtualization(struct amdgpu_device *adev)
 450 {
 451         uint32_t reg = RREG32(mmBIF_IOV_FUNC_IDENTIFIER);
 452         /* bit0: 0 means pf and 1 means vf */
 453         /* bit31: 0 means disable IOV and 1 means enable */
 454         if (reg & 1)
 455                 adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF;
 456
 457         if (reg & 0x80000000)
 458                 adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV;
 459
 460         if (reg == 0) {
 461                 if (is_virtual_machine()) /* passthrough mode exclus sr-iov mode */
 462                         adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE;
 463         }
 464 }
 465
 466 static const struct amdgpu_allowed_register_entry tonga_allowed_read_registers[] = {
 467         {mmGB_MACROTILE_MODE7, true},
 468 };
 469
 470 static const struct amdgpu_allowed_register_entry cz_allowed_read_registers[] = {
 471         {mmGB_TILE_MODE7, true},
 472         {mmGB_TILE_MODE12, true},
 473         {mmGB_TILE_MODE17, true},
 474         {mmGB_TILE_MODE23, true},
 475         {mmGB_MACROTILE_MODE7, true},
 476 };
 477
 478 static const struct amdgpu_allowed_register_entry vi_allowed_read_registers[] = {
 479         {mmGRBM_STATUS, false},
 480         {mmGRBM_STATUS2, false},
 481         {mmGRBM_STATUS_SE0, false},
 482         {mmGRBM_STATUS_SE1, false},
 483         {mmGRBM_STATUS_SE2, false},
 484         {mmGRBM_STATUS_SE3, false},
 485         {mmSRBM_STATUS, false},
 486         {mmSRBM_STATUS2, false},
 487         {mmSRBM_STATUS3, false},
 488         {mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET, false},
 489         {mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET, false},
 490         {mmCP_STAT, false},
 491         {mmCP_STALLED_STAT1, false},
 492         {mmCP_STALLED_STAT2, false},
 493         {mmCP_STALLED_STAT3, false},
 494         {mmCP_CPF_BUSY_STAT, false},
 495         {mmCP_CPF_STALLED_STAT1, false},
 496         {mmCP_CPF_STATUS, false},
 497         {mmCP_CPC_BUSY_STAT, false},
 498         {mmCP_CPC_STALLED_STAT1, false},
 499         {mmCP_CPC_STATUS, false},
 500         {mmGB_ADDR_CONFIG, false},
 501         {mmMC_ARB_RAMCFG, false},
 502         {mmGB_TILE_MODE0, false},
 503         {mmGB_TILE_MODE1, false},
 504         {mmGB_TILE_MODE2, false},
 505         {mmGB_TILE_MODE3, false},
 506         {mmGB_TILE_MODE4, false},
 507         {mmGB_TILE_MODE5, false},
 508         {mmGB_TILE_MODE6, false},
 509         {mmGB_TILE_MODE7, false},
 510         {mmGB_TILE_MODE8, false},
 511         {mmGB_TILE_MODE9, false},
 512         {mmGB_TILE_MODE10, false},
 513         {mmGB_TILE_MODE11, false},
 514         {mmGB_TILE_MODE12, false},
 515         {mmGB_TILE_MODE13, false},
 516         {mmGB_TILE_MODE14, false},
 517         {mmGB_TILE_MODE15, false},
 518         {mmGB_TILE_MODE16, false},
 519         {mmGB_TILE_MODE17, false},
 520         {mmGB_TILE_MODE18, false},
 521         {mmGB_TILE_MODE19, false},
 522         {mmGB_TILE_MODE20, false},
 523         {mmGB_TILE_MODE21, false},
 524         {mmGB_TILE_MODE22, false},
 525         {mmGB_TILE_MODE23, false},
 526         {mmGB_TILE_MODE24, false},
 527         {mmGB_TILE_MODE25, false},
 528         {mmGB_TILE_MODE26, false},
 529         {mmGB_TILE_MODE27, false},
 530         {mmGB_TILE_MODE28, false},
 531         {mmGB_TILE_MODE29, false},
 532         {mmGB_TILE_MODE30, false},
 533         {mmGB_TILE_MODE31, false},
 534         {mmGB_MACROTILE_MODE0, false},
 535         {mmGB_MACROTILE_MODE1, false},
 536         {mmGB_MACROTILE_MODE2, false},
 537         {mmGB_MACROTILE_MODE3, false},
 538         {mmGB_MACROTILE_MODE4, false},
 539         {mmGB_MACROTILE_MODE5, false},
 540         {mmGB_MACROTILE_MODE6, false},
 541         {mmGB_MACROTILE_MODE7, false},
 542         {mmGB_MACROTILE_MODE8, false},
 543         {mmGB_MACROTILE_MODE9, false},
 544         {mmGB_MACROTILE_MODE10, false},
 545         {mmGB_MACROTILE_MODE11, false},
 546         {mmGB_MACROTILE_MODE12, false},
 547         {mmGB_MACROTILE_MODE13, false},
 548         {mmGB_MACROTILE_MODE14, false},
 549         {mmGB_MACROTILE_MODE15, false},
 550         {mmCC_RB_BACKEND_DISABLE, false, true},
 551         {mmGC_USER_RB_BACKEND_DISABLE, false, true},
 552         {mmGB_BACKEND_MAP, false, false},
 553         {mmPA_SC_RASTER_CONFIG, false, true},
 554         {mmPA_SC_RASTER_CONFIG_1, false, true},
 555 };
 556
 557 static uint32_t vi_get_register_value(struct amdgpu_device *adev,
 558                                       bool indexed, u32 se_num,
 559                                       u32 sh_num, u32 reg_offset)
 560 {
 561         if (indexed) {
 562                 uint32_t val;
 563                 unsigned se_idx = (se_num == 0xffffffff) ? 0 : se_num;
 564                 unsigned sh_idx = (sh_num == 0xffffffff) ? 0 : sh_num;
 565
 566                 switch (reg_offset) {
 567                 case mmCC_RB_BACKEND_DISABLE:
 568                         return adev->gfx.config.rb_config[se_idx][sh_idx].rb_backend_disable;
 569                 case mmGC_USER_RB_BACKEND_DISABLE:
 570                         return adev->gfx.config.rb_config[se_idx][sh_idx].user_rb_backend_disable;
 571                 case mmPA_SC_RASTER_CONFIG:
 572                         return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config;
 573                 case mmPA_SC_RASTER_CONFIG_1:
 574                         return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config_1;
 575                 }
 576
 577                 mutex_lock(&adev->grbm_idx_mutex);
 578                 if (se_num != 0xffffffff || sh_num != 0xffffffff)
 579                         amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
 580
 581                 val = RREG32(reg_offset);
 582
 583                 if (se_num != 0xffffffff || sh_num != 0xffffffff)
 584                         amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
 585                 mutex_unlock(&adev->grbm_idx_mutex);
 586                 return val;
 587         } else {
 588                 unsigned idx;
 589
 590                 switch (reg_offset) {
 591                 case mmGB_ADDR_CONFIG:
 592                         return adev->gfx.config.gb_addr_config;
 593                 case mmMC_ARB_RAMCFG:
 594                         return adev->gfx.config.mc_arb_ramcfg;
 595                 case mmGB_TILE_MODE0:
 596                 case mmGB_TILE_MODE1:
 597                 case mmGB_TILE_MODE2:
 598                 case mmGB_TILE_MODE3:
 599                 case mmGB_TILE_MODE4:
 600                 case mmGB_TILE_MODE5:
 601                 case mmGB_TILE_MODE6:
 602                 case mmGB_TILE_MODE7:
 603                 case mmGB_TILE_MODE8:
 604                 case mmGB_TILE_MODE9:
 605                 case mmGB_TILE_MODE10:
 606                 case mmGB_TILE_MODE11:
 607                 case mmGB_TILE_MODE12:
 608                 case mmGB_TILE_MODE13:
 609                 case mmGB_TILE_MODE14:
 610                 case mmGB_TILE_MODE15:
 611                 case mmGB_TILE_MODE16:
 612                 case mmGB_TILE_MODE17:
 613                 case mmGB_TILE_MODE18:
 614                 case mmGB_TILE_MODE19:
 615                 case mmGB_TILE_MODE20:
 616                 case mmGB_TILE_MODE21:
 617                 case mmGB_TILE_MODE22:
 618                 case mmGB_TILE_MODE23:
 619                 case mmGB_TILE_MODE24:
 620                 case mmGB_TILE_MODE25:
 621                 case mmGB_TILE_MODE26:
 622                 case mmGB_TILE_MODE27:
 623                 case mmGB_TILE_MODE28:
 624                 case mmGB_TILE_MODE29:
 625                 case mmGB_TILE_MODE30:
 626                 case mmGB_TILE_MODE31:
 627                         idx = (reg_offset - mmGB_TILE_MODE0);
 628                         return adev->gfx.config.tile_mode_array[idx];
 629                 case mmGB_MACROTILE_MODE0:
 630                 case mmGB_MACROTILE_MODE1:
 631                 case mmGB_MACROTILE_MODE2:
 632                 case mmGB_MACROTILE_MODE3:
 633                 case mmGB_MACROTILE_MODE4:
 634                 case mmGB_MACROTILE_MODE5:
 635                 case mmGB_MACROTILE_MODE6:
 636                 case mmGB_MACROTILE_MODE7:
 637                 case mmGB_MACROTILE_MODE8:
 638                 case mmGB_MACROTILE_MODE9:
 639                 case mmGB_MACROTILE_MODE10:
 640                 case mmGB_MACROTILE_MODE11:
 641                 case mmGB_MACROTILE_MODE12:
 642                 case mmGB_MACROTILE_MODE13:
 643                 case mmGB_MACROTILE_MODE14:
 644                 case mmGB_MACROTILE_MODE15:
 645                         idx = (reg_offset - mmGB_MACROTILE_MODE0);
 646                         return adev->gfx.config.macrotile_mode_array[idx];
 647                 default:
 648                         return RREG32(reg_offset);
 649                 }
 650         }
 651 }
 652
 653 static int vi_read_register(struct amdgpu_device *adev, u32 se_num,
 654                             u32 sh_num, u32 reg_offset, u32 *value)
 655 {
 656         const struct amdgpu_allowed_register_entry *asic_register_table = NULL;
 657         const struct amdgpu_allowed_register_entry *asic_register_entry;
 658         uint32_t size, i;
 659
 660         *value = 0;
 661         switch (adev->asic_type) {
 662         case CHIP_TOPAZ:
 663                 asic_register_table = tonga_allowed_read_registers;
 664                 size = ARRAY_SIZE(tonga_allowed_read_registers);
 665                 break;
 666         case CHIP_FIJI:
 667         case CHIP_TONGA:
 668         case CHIP_POLARIS11:
 669         case CHIP_POLARIS10:
 670         case CHIP_POLARIS12:
 671         case CHIP_CARRIZO:
 672         case CHIP_STONEY:
 673                 asic_register_table = cz_allowed_read_registers;
 674                 size = ARRAY_SIZE(cz_allowed_read_registers);
 675                 break;
 676         default:
 677                 return -EINVAL;
 678         }
 679
 680         if (asic_register_table) {
 681                 for (i = 0; i < size; i++) {
 682                         asic_register_entry = asic_register_table + i;
 683                         if (reg_offset != asic_register_entry->reg_offset)
 684                                 continue;
 685                         if (!asic_register_entry->untouched)
 686                                 *value = vi_get_register_value(adev,
 687                                                                asic_register_entry->grbm_indexed,
 688                                                                se_num, sh_num, reg_offset);
 689                         return 0;
 690                 }
 691         }
 692
 693         for (i = 0; i < ARRAY_SIZE(vi_allowed_read_registers); i++) {
 694                 if (reg_offset != vi_allowed_read_registers[i].reg_offset)
 695                         continue;
 696
 697                 if (!vi_allowed_read_registers[i].untouched)
 698                         *value = vi_get_register_value(adev,
 699                                                        vi_allowed_read_registers[i].grbm_indexed,
 700                                                        se_num, sh_num, reg_offset);
 701                 return 0;
 702         }
 703         return -EINVAL;
 704 }
 705
 706 static int vi_gpu_pci_config_reset(struct amdgpu_device *adev)
 707 {
 708         u32 i;
 709
 710         dev_info(adev->dev, "GPU pci config reset\n");
 711
 712         /* disable BM */
 713         pci_clear_master(adev->pdev);
 714         /* reset */
 715         amdgpu_pci_config_reset(adev);
 716
 717         udelay(100);
 718
 719         /* wait for asic to come out of reset */
 720         for (i = 0; i < adev->usec_timeout; i++) {
 721                 if (RREG32(mmCONFIG_MEMSIZE) != 0xffffffff) {
 722                         /* enable BM */
 723                         pci_set_master(adev->pdev);
 724                         adev->has_hw_reset = true;
 725                         return 0;
 726                 }
 727                 udelay(1);
 728         }
 729         return -EINVAL;
 730 }
 731
 732 /**
 733  * vi_asic_reset - soft reset GPU
 734  *
 735  * @adev: amdgpu_device pointer
 736  *
 737  * Look up which blocks are hung and attempt
 738  * to reset them.
 739  * Returns 0 for success.
 740  */
 741 static int vi_asic_reset(struct amdgpu_device *adev)
 742 {
 743         int r;
 744
 745         amdgpu_atombios_scratch_regs_engine_hung(adev, true);
 746
 747         r = vi_gpu_pci_config_reset(adev);
 748
 749         amdgpu_atombios_scratch_regs_engine_hung(adev, false);
 750
 751         return r;
 752 }
 753
 754 static u32 vi_get_config_memsize(struct amdgpu_device *adev)
 755 {
 756         return RREG32(mmCONFIG_MEMSIZE);
 757 }
 758
 759 static int vi_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
 760                         u32 cntl_reg, u32 status_reg)
 761 {
 762         int r, i;
 763         struct atom_clock_dividers dividers;
 764         uint32_t tmp;
 765
 766         r = amdgpu_atombios_get_clock_dividers(adev,
 767                                                COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
 768                                                clock, false, &dividers);
 769         if (r)
 770                 return r;
 771
 772         tmp = RREG32_SMC(cntl_reg);
 773         tmp &= ~(CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK |
 774                 CG_DCLK_CNTL__DCLK_DIVIDER_MASK);
 775         tmp |= dividers.post_divider;
 776         WREG32_SMC(cntl_reg, tmp);
 777
 778         for (i = 0; i < 100; i++) {
 779                 if (RREG32_SMC(status_reg) & CG_DCLK_STATUS__DCLK_STATUS_MASK)
 780                         break;
 781                 mdelay(10);
 782         }
 783         if (i == 100)
 784                 return -ETIMEDOUT;
 785
 786         return 0;
 787 }
 788
 789 static int vi_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
 790 {
 791         int r;
 792
 793         r = vi_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
 794         if (r)
 795                 return r;
 796
 797         r = vi_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
 798         if (r)
 799                 return r;
 800
 801         return 0;
 802 }
 803
 804 static int vi_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
 805 {
 806         int r, i;
 807         struct atom_clock_dividers dividers;
 808         u32 tmp;
 809
 810         r = amdgpu_atombios_get_clock_dividers(adev,
 811                                                COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
 812                                                ecclk, false, &dividers);
 813         if (r)
 814                 return r;
 815
 816         for (i = 0; i < 100; i++) {
 817                 if (RREG32_SMC(ixCG_ECLK_STATUS) & CG_ECLK_STATUS__ECLK_STATUS_MASK)
 818                         break;
 819                 mdelay(10);
 820         }
 821         if (i == 100)
 822                 return -ETIMEDOUT;
 823
 824         tmp = RREG32_SMC(ixCG_ECLK_CNTL);
 825         tmp &= ~(CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK |
 826                 CG_ECLK_CNTL__ECLK_DIVIDER_MASK);
 827         tmp |= dividers.post_divider;
 828         WREG32_SMC(ixCG_ECLK_CNTL, tmp);
 829
 830         for (i = 0; i < 100; i++) {
 831                 if (RREG32_SMC(ixCG_ECLK_STATUS) & CG_ECLK_STATUS__ECLK_STATUS_MASK)
 832                         break;
 833                 mdelay(10);
 834         }
 835         if (i == 100)
 836                 return -ETIMEDOUT;
 837
 838         return 0;
 839 }
 840
 841 static void vi_pcie_gen3_enable(struct amdgpu_device *adev)
 842 {
 843         if (pci_is_root_bus(adev->pdev->bus))
 844                 return;
 845
 846         if (amdgpu_pcie_gen2 == 0)
 847                 return;
 848
 849         if (adev->flags & AMD_IS_APU)
 850                 return;
 851
 852         if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
 853                                         CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
 854                 return;
 855
 856         /* todo */
 857 }
 858
 859 static void vi_program_aspm(struct amdgpu_device *adev)
 860 {
 861
 862         if (amdgpu_aspm == 0)
 863                 return;
 864
 865         /* todo */
 866 }
 867
 868 static void vi_enable_doorbell_aperture(struct amdgpu_device *adev,
 869                                         bool enable)
 870 {
 871         u32 tmp;
 872
 873         /* not necessary on CZ */
 874         if (adev->flags & AMD_IS_APU)
 875                 return;
 876
 877         tmp = RREG32(mmBIF_DOORBELL_APER_EN);
 878         if (enable)
 879                 tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 1);
 880         else
 881                 tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 0);
 882
 883         WREG32(mmBIF_DOORBELL_APER_EN, tmp);
 884 }
 885
 886 #define ATI_REV_ID_FUSE_MACRO__ADDRESS      0xC0014044
 887 #define ATI_REV_ID_FUSE_MACRO__SHIFT        9
 888 #define ATI_REV_ID_FUSE_MACRO__MASK         0x00001E00
 889
 890 static uint32_t vi_get_rev_id(struct amdgpu_device *adev)
 891 {
 892         if (adev->flags & AMD_IS_APU)
 893                 return (RREG32_SMC(ATI_REV_ID_FUSE_MACRO__ADDRESS) & ATI_REV_ID_FUSE_MACRO__MASK)
 894                         >> ATI_REV_ID_FUSE_MACRO__SHIFT;
 895         else
 896                 return (RREG32(mmPCIE_EFUSE4) & PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID_MASK)
 897                         >> PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID__SHIFT;
 898 }
 899
 900 static const struct amdgpu_asic_funcs vi_asic_funcs =
 901 {
 902         .read_disabled_bios = &vi_read_disabled_bios,
 903         .read_bios_from_rom = &vi_read_bios_from_rom,
 904         .read_register = &vi_read_register,
 905         .reset = &vi_asic_reset,
 906         .set_vga_state = &vi_vga_set_state,
 907         .get_xclk = &vi_get_xclk,
 908         .set_uvd_clocks = &vi_set_uvd_clocks,
 909         .set_vce_clocks = &vi_set_vce_clocks,
 910         .get_config_memsize = &vi_get_config_memsize,
 911 };
 912
 913 #define CZ_REV_BRISTOL(rev)      \
 914         ((rev >= 0xC8 && rev <= 0xCE) || (rev >= 0xE1 && rev <= 0xE6))
 915
 916 static int vi_common_early_init(void *handle)
 917 {
 918         bool smc_enabled = false;
 919         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 920
 921         if (adev->flags & AMD_IS_APU) {
 922                 adev->smc_rreg = &cz_smc_rreg;
 923                 adev->smc_wreg = &cz_smc_wreg;
 924         } else {
 925                 adev->smc_rreg = &vi_smc_rreg;
 926                 adev->smc_wreg = &vi_smc_wreg;
 927         }
 928         adev->pcie_rreg = &vi_pcie_rreg;
 929         adev->pcie_wreg = &vi_pcie_wreg;
 930         adev->uvd_ctx_rreg = &vi_uvd_ctx_rreg;
 931         adev->uvd_ctx_wreg = &vi_uvd_ctx_wreg;
 932         adev->didt_rreg = &vi_didt_rreg;
 933         adev->didt_wreg = &vi_didt_wreg;
 934         adev->gc_cac_rreg = &vi_gc_cac_rreg;
 935         adev->gc_cac_wreg = &vi_gc_cac_wreg;
 936
 937         adev->asic_funcs = &vi_asic_funcs;
 938
 939         if (amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_SMC) &&
 940                 (amdgpu_ip_block_mask & (1 << AMD_IP_BLOCK_TYPE_SMC)))
 941                 smc_enabled = true;
 942
 943         if (amdgpu_sriov_vf(adev)) {
 944                 amdgpu_virt_init_setting(adev);
 945                 xgpu_vi_mailbox_set_irq_funcs(adev);
 946         }
 947
 948         adev->rev_id = vi_get_rev_id(adev);
 949         adev->external_rev_id = 0xFF;
 950         switch (adev->asic_type) {
 951         case CHIP_TOPAZ:
 952                 adev->cg_flags = 0;
 953                 adev->pg_flags = 0;
 954                 adev->external_rev_id = 0x1;
 955                 break;
 956         case CHIP_FIJI:
 957                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 958                         AMD_CG_SUPPORT_GFX_MGLS |
 959                         AMD_CG_SUPPORT_GFX_RLC_LS |
 960                         AMD_CG_SUPPORT_GFX_CP_LS |
 961                         AMD_CG_SUPPORT_GFX_CGTS |
 962                         AMD_CG_SUPPORT_GFX_CGTS_LS |
 963                         AMD_CG_SUPPORT_GFX_CGCG |
 964                         AMD_CG_SUPPORT_GFX_CGLS |
 965                         AMD_CG_SUPPORT_SDMA_MGCG |
 966                         AMD_CG_SUPPORT_SDMA_LS |
 967                         AMD_CG_SUPPORT_BIF_LS |
 968                         AMD_CG_SUPPORT_HDP_MGCG |
 969                         AMD_CG_SUPPORT_HDP_LS |
 970                         AMD_CG_SUPPORT_ROM_MGCG |
 971                         AMD_CG_SUPPORT_MC_MGCG |
 972                         AMD_CG_SUPPORT_MC_LS |
 973                         AMD_CG_SUPPORT_UVD_MGCG;
 974                 adev->pg_flags = 0;
 975                 adev->external_rev_id = adev->rev_id + 0x3c;
 976                 break;
 977         case CHIP_TONGA:
 978                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 979                         AMD_CG_SUPPORT_GFX_CGCG |
 980                         AMD_CG_SUPPORT_GFX_CGLS |
 981                         AMD_CG_SUPPORT_SDMA_MGCG |
 982                         AMD_CG_SUPPORT_SDMA_LS |
 983                         AMD_CG_SUPPORT_BIF_LS |
 984                         AMD_CG_SUPPORT_HDP_MGCG |
 985                         AMD_CG_SUPPORT_HDP_LS |
 986                         AMD_CG_SUPPORT_ROM_MGCG |
 987                         AMD_CG_SUPPORT_MC_MGCG |
 988                         AMD_CG_SUPPORT_MC_LS |
 989                         AMD_CG_SUPPORT_DRM_LS |
 990                         AMD_CG_SUPPORT_UVD_MGCG;
 991                 adev->pg_flags = 0;
 992                 adev->external_rev_id = adev->rev_id + 0x14;
 993                 break;
 994         case CHIP_POLARIS11:
 995                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 996                         AMD_CG_SUPPORT_GFX_RLC_LS |
 997                         AMD_CG_SUPPORT_GFX_CP_LS |
 998                         AMD_CG_SUPPORT_GFX_CGCG |
 999                         AMD_CG_SUPPORT_GFX_CGLS |
1000                         AMD_CG_SUPPORT_GFX_3D_CGCG |
1001                         AMD_CG_SUPPORT_GFX_3D_CGLS |
1002                         AMD_CG_SUPPORT_SDMA_MGCG |
1003                         AMD_CG_SUPPORT_SDMA_LS |
1004                         AMD_CG_SUPPORT_BIF_MGCG |
1005                         AMD_CG_SUPPORT_BIF_LS |
1006                         AMD_CG_SUPPORT_HDP_MGCG |
1007                         AMD_CG_SUPPORT_HDP_LS |
1008                         AMD_CG_SUPPORT_ROM_MGCG |
1009                         AMD_CG_SUPPORT_MC_MGCG |
1010                         AMD_CG_SUPPORT_MC_LS |
1011                         AMD_CG_SUPPORT_DRM_LS |
1012                         AMD_CG_SUPPORT_UVD_MGCG |
1013                         AMD_CG_SUPPORT_VCE_MGCG;
1014                 adev->pg_flags = 0;
1015                 adev->external_rev_id = adev->rev_id + 0x5A;
1016                 break;
1017         case CHIP_POLARIS10:
1018                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1019                         AMD_CG_SUPPORT_GFX_RLC_LS |
1020                         AMD_CG_SUPPORT_GFX_CP_LS |
1021                         AMD_CG_SUPPORT_GFX_CGCG |
1022                         AMD_CG_SUPPORT_GFX_CGLS |
1023                         AMD_CG_SUPPORT_GFX_3D_CGCG |
1024                         AMD_CG_SUPPORT_GFX_3D_CGLS |
1025                         AMD_CG_SUPPORT_SDMA_MGCG |
1026                         AMD_CG_SUPPORT_SDMA_LS |
1027                         AMD_CG_SUPPORT_BIF_MGCG |
1028                         AMD_CG_SUPPORT_BIF_LS |
1029                         AMD_CG_SUPPORT_HDP_MGCG |
1030                         AMD_CG_SUPPORT_HDP_LS |
1031                         AMD_CG_SUPPORT_ROM_MGCG |
1032                         AMD_CG_SUPPORT_MC_MGCG |
1033                         AMD_CG_SUPPORT_MC_LS |
1034                         AMD_CG_SUPPORT_DRM_LS |
1035                         AMD_CG_SUPPORT_UVD_MGCG |
1036                         AMD_CG_SUPPORT_VCE_MGCG;
1037                 adev->pg_flags = 0;
1038                 adev->external_rev_id = adev->rev_id + 0x50;
1039                 break;
1040         case CHIP_POLARIS12:
1041                 adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG;
1042                 adev->pg_flags = 0;
1043                 adev->external_rev_id = adev->rev_id + 0x64;
1044                 break;
1045         case CHIP_CARRIZO:
1046                 adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG |
1047                         AMD_CG_SUPPORT_GFX_MGCG |
1048                         AMD_CG_SUPPORT_GFX_MGLS |
1049                         AMD_CG_SUPPORT_GFX_RLC_LS |
1050                         AMD_CG_SUPPORT_GFX_CP_LS |
1051                         AMD_CG_SUPPORT_GFX_CGTS |
1052                         AMD_CG_SUPPORT_GFX_CGTS_LS |
1053                         AMD_CG_SUPPORT_GFX_CGCG |
1054                         AMD_CG_SUPPORT_GFX_CGLS |
1055                         AMD_CG_SUPPORT_BIF_LS |
1056                         AMD_CG_SUPPORT_HDP_MGCG |
1057                         AMD_CG_SUPPORT_HDP_LS |
1058                         AMD_CG_SUPPORT_SDMA_MGCG |
1059                         AMD_CG_SUPPORT_SDMA_LS |
1060                         AMD_CG_SUPPORT_VCE_MGCG;
1061                 /* rev0 hardware requires workarounds to support PG */
1062                 adev->pg_flags = 0;
1063                 if (adev->rev_id != 0x00 || CZ_REV_BRISTOL(adev->pdev->revision)) {
1064                         adev->pg_flags |=
1065                                 AMD_PG_SUPPORT_GFX_SMG |
1066                                 AMD_PG_SUPPORT_GFX_PIPELINE |
1067                                 AMD_PG_SUPPORT_CP |
1068                                 AMD_PG_SUPPORT_UVD |
1069                                 AMD_PG_SUPPORT_VCE;
1070                 }
1071                 adev->external_rev_id = adev->rev_id + 0x1;
1072                 break;
1073         case CHIP_STONEY:
1074                 adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG |
1075                         AMD_CG_SUPPORT_GFX_MGCG |
1076                         AMD_CG_SUPPORT_GFX_MGLS |
1077                         AMD_CG_SUPPORT_GFX_RLC_LS |
1078                         AMD_CG_SUPPORT_GFX_CP_LS |
1079                         AMD_CG_SUPPORT_GFX_CGTS |
1080                         AMD_CG_SUPPORT_GFX_CGTS_LS |
1081                         AMD_CG_SUPPORT_GFX_CGCG |
1082                         AMD_CG_SUPPORT_GFX_CGLS |
1083                         AMD_CG_SUPPORT_BIF_LS |
1084                         AMD_CG_SUPPORT_HDP_MGCG |
1085                         AMD_CG_SUPPORT_HDP_LS |
1086                         AMD_CG_SUPPORT_SDMA_MGCG |
1087                         AMD_CG_SUPPORT_SDMA_LS |
1088                         AMD_CG_SUPPORT_VCE_MGCG;
1089                 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG |
1090                         AMD_PG_SUPPORT_GFX_SMG |
1091                         AMD_PG_SUPPORT_GFX_PIPELINE |
1092                         AMD_PG_SUPPORT_CP |
1093                         AMD_PG_SUPPORT_UVD |
1094                         AMD_PG_SUPPORT_VCE;
1095                 adev->external_rev_id = adev->rev_id + 0x61;
1096                 break;
1097         default:
1098                 /* FIXME: not supported yet */
1099                 return -EINVAL;
1100         }
1101
1102         if (amdgpu_smc_load_fw && smc_enabled)
1103                 adev->firmware.smu_load = true;
1104
1105         amdgpu_get_pcie_info(adev);
1106
1107         return 0;
1108 }
1109
1110 static int vi_common_late_init(void *handle)
1111 {
1112         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1113
1114         if (amdgpu_sriov_vf(adev))
1115                 xgpu_vi_mailbox_get_irq(adev);
1116
1117         return 0;
1118 }
1119
1120 static int vi_common_sw_init(void *handle)
1121 {
1122         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1123
1124         if (amdgpu_sriov_vf(adev))
1125                 xgpu_vi_mailbox_add_irq_id(adev);
1126
1127         return 0;
1128 }
1129
1130 static int vi_common_sw_fini(void *handle)
1131 {
1132         return 0;
1133 }
1134
1135 static int vi_common_hw_init(void *handle)
1136 {
1137         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1138
1139         /* move the golden regs per IP block */
1140         vi_init_golden_registers(adev);
1141         /* enable pcie gen2/3 link */
1142         vi_pcie_gen3_enable(adev);
1143         /* enable aspm */
1144         vi_program_aspm(adev);
1145         /* enable the doorbell aperture */
1146         vi_enable_doorbell_aperture(adev, true);
1147
1148         return 0;
1149 }
1150
1151 static int vi_common_hw_fini(void *handle)
1152 {
1153         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1154
1155         /* enable the doorbell aperture */
1156         vi_enable_doorbell_aperture(adev, false);
1157
1158         if (amdgpu_sriov_vf(adev))
1159                 xgpu_vi_mailbox_put_irq(adev);
1160
1161         return 0;
1162 }
1163
1164 static int vi_common_suspend(void *handle)
1165 {
1166         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1167
1168         return vi_common_hw_fini(adev);
1169 }
1170
1171 static int vi_common_resume(void *handle)
1172 {
1173         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1174
1175         return vi_common_hw_init(adev);
1176 }
1177
1178 static bool vi_common_is_idle(void *handle)
1179 {
1180         return true;
1181 }
1182
1183 static int vi_common_wait_for_idle(void *handle)
1184 {
1185         return 0;
1186 }
1187
1188 static int vi_common_soft_reset(void *handle)
1189 {
1190         return 0;
1191 }
1192
1193 static void vi_update_bif_medium_grain_light_sleep(struct amdgpu_device *adev,
1194                                                    bool enable)
1195 {
1196         uint32_t temp, data;
1197
1198         temp = data = RREG32_PCIE(ixPCIE_CNTL2);
1199
1200         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))
1201                 data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
1202                                 PCIE_CNTL2__MST_MEM_LS_EN_MASK |
1203                                 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK;
1204         else
1205                 data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
1206                                 PCIE_CNTL2__MST_MEM_LS_EN_MASK |
1207                                 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
1208
1209         if (temp != data)
1210                 WREG32_PCIE(ixPCIE_CNTL2, data);
1211 }
1212
1213 static void vi_update_hdp_medium_grain_clock_gating(struct amdgpu_device *adev,
1214                                                     bool enable)
1215 {
1216         uint32_t temp, data;
1217
1218         temp = data = RREG32(mmHDP_HOST_PATH_CNTL);
1219
1220         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG))
1221                 data &= ~HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK;
1222         else
1223                 data |= HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK;
1224
1225         if (temp != data)
1226                 WREG32(mmHDP_HOST_PATH_CNTL, data);
1227 }
1228
1229 static void vi_update_hdp_light_sleep(struct amdgpu_device *adev,
1230                                       bool enable)
1231 {
1232         uint32_t temp, data;
1233
1234         temp = data = RREG32(mmHDP_MEM_POWER_LS);
1235
1236         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
1237                 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1238         else
1239                 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1240
1241         if (temp != data)
1242                 WREG32(mmHDP_MEM_POWER_LS, data);
1243 }
1244
1245 static void vi_update_drm_light_sleep(struct amdgpu_device *adev,
1246                                       bool enable)
1247 {
1248         uint32_t temp, data;
1249
1250         temp = data = RREG32(0x157a);
1251
1252         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))
1253                 data |= 1;
1254         else
1255                 data &= ~1;
1256
1257         if (temp != data)
1258                 WREG32(0x157a, data);
1259 }
1260
1261
1262 static void vi_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,
1263                                                     bool enable)
1264 {
1265         uint32_t temp, data;
1266
1267         temp = data = RREG32_SMC(ixCGTT_ROM_CLK_CTRL0);
1268
1269         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))
1270                 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1271                                 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK);
1272         else
1273                 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1274                                 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK;
1275
1276         if (temp != data)
1277                 WREG32_SMC(ixCGTT_ROM_CLK_CTRL0, data);
1278 }
1279
1280 static int vi_common_set_clockgating_state_by_smu(void *handle,
1281                                            enum amd_clockgating_state state)
1282 {
1283         uint32_t msg_id, pp_state = 0;
1284         uint32_t pp_support_state = 0;
1285         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1286         void *pp_handle = adev->powerplay.pp_handle;
1287
1288         if (adev->cg_flags & (AMD_CG_SUPPORT_MC_LS | AMD_CG_SUPPORT_MC_MGCG)) {
1289                 if (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) {
1290                         pp_support_state = AMD_CG_SUPPORT_MC_LS;
1291                         pp_state = PP_STATE_LS;
1292                 }
1293                 if (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG) {
1294                         pp_support_state |= AMD_CG_SUPPORT_MC_MGCG;
1295                         pp_state |= PP_STATE_CG;
1296                 }
1297                 if (state == AMD_CG_STATE_UNGATE)
1298                         pp_state = 0;
1299                 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1300                                PP_BLOCK_SYS_MC,
1301                                pp_support_state,
1302                                pp_state);
1303                 amd_set_clockgating_by_smu(pp_handle, msg_id);
1304         }
1305
1306         if (adev->cg_flags & (AMD_CG_SUPPORT_SDMA_LS | AMD_CG_SUPPORT_SDMA_MGCG)) {
1307                 if (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS) {
1308                         pp_support_state = AMD_CG_SUPPORT_SDMA_LS;
1309                         pp_state = PP_STATE_LS;
1310                 }
1311                 if (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG) {
1312                         pp_support_state |= AMD_CG_SUPPORT_SDMA_MGCG;
1313                         pp_state |= PP_STATE_CG;
1314                 }
1315                 if (state == AMD_CG_STATE_UNGATE)
1316                         pp_state = 0;
1317                 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1318                                PP_BLOCK_SYS_SDMA,
1319                                pp_support_state,
1320                                pp_state);
1321                 amd_set_clockgating_by_smu(pp_handle, msg_id);
1322         }
1323
1324         if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_MGCG)) {
1325                 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) {
1326                         pp_support_state = AMD_CG_SUPPORT_HDP_LS;
1327                         pp_state = PP_STATE_LS;
1328                 }
1329                 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG) {
1330                         pp_support_state |= AMD_CG_SUPPORT_HDP_MGCG;
1331                         pp_state |= PP_STATE_CG;
1332                 }
1333                 if (state == AMD_CG_STATE_UNGATE)
1334                         pp_state = 0;
1335                 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1336                                PP_BLOCK_SYS_HDP,
1337                                pp_support_state,
1338                                pp_state);
1339                 amd_set_clockgating_by_smu(pp_handle, msg_id);
1340         }
1341
1342
1343         if (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS) {
1344                 if (state == AMD_CG_STATE_UNGATE)
1345                         pp_state = 0;
1346                 else
1347                         pp_state = PP_STATE_LS;
1348
1349                 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1350                                PP_BLOCK_SYS_BIF,
1351                                PP_STATE_SUPPORT_LS,
1352                                 pp_state);
1353                 amd_set_clockgating_by_smu(pp_handle, msg_id);
1354         }
1355         if (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG) {
1356                 if (state == AMD_CG_STATE_UNGATE)
1357                         pp_state = 0;
1358                 else
1359                         pp_state = PP_STATE_CG;
1360
1361                 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1362                                PP_BLOCK_SYS_BIF,
1363                                PP_STATE_SUPPORT_CG,
1364                                pp_state);
1365                 amd_set_clockgating_by_smu(pp_handle, msg_id);
1366         }
1367
1368         if (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS) {
1369
1370                 if (state == AMD_CG_STATE_UNGATE)
1371                         pp_state = 0;
1372                 else
1373                         pp_state = PP_STATE_LS;
1374
1375                 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1376                                PP_BLOCK_SYS_DRM,
1377                                PP_STATE_SUPPORT_LS,
1378                                pp_state);
1379                 amd_set_clockgating_by_smu(pp_handle, msg_id);
1380         }
1381
1382         if (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG) {
1383
1384                 if (state == AMD_CG_STATE_UNGATE)
1385                         pp_state = 0;
1386                 else
1387                         pp_state = PP_STATE_CG;
1388
1389                 msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
1390                                PP_BLOCK_SYS_ROM,
1391                                PP_STATE_SUPPORT_CG,
1392                                pp_state);
1393                 amd_set_clockgating_by_smu(pp_handle, msg_id);
1394         }
1395         return 0;
1396 }
1397
1398 static int vi_common_set_clockgating_state(void *handle,
1399                                            enum amd_clockgating_state state)
1400 {
1401         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1402
1403         if (amdgpu_sriov_vf(adev))
1404                 return 0;
1405
1406         switch (adev->asic_type) {
1407         case CHIP_FIJI:
1408                 vi_update_bif_medium_grain_light_sleep(adev,
1409                                 state == AMD_CG_STATE_GATE);
1410                 vi_update_hdp_medium_grain_clock_gating(adev,
1411                                 state == AMD_CG_STATE_GATE);
1412                 vi_update_hdp_light_sleep(adev,
1413                                 state == AMD_CG_STATE_GATE);
1414                 vi_update_rom_medium_grain_clock_gating(adev,
1415                                 state == AMD_CG_STATE_GATE);
1416                 break;
1417         case CHIP_CARRIZO:
1418         case CHIP_STONEY:
1419                 vi_update_bif_medium_grain_light_sleep(adev,
1420                                 state == AMD_CG_STATE_GATE);
1421                 vi_update_hdp_medium_grain_clock_gating(adev,
1422                                 state == AMD_CG_STATE_GATE);
1423                 vi_update_hdp_light_sleep(adev,
1424                                 state == AMD_CG_STATE_GATE);
1425                 vi_update_drm_light_sleep(adev,
1426                                 state == AMD_CG_STATE_GATE);
1427                 break;
1428         case CHIP_TONGA:
1429         case CHIP_POLARIS10:
1430         case CHIP_POLARIS11:
1431         case CHIP_POLARIS12:
1432                 vi_common_set_clockgating_state_by_smu(adev, state);
1433         default:
1434                 break;
1435         }
1436         return 0;
1437 }
1438
1439 static int vi_common_set_powergating_state(void *handle,
1440                                             enum amd_powergating_state state)
1441 {
1442         return 0;
1443 }
1444
1445 static void vi_common_get_clockgating_state(void *handle, u32 *flags)
1446 {
1447         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1448         int data;
1449
1450         if (amdgpu_sriov_vf(adev))
1451                 *flags = 0;
1452
1453         /* AMD_CG_SUPPORT_BIF_LS */
1454         data = RREG32_PCIE(ixPCIE_CNTL2);
1455         if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK)
1456                 *flags |= AMD_CG_SUPPORT_BIF_LS;
1457
1458         /* AMD_CG_SUPPORT_HDP_LS */
1459         data = RREG32(mmHDP_MEM_POWER_LS);
1460         if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK)
1461                 *flags |= AMD_CG_SUPPORT_HDP_LS;
1462
1463         /* AMD_CG_SUPPORT_HDP_MGCG */
1464         data = RREG32(mmHDP_HOST_PATH_CNTL);
1465         if (!(data & HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK))
1466                 *flags |= AMD_CG_SUPPORT_HDP_MGCG;
1467
1468         /* AMD_CG_SUPPORT_ROM_MGCG */
1469         data = RREG32_SMC(ixCGTT_ROM_CLK_CTRL0);
1470         if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))
1471                 *flags |= AMD_CG_SUPPORT_ROM_MGCG;
1472 }
1473
1474 static const struct amd_ip_funcs vi_common_ip_funcs = {
1475         .name = "vi_common",
1476         .early_init = vi_common_early_init,
1477         .late_init = vi_common_late_init,
1478         .sw_init = vi_common_sw_init,
1479         .sw_fini = vi_common_sw_fini,
1480         .hw_init = vi_common_hw_init,
1481         .hw_fini = vi_common_hw_fini,
1482         .suspend = vi_common_suspend,
1483         .resume = vi_common_resume,
1484         .is_idle = vi_common_is_idle,
1485         .wait_for_idle = vi_common_wait_for_idle,
1486         .soft_reset = vi_common_soft_reset,
1487         .set_clockgating_state = vi_common_set_clockgating_state,
1488         .set_powergating_state = vi_common_set_powergating_state,
1489         .get_clockgating_state = vi_common_get_clockgating_state,
1490 };
1491
1492 static const struct amdgpu_ip_block_version vi_common_ip_block =
1493 {
1494         .type = AMD_IP_BLOCK_TYPE_COMMON,
1495         .major = 1,
1496         .minor = 0,
1497         .rev = 0,
1498         .funcs = &vi_common_ip_funcs,
1499 };
1500
1501 int vi_set_ip_blocks(struct amdgpu_device *adev)
1502 {
1503         /* in early init stage, vbios code won't work */
1504         vi_detect_hw_virtualization(adev);
1505
1506         if (amdgpu_sriov_vf(adev))
1507                 adev->virt.ops = &xgpu_vi_virt_ops;
1508
1509         switch (adev->asic_type) {
1510         case CHIP_TOPAZ:
1511                 /* topaz has no DCE, UVD, VCE */
1512                 amdgpu_ip_block_add(adev, &vi_common_ip_block);
1513                 amdgpu_ip_block_add(adev, &gmc_v7_4_ip_block);
1514                 amdgpu_ip_block_add(adev, &iceland_ih_ip_block);
1515                 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
1516                 if (adev->enable_virtual_display)
1517                         amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
1518                 amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block);
1519                 amdgpu_ip_block_add(adev, &sdma_v2_4_ip_block);
1520                 break;
1521         case CHIP_FIJI:
1522                 amdgpu_ip_block_add(adev, &vi_common_ip_block);
1523                 amdgpu_ip_block_add(adev, &gmc_v8_5_ip_block);
1524                 amdgpu_ip_block_add(adev, &tonga_ih_ip_block);
1525                 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
1526                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
1527                         amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
1528                 else
1529                         amdgpu_ip_block_add(adev, &dce_v10_1_ip_block);
1530                 amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block);
1531                 amdgpu_ip_block_add(adev, &sdma_v3_0_ip_block);
1532                 if (!amdgpu_sriov_vf(adev)) {
1533                         amdgpu_ip_block_add(adev, &uvd_v6_0_ip_block);
1534                         amdgpu_ip_block_add(adev, &vce_v3_0_ip_block);
1535                 }
1536                 break;
1537         case CHIP_TONGA:
1538                 amdgpu_ip_block_add(adev, &vi_common_ip_block);
1539                 amdgpu_ip_block_add(adev, &gmc_v8_0_ip_block);
1540                 amdgpu_ip_block_add(adev, &tonga_ih_ip_block);
1541                 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
1542                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
1543                         amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
1544                 else
1545                         amdgpu_ip_block_add(adev, &dce_v10_0_ip_block);
1546                 amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block);
1547                 amdgpu_ip_block_add(adev, &sdma_v3_0_ip_block);
1548                 if (!amdgpu_sriov_vf(adev)) {
1549                         amdgpu_ip_block_add(adev, &uvd_v5_0_ip_block);
1550                         amdgpu_ip_block_add(adev, &vce_v3_0_ip_block);
1551                 }
1552                 break;
1553         case CHIP_POLARIS11:
1554         case CHIP_POLARIS10:
1555         case CHIP_POLARIS12:
1556                 amdgpu_ip_block_add(adev, &vi_common_ip_block);
1557                 amdgpu_ip_block_add(adev, &gmc_v8_1_ip_block);
1558                 amdgpu_ip_block_add(adev, &tonga_ih_ip_block);
1559                 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
1560                 if (adev->enable_virtual_display)
1561                         amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
1562                 else
1563                         amdgpu_ip_block_add(adev, &dce_v11_2_ip_block);
1564                 amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block);
1565                 amdgpu_ip_block_add(adev, &sdma_v3_1_ip_block);
1566                 amdgpu_ip_block_add(adev, &uvd_v6_3_ip_block);
1567                 amdgpu_ip_block_add(adev, &vce_v3_4_ip_block);
1568                 break;
1569         case CHIP_CARRIZO:
1570                 amdgpu_ip_block_add(adev, &vi_common_ip_block);
1571                 amdgpu_ip_block_add(adev, &gmc_v8_0_ip_block);
1572                 amdgpu_ip_block_add(adev, &cz_ih_ip_block);
1573                 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
1574                 if (adev->enable_virtual_display)
1575                         amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
1576                 else
1577                         amdgpu_ip_block_add(adev, &dce_v11_0_ip_block);
1578                 amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block);
1579                 amdgpu_ip_block_add(adev, &sdma_v3_0_ip_block);
1580                 amdgpu_ip_block_add(adev, &uvd_v6_0_ip_block);
1581                 amdgpu_ip_block_add(adev, &vce_v3_1_ip_block);
1582 #if defined(CONFIG_DRM_AMD_ACP)
1583                 amdgpu_ip_block_add(adev, &acp_ip_block);
1584 #endif
1585                 break;
1586         case CHIP_STONEY:
1587                 amdgpu_ip_block_add(adev, &vi_common_ip_block);
1588                 amdgpu_ip_block_add(adev, &gmc_v8_0_ip_block);
1589                 amdgpu_ip_block_add(adev, &cz_ih_ip_block);
1590                 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
1591                 if (adev->enable_virtual_display)
1592                         amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
1593                 else
1594                         amdgpu_ip_block_add(adev, &dce_v11_0_ip_block);
1595                 amdgpu_ip_block_add(adev, &gfx_v8_1_ip_block);
1596                 amdgpu_ip_block_add(adev, &sdma_v3_0_ip_block);
1597                 amdgpu_ip_block_add(adev, &uvd_v6_2_ip_block);
1598                 amdgpu_ip_block_add(adev, &vce_v3_4_ip_block);
1599 #if defined(CONFIG_DRM_AMD_ACP)
1600                 amdgpu_ip_block_add(adev, &acp_ip_block);
1601 #endif
1602                 break;
1603         default:
1604                 /* FIXME: not supported yet */
1605                 return -EINVAL;
1606         }
1607
1608         return 0;
1609 }