drivers/gpu/drm/amd/amdgpu/vi.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <linux/slab.h>
  25 #include <linux/module.h>
  26 #include "drmP.h"
  27 #include "amdgpu.h"
  28 #include "amdgpu_atombios.h"
  29 #include "amdgpu_ih.h"
  30 #include "amdgpu_uvd.h"
  31 #include "amdgpu_vce.h"
  32 #include "amdgpu_ucode.h"
  33 #include "atom.h"
  34
  35 #include "gmc/gmc_8_1_d.h"
  36 #include "gmc/gmc_8_1_sh_mask.h"
  37
  38 #include "oss/oss_3_0_d.h"
  39 #include "oss/oss_3_0_sh_mask.h"
  40
  41 #include "bif/bif_5_0_d.h"
  42 #include "bif/bif_5_0_sh_mask.h"
  43
  44 #include "gca/gfx_8_0_d.h"
  45 #include "gca/gfx_8_0_sh_mask.h"
  46
  47 #include "smu/smu_7_1_1_d.h"
  48 #include "smu/smu_7_1_1_sh_mask.h"
  49
  50 #include "uvd/uvd_5_0_d.h"
  51 #include "uvd/uvd_5_0_sh_mask.h"
  52
  53 #include "vce/vce_3_0_d.h"
  54 #include "vce/vce_3_0_sh_mask.h"
  55
  56 #include "dce/dce_10_0_d.h"
  57 #include "dce/dce_10_0_sh_mask.h"
  58
  59 #include "vid.h"
  60 #include "vi.h"
  61 #include "vi_dpm.h"
  62 #include "gmc_v8_0.h"
  63 #include "gfx_v8_0.h"
  64 #include "sdma_v2_4.h"
  65 #include "sdma_v3_0.h"
  66 #include "dce_v10_0.h"
  67 #include "dce_v11_0.h"
  68 #include "iceland_ih.h"
  69 #include "tonga_ih.h"
  70 #include "cz_ih.h"
  71 #include "uvd_v5_0.h"
  72 #include "uvd_v6_0.h"
  73 #include "vce_v3_0.h"
  74
  75 /*
  76  * Indirect registers accessor
  77  */
  78 static u32 vi_pcie_rreg(struct amdgpu_device *adev, u32 reg)
  79 {
  80         unsigned long flags;
  81         u32 r;
  82
  83         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
  84         WREG32(mmPCIE_INDEX, reg);
  85         (void)RREG32(mmPCIE_INDEX);
  86         r = RREG32(mmPCIE_DATA);
  87         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
  88         return r;
  89 }
  90
  91 static void vi_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
  92 {
  93         unsigned long flags;
  94
  95         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
  96         WREG32(mmPCIE_INDEX, reg);
  97         (void)RREG32(mmPCIE_INDEX);
  98         WREG32(mmPCIE_DATA, v);
  99         (void)RREG32(mmPCIE_DATA);
 100         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 101 }
 102
 103 static u32 vi_smc_rreg(struct amdgpu_device *adev, u32 reg)
 104 {
 105         unsigned long flags;
 106         u32 r;
 107
 108         spin_lock_irqsave(&adev->smc_idx_lock, flags);
 109         WREG32(mmSMC_IND_INDEX_0, (reg));
 110         r = RREG32(mmSMC_IND_DATA_0);
 111         spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
 112         return r;
 113 }
 114
 115 static void vi_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 116 {
 117         unsigned long flags;
 118
 119         spin_lock_irqsave(&adev->smc_idx_lock, flags);
 120         WREG32(mmSMC_IND_INDEX_0, (reg));
 121         WREG32(mmSMC_IND_DATA_0, (v));
 122         spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
 123 }
 124
 125 /* smu_8_0_d.h */
 126 #define mmMP0PUB_IND_INDEX                                                      0x180
 127 #define mmMP0PUB_IND_DATA                                                       0x181
 128
 129 static u32 cz_smc_rreg(struct amdgpu_device *adev, u32 reg)
 130 {
 131         unsigned long flags;
 132         u32 r;
 133
 134         spin_lock_irqsave(&adev->smc_idx_lock, flags);
 135         WREG32(mmMP0PUB_IND_INDEX, (reg));
 136         r = RREG32(mmMP0PUB_IND_DATA);
 137         spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
 138         return r;
 139 }
 140
 141 static void cz_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 142 {
 143         unsigned long flags;
 144
 145         spin_lock_irqsave(&adev->smc_idx_lock, flags);
 146         WREG32(mmMP0PUB_IND_INDEX, (reg));
 147         WREG32(mmMP0PUB_IND_DATA, (v));
 148         spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
 149 }
 150
 151 static u32 vi_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
 152 {
 153         unsigned long flags;
 154         u32 r;
 155
 156         spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
 157         WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
 158         r = RREG32(mmUVD_CTX_DATA);
 159         spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
 160         return r;
 161 }
 162
 163 static void vi_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 164 {
 165         unsigned long flags;
 166
 167         spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
 168         WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
 169         WREG32(mmUVD_CTX_DATA, (v));
 170         spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
 171 }
 172
 173 static u32 vi_didt_rreg(struct amdgpu_device *adev, u32 reg)
 174 {
 175         unsigned long flags;
 176         u32 r;
 177
 178         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 179         WREG32(mmDIDT_IND_INDEX, (reg));
 180         r = RREG32(mmDIDT_IND_DATA);
 181         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 182         return r;
 183 }
 184
 185 static void vi_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 186 {
 187         unsigned long flags;
 188
 189         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 190         WREG32(mmDIDT_IND_INDEX, (reg));
 191         WREG32(mmDIDT_IND_DATA, (v));
 192         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 193 }
 194
 195 static const u32 tonga_mgcg_cgcg_init[] =
 196 {
 197         mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
 198         mmPCIE_INDEX, 0xffffffff, 0x0140001c,
 199         mmPCIE_DATA, 0x000f0000, 0x00000000,
 200         mmSMC_IND_INDEX_4, 0xffffffff, 0xC060000C,
 201         mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100,
 202         mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
 203         mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
 204 };
 205
 206 static const u32 fiji_mgcg_cgcg_init[] =
 207 {
 208         mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
 209         mmPCIE_INDEX, 0xffffffff, 0x0140001c,
 210         mmPCIE_DATA, 0x000f0000, 0x00000000,
 211         mmSMC_IND_INDEX_4, 0xffffffff, 0xC060000C,
 212         mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100,
 213         mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
 214         mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
 215 };
 216
 217 static const u32 iceland_mgcg_cgcg_init[] =
 218 {
 219         mmPCIE_INDEX, 0xffffffff, ixPCIE_CNTL2,
 220         mmPCIE_DATA, 0x000f0000, 0x00000000,
 221         mmSMC_IND_INDEX_4, 0xffffffff, ixCGTT_ROM_CLK_CTRL0,
 222         mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100,
 223         mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
 224 };
 225
 226 static const u32 cz_mgcg_cgcg_init[] =
 227 {
 228         mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
 229         mmPCIE_INDEX, 0xffffffff, 0x0140001c,
 230         mmPCIE_DATA, 0x000f0000, 0x00000000,
 231         mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
 232         mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
 233 };
 234
 235 static const u32 stoney_mgcg_cgcg_init[] =
 236 {
 237         mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00000100,
 238         mmHDP_XDP_CGTT_BLK_CTRL, 0xffffffff, 0x00000104,
 239         mmHDP_HOST_PATH_CNTL, 0xffffffff, 0x0f000027,
 240 };
 241
 242 static void vi_init_golden_registers(struct amdgpu_device *adev)
 243 {
 244         /* Some of the registers might be dependent on GRBM_GFX_INDEX */
 245         mutex_lock(&adev->grbm_idx_mutex);
 246
 247         switch (adev->asic_type) {
 248         case CHIP_TOPAZ:
 249                 amdgpu_program_register_sequence(adev,
 250                                                  iceland_mgcg_cgcg_init,
 251                                                  (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
 252                 break;
 253         case CHIP_FIJI:
 254                 amdgpu_program_register_sequence(adev,
 255                                                  fiji_mgcg_cgcg_init,
 256                                                  (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
 257                 break;
 258         case CHIP_TONGA:
 259                 amdgpu_program_register_sequence(adev,
 260                                                  tonga_mgcg_cgcg_init,
 261                                                  (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
 262                 break;
 263         case CHIP_CARRIZO:
 264                 amdgpu_program_register_sequence(adev,
 265                                                  cz_mgcg_cgcg_init,
 266                                                  (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
 267                 break;
 268         case CHIP_STONEY:
 269                 amdgpu_program_register_sequence(adev,
 270                                                  stoney_mgcg_cgcg_init,
 271                                                  (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
 272                 break;
 273         default:
 274                 break;
 275         }
 276         mutex_unlock(&adev->grbm_idx_mutex);
 277 }
 278
 279 /**
 280  * vi_get_xclk - get the xclk
 281  *
 282  * @adev: amdgpu_device pointer
 283  *
 284  * Returns the reference clock used by the gfx engine
 285  * (VI).
 286  */
 287 static u32 vi_get_xclk(struct amdgpu_device *adev)
 288 {
 289         u32 reference_clock = adev->clock.spll.reference_freq;
 290         u32 tmp;
 291
 292         if (adev->flags & AMD_IS_APU)
 293                 return reference_clock;
 294
 295         tmp = RREG32_SMC(ixCG_CLKPIN_CNTL_2);
 296         if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK))
 297                 return 1000;
 298
 299         tmp = RREG32_SMC(ixCG_CLKPIN_CNTL);
 300         if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL, XTALIN_DIVIDE))
 301                 return reference_clock / 4;
 302
 303         return reference_clock;
 304 }
 305
 306 /**
 307  * vi_srbm_select - select specific register instances
 308  *
 309  * @adev: amdgpu_device pointer
 310  * @me: selected ME (micro engine)
 311  * @pipe: pipe
 312  * @queue: queue
 313  * @vmid: VMID
 314  *
 315  * Switches the currently active registers instances.  Some
 316  * registers are instanced per VMID, others are instanced per
 317  * me/pipe/queue combination.
 318  */
 319 void vi_srbm_select(struct amdgpu_device *adev,
 320                      u32 me, u32 pipe, u32 queue, u32 vmid)
 321 {
 322         u32 srbm_gfx_cntl = 0;
 323         srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, PIPEID, pipe);
 324         srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, MEID, me);
 325         srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, vmid);
 326         srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, QUEUEID, queue);
 327         WREG32(mmSRBM_GFX_CNTL, srbm_gfx_cntl);
 328 }
 329
 330 static void vi_vga_set_state(struct amdgpu_device *adev, bool state)
 331 {
 332         /* todo */
 333 }
 334
 335 static bool vi_read_disabled_bios(struct amdgpu_device *adev)
 336 {
 337         u32 bus_cntl;
 338         u32 d1vga_control = 0;
 339         u32 d2vga_control = 0;
 340         u32 vga_render_control = 0;
 341         u32 rom_cntl;
 342         bool r;
 343
 344         bus_cntl = RREG32(mmBUS_CNTL);
 345         if (adev->mode_info.num_crtc) {
 346                 d1vga_control = RREG32(mmD1VGA_CONTROL);
 347                 d2vga_control = RREG32(mmD2VGA_CONTROL);
 348                 vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
 349         }
 350         rom_cntl = RREG32_SMC(ixROM_CNTL);
 351
 352         /* enable the rom */
 353         WREG32(mmBUS_CNTL, (bus_cntl & ~BUS_CNTL__BIOS_ROM_DIS_MASK));
 354         if (adev->mode_info.num_crtc) {
 355                 /* Disable VGA mode */
 356                 WREG32(mmD1VGA_CONTROL,
 357                        (d1vga_control & ~(D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK |
 358                                           D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK)));
 359                 WREG32(mmD2VGA_CONTROL,
 360                        (d2vga_control & ~(D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK |
 361                                           D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK)));
 362                 WREG32(mmVGA_RENDER_CONTROL,
 363                        (vga_render_control & ~VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK));
 364         }
 365         WREG32_SMC(ixROM_CNTL, rom_cntl | ROM_CNTL__SCK_OVERWRITE_MASK);
 366
 367         r = amdgpu_read_bios(adev);
 368
 369         /* restore regs */
 370         WREG32(mmBUS_CNTL, bus_cntl);
 371         if (adev->mode_info.num_crtc) {
 372                 WREG32(mmD1VGA_CONTROL, d1vga_control);
 373                 WREG32(mmD2VGA_CONTROL, d2vga_control);
 374                 WREG32(mmVGA_RENDER_CONTROL, vga_render_control);
 375         }
 376         WREG32_SMC(ixROM_CNTL, rom_cntl);
 377         return r;
 378 }
 379
 380 static bool vi_read_bios_from_rom(struct amdgpu_device *adev,
 381                                   u8 *bios, u32 length_bytes)
 382 {
 383         u32 *dw_ptr;
 384         unsigned long flags;
 385         u32 i, length_dw;
 386
 387         if (bios == NULL)
 388                 return false;
 389         if (length_bytes == 0)
 390                 return false;
 391         /* APU vbios image is part of sbios image */
 392         if (adev->flags & AMD_IS_APU)
 393                 return false;
 394
 395         dw_ptr = (u32 *)bios;
 396         length_dw = ALIGN(length_bytes, 4) / 4;
 397         /* take the smc lock since we are using the smc index */
 398         spin_lock_irqsave(&adev->smc_idx_lock, flags);
 399         /* set rom index to 0 */
 400         WREG32(mmSMC_IND_INDEX_0, ixROM_INDEX);
 401         WREG32(mmSMC_IND_DATA_0, 0);
 402         /* set index to data for continous read */
 403         WREG32(mmSMC_IND_INDEX_0, ixROM_DATA);
 404         for (i = 0; i < length_dw; i++)
 405                 dw_ptr[i] = RREG32(mmSMC_IND_DATA_0);
 406         spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
 407
 408         return true;
 409 }
 410
 411 static struct amdgpu_allowed_register_entry tonga_allowed_read_registers[] = {
 412         {mmGB_MACROTILE_MODE7, true},
 413 };
 414
 415 static struct amdgpu_allowed_register_entry cz_allowed_read_registers[] = {
 416         {mmGB_TILE_MODE7, true},
 417         {mmGB_TILE_MODE12, true},
 418         {mmGB_TILE_MODE17, true},
 419         {mmGB_TILE_MODE23, true},
 420         {mmGB_MACROTILE_MODE7, true},
 421 };
 422
 423 static struct amdgpu_allowed_register_entry vi_allowed_read_registers[] = {
 424         {mmGRBM_STATUS, false},
 425         {mmGRBM_STATUS2, false},
 426         {mmGRBM_STATUS_SE0, false},
 427         {mmGRBM_STATUS_SE1, false},
 428         {mmGRBM_STATUS_SE2, false},
 429         {mmGRBM_STATUS_SE3, false},
 430         {mmSRBM_STATUS, false},
 431         {mmSRBM_STATUS2, false},
 432         {mmSRBM_STATUS3, false},
 433         {mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET, false},
 434         {mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET, false},
 435         {mmCP_STAT, false},
 436         {mmCP_STALLED_STAT1, false},
 437         {mmCP_STALLED_STAT2, false},
 438         {mmCP_STALLED_STAT3, false},
 439         {mmCP_CPF_BUSY_STAT, false},
 440         {mmCP_CPF_STALLED_STAT1, false},
 441         {mmCP_CPF_STATUS, false},
 442         {mmCP_CPC_BUSY_STAT, false},
 443         {mmCP_CPC_STALLED_STAT1, false},
 444         {mmCP_CPC_STATUS, false},
 445         {mmGB_ADDR_CONFIG, false},
 446         {mmMC_ARB_RAMCFG, false},
 447         {mmGB_TILE_MODE0, false},
 448         {mmGB_TILE_MODE1, false},
 449         {mmGB_TILE_MODE2, false},
 450         {mmGB_TILE_MODE3, false},
 451         {mmGB_TILE_MODE4, false},
 452         {mmGB_TILE_MODE5, false},
 453         {mmGB_TILE_MODE6, false},
 454         {mmGB_TILE_MODE7, false},
 455         {mmGB_TILE_MODE8, false},
 456         {mmGB_TILE_MODE9, false},
 457         {mmGB_TILE_MODE10, false},
 458         {mmGB_TILE_MODE11, false},
 459         {mmGB_TILE_MODE12, false},
 460         {mmGB_TILE_MODE13, false},
 461         {mmGB_TILE_MODE14, false},
 462         {mmGB_TILE_MODE15, false},
 463         {mmGB_TILE_MODE16, false},
 464         {mmGB_TILE_MODE17, false},
 465         {mmGB_TILE_MODE18, false},
 466         {mmGB_TILE_MODE19, false},
 467         {mmGB_TILE_MODE20, false},
 468         {mmGB_TILE_MODE21, false},
 469         {mmGB_TILE_MODE22, false},
 470         {mmGB_TILE_MODE23, false},
 471         {mmGB_TILE_MODE24, false},
 472         {mmGB_TILE_MODE25, false},
 473         {mmGB_TILE_MODE26, false},
 474         {mmGB_TILE_MODE27, false},
 475         {mmGB_TILE_MODE28, false},
 476         {mmGB_TILE_MODE29, false},
 477         {mmGB_TILE_MODE30, false},
 478         {mmGB_TILE_MODE31, false},
 479         {mmGB_MACROTILE_MODE0, false},
 480         {mmGB_MACROTILE_MODE1, false},
 481         {mmGB_MACROTILE_MODE2, false},
 482         {mmGB_MACROTILE_MODE3, false},
 483         {mmGB_MACROTILE_MODE4, false},
 484         {mmGB_MACROTILE_MODE5, false},
 485         {mmGB_MACROTILE_MODE6, false},
 486         {mmGB_MACROTILE_MODE7, false},
 487         {mmGB_MACROTILE_MODE8, false},
 488         {mmGB_MACROTILE_MODE9, false},
 489         {mmGB_MACROTILE_MODE10, false},
 490         {mmGB_MACROTILE_MODE11, false},
 491         {mmGB_MACROTILE_MODE12, false},
 492         {mmGB_MACROTILE_MODE13, false},
 493         {mmGB_MACROTILE_MODE14, false},
 494         {mmGB_MACROTILE_MODE15, false},
 495         {mmCC_RB_BACKEND_DISABLE, false, true},
 496         {mmGC_USER_RB_BACKEND_DISABLE, false, true},
 497         {mmGB_BACKEND_MAP, false, false},
 498         {mmPA_SC_RASTER_CONFIG, false, true},
 499         {mmPA_SC_RASTER_CONFIG_1, false, true},
 500 };
 501
 502 static uint32_t vi_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
 503                                          u32 sh_num, u32 reg_offset)
 504 {
 505         uint32_t val;
 506
 507         mutex_lock(&adev->grbm_idx_mutex);
 508         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 509                 gfx_v8_0_select_se_sh(adev, se_num, sh_num);
 510
 511         val = RREG32(reg_offset);
 512
 513         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 514                 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
 515         mutex_unlock(&adev->grbm_idx_mutex);
 516         return val;
 517 }
 518
 519 static int vi_read_register(struct amdgpu_device *adev, u32 se_num,
 520                             u32 sh_num, u32 reg_offset, u32 *value)
 521 {
 522         struct amdgpu_allowed_register_entry *asic_register_table = NULL;
 523         struct amdgpu_allowed_register_entry *asic_register_entry;
 524         uint32_t size, i;
 525
 526         *value = 0;
 527         switch (adev->asic_type) {
 528         case CHIP_TOPAZ:
 529                 asic_register_table = tonga_allowed_read_registers;
 530                 size = ARRAY_SIZE(tonga_allowed_read_registers);
 531                 break;
 532         case CHIP_FIJI:
 533         case CHIP_TONGA:
 534         case CHIP_CARRIZO:
 535         case CHIP_STONEY:
 536                 asic_register_table = cz_allowed_read_registers;
 537                 size = ARRAY_SIZE(cz_allowed_read_registers);
 538                 break;
 539         default:
 540                 return -EINVAL;
 541         }
 542
 543         if (asic_register_table) {
 544                 for (i = 0; i < size; i++) {
 545                         asic_register_entry = asic_register_table + i;
 546                         if (reg_offset != asic_register_entry->reg_offset)
 547                                 continue;
 548                         if (!asic_register_entry->untouched)
 549                                 *value = asic_register_entry->grbm_indexed ?
 550                                         vi_read_indexed_register(adev, se_num,
 551                                                                  sh_num, reg_offset) :
 552                                         RREG32(reg_offset);
 553                         return 0;
 554                 }
 555         }
 556
 557         for (i = 0; i < ARRAY_SIZE(vi_allowed_read_registers); i++) {
 558                 if (reg_offset != vi_allowed_read_registers[i].reg_offset)
 559                         continue;
 560
 561                 if (!vi_allowed_read_registers[i].untouched)
 562                         *value = vi_allowed_read_registers[i].grbm_indexed ?
 563                                 vi_read_indexed_register(adev, se_num,
 564                                                          sh_num, reg_offset) :
 565                                 RREG32(reg_offset);
 566                 return 0;
 567         }
 568         return -EINVAL;
 569 }
 570
 571 static void vi_print_gpu_status_regs(struct amdgpu_device *adev)
 572 {
 573         dev_info(adev->dev, "  GRBM_STATUS=0x%08X\n",
 574                 RREG32(mmGRBM_STATUS));
 575         dev_info(adev->dev, "  GRBM_STATUS2=0x%08X\n",
 576                 RREG32(mmGRBM_STATUS2));
 577         dev_info(adev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
 578                 RREG32(mmGRBM_STATUS_SE0));
 579         dev_info(adev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
 580                 RREG32(mmGRBM_STATUS_SE1));
 581         dev_info(adev->dev, "  GRBM_STATUS_SE2=0x%08X\n",
 582                 RREG32(mmGRBM_STATUS_SE2));
 583         dev_info(adev->dev, "  GRBM_STATUS_SE3=0x%08X\n",
 584                 RREG32(mmGRBM_STATUS_SE3));
 585         dev_info(adev->dev, "  SRBM_STATUS=0x%08X\n",
 586                 RREG32(mmSRBM_STATUS));
 587         dev_info(adev->dev, "  SRBM_STATUS2=0x%08X\n",
 588                 RREG32(mmSRBM_STATUS2));
 589         dev_info(adev->dev, "  SDMA0_STATUS_REG   = 0x%08X\n",
 590                 RREG32(mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET));
 591         if (adev->sdma.num_instances > 1) {
 592                 dev_info(adev->dev, "  SDMA1_STATUS_REG   = 0x%08X\n",
 593                         RREG32(mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET));
 594         }
 595         dev_info(adev->dev, "  CP_STAT = 0x%08x\n", RREG32(mmCP_STAT));
 596         dev_info(adev->dev, "  CP_STALLED_STAT1 = 0x%08x\n",
 597                  RREG32(mmCP_STALLED_STAT1));
 598         dev_info(adev->dev, "  CP_STALLED_STAT2 = 0x%08x\n",
 599                  RREG32(mmCP_STALLED_STAT2));
 600         dev_info(adev->dev, "  CP_STALLED_STAT3 = 0x%08x\n",
 601                  RREG32(mmCP_STALLED_STAT3));
 602         dev_info(adev->dev, "  CP_CPF_BUSY_STAT = 0x%08x\n",
 603                  RREG32(mmCP_CPF_BUSY_STAT));
 604         dev_info(adev->dev, "  CP_CPF_STALLED_STAT1 = 0x%08x\n",
 605                  RREG32(mmCP_CPF_STALLED_STAT1));
 606         dev_info(adev->dev, "  CP_CPF_STATUS = 0x%08x\n", RREG32(mmCP_CPF_STATUS));
 607         dev_info(adev->dev, "  CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(mmCP_CPC_BUSY_STAT));
 608         dev_info(adev->dev, "  CP_CPC_STALLED_STAT1 = 0x%08x\n",
 609                  RREG32(mmCP_CPC_STALLED_STAT1));
 610         dev_info(adev->dev, "  CP_CPC_STATUS = 0x%08x\n", RREG32(mmCP_CPC_STATUS));
 611 }
 612
 613 /**
 614  * vi_gpu_check_soft_reset - check which blocks are busy
 615  *
 616  * @adev: amdgpu_device pointer
 617  *
 618  * Check which blocks are busy and return the relevant reset
 619  * mask to be used by vi_gpu_soft_reset().
 620  * Returns a mask of the blocks to be reset.
 621  */
 622 u32 vi_gpu_check_soft_reset(struct amdgpu_device *adev)
 623 {
 624         u32 reset_mask = 0;
 625         u32 tmp;
 626
 627         /* GRBM_STATUS */
 628         tmp = RREG32(mmGRBM_STATUS);
 629         if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
 630                    GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
 631                    GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
 632                    GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
 633                    GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
 634                    GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK))
 635                 reset_mask |= AMDGPU_RESET_GFX;
 636
 637         if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK))
 638                 reset_mask |= AMDGPU_RESET_CP;
 639
 640         /* GRBM_STATUS2 */
 641         tmp = RREG32(mmGRBM_STATUS2);
 642         if (tmp & GRBM_STATUS2__RLC_BUSY_MASK)
 643                 reset_mask |= AMDGPU_RESET_RLC;
 644
 645         if (tmp & (GRBM_STATUS2__CPF_BUSY_MASK |
 646                    GRBM_STATUS2__CPC_BUSY_MASK |
 647                    GRBM_STATUS2__CPG_BUSY_MASK))
 648                 reset_mask |= AMDGPU_RESET_CP;
 649
 650         /* SRBM_STATUS2 */
 651         tmp = RREG32(mmSRBM_STATUS2);
 652         if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK)
 653                 reset_mask |= AMDGPU_RESET_DMA;
 654
 655         if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK)
 656                 reset_mask |= AMDGPU_RESET_DMA1;
 657
 658         /* SRBM_STATUS */
 659         tmp = RREG32(mmSRBM_STATUS);
 660
 661         if (tmp & SRBM_STATUS__IH_BUSY_MASK)
 662                 reset_mask |= AMDGPU_RESET_IH;
 663
 664         if (tmp & SRBM_STATUS__SEM_BUSY_MASK)
 665                 reset_mask |= AMDGPU_RESET_SEM;
 666
 667         if (tmp & SRBM_STATUS__GRBM_RQ_PENDING_MASK)
 668                 reset_mask |= AMDGPU_RESET_GRBM;
 669
 670         if (adev->asic_type != CHIP_TOPAZ) {
 671                 if (tmp & (SRBM_STATUS__UVD_RQ_PENDING_MASK |
 672                            SRBM_STATUS__UVD_BUSY_MASK))
 673                         reset_mask |= AMDGPU_RESET_UVD;
 674         }
 675
 676         if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
 677                 reset_mask |= AMDGPU_RESET_VMC;
 678
 679         if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
 680                    SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK))
 681                 reset_mask |= AMDGPU_RESET_MC;
 682
 683         /* SDMA0_STATUS_REG */
 684         tmp = RREG32(mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET);
 685         if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
 686                 reset_mask |= AMDGPU_RESET_DMA;
 687
 688         /* SDMA1_STATUS_REG */
 689         if (adev->sdma.num_instances > 1) {
 690                 tmp = RREG32(mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET);
 691                 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
 692                         reset_mask |= AMDGPU_RESET_DMA1;
 693         }
 694 #if 0
 695         /* VCE_STATUS */
 696         if (adev->asic_type != CHIP_TOPAZ) {
 697                 tmp = RREG32(mmVCE_STATUS);
 698                 if (tmp & VCE_STATUS__VCPU_REPORT_RB0_BUSY_MASK)
 699                         reset_mask |= AMDGPU_RESET_VCE;
 700                 if (tmp & VCE_STATUS__VCPU_REPORT_RB1_BUSY_MASK)
 701                         reset_mask |= AMDGPU_RESET_VCE1;
 702
 703         }
 704
 705         if (adev->asic_type != CHIP_TOPAZ) {
 706                 if (amdgpu_display_is_display_hung(adev))
 707                         reset_mask |= AMDGPU_RESET_DISPLAY;
 708         }
 709 #endif
 710
 711         /* Skip MC reset as it's mostly likely not hung, just busy */
 712         if (reset_mask & AMDGPU_RESET_MC) {
 713                 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);
 714                 reset_mask &= ~AMDGPU_RESET_MC;
 715         }
 716
 717         return reset_mask;
 718 }
 719
 720 /**
 721  * vi_gpu_soft_reset - soft reset GPU
 722  *
 723  * @adev: amdgpu_device pointer
 724  * @reset_mask: mask of which blocks to reset
 725  *
 726  * Soft reset the blocks specified in @reset_mask.
 727  */
 728 static void vi_gpu_soft_reset(struct amdgpu_device *adev, u32 reset_mask)
 729 {
 730         struct amdgpu_mode_mc_save save;
 731         u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
 732         u32 tmp;
 733
 734         if (reset_mask == 0)
 735                 return;
 736
 737         dev_info(adev->dev, "GPU softreset: 0x%08X\n", reset_mask);
 738
 739         vi_print_gpu_status_regs(adev);
 740         dev_info(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
 741                  RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR));
 742         dev_info(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
 743                  RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS));
 744
 745         /* disable CG/PG */
 746
 747         /* stop the rlc */
 748         //XXX
 749         //gfx_v8_0_rlc_stop(adev);
 750
 751         /* Disable GFX parsing/prefetching */
 752         tmp = RREG32(mmCP_ME_CNTL);
 753         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1);
 754         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1);
 755         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1);
 756         WREG32(mmCP_ME_CNTL, tmp);
 757
 758         /* Disable MEC parsing/prefetching */
 759         tmp = RREG32(mmCP_MEC_CNTL);
 760         tmp = REG_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME1_HALT, 1);
 761         tmp = REG_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME2_HALT, 1);
 762         WREG32(mmCP_MEC_CNTL, tmp);
 763
 764         if (reset_mask & AMDGPU_RESET_DMA) {
 765                 /* sdma0 */
 766                 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
 767                 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 1);
 768                 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
 769         }
 770         if (reset_mask & AMDGPU_RESET_DMA1) {
 771                 /* sdma1 */
 772                 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
 773                 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 1);
 774                 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
 775         }
 776
 777         gmc_v8_0_mc_stop(adev, &save);
 778         if (amdgpu_asic_wait_for_mc_idle(adev)) {
 779                 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
 780         }
 781
 782         if (reset_mask & (AMDGPU_RESET_GFX | AMDGPU_RESET_COMPUTE | AMDGPU_RESET_CP)) {
 783                 grbm_soft_reset =
 784                         REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
 785                 grbm_soft_reset =
 786                         REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
 787         }
 788
 789         if (reset_mask & AMDGPU_RESET_CP) {
 790                 grbm_soft_reset =
 791                         REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
 792                 srbm_soft_reset =
 793                         REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
 794         }
 795
 796         if (reset_mask & AMDGPU_RESET_DMA)
 797                 srbm_soft_reset =
 798                         REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA, 1);
 799
 800         if (reset_mask & AMDGPU_RESET_DMA1)
 801                 srbm_soft_reset =
 802                         REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1, 1);
 803
 804         if (reset_mask & AMDGPU_RESET_DISPLAY)
 805                 srbm_soft_reset =
 806                         REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_DC, 1);
 807
 808         if (reset_mask & AMDGPU_RESET_RLC)
 809                 grbm_soft_reset =
 810                         REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
 811
 812         if (reset_mask & AMDGPU_RESET_SEM)
 813                 srbm_soft_reset =
 814                         REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SEM, 1);
 815
 816         if (reset_mask & AMDGPU_RESET_IH)
 817                 srbm_soft_reset =
 818                         REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_IH, 1);
 819
 820         if (reset_mask & AMDGPU_RESET_GRBM)
 821                 srbm_soft_reset =
 822                         REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
 823
 824         if (reset_mask & AMDGPU_RESET_VMC)
 825                 srbm_soft_reset =
 826                         REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
 827
 828         if (reset_mask & AMDGPU_RESET_UVD)
 829                 srbm_soft_reset =
 830                         REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_UVD, 1);
 831
 832         if (reset_mask & AMDGPU_RESET_VCE)
 833                 srbm_soft_reset =
 834                         REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE0, 1);
 835
 836         if (reset_mask & AMDGPU_RESET_VCE)
 837                 srbm_soft_reset =
 838                         REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE1, 1);
 839
 840         if (!(adev->flags & AMD_IS_APU)) {
 841                 if (reset_mask & AMDGPU_RESET_MC)
 842                 srbm_soft_reset =
 843                         REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
 844         }
 845
 846         if (grbm_soft_reset) {
 847                 tmp = RREG32(mmGRBM_SOFT_RESET);
 848                 tmp |= grbm_soft_reset;
 849                 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
 850                 WREG32(mmGRBM_SOFT_RESET, tmp);
 851                 tmp = RREG32(mmGRBM_SOFT_RESET);
 852
 853                 udelay(50);
 854
 855                 tmp &= ~grbm_soft_reset;
 856                 WREG32(mmGRBM_SOFT_RESET, tmp);
 857                 tmp = RREG32(mmGRBM_SOFT_RESET);
 858         }
 859
 860         if (srbm_soft_reset) {
 861                 tmp = RREG32(mmSRBM_SOFT_RESET);
 862                 tmp |= srbm_soft_reset;
 863                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
 864                 WREG32(mmSRBM_SOFT_RESET, tmp);
 865                 tmp = RREG32(mmSRBM_SOFT_RESET);
 866
 867                 udelay(50);
 868
 869                 tmp &= ~srbm_soft_reset;
 870                 WREG32(mmSRBM_SOFT_RESET, tmp);
 871                 tmp = RREG32(mmSRBM_SOFT_RESET);
 872         }
 873
 874         /* Wait a little for things to settle down */
 875         udelay(50);
 876
 877         gmc_v8_0_mc_resume(adev, &save);
 878         udelay(50);
 879
 880         vi_print_gpu_status_regs(adev);
 881 }
 882
 883 static void vi_gpu_pci_config_reset(struct amdgpu_device *adev)
 884 {
 885         struct amdgpu_mode_mc_save save;
 886         u32 tmp, i;
 887
 888         dev_info(adev->dev, "GPU pci config reset\n");
 889
 890         /* disable dpm? */
 891
 892         /* disable cg/pg */
 893
 894         /* Disable GFX parsing/prefetching */
 895         tmp = RREG32(mmCP_ME_CNTL);
 896         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1);
 897         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1);
 898         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1);
 899         WREG32(mmCP_ME_CNTL, tmp);
 900
 901         /* Disable MEC parsing/prefetching */
 902         tmp = RREG32(mmCP_MEC_CNTL);
 903         tmp = REG_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME1_HALT, 1);
 904         tmp = REG_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME2_HALT, 1);
 905         WREG32(mmCP_MEC_CNTL, tmp);
 906
 907         /* Disable GFX parsing/prefetching */
 908         WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK |
 909                 CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK);
 910
 911         /* Disable MEC parsing/prefetching */
 912         WREG32(mmCP_MEC_CNTL,
 913                         CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK);
 914
 915         /* sdma0 */
 916         tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
 917         tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 1);
 918         WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
 919
 920         /* sdma1 */
 921         tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
 922         tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 1);
 923         WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
 924
 925         /* XXX other engines? */
 926
 927         /* halt the rlc, disable cp internal ints */
 928         //XXX
 929         //gfx_v8_0_rlc_stop(adev);
 930
 931         udelay(50);
 932
 933         /* disable mem access */
 934         gmc_v8_0_mc_stop(adev, &save);
 935         if (amdgpu_asic_wait_for_mc_idle(adev)) {
 936                 dev_warn(adev->dev, "Wait for MC idle timed out !\n");
 937         }
 938
 939         /* disable BM */
 940         pci_clear_master(adev->pdev);
 941         /* reset */
 942         amdgpu_pci_config_reset(adev);
 943
 944         udelay(100);
 945
 946         /* wait for asic to come out of reset */
 947         for (i = 0; i < adev->usec_timeout; i++) {
 948                 if (RREG32(mmCONFIG_MEMSIZE) != 0xffffffff)
 949                         break;
 950                 udelay(1);
 951         }
 952
 953 }
 954
 955 static void vi_set_bios_scratch_engine_hung(struct amdgpu_device *adev, bool hung)
 956 {
 957         u32 tmp = RREG32(mmBIOS_SCRATCH_3);
 958
 959         if (hung)
 960                 tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG;
 961         else
 962                 tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG;
 963
 964         WREG32(mmBIOS_SCRATCH_3, tmp);
 965 }
 966
 967 /**
 968  * vi_asic_reset - soft reset GPU
 969  *
 970  * @adev: amdgpu_device pointer
 971  *
 972  * Look up which blocks are hung and attempt
 973  * to reset them.
 974  * Returns 0 for success.
 975  */
 976 static int vi_asic_reset(struct amdgpu_device *adev)
 977 {
 978         u32 reset_mask;
 979
 980         reset_mask = vi_gpu_check_soft_reset(adev);
 981
 982         if (reset_mask)
 983                 vi_set_bios_scratch_engine_hung(adev, true);
 984
 985         /* try soft reset */
 986         vi_gpu_soft_reset(adev, reset_mask);
 987
 988         reset_mask = vi_gpu_check_soft_reset(adev);
 989
 990         /* try pci config reset */
 991         if (reset_mask && amdgpu_hard_reset)
 992                 vi_gpu_pci_config_reset(adev);
 993
 994         reset_mask = vi_gpu_check_soft_reset(adev);
 995
 996         if (!reset_mask)
 997                 vi_set_bios_scratch_engine_hung(adev, false);
 998
 999         return 0;
1000 }
1001
1002 static int vi_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
1003                         u32 cntl_reg, u32 status_reg)
1004 {
1005         int r, i;
1006         struct atom_clock_dividers dividers;
1007         uint32_t tmp;
1008
1009         r = amdgpu_atombios_get_clock_dividers(adev,
1010                                                COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
1011                                                clock, false, &dividers);
1012         if (r)
1013                 return r;
1014
1015         tmp = RREG32_SMC(cntl_reg);
1016         tmp &= ~(CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK |
1017                 CG_DCLK_CNTL__DCLK_DIVIDER_MASK);
1018         tmp |= dividers.post_divider;
1019         WREG32_SMC(cntl_reg, tmp);
1020
1021         for (i = 0; i < 100; i++) {
1022                 if (RREG32_SMC(status_reg) & CG_DCLK_STATUS__DCLK_STATUS_MASK)
1023                         break;
1024                 mdelay(10);
1025         }
1026         if (i == 100)
1027                 return -ETIMEDOUT;
1028
1029         return 0;
1030 }
1031
1032 static int vi_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
1033 {
1034         int r;
1035
1036         r = vi_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
1037         if (r)
1038                 return r;
1039
1040         r = vi_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
1041
1042         return 0;
1043 }
1044
1045 static int vi_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
1046 {
1047         /* todo */
1048
1049         return 0;
1050 }
1051
1052 static void vi_pcie_gen3_enable(struct amdgpu_device *adev)
1053 {
1054         u32 mask;
1055         int ret;
1056
1057         if (pci_is_root_bus(adev->pdev->bus))
1058                 return;
1059
1060         if (amdgpu_pcie_gen2 == 0)
1061                 return;
1062
1063         if (adev->flags & AMD_IS_APU)
1064                 return;
1065
1066         ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
1067         if (ret != 0)
1068                 return;
1069
1070         if (!(mask & (DRM_PCIE_SPEED_50 | DRM_PCIE_SPEED_80)))
1071                 return;
1072
1073         /* todo */
1074 }
1075
1076 static void vi_program_aspm(struct amdgpu_device *adev)
1077 {
1078
1079         if (amdgpu_aspm == 0)
1080                 return;
1081
1082         /* todo */
1083 }
1084
1085 static void vi_enable_doorbell_aperture(struct amdgpu_device *adev,
1086                                         bool enable)
1087 {
1088         u32 tmp;
1089
1090         /* not necessary on CZ */
1091         if (adev->flags & AMD_IS_APU)
1092                 return;
1093
1094         tmp = RREG32(mmBIF_DOORBELL_APER_EN);
1095         if (enable)
1096                 tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 1);
1097         else
1098                 tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 0);
1099
1100         WREG32(mmBIF_DOORBELL_APER_EN, tmp);
1101 }
1102
1103 /* topaz has no DCE, UVD, VCE */
1104 static const struct amdgpu_ip_block_version topaz_ip_blocks[] =
1105 {
1106         /* ORDER MATTERS! */
1107         {
1108                 .type = AMD_IP_BLOCK_TYPE_COMMON,
1109                 .major = 2,
1110                 .minor = 0,
1111                 .rev = 0,
1112                 .funcs = &vi_common_ip_funcs,
1113         },
1114         {
1115                 .type = AMD_IP_BLOCK_TYPE_GMC,
1116                 .major = 8,
1117                 .minor = 0,
1118                 .rev = 0,
1119                 .funcs = &gmc_v8_0_ip_funcs,
1120         },
1121         {
1122                 .type = AMD_IP_BLOCK_TYPE_IH,
1123                 .major = 2,
1124                 .minor = 4,
1125                 .rev = 0,
1126                 .funcs = &iceland_ih_ip_funcs,
1127         },
1128         {
1129                 .type = AMD_IP_BLOCK_TYPE_SMC,
1130                 .major = 7,
1131                 .minor = 1,
1132                 .rev = 0,
1133                 .funcs = &iceland_dpm_ip_funcs,
1134         },
1135         {
1136                 .type = AMD_IP_BLOCK_TYPE_GFX,
1137                 .major = 8,
1138                 .minor = 0,
1139                 .rev = 0,
1140                 .funcs = &gfx_v8_0_ip_funcs,
1141         },
1142         {
1143                 .type = AMD_IP_BLOCK_TYPE_SDMA,
1144                 .major = 2,
1145                 .minor = 4,
1146                 .rev = 0,
1147                 .funcs = &sdma_v2_4_ip_funcs,
1148         },
1149 };
1150
1151 static const struct amdgpu_ip_block_version tonga_ip_blocks[] =
1152 {
1153         /* ORDER MATTERS! */
1154         {
1155                 .type = AMD_IP_BLOCK_TYPE_COMMON,
1156                 .major = 2,
1157                 .minor = 0,
1158                 .rev = 0,
1159                 .funcs = &vi_common_ip_funcs,
1160         },
1161         {
1162                 .type = AMD_IP_BLOCK_TYPE_GMC,
1163                 .major = 8,
1164                 .minor = 0,
1165                 .rev = 0,
1166                 .funcs = &gmc_v8_0_ip_funcs,
1167         },
1168         {
1169                 .type = AMD_IP_BLOCK_TYPE_IH,
1170                 .major = 3,
1171                 .minor = 0,
1172                 .rev = 0,
1173                 .funcs = &tonga_ih_ip_funcs,
1174         },
1175         {
1176                 .type = AMD_IP_BLOCK_TYPE_SMC,
1177                 .major = 7,
1178                 .minor = 1,
1179                 .rev = 0,
1180                 .funcs = &tonga_dpm_ip_funcs,
1181         },
1182         {
1183                 .type = AMD_IP_BLOCK_TYPE_DCE,
1184                 .major = 10,
1185                 .minor = 0,
1186                 .rev = 0,
1187                 .funcs = &dce_v10_0_ip_funcs,
1188         },
1189         {
1190                 .type = AMD_IP_BLOCK_TYPE_GFX,
1191                 .major = 8,
1192                 .minor = 0,
1193                 .rev = 0,
1194                 .funcs = &gfx_v8_0_ip_funcs,
1195         },
1196         {
1197                 .type = AMD_IP_BLOCK_TYPE_SDMA,
1198                 .major = 3,
1199                 .minor = 0,
1200                 .rev = 0,
1201                 .funcs = &sdma_v3_0_ip_funcs,
1202         },
1203         {
1204                 .type = AMD_IP_BLOCK_TYPE_UVD,
1205                 .major = 5,
1206                 .minor = 0,
1207                 .rev = 0,
1208                 .funcs = &uvd_v5_0_ip_funcs,
1209         },
1210         {
1211                 .type = AMD_IP_BLOCK_TYPE_VCE,
1212                 .major = 3,
1213                 .minor = 0,
1214                 .rev = 0,
1215                 .funcs = &vce_v3_0_ip_funcs,
1216         },
1217 };
1218
1219 static const struct amdgpu_ip_block_version fiji_ip_blocks[] =
1220 {
1221         /* ORDER MATTERS! */
1222         {
1223                 .type = AMD_IP_BLOCK_TYPE_COMMON,
1224                 .major = 2,
1225                 .minor = 0,
1226                 .rev = 0,
1227                 .funcs = &vi_common_ip_funcs,
1228         },
1229         {
1230                 .type = AMD_IP_BLOCK_TYPE_GMC,
1231                 .major = 8,
1232                 .minor = 5,
1233                 .rev = 0,
1234                 .funcs = &gmc_v8_0_ip_funcs,
1235         },
1236         {
1237                 .type = AMD_IP_BLOCK_TYPE_IH,
1238                 .major = 3,
1239                 .minor = 0,
1240                 .rev = 0,
1241                 .funcs = &tonga_ih_ip_funcs,
1242         },
1243         {
1244                 .type = AMD_IP_BLOCK_TYPE_SMC,
1245                 .major = 7,
1246                 .minor = 1,
1247                 .rev = 0,
1248                 .funcs = &fiji_dpm_ip_funcs,
1249         },
1250         {
1251                 .type = AMD_IP_BLOCK_TYPE_DCE,
1252                 .major = 10,
1253                 .minor = 1,
1254                 .rev = 0,
1255                 .funcs = &dce_v10_0_ip_funcs,
1256         },
1257         {
1258                 .type = AMD_IP_BLOCK_TYPE_GFX,
1259                 .major = 8,
1260                 .minor = 0,
1261                 .rev = 0,
1262                 .funcs = &gfx_v8_0_ip_funcs,
1263         },
1264         {
1265                 .type = AMD_IP_BLOCK_TYPE_SDMA,
1266                 .major = 3,
1267                 .minor = 0,
1268                 .rev = 0,
1269                 .funcs = &sdma_v3_0_ip_funcs,
1270         },
1271         {
1272                 .type = AMD_IP_BLOCK_TYPE_UVD,
1273                 .major = 6,
1274                 .minor = 0,
1275                 .rev = 0,
1276                 .funcs = &uvd_v6_0_ip_funcs,
1277         },
1278         {
1279                 .type = AMD_IP_BLOCK_TYPE_VCE,
1280                 .major = 3,
1281                 .minor = 0,
1282                 .rev = 0,
1283                 .funcs = &vce_v3_0_ip_funcs,
1284         },
1285 };
1286
1287 static const struct amdgpu_ip_block_version cz_ip_blocks[] =
1288 {
1289         /* ORDER MATTERS! */
1290         {
1291                 .type = AMD_IP_BLOCK_TYPE_COMMON,
1292                 .major = 2,
1293                 .minor = 0,
1294                 .rev = 0,
1295                 .funcs = &vi_common_ip_funcs,
1296         },
1297         {
1298                 .type = AMD_IP_BLOCK_TYPE_GMC,
1299                 .major = 8,
1300                 .minor = 0,
1301                 .rev = 0,
1302                 .funcs = &gmc_v8_0_ip_funcs,
1303         },
1304         {
1305                 .type = AMD_IP_BLOCK_TYPE_IH,
1306                 .major = 3,
1307                 .minor = 0,
1308                 .rev = 0,
1309                 .funcs = &cz_ih_ip_funcs,
1310         },
1311         {
1312                 .type = AMD_IP_BLOCK_TYPE_SMC,
1313                 .major = 8,
1314                 .minor = 0,
1315                 .rev = 0,
1316                 .funcs = &cz_dpm_ip_funcs,
1317         },
1318         {
1319                 .type = AMD_IP_BLOCK_TYPE_DCE,
1320                 .major = 11,
1321                 .minor = 0,
1322                 .rev = 0,
1323                 .funcs = &dce_v11_0_ip_funcs,
1324         },
1325         {
1326                 .type = AMD_IP_BLOCK_TYPE_GFX,
1327                 .major = 8,
1328                 .minor = 0,
1329                 .rev = 0,
1330                 .funcs = &gfx_v8_0_ip_funcs,
1331         },
1332         {
1333                 .type = AMD_IP_BLOCK_TYPE_SDMA,
1334                 .major = 3,
1335                 .minor = 0,
1336                 .rev = 0,
1337                 .funcs = &sdma_v3_0_ip_funcs,
1338         },
1339         {
1340                 .type = AMD_IP_BLOCK_TYPE_UVD,
1341                 .major = 6,
1342                 .minor = 0,
1343                 .rev = 0,
1344                 .funcs = &uvd_v6_0_ip_funcs,
1345         },
1346         {
1347                 .type = AMD_IP_BLOCK_TYPE_VCE,
1348                 .major = 3,
1349                 .minor = 0,
1350                 .rev = 0,
1351                 .funcs = &vce_v3_0_ip_funcs,
1352         },
1353 };
1354
1355 int vi_set_ip_blocks(struct amdgpu_device *adev)
1356 {
1357         switch (adev->asic_type) {
1358         case CHIP_TOPAZ:
1359                 adev->ip_blocks = topaz_ip_blocks;
1360                 adev->num_ip_blocks = ARRAY_SIZE(topaz_ip_blocks);
1361                 break;
1362         case CHIP_FIJI:
1363                 adev->ip_blocks = fiji_ip_blocks;
1364                 adev->num_ip_blocks = ARRAY_SIZE(fiji_ip_blocks);
1365                 break;
1366         case CHIP_TONGA:
1367                 adev->ip_blocks = tonga_ip_blocks;
1368                 adev->num_ip_blocks = ARRAY_SIZE(tonga_ip_blocks);
1369                 break;
1370         case CHIP_CARRIZO:
1371         case CHIP_STONEY:
1372                 adev->ip_blocks = cz_ip_blocks;
1373                 adev->num_ip_blocks = ARRAY_SIZE(cz_ip_blocks);
1374                 break;
1375         default:
1376                 /* FIXME: not supported yet */
1377                 return -EINVAL;
1378         }
1379
1380         return 0;
1381 }
1382
1383 #define ATI_REV_ID_FUSE_MACRO__ADDRESS      0xC0014044
1384 #define ATI_REV_ID_FUSE_MACRO__SHIFT        9
1385 #define ATI_REV_ID_FUSE_MACRO__MASK         0x00001E00
1386
1387 static uint32_t vi_get_rev_id(struct amdgpu_device *adev)
1388 {
1389         if (adev->asic_type == CHIP_TOPAZ)
1390                 return (RREG32(mmPCIE_EFUSE4) & PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID_MASK)
1391                         >> PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID__SHIFT;
1392         else if (adev->flags & AMD_IS_APU)
1393                 return (RREG32_SMC(ATI_REV_ID_FUSE_MACRO__ADDRESS) & ATI_REV_ID_FUSE_MACRO__MASK)
1394                         >> ATI_REV_ID_FUSE_MACRO__SHIFT;
1395         else
1396                 return (RREG32(mmCC_DRM_ID_STRAPS) & CC_DRM_ID_STRAPS__ATI_REV_ID_MASK)
1397                         >> CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT;
1398 }
1399
1400 static const struct amdgpu_asic_funcs vi_asic_funcs =
1401 {
1402         .read_disabled_bios = &vi_read_disabled_bios,
1403         .read_bios_from_rom = &vi_read_bios_from_rom,
1404         .read_register = &vi_read_register,
1405         .reset = &vi_asic_reset,
1406         .set_vga_state = &vi_vga_set_state,
1407         .get_xclk = &vi_get_xclk,
1408         .set_uvd_clocks = &vi_set_uvd_clocks,
1409         .set_vce_clocks = &vi_set_vce_clocks,
1410         .get_cu_info = &gfx_v8_0_get_cu_info,
1411         /* these should be moved to their own ip modules */
1412         .get_gpu_clock_counter = &gfx_v8_0_get_gpu_clock_counter,
1413         .wait_for_mc_idle = &gmc_v8_0_mc_wait_for_idle,
1414 };
1415
1416 static int vi_common_early_init(void *handle)
1417 {
1418         bool smc_enabled = false;
1419         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1420
1421         if (adev->flags & AMD_IS_APU) {
1422                 adev->smc_rreg = &cz_smc_rreg;
1423                 adev->smc_wreg = &cz_smc_wreg;
1424         } else {
1425                 adev->smc_rreg = &vi_smc_rreg;
1426                 adev->smc_wreg = &vi_smc_wreg;
1427         }
1428         adev->pcie_rreg = &vi_pcie_rreg;
1429         adev->pcie_wreg = &vi_pcie_wreg;
1430         adev->uvd_ctx_rreg = &vi_uvd_ctx_rreg;
1431         adev->uvd_ctx_wreg = &vi_uvd_ctx_wreg;
1432         adev->didt_rreg = &vi_didt_rreg;
1433         adev->didt_wreg = &vi_didt_wreg;
1434
1435         adev->asic_funcs = &vi_asic_funcs;
1436
1437         if (amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_SMC) &&
1438                 (amdgpu_ip_block_mask & (1 << AMD_IP_BLOCK_TYPE_SMC)))
1439                 smc_enabled = true;
1440
1441         adev->rev_id = vi_get_rev_id(adev);
1442         adev->external_rev_id = 0xFF;
1443         switch (adev->asic_type) {
1444         case CHIP_TOPAZ:
1445                 adev->has_uvd = false;
1446                 adev->cg_flags = 0;
1447                 adev->pg_flags = 0;
1448                 adev->external_rev_id = 0x1;
1449                 break;
1450         case CHIP_FIJI:
1451                 adev->has_uvd = true;
1452                 adev->cg_flags = 0;
1453                 adev->pg_flags = 0;
1454                 adev->external_rev_id = adev->rev_id + 0x3c;
1455                 break;
1456         case CHIP_TONGA:
1457                 adev->has_uvd = true;
1458                 adev->cg_flags = 0;
1459                 adev->pg_flags = 0;
1460                 adev->external_rev_id = adev->rev_id + 0x14;
1461                 break;
1462         case CHIP_CARRIZO:
1463         case CHIP_STONEY:
1464                 adev->has_uvd = true;
1465                 adev->cg_flags = 0;
1466                 /* Disable UVD pg */
1467                 adev->pg_flags = /* AMDGPU_PG_SUPPORT_UVD | */AMDGPU_PG_SUPPORT_VCE;
1468                 adev->external_rev_id = adev->rev_id + 0x1;
1469                 break;
1470         default:
1471                 /* FIXME: not supported yet */
1472                 return -EINVAL;
1473         }
1474
1475         if (amdgpu_smc_load_fw && smc_enabled)
1476                 adev->firmware.smu_load = true;
1477
1478         return 0;
1479 }
1480
1481 static int vi_common_sw_init(void *handle)
1482 {
1483         return 0;
1484 }
1485
1486 static int vi_common_sw_fini(void *handle)
1487 {
1488         return 0;
1489 }
1490
1491 static int vi_common_hw_init(void *handle)
1492 {
1493         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1494
1495         /* move the golden regs per IP block */
1496         vi_init_golden_registers(adev);
1497         /* enable pcie gen2/3 link */
1498         vi_pcie_gen3_enable(adev);
1499         /* enable aspm */
1500         vi_program_aspm(adev);
1501         /* enable the doorbell aperture */
1502         vi_enable_doorbell_aperture(adev, true);
1503
1504         return 0;
1505 }
1506
1507 static int vi_common_hw_fini(void *handle)
1508 {
1509         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1510
1511         /* enable the doorbell aperture */
1512         vi_enable_doorbell_aperture(adev, false);
1513
1514         return 0;
1515 }
1516
1517 static int vi_common_suspend(void *handle)
1518 {
1519         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1520
1521         return vi_common_hw_fini(adev);
1522 }
1523
1524 static int vi_common_resume(void *handle)
1525 {
1526         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1527
1528         return vi_common_hw_init(adev);
1529 }
1530
1531 static bool vi_common_is_idle(void *handle)
1532 {
1533         return true;
1534 }
1535
1536 static int vi_common_wait_for_idle(void *handle)
1537 {
1538         return 0;
1539 }
1540
1541 static void vi_common_print_status(void *handle)
1542 {
1543         return;
1544 }
1545
1546 static int vi_common_soft_reset(void *handle)
1547 {
1548         return 0;
1549 }
1550
1551 static int vi_common_set_clockgating_state(void *handle,
1552                                             enum amd_clockgating_state state)
1553 {
1554         return 0;
1555 }
1556
1557 static int vi_common_set_powergating_state(void *handle,
1558                                             enum amd_powergating_state state)
1559 {
1560         return 0;
1561 }
1562
1563 const struct amd_ip_funcs vi_common_ip_funcs = {
1564         .early_init = vi_common_early_init,
1565         .late_init = NULL,
1566         .sw_init = vi_common_sw_init,
1567         .sw_fini = vi_common_sw_fini,
1568         .hw_init = vi_common_hw_init,
1569         .hw_fini = vi_common_hw_fini,
1570         .suspend = vi_common_suspend,
1571         .resume = vi_common_resume,
1572         .is_idle = vi_common_is_idle,
1573         .wait_for_idle = vi_common_wait_for_idle,
1574         .soft_reset = vi_common_soft_reset,
1575         .print_status = vi_common_print_status,
1576         .set_clockgating_state = vi_common_set_clockgating_state,
1577         .set_powergating_state = vi_common_set_powergating_state,
1578 };
1579