2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/firmware.h>
24 #include <linux/slab.h>
25 #include <linux/module.h>
28 #include "amdgpu_atombios.h"
29 #include "amdgpu_ih.h"
30 #include "amdgpu_uvd.h"
31 #include "amdgpu_vce.h"
32 #include "amdgpu_ucode.h"
36 #include "gmc/gmc_8_1_d.h"
37 #include "gmc/gmc_8_1_sh_mask.h"
39 #include "oss/oss_3_0_d.h"
40 #include "oss/oss_3_0_sh_mask.h"
42 #include "bif/bif_5_0_d.h"
43 #include "bif/bif_5_0_sh_mask.h"
45 #include "gca/gfx_8_0_d.h"
46 #include "gca/gfx_8_0_sh_mask.h"
48 #include "smu/smu_7_1_1_d.h"
49 #include "smu/smu_7_1_1_sh_mask.h"
51 #include "uvd/uvd_5_0_d.h"
52 #include "uvd/uvd_5_0_sh_mask.h"
54 #include "vce/vce_3_0_d.h"
55 #include "vce/vce_3_0_sh_mask.h"
57 #include "dce/dce_10_0_d.h"
58 #include "dce/dce_10_0_sh_mask.h"
65 #include "sdma_v2_4.h"
66 #include "sdma_v3_0.h"
67 #include "dce_v10_0.h"
68 #include "dce_v11_0.h"
69 #include "iceland_ih.h"
75 #include "amdgpu_powerplay.h"
78 * Indirect registers accessor
80 static u32 vi_pcie_rreg(struct amdgpu_device *adev, u32 reg)
85 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
86 WREG32(mmPCIE_INDEX, reg);
87 (void)RREG32(mmPCIE_INDEX);
88 r = RREG32(mmPCIE_DATA);
89 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
93 static void vi_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
97 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
98 WREG32(mmPCIE_INDEX, reg);
99 (void)RREG32(mmPCIE_INDEX);
100 WREG32(mmPCIE_DATA, v);
101 (void)RREG32(mmPCIE_DATA);
102 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
105 static u32 vi_smc_rreg(struct amdgpu_device *adev, u32 reg)
110 spin_lock_irqsave(&adev->smc_idx_lock, flags);
111 WREG32(mmSMC_IND_INDEX_0, (reg));
112 r = RREG32(mmSMC_IND_DATA_0);
113 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
117 static void vi_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
121 spin_lock_irqsave(&adev->smc_idx_lock, flags);
122 WREG32(mmSMC_IND_INDEX_0, (reg));
123 WREG32(mmSMC_IND_DATA_0, (v));
124 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
128 #define mmMP0PUB_IND_INDEX 0x180
129 #define mmMP0PUB_IND_DATA 0x181
131 static u32 cz_smc_rreg(struct amdgpu_device *adev, u32 reg)
136 spin_lock_irqsave(&adev->smc_idx_lock, flags);
137 WREG32(mmMP0PUB_IND_INDEX, (reg));
138 r = RREG32(mmMP0PUB_IND_DATA);
139 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
143 static void cz_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
147 spin_lock_irqsave(&adev->smc_idx_lock, flags);
148 WREG32(mmMP0PUB_IND_INDEX, (reg));
149 WREG32(mmMP0PUB_IND_DATA, (v));
150 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
153 static u32 vi_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
158 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
159 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
160 r = RREG32(mmUVD_CTX_DATA);
161 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
165 static void vi_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
169 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
170 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
171 WREG32(mmUVD_CTX_DATA, (v));
172 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
175 static u32 vi_didt_rreg(struct amdgpu_device *adev, u32 reg)
180 spin_lock_irqsave(&adev->didt_idx_lock, flags);
181 WREG32(mmDIDT_IND_INDEX, (reg));
182 r = RREG32(mmDIDT_IND_DATA);
183 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
187 static void vi_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
191 spin_lock_irqsave(&adev->didt_idx_lock, flags);
192 WREG32(mmDIDT_IND_INDEX, (reg));
193 WREG32(mmDIDT_IND_DATA, (v));
194 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
197 static const u32 tonga_mgcg_cgcg_init[] =
199 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
200 mmPCIE_INDEX, 0xffffffff, 0x0140001c,
201 mmPCIE_DATA, 0x000f0000, 0x00000000,
202 mmSMC_IND_INDEX_4, 0xffffffff, 0xC060000C,
203 mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100,
204 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
205 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
208 static const u32 fiji_mgcg_cgcg_init[] =
210 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
211 mmPCIE_INDEX, 0xffffffff, 0x0140001c,
212 mmPCIE_DATA, 0x000f0000, 0x00000000,
213 mmSMC_IND_INDEX_4, 0xffffffff, 0xC060000C,
214 mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100,
215 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
216 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
219 static const u32 iceland_mgcg_cgcg_init[] =
221 mmPCIE_INDEX, 0xffffffff, ixPCIE_CNTL2,
222 mmPCIE_DATA, 0x000f0000, 0x00000000,
223 mmSMC_IND_INDEX_4, 0xffffffff, ixCGTT_ROM_CLK_CTRL0,
224 mmSMC_IND_DATA_4, 0xc0000fff, 0x00000100,
225 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
228 static const u32 cz_mgcg_cgcg_init[] =
230 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
231 mmPCIE_INDEX, 0xffffffff, 0x0140001c,
232 mmPCIE_DATA, 0x000f0000, 0x00000000,
233 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
234 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
237 static const u32 stoney_mgcg_cgcg_init[] =
239 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00000100,
240 mmHDP_XDP_CGTT_BLK_CTRL, 0xffffffff, 0x00000104,
241 mmHDP_HOST_PATH_CNTL, 0xffffffff, 0x0f000027,
244 static void vi_init_golden_registers(struct amdgpu_device *adev)
246 /* Some of the registers might be dependent on GRBM_GFX_INDEX */
247 mutex_lock(&adev->grbm_idx_mutex);
249 switch (adev->asic_type) {
251 amdgpu_program_register_sequence(adev,
252 iceland_mgcg_cgcg_init,
253 (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
256 amdgpu_program_register_sequence(adev,
258 (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
261 amdgpu_program_register_sequence(adev,
262 tonga_mgcg_cgcg_init,
263 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
266 amdgpu_program_register_sequence(adev,
268 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
271 amdgpu_program_register_sequence(adev,
272 stoney_mgcg_cgcg_init,
273 (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
278 mutex_unlock(&adev->grbm_idx_mutex);
282 * vi_get_xclk - get the xclk
284 * @adev: amdgpu_device pointer
286 * Returns the reference clock used by the gfx engine
289 static u32 vi_get_xclk(struct amdgpu_device *adev)
291 u32 reference_clock = adev->clock.spll.reference_freq;
294 if (adev->flags & AMD_IS_APU)
295 return reference_clock;
297 tmp = RREG32_SMC(ixCG_CLKPIN_CNTL_2);
298 if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK))
301 tmp = RREG32_SMC(ixCG_CLKPIN_CNTL);
302 if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL, XTALIN_DIVIDE))
303 return reference_clock / 4;
305 return reference_clock;
309 * vi_srbm_select - select specific register instances
311 * @adev: amdgpu_device pointer
312 * @me: selected ME (micro engine)
317 * Switches the currently active registers instances. Some
318 * registers are instanced per VMID, others are instanced per
319 * me/pipe/queue combination.
321 void vi_srbm_select(struct amdgpu_device *adev,
322 u32 me, u32 pipe, u32 queue, u32 vmid)
324 u32 srbm_gfx_cntl = 0;
325 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, PIPEID, pipe);
326 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, MEID, me);
327 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, vmid);
328 srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, QUEUEID, queue);
329 WREG32(mmSRBM_GFX_CNTL, srbm_gfx_cntl);
332 static void vi_vga_set_state(struct amdgpu_device *adev, bool state)
337 static bool vi_read_disabled_bios(struct amdgpu_device *adev)
340 u32 d1vga_control = 0;
341 u32 d2vga_control = 0;
342 u32 vga_render_control = 0;
346 bus_cntl = RREG32(mmBUS_CNTL);
347 if (adev->mode_info.num_crtc) {
348 d1vga_control = RREG32(mmD1VGA_CONTROL);
349 d2vga_control = RREG32(mmD2VGA_CONTROL);
350 vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
352 rom_cntl = RREG32_SMC(ixROM_CNTL);
355 WREG32(mmBUS_CNTL, (bus_cntl & ~BUS_CNTL__BIOS_ROM_DIS_MASK));
356 if (adev->mode_info.num_crtc) {
357 /* Disable VGA mode */
358 WREG32(mmD1VGA_CONTROL,
359 (d1vga_control & ~(D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK |
360 D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK)));
361 WREG32(mmD2VGA_CONTROL,
362 (d2vga_control & ~(D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK |
363 D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK)));
364 WREG32(mmVGA_RENDER_CONTROL,
365 (vga_render_control & ~VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK));
367 WREG32_SMC(ixROM_CNTL, rom_cntl | ROM_CNTL__SCK_OVERWRITE_MASK);
369 r = amdgpu_read_bios(adev);
372 WREG32(mmBUS_CNTL, bus_cntl);
373 if (adev->mode_info.num_crtc) {
374 WREG32(mmD1VGA_CONTROL, d1vga_control);
375 WREG32(mmD2VGA_CONTROL, d2vga_control);
376 WREG32(mmVGA_RENDER_CONTROL, vga_render_control);
378 WREG32_SMC(ixROM_CNTL, rom_cntl);
382 static bool vi_read_bios_from_rom(struct amdgpu_device *adev,
383 u8 *bios, u32 length_bytes)
391 if (length_bytes == 0)
393 /* APU vbios image is part of sbios image */
394 if (adev->flags & AMD_IS_APU)
397 dw_ptr = (u32 *)bios;
398 length_dw = ALIGN(length_bytes, 4) / 4;
399 /* take the smc lock since we are using the smc index */
400 spin_lock_irqsave(&adev->smc_idx_lock, flags);
401 /* set rom index to 0 */
402 WREG32(mmSMC_IND_INDEX_0, ixROM_INDEX);
403 WREG32(mmSMC_IND_DATA_0, 0);
404 /* set index to data for continous read */
405 WREG32(mmSMC_IND_INDEX_0, ixROM_DATA);
406 for (i = 0; i < length_dw; i++)
407 dw_ptr[i] = RREG32(mmSMC_IND_DATA_0);
408 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
413 static struct amdgpu_allowed_register_entry tonga_allowed_read_registers[] = {
414 {mmGB_MACROTILE_MODE7, true},
417 static struct amdgpu_allowed_register_entry cz_allowed_read_registers[] = {
418 {mmGB_TILE_MODE7, true},
419 {mmGB_TILE_MODE12, true},
420 {mmGB_TILE_MODE17, true},
421 {mmGB_TILE_MODE23, true},
422 {mmGB_MACROTILE_MODE7, true},
425 static struct amdgpu_allowed_register_entry vi_allowed_read_registers[] = {
426 {mmGRBM_STATUS, false},
427 {mmGRBM_STATUS2, false},
428 {mmGRBM_STATUS_SE0, false},
429 {mmGRBM_STATUS_SE1, false},
430 {mmGRBM_STATUS_SE2, false},
431 {mmGRBM_STATUS_SE3, false},
432 {mmSRBM_STATUS, false},
433 {mmSRBM_STATUS2, false},
434 {mmSRBM_STATUS3, false},
435 {mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET, false},
436 {mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET, false},
438 {mmCP_STALLED_STAT1, false},
439 {mmCP_STALLED_STAT2, false},
440 {mmCP_STALLED_STAT3, false},
441 {mmCP_CPF_BUSY_STAT, false},
442 {mmCP_CPF_STALLED_STAT1, false},
443 {mmCP_CPF_STATUS, false},
444 {mmCP_CPC_BUSY_STAT, false},
445 {mmCP_CPC_STALLED_STAT1, false},
446 {mmCP_CPC_STATUS, false},
447 {mmGB_ADDR_CONFIG, false},
448 {mmMC_ARB_RAMCFG, false},
449 {mmGB_TILE_MODE0, false},
450 {mmGB_TILE_MODE1, false},
451 {mmGB_TILE_MODE2, false},
452 {mmGB_TILE_MODE3, false},
453 {mmGB_TILE_MODE4, false},
454 {mmGB_TILE_MODE5, false},
455 {mmGB_TILE_MODE6, false},
456 {mmGB_TILE_MODE7, false},
457 {mmGB_TILE_MODE8, false},
458 {mmGB_TILE_MODE9, false},
459 {mmGB_TILE_MODE10, false},
460 {mmGB_TILE_MODE11, false},
461 {mmGB_TILE_MODE12, false},
462 {mmGB_TILE_MODE13, false},
463 {mmGB_TILE_MODE14, false},
464 {mmGB_TILE_MODE15, false},
465 {mmGB_TILE_MODE16, false},
466 {mmGB_TILE_MODE17, false},
467 {mmGB_TILE_MODE18, false},
468 {mmGB_TILE_MODE19, false},
469 {mmGB_TILE_MODE20, false},
470 {mmGB_TILE_MODE21, false},
471 {mmGB_TILE_MODE22, false},
472 {mmGB_TILE_MODE23, false},
473 {mmGB_TILE_MODE24, false},
474 {mmGB_TILE_MODE25, false},
475 {mmGB_TILE_MODE26, false},
476 {mmGB_TILE_MODE27, false},
477 {mmGB_TILE_MODE28, false},
478 {mmGB_TILE_MODE29, false},
479 {mmGB_TILE_MODE30, false},
480 {mmGB_TILE_MODE31, false},
481 {mmGB_MACROTILE_MODE0, false},
482 {mmGB_MACROTILE_MODE1, false},
483 {mmGB_MACROTILE_MODE2, false},
484 {mmGB_MACROTILE_MODE3, false},
485 {mmGB_MACROTILE_MODE4, false},
486 {mmGB_MACROTILE_MODE5, false},
487 {mmGB_MACROTILE_MODE6, false},
488 {mmGB_MACROTILE_MODE7, false},
489 {mmGB_MACROTILE_MODE8, false},
490 {mmGB_MACROTILE_MODE9, false},
491 {mmGB_MACROTILE_MODE10, false},
492 {mmGB_MACROTILE_MODE11, false},
493 {mmGB_MACROTILE_MODE12, false},
494 {mmGB_MACROTILE_MODE13, false},
495 {mmGB_MACROTILE_MODE14, false},
496 {mmGB_MACROTILE_MODE15, false},
497 {mmCC_RB_BACKEND_DISABLE, false, true},
498 {mmGC_USER_RB_BACKEND_DISABLE, false, true},
499 {mmGB_BACKEND_MAP, false, false},
500 {mmPA_SC_RASTER_CONFIG, false, true},
501 {mmPA_SC_RASTER_CONFIG_1, false, true},
504 static uint32_t vi_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
505 u32 sh_num, u32 reg_offset)
509 mutex_lock(&adev->grbm_idx_mutex);
510 if (se_num != 0xffffffff || sh_num != 0xffffffff)
511 gfx_v8_0_select_se_sh(adev, se_num, sh_num);
513 val = RREG32(reg_offset);
515 if (se_num != 0xffffffff || sh_num != 0xffffffff)
516 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
517 mutex_unlock(&adev->grbm_idx_mutex);
521 static int vi_read_register(struct amdgpu_device *adev, u32 se_num,
522 u32 sh_num, u32 reg_offset, u32 *value)
524 struct amdgpu_allowed_register_entry *asic_register_table = NULL;
525 struct amdgpu_allowed_register_entry *asic_register_entry;
529 switch (adev->asic_type) {
531 asic_register_table = tonga_allowed_read_registers;
532 size = ARRAY_SIZE(tonga_allowed_read_registers);
538 asic_register_table = cz_allowed_read_registers;
539 size = ARRAY_SIZE(cz_allowed_read_registers);
545 if (asic_register_table) {
546 for (i = 0; i < size; i++) {
547 asic_register_entry = asic_register_table + i;
548 if (reg_offset != asic_register_entry->reg_offset)
550 if (!asic_register_entry->untouched)
551 *value = asic_register_entry->grbm_indexed ?
552 vi_read_indexed_register(adev, se_num,
553 sh_num, reg_offset) :
559 for (i = 0; i < ARRAY_SIZE(vi_allowed_read_registers); i++) {
560 if (reg_offset != vi_allowed_read_registers[i].reg_offset)
563 if (!vi_allowed_read_registers[i].untouched)
564 *value = vi_allowed_read_registers[i].grbm_indexed ?
565 vi_read_indexed_register(adev, se_num,
566 sh_num, reg_offset) :
573 static void vi_print_gpu_status_regs(struct amdgpu_device *adev)
575 dev_info(adev->dev, " GRBM_STATUS=0x%08X\n",
576 RREG32(mmGRBM_STATUS));
577 dev_info(adev->dev, " GRBM_STATUS2=0x%08X\n",
578 RREG32(mmGRBM_STATUS2));
579 dev_info(adev->dev, " GRBM_STATUS_SE0=0x%08X\n",
580 RREG32(mmGRBM_STATUS_SE0));
581 dev_info(adev->dev, " GRBM_STATUS_SE1=0x%08X\n",
582 RREG32(mmGRBM_STATUS_SE1));
583 dev_info(adev->dev, " GRBM_STATUS_SE2=0x%08X\n",
584 RREG32(mmGRBM_STATUS_SE2));
585 dev_info(adev->dev, " GRBM_STATUS_SE3=0x%08X\n",
586 RREG32(mmGRBM_STATUS_SE3));
587 dev_info(adev->dev, " SRBM_STATUS=0x%08X\n",
588 RREG32(mmSRBM_STATUS));
589 dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n",
590 RREG32(mmSRBM_STATUS2));
591 dev_info(adev->dev, " SDMA0_STATUS_REG = 0x%08X\n",
592 RREG32(mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET));
593 if (adev->sdma.num_instances > 1) {
594 dev_info(adev->dev, " SDMA1_STATUS_REG = 0x%08X\n",
595 RREG32(mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET));
597 dev_info(adev->dev, " CP_STAT = 0x%08x\n", RREG32(mmCP_STAT));
598 dev_info(adev->dev, " CP_STALLED_STAT1 = 0x%08x\n",
599 RREG32(mmCP_STALLED_STAT1));
600 dev_info(adev->dev, " CP_STALLED_STAT2 = 0x%08x\n",
601 RREG32(mmCP_STALLED_STAT2));
602 dev_info(adev->dev, " CP_STALLED_STAT3 = 0x%08x\n",
603 RREG32(mmCP_STALLED_STAT3));
604 dev_info(adev->dev, " CP_CPF_BUSY_STAT = 0x%08x\n",
605 RREG32(mmCP_CPF_BUSY_STAT));
606 dev_info(adev->dev, " CP_CPF_STALLED_STAT1 = 0x%08x\n",
607 RREG32(mmCP_CPF_STALLED_STAT1));
608 dev_info(adev->dev, " CP_CPF_STATUS = 0x%08x\n", RREG32(mmCP_CPF_STATUS));
609 dev_info(adev->dev, " CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(mmCP_CPC_BUSY_STAT));
610 dev_info(adev->dev, " CP_CPC_STALLED_STAT1 = 0x%08x\n",
611 RREG32(mmCP_CPC_STALLED_STAT1));
612 dev_info(adev->dev, " CP_CPC_STATUS = 0x%08x\n", RREG32(mmCP_CPC_STATUS));
616 * vi_gpu_check_soft_reset - check which blocks are busy
618 * @adev: amdgpu_device pointer
620 * Check which blocks are busy and return the relevant reset
621 * mask to be used by vi_gpu_soft_reset().
622 * Returns a mask of the blocks to be reset.
624 u32 vi_gpu_check_soft_reset(struct amdgpu_device *adev)
630 tmp = RREG32(mmGRBM_STATUS);
631 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
632 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
633 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
634 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
635 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
636 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK))
637 reset_mask |= AMDGPU_RESET_GFX;
639 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK))
640 reset_mask |= AMDGPU_RESET_CP;
643 tmp = RREG32(mmGRBM_STATUS2);
644 if (tmp & GRBM_STATUS2__RLC_BUSY_MASK)
645 reset_mask |= AMDGPU_RESET_RLC;
647 if (tmp & (GRBM_STATUS2__CPF_BUSY_MASK |
648 GRBM_STATUS2__CPC_BUSY_MASK |
649 GRBM_STATUS2__CPG_BUSY_MASK))
650 reset_mask |= AMDGPU_RESET_CP;
653 tmp = RREG32(mmSRBM_STATUS2);
654 if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK)
655 reset_mask |= AMDGPU_RESET_DMA;
657 if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK)
658 reset_mask |= AMDGPU_RESET_DMA1;
661 tmp = RREG32(mmSRBM_STATUS);
663 if (tmp & SRBM_STATUS__IH_BUSY_MASK)
664 reset_mask |= AMDGPU_RESET_IH;
666 if (tmp & SRBM_STATUS__SEM_BUSY_MASK)
667 reset_mask |= AMDGPU_RESET_SEM;
669 if (tmp & SRBM_STATUS__GRBM_RQ_PENDING_MASK)
670 reset_mask |= AMDGPU_RESET_GRBM;
672 if (adev->asic_type != CHIP_TOPAZ) {
673 if (tmp & (SRBM_STATUS__UVD_RQ_PENDING_MASK |
674 SRBM_STATUS__UVD_BUSY_MASK))
675 reset_mask |= AMDGPU_RESET_UVD;
678 if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
679 reset_mask |= AMDGPU_RESET_VMC;
681 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
682 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK))
683 reset_mask |= AMDGPU_RESET_MC;
685 /* SDMA0_STATUS_REG */
686 tmp = RREG32(mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET);
687 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
688 reset_mask |= AMDGPU_RESET_DMA;
690 /* SDMA1_STATUS_REG */
691 if (adev->sdma.num_instances > 1) {
692 tmp = RREG32(mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET);
693 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
694 reset_mask |= AMDGPU_RESET_DMA1;
698 if (adev->asic_type != CHIP_TOPAZ) {
699 tmp = RREG32(mmVCE_STATUS);
700 if (tmp & VCE_STATUS__VCPU_REPORT_RB0_BUSY_MASK)
701 reset_mask |= AMDGPU_RESET_VCE;
702 if (tmp & VCE_STATUS__VCPU_REPORT_RB1_BUSY_MASK)
703 reset_mask |= AMDGPU_RESET_VCE1;
707 if (adev->asic_type != CHIP_TOPAZ) {
708 if (amdgpu_display_is_display_hung(adev))
709 reset_mask |= AMDGPU_RESET_DISPLAY;
713 /* Skip MC reset as it's mostly likely not hung, just busy */
714 if (reset_mask & AMDGPU_RESET_MC) {
715 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);
716 reset_mask &= ~AMDGPU_RESET_MC;
723 * vi_gpu_soft_reset - soft reset GPU
725 * @adev: amdgpu_device pointer
726 * @reset_mask: mask of which blocks to reset
728 * Soft reset the blocks specified in @reset_mask.
730 static void vi_gpu_soft_reset(struct amdgpu_device *adev, u32 reset_mask)
732 struct amdgpu_mode_mc_save save;
733 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
739 dev_info(adev->dev, "GPU softreset: 0x%08X\n", reset_mask);
741 vi_print_gpu_status_regs(adev);
742 dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
743 RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR));
744 dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
745 RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS));
751 //gfx_v8_0_rlc_stop(adev);
753 /* Disable GFX parsing/prefetching */
754 tmp = RREG32(mmCP_ME_CNTL);
755 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1);
756 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1);
757 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1);
758 WREG32(mmCP_ME_CNTL, tmp);
760 /* Disable MEC parsing/prefetching */
761 tmp = RREG32(mmCP_MEC_CNTL);
762 tmp = REG_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME1_HALT, 1);
763 tmp = REG_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME2_HALT, 1);
764 WREG32(mmCP_MEC_CNTL, tmp);
766 if (reset_mask & AMDGPU_RESET_DMA) {
768 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
769 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 1);
770 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
772 if (reset_mask & AMDGPU_RESET_DMA1) {
774 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
775 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 1);
776 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
779 gmc_v8_0_mc_stop(adev, &save);
780 if (amdgpu_asic_wait_for_mc_idle(adev)) {
781 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
784 if (reset_mask & (AMDGPU_RESET_GFX | AMDGPU_RESET_COMPUTE | AMDGPU_RESET_CP)) {
786 REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
788 REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
791 if (reset_mask & AMDGPU_RESET_CP) {
793 REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
795 REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
798 if (reset_mask & AMDGPU_RESET_DMA)
800 REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA, 1);
802 if (reset_mask & AMDGPU_RESET_DMA1)
804 REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1, 1);
806 if (reset_mask & AMDGPU_RESET_DISPLAY)
808 REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_DC, 1);
810 if (reset_mask & AMDGPU_RESET_RLC)
812 REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
814 if (reset_mask & AMDGPU_RESET_SEM)
816 REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SEM, 1);
818 if (reset_mask & AMDGPU_RESET_IH)
820 REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_IH, 1);
822 if (reset_mask & AMDGPU_RESET_GRBM)
824 REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
826 if (reset_mask & AMDGPU_RESET_VMC)
828 REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
830 if (reset_mask & AMDGPU_RESET_UVD)
832 REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_UVD, 1);
834 if (reset_mask & AMDGPU_RESET_VCE)
836 REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE0, 1);
838 if (reset_mask & AMDGPU_RESET_VCE)
840 REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE1, 1);
842 if (!(adev->flags & AMD_IS_APU)) {
843 if (reset_mask & AMDGPU_RESET_MC)
845 REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
848 if (grbm_soft_reset) {
849 tmp = RREG32(mmGRBM_SOFT_RESET);
850 tmp |= grbm_soft_reset;
851 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
852 WREG32(mmGRBM_SOFT_RESET, tmp);
853 tmp = RREG32(mmGRBM_SOFT_RESET);
857 tmp &= ~grbm_soft_reset;
858 WREG32(mmGRBM_SOFT_RESET, tmp);
859 tmp = RREG32(mmGRBM_SOFT_RESET);
862 if (srbm_soft_reset) {
863 tmp = RREG32(mmSRBM_SOFT_RESET);
864 tmp |= srbm_soft_reset;
865 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
866 WREG32(mmSRBM_SOFT_RESET, tmp);
867 tmp = RREG32(mmSRBM_SOFT_RESET);
871 tmp &= ~srbm_soft_reset;
872 WREG32(mmSRBM_SOFT_RESET, tmp);
873 tmp = RREG32(mmSRBM_SOFT_RESET);
876 /* Wait a little for things to settle down */
879 gmc_v8_0_mc_resume(adev, &save);
882 vi_print_gpu_status_regs(adev);
885 static void vi_gpu_pci_config_reset(struct amdgpu_device *adev)
887 struct amdgpu_mode_mc_save save;
890 dev_info(adev->dev, "GPU pci config reset\n");
896 /* Disable GFX parsing/prefetching */
897 tmp = RREG32(mmCP_ME_CNTL);
898 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1);
899 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1);
900 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1);
901 WREG32(mmCP_ME_CNTL, tmp);
903 /* Disable MEC parsing/prefetching */
904 tmp = RREG32(mmCP_MEC_CNTL);
905 tmp = REG_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME1_HALT, 1);
906 tmp = REG_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME2_HALT, 1);
907 WREG32(mmCP_MEC_CNTL, tmp);
909 /* Disable GFX parsing/prefetching */
910 WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK |
911 CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK);
913 /* Disable MEC parsing/prefetching */
914 WREG32(mmCP_MEC_CNTL,
915 CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK);
918 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
919 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 1);
920 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
923 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
924 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 1);
925 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
927 /* XXX other engines? */
929 /* halt the rlc, disable cp internal ints */
931 //gfx_v8_0_rlc_stop(adev);
935 /* disable mem access */
936 gmc_v8_0_mc_stop(adev, &save);
937 if (amdgpu_asic_wait_for_mc_idle(adev)) {
938 dev_warn(adev->dev, "Wait for MC idle timed out !\n");
942 pci_clear_master(adev->pdev);
944 amdgpu_pci_config_reset(adev);
948 /* wait for asic to come out of reset */
949 for (i = 0; i < adev->usec_timeout; i++) {
950 if (RREG32(mmCONFIG_MEMSIZE) != 0xffffffff)
957 static void vi_set_bios_scratch_engine_hung(struct amdgpu_device *adev, bool hung)
959 u32 tmp = RREG32(mmBIOS_SCRATCH_3);
962 tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG;
964 tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG;
966 WREG32(mmBIOS_SCRATCH_3, tmp);
970 * vi_asic_reset - soft reset GPU
972 * @adev: amdgpu_device pointer
974 * Look up which blocks are hung and attempt
976 * Returns 0 for success.
978 static int vi_asic_reset(struct amdgpu_device *adev)
982 reset_mask = vi_gpu_check_soft_reset(adev);
985 vi_set_bios_scratch_engine_hung(adev, true);
988 vi_gpu_soft_reset(adev, reset_mask);
990 reset_mask = vi_gpu_check_soft_reset(adev);
992 /* try pci config reset */
993 if (reset_mask && amdgpu_hard_reset)
994 vi_gpu_pci_config_reset(adev);
996 reset_mask = vi_gpu_check_soft_reset(adev);
999 vi_set_bios_scratch_engine_hung(adev, false);
1004 static int vi_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
1005 u32 cntl_reg, u32 status_reg)
1008 struct atom_clock_dividers dividers;
1011 r = amdgpu_atombios_get_clock_dividers(adev,
1012 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
1013 clock, false, ÷rs);
1017 tmp = RREG32_SMC(cntl_reg);
1018 tmp &= ~(CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK |
1019 CG_DCLK_CNTL__DCLK_DIVIDER_MASK);
1020 tmp |= dividers.post_divider;
1021 WREG32_SMC(cntl_reg, tmp);
1023 for (i = 0; i < 100; i++) {
1024 if (RREG32_SMC(status_reg) & CG_DCLK_STATUS__DCLK_STATUS_MASK)
1034 static int vi_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
1038 r = vi_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
1042 r = vi_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
1047 static int vi_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
1054 static void vi_pcie_gen3_enable(struct amdgpu_device *adev)
1056 if (pci_is_root_bus(adev->pdev->bus))
1059 if (amdgpu_pcie_gen2 == 0)
1062 if (adev->flags & AMD_IS_APU)
1065 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
1066 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
1072 static void vi_program_aspm(struct amdgpu_device *adev)
1075 if (amdgpu_aspm == 0)
1081 static void vi_enable_doorbell_aperture(struct amdgpu_device *adev,
1086 /* not necessary on CZ */
1087 if (adev->flags & AMD_IS_APU)
1090 tmp = RREG32(mmBIF_DOORBELL_APER_EN);
1092 tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 1);
1094 tmp = REG_SET_FIELD(tmp, BIF_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, 0);
1096 WREG32(mmBIF_DOORBELL_APER_EN, tmp);
1099 /* topaz has no DCE, UVD, VCE */
1100 static const struct amdgpu_ip_block_version topaz_ip_blocks[] =
1102 /* ORDER MATTERS! */
1104 .type = AMD_IP_BLOCK_TYPE_COMMON,
1108 .funcs = &vi_common_ip_funcs,
1111 .type = AMD_IP_BLOCK_TYPE_GMC,
1115 .funcs = &gmc_v8_0_ip_funcs,
1118 .type = AMD_IP_BLOCK_TYPE_IH,
1122 .funcs = &iceland_ih_ip_funcs,
1125 .type = AMD_IP_BLOCK_TYPE_SMC,
1129 .funcs = &amdgpu_pp_ip_funcs,
1132 .type = AMD_IP_BLOCK_TYPE_GFX,
1136 .funcs = &gfx_v8_0_ip_funcs,
1139 .type = AMD_IP_BLOCK_TYPE_SDMA,
1143 .funcs = &sdma_v2_4_ip_funcs,
1147 static const struct amdgpu_ip_block_version tonga_ip_blocks[] =
1149 /* ORDER MATTERS! */
1151 .type = AMD_IP_BLOCK_TYPE_COMMON,
1155 .funcs = &vi_common_ip_funcs,
1158 .type = AMD_IP_BLOCK_TYPE_GMC,
1162 .funcs = &gmc_v8_0_ip_funcs,
1165 .type = AMD_IP_BLOCK_TYPE_IH,
1169 .funcs = &tonga_ih_ip_funcs,
1172 .type = AMD_IP_BLOCK_TYPE_SMC,
1176 .funcs = &amdgpu_pp_ip_funcs,
1179 .type = AMD_IP_BLOCK_TYPE_DCE,
1183 .funcs = &dce_v10_0_ip_funcs,
1186 .type = AMD_IP_BLOCK_TYPE_GFX,
1190 .funcs = &gfx_v8_0_ip_funcs,
1193 .type = AMD_IP_BLOCK_TYPE_SDMA,
1197 .funcs = &sdma_v3_0_ip_funcs,
1200 .type = AMD_IP_BLOCK_TYPE_UVD,
1204 .funcs = &uvd_v5_0_ip_funcs,
1207 .type = AMD_IP_BLOCK_TYPE_VCE,
1211 .funcs = &vce_v3_0_ip_funcs,
1215 static const struct amdgpu_ip_block_version fiji_ip_blocks[] =
1217 /* ORDER MATTERS! */
1219 .type = AMD_IP_BLOCK_TYPE_COMMON,
1223 .funcs = &vi_common_ip_funcs,
1226 .type = AMD_IP_BLOCK_TYPE_GMC,
1230 .funcs = &gmc_v8_0_ip_funcs,
1233 .type = AMD_IP_BLOCK_TYPE_IH,
1237 .funcs = &tonga_ih_ip_funcs,
1240 .type = AMD_IP_BLOCK_TYPE_SMC,
1244 .funcs = &amdgpu_pp_ip_funcs,
1247 .type = AMD_IP_BLOCK_TYPE_DCE,
1251 .funcs = &dce_v10_0_ip_funcs,
1254 .type = AMD_IP_BLOCK_TYPE_GFX,
1258 .funcs = &gfx_v8_0_ip_funcs,
1261 .type = AMD_IP_BLOCK_TYPE_SDMA,
1265 .funcs = &sdma_v3_0_ip_funcs,
1268 .type = AMD_IP_BLOCK_TYPE_UVD,
1272 .funcs = &uvd_v6_0_ip_funcs,
1275 .type = AMD_IP_BLOCK_TYPE_VCE,
1279 .funcs = &vce_v3_0_ip_funcs,
1283 static const struct amdgpu_ip_block_version cz_ip_blocks[] =
1285 /* ORDER MATTERS! */
1287 .type = AMD_IP_BLOCK_TYPE_COMMON,
1291 .funcs = &vi_common_ip_funcs,
1294 .type = AMD_IP_BLOCK_TYPE_GMC,
1298 .funcs = &gmc_v8_0_ip_funcs,
1301 .type = AMD_IP_BLOCK_TYPE_IH,
1305 .funcs = &cz_ih_ip_funcs,
1308 .type = AMD_IP_BLOCK_TYPE_SMC,
1312 .funcs = &amdgpu_pp_ip_funcs
1315 .type = AMD_IP_BLOCK_TYPE_DCE,
1319 .funcs = &dce_v11_0_ip_funcs,
1322 .type = AMD_IP_BLOCK_TYPE_GFX,
1326 .funcs = &gfx_v8_0_ip_funcs,
1329 .type = AMD_IP_BLOCK_TYPE_SDMA,
1333 .funcs = &sdma_v3_0_ip_funcs,
1336 .type = AMD_IP_BLOCK_TYPE_UVD,
1340 .funcs = &uvd_v6_0_ip_funcs,
1343 .type = AMD_IP_BLOCK_TYPE_VCE,
1347 .funcs = &vce_v3_0_ip_funcs,
1351 int vi_set_ip_blocks(struct amdgpu_device *adev)
1353 switch (adev->asic_type) {
1355 adev->ip_blocks = topaz_ip_blocks;
1356 adev->num_ip_blocks = ARRAY_SIZE(topaz_ip_blocks);
1359 adev->ip_blocks = fiji_ip_blocks;
1360 adev->num_ip_blocks = ARRAY_SIZE(fiji_ip_blocks);
1363 adev->ip_blocks = tonga_ip_blocks;
1364 adev->num_ip_blocks = ARRAY_SIZE(tonga_ip_blocks);
1368 adev->ip_blocks = cz_ip_blocks;
1369 adev->num_ip_blocks = ARRAY_SIZE(cz_ip_blocks);
1372 /* FIXME: not supported yet */
1379 #define ATI_REV_ID_FUSE_MACRO__ADDRESS 0xC0014044
1380 #define ATI_REV_ID_FUSE_MACRO__SHIFT 9
1381 #define ATI_REV_ID_FUSE_MACRO__MASK 0x00001E00
1383 static uint32_t vi_get_rev_id(struct amdgpu_device *adev)
1385 if (adev->flags & AMD_IS_APU)
1386 return (RREG32_SMC(ATI_REV_ID_FUSE_MACRO__ADDRESS) & ATI_REV_ID_FUSE_MACRO__MASK)
1387 >> ATI_REV_ID_FUSE_MACRO__SHIFT;
1389 return (RREG32(mmPCIE_EFUSE4) & PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID_MASK)
1390 >> PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID__SHIFT;
1393 static const struct amdgpu_asic_funcs vi_asic_funcs =
1395 .read_disabled_bios = &vi_read_disabled_bios,
1396 .read_bios_from_rom = &vi_read_bios_from_rom,
1397 .read_register = &vi_read_register,
1398 .reset = &vi_asic_reset,
1399 .set_vga_state = &vi_vga_set_state,
1400 .get_xclk = &vi_get_xclk,
1401 .set_uvd_clocks = &vi_set_uvd_clocks,
1402 .set_vce_clocks = &vi_set_vce_clocks,
1403 .get_cu_info = &gfx_v8_0_get_cu_info,
1404 /* these should be moved to their own ip modules */
1405 .get_gpu_clock_counter = &gfx_v8_0_get_gpu_clock_counter,
1406 .wait_for_mc_idle = &gmc_v8_0_mc_wait_for_idle,
1409 static int vi_common_early_init(void *handle)
1411 bool smc_enabled = false;
1412 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1414 if (adev->flags & AMD_IS_APU) {
1415 adev->smc_rreg = &cz_smc_rreg;
1416 adev->smc_wreg = &cz_smc_wreg;
1418 adev->smc_rreg = &vi_smc_rreg;
1419 adev->smc_wreg = &vi_smc_wreg;
1421 adev->pcie_rreg = &vi_pcie_rreg;
1422 adev->pcie_wreg = &vi_pcie_wreg;
1423 adev->uvd_ctx_rreg = &vi_uvd_ctx_rreg;
1424 adev->uvd_ctx_wreg = &vi_uvd_ctx_wreg;
1425 adev->didt_rreg = &vi_didt_rreg;
1426 adev->didt_wreg = &vi_didt_wreg;
1428 adev->asic_funcs = &vi_asic_funcs;
1430 if (amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_SMC) &&
1431 (amdgpu_ip_block_mask & (1 << AMD_IP_BLOCK_TYPE_SMC)))
1434 adev->rev_id = vi_get_rev_id(adev);
1435 adev->external_rev_id = 0xFF;
1436 switch (adev->asic_type) {
1438 adev->has_uvd = false;
1441 adev->external_rev_id = 0x1;
1444 adev->has_uvd = true;
1445 adev->cg_flags = AMDGPU_CG_SUPPORT_UVD_MGCG |
1446 AMDGPU_CG_SUPPORT_VCE_MGCG;
1448 adev->external_rev_id = adev->rev_id + 0x3c;
1451 adev->has_uvd = true;
1454 adev->external_rev_id = adev->rev_id + 0x14;
1458 adev->has_uvd = true;
1460 /* Disable UVD pg */
1461 adev->pg_flags = /* AMDGPU_PG_SUPPORT_UVD | */AMDGPU_PG_SUPPORT_VCE;
1462 adev->external_rev_id = adev->rev_id + 0x1;
1465 /* FIXME: not supported yet */
1469 if (amdgpu_smc_load_fw && smc_enabled)
1470 adev->firmware.smu_load = true;
1472 amdgpu_get_pcie_info(adev);
1477 static int vi_common_sw_init(void *handle)
1482 static int vi_common_sw_fini(void *handle)
1487 static int vi_common_hw_init(void *handle)
1489 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1491 /* move the golden regs per IP block */
1492 vi_init_golden_registers(adev);
1493 /* enable pcie gen2/3 link */
1494 vi_pcie_gen3_enable(adev);
1496 vi_program_aspm(adev);
1497 /* enable the doorbell aperture */
1498 vi_enable_doorbell_aperture(adev, true);
1503 static int vi_common_hw_fini(void *handle)
1505 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1507 /* enable the doorbell aperture */
1508 vi_enable_doorbell_aperture(adev, false);
1513 static int vi_common_suspend(void *handle)
1515 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1517 return vi_common_hw_fini(adev);
1520 static int vi_common_resume(void *handle)
1522 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1524 return vi_common_hw_init(adev);
1527 static bool vi_common_is_idle(void *handle)
1532 static int vi_common_wait_for_idle(void *handle)
1537 static void vi_common_print_status(void *handle)
1542 static int vi_common_soft_reset(void *handle)
1547 static void fiji_update_bif_medium_grain_light_sleep(struct amdgpu_device *adev,
1550 uint32_t temp, data;
1552 temp = data = RREG32_PCIE(ixPCIE_CNTL2);
1555 data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
1556 PCIE_CNTL2__MST_MEM_LS_EN_MASK |
1557 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK;
1559 data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
1560 PCIE_CNTL2__MST_MEM_LS_EN_MASK |
1561 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
1564 WREG32_PCIE(ixPCIE_CNTL2, data);
1567 static void fiji_update_hdp_medium_grain_clock_gating(struct amdgpu_device *adev,
1570 uint32_t temp, data;
1572 temp = data = RREG32(mmHDP_HOST_PATH_CNTL);
1575 data &= ~HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK;
1577 data |= HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK;
1580 WREG32(mmHDP_HOST_PATH_CNTL, data);
1583 static void fiji_update_hdp_light_sleep(struct amdgpu_device *adev,
1586 uint32_t temp, data;
1588 temp = data = RREG32(mmHDP_MEM_POWER_LS);
1591 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1593 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1596 WREG32(mmHDP_MEM_POWER_LS, data);
1599 static void fiji_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,
1602 uint32_t temp, data;
1604 temp = data = RREG32_SMC(ixCGTT_ROM_CLK_CTRL0);
1607 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1608 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK);
1610 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1611 CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK;
1614 WREG32_SMC(ixCGTT_ROM_CLK_CTRL0, data);
1617 static int vi_common_set_clockgating_state(void *handle,
1618 enum amd_clockgating_state state)
1620 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1622 switch (adev->asic_type) {
1624 fiji_update_bif_medium_grain_light_sleep(adev,
1625 state == AMD_CG_STATE_GATE ? true : false);
1626 fiji_update_hdp_medium_grain_clock_gating(adev,
1627 state == AMD_CG_STATE_GATE ? true : false);
1628 fiji_update_hdp_light_sleep(adev,
1629 state == AMD_CG_STATE_GATE ? true : false);
1630 fiji_update_rom_medium_grain_clock_gating(adev,
1631 state == AMD_CG_STATE_GATE ? true : false);
1639 static int vi_common_set_powergating_state(void *handle,
1640 enum amd_powergating_state state)
1645 const struct amd_ip_funcs vi_common_ip_funcs = {
1646 .early_init = vi_common_early_init,
1648 .sw_init = vi_common_sw_init,
1649 .sw_fini = vi_common_sw_fini,
1650 .hw_init = vi_common_hw_init,
1651 .hw_fini = vi_common_hw_fini,
1652 .suspend = vi_common_suspend,
1653 .resume = vi_common_resume,
1654 .is_idle = vi_common_is_idle,
1655 .wait_for_idle = vi_common_wait_for_idle,
1656 .soft_reset = vi_common_soft_reset,
1657 .print_status = vi_common_print_status,
1658 .set_clockgating_state = vi_common_set_clockgating_state,
1659 .set_powergating_state = vi_common_set_powergating_state,