2 * Copyright 2020 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/pci.h>
27 #include "amdgpu_ih.h"
30 #include "oss/osssys_4_2_0_offset.h"
31 #include "oss/osssys_4_2_0_sh_mask.h"
33 #include "soc15_common.h"
34 #include "vega20_ih.h"
36 #define MAX_REARM_RETRY 10
38 static void vega20_ih_set_interrupt_funcs(struct amdgpu_device *adev);
41 * vega20_ih_init_register_offset - Initialize register offset for ih rings
43 * @adev: amdgpu_device pointer
45 * Initialize register offset ih rings (VEGA20).
47 static void vega20_ih_init_register_offset(struct amdgpu_device *adev)
49 struct amdgpu_ih_regs *ih_regs;
51 if (adev->irq.ih.ring_size) {
52 ih_regs = &adev->irq.ih.ih_regs;
53 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE);
54 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI);
55 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL);
56 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR);
57 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR);
58 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR);
59 ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO);
60 ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI);
61 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL;
64 if (adev->irq.ih1.ring_size) {
65 ih_regs = &adev->irq.ih1.ih_regs;
66 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1);
67 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING1);
68 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1);
69 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1);
70 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1);
71 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1);
72 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING1;
75 if (adev->irq.ih2.ring_size) {
76 ih_regs = &adev->irq.ih2.ih_regs;
77 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING2);
78 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING2);
79 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2);
80 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2);
81 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2);
82 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2);
83 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING2;
88 * vega20_ih_toggle_ring_interrupts - toggle the interrupt ring buffer
90 * @adev: amdgpu_device pointer
91 * @ih: amdgpu_ih_ring pointet
92 * @enable: true - enable the interrupts, false - disable the interrupts
94 * Toggle the interrupt ring buffer (VEGA20)
96 static int vega20_ih_toggle_ring_interrupts(struct amdgpu_device *adev,
97 struct amdgpu_ih_ring *ih,
100 struct amdgpu_ih_regs *ih_regs;
103 ih_regs = &ih->ih_regs;
105 tmp = RREG32(ih_regs->ih_rb_cntl);
106 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0));
107 /* enable_intr field is only valid in ring0 */
108 if (ih == &adev->irq.ih)
109 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));
110 if (amdgpu_sriov_vf(adev)) {
111 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
112 dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n");
116 WREG32(ih_regs->ih_rb_cntl, tmp);
122 /* set rptr, wptr to 0 */
123 WREG32(ih_regs->ih_rb_rptr, 0);
124 WREG32(ih_regs->ih_rb_wptr, 0);
133 * vega20_ih_toggle_interrupts - Toggle all the available interrupt ring buffers
135 * @adev: amdgpu_device pointer
136 * @enable: enable or disable interrupt ring buffers
138 * Toggle all the available interrupt ring buffers (VEGA20).
140 static int vega20_ih_toggle_interrupts(struct amdgpu_device *adev, bool enable)
142 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2};
146 for (i = 0; i < ARRAY_SIZE(ih); i++) {
147 if (ih[i]->ring_size) {
148 r = vega20_ih_toggle_ring_interrupts(adev, ih[i], enable);
157 static uint32_t vega20_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl)
159 int rb_bufsz = order_base_2(ih->ring_size / 4);
161 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
162 MC_SPACE, ih->use_bus_addr ? 1 : 4);
163 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
164 WPTR_OVERFLOW_CLEAR, 1);
165 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
166 WPTR_OVERFLOW_ENABLE, 1);
167 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);
168 /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register
169 * value is written to memory
171 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
172 WPTR_WRITEBACK_ENABLE, 1);
173 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1);
174 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0);
175 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);
180 static uint32_t vega20_ih_doorbell_rptr(struct amdgpu_ih_ring *ih)
182 u32 ih_doorbell_rtpr = 0;
184 if (ih->use_doorbell) {
185 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
186 IH_DOORBELL_RPTR, OFFSET,
188 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
192 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
196 return ih_doorbell_rtpr;
200 * vega20_ih_enable_ring - enable an ih ring buffer
202 * @adev: amdgpu_device pointer
203 * @ih: amdgpu_ih_ring pointer
205 * Enable an ih ring buffer (VEGA20)
207 static int vega20_ih_enable_ring(struct amdgpu_device *adev,
208 struct amdgpu_ih_ring *ih)
210 struct amdgpu_ih_regs *ih_regs;
213 ih_regs = &ih->ih_regs;
215 /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/
216 WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8);
217 WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff);
219 tmp = RREG32(ih_regs->ih_rb_cntl);
220 tmp = vega20_ih_rb_cntl(ih, tmp);
221 if (ih == &adev->irq.ih)
222 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled);
223 if (ih == &adev->irq.ih1) {
224 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 0);
225 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1);
227 if (amdgpu_sriov_vf(adev)) {
228 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
229 dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n");
233 WREG32(ih_regs->ih_rb_cntl, tmp);
236 if (ih == &adev->irq.ih) {
237 /* set the ih ring 0 writeback address whether it's enabled or not */
238 WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr));
239 WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF);
242 /* set rptr, wptr to 0 */
243 WREG32(ih_regs->ih_rb_wptr, 0);
244 WREG32(ih_regs->ih_rb_rptr, 0);
246 WREG32(ih_regs->ih_doorbell_rptr, vega20_ih_doorbell_rptr(ih));
252 * vega20_ih_irq_init - init and enable the interrupt ring
254 * @adev: amdgpu_device pointer
256 * Allocate a ring buffer for the interrupt controller,
257 * enable the RLC, disable interrupts, enable the IH
258 * ring buffer and enable it (VI).
259 * Called at device load and reume.
260 * Returns 0 for success, errors for failure.
262 static int vega20_ih_irq_init(struct amdgpu_device *adev)
264 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2};
271 ret = vega20_ih_toggle_interrupts(adev, false);
275 adev->nbio.funcs->ih_control(adev);
277 if (adev->asic_type == CHIP_ARCTURUS &&
278 adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
279 ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN);
280 if (adev->irq.ih.use_bus_addr) {
281 ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN,
282 MC_SPACE_GPA_ENABLE, 1);
284 ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN,
285 MC_SPACE_FBPA_ENABLE, 1);
287 WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken);
290 for (i = 0; i < ARRAY_SIZE(ih); i++) {
291 if (ih[i]->ring_size) {
292 ret = vega20_ih_enable_ring(adev, ih[i]);
298 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL);
299 tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL,
300 CLIENT18_IS_STORM_CLIENT, 1);
301 WREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL, tmp);
303 tmp = RREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL);
304 tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1);
305 WREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL, tmp);
307 pci_set_master(adev->pdev);
309 /* enable interrupts */
310 ret = vega20_ih_toggle_interrupts(adev, true);
318 * vega20_ih_irq_disable - disable interrupts
320 * @adev: amdgpu_device pointer
322 * Disable interrupts on the hw (VEGA20).
324 static void vega20_ih_irq_disable(struct amdgpu_device *adev)
326 vega20_ih_toggle_interrupts(adev, false);
328 /* Wait and acknowledge irq */
333 * vega20_ih_get_wptr - get the IH ring buffer wptr
335 * @adev: amdgpu_device pointer
337 * Get the IH ring buffer wptr from either the register
338 * or the writeback memory buffer (VEGA20). Also check for
339 * ring buffer overflow and deal with it.
340 * Returns the value of the wptr.
342 static u32 vega20_ih_get_wptr(struct amdgpu_device *adev,
343 struct amdgpu_ih_ring *ih)
346 struct amdgpu_ih_regs *ih_regs;
348 wptr = le32_to_cpu(*ih->wptr_cpu);
349 ih_regs = &ih->ih_regs;
351 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
354 /* Double check that the overflow wasn't already cleared. */
355 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr);
356 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
359 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
361 /* When a ring buffer overflow happen start parsing interrupt
362 * from the last not overwritten vector (wptr + 32). Hopefully
363 * this should allow us to catchup.
365 tmp = (wptr + 32) & ih->ptr_mask;
366 dev_warn(adev->dev, "IH ring buffer overflow "
367 "(0x%08X, 0x%08X, 0x%08X)\n",
368 wptr, ih->rptr, tmp);
371 tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl);
372 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
373 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
376 return (wptr & ih->ptr_mask);
380 * vega20_ih_irq_rearm - rearm IRQ if lost
382 * @adev: amdgpu_device pointer
385 static void vega20_ih_irq_rearm(struct amdgpu_device *adev,
386 struct amdgpu_ih_ring *ih)
390 struct amdgpu_ih_regs *ih_regs;
392 ih_regs = &ih->ih_regs;
394 /* Rearm IRQ / re-wwrite doorbell if doorbell write is lost */
395 for (i = 0; i < MAX_REARM_RETRY; i++) {
396 v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr);
397 if ((v < ih->ring_size) && (v != ih->rptr))
398 WDOORBELL32(ih->doorbell_index, ih->rptr);
405 * vega20_ih_set_rptr - set the IH ring buffer rptr
407 * @adev: amdgpu_device pointer
409 * Set the IH ring buffer rptr.
411 static void vega20_ih_set_rptr(struct amdgpu_device *adev,
412 struct amdgpu_ih_ring *ih)
414 struct amdgpu_ih_regs *ih_regs;
416 if (ih->use_doorbell) {
417 /* XXX check if swapping is necessary on BE */
418 *ih->rptr_cpu = ih->rptr;
419 WDOORBELL32(ih->doorbell_index, ih->rptr);
421 if (amdgpu_sriov_vf(adev))
422 vega20_ih_irq_rearm(adev, ih);
424 ih_regs = &ih->ih_regs;
425 WREG32(ih_regs->ih_rb_rptr, ih->rptr);
430 * vega20_ih_self_irq - dispatch work for ring 1 and 2
432 * @adev: amdgpu_device pointer
433 * @source: irq source
434 * @entry: IV with WPTR update
436 * Update the WPTR from the IV and schedule work to handle the entries.
438 static int vega20_ih_self_irq(struct amdgpu_device *adev,
439 struct amdgpu_irq_src *source,
440 struct amdgpu_iv_entry *entry)
442 uint32_t wptr = cpu_to_le32(entry->src_data[0]);
444 switch (entry->ring_id) {
446 *adev->irq.ih1.wptr_cpu = wptr;
447 schedule_work(&adev->irq.ih1_work);
450 *adev->irq.ih2.wptr_cpu = wptr;
451 schedule_work(&adev->irq.ih2_work);
458 static const struct amdgpu_irq_src_funcs vega20_ih_self_irq_funcs = {
459 .process = vega20_ih_self_irq,
462 static void vega20_ih_set_self_irq_funcs(struct amdgpu_device *adev)
464 adev->irq.self_irq.num_types = 0;
465 adev->irq.self_irq.funcs = &vega20_ih_self_irq_funcs;
468 static int vega20_ih_early_init(void *handle)
470 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
472 vega20_ih_set_interrupt_funcs(adev);
473 vega20_ih_set_self_irq_funcs(adev);
477 static int vega20_ih_sw_init(void *handle)
479 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
482 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0,
483 &adev->irq.self_irq);
487 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, true);
491 adev->irq.ih.use_doorbell = true;
492 adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1;
494 r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, true);
498 adev->irq.ih1.use_doorbell = true;
499 adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1;
501 r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, PAGE_SIZE, true);
505 adev->irq.ih2.use_doorbell = true;
506 adev->irq.ih2.doorbell_index = (adev->doorbell_index.ih + 2) << 1;
508 /* initialize ih control registers offset */
509 vega20_ih_init_register_offset(adev);
511 r = amdgpu_irq_init(adev);
516 static int vega20_ih_sw_fini(void *handle)
518 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
520 amdgpu_irq_fini(adev);
521 amdgpu_ih_ring_fini(adev, &adev->irq.ih2);
522 amdgpu_ih_ring_fini(adev, &adev->irq.ih1);
523 amdgpu_ih_ring_fini(adev, &adev->irq.ih);
528 static int vega20_ih_hw_init(void *handle)
531 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
533 r = vega20_ih_irq_init(adev);
540 static int vega20_ih_hw_fini(void *handle)
542 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
544 vega20_ih_irq_disable(adev);
549 static int vega20_ih_suspend(void *handle)
551 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
553 return vega20_ih_hw_fini(adev);
556 static int vega20_ih_resume(void *handle)
558 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
560 return vega20_ih_hw_init(adev);
563 static bool vega20_ih_is_idle(void *handle)
569 static int vega20_ih_wait_for_idle(void *handle)
575 static int vega20_ih_soft_reset(void *handle)
582 static void vega20_ih_update_clockgating_state(struct amdgpu_device *adev,
585 uint32_t data, def, field_val;
587 if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) {
588 def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL);
589 field_val = enable ? 0 : 1;
590 data = REG_SET_FIELD(data, IH_CLK_CTRL,
591 IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE, field_val);
592 data = REG_SET_FIELD(data, IH_CLK_CTRL,
593 IH_BUFFER_MEM_CLK_SOFT_OVERRIDE, field_val);
594 data = REG_SET_FIELD(data, IH_CLK_CTRL,
595 DBUS_MUX_CLK_SOFT_OVERRIDE, field_val);
596 data = REG_SET_FIELD(data, IH_CLK_CTRL,
597 OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val);
598 data = REG_SET_FIELD(data, IH_CLK_CTRL,
599 LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val);
600 data = REG_SET_FIELD(data, IH_CLK_CTRL,
601 DYN_CLK_SOFT_OVERRIDE, field_val);
602 data = REG_SET_FIELD(data, IH_CLK_CTRL,
603 REG_CLK_SOFT_OVERRIDE, field_val);
605 WREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL, data);
609 static int vega20_ih_set_clockgating_state(void *handle,
610 enum amd_clockgating_state state)
612 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
614 vega20_ih_update_clockgating_state(adev,
615 state == AMD_CG_STATE_GATE);
620 static int vega20_ih_set_powergating_state(void *handle,
621 enum amd_powergating_state state)
626 const struct amd_ip_funcs vega20_ih_ip_funcs = {
628 .early_init = vega20_ih_early_init,
630 .sw_init = vega20_ih_sw_init,
631 .sw_fini = vega20_ih_sw_fini,
632 .hw_init = vega20_ih_hw_init,
633 .hw_fini = vega20_ih_hw_fini,
634 .suspend = vega20_ih_suspend,
635 .resume = vega20_ih_resume,
636 .is_idle = vega20_ih_is_idle,
637 .wait_for_idle = vega20_ih_wait_for_idle,
638 .soft_reset = vega20_ih_soft_reset,
639 .set_clockgating_state = vega20_ih_set_clockgating_state,
640 .set_powergating_state = vega20_ih_set_powergating_state,
643 static const struct amdgpu_ih_funcs vega20_ih_funcs = {
644 .get_wptr = vega20_ih_get_wptr,
645 .decode_iv = amdgpu_ih_decode_iv_helper,
646 .set_rptr = vega20_ih_set_rptr
649 static void vega20_ih_set_interrupt_funcs(struct amdgpu_device *adev)
651 adev->irq.ih_funcs = &vega20_ih_funcs;
654 const struct amdgpu_ip_block_version vega20_ih_ip_block =
656 .type = AMD_IP_BLOCK_TYPE_IH,
660 .funcs = &vega20_ih_ip_funcs,