drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include "amdgpu.h"
  26 #include "amdgpu_vcn.h"
  27 #include "amdgpu_pm.h"
  28 #include "soc15.h"
  29 #include "soc15d.h"
  30 #include "vcn_v2_0.h"
  31 #include "mmsch_v3_0.h"
  32
  33 #include "vcn/vcn_3_0_0_offset.h"
  34 #include "vcn/vcn_3_0_0_sh_mask.h"
  35 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h"
  36
  37 #include <drm/drm_drv.h>
  38
  39 #define mmUVD_CONTEXT_ID_INTERNAL_OFFSET                        0x27
  40 #define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET                    0x0f
  41 #define mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET                  0x10
  42 #define mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET                  0x11
  43 #define mmUVD_NO_OP_INTERNAL_OFFSET                             0x29
  44 #define mmUVD_GP_SCRATCH8_INTERNAL_OFFSET                       0x66
  45 #define mmUVD_SCRATCH9_INTERNAL_OFFSET                          0xc01d
  46
  47 #define mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET                   0x431
  48 #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET          0x3b4
  49 #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET         0x3b5
  50 #define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET                       0x25c
  51
  52 #define VCN_INSTANCES_SIENNA_CICHLID                            2
  53 #define DEC_SW_RING_ENABLED                                     FALSE
  54
  55 #define RDECODE_MSG_CREATE                                      0x00000000
  56 #define RDECODE_MESSAGE_CREATE                                  0x00000001
  57
  58 static int amdgpu_ih_clientid_vcns[] = {
  59         SOC15_IH_CLIENTID_VCN,
  60         SOC15_IH_CLIENTID_VCN1
  61 };
  62
  63 static int vcn_v3_0_start_sriov(struct amdgpu_device *adev);
  64 static void vcn_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev);
  65 static void vcn_v3_0_set_enc_ring_funcs(struct amdgpu_device *adev);
  66 static void vcn_v3_0_set_irq_funcs(struct amdgpu_device *adev);
  67 static int vcn_v3_0_set_powergating_state(void *handle,
  68                         enum amd_powergating_state state);
  69 static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev,
  70                         int inst_idx, struct dpg_pause_state *new_state);
  71
  72 static void vcn_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring);
  73 static void vcn_v3_0_enc_ring_set_wptr(struct amdgpu_ring *ring);
  74
  75 /**
  76  * vcn_v3_0_early_init - set function pointers
  77  *
  78  * @handle: amdgpu_device pointer
  79  *
  80  * Set ring and irq function pointers
  81  */
  82 static int vcn_v3_0_early_init(void *handle)
  83 {
  84         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  85
  86         if (amdgpu_sriov_vf(adev)) {
  87                 adev->vcn.num_vcn_inst = VCN_INSTANCES_SIENNA_CICHLID;
  88                 adev->vcn.harvest_config = 0;
  89                 adev->vcn.num_enc_rings = 1;
  90
  91         } else {
  92                 if (adev->vcn.harvest_config == (AMDGPU_VCN_HARVEST_VCN0 |
  93                                                  AMDGPU_VCN_HARVEST_VCN1))
  94                         /* both instances are harvested, disable the block */
  95                         return -ENOENT;
  96
  97                 if (adev->ip_versions[UVD_HWIP][0] == IP_VERSION(3, 0, 33))
  98                         adev->vcn.num_enc_rings = 0;
  99                 else
 100                         adev->vcn.num_enc_rings = 2;
 101         }
 102
 103         vcn_v3_0_set_dec_ring_funcs(adev);
 104         vcn_v3_0_set_enc_ring_funcs(adev);
 105         vcn_v3_0_set_irq_funcs(adev);
 106
 107         return 0;
 108 }
 109
 110 /**
 111  * vcn_v3_0_sw_init - sw init for VCN block
 112  *
 113  * @handle: amdgpu_device pointer
 114  *
 115  * Load firmware and sw initialization
 116  */
 117 static int vcn_v3_0_sw_init(void *handle)
 118 {
 119         struct amdgpu_ring *ring;
 120         int i, j, r;
 121         int vcn_doorbell_index = 0;
 122         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 123
 124         r = amdgpu_vcn_sw_init(adev);
 125         if (r)
 126                 return r;
 127
 128         amdgpu_vcn_setup_ucode(adev);
 129
 130         r = amdgpu_vcn_resume(adev);
 131         if (r)
 132                 return r;
 133
 134         /*
 135          * Note: doorbell assignment is fixed for SRIOV multiple VCN engines
 136          * Formula:
 137          *   vcn_db_base  = adev->doorbell_index.vcn.vcn_ring0_1 << 1;
 138          *   dec_ring_i   = vcn_db_base + i * (adev->vcn.num_enc_rings + 1)
 139          *   enc_ring_i,j = vcn_db_base + i * (adev->vcn.num_enc_rings + 1) + 1 + j
 140          */
 141         if (amdgpu_sriov_vf(adev)) {
 142                 vcn_doorbell_index = adev->doorbell_index.vcn.vcn_ring0_1;
 143                 /* get DWORD offset */
 144                 vcn_doorbell_index = vcn_doorbell_index << 1;
 145         }
 146
 147         for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 148                 volatile struct amdgpu_fw_shared *fw_shared;
 149
 150                 if (adev->vcn.harvest_config & (1 << i))
 151                         continue;
 152
 153                 adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET;
 154                 adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET;
 155                 adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET;
 156                 adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET;
 157                 adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET;
 158                 adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET;
 159
 160                 adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET;
 161                 adev->vcn.inst[i].external.scratch9 = SOC15_REG_OFFSET(VCN, i, mmUVD_SCRATCH9);
 162                 adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET;
 163                 adev->vcn.inst[i].external.data0 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA0);
 164                 adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET;
 165                 adev->vcn.inst[i].external.data1 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA1);
 166                 adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET;
 167                 adev->vcn.inst[i].external.cmd = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_CMD);
 168                 adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET;
 169                 adev->vcn.inst[i].external.nop = SOC15_REG_OFFSET(VCN, i, mmUVD_NO_OP);
 170
 171                 /* VCN DEC TRAP */
 172                 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i],
 173                                 VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst[i].irq);
 174                 if (r)
 175                         return r;
 176
 177                 atomic_set(&adev->vcn.inst[i].sched_score, 0);
 178
 179                 ring = &adev->vcn.inst[i].ring_dec;
 180                 ring->use_doorbell = true;
 181                 if (amdgpu_sriov_vf(adev)) {
 182                         ring->doorbell_index = vcn_doorbell_index + i * (adev->vcn.num_enc_rings + 1);
 183                 } else {
 184                         ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i;
 185                 }
 186                 sprintf(ring->name, "vcn_dec_%d", i);
 187                 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0,
 188                                      AMDGPU_RING_PRIO_DEFAULT,
 189                                      &adev->vcn.inst[i].sched_score);
 190                 if (r)
 191                         return r;
 192
 193                 for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
 194                         enum amdgpu_ring_priority_level hw_prio = amdgpu_vcn_get_enc_ring_prio(j);
 195
 196                         /* VCN ENC TRAP */
 197                         r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i],
 198                                 j + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq);
 199                         if (r)
 200                                 return r;
 201
 202                         ring = &adev->vcn.inst[i].ring_enc[j];
 203                         ring->use_doorbell = true;
 204                         if (amdgpu_sriov_vf(adev)) {
 205                                 ring->doorbell_index = vcn_doorbell_index + i * (adev->vcn.num_enc_rings + 1) + 1 + j;
 206                         } else {
 207                                 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + j + 8 * i;
 208                         }
 209                         sprintf(ring->name, "vcn_enc_%d.%d", i, j);
 210                         r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0,
 211                                              hw_prio, &adev->vcn.inst[i].sched_score);
 212                         if (r)
 213                                 return r;
 214                 }
 215
 216                 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
 217                 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_SW_RING_FLAG) |
 218                                              cpu_to_le32(AMDGPU_VCN_MULTI_QUEUE_FLAG) |
 219                                              cpu_to_le32(AMDGPU_VCN_FW_SHARED_FLAG_0_RB);
 220                 fw_shared->sw_ring.is_enabled = cpu_to_le32(DEC_SW_RING_ENABLED);
 221
 222                 if (amdgpu_vcnfw_log)
 223                         amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]);
 224         }
 225
 226         if (amdgpu_sriov_vf(adev)) {
 227                 r = amdgpu_virt_alloc_mm_table(adev);
 228                 if (r)
 229                         return r;
 230         }
 231         if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
 232                 adev->vcn.pause_dpg_mode = vcn_v3_0_pause_dpg_mode;
 233
 234         return 0;
 235 }
 236
 237 /**
 238  * vcn_v3_0_sw_fini - sw fini for VCN block
 239  *
 240  * @handle: amdgpu_device pointer
 241  *
 242  * VCN suspend and free up sw allocation
 243  */
 244 static int vcn_v3_0_sw_fini(void *handle)
 245 {
 246         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 247         int i, r, idx;
 248
 249         if (drm_dev_enter(adev_to_drm(adev), &idx)) {
 250                 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 251                         volatile struct amdgpu_fw_shared *fw_shared;
 252
 253                         if (adev->vcn.harvest_config & (1 << i))
 254                                 continue;
 255                         fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
 256                         fw_shared->present_flag_0 = 0;
 257                         fw_shared->sw_ring.is_enabled = false;
 258                 }
 259
 260                 drm_dev_exit(idx);
 261         }
 262
 263         if (amdgpu_sriov_vf(adev))
 264                 amdgpu_virt_free_mm_table(adev);
 265
 266         r = amdgpu_vcn_suspend(adev);
 267         if (r)
 268                 return r;
 269
 270         r = amdgpu_vcn_sw_fini(adev);
 271
 272         return r;
 273 }
 274
 275 /**
 276  * vcn_v3_0_hw_init - start and test VCN block
 277  *
 278  * @handle: amdgpu_device pointer
 279  *
 280  * Initialize the hardware, boot up the VCPU and do some testing
 281  */
 282 static int vcn_v3_0_hw_init(void *handle)
 283 {
 284         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 285         struct amdgpu_ring *ring;
 286         int i, j, r;
 287
 288         if (amdgpu_sriov_vf(adev)) {
 289                 r = vcn_v3_0_start_sriov(adev);
 290                 if (r)
 291                         goto done;
 292
 293                 /* initialize VCN dec and enc ring buffers */
 294                 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
 295                         if (adev->vcn.harvest_config & (1 << i))
 296                                 continue;
 297
 298                         ring = &adev->vcn.inst[i].ring_dec;
 299                         if (amdgpu_vcn_is_disabled_vcn(adev, VCN_DECODE_RING, i)) {
 300                                 ring->sched.ready = false;
 301                                 ring->no_scheduler = true;
 302                                 dev_info(adev->dev, "ring %s is disabled by hypervisor\n", ring->name);
 303                         } else {
 304                                 ring->wptr = 0;
 305                                 ring->wptr_old = 0;
 306                                 vcn_v3_0_dec_ring_set_wptr(ring);
 307                                 ring->sched.ready = true;
 308                         }
 309
 310                         for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
 311                                 ring = &adev->vcn.inst[i].ring_enc[j];
 312                                 if (amdgpu_vcn_is_disabled_vcn(adev, VCN_ENCODE_RING, i)) {
 313                                         ring->sched.ready = false;
 314                                         ring->no_scheduler = true;
 315                                         dev_info(adev->dev, "ring %s is disabled by hypervisor\n", ring->name);
 316                                 } else {
 317                                         ring->wptr = 0;
 318                                         ring->wptr_old = 0;
 319                                         vcn_v3_0_enc_ring_set_wptr(ring);
 320                                         ring->sched.ready = true;
 321                                 }
 322                         }
 323                 }
 324         } else {
 325                 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
 326                         if (adev->vcn.harvest_config & (1 << i))
 327                                 continue;
 328
 329                         ring = &adev->vcn.inst[i].ring_dec;
 330
 331                         adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
 332                                                      ring->doorbell_index, i);
 333
 334                         r = amdgpu_ring_test_helper(ring);
 335                         if (r)
 336                                 goto done;
 337
 338                         for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
 339                                 ring = &adev->vcn.inst[i].ring_enc[j];
 340                                 r = amdgpu_ring_test_helper(ring);
 341                                 if (r)
 342                                         goto done;
 343                         }
 344                 }
 345         }
 346
 347 done:
 348         if (!r)
 349                 DRM_INFO("VCN decode and encode initialized successfully(under %s).\n",
 350                         (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode");
 351
 352         return r;
 353 }
 354
 355 /**
 356  * vcn_v3_0_hw_fini - stop the hardware block
 357  *
 358  * @handle: amdgpu_device pointer
 359  *
 360  * Stop the VCN block, mark ring as not ready any more
 361  */
 362 static int vcn_v3_0_hw_fini(void *handle)
 363 {
 364         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 365         int i;
 366
 367         cancel_delayed_work_sync(&adev->vcn.idle_work);
 368
 369         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
 370                 if (adev->vcn.harvest_config & (1 << i))
 371                         continue;
 372
 373                 if (!amdgpu_sriov_vf(adev)) {
 374                         if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
 375                                         (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
 376                                          RREG32_SOC15(VCN, i, mmUVD_STATUS))) {
 377                                 vcn_v3_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
 378                         }
 379                 }
 380         }
 381
 382         return 0;
 383 }
 384
 385 /**
 386  * vcn_v3_0_suspend - suspend VCN block
 387  *
 388  * @handle: amdgpu_device pointer
 389  *
 390  * HW fini and suspend VCN block
 391  */
 392 static int vcn_v3_0_suspend(void *handle)
 393 {
 394         int r;
 395         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 396
 397         r = vcn_v3_0_hw_fini(adev);
 398         if (r)
 399                 return r;
 400
 401         r = amdgpu_vcn_suspend(adev);
 402
 403         return r;
 404 }
 405
 406 /**
 407  * vcn_v3_0_resume - resume VCN block
 408  *
 409  * @handle: amdgpu_device pointer
 410  *
 411  * Resume firmware and hw init VCN block
 412  */
 413 static int vcn_v3_0_resume(void *handle)
 414 {
 415         int r;
 416         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 417
 418         r = amdgpu_vcn_resume(adev);
 419         if (r)
 420                 return r;
 421
 422         r = vcn_v3_0_hw_init(adev);
 423
 424         return r;
 425 }
 426
 427 /**
 428  * vcn_v3_0_mc_resume - memory controller programming
 429  *
 430  * @adev: amdgpu_device pointer
 431  * @inst: instance number
 432  *
 433  * Let the VCN memory controller know it's offsets
 434  */
 435 static void vcn_v3_0_mc_resume(struct amdgpu_device *adev, int inst)
 436 {
 437         uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
 438         uint32_t offset;
 439
 440         /* cache window 0: fw */
 441         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 442                 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 443                         (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_lo));
 444                 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 445                         (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_hi));
 446                 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET0, 0);
 447                 offset = 0;
 448         } else {
 449                 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 450                         lower_32_bits(adev->vcn.inst[inst].gpu_addr));
 451                 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 452                         upper_32_bits(adev->vcn.inst[inst].gpu_addr));
 453                 offset = size;
 454                 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET0,
 455                         AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
 456         }
 457         WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE0, size);
 458
 459         /* cache window 1: stack */
 460         WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
 461                 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset));
 462         WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
 463                 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset));
 464         WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET1, 0);
 465         WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);
 466
 467         /* cache window 2: context */
 468         WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
 469                 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
 470         WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
 471                 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
 472         WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET2, 0);
 473         WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
 474
 475         /* non-cache window */
 476         WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW,
 477                 lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr));
 478         WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH,
 479                 upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr));
 480         WREG32_SOC15(VCN, inst, mmUVD_VCPU_NONCACHE_OFFSET0, 0);
 481         WREG32_SOC15(VCN, inst, mmUVD_VCPU_NONCACHE_SIZE0,
 482                 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)));
 483 }
 484
 485 static void vcn_v3_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
 486 {
 487         uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
 488         uint32_t offset;
 489
 490         /* cache window 0: fw */
 491         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 492                 if (!indirect) {
 493                         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 494                                 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
 495                                 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect);
 496                         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 497                                 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
 498                                 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect);
 499                         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 500                                 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
 501                 } else {
 502                         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 503                                 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);
 504                         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 505                                 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);
 506                         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 507                                 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
 508                 }
 509                 offset = 0;
 510         } else {
 511                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 512                         VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
 513                         lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
 514                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 515                         VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
 516                         upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
 517                 offset = size;
 518                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 519                         VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0),
 520                         AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);
 521         }
 522
 523         if (!indirect)
 524                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 525                         VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
 526         else
 527                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 528                         VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
 529
 530         /* cache window 1: stack */
 531         if (!indirect) {
 532                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 533                         VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
 534                         lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
 535                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 536                         VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
 537                         upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
 538                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 539                         VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
 540         } else {
 541                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 542                         VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);
 543                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 544                         VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);
 545                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 546                         VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
 547         }
 548         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 549                         VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);
 550
 551         /* cache window 2: context */
 552         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 553                         VCN, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
 554                         lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
 555         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 556                         VCN, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
 557                         upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
 558         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 559                         VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
 560         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 561                         VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);
 562
 563         /* non-cache window */
 564         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 565                         VCN, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),
 566                         lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
 567         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 568                         VCN, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),
 569                         upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
 570         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 571                         VCN, inst_idx, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
 572         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 573                         VCN, inst_idx, mmUVD_VCPU_NONCACHE_SIZE0),
 574                         AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect);
 575
 576         /* VCN global tiling registers */
 577         WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
 578                 UVD, 0, mmUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);
 579 }
 580
 581 static void vcn_v3_0_disable_static_power_gating(struct amdgpu_device *adev, int inst)
 582 {
 583         uint32_t data = 0;
 584
 585         if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
 586                 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
 587                         | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
 588                         | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
 589                         | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
 590                         | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
 591                         | 2 << UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT
 592                         | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT
 593                         | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
 594                         | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
 595                         | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
 596                         | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT
 597                         | 2 << UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT
 598                         | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT
 599                         | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT);
 600
 601                 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data);
 602                 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS,
 603                         UVD_PGFSM_STATUS__UVDM_UVDU_UVDLM_PWR_ON_3_0, 0x3F3FFFFF);
 604         } else {
 605                 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
 606                         | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
 607                         | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
 608                         | 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
 609                         | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
 610                         | 1 << UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT
 611                         | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT
 612                         | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
 613                         | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
 614                         | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
 615                         | 1 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT
 616                         | 1 << UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT
 617                         | 1 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT
 618                         | 1 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT);
 619                 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data);
 620                 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, 0,  0x3F3FFFFF);
 621         }
 622
 623         data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS);
 624         data &= ~0x103;
 625         if (adev->pg_flags & AMD_PG_SUPPORT_VCN)
 626                 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON |
 627                         UVD_POWER_STATUS__UVD_PG_EN_MASK;
 628
 629         WREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS, data);
 630 }
 631
 632 static void vcn_v3_0_enable_static_power_gating(struct amdgpu_device *adev, int inst)
 633 {
 634         uint32_t data;
 635
 636         if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
 637                 /* Before power off, this indicator has to be turned on */
 638                 data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS);
 639                 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK;
 640                 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF;
 641                 WREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS, data);
 642
 643                 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
 644                         | 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
 645                         | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
 646                         | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
 647                         | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
 648                         | 2 << UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT
 649                         | 2 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT
 650                         | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
 651                         | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
 652                         | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
 653                         | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT
 654                         | 2 << UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT
 655                         | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT
 656                         | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT);
 657                 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data);
 658
 659                 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT
 660                         | 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT
 661                         | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT
 662                         | 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT
 663                         | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT
 664                         | 2 << UVD_PGFSM_STATUS__UVDIRL_PWR_STATUS__SHIFT
 665                         | 2 << UVD_PGFSM_STATUS__UVDLM_PWR_STATUS__SHIFT
 666                         | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT
 667                         | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT
 668                         | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT
 669                         | 2 << UVD_PGFSM_STATUS__UVDAB_PWR_STATUS__SHIFT
 670                         | 2 << UVD_PGFSM_STATUS__UVDATD_PWR_STATUS__SHIFT
 671                         | 2 << UVD_PGFSM_STATUS__UVDNA_PWR_STATUS__SHIFT
 672                         | 2 << UVD_PGFSM_STATUS__UVDNB_PWR_STATUS__SHIFT);
 673                 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, data, 0x3F3FFFFF);
 674         }
 675 }
 676
 677 /**
 678  * vcn_v3_0_disable_clock_gating - disable VCN clock gating
 679  *
 680  * @adev: amdgpu_device pointer
 681  * @inst: instance number
 682  *
 683  * Disable clock gating for VCN block
 684  */
 685 static void vcn_v3_0_disable_clock_gating(struct amdgpu_device *adev, int inst)
 686 {
 687         uint32_t data;
 688
 689         /* VCN disable CGC */
 690         data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL);
 691         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 692                 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 693         else
 694                 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
 695         data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 696         data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 697         WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data);
 698
 699         data = RREG32_SOC15(VCN, inst, mmUVD_CGC_GATE);
 700         data &= ~(UVD_CGC_GATE__SYS_MASK
 701                 | UVD_CGC_GATE__UDEC_MASK
 702                 | UVD_CGC_GATE__MPEG2_MASK
 703                 | UVD_CGC_GATE__REGS_MASK
 704                 | UVD_CGC_GATE__RBC_MASK
 705                 | UVD_CGC_GATE__LMI_MC_MASK
 706                 | UVD_CGC_GATE__LMI_UMC_MASK
 707                 | UVD_CGC_GATE__IDCT_MASK
 708                 | UVD_CGC_GATE__MPRD_MASK
 709                 | UVD_CGC_GATE__MPC_MASK
 710                 | UVD_CGC_GATE__LBSI_MASK
 711                 | UVD_CGC_GATE__LRBBM_MASK
 712                 | UVD_CGC_GATE__UDEC_RE_MASK
 713                 | UVD_CGC_GATE__UDEC_CM_MASK
 714                 | UVD_CGC_GATE__UDEC_IT_MASK
 715                 | UVD_CGC_GATE__UDEC_DB_MASK
 716                 | UVD_CGC_GATE__UDEC_MP_MASK
 717                 | UVD_CGC_GATE__WCB_MASK
 718                 | UVD_CGC_GATE__VCPU_MASK
 719                 | UVD_CGC_GATE__MMSCH_MASK);
 720
 721         WREG32_SOC15(VCN, inst, mmUVD_CGC_GATE, data);
 722
 723         SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_CGC_GATE, 0,  0xFFFFFFFF);
 724
 725         data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL);
 726         data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK
 727                 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
 728                 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
 729                 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
 730                 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
 731                 | UVD_CGC_CTRL__SYS_MODE_MASK
 732                 | UVD_CGC_CTRL__UDEC_MODE_MASK
 733                 | UVD_CGC_CTRL__MPEG2_MODE_MASK
 734                 | UVD_CGC_CTRL__REGS_MODE_MASK
 735                 | UVD_CGC_CTRL__RBC_MODE_MASK
 736                 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
 737                 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
 738                 | UVD_CGC_CTRL__IDCT_MODE_MASK
 739                 | UVD_CGC_CTRL__MPRD_MODE_MASK
 740                 | UVD_CGC_CTRL__MPC_MODE_MASK
 741                 | UVD_CGC_CTRL__LBSI_MODE_MASK
 742                 | UVD_CGC_CTRL__LRBBM_MODE_MASK
 743                 | UVD_CGC_CTRL__WCB_MODE_MASK
 744                 | UVD_CGC_CTRL__VCPU_MODE_MASK
 745                 | UVD_CGC_CTRL__MMSCH_MODE_MASK);
 746         WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data);
 747
 748         data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE);
 749         data |= (UVD_SUVD_CGC_GATE__SRE_MASK
 750                 | UVD_SUVD_CGC_GATE__SIT_MASK
 751                 | UVD_SUVD_CGC_GATE__SMP_MASK
 752                 | UVD_SUVD_CGC_GATE__SCM_MASK
 753                 | UVD_SUVD_CGC_GATE__SDB_MASK
 754                 | UVD_SUVD_CGC_GATE__SRE_H264_MASK
 755                 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
 756                 | UVD_SUVD_CGC_GATE__SIT_H264_MASK
 757                 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
 758                 | UVD_SUVD_CGC_GATE__SCM_H264_MASK
 759                 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
 760                 | UVD_SUVD_CGC_GATE__SDB_H264_MASK
 761                 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK
 762                 | UVD_SUVD_CGC_GATE__SCLR_MASK
 763                 | UVD_SUVD_CGC_GATE__ENT_MASK
 764                 | UVD_SUVD_CGC_GATE__IME_MASK
 765                 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
 766                 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
 767                 | UVD_SUVD_CGC_GATE__SITE_MASK
 768                 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK
 769                 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK
 770                 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
 771                 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK
 772                 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK
 773                 | UVD_SUVD_CGC_GATE__EFC_MASK
 774                 | UVD_SUVD_CGC_GATE__SAOE_MASK
 775                 | UVD_SUVD_CGC_GATE__SRE_AV1_MASK
 776                 | UVD_SUVD_CGC_GATE__FBC_PCLK_MASK
 777                 | UVD_SUVD_CGC_GATE__FBC_CCLK_MASK
 778                 | UVD_SUVD_CGC_GATE__SCM_AV1_MASK
 779                 | UVD_SUVD_CGC_GATE__SMPA_MASK);
 780         WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE, data);
 781
 782         data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE2);
 783         data |= (UVD_SUVD_CGC_GATE2__MPBE0_MASK
 784                 | UVD_SUVD_CGC_GATE2__MPBE1_MASK
 785                 | UVD_SUVD_CGC_GATE2__SIT_AV1_MASK
 786                 | UVD_SUVD_CGC_GATE2__SDB_AV1_MASK
 787                 | UVD_SUVD_CGC_GATE2__MPC1_MASK);
 788         WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE2, data);
 789
 790         data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL);
 791         data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
 792                 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
 793                 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
 794                 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
 795                 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
 796                 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
 797                 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
 798                 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
 799                 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK
 800                 | UVD_SUVD_CGC_CTRL__EFC_MODE_MASK
 801                 | UVD_SUVD_CGC_CTRL__SAOE_MODE_MASK
 802                 | UVD_SUVD_CGC_CTRL__SMPA_MODE_MASK
 803                 | UVD_SUVD_CGC_CTRL__MPBE0_MODE_MASK
 804                 | UVD_SUVD_CGC_CTRL__MPBE1_MODE_MASK
 805                 | UVD_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK
 806                 | UVD_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK
 807                 | UVD_SUVD_CGC_CTRL__MPC1_MODE_MASK
 808                 | UVD_SUVD_CGC_CTRL__FBC_PCLK_MASK
 809                 | UVD_SUVD_CGC_CTRL__FBC_CCLK_MASK);
 810         WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL, data);
 811 }
 812
 813 static void vcn_v3_0_clock_gating_dpg_mode(struct amdgpu_device *adev,
 814                 uint8_t sram_sel, int inst_idx, uint8_t indirect)
 815 {
 816         uint32_t reg_data = 0;
 817
 818         /* enable sw clock gating control */
 819         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 820                 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 821         else
 822                 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 823         reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 824         reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 825         reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
 826                  UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
 827                  UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
 828                  UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
 829                  UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
 830                  UVD_CGC_CTRL__SYS_MODE_MASK |
 831                  UVD_CGC_CTRL__UDEC_MODE_MASK |
 832                  UVD_CGC_CTRL__MPEG2_MODE_MASK |
 833                  UVD_CGC_CTRL__REGS_MODE_MASK |
 834                  UVD_CGC_CTRL__RBC_MODE_MASK |
 835                  UVD_CGC_CTRL__LMI_MC_MODE_MASK |
 836                  UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
 837                  UVD_CGC_CTRL__IDCT_MODE_MASK |
 838                  UVD_CGC_CTRL__MPRD_MODE_MASK |
 839                  UVD_CGC_CTRL__MPC_MODE_MASK |
 840                  UVD_CGC_CTRL__LBSI_MODE_MASK |
 841                  UVD_CGC_CTRL__LRBBM_MODE_MASK |
 842                  UVD_CGC_CTRL__WCB_MODE_MASK |
 843                  UVD_CGC_CTRL__VCPU_MODE_MASK |
 844                  UVD_CGC_CTRL__MMSCH_MODE_MASK);
 845         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 846                 VCN, inst_idx, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);
 847
 848         /* turn off clock gating */
 849         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 850                 VCN, inst_idx, mmUVD_CGC_GATE), 0, sram_sel, indirect);
 851
 852         /* turn on SUVD clock gating */
 853         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 854                 VCN, inst_idx, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
 855
 856         /* turn on sw mode in UVD_SUVD_CGC_CTRL */
 857         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 858                 VCN, inst_idx, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
 859 }
 860
 861 /**
 862  * vcn_v3_0_enable_clock_gating - enable VCN clock gating
 863  *
 864  * @adev: amdgpu_device pointer
 865  * @inst: instance number
 866  *
 867  * Enable clock gating for VCN block
 868  */
 869 static void vcn_v3_0_enable_clock_gating(struct amdgpu_device *adev, int inst)
 870 {
 871         uint32_t data;
 872
 873         /* enable VCN CGC */
 874         data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL);
 875         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 876                 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 877         else
 878                 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 879         data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 880         data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 881         WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data);
 882
 883         data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL);
 884         data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK
 885                 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
 886                 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
 887                 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
 888                 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
 889                 | UVD_CGC_CTRL__SYS_MODE_MASK
 890                 | UVD_CGC_CTRL__UDEC_MODE_MASK
 891                 | UVD_CGC_CTRL__MPEG2_MODE_MASK
 892                 | UVD_CGC_CTRL__REGS_MODE_MASK
 893                 | UVD_CGC_CTRL__RBC_MODE_MASK
 894                 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
 895                 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
 896                 | UVD_CGC_CTRL__IDCT_MODE_MASK
 897                 | UVD_CGC_CTRL__MPRD_MODE_MASK
 898                 | UVD_CGC_CTRL__MPC_MODE_MASK
 899                 | UVD_CGC_CTRL__LBSI_MODE_MASK
 900                 | UVD_CGC_CTRL__LRBBM_MODE_MASK
 901                 | UVD_CGC_CTRL__WCB_MODE_MASK
 902                 | UVD_CGC_CTRL__VCPU_MODE_MASK
 903                 | UVD_CGC_CTRL__MMSCH_MODE_MASK);
 904         WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data);
 905
 906         data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL);
 907         data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
 908                 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
 909                 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
 910                 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
 911                 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
 912                 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
 913                 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
 914                 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
 915                 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK
 916                 | UVD_SUVD_CGC_CTRL__EFC_MODE_MASK
 917                 | UVD_SUVD_CGC_CTRL__SAOE_MODE_MASK
 918                 | UVD_SUVD_CGC_CTRL__SMPA_MODE_MASK
 919                 | UVD_SUVD_CGC_CTRL__MPBE0_MODE_MASK
 920                 | UVD_SUVD_CGC_CTRL__MPBE1_MODE_MASK
 921                 | UVD_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK
 922                 | UVD_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK
 923                 | UVD_SUVD_CGC_CTRL__MPC1_MODE_MASK
 924                 | UVD_SUVD_CGC_CTRL__FBC_PCLK_MASK
 925                 | UVD_SUVD_CGC_CTRL__FBC_CCLK_MASK);
 926         WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL, data);
 927 }
 928
 929 static int vcn_v3_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
 930 {
 931         volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
 932         struct amdgpu_ring *ring;
 933         uint32_t rb_bufsz, tmp;
 934
 935         /* disable register anti-hang mechanism */
 936         WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1,
 937                 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
 938         /* enable dynamic power gating mode */
 939         tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS);
 940         tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;
 941         tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK;
 942         WREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS, tmp);
 943
 944         if (indirect)
 945                 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr;
 946
 947         /* enable clock gating */
 948         vcn_v3_0_clock_gating_dpg_mode(adev, 0, inst_idx, indirect);
 949
 950         /* enable VCPU clock */
 951         tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
 952         tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
 953         tmp |= UVD_VCPU_CNTL__BLK_RST_MASK;
 954         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 955                 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect);
 956
 957         /* disable master interupt */
 958         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 959                 VCN, inst_idx, mmUVD_MASTINT_EN), 0, 0, indirect);
 960
 961         /* setup mmUVD_LMI_CTRL */
 962         tmp = (0x8 | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
 963                 UVD_LMI_CTRL__REQ_MODE_MASK |
 964                 UVD_LMI_CTRL__CRC_RESET_MASK |
 965                 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
 966                 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
 967                 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
 968                 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
 969                 0x00100000L);
 970         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 971                 VCN, inst_idx, mmUVD_LMI_CTRL), tmp, 0, indirect);
 972
 973         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 974                 VCN, inst_idx, mmUVD_MPC_CNTL),
 975                 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect);
 976
 977         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 978                 VCN, inst_idx, mmUVD_MPC_SET_MUXA0),
 979                 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
 980                  (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
 981                  (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
 982                  (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect);
 983
 984         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 985                 VCN, inst_idx, mmUVD_MPC_SET_MUXB0),
 986                  ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
 987                  (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
 988                  (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
 989                  (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect);
 990
 991         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 992                 VCN, inst_idx, mmUVD_MPC_SET_MUX),
 993                 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
 994                  (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
 995                  (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);
 996
 997         vcn_v3_0_mc_resume_dpg_mode(adev, inst_idx, indirect);
 998
 999         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
1000                 VCN, inst_idx, mmUVD_REG_XX_MASK), 0x10, 0, indirect);
1001         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
1002                 VCN, inst_idx, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect);
1003
1004         /* enable LMI MC and UMC channels */
1005         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
1006                 VCN, inst_idx, mmUVD_LMI_CTRL2), 0, 0, indirect);
1007
1008         /* unblock VCPU register access */
1009         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
1010                 VCN, inst_idx, mmUVD_RB_ARB_CTRL), 0, 0, indirect);
1011
1012         tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
1013         tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
1014         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
1015                 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect);
1016
1017         /* enable master interrupt */
1018         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
1019                 VCN, inst_idx, mmUVD_MASTINT_EN),
1020                 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
1021
1022         /* add nop to workaround PSP size check */
1023         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
1024                 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect);
1025
1026         if (indirect)
1027                 psp_update_vcn_sram(adev, inst_idx, adev->vcn.inst[inst_idx].dpg_sram_gpu_addr,
1028                         (uint32_t)((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr -
1029                                 (uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr));
1030
1031         ring = &adev->vcn.inst[inst_idx].ring_dec;
1032         /* force RBC into idle state */
1033         rb_bufsz = order_base_2(ring->ring_size);
1034         tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
1035         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1036         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1037         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1038         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
1039         WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_CNTL, tmp);
1040
1041         /* Stall DPG before WPTR/RPTR reset */
1042         WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),
1043                 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK,
1044                 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
1045         fw_shared->multi_queue.decode_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET);
1046
1047         /* set the write pointer delay */
1048         WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR_CNTL, 0);
1049
1050         /* set the wb address */
1051         WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR_ADDR,
1052                 (upper_32_bits(ring->gpu_addr) >> 2));
1053
1054         /* programm the RB_BASE for ring buffer */
1055         WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
1056                 lower_32_bits(ring->gpu_addr));
1057         WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
1058                 upper_32_bits(ring->gpu_addr));
1059
1060         /* Initialize the ring buffer's read and write pointers */
1061         WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, 0);
1062
1063         WREG32_SOC15(VCN, inst_idx, mmUVD_SCRATCH2, 0);
1064
1065         ring->wptr = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR);
1066         WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR,
1067                 lower_32_bits(ring->wptr));
1068
1069         /* Reset FW shared memory RBC WPTR/RPTR */
1070         fw_shared->rb.rptr = 0;
1071         fw_shared->rb.wptr = lower_32_bits(ring->wptr);
1072
1073         /*resetting done, fw can check RB ring */
1074         fw_shared->multi_queue.decode_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET);
1075
1076         /* Unstall DPG */
1077         WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),
1078                 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
1079
1080         return 0;
1081 }
1082
1083 static int vcn_v3_0_start(struct amdgpu_device *adev)
1084 {
1085         volatile struct amdgpu_fw_shared *fw_shared;
1086         struct amdgpu_ring *ring;
1087         uint32_t rb_bufsz, tmp;
1088         int i, j, k, r;
1089
1090         if (adev->pm.dpm_enabled)
1091                 amdgpu_dpm_enable_uvd(adev, true);
1092
1093         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1094                 if (adev->vcn.harvest_config & (1 << i))
1095                         continue;
1096
1097                 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG){
1098                         r = vcn_v3_0_start_dpg_mode(adev, i, adev->vcn.indirect_sram);
1099                         continue;
1100                 }
1101
1102                 /* disable VCN power gating */
1103                 vcn_v3_0_disable_static_power_gating(adev, i);
1104
1105                 /* set VCN status busy */
1106                 tmp = RREG32_SOC15(VCN, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;
1107                 WREG32_SOC15(VCN, i, mmUVD_STATUS, tmp);
1108
1109                 /*SW clock gating */
1110                 vcn_v3_0_disable_clock_gating(adev, i);
1111
1112                 /* enable VCPU clock */
1113                 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),
1114                         UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);
1115
1116                 /* disable master interrupt */
1117                 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 0,
1118                         ~UVD_MASTINT_EN__VCPU_EN_MASK);
1119
1120                 /* enable LMI MC and UMC channels */
1121                 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_LMI_CTRL2), 0,
1122                         ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
1123
1124                 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET);
1125                 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
1126                 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
1127                 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp);
1128
1129                 /* setup mmUVD_LMI_CTRL */
1130                 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL);
1131                 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL, tmp |
1132                         UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
1133                         UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
1134                         UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
1135                         UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
1136
1137                 /* setup mmUVD_MPC_CNTL */
1138                 tmp = RREG32_SOC15(VCN, i, mmUVD_MPC_CNTL);
1139                 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
1140                 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
1141                 WREG32_SOC15(VCN, i, mmUVD_MPC_CNTL, tmp);
1142
1143                 /* setup UVD_MPC_SET_MUXA0 */
1144                 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXA0,
1145                         ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
1146                         (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
1147                         (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
1148                         (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
1149
1150                 /* setup UVD_MPC_SET_MUXB0 */
1151                 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXB0,
1152                         ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
1153                         (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
1154                         (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
1155                         (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
1156
1157                 /* setup mmUVD_MPC_SET_MUX */
1158                 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUX,
1159                         ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
1160                         (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
1161                         (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
1162
1163                 vcn_v3_0_mc_resume(adev, i);
1164
1165                 /* VCN global tiling registers */
1166                 WREG32_SOC15(VCN, i, mmUVD_GFX10_ADDR_CONFIG,
1167                         adev->gfx.config.gb_addr_config);
1168
1169                 /* unblock VCPU register access */
1170                 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 0,
1171                         ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
1172
1173                 /* release VCPU reset to boot */
1174                 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,
1175                         ~UVD_VCPU_CNTL__BLK_RST_MASK);
1176
1177                 for (j = 0; j < 10; ++j) {
1178                         uint32_t status;
1179
1180                         for (k = 0; k < 100; ++k) {
1181                                 status = RREG32_SOC15(VCN, i, mmUVD_STATUS);
1182                                 if (status & 2)
1183                                         break;
1184                                 mdelay(10);
1185                         }
1186                         r = 0;
1187                         if (status & 2)
1188                                 break;
1189
1190                         DRM_ERROR("VCN[%d] decode not responding, trying to reset the VCPU!!!\n", i);
1191                         WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),
1192                                 UVD_VCPU_CNTL__BLK_RST_MASK,
1193                                 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1194                         mdelay(10);
1195                         WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,
1196                                 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1197
1198                         mdelay(10);
1199                         r = -1;
1200                 }
1201
1202                 if (r) {
1203                         DRM_ERROR("VCN[%d] decode not responding, giving up!!!\n", i);
1204                         return r;
1205                 }
1206
1207                 /* enable master interrupt */
1208                 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN),
1209                         UVD_MASTINT_EN__VCPU_EN_MASK,
1210                         ~UVD_MASTINT_EN__VCPU_EN_MASK);
1211
1212                 /* clear the busy bit of VCN_STATUS */
1213                 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 0,
1214                         ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
1215
1216                 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_VMID, 0);
1217
1218                 ring = &adev->vcn.inst[i].ring_dec;
1219                 /* force RBC into idle state */
1220                 rb_bufsz = order_base_2(ring->ring_size);
1221                 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
1222                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1223                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1224                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1225                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
1226                 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_CNTL, tmp);
1227
1228                 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
1229                 fw_shared->multi_queue.decode_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET);
1230
1231                 /* programm the RB_BASE for ring buffer */
1232                 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
1233                         lower_32_bits(ring->gpu_addr));
1234                 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
1235                         upper_32_bits(ring->gpu_addr));
1236
1237                 /* Initialize the ring buffer's read and write pointers */
1238                 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR, 0);
1239
1240                 WREG32_SOC15(VCN, i, mmUVD_SCRATCH2, 0);
1241                 ring->wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR);
1242                 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_WPTR,
1243                         lower_32_bits(ring->wptr));
1244                 fw_shared->rb.wptr = lower_32_bits(ring->wptr);
1245                 fw_shared->multi_queue.decode_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET);
1246
1247                 if (adev->ip_versions[UVD_HWIP][0] != IP_VERSION(3, 0, 33)) {
1248                         fw_shared->multi_queue.encode_generalpurpose_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET);
1249                         ring = &adev->vcn.inst[i].ring_enc[0];
1250                         WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1251                         WREG32_SOC15(VCN, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1252                         WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO, ring->gpu_addr);
1253                         WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1254                         WREG32_SOC15(VCN, i, mmUVD_RB_SIZE, ring->ring_size / 4);
1255                         fw_shared->multi_queue.encode_generalpurpose_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET);
1256
1257                         fw_shared->multi_queue.encode_lowlatency_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET);
1258                         ring = &adev->vcn.inst[i].ring_enc[1];
1259                         WREG32_SOC15(VCN, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
1260                         WREG32_SOC15(VCN, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1261                         WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO2, ring->gpu_addr);
1262                         WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
1263                         WREG32_SOC15(VCN, i, mmUVD_RB_SIZE2, ring->ring_size / 4);
1264                         fw_shared->multi_queue.encode_lowlatency_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET);
1265                 }
1266         }
1267
1268         return 0;
1269 }
1270
1271 static int vcn_v3_0_start_sriov(struct amdgpu_device *adev)
1272 {
1273         int i, j;
1274         struct amdgpu_ring *ring;
1275         uint64_t cache_addr;
1276         uint64_t rb_addr;
1277         uint64_t ctx_addr;
1278         uint32_t param, resp, expected;
1279         uint32_t offset, cache_size;
1280         uint32_t tmp, timeout;
1281
1282         struct amdgpu_mm_table *table = &adev->virt.mm_table;
1283         uint32_t *table_loc;
1284         uint32_t table_size;
1285         uint32_t size, size_dw;
1286
1287         struct mmsch_v3_0_cmd_direct_write
1288                 direct_wt = { {0} };
1289         struct mmsch_v3_0_cmd_direct_read_modify_write
1290                 direct_rd_mod_wt = { {0} };
1291         struct mmsch_v3_0_cmd_end end = { {0} };
1292         struct mmsch_v3_0_init_header header;
1293
1294         direct_wt.cmd_header.command_type =
1295                 MMSCH_COMMAND__DIRECT_REG_WRITE;
1296         direct_rd_mod_wt.cmd_header.command_type =
1297                 MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE;
1298         end.cmd_header.command_type =
1299                 MMSCH_COMMAND__END;
1300
1301         header.version = MMSCH_VERSION;
1302         header.total_size = sizeof(struct mmsch_v3_0_init_header) >> 2;
1303         for (i = 0; i < AMDGPU_MAX_VCN_INSTANCES; i++) {
1304                 header.inst[i].init_status = 0;
1305                 header.inst[i].table_offset = 0;
1306                 header.inst[i].table_size = 0;
1307         }
1308
1309         table_loc = (uint32_t *)table->cpu_addr;
1310         table_loc += header.total_size;
1311         for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1312                 if (adev->vcn.harvest_config & (1 << i))
1313                         continue;
1314
1315                 table_size = 0;
1316
1317                 MMSCH_V3_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, i,
1318                         mmUVD_STATUS),
1319                         ~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY);
1320
1321                 cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
1322
1323                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1324                         MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1325                                 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
1326                                 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo);
1327                         MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1328                                 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
1329                                 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi);
1330                         offset = 0;
1331                         MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1332                                 mmUVD_VCPU_CACHE_OFFSET0),
1333                                 0);
1334                 } else {
1335                         MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1336                                 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
1337                                 lower_32_bits(adev->vcn.inst[i].gpu_addr));
1338                         MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1339                                 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
1340                                 upper_32_bits(adev->vcn.inst[i].gpu_addr));
1341                         offset = cache_size;
1342                         MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1343                                 mmUVD_VCPU_CACHE_OFFSET0),
1344                                 AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
1345                 }
1346
1347                 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1348                         mmUVD_VCPU_CACHE_SIZE0),
1349                         cache_size);
1350
1351                 cache_addr = adev->vcn.inst[i].gpu_addr + offset;
1352                 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1353                         mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
1354                         lower_32_bits(cache_addr));
1355                 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1356                         mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
1357                         upper_32_bits(cache_addr));
1358                 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1359                         mmUVD_VCPU_CACHE_OFFSET1),
1360                         0);
1361                 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1362                         mmUVD_VCPU_CACHE_SIZE1),
1363                         AMDGPU_VCN_STACK_SIZE);
1364
1365                 cache_addr = adev->vcn.inst[i].gpu_addr + offset +
1366                         AMDGPU_VCN_STACK_SIZE;
1367                 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1368                         mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
1369                         lower_32_bits(cache_addr));
1370                 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1371                         mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
1372                         upper_32_bits(cache_addr));
1373                 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1374                         mmUVD_VCPU_CACHE_OFFSET2),
1375                         0);
1376                 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1377                         mmUVD_VCPU_CACHE_SIZE2),
1378                         AMDGPU_VCN_CONTEXT_SIZE);
1379
1380                 for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
1381                         ring = &adev->vcn.inst[i].ring_enc[j];
1382                         ring->wptr = 0;
1383                         rb_addr = ring->gpu_addr;
1384                         MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1385                                 mmUVD_RB_BASE_LO),
1386                                 lower_32_bits(rb_addr));
1387                         MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1388                                 mmUVD_RB_BASE_HI),
1389                                 upper_32_bits(rb_addr));
1390                         MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1391                                 mmUVD_RB_SIZE),
1392                                 ring->ring_size / 4);
1393                 }
1394
1395                 ring = &adev->vcn.inst[i].ring_dec;
1396                 ring->wptr = 0;
1397                 rb_addr = ring->gpu_addr;
1398                 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1399                         mmUVD_LMI_RBC_RB_64BIT_BAR_LOW),
1400                         lower_32_bits(rb_addr));
1401                 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1402                         mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH),
1403                         upper_32_bits(rb_addr));
1404                 /* force RBC into idle state */
1405                 tmp = order_base_2(ring->ring_size);
1406                 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, tmp);
1407                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1408                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1409                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1410                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
1411                 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1412                         mmUVD_RBC_RB_CNTL),
1413                         tmp);
1414
1415                 /* add end packet */
1416                 MMSCH_V3_0_INSERT_END();
1417
1418                 /* refine header */
1419                 header.inst[i].init_status = 0;
1420                 header.inst[i].table_offset = header.total_size;
1421                 header.inst[i].table_size = table_size;
1422                 header.total_size += table_size;
1423         }
1424
1425         /* Update init table header in memory */
1426         size = sizeof(struct mmsch_v3_0_init_header);
1427         table_loc = (uint32_t *)table->cpu_addr;
1428         memcpy((void *)table_loc, &header, size);
1429
1430         /* message MMSCH (in VCN[0]) to initialize this client
1431          * 1, write to mmsch_vf_ctx_addr_lo/hi register with GPU mc addr
1432          * of memory descriptor location
1433          */
1434         ctx_addr = table->gpu_addr;
1435         WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr));
1436         WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr));
1437
1438         /* 2, update vmid of descriptor */
1439         tmp = RREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID);
1440         tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK;
1441         /* use domain0 for MM scheduler */
1442         tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT);
1443         WREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID, tmp);
1444
1445         /* 3, notify mmsch about the size of this descriptor */
1446         size = header.total_size;
1447         WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_SIZE, size);
1448
1449         /* 4, set resp to zero */
1450         WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP, 0);
1451
1452         /* 5, kick off the initialization and wait until
1453          * MMSCH_VF_MAILBOX_RESP becomes non-zero
1454          */
1455         param = 0x10000001;
1456         WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_HOST, param);
1457         tmp = 0;
1458         timeout = 1000;
1459         resp = 0;
1460         expected = param + 1;
1461         while (resp != expected) {
1462                 resp = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP);
1463                 if (resp == expected)
1464                         break;
1465
1466                 udelay(10);
1467                 tmp = tmp + 10;
1468                 if (tmp >= timeout) {
1469                         DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\
1470                                 " waiting for mmMMSCH_VF_MAILBOX_RESP "\
1471                                 "(expected=0x%08x, readback=0x%08x)\n",
1472                                 tmp, expected, resp);
1473                         return -EBUSY;
1474                 }
1475         }
1476
1477         return 0;
1478 }
1479
1480 static int vcn_v3_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)
1481 {
1482         uint32_t tmp;
1483
1484         /* Wait for power status to be 1 */
1485         SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1,
1486                 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1487
1488         /* wait for read ptr to be equal to write ptr */
1489         tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR);
1490         SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF);
1491
1492         tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2);
1493         SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF);
1494
1495         tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;
1496         SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF);
1497
1498         SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1,
1499                 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1500
1501         /* disable dynamic power gating mode */
1502         WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 0,
1503                 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
1504
1505         return 0;
1506 }
1507
1508 static int vcn_v3_0_stop(struct amdgpu_device *adev)
1509 {
1510         uint32_t tmp;
1511         int i, r = 0;
1512
1513         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1514                 if (adev->vcn.harvest_config & (1 << i))
1515                         continue;
1516
1517                 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
1518                         r = vcn_v3_0_stop_dpg_mode(adev, i);
1519                         continue;
1520                 }
1521
1522                 /* wait for vcn idle */
1523                 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7);
1524                 if (r)
1525                         return r;
1526
1527                 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
1528                         UVD_LMI_STATUS__READ_CLEAN_MASK |
1529                         UVD_LMI_STATUS__WRITE_CLEAN_MASK |
1530                         UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
1531                 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp);
1532                 if (r)
1533                         return r;
1534
1535                 /* disable LMI UMC channel */
1536                 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2);
1537                 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
1538                 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2, tmp);
1539                 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK|
1540                         UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
1541                 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp);
1542                 if (r)
1543                         return r;
1544
1545                 /* block VCPU register access */
1546                 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL),
1547                         UVD_RB_ARB_CTRL__VCPU_DIS_MASK,
1548                         ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
1549
1550                 /* reset VCPU */
1551                 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),
1552                         UVD_VCPU_CNTL__BLK_RST_MASK,
1553                         ~UVD_VCPU_CNTL__BLK_RST_MASK);
1554
1555                 /* disable VCPU clock */
1556                 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,
1557                         ~(UVD_VCPU_CNTL__CLK_EN_MASK));
1558
1559                 /* apply soft reset */
1560                 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET);
1561                 tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
1562                 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp);
1563                 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET);
1564                 tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
1565                 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp);
1566
1567                 /* clear status */
1568                 WREG32_SOC15(VCN, i, mmUVD_STATUS, 0);
1569
1570                 /* apply HW clock gating */
1571                 vcn_v3_0_enable_clock_gating(adev, i);
1572
1573                 /* enable VCN power gating */
1574                 vcn_v3_0_enable_static_power_gating(adev, i);
1575         }
1576
1577         if (adev->pm.dpm_enabled)
1578                 amdgpu_dpm_enable_uvd(adev, false);
1579
1580         return 0;
1581 }
1582
1583 static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev,
1584                    int inst_idx, struct dpg_pause_state *new_state)
1585 {
1586         volatile struct amdgpu_fw_shared *fw_shared;
1587         struct amdgpu_ring *ring;
1588         uint32_t reg_data = 0;
1589         int ret_code;
1590
1591         /* pause/unpause if state is changed */
1592         if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {
1593                 DRM_DEBUG("dpg pause state changed %d -> %d",
1594                         adev->vcn.inst[inst_idx].pause_state.fw_based,  new_state->fw_based);
1595                 reg_data = RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE) &
1596                         (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
1597
1598                 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) {
1599                         ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 0x1,
1600                                 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1601
1602                         if (!ret_code) {
1603                                 /* pause DPG */
1604                                 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1605                                 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data);
1606
1607                                 /* wait for ACK */
1608                                 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_DPG_PAUSE,
1609                                         UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK,
1610                                         UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
1611
1612                                 /* Stall DPG before WPTR/RPTR reset */
1613                                 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),
1614                                         UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK,
1615                                         ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
1616
1617                                 if (adev->ip_versions[UVD_HWIP][0] != IP_VERSION(3, 0, 33)) {
1618                                         /* Restore */
1619                                         fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
1620                                         fw_shared->multi_queue.encode_generalpurpose_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET);
1621                                         ring = &adev->vcn.inst[inst_idx].ring_enc[0];
1622                                         ring->wptr = 0;
1623                                         WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO, ring->gpu_addr);
1624                                         WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1625                                         WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE, ring->ring_size / 4);
1626                                         WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1627                                         WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1628                                         fw_shared->multi_queue.encode_generalpurpose_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET);
1629
1630                                         fw_shared->multi_queue.encode_lowlatency_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET);
1631                                         ring = &adev->vcn.inst[inst_idx].ring_enc[1];
1632                                         ring->wptr = 0;
1633                                         WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO2, ring->gpu_addr);
1634                                         WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
1635                                         WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE2, ring->ring_size / 4);
1636                                         WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
1637                                         WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1638                                         fw_shared->multi_queue.encode_lowlatency_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET);
1639
1640                                         /* restore wptr/rptr with pointers saved in FW shared memory*/
1641                                         WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, fw_shared->rb.rptr);
1642                                         WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR, fw_shared->rb.wptr);
1643                                 }
1644
1645                                 /* Unstall DPG */
1646                                 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),
1647                                         0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
1648
1649                                 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS,
1650                                         UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1651                         }
1652                 } else {
1653                         /* unpause dpg, no need to wait */
1654                         reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1655                         WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data);
1656                 }
1657                 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;
1658         }
1659
1660         return 0;
1661 }
1662
1663 /**
1664  * vcn_v3_0_dec_ring_get_rptr - get read pointer
1665  *
1666  * @ring: amdgpu_ring pointer
1667  *
1668  * Returns the current hardware read pointer
1669  */
1670 static uint64_t vcn_v3_0_dec_ring_get_rptr(struct amdgpu_ring *ring)
1671 {
1672         struct amdgpu_device *adev = ring->adev;
1673
1674         return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_RPTR);
1675 }
1676
1677 /**
1678  * vcn_v3_0_dec_ring_get_wptr - get write pointer
1679  *
1680  * @ring: amdgpu_ring pointer
1681  *
1682  * Returns the current hardware write pointer
1683  */
1684 static uint64_t vcn_v3_0_dec_ring_get_wptr(struct amdgpu_ring *ring)
1685 {
1686         struct amdgpu_device *adev = ring->adev;
1687
1688         if (ring->use_doorbell)
1689                 return adev->wb.wb[ring->wptr_offs];
1690         else
1691                 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR);
1692 }
1693
1694 /**
1695  * vcn_v3_0_dec_ring_set_wptr - set write pointer
1696  *
1697  * @ring: amdgpu_ring pointer
1698  *
1699  * Commits the write pointer to the hardware
1700  */
1701 static void vcn_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
1702 {
1703         struct amdgpu_device *adev = ring->adev;
1704         volatile struct amdgpu_fw_shared *fw_shared;
1705
1706         if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
1707                 /*whenever update RBC_RB_WPTR, we save the wptr in shared rb.wptr and scratch2 */
1708                 fw_shared = adev->vcn.inst[ring->me].fw_shared.cpu_addr;
1709                 fw_shared->rb.wptr = lower_32_bits(ring->wptr);
1710                 WREG32_SOC15(VCN, ring->me, mmUVD_SCRATCH2,
1711                         lower_32_bits(ring->wptr));
1712         }
1713
1714         if (ring->use_doorbell) {
1715                 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
1716                 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1717         } else {
1718                 WREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
1719         }
1720 }
1721
1722 static void vcn_v3_0_dec_sw_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
1723                                 u64 seq, uint32_t flags)
1724 {
1725         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1726
1727         amdgpu_ring_write(ring, VCN_DEC_SW_CMD_FENCE);
1728         amdgpu_ring_write(ring, addr);
1729         amdgpu_ring_write(ring, upper_32_bits(addr));
1730         amdgpu_ring_write(ring, seq);
1731         amdgpu_ring_write(ring, VCN_DEC_SW_CMD_TRAP);
1732 }
1733
1734 static void vcn_v3_0_dec_sw_ring_insert_end(struct amdgpu_ring *ring)
1735 {
1736         amdgpu_ring_write(ring, VCN_DEC_SW_CMD_END);
1737 }
1738
1739 static void vcn_v3_0_dec_sw_ring_emit_ib(struct amdgpu_ring *ring,
1740                                struct amdgpu_job *job,
1741                                struct amdgpu_ib *ib,
1742                                uint32_t flags)
1743 {
1744         uint32_t vmid = AMDGPU_JOB_GET_VMID(job);
1745
1746         amdgpu_ring_write(ring, VCN_DEC_SW_CMD_IB);
1747         amdgpu_ring_write(ring, vmid);
1748         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1749         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1750         amdgpu_ring_write(ring, ib->length_dw);
1751 }
1752
1753 static void vcn_v3_0_dec_sw_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1754                                 uint32_t val, uint32_t mask)
1755 {
1756         amdgpu_ring_write(ring, VCN_DEC_SW_CMD_REG_WAIT);
1757         amdgpu_ring_write(ring, reg << 2);
1758         amdgpu_ring_write(ring, mask);
1759         amdgpu_ring_write(ring, val);
1760 }
1761
1762 static void vcn_v3_0_dec_sw_ring_emit_vm_flush(struct amdgpu_ring *ring,
1763                                 uint32_t vmid, uint64_t pd_addr)
1764 {
1765         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1766         uint32_t data0, data1, mask;
1767
1768         pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1769
1770         /* wait for register write */
1771         data0 = hub->ctx0_ptb_addr_lo32 + vmid * hub->ctx_addr_distance;
1772         data1 = lower_32_bits(pd_addr);
1773         mask = 0xffffffff;
1774         vcn_v3_0_dec_sw_ring_emit_reg_wait(ring, data0, data1, mask);
1775 }
1776
1777 static void vcn_v3_0_dec_sw_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val)
1778 {
1779         amdgpu_ring_write(ring, VCN_DEC_SW_CMD_REG_WRITE);
1780         amdgpu_ring_write(ring, reg << 2);
1781         amdgpu_ring_write(ring, val);
1782 }
1783
1784 static const struct amdgpu_ring_funcs vcn_v3_0_dec_sw_ring_vm_funcs = {
1785         .type = AMDGPU_RING_TYPE_VCN_DEC,
1786         .align_mask = 0x3f,
1787         .nop = VCN_DEC_SW_CMD_NO_OP,
1788         .vmhub = AMDGPU_MMHUB_0,
1789         .get_rptr = vcn_v3_0_dec_ring_get_rptr,
1790         .get_wptr = vcn_v3_0_dec_ring_get_wptr,
1791         .set_wptr = vcn_v3_0_dec_ring_set_wptr,
1792         .emit_frame_size =
1793                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1794                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
1795                 4 + /* vcn_v3_0_dec_sw_ring_emit_vm_flush */
1796                 5 + 5 + /* vcn_v3_0_dec_sw_ring_emit_fdec_swe x2 vm fdec_swe */
1797                 1, /* vcn_v3_0_dec_sw_ring_insert_end */
1798         .emit_ib_size = 5, /* vcn_v3_0_dec_sw_ring_emit_ib */
1799         .emit_ib = vcn_v3_0_dec_sw_ring_emit_ib,
1800         .emit_fence = vcn_v3_0_dec_sw_ring_emit_fence,
1801         .emit_vm_flush = vcn_v3_0_dec_sw_ring_emit_vm_flush,
1802         .test_ring = amdgpu_vcn_dec_sw_ring_test_ring,
1803         .test_ib = NULL,//amdgpu_vcn_dec_sw_ring_test_ib,
1804         .insert_nop = amdgpu_ring_insert_nop,
1805         .insert_end = vcn_v3_0_dec_sw_ring_insert_end,
1806         .pad_ib = amdgpu_ring_generic_pad_ib,
1807         .begin_use = amdgpu_vcn_ring_begin_use,
1808         .end_use = amdgpu_vcn_ring_end_use,
1809         .emit_wreg = vcn_v3_0_dec_sw_ring_emit_wreg,
1810         .emit_reg_wait = vcn_v3_0_dec_sw_ring_emit_reg_wait,
1811         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1812 };
1813
1814 static int vcn_v3_0_limit_sched(struct amdgpu_cs_parser *p)
1815 {
1816         struct drm_gpu_scheduler **scheds;
1817
1818         /* The create msg must be in the first IB submitted */
1819         if (atomic_read(&p->entity->fence_seq))
1820                 return -EINVAL;
1821
1822         scheds = p->adev->gpu_sched[AMDGPU_HW_IP_VCN_DEC]
1823                 [AMDGPU_RING_PRIO_DEFAULT].sched;
1824         drm_sched_entity_modify_sched(p->entity, scheds, 1);
1825         return 0;
1826 }
1827
1828 static int vcn_v3_0_dec_msg(struct amdgpu_cs_parser *p, uint64_t addr)
1829 {
1830         struct ttm_operation_ctx ctx = { false, false };
1831         struct amdgpu_bo_va_mapping *map;
1832         uint32_t *msg, num_buffers;
1833         struct amdgpu_bo *bo;
1834         uint64_t start, end;
1835         unsigned int i;
1836         void * ptr;
1837         int r;
1838
1839         addr &= AMDGPU_GMC_HOLE_MASK;
1840         r = amdgpu_cs_find_mapping(p, addr, &bo, &map);
1841         if (r) {
1842                 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr);
1843                 return r;
1844         }
1845
1846         start = map->start * AMDGPU_GPU_PAGE_SIZE;
1847         end = (map->last + 1) * AMDGPU_GPU_PAGE_SIZE;
1848         if (addr & 0x7) {
1849                 DRM_ERROR("VCN messages must be 8 byte aligned!\n");
1850                 return -EINVAL;
1851         }
1852
1853         bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
1854         amdgpu_bo_placement_from_domain(bo, bo->allowed_domains);
1855         r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
1856         if (r) {
1857                 DRM_ERROR("Failed validating the VCN message BO (%d)!\n", r);
1858                 return r;
1859         }
1860
1861         r = amdgpu_bo_kmap(bo, &ptr);
1862         if (r) {
1863                 DRM_ERROR("Failed mapping the VCN message (%d)!\n", r);
1864                 return r;
1865         }
1866
1867         msg = ptr + addr - start;
1868
1869         /* Check length */
1870         if (msg[1] > end - addr) {
1871                 r = -EINVAL;
1872                 goto out;
1873         }
1874
1875         if (msg[3] != RDECODE_MSG_CREATE)
1876                 goto out;
1877
1878         num_buffers = msg[2];
1879         for (i = 0, msg = &msg[6]; i < num_buffers; ++i, msg += 4) {
1880                 uint32_t offset, size, *create;
1881
1882                 if (msg[0] != RDECODE_MESSAGE_CREATE)
1883                         continue;
1884
1885                 offset = msg[1];
1886                 size = msg[2];
1887
1888                 if (offset + size > end) {
1889                         r = -EINVAL;
1890                         goto out;
1891                 }
1892
1893                 create = ptr + addr + offset - start;
1894
1895                 /* H246, HEVC and VP9 can run on any instance */
1896                 if (create[0] == 0x7 || create[0] == 0x10 || create[0] == 0x11)
1897                         continue;
1898
1899                 r = vcn_v3_0_limit_sched(p);
1900                 if (r)
1901                         goto out;
1902         }
1903
1904 out:
1905         amdgpu_bo_kunmap(bo);
1906         return r;
1907 }
1908
1909 static int vcn_v3_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p,
1910                                            uint32_t ib_idx)
1911 {
1912         struct amdgpu_ring *ring = to_amdgpu_ring(p->entity->rq->sched);
1913         struct amdgpu_ib *ib = &p->job->ibs[ib_idx];
1914         uint32_t msg_lo = 0, msg_hi = 0;
1915         unsigned i;
1916         int r;
1917
1918         /* The first instance can decode anything */
1919         if (!ring->me)
1920                 return 0;
1921
1922         for (i = 0; i < ib->length_dw; i += 2) {
1923                 uint32_t reg = amdgpu_get_ib_value(p, ib_idx, i);
1924                 uint32_t val = amdgpu_get_ib_value(p, ib_idx, i + 1);
1925
1926                 if (reg == PACKET0(p->adev->vcn.internal.data0, 0)) {
1927                         msg_lo = val;
1928                 } else if (reg == PACKET0(p->adev->vcn.internal.data1, 0)) {
1929                         msg_hi = val;
1930                 } else if (reg == PACKET0(p->adev->vcn.internal.cmd, 0) &&
1931                            val == 0) {
1932                         r = vcn_v3_0_dec_msg(p, ((u64)msg_hi) << 32 | msg_lo);
1933                         if (r)
1934                                 return r;
1935                 }
1936         }
1937         return 0;
1938 }
1939
1940 static const struct amdgpu_ring_funcs vcn_v3_0_dec_ring_vm_funcs = {
1941         .type = AMDGPU_RING_TYPE_VCN_DEC,
1942         .align_mask = 0xf,
1943         .vmhub = AMDGPU_MMHUB_0,
1944         .get_rptr = vcn_v3_0_dec_ring_get_rptr,
1945         .get_wptr = vcn_v3_0_dec_ring_get_wptr,
1946         .set_wptr = vcn_v3_0_dec_ring_set_wptr,
1947         .patch_cs_in_place = vcn_v3_0_ring_patch_cs_in_place,
1948         .emit_frame_size =
1949                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
1950                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
1951                 8 + /* vcn_v2_0_dec_ring_emit_vm_flush */
1952                 14 + 14 + /* vcn_v2_0_dec_ring_emit_fence x2 vm fence */
1953                 6,
1954         .emit_ib_size = 8, /* vcn_v2_0_dec_ring_emit_ib */
1955         .emit_ib = vcn_v2_0_dec_ring_emit_ib,
1956         .emit_fence = vcn_v2_0_dec_ring_emit_fence,
1957         .emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush,
1958         .test_ring = vcn_v2_0_dec_ring_test_ring,
1959         .test_ib = amdgpu_vcn_dec_ring_test_ib,
1960         .insert_nop = vcn_v2_0_dec_ring_insert_nop,
1961         .insert_start = vcn_v2_0_dec_ring_insert_start,
1962         .insert_end = vcn_v2_0_dec_ring_insert_end,
1963         .pad_ib = amdgpu_ring_generic_pad_ib,
1964         .begin_use = amdgpu_vcn_ring_begin_use,
1965         .end_use = amdgpu_vcn_ring_end_use,
1966         .emit_wreg = vcn_v2_0_dec_ring_emit_wreg,
1967         .emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait,
1968         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1969 };
1970
1971 /**
1972  * vcn_v3_0_enc_ring_get_rptr - get enc read pointer
1973  *
1974  * @ring: amdgpu_ring pointer
1975  *
1976  * Returns the current hardware enc read pointer
1977  */
1978 static uint64_t vcn_v3_0_enc_ring_get_rptr(struct amdgpu_ring *ring)
1979 {
1980         struct amdgpu_device *adev = ring->adev;
1981
1982         if (ring == &adev->vcn.inst[ring->me].ring_enc[0])
1983                 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR);
1984         else
1985                 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR2);
1986 }
1987
1988 /**
1989  * vcn_v3_0_enc_ring_get_wptr - get enc write pointer
1990  *
1991  * @ring: amdgpu_ring pointer
1992  *
1993  * Returns the current hardware enc write pointer
1994  */
1995 static uint64_t vcn_v3_0_enc_ring_get_wptr(struct amdgpu_ring *ring)
1996 {
1997         struct amdgpu_device *adev = ring->adev;
1998
1999         if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) {
2000                 if (ring->use_doorbell)
2001                         return adev->wb.wb[ring->wptr_offs];
2002                 else
2003                         return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR);
2004         } else {
2005                 if (ring->use_doorbell)
2006                         return adev->wb.wb[ring->wptr_offs];
2007                 else
2008                         return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2);
2009         }
2010 }
2011
2012 /**
2013  * vcn_v3_0_enc_ring_set_wptr - set enc write pointer
2014  *
2015  * @ring: amdgpu_ring pointer
2016  *
2017  * Commits the enc write pointer to the hardware
2018  */
2019 static void vcn_v3_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
2020 {
2021         struct amdgpu_device *adev = ring->adev;
2022
2023         if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) {
2024                 if (ring->use_doorbell) {
2025                         adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
2026                         WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
2027                 } else {
2028                         WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
2029                 }
2030         } else {
2031                 if (ring->use_doorbell) {
2032                         adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
2033                         WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
2034                 } else {
2035                         WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
2036                 }
2037         }
2038 }
2039
2040 static const struct amdgpu_ring_funcs vcn_v3_0_enc_ring_vm_funcs = {
2041         .type = AMDGPU_RING_TYPE_VCN_ENC,
2042         .align_mask = 0x3f,
2043         .nop = VCN_ENC_CMD_NO_OP,
2044         .vmhub = AMDGPU_MMHUB_0,
2045         .get_rptr = vcn_v3_0_enc_ring_get_rptr,
2046         .get_wptr = vcn_v3_0_enc_ring_get_wptr,
2047         .set_wptr = vcn_v3_0_enc_ring_set_wptr,
2048         .emit_frame_size =
2049                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2050                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
2051                 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */
2052                 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */
2053                 1, /* vcn_v2_0_enc_ring_insert_end */
2054         .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */
2055         .emit_ib = vcn_v2_0_enc_ring_emit_ib,
2056         .emit_fence = vcn_v2_0_enc_ring_emit_fence,
2057         .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush,
2058         .test_ring = amdgpu_vcn_enc_ring_test_ring,
2059         .test_ib = amdgpu_vcn_enc_ring_test_ib,
2060         .insert_nop = amdgpu_ring_insert_nop,
2061         .insert_end = vcn_v2_0_enc_ring_insert_end,
2062         .pad_ib = amdgpu_ring_generic_pad_ib,
2063         .begin_use = amdgpu_vcn_ring_begin_use,
2064         .end_use = amdgpu_vcn_ring_end_use,
2065         .emit_wreg = vcn_v2_0_enc_ring_emit_wreg,
2066         .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait,
2067         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2068 };
2069
2070 static void vcn_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev)
2071 {
2072         int i;
2073
2074         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
2075                 if (adev->vcn.harvest_config & (1 << i))
2076                         continue;
2077
2078                 if (!DEC_SW_RING_ENABLED)
2079                         adev->vcn.inst[i].ring_dec.funcs = &vcn_v3_0_dec_ring_vm_funcs;
2080                 else
2081                         adev->vcn.inst[i].ring_dec.funcs = &vcn_v3_0_dec_sw_ring_vm_funcs;
2082                 adev->vcn.inst[i].ring_dec.me = i;
2083                 DRM_INFO("VCN(%d) decode%s is enabled in VM mode\n", i,
2084                           DEC_SW_RING_ENABLED?"(Software Ring)":"");
2085         }
2086 }
2087
2088 static void vcn_v3_0_set_enc_ring_funcs(struct amdgpu_device *adev)
2089 {
2090         int i, j;
2091
2092         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
2093                 if (adev->vcn.harvest_config & (1 << i))
2094                         continue;
2095
2096                 for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
2097                         adev->vcn.inst[i].ring_enc[j].funcs = &vcn_v3_0_enc_ring_vm_funcs;
2098                         adev->vcn.inst[i].ring_enc[j].me = i;
2099                 }
2100                 if (adev->vcn.num_enc_rings > 0)
2101                         DRM_INFO("VCN(%d) encode is enabled in VM mode\n", i);
2102         }
2103 }
2104
2105 static bool vcn_v3_0_is_idle(void *handle)
2106 {
2107         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2108         int i, ret = 1;
2109
2110         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
2111                 if (adev->vcn.harvest_config & (1 << i))
2112                         continue;
2113
2114                 ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE);
2115         }
2116
2117         return ret;
2118 }
2119
2120 static int vcn_v3_0_wait_for_idle(void *handle)
2121 {
2122         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2123         int i, ret = 0;
2124
2125         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
2126                 if (adev->vcn.harvest_config & (1 << i))
2127                         continue;
2128
2129                 ret = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE,
2130                         UVD_STATUS__IDLE);
2131                 if (ret)
2132                         return ret;
2133         }
2134
2135         return ret;
2136 }
2137
2138 static int vcn_v3_0_set_clockgating_state(void *handle,
2139                                           enum amd_clockgating_state state)
2140 {
2141         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2142         bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
2143         int i;
2144
2145         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
2146                 if (adev->vcn.harvest_config & (1 << i))
2147                         continue;
2148
2149                 if (enable) {
2150                         if (RREG32_SOC15(VCN, i, mmUVD_STATUS) != UVD_STATUS__IDLE)
2151                                 return -EBUSY;
2152                         vcn_v3_0_enable_clock_gating(adev, i);
2153                 } else {
2154                         vcn_v3_0_disable_clock_gating(adev, i);
2155                 }
2156         }
2157
2158         return 0;
2159 }
2160
2161 static int vcn_v3_0_set_powergating_state(void *handle,
2162                                           enum amd_powergating_state state)
2163 {
2164         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2165         int ret;
2166
2167         /* for SRIOV, guest should not control VCN Power-gating
2168          * MMSCH FW should control Power-gating and clock-gating
2169          * guest should avoid touching CGC and PG
2170          */
2171         if (amdgpu_sriov_vf(adev)) {
2172                 adev->vcn.cur_state = AMD_PG_STATE_UNGATE;
2173                 return 0;
2174         }
2175
2176         if(state == adev->vcn.cur_state)
2177                 return 0;
2178
2179         if (state == AMD_PG_STATE_GATE)
2180                 ret = vcn_v3_0_stop(adev);
2181         else
2182                 ret = vcn_v3_0_start(adev);
2183
2184         if(!ret)
2185                 adev->vcn.cur_state = state;
2186
2187         return ret;
2188 }
2189
2190 static int vcn_v3_0_set_interrupt_state(struct amdgpu_device *adev,
2191                                         struct amdgpu_irq_src *source,
2192                                         unsigned type,
2193                                         enum amdgpu_interrupt_state state)
2194 {
2195         return 0;
2196 }
2197
2198 static int vcn_v3_0_process_interrupt(struct amdgpu_device *adev,
2199                                       struct amdgpu_irq_src *source,
2200                                       struct amdgpu_iv_entry *entry)
2201 {
2202         uint32_t ip_instance;
2203
2204         switch (entry->client_id) {
2205         case SOC15_IH_CLIENTID_VCN:
2206                 ip_instance = 0;
2207                 break;
2208         case SOC15_IH_CLIENTID_VCN1:
2209                 ip_instance = 1;
2210                 break;
2211         default:
2212                 DRM_ERROR("Unhandled client id: %d\n", entry->client_id);
2213                 return 0;
2214         }
2215
2216         DRM_DEBUG("IH: VCN TRAP\n");
2217
2218         switch (entry->src_id) {
2219         case VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT:
2220                 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_dec);
2221                 break;
2222         case VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE:
2223                 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]);
2224                 break;
2225         case VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY:
2226                 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[1]);
2227                 break;
2228         default:
2229                 DRM_ERROR("Unhandled interrupt: %d %d\n",
2230                           entry->src_id, entry->src_data[0]);
2231                 break;
2232         }
2233
2234         return 0;
2235 }
2236
2237 static const struct amdgpu_irq_src_funcs vcn_v3_0_irq_funcs = {
2238         .set = vcn_v3_0_set_interrupt_state,
2239         .process = vcn_v3_0_process_interrupt,
2240 };
2241
2242 static void vcn_v3_0_set_irq_funcs(struct amdgpu_device *adev)
2243 {
2244         int i;
2245
2246         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
2247                 if (adev->vcn.harvest_config & (1 << i))
2248                         continue;
2249
2250                 adev->vcn.inst[i].irq.num_types = adev->vcn.num_enc_rings + 1;
2251                 adev->vcn.inst[i].irq.funcs = &vcn_v3_0_irq_funcs;
2252         }
2253 }
2254
2255 static const struct amd_ip_funcs vcn_v3_0_ip_funcs = {
2256         .name = "vcn_v3_0",
2257         .early_init = vcn_v3_0_early_init,
2258         .late_init = NULL,
2259         .sw_init = vcn_v3_0_sw_init,
2260         .sw_fini = vcn_v3_0_sw_fini,
2261         .hw_init = vcn_v3_0_hw_init,
2262         .hw_fini = vcn_v3_0_hw_fini,
2263         .suspend = vcn_v3_0_suspend,
2264         .resume = vcn_v3_0_resume,
2265         .is_idle = vcn_v3_0_is_idle,
2266         .wait_for_idle = vcn_v3_0_wait_for_idle,
2267         .check_soft_reset = NULL,
2268         .pre_soft_reset = NULL,
2269         .soft_reset = NULL,
2270         .post_soft_reset = NULL,
2271         .set_clockgating_state = vcn_v3_0_set_clockgating_state,
2272         .set_powergating_state = vcn_v3_0_set_powergating_state,
2273 };
2274
2275 const struct amdgpu_ip_block_version vcn_v3_0_ip_block =
2276 {
2277         .type = AMD_IP_BLOCK_TYPE_VCN,
2278         .major = 3,
2279         .minor = 0,
2280         .rev = 0,
2281         .funcs = &vcn_v3_0_ip_funcs,
2282 };