2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/firmware.h>
26 #include "amdgpu_vcn.h"
27 #include "amdgpu_pm.h"
31 #include "mmsch_v3_0.h"
33 #include "vcn/vcn_3_0_0_offset.h"
34 #include "vcn/vcn_3_0_0_sh_mask.h"
35 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h"
37 #define mmUVD_CONTEXT_ID_INTERNAL_OFFSET 0x27
38 #define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET 0x0f
39 #define mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET 0x10
40 #define mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET 0x11
41 #define mmUVD_NO_OP_INTERNAL_OFFSET 0x29
42 #define mmUVD_GP_SCRATCH8_INTERNAL_OFFSET 0x66
43 #define mmUVD_SCRATCH9_INTERNAL_OFFSET 0xc01d
45 #define mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET 0x431
46 #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x3b4
47 #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x3b5
48 #define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET 0x25c
50 #define VCN_INSTANCES_SIENNA_CICHLID 2
51 #define DEC_SW_RING_ENABLED FALSE
53 #define RDECODE_MSG_CREATE 0x00000000
54 #define RDECODE_MESSAGE_CREATE 0x00000001
56 static int amdgpu_ih_clientid_vcns[] = {
57 SOC15_IH_CLIENTID_VCN,
58 SOC15_IH_CLIENTID_VCN1
61 static int amdgpu_ucode_id_vcns[] = {
66 static int vcn_v3_0_start_sriov(struct amdgpu_device *adev);
67 static void vcn_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev);
68 static void vcn_v3_0_set_enc_ring_funcs(struct amdgpu_device *adev);
69 static void vcn_v3_0_set_irq_funcs(struct amdgpu_device *adev);
70 static int vcn_v3_0_set_powergating_state(void *handle,
71 enum amd_powergating_state state);
72 static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev,
73 int inst_idx, struct dpg_pause_state *new_state);
75 static void vcn_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring);
76 static void vcn_v3_0_enc_ring_set_wptr(struct amdgpu_ring *ring);
79 * vcn_v3_0_early_init - set function pointers
81 * @handle: amdgpu_device pointer
83 * Set ring and irq function pointers
85 static int vcn_v3_0_early_init(void *handle)
87 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
89 if (amdgpu_sriov_vf(adev)) {
90 adev->vcn.num_vcn_inst = VCN_INSTANCES_SIENNA_CICHLID;
91 adev->vcn.harvest_config = 0;
92 adev->vcn.num_enc_rings = 1;
95 if (adev->asic_type == CHIP_SIENNA_CICHLID) {
99 adev->vcn.num_vcn_inst = VCN_INSTANCES_SIENNA_CICHLID;
100 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
101 harvest = RREG32_SOC15(VCN, i, mmCC_UVD_HARVESTING);
102 if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK)
103 adev->vcn.harvest_config |= 1 << i;
106 if (adev->vcn.harvest_config == (AMDGPU_VCN_HARVEST_VCN0 |
107 AMDGPU_VCN_HARVEST_VCN1))
108 /* both instances are harvested, disable the block */
111 adev->vcn.num_vcn_inst = 1;
113 adev->vcn.num_enc_rings = 2;
116 vcn_v3_0_set_dec_ring_funcs(adev);
117 vcn_v3_0_set_enc_ring_funcs(adev);
118 vcn_v3_0_set_irq_funcs(adev);
124 * vcn_v3_0_sw_init - sw init for VCN block
126 * @handle: amdgpu_device pointer
128 * Load firmware and sw initialization
130 static int vcn_v3_0_sw_init(void *handle)
132 struct amdgpu_ring *ring;
134 int vcn_doorbell_index = 0;
135 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
137 r = amdgpu_vcn_sw_init(adev);
141 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
142 const struct common_firmware_header *hdr;
143 hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
144 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = AMDGPU_UCODE_ID_VCN;
145 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw;
146 adev->firmware.fw_size +=
147 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
149 if (adev->vcn.num_vcn_inst == VCN_INSTANCES_SIENNA_CICHLID) {
150 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN1].ucode_id = AMDGPU_UCODE_ID_VCN1;
151 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN1].fw = adev->vcn.fw;
152 adev->firmware.fw_size +=
153 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
155 DRM_INFO("PSP loading VCN firmware\n");
158 r = amdgpu_vcn_resume(adev);
163 * Note: doorbell assignment is fixed for SRIOV multiple VCN engines
165 * vcn_db_base = adev->doorbell_index.vcn.vcn_ring0_1 << 1;
166 * dec_ring_i = vcn_db_base + i * (adev->vcn.num_enc_rings + 1)
167 * enc_ring_i,j = vcn_db_base + i * (adev->vcn.num_enc_rings + 1) + 1 + j
169 if (amdgpu_sriov_vf(adev)) {
170 vcn_doorbell_index = adev->doorbell_index.vcn.vcn_ring0_1;
171 /* get DWORD offset */
172 vcn_doorbell_index = vcn_doorbell_index << 1;
175 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
176 volatile struct amdgpu_fw_shared *fw_shared;
178 if (adev->vcn.harvest_config & (1 << i))
181 adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET;
182 adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET;
183 adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET;
184 adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET;
185 adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET;
186 adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET;
188 adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET;
189 adev->vcn.inst[i].external.scratch9 = SOC15_REG_OFFSET(VCN, i, mmUVD_SCRATCH9);
190 adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET;
191 adev->vcn.inst[i].external.data0 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA0);
192 adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET;
193 adev->vcn.inst[i].external.data1 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA1);
194 adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET;
195 adev->vcn.inst[i].external.cmd = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_CMD);
196 adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET;
197 adev->vcn.inst[i].external.nop = SOC15_REG_OFFSET(VCN, i, mmUVD_NO_OP);
200 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i],
201 VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst[i].irq);
205 atomic_set(&adev->vcn.inst[i].sched_score, 0);
207 ring = &adev->vcn.inst[i].ring_dec;
208 ring->use_doorbell = true;
209 if (amdgpu_sriov_vf(adev)) {
210 ring->doorbell_index = vcn_doorbell_index + i * (adev->vcn.num_enc_rings + 1);
212 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i;
214 sprintf(ring->name, "vcn_dec_%d", i);
215 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0,
216 AMDGPU_RING_PRIO_DEFAULT,
217 &adev->vcn.inst[i].sched_score);
221 for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
223 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i],
224 j + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq);
228 ring = &adev->vcn.inst[i].ring_enc[j];
229 ring->use_doorbell = true;
230 if (amdgpu_sriov_vf(adev)) {
231 ring->doorbell_index = vcn_doorbell_index + i * (adev->vcn.num_enc_rings + 1) + 1 + j;
233 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + j + 8 * i;
235 sprintf(ring->name, "vcn_enc_%d.%d", i, j);
236 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0,
237 AMDGPU_RING_PRIO_DEFAULT,
238 &adev->vcn.inst[i].sched_score);
243 fw_shared = adev->vcn.inst[i].fw_shared_cpu_addr;
244 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_SW_RING_FLAG) |
245 cpu_to_le32(AMDGPU_VCN_MULTI_QUEUE_FLAG) |
246 cpu_to_le32(AMDGPU_VCN_FW_SHARED_FLAG_0_RB);
247 fw_shared->sw_ring.is_enabled = cpu_to_le32(DEC_SW_RING_ENABLED);
250 if (amdgpu_sriov_vf(adev)) {
251 r = amdgpu_virt_alloc_mm_table(adev);
255 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
256 adev->vcn.pause_dpg_mode = vcn_v3_0_pause_dpg_mode;
262 * vcn_v3_0_sw_fini - sw fini for VCN block
264 * @handle: amdgpu_device pointer
266 * VCN suspend and free up sw allocation
268 static int vcn_v3_0_sw_fini(void *handle)
270 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
273 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
274 volatile struct amdgpu_fw_shared *fw_shared;
276 if (adev->vcn.harvest_config & (1 << i))
278 fw_shared = adev->vcn.inst[i].fw_shared_cpu_addr;
279 fw_shared->present_flag_0 = 0;
280 fw_shared->sw_ring.is_enabled = false;
283 if (amdgpu_sriov_vf(adev))
284 amdgpu_virt_free_mm_table(adev);
286 r = amdgpu_vcn_suspend(adev);
290 r = amdgpu_vcn_sw_fini(adev);
296 * vcn_v3_0_hw_init - start and test VCN block
298 * @handle: amdgpu_device pointer
300 * Initialize the hardware, boot up the VCPU and do some testing
302 static int vcn_v3_0_hw_init(void *handle)
304 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
305 struct amdgpu_ring *ring;
308 if (amdgpu_sriov_vf(adev)) {
309 r = vcn_v3_0_start_sriov(adev);
313 /* initialize VCN dec and enc ring buffers */
314 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
315 if (adev->vcn.harvest_config & (1 << i))
318 ring = &adev->vcn.inst[i].ring_dec;
319 if (ring->sched.ready) {
322 vcn_v3_0_dec_ring_set_wptr(ring);
325 for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
326 ring = &adev->vcn.inst[i].ring_enc[j];
327 if (ring->sched.ready) {
330 vcn_v3_0_enc_ring_set_wptr(ring);
335 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
336 if (adev->vcn.harvest_config & (1 << i))
339 ring = &adev->vcn.inst[i].ring_dec;
341 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
342 ring->doorbell_index, i);
344 r = amdgpu_ring_test_helper(ring);
348 for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
349 ring = &adev->vcn.inst[i].ring_enc[j];
350 r = amdgpu_ring_test_helper(ring);
359 DRM_INFO("VCN decode and encode initialized successfully(under %s).\n",
360 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode");
366 * vcn_v3_0_hw_fini - stop the hardware block
368 * @handle: amdgpu_device pointer
370 * Stop the VCN block, mark ring as not ready any more
372 static int vcn_v3_0_hw_fini(void *handle)
374 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
375 struct amdgpu_ring *ring;
378 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
379 if (adev->vcn.harvest_config & (1 << i))
382 ring = &adev->vcn.inst[i].ring_dec;
384 if (!amdgpu_sriov_vf(adev)) {
385 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
386 (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
387 RREG32_SOC15(VCN, i, mmUVD_STATUS))) {
388 vcn_v3_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
391 ring->sched.ready = false;
393 for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
394 ring = &adev->vcn.inst[i].ring_enc[j];
395 ring->sched.ready = false;
403 * vcn_v3_0_suspend - suspend VCN block
405 * @handle: amdgpu_device pointer
407 * HW fini and suspend VCN block
409 static int vcn_v3_0_suspend(void *handle)
412 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
414 r = vcn_v3_0_hw_fini(adev);
418 r = amdgpu_vcn_suspend(adev);
424 * vcn_v3_0_resume - resume VCN block
426 * @handle: amdgpu_device pointer
428 * Resume firmware and hw init VCN block
430 static int vcn_v3_0_resume(void *handle)
433 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
435 r = amdgpu_vcn_resume(adev);
439 r = vcn_v3_0_hw_init(adev);
445 * vcn_v3_0_mc_resume - memory controller programming
447 * @adev: amdgpu_device pointer
448 * @inst: instance number
450 * Let the VCN memory controller know it's offsets
452 static void vcn_v3_0_mc_resume(struct amdgpu_device *adev, int inst)
454 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
457 /* cache window 0: fw */
458 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
459 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
460 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_lo));
461 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
462 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_hi));
463 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET0, 0);
466 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
467 lower_32_bits(adev->vcn.inst[inst].gpu_addr));
468 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
469 upper_32_bits(adev->vcn.inst[inst].gpu_addr));
471 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET0,
472 AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
474 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE0, size);
476 /* cache window 1: stack */
477 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
478 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset));
479 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
480 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset));
481 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET1, 0);
482 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);
484 /* cache window 2: context */
485 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
486 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
487 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
488 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
489 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET2, 0);
490 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
492 /* non-cache window */
493 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW,
494 lower_32_bits(adev->vcn.inst[inst].fw_shared_gpu_addr));
495 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH,
496 upper_32_bits(adev->vcn.inst[inst].fw_shared_gpu_addr));
497 WREG32_SOC15(VCN, inst, mmUVD_VCPU_NONCACHE_OFFSET0, 0);
498 WREG32_SOC15(VCN, inst, mmUVD_VCPU_NONCACHE_SIZE0,
499 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)));
502 static void vcn_v3_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
504 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
507 /* cache window 0: fw */
508 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
510 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
511 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
512 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect);
513 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
514 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
515 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect);
516 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
517 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
519 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
520 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);
521 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
522 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);
523 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
524 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
528 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
529 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
530 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
531 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
532 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
533 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
535 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
536 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0),
537 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);
541 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
542 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
544 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
545 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
547 /* cache window 1: stack */
549 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
550 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
551 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
552 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
553 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
554 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
555 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
556 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
558 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
559 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);
560 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
561 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);
562 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
563 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
565 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
566 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);
568 /* cache window 2: context */
569 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
570 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
571 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
572 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
573 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
574 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
575 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
576 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
577 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
578 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);
580 /* non-cache window */
581 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
582 VCN, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),
583 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared_gpu_addr), 0, indirect);
584 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
585 VCN, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),
586 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared_gpu_addr), 0, indirect);
587 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
588 VCN, inst_idx, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
589 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
590 VCN, inst_idx, mmUVD_VCPU_NONCACHE_SIZE0),
591 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect);
594 static void vcn_v3_0_disable_static_power_gating(struct amdgpu_device *adev, int inst)
598 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
599 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
600 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
601 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
602 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
603 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
604 | 2 << UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT
605 | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT
606 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
607 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
608 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
609 | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT
610 | 2 << UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT
611 | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT
612 | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT);
614 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data);
615 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS,
616 UVD_PGFSM_STATUS__UVDM_UVDU_UVDLM_PWR_ON_3_0, 0x3F3FFFFF);
618 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
619 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
620 | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
621 | 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
622 | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
623 | 1 << UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT
624 | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT
625 | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
626 | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
627 | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
628 | 1 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT
629 | 1 << UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT
630 | 1 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT
631 | 1 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT);
632 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data);
633 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, 0, 0x3F3FFFFF);
636 data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS);
638 if (adev->pg_flags & AMD_PG_SUPPORT_VCN)
639 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON |
640 UVD_POWER_STATUS__UVD_PG_EN_MASK;
642 WREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS, data);
645 static void vcn_v3_0_enable_static_power_gating(struct amdgpu_device *adev, int inst)
649 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
650 /* Before power off, this indicator has to be turned on */
651 data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS);
652 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK;
653 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF;
654 WREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS, data);
656 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
657 | 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
658 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
659 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
660 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
661 | 2 << UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT
662 | 2 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT
663 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
664 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
665 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
666 | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT
667 | 2 << UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT
668 | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT
669 | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT);
670 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data);
672 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT
673 | 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT
674 | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT
675 | 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT
676 | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT
677 | 2 << UVD_PGFSM_STATUS__UVDIRL_PWR_STATUS__SHIFT
678 | 2 << UVD_PGFSM_STATUS__UVDLM_PWR_STATUS__SHIFT
679 | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT
680 | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT
681 | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT
682 | 2 << UVD_PGFSM_STATUS__UVDAB_PWR_STATUS__SHIFT
683 | 2 << UVD_PGFSM_STATUS__UVDATD_PWR_STATUS__SHIFT
684 | 2 << UVD_PGFSM_STATUS__UVDNA_PWR_STATUS__SHIFT
685 | 2 << UVD_PGFSM_STATUS__UVDNB_PWR_STATUS__SHIFT);
686 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, data, 0x3F3FFFFF);
691 * vcn_v3_0_disable_clock_gating - disable VCN clock gating
693 * @adev: amdgpu_device pointer
694 * @inst: instance number
696 * Disable clock gating for VCN block
698 static void vcn_v3_0_disable_clock_gating(struct amdgpu_device *adev, int inst)
702 /* VCN disable CGC */
703 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL);
704 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
705 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
707 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
708 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
709 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
710 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data);
712 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_GATE);
713 data &= ~(UVD_CGC_GATE__SYS_MASK
714 | UVD_CGC_GATE__UDEC_MASK
715 | UVD_CGC_GATE__MPEG2_MASK
716 | UVD_CGC_GATE__REGS_MASK
717 | UVD_CGC_GATE__RBC_MASK
718 | UVD_CGC_GATE__LMI_MC_MASK
719 | UVD_CGC_GATE__LMI_UMC_MASK
720 | UVD_CGC_GATE__IDCT_MASK
721 | UVD_CGC_GATE__MPRD_MASK
722 | UVD_CGC_GATE__MPC_MASK
723 | UVD_CGC_GATE__LBSI_MASK
724 | UVD_CGC_GATE__LRBBM_MASK
725 | UVD_CGC_GATE__UDEC_RE_MASK
726 | UVD_CGC_GATE__UDEC_CM_MASK
727 | UVD_CGC_GATE__UDEC_IT_MASK
728 | UVD_CGC_GATE__UDEC_DB_MASK
729 | UVD_CGC_GATE__UDEC_MP_MASK
730 | UVD_CGC_GATE__WCB_MASK
731 | UVD_CGC_GATE__VCPU_MASK
732 | UVD_CGC_GATE__MMSCH_MASK);
734 WREG32_SOC15(VCN, inst, mmUVD_CGC_GATE, data);
736 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_CGC_GATE, 0, 0xFFFFFFFF);
738 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL);
739 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK
740 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
741 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
742 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
743 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
744 | UVD_CGC_CTRL__SYS_MODE_MASK
745 | UVD_CGC_CTRL__UDEC_MODE_MASK
746 | UVD_CGC_CTRL__MPEG2_MODE_MASK
747 | UVD_CGC_CTRL__REGS_MODE_MASK
748 | UVD_CGC_CTRL__RBC_MODE_MASK
749 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
750 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
751 | UVD_CGC_CTRL__IDCT_MODE_MASK
752 | UVD_CGC_CTRL__MPRD_MODE_MASK
753 | UVD_CGC_CTRL__MPC_MODE_MASK
754 | UVD_CGC_CTRL__LBSI_MODE_MASK
755 | UVD_CGC_CTRL__LRBBM_MODE_MASK
756 | UVD_CGC_CTRL__WCB_MODE_MASK
757 | UVD_CGC_CTRL__VCPU_MODE_MASK
758 | UVD_CGC_CTRL__MMSCH_MODE_MASK);
759 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data);
761 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE);
762 data |= (UVD_SUVD_CGC_GATE__SRE_MASK
763 | UVD_SUVD_CGC_GATE__SIT_MASK
764 | UVD_SUVD_CGC_GATE__SMP_MASK
765 | UVD_SUVD_CGC_GATE__SCM_MASK
766 | UVD_SUVD_CGC_GATE__SDB_MASK
767 | UVD_SUVD_CGC_GATE__SRE_H264_MASK
768 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
769 | UVD_SUVD_CGC_GATE__SIT_H264_MASK
770 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
771 | UVD_SUVD_CGC_GATE__SCM_H264_MASK
772 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
773 | UVD_SUVD_CGC_GATE__SDB_H264_MASK
774 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK
775 | UVD_SUVD_CGC_GATE__SCLR_MASK
776 | UVD_SUVD_CGC_GATE__ENT_MASK
777 | UVD_SUVD_CGC_GATE__IME_MASK
778 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
779 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
780 | UVD_SUVD_CGC_GATE__SITE_MASK
781 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK
782 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK
783 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
784 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK
785 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK
786 | UVD_SUVD_CGC_GATE__EFC_MASK
787 | UVD_SUVD_CGC_GATE__SAOE_MASK
788 | UVD_SUVD_CGC_GATE__SRE_AV1_MASK
789 | UVD_SUVD_CGC_GATE__FBC_PCLK_MASK
790 | UVD_SUVD_CGC_GATE__FBC_CCLK_MASK
791 | UVD_SUVD_CGC_GATE__SCM_AV1_MASK
792 | UVD_SUVD_CGC_GATE__SMPA_MASK);
793 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE, data);
795 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE2);
796 data |= (UVD_SUVD_CGC_GATE2__MPBE0_MASK
797 | UVD_SUVD_CGC_GATE2__MPBE1_MASK
798 | UVD_SUVD_CGC_GATE2__SIT_AV1_MASK
799 | UVD_SUVD_CGC_GATE2__SDB_AV1_MASK
800 | UVD_SUVD_CGC_GATE2__MPC1_MASK);
801 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE2, data);
803 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL);
804 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
805 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
806 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
807 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
808 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
809 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
810 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
811 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
812 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK
813 | UVD_SUVD_CGC_CTRL__EFC_MODE_MASK
814 | UVD_SUVD_CGC_CTRL__SAOE_MODE_MASK
815 | UVD_SUVD_CGC_CTRL__SMPA_MODE_MASK
816 | UVD_SUVD_CGC_CTRL__MPBE0_MODE_MASK
817 | UVD_SUVD_CGC_CTRL__MPBE1_MODE_MASK
818 | UVD_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK
819 | UVD_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK
820 | UVD_SUVD_CGC_CTRL__MPC1_MODE_MASK
821 | UVD_SUVD_CGC_CTRL__FBC_PCLK_MASK
822 | UVD_SUVD_CGC_CTRL__FBC_CCLK_MASK);
823 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL, data);
826 static void vcn_v3_0_clock_gating_dpg_mode(struct amdgpu_device *adev,
827 uint8_t sram_sel, int inst_idx, uint8_t indirect)
829 uint32_t reg_data = 0;
831 /* enable sw clock gating control */
832 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
833 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
835 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
836 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
837 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
838 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
839 UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
840 UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
841 UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
842 UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
843 UVD_CGC_CTRL__SYS_MODE_MASK |
844 UVD_CGC_CTRL__UDEC_MODE_MASK |
845 UVD_CGC_CTRL__MPEG2_MODE_MASK |
846 UVD_CGC_CTRL__REGS_MODE_MASK |
847 UVD_CGC_CTRL__RBC_MODE_MASK |
848 UVD_CGC_CTRL__LMI_MC_MODE_MASK |
849 UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
850 UVD_CGC_CTRL__IDCT_MODE_MASK |
851 UVD_CGC_CTRL__MPRD_MODE_MASK |
852 UVD_CGC_CTRL__MPC_MODE_MASK |
853 UVD_CGC_CTRL__LBSI_MODE_MASK |
854 UVD_CGC_CTRL__LRBBM_MODE_MASK |
855 UVD_CGC_CTRL__WCB_MODE_MASK |
856 UVD_CGC_CTRL__VCPU_MODE_MASK |
857 UVD_CGC_CTRL__MMSCH_MODE_MASK);
858 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
859 VCN, inst_idx, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);
861 /* turn off clock gating */
862 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
863 VCN, inst_idx, mmUVD_CGC_GATE), 0, sram_sel, indirect);
865 /* turn on SUVD clock gating */
866 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
867 VCN, inst_idx, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
869 /* turn on sw mode in UVD_SUVD_CGC_CTRL */
870 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
871 VCN, inst_idx, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
875 * vcn_v3_0_enable_clock_gating - enable VCN clock gating
877 * @adev: amdgpu_device pointer
878 * @inst: instance number
880 * Enable clock gating for VCN block
882 static void vcn_v3_0_enable_clock_gating(struct amdgpu_device *adev, int inst)
887 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL);
888 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
889 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
891 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
892 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
893 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
894 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data);
896 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL);
897 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK
898 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
899 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
900 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
901 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
902 | UVD_CGC_CTRL__SYS_MODE_MASK
903 | UVD_CGC_CTRL__UDEC_MODE_MASK
904 | UVD_CGC_CTRL__MPEG2_MODE_MASK
905 | UVD_CGC_CTRL__REGS_MODE_MASK
906 | UVD_CGC_CTRL__RBC_MODE_MASK
907 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
908 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
909 | UVD_CGC_CTRL__IDCT_MODE_MASK
910 | UVD_CGC_CTRL__MPRD_MODE_MASK
911 | UVD_CGC_CTRL__MPC_MODE_MASK
912 | UVD_CGC_CTRL__LBSI_MODE_MASK
913 | UVD_CGC_CTRL__LRBBM_MODE_MASK
914 | UVD_CGC_CTRL__WCB_MODE_MASK
915 | UVD_CGC_CTRL__VCPU_MODE_MASK
916 | UVD_CGC_CTRL__MMSCH_MODE_MASK);
917 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data);
919 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL);
920 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
921 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
922 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
923 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
924 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
925 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
926 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
927 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
928 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK
929 | UVD_SUVD_CGC_CTRL__EFC_MODE_MASK
930 | UVD_SUVD_CGC_CTRL__SAOE_MODE_MASK
931 | UVD_SUVD_CGC_CTRL__SMPA_MODE_MASK
932 | UVD_SUVD_CGC_CTRL__MPBE0_MODE_MASK
933 | UVD_SUVD_CGC_CTRL__MPBE1_MODE_MASK
934 | UVD_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK
935 | UVD_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK
936 | UVD_SUVD_CGC_CTRL__MPC1_MODE_MASK
937 | UVD_SUVD_CGC_CTRL__FBC_PCLK_MASK
938 | UVD_SUVD_CGC_CTRL__FBC_CCLK_MASK);
939 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL, data);
942 static int vcn_v3_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
944 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared_cpu_addr;
945 struct amdgpu_ring *ring;
946 uint32_t rb_bufsz, tmp;
948 /* disable register anti-hang mechanism */
949 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1,
950 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
951 /* enable dynamic power gating mode */
952 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS);
953 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;
954 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK;
955 WREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS, tmp);
958 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr;
960 /* enable clock gating */
961 vcn_v3_0_clock_gating_dpg_mode(adev, 0, inst_idx, indirect);
963 /* enable VCPU clock */
964 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
965 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
966 tmp |= UVD_VCPU_CNTL__BLK_RST_MASK;
967 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
968 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect);
970 /* disable master interupt */
971 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
972 VCN, inst_idx, mmUVD_MASTINT_EN), 0, 0, indirect);
974 /* setup mmUVD_LMI_CTRL */
975 tmp = (0x8 | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
976 UVD_LMI_CTRL__REQ_MODE_MASK |
977 UVD_LMI_CTRL__CRC_RESET_MASK |
978 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
979 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
980 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
981 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
983 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
984 VCN, inst_idx, mmUVD_LMI_CTRL), tmp, 0, indirect);
986 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
987 VCN, inst_idx, mmUVD_MPC_CNTL),
988 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect);
990 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
991 VCN, inst_idx, mmUVD_MPC_SET_MUXA0),
992 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
993 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
994 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
995 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect);
997 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
998 VCN, inst_idx, mmUVD_MPC_SET_MUXB0),
999 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
1000 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
1001 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
1002 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect);
1004 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
1005 VCN, inst_idx, mmUVD_MPC_SET_MUX),
1006 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
1007 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
1008 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);
1010 vcn_v3_0_mc_resume_dpg_mode(adev, inst_idx, indirect);
1012 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
1013 VCN, inst_idx, mmUVD_REG_XX_MASK), 0x10, 0, indirect);
1014 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
1015 VCN, inst_idx, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect);
1017 /* enable LMI MC and UMC channels */
1018 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
1019 VCN, inst_idx, mmUVD_LMI_CTRL2), 0, 0, indirect);
1021 /* unblock VCPU register access */
1022 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
1023 VCN, inst_idx, mmUVD_RB_ARB_CTRL), 0, 0, indirect);
1025 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
1026 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
1027 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
1028 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect);
1030 /* enable master interrupt */
1031 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
1032 VCN, inst_idx, mmUVD_MASTINT_EN),
1033 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
1035 /* add nop to workaround PSP size check */
1036 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
1037 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect);
1040 psp_update_vcn_sram(adev, inst_idx, adev->vcn.inst[inst_idx].dpg_sram_gpu_addr,
1041 (uint32_t)((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr -
1042 (uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr));
1044 ring = &adev->vcn.inst[inst_idx].ring_dec;
1045 /* force RBC into idle state */
1046 rb_bufsz = order_base_2(ring->ring_size);
1047 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
1048 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1049 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1050 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1051 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
1052 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_CNTL, tmp);
1054 /* Stall DPG before WPTR/RPTR reset */
1055 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),
1056 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK,
1057 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
1058 fw_shared->multi_queue.decode_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET);
1060 /* set the write pointer delay */
1061 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR_CNTL, 0);
1063 /* set the wb address */
1064 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR_ADDR,
1065 (upper_32_bits(ring->gpu_addr) >> 2));
1067 /* programm the RB_BASE for ring buffer */
1068 WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
1069 lower_32_bits(ring->gpu_addr));
1070 WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
1071 upper_32_bits(ring->gpu_addr));
1073 /* Initialize the ring buffer's read and write pointers */
1074 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, 0);
1076 WREG32_SOC15(VCN, inst_idx, mmUVD_SCRATCH2, 0);
1078 ring->wptr = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR);
1079 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR,
1080 lower_32_bits(ring->wptr));
1082 /* Reset FW shared memory RBC WPTR/RPTR */
1083 fw_shared->rb.rptr = 0;
1084 fw_shared->rb.wptr = lower_32_bits(ring->wptr);
1086 /*resetting done, fw can check RB ring */
1087 fw_shared->multi_queue.decode_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET);
1090 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),
1091 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
1096 static int vcn_v3_0_start(struct amdgpu_device *adev)
1098 volatile struct amdgpu_fw_shared *fw_shared;
1099 struct amdgpu_ring *ring;
1100 uint32_t rb_bufsz, tmp;
1103 if (adev->pm.dpm_enabled)
1104 amdgpu_dpm_enable_uvd(adev, true);
1106 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1107 if (adev->vcn.harvest_config & (1 << i))
1110 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG){
1111 r = vcn_v3_0_start_dpg_mode(adev, i, adev->vcn.indirect_sram);
1115 /* disable VCN power gating */
1116 vcn_v3_0_disable_static_power_gating(adev, i);
1118 /* set VCN status busy */
1119 tmp = RREG32_SOC15(VCN, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;
1120 WREG32_SOC15(VCN, i, mmUVD_STATUS, tmp);
1122 /*SW clock gating */
1123 vcn_v3_0_disable_clock_gating(adev, i);
1125 /* enable VCPU clock */
1126 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),
1127 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);
1129 /* disable master interrupt */
1130 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 0,
1131 ~UVD_MASTINT_EN__VCPU_EN_MASK);
1133 /* enable LMI MC and UMC channels */
1134 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_LMI_CTRL2), 0,
1135 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
1137 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET);
1138 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
1139 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
1140 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp);
1142 /* setup mmUVD_LMI_CTRL */
1143 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL);
1144 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL, tmp |
1145 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
1146 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
1147 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
1148 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
1150 /* setup mmUVD_MPC_CNTL */
1151 tmp = RREG32_SOC15(VCN, i, mmUVD_MPC_CNTL);
1152 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
1153 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
1154 WREG32_SOC15(VCN, i, mmUVD_MPC_CNTL, tmp);
1156 /* setup UVD_MPC_SET_MUXA0 */
1157 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXA0,
1158 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
1159 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
1160 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
1161 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
1163 /* setup UVD_MPC_SET_MUXB0 */
1164 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXB0,
1165 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
1166 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
1167 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
1168 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
1170 /* setup mmUVD_MPC_SET_MUX */
1171 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUX,
1172 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
1173 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
1174 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
1176 vcn_v3_0_mc_resume(adev, i);
1178 /* VCN global tiling registers */
1179 WREG32_SOC15(VCN, i, mmUVD_GFX10_ADDR_CONFIG,
1180 adev->gfx.config.gb_addr_config);
1182 /* unblock VCPU register access */
1183 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 0,
1184 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
1186 /* release VCPU reset to boot */
1187 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,
1188 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1190 for (j = 0; j < 10; ++j) {
1193 for (k = 0; k < 100; ++k) {
1194 status = RREG32_SOC15(VCN, i, mmUVD_STATUS);
1203 DRM_ERROR("VCN[%d] decode not responding, trying to reset the VCPU!!!\n", i);
1204 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),
1205 UVD_VCPU_CNTL__BLK_RST_MASK,
1206 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1208 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,
1209 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1216 DRM_ERROR("VCN[%d] decode not responding, giving up!!!\n", i);
1220 /* enable master interrupt */
1221 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN),
1222 UVD_MASTINT_EN__VCPU_EN_MASK,
1223 ~UVD_MASTINT_EN__VCPU_EN_MASK);
1225 /* clear the busy bit of VCN_STATUS */
1226 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 0,
1227 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
1229 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_VMID, 0);
1231 ring = &adev->vcn.inst[i].ring_dec;
1232 /* force RBC into idle state */
1233 rb_bufsz = order_base_2(ring->ring_size);
1234 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
1235 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1236 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1237 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1238 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
1239 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_CNTL, tmp);
1241 fw_shared = adev->vcn.inst[i].fw_shared_cpu_addr;
1242 fw_shared->multi_queue.decode_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET);
1244 /* programm the RB_BASE for ring buffer */
1245 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
1246 lower_32_bits(ring->gpu_addr));
1247 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
1248 upper_32_bits(ring->gpu_addr));
1250 /* Initialize the ring buffer's read and write pointers */
1251 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR, 0);
1253 WREG32_SOC15(VCN, i, mmUVD_SCRATCH2, 0);
1254 ring->wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR);
1255 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_WPTR,
1256 lower_32_bits(ring->wptr));
1257 fw_shared->rb.wptr = lower_32_bits(ring->wptr);
1258 fw_shared->multi_queue.decode_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET);
1260 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET);
1261 ring = &adev->vcn.inst[i].ring_enc[0];
1262 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1263 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1264 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO, ring->gpu_addr);
1265 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1266 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE, ring->ring_size / 4);
1267 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET);
1269 fw_shared->multi_queue.encode_lowlatency_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET);
1270 ring = &adev->vcn.inst[i].ring_enc[1];
1271 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
1272 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1273 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO2, ring->gpu_addr);
1274 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
1275 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE2, ring->ring_size / 4);
1276 fw_shared->multi_queue.encode_lowlatency_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET);
1282 static int vcn_v3_0_start_sriov(struct amdgpu_device *adev)
1285 struct amdgpu_ring *ring;
1286 uint64_t cache_addr;
1289 uint32_t param, resp, expected;
1290 uint32_t offset, cache_size;
1291 uint32_t tmp, timeout;
1294 struct amdgpu_mm_table *table = &adev->virt.mm_table;
1295 uint32_t *table_loc;
1296 uint32_t table_size;
1297 uint32_t size, size_dw;
1301 struct mmsch_v3_0_cmd_direct_write
1302 direct_wt = { {0} };
1303 struct mmsch_v3_0_cmd_direct_read_modify_write
1304 direct_rd_mod_wt = { {0} };
1305 struct mmsch_v3_0_cmd_end end = { {0} };
1306 struct mmsch_v3_0_init_header header;
1308 direct_wt.cmd_header.command_type =
1309 MMSCH_COMMAND__DIRECT_REG_WRITE;
1310 direct_rd_mod_wt.cmd_header.command_type =
1311 MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE;
1312 end.cmd_header.command_type =
1315 header.version = MMSCH_VERSION;
1316 header.total_size = sizeof(struct mmsch_v3_0_init_header) >> 2;
1317 for (i = 0; i < AMDGPU_MAX_VCN_INSTANCES; i++) {
1318 header.inst[i].init_status = 0;
1319 header.inst[i].table_offset = 0;
1320 header.inst[i].table_size = 0;
1323 table_loc = (uint32_t *)table->cpu_addr;
1324 table_loc += header.total_size;
1325 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1326 if (adev->vcn.harvest_config & (1 << i))
1331 MMSCH_V3_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, i,
1333 ~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY);
1335 cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
1337 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1338 id = amdgpu_ucode_id_vcns[i];
1339 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1340 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
1341 adev->firmware.ucode[id].tmr_mc_addr_lo);
1342 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1343 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
1344 adev->firmware.ucode[id].tmr_mc_addr_hi);
1346 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1347 mmUVD_VCPU_CACHE_OFFSET0),
1350 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1351 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
1352 lower_32_bits(adev->vcn.inst[i].gpu_addr));
1353 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1354 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
1355 upper_32_bits(adev->vcn.inst[i].gpu_addr));
1356 offset = cache_size;
1357 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1358 mmUVD_VCPU_CACHE_OFFSET0),
1359 AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
1362 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1363 mmUVD_VCPU_CACHE_SIZE0),
1366 cache_addr = adev->vcn.inst[i].gpu_addr + offset;
1367 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1368 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
1369 lower_32_bits(cache_addr));
1370 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1371 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
1372 upper_32_bits(cache_addr));
1373 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1374 mmUVD_VCPU_CACHE_OFFSET1),
1376 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1377 mmUVD_VCPU_CACHE_SIZE1),
1378 AMDGPU_VCN_STACK_SIZE);
1380 cache_addr = adev->vcn.inst[i].gpu_addr + offset +
1381 AMDGPU_VCN_STACK_SIZE;
1382 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1383 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
1384 lower_32_bits(cache_addr));
1385 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1386 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
1387 upper_32_bits(cache_addr));
1388 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1389 mmUVD_VCPU_CACHE_OFFSET2),
1391 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1392 mmUVD_VCPU_CACHE_SIZE2),
1393 AMDGPU_VCN_CONTEXT_SIZE);
1395 for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
1396 ring = &adev->vcn.inst[i].ring_enc[j];
1398 rb_addr = ring->gpu_addr;
1399 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1401 lower_32_bits(rb_addr));
1402 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1404 upper_32_bits(rb_addr));
1405 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1407 ring->ring_size / 4);
1410 ring = &adev->vcn.inst[i].ring_dec;
1412 rb_addr = ring->gpu_addr;
1413 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1414 mmUVD_LMI_RBC_RB_64BIT_BAR_LOW),
1415 lower_32_bits(rb_addr));
1416 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1417 mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH),
1418 upper_32_bits(rb_addr));
1419 /* force RBC into idle state */
1420 tmp = order_base_2(ring->ring_size);
1421 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, tmp);
1422 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1423 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1424 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1425 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
1426 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1430 /* add end packet */
1431 MMSCH_V3_0_INSERT_END();
1434 header.inst[i].init_status = 0;
1435 header.inst[i].table_offset = header.total_size;
1436 header.inst[i].table_size = table_size;
1437 header.total_size += table_size;
1440 /* Update init table header in memory */
1441 size = sizeof(struct mmsch_v3_0_init_header);
1442 table_loc = (uint32_t *)table->cpu_addr;
1443 memcpy((void *)table_loc, &header, size);
1445 /* message MMSCH (in VCN[0]) to initialize this client
1446 * 1, write to mmsch_vf_ctx_addr_lo/hi register with GPU mc addr
1447 * of memory descriptor location
1449 ctx_addr = table->gpu_addr;
1450 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr));
1451 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr));
1453 /* 2, update vmid of descriptor */
1454 tmp = RREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID);
1455 tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK;
1456 /* use domain0 for MM scheduler */
1457 tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT);
1458 WREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID, tmp);
1460 /* 3, notify mmsch about the size of this descriptor */
1461 size = header.total_size;
1462 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_SIZE, size);
1464 /* 4, set resp to zero */
1465 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP, 0);
1467 /* 5, kick off the initialization and wait until
1468 * MMSCH_VF_MAILBOX_RESP becomes non-zero
1471 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_HOST, param);
1475 expected = param + 1;
1476 while (resp != expected) {
1477 resp = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP);
1478 if (resp == expected)
1483 if (tmp >= timeout) {
1484 DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\
1485 " waiting for mmMMSCH_VF_MAILBOX_RESP "\
1486 "(expected=0x%08x, readback=0x%08x)\n",
1487 tmp, expected, resp);
1492 /* 6, check each VCN's init_status
1493 * if it remains as 0, then this VCN is not assigned to current VF
1494 * do not start ring for this VCN
1496 size = sizeof(struct mmsch_v3_0_init_header);
1497 table_loc = (uint32_t *)table->cpu_addr;
1498 memcpy(&header, (void *)table_loc, size);
1500 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1501 if (adev->vcn.harvest_config & (1 << i))
1504 is_vcn_ready = (header.inst[i].init_status == 1);
1506 DRM_INFO("VCN(%d) engine is disabled by hypervisor\n", i);
1508 ring = &adev->vcn.inst[i].ring_dec;
1509 ring->sched.ready = is_vcn_ready;
1510 for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
1511 ring = &adev->vcn.inst[i].ring_enc[j];
1512 ring->sched.ready = is_vcn_ready;
1519 static int vcn_v3_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)
1523 /* Wait for power status to be 1 */
1524 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1,
1525 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1527 /* wait for read ptr to be equal to write ptr */
1528 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR);
1529 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF);
1531 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2);
1532 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF);
1534 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;
1535 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF);
1537 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1,
1538 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1540 /* disable dynamic power gating mode */
1541 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 0,
1542 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
1547 static int vcn_v3_0_stop(struct amdgpu_device *adev)
1552 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1553 if (adev->vcn.harvest_config & (1 << i))
1556 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
1557 r = vcn_v3_0_stop_dpg_mode(adev, i);
1561 /* wait for vcn idle */
1562 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7);
1566 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
1567 UVD_LMI_STATUS__READ_CLEAN_MASK |
1568 UVD_LMI_STATUS__WRITE_CLEAN_MASK |
1569 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
1570 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp);
1574 /* disable LMI UMC channel */
1575 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2);
1576 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
1577 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2, tmp);
1578 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK|
1579 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
1580 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp);
1584 /* block VCPU register access */
1585 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL),
1586 UVD_RB_ARB_CTRL__VCPU_DIS_MASK,
1587 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
1590 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),
1591 UVD_VCPU_CNTL__BLK_RST_MASK,
1592 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1594 /* disable VCPU clock */
1595 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,
1596 ~(UVD_VCPU_CNTL__CLK_EN_MASK));
1598 /* apply soft reset */
1599 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET);
1600 tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
1601 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp);
1602 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET);
1603 tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
1604 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp);
1607 WREG32_SOC15(VCN, i, mmUVD_STATUS, 0);
1609 /* apply HW clock gating */
1610 vcn_v3_0_enable_clock_gating(adev, i);
1612 /* enable VCN power gating */
1613 vcn_v3_0_enable_static_power_gating(adev, i);
1616 if (adev->pm.dpm_enabled)
1617 amdgpu_dpm_enable_uvd(adev, false);
1622 static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev,
1623 int inst_idx, struct dpg_pause_state *new_state)
1625 volatile struct amdgpu_fw_shared *fw_shared;
1626 struct amdgpu_ring *ring;
1627 uint32_t reg_data = 0;
1630 /* pause/unpause if state is changed */
1631 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {
1632 DRM_DEBUG("dpg pause state changed %d -> %d",
1633 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based);
1634 reg_data = RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE) &
1635 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
1637 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) {
1638 ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 0x1,
1639 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1643 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1644 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data);
1647 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_DPG_PAUSE,
1648 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK,
1649 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
1651 /* Stall DPG before WPTR/RPTR reset */
1652 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),
1653 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK,
1654 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
1657 fw_shared = adev->vcn.inst[inst_idx].fw_shared_cpu_addr;
1658 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET);
1659 ring = &adev->vcn.inst[inst_idx].ring_enc[0];
1661 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO, ring->gpu_addr);
1662 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1663 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE, ring->ring_size / 4);
1664 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1665 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1666 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET);
1668 fw_shared->multi_queue.encode_lowlatency_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET);
1669 ring = &adev->vcn.inst[inst_idx].ring_enc[1];
1671 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO2, ring->gpu_addr);
1672 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
1673 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE2, ring->ring_size / 4);
1674 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
1675 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1676 fw_shared->multi_queue.encode_lowlatency_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET);
1678 /* restore wptr/rptr with pointers saved in FW shared memory*/
1679 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, fw_shared->rb.rptr);
1680 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR, fw_shared->rb.wptr);
1683 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),
1684 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
1686 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS,
1687 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1690 /* unpause dpg, no need to wait */
1691 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1692 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data);
1694 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;
1701 * vcn_v3_0_dec_ring_get_rptr - get read pointer
1703 * @ring: amdgpu_ring pointer
1705 * Returns the current hardware read pointer
1707 static uint64_t vcn_v3_0_dec_ring_get_rptr(struct amdgpu_ring *ring)
1709 struct amdgpu_device *adev = ring->adev;
1711 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_RPTR);
1715 * vcn_v3_0_dec_ring_get_wptr - get write pointer
1717 * @ring: amdgpu_ring pointer
1719 * Returns the current hardware write pointer
1721 static uint64_t vcn_v3_0_dec_ring_get_wptr(struct amdgpu_ring *ring)
1723 struct amdgpu_device *adev = ring->adev;
1725 if (ring->use_doorbell)
1726 return adev->wb.wb[ring->wptr_offs];
1728 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR);
1732 * vcn_v3_0_dec_ring_set_wptr - set write pointer
1734 * @ring: amdgpu_ring pointer
1736 * Commits the write pointer to the hardware
1738 static void vcn_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
1740 struct amdgpu_device *adev = ring->adev;
1741 volatile struct amdgpu_fw_shared *fw_shared;
1743 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
1744 /*whenever update RBC_RB_WPTR, we save the wptr in shared rb.wptr and scratch2 */
1745 fw_shared = adev->vcn.inst[ring->me].fw_shared_cpu_addr;
1746 fw_shared->rb.wptr = lower_32_bits(ring->wptr);
1747 WREG32_SOC15(VCN, ring->me, mmUVD_SCRATCH2,
1748 lower_32_bits(ring->wptr));
1751 if (ring->use_doorbell) {
1752 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
1753 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1755 WREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
1759 static void vcn_v3_0_dec_sw_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
1760 u64 seq, uint32_t flags)
1762 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1764 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_FENCE);
1765 amdgpu_ring_write(ring, addr);
1766 amdgpu_ring_write(ring, upper_32_bits(addr));
1767 amdgpu_ring_write(ring, seq);
1768 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_TRAP);
1771 static void vcn_v3_0_dec_sw_ring_insert_end(struct amdgpu_ring *ring)
1773 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_END);
1776 static void vcn_v3_0_dec_sw_ring_emit_ib(struct amdgpu_ring *ring,
1777 struct amdgpu_job *job,
1778 struct amdgpu_ib *ib,
1781 uint32_t vmid = AMDGPU_JOB_GET_VMID(job);
1783 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_IB);
1784 amdgpu_ring_write(ring, vmid);
1785 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1786 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1787 amdgpu_ring_write(ring, ib->length_dw);
1790 static void vcn_v3_0_dec_sw_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1791 uint32_t val, uint32_t mask)
1793 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_REG_WAIT);
1794 amdgpu_ring_write(ring, reg << 2);
1795 amdgpu_ring_write(ring, mask);
1796 amdgpu_ring_write(ring, val);
1799 static void vcn_v3_0_dec_sw_ring_emit_vm_flush(struct amdgpu_ring *ring,
1800 uint32_t vmid, uint64_t pd_addr)
1802 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1803 uint32_t data0, data1, mask;
1805 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1807 /* wait for register write */
1808 data0 = hub->ctx0_ptb_addr_lo32 + vmid * hub->ctx_addr_distance;
1809 data1 = lower_32_bits(pd_addr);
1811 vcn_v3_0_dec_sw_ring_emit_reg_wait(ring, data0, data1, mask);
1814 static void vcn_v3_0_dec_sw_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val)
1816 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_REG_WRITE);
1817 amdgpu_ring_write(ring, reg << 2);
1818 amdgpu_ring_write(ring, val);
1821 static const struct amdgpu_ring_funcs vcn_v3_0_dec_sw_ring_vm_funcs = {
1822 .type = AMDGPU_RING_TYPE_VCN_DEC,
1824 .nop = VCN_DEC_SW_CMD_NO_OP,
1825 .vmhub = AMDGPU_MMHUB_0,
1826 .get_rptr = vcn_v3_0_dec_ring_get_rptr,
1827 .get_wptr = vcn_v3_0_dec_ring_get_wptr,
1828 .set_wptr = vcn_v3_0_dec_ring_set_wptr,
1830 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1831 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
1832 4 + /* vcn_v3_0_dec_sw_ring_emit_vm_flush */
1833 5 + 5 + /* vcn_v3_0_dec_sw_ring_emit_fdec_swe x2 vm fdec_swe */
1834 1, /* vcn_v3_0_dec_sw_ring_insert_end */
1835 .emit_ib_size = 5, /* vcn_v3_0_dec_sw_ring_emit_ib */
1836 .emit_ib = vcn_v3_0_dec_sw_ring_emit_ib,
1837 .emit_fence = vcn_v3_0_dec_sw_ring_emit_fence,
1838 .emit_vm_flush = vcn_v3_0_dec_sw_ring_emit_vm_flush,
1839 .test_ring = amdgpu_vcn_dec_sw_ring_test_ring,
1840 .test_ib = NULL,//amdgpu_vcn_dec_sw_ring_test_ib,
1841 .insert_nop = amdgpu_ring_insert_nop,
1842 .insert_end = vcn_v3_0_dec_sw_ring_insert_end,
1843 .pad_ib = amdgpu_ring_generic_pad_ib,
1844 .begin_use = amdgpu_vcn_ring_begin_use,
1845 .end_use = amdgpu_vcn_ring_end_use,
1846 .emit_wreg = vcn_v3_0_dec_sw_ring_emit_wreg,
1847 .emit_reg_wait = vcn_v3_0_dec_sw_ring_emit_reg_wait,
1848 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1851 static int vcn_v3_0_limit_sched(struct amdgpu_cs_parser *p)
1853 struct drm_gpu_scheduler **scheds;
1855 /* The create msg must be in the first IB submitted */
1856 if (atomic_read(&p->entity->fence_seq))
1859 scheds = p->adev->gpu_sched[AMDGPU_HW_IP_VCN_DEC]
1860 [AMDGPU_RING_PRIO_DEFAULT].sched;
1861 drm_sched_entity_modify_sched(p->entity, scheds, 1);
1865 static int vcn_v3_0_dec_msg(struct amdgpu_cs_parser *p, uint64_t addr)
1867 struct ttm_operation_ctx ctx = { false, false };
1868 struct amdgpu_bo_va_mapping *map;
1869 uint32_t *msg, num_buffers;
1870 struct amdgpu_bo *bo;
1871 uint64_t start, end;
1876 addr &= AMDGPU_GMC_HOLE_MASK;
1877 r = amdgpu_cs_find_mapping(p, addr, &bo, &map);
1879 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr);
1883 start = map->start * AMDGPU_GPU_PAGE_SIZE;
1884 end = (map->last + 1) * AMDGPU_GPU_PAGE_SIZE;
1886 DRM_ERROR("VCN messages must be 8 byte aligned!\n");
1890 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
1891 amdgpu_bo_placement_from_domain(bo, bo->allowed_domains);
1892 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
1894 DRM_ERROR("Failed validating the VCN message BO (%d)!\n", r);
1898 r = amdgpu_bo_kmap(bo, &ptr);
1900 DRM_ERROR("Failed mapping the VCN message (%d)!\n", r);
1904 msg = ptr + addr - start;
1907 if (msg[1] > end - addr) {
1912 if (msg[3] != RDECODE_MSG_CREATE)
1915 num_buffers = msg[2];
1916 for (i = 0, msg = &msg[6]; i < num_buffers; ++i, msg += 4) {
1917 uint32_t offset, size, *create;
1919 if (msg[0] != RDECODE_MESSAGE_CREATE)
1925 if (offset + size > end) {
1930 create = ptr + addr + offset - start;
1932 /* H246, HEVC and VP9 can run on any instance */
1933 if (create[0] == 0x7 || create[0] == 0x10 || create[0] == 0x11)
1936 r = vcn_v3_0_limit_sched(p);
1942 amdgpu_bo_kunmap(bo);
1946 static int vcn_v3_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p,
1949 struct amdgpu_ring *ring = to_amdgpu_ring(p->entity->rq->sched);
1950 struct amdgpu_ib *ib = &p->job->ibs[ib_idx];
1951 uint32_t msg_lo = 0, msg_hi = 0;
1955 /* The first instance can decode anything */
1959 for (i = 0; i < ib->length_dw; i += 2) {
1960 uint32_t reg = amdgpu_get_ib_value(p, ib_idx, i);
1961 uint32_t val = amdgpu_get_ib_value(p, ib_idx, i + 1);
1963 if (reg == PACKET0(p->adev->vcn.internal.data0, 0)) {
1965 } else if (reg == PACKET0(p->adev->vcn.internal.data1, 0)) {
1967 } else if (reg == PACKET0(p->adev->vcn.internal.cmd, 0) &&
1969 r = vcn_v3_0_dec_msg(p, ((u64)msg_hi) << 32 | msg_lo);
1977 static const struct amdgpu_ring_funcs vcn_v3_0_dec_ring_vm_funcs = {
1978 .type = AMDGPU_RING_TYPE_VCN_DEC,
1980 .vmhub = AMDGPU_MMHUB_0,
1981 .get_rptr = vcn_v3_0_dec_ring_get_rptr,
1982 .get_wptr = vcn_v3_0_dec_ring_get_wptr,
1983 .set_wptr = vcn_v3_0_dec_ring_set_wptr,
1984 .patch_cs_in_place = vcn_v3_0_ring_patch_cs_in_place,
1986 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
1987 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
1988 8 + /* vcn_v2_0_dec_ring_emit_vm_flush */
1989 14 + 14 + /* vcn_v2_0_dec_ring_emit_fence x2 vm fence */
1991 .emit_ib_size = 8, /* vcn_v2_0_dec_ring_emit_ib */
1992 .emit_ib = vcn_v2_0_dec_ring_emit_ib,
1993 .emit_fence = vcn_v2_0_dec_ring_emit_fence,
1994 .emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush,
1995 .test_ring = vcn_v2_0_dec_ring_test_ring,
1996 .test_ib = amdgpu_vcn_dec_ring_test_ib,
1997 .insert_nop = vcn_v2_0_dec_ring_insert_nop,
1998 .insert_start = vcn_v2_0_dec_ring_insert_start,
1999 .insert_end = vcn_v2_0_dec_ring_insert_end,
2000 .pad_ib = amdgpu_ring_generic_pad_ib,
2001 .begin_use = amdgpu_vcn_ring_begin_use,
2002 .end_use = amdgpu_vcn_ring_end_use,
2003 .emit_wreg = vcn_v2_0_dec_ring_emit_wreg,
2004 .emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait,
2005 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2009 * vcn_v3_0_enc_ring_get_rptr - get enc read pointer
2011 * @ring: amdgpu_ring pointer
2013 * Returns the current hardware enc read pointer
2015 static uint64_t vcn_v3_0_enc_ring_get_rptr(struct amdgpu_ring *ring)
2017 struct amdgpu_device *adev = ring->adev;
2019 if (ring == &adev->vcn.inst[ring->me].ring_enc[0])
2020 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR);
2022 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR2);
2026 * vcn_v3_0_enc_ring_get_wptr - get enc write pointer
2028 * @ring: amdgpu_ring pointer
2030 * Returns the current hardware enc write pointer
2032 static uint64_t vcn_v3_0_enc_ring_get_wptr(struct amdgpu_ring *ring)
2034 struct amdgpu_device *adev = ring->adev;
2036 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) {
2037 if (ring->use_doorbell)
2038 return adev->wb.wb[ring->wptr_offs];
2040 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR);
2042 if (ring->use_doorbell)
2043 return adev->wb.wb[ring->wptr_offs];
2045 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2);
2050 * vcn_v3_0_enc_ring_set_wptr - set enc write pointer
2052 * @ring: amdgpu_ring pointer
2054 * Commits the enc write pointer to the hardware
2056 static void vcn_v3_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
2058 struct amdgpu_device *adev = ring->adev;
2060 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) {
2061 if (ring->use_doorbell) {
2062 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
2063 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
2065 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
2068 if (ring->use_doorbell) {
2069 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
2070 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
2072 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
2077 static const struct amdgpu_ring_funcs vcn_v3_0_enc_ring_vm_funcs = {
2078 .type = AMDGPU_RING_TYPE_VCN_ENC,
2080 .nop = VCN_ENC_CMD_NO_OP,
2081 .vmhub = AMDGPU_MMHUB_0,
2082 .get_rptr = vcn_v3_0_enc_ring_get_rptr,
2083 .get_wptr = vcn_v3_0_enc_ring_get_wptr,
2084 .set_wptr = vcn_v3_0_enc_ring_set_wptr,
2086 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2087 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
2088 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */
2089 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */
2090 1, /* vcn_v2_0_enc_ring_insert_end */
2091 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */
2092 .emit_ib = vcn_v2_0_enc_ring_emit_ib,
2093 .emit_fence = vcn_v2_0_enc_ring_emit_fence,
2094 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush,
2095 .test_ring = amdgpu_vcn_enc_ring_test_ring,
2096 .test_ib = amdgpu_vcn_enc_ring_test_ib,
2097 .insert_nop = amdgpu_ring_insert_nop,
2098 .insert_end = vcn_v2_0_enc_ring_insert_end,
2099 .pad_ib = amdgpu_ring_generic_pad_ib,
2100 .begin_use = amdgpu_vcn_ring_begin_use,
2101 .end_use = amdgpu_vcn_ring_end_use,
2102 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg,
2103 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait,
2104 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2107 static void vcn_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev)
2111 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
2112 if (adev->vcn.harvest_config & (1 << i))
2115 if (!DEC_SW_RING_ENABLED)
2116 adev->vcn.inst[i].ring_dec.funcs = &vcn_v3_0_dec_ring_vm_funcs;
2118 adev->vcn.inst[i].ring_dec.funcs = &vcn_v3_0_dec_sw_ring_vm_funcs;
2119 adev->vcn.inst[i].ring_dec.me = i;
2120 DRM_INFO("VCN(%d) decode%s is enabled in VM mode\n", i,
2121 DEC_SW_RING_ENABLED?"(Software Ring)":"");
2125 static void vcn_v3_0_set_enc_ring_funcs(struct amdgpu_device *adev)
2129 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
2130 if (adev->vcn.harvest_config & (1 << i))
2133 for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
2134 adev->vcn.inst[i].ring_enc[j].funcs = &vcn_v3_0_enc_ring_vm_funcs;
2135 adev->vcn.inst[i].ring_enc[j].me = i;
2137 DRM_INFO("VCN(%d) encode is enabled in VM mode\n", i);
2141 static bool vcn_v3_0_is_idle(void *handle)
2143 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2146 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
2147 if (adev->vcn.harvest_config & (1 << i))
2150 ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE);
2156 static int vcn_v3_0_wait_for_idle(void *handle)
2158 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2161 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
2162 if (adev->vcn.harvest_config & (1 << i))
2165 ret = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE,
2174 static int vcn_v3_0_set_clockgating_state(void *handle,
2175 enum amd_clockgating_state state)
2177 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2178 bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
2181 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
2182 if (adev->vcn.harvest_config & (1 << i))
2186 if (RREG32_SOC15(VCN, i, mmUVD_STATUS) != UVD_STATUS__IDLE)
2188 vcn_v3_0_enable_clock_gating(adev, i);
2190 vcn_v3_0_disable_clock_gating(adev, i);
2197 static int vcn_v3_0_set_powergating_state(void *handle,
2198 enum amd_powergating_state state)
2200 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2203 /* for SRIOV, guest should not control VCN Power-gating
2204 * MMSCH FW should control Power-gating and clock-gating
2205 * guest should avoid touching CGC and PG
2207 if (amdgpu_sriov_vf(adev)) {
2208 adev->vcn.cur_state = AMD_PG_STATE_UNGATE;
2212 if(state == adev->vcn.cur_state)
2215 if (state == AMD_PG_STATE_GATE)
2216 ret = vcn_v3_0_stop(adev);
2218 ret = vcn_v3_0_start(adev);
2221 adev->vcn.cur_state = state;
2226 static int vcn_v3_0_set_interrupt_state(struct amdgpu_device *adev,
2227 struct amdgpu_irq_src *source,
2229 enum amdgpu_interrupt_state state)
2234 static int vcn_v3_0_process_interrupt(struct amdgpu_device *adev,
2235 struct amdgpu_irq_src *source,
2236 struct amdgpu_iv_entry *entry)
2238 uint32_t ip_instance;
2240 switch (entry->client_id) {
2241 case SOC15_IH_CLIENTID_VCN:
2244 case SOC15_IH_CLIENTID_VCN1:
2248 DRM_ERROR("Unhandled client id: %d\n", entry->client_id);
2252 DRM_DEBUG("IH: VCN TRAP\n");
2254 switch (entry->src_id) {
2255 case VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT:
2256 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_dec);
2258 case VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE:
2259 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]);
2261 case VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY:
2262 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[1]);
2265 DRM_ERROR("Unhandled interrupt: %d %d\n",
2266 entry->src_id, entry->src_data[0]);
2273 static const struct amdgpu_irq_src_funcs vcn_v3_0_irq_funcs = {
2274 .set = vcn_v3_0_set_interrupt_state,
2275 .process = vcn_v3_0_process_interrupt,
2278 static void vcn_v3_0_set_irq_funcs(struct amdgpu_device *adev)
2282 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
2283 if (adev->vcn.harvest_config & (1 << i))
2286 adev->vcn.inst[i].irq.num_types = adev->vcn.num_enc_rings + 1;
2287 adev->vcn.inst[i].irq.funcs = &vcn_v3_0_irq_funcs;
2291 static const struct amd_ip_funcs vcn_v3_0_ip_funcs = {
2293 .early_init = vcn_v3_0_early_init,
2295 .sw_init = vcn_v3_0_sw_init,
2296 .sw_fini = vcn_v3_0_sw_fini,
2297 .hw_init = vcn_v3_0_hw_init,
2298 .hw_fini = vcn_v3_0_hw_fini,
2299 .suspend = vcn_v3_0_suspend,
2300 .resume = vcn_v3_0_resume,
2301 .is_idle = vcn_v3_0_is_idle,
2302 .wait_for_idle = vcn_v3_0_wait_for_idle,
2303 .check_soft_reset = NULL,
2304 .pre_soft_reset = NULL,
2306 .post_soft_reset = NULL,
2307 .set_clockgating_state = vcn_v3_0_set_clockgating_state,
2308 .set_powergating_state = vcn_v3_0_set_powergating_state,
2311 const struct amdgpu_ip_block_version vcn_v3_0_ip_block =
2313 .type = AMD_IP_BLOCK_TYPE_VCN,
2317 .funcs = &vcn_v3_0_ip_funcs,