drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Christian König <christian.koenig@amd.com>
  23  */
  24
  25 #include <linux/firmware.h>
  26 #include <drm/drmP.h>
  27 #include "amdgpu.h"
  28 #include "amdgpu_uvd.h"
  29 #include "vid.h"
  30 #include "uvd/uvd_6_0_d.h"
  31 #include "uvd/uvd_6_0_sh_mask.h"
  32 #include "oss/oss_2_0_d.h"
  33 #include "oss/oss_2_0_sh_mask.h"
  34 #include "smu/smu_7_1_3_d.h"
  35 #include "smu/smu_7_1_3_sh_mask.h"
  36 #include "bif/bif_5_1_d.h"
  37 #include "gmc/gmc_8_1_d.h"
  38 #include "vi.h"
  39
  40 static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev);
  41 static void uvd_v6_0_set_enc_ring_funcs(struct amdgpu_device *adev);
  42
  43 static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev);
  44 static int uvd_v6_0_start(struct amdgpu_device *adev);
  45 static void uvd_v6_0_stop(struct amdgpu_device *adev);
  46 static void uvd_v6_0_set_sw_clock_gating(struct amdgpu_device *adev);
  47 static int uvd_v6_0_set_clockgating_state(void *handle,
  48                                           enum amd_clockgating_state state);
  49 static void uvd_v6_0_enable_mgcg(struct amdgpu_device *adev,
  50                                  bool enable);
  51
  52 /**
  53 * uvd_v6_0_enc_support - get encode support status
  54 *
  55 * @adev: amdgpu_device pointer
  56 *
  57 * Returns the current hardware encode support status
  58 */
  59 static inline bool uvd_v6_0_enc_support(struct amdgpu_device *adev)
  60 {
  61         return ((adev->asic_type >= CHIP_POLARIS10) && (adev->asic_type <= CHIP_POLARIS12));
  62 }
  63
  64 /**
  65  * uvd_v6_0_ring_get_rptr - get read pointer
  66  *
  67  * @ring: amdgpu_ring pointer
  68  *
  69  * Returns the current hardware read pointer
  70  */
  71 static uint64_t uvd_v6_0_ring_get_rptr(struct amdgpu_ring *ring)
  72 {
  73         struct amdgpu_device *adev = ring->adev;
  74
  75         return RREG32(mmUVD_RBC_RB_RPTR);
  76 }
  77
  78 /**
  79  * uvd_v6_0_enc_ring_get_rptr - get enc read pointer
  80  *
  81  * @ring: amdgpu_ring pointer
  82  *
  83  * Returns the current hardware enc read pointer
  84  */
  85 static uint64_t uvd_v6_0_enc_ring_get_rptr(struct amdgpu_ring *ring)
  86 {
  87         struct amdgpu_device *adev = ring->adev;
  88
  89         if (ring == &adev->uvd.ring_enc[0])
  90                 return RREG32(mmUVD_RB_RPTR);
  91         else
  92                 return RREG32(mmUVD_RB_RPTR2);
  93 }
  94 /**
  95  * uvd_v6_0_ring_get_wptr - get write pointer
  96  *
  97  * @ring: amdgpu_ring pointer
  98  *
  99  * Returns the current hardware write pointer
 100  */
 101 static uint64_t uvd_v6_0_ring_get_wptr(struct amdgpu_ring *ring)
 102 {
 103         struct amdgpu_device *adev = ring->adev;
 104
 105         return RREG32(mmUVD_RBC_RB_WPTR);
 106 }
 107
 108 /**
 109  * uvd_v6_0_enc_ring_get_wptr - get enc write pointer
 110  *
 111  * @ring: amdgpu_ring pointer
 112  *
 113  * Returns the current hardware enc write pointer
 114  */
 115 static uint64_t uvd_v6_0_enc_ring_get_wptr(struct amdgpu_ring *ring)
 116 {
 117         struct amdgpu_device *adev = ring->adev;
 118
 119         if (ring == &adev->uvd.ring_enc[0])
 120                 return RREG32(mmUVD_RB_WPTR);
 121         else
 122                 return RREG32(mmUVD_RB_WPTR2);
 123 }
 124
 125 /**
 126  * uvd_v6_0_ring_set_wptr - set write pointer
 127  *
 128  * @ring: amdgpu_ring pointer
 129  *
 130  * Commits the write pointer to the hardware
 131  */
 132 static void uvd_v6_0_ring_set_wptr(struct amdgpu_ring *ring)
 133 {
 134         struct amdgpu_device *adev = ring->adev;
 135
 136         WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
 137 }
 138
 139 /**
 140  * uvd_v6_0_enc_ring_set_wptr - set enc write pointer
 141  *
 142  * @ring: amdgpu_ring pointer
 143  *
 144  * Commits the enc write pointer to the hardware
 145  */
 146 static void uvd_v6_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
 147 {
 148         struct amdgpu_device *adev = ring->adev;
 149
 150         if (ring == &adev->uvd.ring_enc[0])
 151                 WREG32(mmUVD_RB_WPTR,
 152                         lower_32_bits(ring->wptr));
 153         else
 154                 WREG32(mmUVD_RB_WPTR2,
 155                         lower_32_bits(ring->wptr));
 156 }
 157
 158 /**
 159  * uvd_v6_0_enc_ring_test_ring - test if UVD ENC ring is working
 160  *
 161  * @ring: the engine to test on
 162  *
 163  */
 164 static int uvd_v6_0_enc_ring_test_ring(struct amdgpu_ring *ring)
 165 {
 166         struct amdgpu_device *adev = ring->adev;
 167         uint32_t rptr = amdgpu_ring_get_rptr(ring);
 168         unsigned i;
 169         int r;
 170
 171         r = amdgpu_ring_alloc(ring, 16);
 172         if (r) {
 173                 DRM_ERROR("amdgpu: uvd enc failed to lock ring %d (%d).\n",
 174                           ring->idx, r);
 175                 return r;
 176         }
 177         amdgpu_ring_write(ring, HEVC_ENC_CMD_END);
 178         amdgpu_ring_commit(ring);
 179
 180         for (i = 0; i < adev->usec_timeout; i++) {
 181                 if (amdgpu_ring_get_rptr(ring) != rptr)
 182                         break;
 183                 DRM_UDELAY(1);
 184         }
 185
 186         if (i < adev->usec_timeout) {
 187                 DRM_DEBUG("ring test on %d succeeded in %d usecs\n",
 188                          ring->idx, i);
 189         } else {
 190                 DRM_ERROR("amdgpu: ring %d test failed\n",
 191                           ring->idx);
 192                 r = -ETIMEDOUT;
 193         }
 194
 195         return r;
 196 }
 197
 198 /**
 199  * uvd_v6_0_enc_get_create_msg - generate a UVD ENC create msg
 200  *
 201  * @adev: amdgpu_device pointer
 202  * @ring: ring we should submit the msg to
 203  * @handle: session handle to use
 204  * @fence: optional fence to return
 205  *
 206  * Open up a stream for HW test
 207  */
 208 static int uvd_v6_0_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
 209                                        struct dma_fence **fence)
 210 {
 211         const unsigned ib_size_dw = 16;
 212         struct amdgpu_job *job;
 213         struct amdgpu_ib *ib;
 214         struct dma_fence *f = NULL;
 215         uint64_t dummy;
 216         int i, r;
 217
 218         r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
 219         if (r)
 220                 return r;
 221
 222         ib = &job->ibs[0];
 223         dummy = ib->gpu_addr + 1024;
 224
 225         ib->length_dw = 0;
 226         ib->ptr[ib->length_dw++] = 0x00000018;
 227         ib->ptr[ib->length_dw++] = 0x00000001; /* session info */
 228         ib->ptr[ib->length_dw++] = handle;
 229         ib->ptr[ib->length_dw++] = 0x00010000;
 230         ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
 231         ib->ptr[ib->length_dw++] = dummy;
 232
 233         ib->ptr[ib->length_dw++] = 0x00000014;
 234         ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
 235         ib->ptr[ib->length_dw++] = 0x0000001c;
 236         ib->ptr[ib->length_dw++] = 0x00000001;
 237         ib->ptr[ib->length_dw++] = 0x00000000;
 238
 239         ib->ptr[ib->length_dw++] = 0x00000008;
 240         ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */
 241
 242         for (i = ib->length_dw; i < ib_size_dw; ++i)
 243                 ib->ptr[i] = 0x0;
 244
 245         r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f);
 246         job->fence = dma_fence_get(f);
 247         if (r)
 248                 goto err;
 249
 250         amdgpu_job_free(job);
 251         if (fence)
 252                 *fence = dma_fence_get(f);
 253         dma_fence_put(f);
 254         return 0;
 255
 256 err:
 257         amdgpu_job_free(job);
 258         return r;
 259 }
 260
 261 /**
 262  * uvd_v6_0_enc_get_destroy_msg - generate a UVD ENC destroy msg
 263  *
 264  * @adev: amdgpu_device pointer
 265  * @ring: ring we should submit the msg to
 266  * @handle: session handle to use
 267  * @fence: optional fence to return
 268  *
 269  * Close up a stream for HW test or if userspace failed to do so
 270  */
 271 static int uvd_v6_0_enc_get_destroy_msg(struct amdgpu_ring *ring,
 272                                         uint32_t handle,
 273                                         bool direct, struct dma_fence **fence)
 274 {
 275         const unsigned ib_size_dw = 16;
 276         struct amdgpu_job *job;
 277         struct amdgpu_ib *ib;
 278         struct dma_fence *f = NULL;
 279         uint64_t dummy;
 280         int i, r;
 281
 282         r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
 283         if (r)
 284                 return r;
 285
 286         ib = &job->ibs[0];
 287         dummy = ib->gpu_addr + 1024;
 288
 289         ib->length_dw = 0;
 290         ib->ptr[ib->length_dw++] = 0x00000018;
 291         ib->ptr[ib->length_dw++] = 0x00000001; /* session info */
 292         ib->ptr[ib->length_dw++] = handle;
 293         ib->ptr[ib->length_dw++] = 0x00010000;
 294         ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
 295         ib->ptr[ib->length_dw++] = dummy;
 296
 297         ib->ptr[ib->length_dw++] = 0x00000014;
 298         ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
 299         ib->ptr[ib->length_dw++] = 0x0000001c;
 300         ib->ptr[ib->length_dw++] = 0x00000001;
 301         ib->ptr[ib->length_dw++] = 0x00000000;
 302
 303         ib->ptr[ib->length_dw++] = 0x00000008;
 304         ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */
 305
 306         for (i = ib->length_dw; i < ib_size_dw; ++i)
 307                 ib->ptr[i] = 0x0;
 308
 309         if (direct) {
 310                 r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f);
 311                 job->fence = dma_fence_get(f);
 312                 if (r)
 313                         goto err;
 314
 315                 amdgpu_job_free(job);
 316         } else {
 317                 r = amdgpu_job_submit(job, ring, &ring->adev->vce.entity,
 318                                       AMDGPU_FENCE_OWNER_UNDEFINED, &f);
 319                 if (r)
 320                         goto err;
 321         }
 322
 323         if (fence)
 324                 *fence = dma_fence_get(f);
 325         dma_fence_put(f);
 326         return 0;
 327
 328 err:
 329         amdgpu_job_free(job);
 330         return r;
 331 }
 332
 333 /**
 334  * uvd_v6_0_enc_ring_test_ib - test if UVD ENC IBs are working
 335  *
 336  * @ring: the engine to test on
 337  *
 338  */
 339 static int uvd_v6_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 340 {
 341         struct dma_fence *fence = NULL;
 342         long r;
 343
 344         r = uvd_v6_0_enc_get_create_msg(ring, 1, NULL);
 345         if (r) {
 346                 DRM_ERROR("amdgpu: failed to get create msg (%ld).\n", r);
 347                 goto error;
 348         }
 349
 350         r = uvd_v6_0_enc_get_destroy_msg(ring, 1, true, &fence);
 351         if (r) {
 352                 DRM_ERROR("amdgpu: failed to get destroy ib (%ld).\n", r);
 353                 goto error;
 354         }
 355
 356         r = dma_fence_wait_timeout(fence, false, timeout);
 357         if (r == 0) {
 358                 DRM_ERROR("amdgpu: IB test timed out.\n");
 359                 r = -ETIMEDOUT;
 360         } else if (r < 0) {
 361                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
 362         } else {
 363                 DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
 364                 r = 0;
 365         }
 366 error:
 367         dma_fence_put(fence);
 368         return r;
 369 }
 370 static int uvd_v6_0_early_init(void *handle)
 371 {
 372         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 373
 374         if (!(adev->flags & AMD_IS_APU) &&
 375             (RREG32_SMC(ixCC_HARVEST_FUSES) & CC_HARVEST_FUSES__UVD_DISABLE_MASK))
 376                 return -ENOENT;
 377
 378         uvd_v6_0_set_ring_funcs(adev);
 379
 380         if (uvd_v6_0_enc_support(adev)) {
 381                 adev->uvd.num_enc_rings = 2;
 382                 uvd_v6_0_set_enc_ring_funcs(adev);
 383         }
 384
 385         uvd_v6_0_set_irq_funcs(adev);
 386
 387         return 0;
 388 }
 389
 390 static int uvd_v6_0_sw_init(void *handle)
 391 {
 392         struct amdgpu_ring *ring;
 393         int i, r;
 394         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 395
 396         /* UVD TRAP */
 397         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 124, &adev->uvd.irq);
 398         if (r)
 399                 return r;
 400
 401         /* UVD ENC TRAP */
 402         if (uvd_v6_0_enc_support(adev)) {
 403                 for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
 404                         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i + 119, &adev->uvd.irq);
 405                         if (r)
 406                                 return r;
 407                 }
 408         }
 409
 410         r = amdgpu_uvd_sw_init(adev);
 411         if (r)
 412                 return r;
 413
 414         if (uvd_v6_0_enc_support(adev)) {
 415                 struct drm_sched_rq *rq;
 416                 ring = &adev->uvd.ring_enc[0];
 417                 rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
 418                 r = drm_sched_entity_init(&ring->sched, &adev->uvd.entity_enc,
 419                                           rq, amdgpu_sched_jobs, NULL);
 420                 if (r) {
 421                         DRM_ERROR("Failed setting up UVD ENC run queue.\n");
 422                         return r;
 423                 }
 424         }
 425
 426         r = amdgpu_uvd_resume(adev);
 427         if (r)
 428                 return r;
 429
 430         ring = &adev->uvd.ring;
 431         sprintf(ring->name, "uvd");
 432         r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0);
 433         if (r)
 434                 return r;
 435
 436         if (uvd_v6_0_enc_support(adev)) {
 437                 for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
 438                         ring = &adev->uvd.ring_enc[i];
 439                         sprintf(ring->name, "uvd_enc%d", i);
 440                         r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0);
 441                         if (r)
 442                                 return r;
 443                 }
 444         }
 445
 446         return r;
 447 }
 448
 449 static int uvd_v6_0_sw_fini(void *handle)
 450 {
 451         int i, r;
 452         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 453
 454         r = amdgpu_uvd_suspend(adev);
 455         if (r)
 456                 return r;
 457
 458         if (uvd_v6_0_enc_support(adev)) {
 459                 drm_sched_entity_fini(&adev->uvd.ring_enc[0].sched, &adev->uvd.entity_enc);
 460
 461                 for (i = 0; i < adev->uvd.num_enc_rings; ++i)
 462                         amdgpu_ring_fini(&adev->uvd.ring_enc[i]);
 463         }
 464
 465         return amdgpu_uvd_sw_fini(adev);
 466 }
 467
 468 /**
 469  * uvd_v6_0_hw_init - start and test UVD block
 470  *
 471  * @adev: amdgpu_device pointer
 472  *
 473  * Initialize the hardware, boot up the VCPU and do some testing
 474  */
 475 static int uvd_v6_0_hw_init(void *handle)
 476 {
 477         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 478         struct amdgpu_ring *ring = &adev->uvd.ring;
 479         uint32_t tmp;
 480         int i, r;
 481
 482         amdgpu_asic_set_uvd_clocks(adev, 10000, 10000);
 483         uvd_v6_0_set_clockgating_state(adev, AMD_CG_STATE_UNGATE);
 484         uvd_v6_0_enable_mgcg(adev, true);
 485
 486         ring->ready = true;
 487         r = amdgpu_ring_test_ring(ring);
 488         if (r) {
 489                 ring->ready = false;
 490                 goto done;
 491         }
 492
 493         r = amdgpu_ring_alloc(ring, 10);
 494         if (r) {
 495                 DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r);
 496                 goto done;
 497         }
 498
 499         tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);
 500         amdgpu_ring_write(ring, tmp);
 501         amdgpu_ring_write(ring, 0xFFFFF);
 502
 503         tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0);
 504         amdgpu_ring_write(ring, tmp);
 505         amdgpu_ring_write(ring, 0xFFFFF);
 506
 507         tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0);
 508         amdgpu_ring_write(ring, tmp);
 509         amdgpu_ring_write(ring, 0xFFFFF);
 510
 511         /* Clear timeout status bits */
 512         amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0));
 513         amdgpu_ring_write(ring, 0x8);
 514
 515         amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0));
 516         amdgpu_ring_write(ring, 3);
 517
 518         amdgpu_ring_commit(ring);
 519
 520         if (uvd_v6_0_enc_support(adev)) {
 521                 for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
 522                         ring = &adev->uvd.ring_enc[i];
 523                         ring->ready = true;
 524                         r = amdgpu_ring_test_ring(ring);
 525                         if (r) {
 526                                 ring->ready = false;
 527                                 goto done;
 528                         }
 529                 }
 530         }
 531
 532 done:
 533         if (!r) {
 534                 if (uvd_v6_0_enc_support(adev))
 535                         DRM_INFO("UVD and UVD ENC initialized successfully.\n");
 536                 else
 537                         DRM_INFO("UVD initialized successfully.\n");
 538         }
 539
 540         return r;
 541 }
 542
 543 /**
 544  * uvd_v6_0_hw_fini - stop the hardware block
 545  *
 546  * @adev: amdgpu_device pointer
 547  *
 548  * Stop the UVD block, mark ring as not ready any more
 549  */
 550 static int uvd_v6_0_hw_fini(void *handle)
 551 {
 552         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 553         struct amdgpu_ring *ring = &adev->uvd.ring;
 554
 555         if (RREG32(mmUVD_STATUS) != 0)
 556                 uvd_v6_0_stop(adev);
 557
 558         ring->ready = false;
 559
 560         return 0;
 561 }
 562
 563 static int uvd_v6_0_suspend(void *handle)
 564 {
 565         int r;
 566         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 567
 568         r = uvd_v6_0_hw_fini(adev);
 569         if (r)
 570                 return r;
 571
 572         return amdgpu_uvd_suspend(adev);
 573 }
 574
 575 static int uvd_v6_0_resume(void *handle)
 576 {
 577         int r;
 578         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 579
 580         r = amdgpu_uvd_resume(adev);
 581         if (r)
 582                 return r;
 583
 584         return uvd_v6_0_hw_init(adev);
 585 }
 586
 587 /**
 588  * uvd_v6_0_mc_resume - memory controller programming
 589  *
 590  * @adev: amdgpu_device pointer
 591  *
 592  * Let the UVD memory controller know it's offsets
 593  */
 594 static void uvd_v6_0_mc_resume(struct amdgpu_device *adev)
 595 {
 596         uint64_t offset;
 597         uint32_t size;
 598
 599         /* programm memory controller bits 0-27 */
 600         WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 601                         lower_32_bits(adev->uvd.gpu_addr));
 602         WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 603                         upper_32_bits(adev->uvd.gpu_addr));
 604
 605         offset = AMDGPU_UVD_FIRMWARE_OFFSET;
 606         size = AMDGPU_UVD_FIRMWARE_SIZE(adev);
 607         WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3);
 608         WREG32(mmUVD_VCPU_CACHE_SIZE0, size);
 609
 610         offset += size;
 611         size = AMDGPU_UVD_HEAP_SIZE;
 612         WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3);
 613         WREG32(mmUVD_VCPU_CACHE_SIZE1, size);
 614
 615         offset += size;
 616         size = AMDGPU_UVD_STACK_SIZE +
 617                (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles);
 618         WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3);
 619         WREG32(mmUVD_VCPU_CACHE_SIZE2, size);
 620
 621         WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
 622         WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
 623         WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
 624
 625         WREG32(mmUVD_GP_SCRATCH4, adev->uvd.max_handles);
 626 }
 627
 628 #if 0
 629 static void cz_set_uvd_clock_gating_branches(struct amdgpu_device *adev,
 630                 bool enable)
 631 {
 632         u32 data, data1;
 633
 634         data = RREG32(mmUVD_CGC_GATE);
 635         data1 = RREG32(mmUVD_SUVD_CGC_GATE);
 636         if (enable) {
 637                 data |= UVD_CGC_GATE__SYS_MASK |
 638                                 UVD_CGC_GATE__UDEC_MASK |
 639                                 UVD_CGC_GATE__MPEG2_MASK |
 640                                 UVD_CGC_GATE__RBC_MASK |
 641                                 UVD_CGC_GATE__LMI_MC_MASK |
 642                                 UVD_CGC_GATE__IDCT_MASK |
 643                                 UVD_CGC_GATE__MPRD_MASK |
 644                                 UVD_CGC_GATE__MPC_MASK |
 645                                 UVD_CGC_GATE__LBSI_MASK |
 646                                 UVD_CGC_GATE__LRBBM_MASK |
 647                                 UVD_CGC_GATE__UDEC_RE_MASK |
 648                                 UVD_CGC_GATE__UDEC_CM_MASK |
 649                                 UVD_CGC_GATE__UDEC_IT_MASK |
 650                                 UVD_CGC_GATE__UDEC_DB_MASK |
 651                                 UVD_CGC_GATE__UDEC_MP_MASK |
 652                                 UVD_CGC_GATE__WCB_MASK |
 653                                 UVD_CGC_GATE__VCPU_MASK |
 654                                 UVD_CGC_GATE__SCPU_MASK;
 655                 data1 |= UVD_SUVD_CGC_GATE__SRE_MASK |
 656                                 UVD_SUVD_CGC_GATE__SIT_MASK |
 657                                 UVD_SUVD_CGC_GATE__SMP_MASK |
 658                                 UVD_SUVD_CGC_GATE__SCM_MASK |
 659                                 UVD_SUVD_CGC_GATE__SDB_MASK |
 660                                 UVD_SUVD_CGC_GATE__SRE_H264_MASK |
 661                                 UVD_SUVD_CGC_GATE__SRE_HEVC_MASK |
 662                                 UVD_SUVD_CGC_GATE__SIT_H264_MASK |
 663                                 UVD_SUVD_CGC_GATE__SIT_HEVC_MASK |
 664                                 UVD_SUVD_CGC_GATE__SCM_H264_MASK |
 665                                 UVD_SUVD_CGC_GATE__SCM_HEVC_MASK |
 666                                 UVD_SUVD_CGC_GATE__SDB_H264_MASK |
 667                                 UVD_SUVD_CGC_GATE__SDB_HEVC_MASK;
 668         } else {
 669                 data &= ~(UVD_CGC_GATE__SYS_MASK |
 670                                 UVD_CGC_GATE__UDEC_MASK |
 671                                 UVD_CGC_GATE__MPEG2_MASK |
 672                                 UVD_CGC_GATE__RBC_MASK |
 673                                 UVD_CGC_GATE__LMI_MC_MASK |
 674                                 UVD_CGC_GATE__LMI_UMC_MASK |
 675                                 UVD_CGC_GATE__IDCT_MASK |
 676                                 UVD_CGC_GATE__MPRD_MASK |
 677                                 UVD_CGC_GATE__MPC_MASK |
 678                                 UVD_CGC_GATE__LBSI_MASK |
 679                                 UVD_CGC_GATE__LRBBM_MASK |
 680                                 UVD_CGC_GATE__UDEC_RE_MASK |
 681                                 UVD_CGC_GATE__UDEC_CM_MASK |
 682                                 UVD_CGC_GATE__UDEC_IT_MASK |
 683                                 UVD_CGC_GATE__UDEC_DB_MASK |
 684                                 UVD_CGC_GATE__UDEC_MP_MASK |
 685                                 UVD_CGC_GATE__WCB_MASK |
 686                                 UVD_CGC_GATE__VCPU_MASK |
 687                                 UVD_CGC_GATE__SCPU_MASK);
 688                 data1 &= ~(UVD_SUVD_CGC_GATE__SRE_MASK |
 689                                 UVD_SUVD_CGC_GATE__SIT_MASK |
 690                                 UVD_SUVD_CGC_GATE__SMP_MASK |
 691                                 UVD_SUVD_CGC_GATE__SCM_MASK |
 692                                 UVD_SUVD_CGC_GATE__SDB_MASK |
 693                                 UVD_SUVD_CGC_GATE__SRE_H264_MASK |
 694                                 UVD_SUVD_CGC_GATE__SRE_HEVC_MASK |
 695                                 UVD_SUVD_CGC_GATE__SIT_H264_MASK |
 696                                 UVD_SUVD_CGC_GATE__SIT_HEVC_MASK |
 697                                 UVD_SUVD_CGC_GATE__SCM_H264_MASK |
 698                                 UVD_SUVD_CGC_GATE__SCM_HEVC_MASK |
 699                                 UVD_SUVD_CGC_GATE__SDB_H264_MASK |
 700                                 UVD_SUVD_CGC_GATE__SDB_HEVC_MASK);
 701         }
 702         WREG32(mmUVD_CGC_GATE, data);
 703         WREG32(mmUVD_SUVD_CGC_GATE, data1);
 704 }
 705 #endif
 706
 707 /**
 708  * uvd_v6_0_start - start UVD block
 709  *
 710  * @adev: amdgpu_device pointer
 711  *
 712  * Setup and start the UVD block
 713  */
 714 static int uvd_v6_0_start(struct amdgpu_device *adev)
 715 {
 716         struct amdgpu_ring *ring = &adev->uvd.ring;
 717         uint32_t rb_bufsz, tmp;
 718         uint32_t lmi_swap_cntl;
 719         uint32_t mp_swap_cntl;
 720         int i, j, r;
 721
 722         /* disable DPG */
 723         WREG32_P(mmUVD_POWER_STATUS, 0, ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
 724
 725         /* disable byte swapping */
 726         lmi_swap_cntl = 0;
 727         mp_swap_cntl = 0;
 728
 729         uvd_v6_0_mc_resume(adev);
 730
 731         /* disable interupt */
 732         WREG32_FIELD(UVD_MASTINT_EN, VCPU_EN, 0);
 733
 734         /* stall UMC and register bus before resetting VCPU */
 735         WREG32_FIELD(UVD_LMI_CTRL2, STALL_ARB_UMC, 1);
 736         mdelay(1);
 737
 738         /* put LMI, VCPU, RBC etc... into reset */
 739         WREG32(mmUVD_SOFT_RESET,
 740                 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
 741                 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK |
 742                 UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
 743                 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK |
 744                 UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
 745                 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK |
 746                 UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
 747                 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
 748         mdelay(5);
 749
 750         /* take UVD block out of reset */
 751         WREG32_FIELD(SRBM_SOFT_RESET, SOFT_RESET_UVD, 0);
 752         mdelay(5);
 753
 754         /* initialize UVD memory controller */
 755         WREG32(mmUVD_LMI_CTRL,
 756                 (0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
 757                 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
 758                 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
 759                 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
 760                 UVD_LMI_CTRL__REQ_MODE_MASK |
 761                 UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL_MASK);
 762
 763 #ifdef __BIG_ENDIAN
 764         /* swap (8 in 32) RB and IB */
 765         lmi_swap_cntl = 0xa;
 766         mp_swap_cntl = 0;
 767 #endif
 768         WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
 769         WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl);
 770
 771         WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040);
 772         WREG32(mmUVD_MPC_SET_MUXA1, 0x0);
 773         WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040);
 774         WREG32(mmUVD_MPC_SET_MUXB1, 0x0);
 775         WREG32(mmUVD_MPC_SET_ALU, 0);
 776         WREG32(mmUVD_MPC_SET_MUX, 0x88);
 777
 778         /* take all subblocks out of reset, except VCPU */
 779         WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 780         mdelay(5);
 781
 782         /* enable VCPU clock */
 783         WREG32(mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK);
 784
 785         /* enable UMC */
 786         WREG32_FIELD(UVD_LMI_CTRL2, STALL_ARB_UMC, 0);
 787
 788         /* boot up the VCPU */
 789         WREG32(mmUVD_SOFT_RESET, 0);
 790         mdelay(10);
 791
 792         for (i = 0; i < 10; ++i) {
 793                 uint32_t status;
 794
 795                 for (j = 0; j < 100; ++j) {
 796                         status = RREG32(mmUVD_STATUS);
 797                         if (status & 2)
 798                                 break;
 799                         mdelay(10);
 800                 }
 801                 r = 0;
 802                 if (status & 2)
 803                         break;
 804
 805                 DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n");
 806                 WREG32_FIELD(UVD_SOFT_RESET, VCPU_SOFT_RESET, 1);
 807                 mdelay(10);
 808                 WREG32_FIELD(UVD_SOFT_RESET, VCPU_SOFT_RESET, 0);
 809                 mdelay(10);
 810                 r = -1;
 811         }
 812
 813         if (r) {
 814                 DRM_ERROR("UVD not responding, giving up!!!\n");
 815                 return r;
 816         }
 817         /* enable master interrupt */
 818         WREG32_P(mmUVD_MASTINT_EN,
 819                 (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK),
 820                 ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK));
 821
 822         /* clear the bit 4 of UVD_STATUS */
 823         WREG32_P(mmUVD_STATUS, 0, ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
 824
 825         /* force RBC into idle state */
 826         rb_bufsz = order_base_2(ring->ring_size);
 827         tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
 828         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
 829         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
 830         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
 831         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
 832         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
 833         WREG32(mmUVD_RBC_RB_CNTL, tmp);
 834
 835         /* set the write pointer delay */
 836         WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0);
 837
 838         /* set the wb address */
 839         WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2));
 840
 841         /* programm the RB_BASE for ring buffer */
 842         WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
 843                         lower_32_bits(ring->gpu_addr));
 844         WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
 845                         upper_32_bits(ring->gpu_addr));
 846
 847         /* Initialize the ring buffer's read and write pointers */
 848         WREG32(mmUVD_RBC_RB_RPTR, 0);
 849
 850         ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);
 851         WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
 852
 853         WREG32_FIELD(UVD_RBC_RB_CNTL, RB_NO_FETCH, 0);
 854
 855         if (uvd_v6_0_enc_support(adev)) {
 856                 ring = &adev->uvd.ring_enc[0];
 857                 WREG32(mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
 858                 WREG32(mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
 859                 WREG32(mmUVD_RB_BASE_LO, ring->gpu_addr);
 860                 WREG32(mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
 861                 WREG32(mmUVD_RB_SIZE, ring->ring_size / 4);
 862
 863                 ring = &adev->uvd.ring_enc[1];
 864                 WREG32(mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
 865                 WREG32(mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
 866                 WREG32(mmUVD_RB_BASE_LO2, ring->gpu_addr);
 867                 WREG32(mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
 868                 WREG32(mmUVD_RB_SIZE2, ring->ring_size / 4);
 869         }
 870
 871         return 0;
 872 }
 873
 874 /**
 875  * uvd_v6_0_stop - stop UVD block
 876  *
 877  * @adev: amdgpu_device pointer
 878  *
 879  * stop the UVD block
 880  */
 881 static void uvd_v6_0_stop(struct amdgpu_device *adev)
 882 {
 883         /* force RBC into idle state */
 884         WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);
 885
 886         /* Stall UMC and register bus before resetting VCPU */
 887         WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
 888         mdelay(1);
 889
 890         /* put VCPU into reset */
 891         WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 892         mdelay(5);
 893
 894         /* disable VCPU clock */
 895         WREG32(mmUVD_VCPU_CNTL, 0x0);
 896
 897         /* Unstall UMC and register bus */
 898         WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));
 899
 900         WREG32(mmUVD_STATUS, 0);
 901 }
 902
 903 /**
 904  * uvd_v6_0_ring_emit_fence - emit an fence & trap command
 905  *
 906  * @ring: amdgpu_ring pointer
 907  * @fence: fence to emit
 908  *
 909  * Write a fence and a trap command to the ring.
 910  */
 911 static void uvd_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 912                                      unsigned flags)
 913 {
 914         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
 915
 916         amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
 917         amdgpu_ring_write(ring, seq);
 918         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
 919         amdgpu_ring_write(ring, addr & 0xffffffff);
 920         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
 921         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
 922         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
 923         amdgpu_ring_write(ring, 0);
 924
 925         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
 926         amdgpu_ring_write(ring, 0);
 927         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
 928         amdgpu_ring_write(ring, 0);
 929         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
 930         amdgpu_ring_write(ring, 2);
 931 }
 932
 933 /**
 934  * uvd_v6_0_enc_ring_emit_fence - emit an enc fence & trap command
 935  *
 936  * @ring: amdgpu_ring pointer
 937  * @fence: fence to emit
 938  *
 939  * Write enc a fence and a trap command to the ring.
 940  */
 941 static void uvd_v6_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
 942                         u64 seq, unsigned flags)
 943 {
 944         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
 945
 946         amdgpu_ring_write(ring, HEVC_ENC_CMD_FENCE);
 947         amdgpu_ring_write(ring, addr);
 948         amdgpu_ring_write(ring, upper_32_bits(addr));
 949         amdgpu_ring_write(ring, seq);
 950         amdgpu_ring_write(ring, HEVC_ENC_CMD_TRAP);
 951 }
 952
 953 /**
 954  * uvd_v6_0_ring_emit_hdp_flush - emit an hdp flush
 955  *
 956  * @ring: amdgpu_ring pointer
 957  *
 958  * Emits an hdp flush.
 959  */
 960 static void uvd_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 961 {
 962         amdgpu_ring_write(ring, PACKET0(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0));
 963         amdgpu_ring_write(ring, 0);
 964 }
 965
 966 /**
 967  * uvd_v6_0_ring_hdp_invalidate - emit an hdp invalidate
 968  *
 969  * @ring: amdgpu_ring pointer
 970  *
 971  * Emits an hdp invalidate.
 972  */
 973 static void uvd_v6_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
 974 {
 975         amdgpu_ring_write(ring, PACKET0(mmHDP_DEBUG0, 0));
 976         amdgpu_ring_write(ring, 1);
 977 }
 978
 979 /**
 980  * uvd_v6_0_ring_test_ring - register write test
 981  *
 982  * @ring: amdgpu_ring pointer
 983  *
 984  * Test if we can successfully write to the context register
 985  */
 986 static int uvd_v6_0_ring_test_ring(struct amdgpu_ring *ring)
 987 {
 988         struct amdgpu_device *adev = ring->adev;
 989         uint32_t tmp = 0;
 990         unsigned i;
 991         int r;
 992
 993         WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD);
 994         r = amdgpu_ring_alloc(ring, 3);
 995         if (r) {
 996                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
 997                           ring->idx, r);
 998                 return r;
 999         }
1000         amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
1001         amdgpu_ring_write(ring, 0xDEADBEEF);
1002         amdgpu_ring_commit(ring);
1003         for (i = 0; i < adev->usec_timeout; i++) {
1004                 tmp = RREG32(mmUVD_CONTEXT_ID);
1005                 if (tmp == 0xDEADBEEF)
1006                         break;
1007                 DRM_UDELAY(1);
1008         }
1009
1010         if (i < adev->usec_timeout) {
1011                 DRM_DEBUG("ring test on %d succeeded in %d usecs\n",
1012                          ring->idx, i);
1013         } else {
1014                 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
1015                           ring->idx, tmp);
1016                 r = -EINVAL;
1017         }
1018         return r;
1019 }
1020
1021 /**
1022  * uvd_v6_0_ring_emit_ib - execute indirect buffer
1023  *
1024  * @ring: amdgpu_ring pointer
1025  * @ib: indirect buffer to execute
1026  *
1027  * Write ring commands to execute the indirect buffer
1028  */
1029 static void uvd_v6_0_ring_emit_ib(struct amdgpu_ring *ring,
1030                                   struct amdgpu_ib *ib,
1031                                   unsigned vmid, bool ctx_switch)
1032 {
1033         amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_VMID, 0));
1034         amdgpu_ring_write(ring, vmid);
1035
1036         amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0));
1037         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1038         amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH, 0));
1039         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1040         amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0));
1041         amdgpu_ring_write(ring, ib->length_dw);
1042 }
1043
1044 /**
1045  * uvd_v6_0_enc_ring_emit_ib - enc execute indirect buffer
1046  *
1047  * @ring: amdgpu_ring pointer
1048  * @ib: indirect buffer to execute
1049  *
1050  * Write enc ring commands to execute the indirect buffer
1051  */
1052 static void uvd_v6_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
1053                 struct amdgpu_ib *ib, unsigned int vmid, bool ctx_switch)
1054 {
1055         amdgpu_ring_write(ring, HEVC_ENC_CMD_IB_VM);
1056         amdgpu_ring_write(ring, vmid);
1057         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1058         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1059         amdgpu_ring_write(ring, ib->length_dw);
1060 }
1061
1062 static void uvd_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1063                                          unsigned vmid, uint64_t pd_addr)
1064 {
1065         uint32_t reg;
1066
1067         if (vmid < 8)
1068                 reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid;
1069         else
1070                 reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8;
1071
1072         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
1073         amdgpu_ring_write(ring, reg << 2);
1074         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
1075         amdgpu_ring_write(ring, pd_addr >> 12);
1076         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
1077         amdgpu_ring_write(ring, 0x8);
1078
1079         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
1080         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
1081         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
1082         amdgpu_ring_write(ring, 1 << vmid);
1083         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
1084         amdgpu_ring_write(ring, 0x8);
1085
1086         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
1087         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
1088         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
1089         amdgpu_ring_write(ring, 0);
1090         amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH8, 0));
1091         amdgpu_ring_write(ring, 1 << vmid); /* mask */
1092         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
1093         amdgpu_ring_write(ring, 0xC);
1094 }
1095
1096 static void uvd_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1097 {
1098         uint32_t seq = ring->fence_drv.sync_seq;
1099         uint64_t addr = ring->fence_drv.gpu_addr;
1100
1101         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
1102         amdgpu_ring_write(ring, lower_32_bits(addr));
1103         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
1104         amdgpu_ring_write(ring, upper_32_bits(addr));
1105         amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH8, 0));
1106         amdgpu_ring_write(ring, 0xffffffff); /* mask */
1107         amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH9, 0));
1108         amdgpu_ring_write(ring, seq);
1109         amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
1110         amdgpu_ring_write(ring, 0xE);
1111 }
1112
1113 static void uvd_v6_0_enc_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1114 {
1115         uint32_t seq = ring->fence_drv.sync_seq;
1116         uint64_t addr = ring->fence_drv.gpu_addr;
1117
1118         amdgpu_ring_write(ring, HEVC_ENC_CMD_WAIT_GE);
1119         amdgpu_ring_write(ring, lower_32_bits(addr));
1120         amdgpu_ring_write(ring, upper_32_bits(addr));
1121         amdgpu_ring_write(ring, seq);
1122 }
1123
1124 static void uvd_v6_0_enc_ring_insert_end(struct amdgpu_ring *ring)
1125 {
1126         amdgpu_ring_write(ring, HEVC_ENC_CMD_END);
1127 }
1128
1129 static void uvd_v6_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
1130         unsigned int vmid, uint64_t pd_addr)
1131 {
1132         amdgpu_ring_write(ring, HEVC_ENC_CMD_UPDATE_PTB);
1133         amdgpu_ring_write(ring, vmid);
1134         amdgpu_ring_write(ring, pd_addr >> 12);
1135
1136         amdgpu_ring_write(ring, HEVC_ENC_CMD_FLUSH_TLB);
1137         amdgpu_ring_write(ring, vmid);
1138 }
1139
1140 static bool uvd_v6_0_is_idle(void *handle)
1141 {
1142         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1143
1144         return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
1145 }
1146
1147 static int uvd_v6_0_wait_for_idle(void *handle)
1148 {
1149         unsigned i;
1150         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1151
1152         for (i = 0; i < adev->usec_timeout; i++) {
1153                 if (uvd_v6_0_is_idle(handle))
1154                         return 0;
1155         }
1156         return -ETIMEDOUT;
1157 }
1158
1159 #define AMDGPU_UVD_STATUS_BUSY_MASK    0xfd
1160 static bool uvd_v6_0_check_soft_reset(void *handle)
1161 {
1162         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1163         u32 srbm_soft_reset = 0;
1164         u32 tmp = RREG32(mmSRBM_STATUS);
1165
1166         if (REG_GET_FIELD(tmp, SRBM_STATUS, UVD_RQ_PENDING) ||
1167             REG_GET_FIELD(tmp, SRBM_STATUS, UVD_BUSY) ||
1168             (RREG32(mmUVD_STATUS) & AMDGPU_UVD_STATUS_BUSY_MASK))
1169                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_UVD, 1);
1170
1171         if (srbm_soft_reset) {
1172                 adev->uvd.srbm_soft_reset = srbm_soft_reset;
1173                 return true;
1174         } else {
1175                 adev->uvd.srbm_soft_reset = 0;
1176                 return false;
1177         }
1178 }
1179
1180 static int uvd_v6_0_pre_soft_reset(void *handle)
1181 {
1182         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1183
1184         if (!adev->uvd.srbm_soft_reset)
1185                 return 0;
1186
1187         uvd_v6_0_stop(adev);
1188         return 0;
1189 }
1190
1191 static int uvd_v6_0_soft_reset(void *handle)
1192 {
1193         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1194         u32 srbm_soft_reset;
1195
1196         if (!adev->uvd.srbm_soft_reset)
1197                 return 0;
1198         srbm_soft_reset = adev->uvd.srbm_soft_reset;
1199
1200         if (srbm_soft_reset) {
1201                 u32 tmp;
1202
1203                 tmp = RREG32(mmSRBM_SOFT_RESET);
1204                 tmp |= srbm_soft_reset;
1205                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1206                 WREG32(mmSRBM_SOFT_RESET, tmp);
1207                 tmp = RREG32(mmSRBM_SOFT_RESET);
1208
1209                 udelay(50);
1210
1211                 tmp &= ~srbm_soft_reset;
1212                 WREG32(mmSRBM_SOFT_RESET, tmp);
1213                 tmp = RREG32(mmSRBM_SOFT_RESET);
1214
1215                 /* Wait a little for things to settle down */
1216                 udelay(50);
1217         }
1218
1219         return 0;
1220 }
1221
1222 static int uvd_v6_0_post_soft_reset(void *handle)
1223 {
1224         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1225
1226         if (!adev->uvd.srbm_soft_reset)
1227                 return 0;
1228
1229         mdelay(5);
1230
1231         return uvd_v6_0_start(adev);
1232 }
1233
1234 static int uvd_v6_0_set_interrupt_state(struct amdgpu_device *adev,
1235                                         struct amdgpu_irq_src *source,
1236                                         unsigned type,
1237                                         enum amdgpu_interrupt_state state)
1238 {
1239         // TODO
1240         return 0;
1241 }
1242
1243 static int uvd_v6_0_process_interrupt(struct amdgpu_device *adev,
1244                                       struct amdgpu_irq_src *source,
1245                                       struct amdgpu_iv_entry *entry)
1246 {
1247         bool int_handled = true;
1248         DRM_DEBUG("IH: UVD TRAP\n");
1249
1250         switch (entry->src_id) {
1251         case 124:
1252                 amdgpu_fence_process(&adev->uvd.ring);
1253                 break;
1254         case 119:
1255                 if (likely(uvd_v6_0_enc_support(adev)))
1256                         amdgpu_fence_process(&adev->uvd.ring_enc[0]);
1257                 else
1258                         int_handled = false;
1259                 break;
1260         case 120:
1261                 if (likely(uvd_v6_0_enc_support(adev)))
1262                         amdgpu_fence_process(&adev->uvd.ring_enc[1]);
1263                 else
1264                         int_handled = false;
1265                 break;
1266         }
1267
1268         if (false == int_handled)
1269                         DRM_ERROR("Unhandled interrupt: %d %d\n",
1270                           entry->src_id, entry->src_data[0]);
1271
1272         return 0;
1273 }
1274
1275 static void uvd_v6_0_enable_clock_gating(struct amdgpu_device *adev, bool enable)
1276 {
1277         uint32_t data1, data3;
1278
1279         data1 = RREG32(mmUVD_SUVD_CGC_GATE);
1280         data3 = RREG32(mmUVD_CGC_GATE);
1281
1282         data1 |= UVD_SUVD_CGC_GATE__SRE_MASK |
1283                      UVD_SUVD_CGC_GATE__SIT_MASK |
1284                      UVD_SUVD_CGC_GATE__SMP_MASK |
1285                      UVD_SUVD_CGC_GATE__SCM_MASK |
1286                      UVD_SUVD_CGC_GATE__SDB_MASK |
1287                      UVD_SUVD_CGC_GATE__SRE_H264_MASK |
1288                      UVD_SUVD_CGC_GATE__SRE_HEVC_MASK |
1289                      UVD_SUVD_CGC_GATE__SIT_H264_MASK |
1290                      UVD_SUVD_CGC_GATE__SIT_HEVC_MASK |
1291                      UVD_SUVD_CGC_GATE__SCM_H264_MASK |
1292                      UVD_SUVD_CGC_GATE__SCM_HEVC_MASK |
1293                      UVD_SUVD_CGC_GATE__SDB_H264_MASK |
1294                      UVD_SUVD_CGC_GATE__SDB_HEVC_MASK;
1295
1296         if (enable) {
1297                 data3 |= (UVD_CGC_GATE__SYS_MASK       |
1298                         UVD_CGC_GATE__UDEC_MASK      |
1299                         UVD_CGC_GATE__MPEG2_MASK     |
1300                         UVD_CGC_GATE__RBC_MASK       |
1301                         UVD_CGC_GATE__LMI_MC_MASK    |
1302                         UVD_CGC_GATE__LMI_UMC_MASK   |
1303                         UVD_CGC_GATE__IDCT_MASK      |
1304                         UVD_CGC_GATE__MPRD_MASK      |
1305                         UVD_CGC_GATE__MPC_MASK       |
1306                         UVD_CGC_GATE__LBSI_MASK      |
1307                         UVD_CGC_GATE__LRBBM_MASK     |
1308                         UVD_CGC_GATE__UDEC_RE_MASK   |
1309                         UVD_CGC_GATE__UDEC_CM_MASK   |
1310                         UVD_CGC_GATE__UDEC_IT_MASK   |
1311                         UVD_CGC_GATE__UDEC_DB_MASK   |
1312                         UVD_CGC_GATE__UDEC_MP_MASK   |
1313                         UVD_CGC_GATE__WCB_MASK       |
1314                         UVD_CGC_GATE__JPEG_MASK      |
1315                         UVD_CGC_GATE__SCPU_MASK      |
1316                         UVD_CGC_GATE__JPEG2_MASK);
1317                 /* only in pg enabled, we can gate clock to vcpu*/
1318                 if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
1319                         data3 |= UVD_CGC_GATE__VCPU_MASK;
1320
1321                 data3 &= ~UVD_CGC_GATE__REGS_MASK;
1322         } else {
1323                 data3 = 0;
1324         }
1325
1326         WREG32(mmUVD_SUVD_CGC_GATE, data1);
1327         WREG32(mmUVD_CGC_GATE, data3);
1328 }
1329
1330 static void uvd_v6_0_set_sw_clock_gating(struct amdgpu_device *adev)
1331 {
1332         uint32_t data, data2;
1333
1334         data = RREG32(mmUVD_CGC_CTRL);
1335         data2 = RREG32(mmUVD_SUVD_CGC_CTRL);
1336
1337
1338         data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK |
1339                   UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
1340
1341
1342         data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK |
1343                 (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) |
1344                 (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY));
1345
1346         data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
1347                         UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
1348                         UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
1349                         UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
1350                         UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
1351                         UVD_CGC_CTRL__SYS_MODE_MASK |
1352                         UVD_CGC_CTRL__UDEC_MODE_MASK |
1353                         UVD_CGC_CTRL__MPEG2_MODE_MASK |
1354                         UVD_CGC_CTRL__REGS_MODE_MASK |
1355                         UVD_CGC_CTRL__RBC_MODE_MASK |
1356                         UVD_CGC_CTRL__LMI_MC_MODE_MASK |
1357                         UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
1358                         UVD_CGC_CTRL__IDCT_MODE_MASK |
1359                         UVD_CGC_CTRL__MPRD_MODE_MASK |
1360                         UVD_CGC_CTRL__MPC_MODE_MASK |
1361                         UVD_CGC_CTRL__LBSI_MODE_MASK |
1362                         UVD_CGC_CTRL__LRBBM_MODE_MASK |
1363                         UVD_CGC_CTRL__WCB_MODE_MASK |
1364                         UVD_CGC_CTRL__VCPU_MODE_MASK |
1365                         UVD_CGC_CTRL__JPEG_MODE_MASK |
1366                         UVD_CGC_CTRL__SCPU_MODE_MASK |
1367                         UVD_CGC_CTRL__JPEG2_MODE_MASK);
1368         data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK |
1369                         UVD_SUVD_CGC_CTRL__SIT_MODE_MASK |
1370                         UVD_SUVD_CGC_CTRL__SMP_MODE_MASK |
1371                         UVD_SUVD_CGC_CTRL__SCM_MODE_MASK |
1372                         UVD_SUVD_CGC_CTRL__SDB_MODE_MASK);
1373
1374         WREG32(mmUVD_CGC_CTRL, data);
1375         WREG32(mmUVD_SUVD_CGC_CTRL, data2);
1376 }
1377
1378 #if 0
1379 static void uvd_v6_0_set_hw_clock_gating(struct amdgpu_device *adev)
1380 {
1381         uint32_t data, data1, cgc_flags, suvd_flags;
1382
1383         data = RREG32(mmUVD_CGC_GATE);
1384         data1 = RREG32(mmUVD_SUVD_CGC_GATE);
1385
1386         cgc_flags = UVD_CGC_GATE__SYS_MASK |
1387                 UVD_CGC_GATE__UDEC_MASK |
1388                 UVD_CGC_GATE__MPEG2_MASK |
1389                 UVD_CGC_GATE__RBC_MASK |
1390                 UVD_CGC_GATE__LMI_MC_MASK |
1391                 UVD_CGC_GATE__IDCT_MASK |
1392                 UVD_CGC_GATE__MPRD_MASK |
1393                 UVD_CGC_GATE__MPC_MASK |
1394                 UVD_CGC_GATE__LBSI_MASK |
1395                 UVD_CGC_GATE__LRBBM_MASK |
1396                 UVD_CGC_GATE__UDEC_RE_MASK |
1397                 UVD_CGC_GATE__UDEC_CM_MASK |
1398                 UVD_CGC_GATE__UDEC_IT_MASK |
1399                 UVD_CGC_GATE__UDEC_DB_MASK |
1400                 UVD_CGC_GATE__UDEC_MP_MASK |
1401                 UVD_CGC_GATE__WCB_MASK |
1402                 UVD_CGC_GATE__VCPU_MASK |
1403                 UVD_CGC_GATE__SCPU_MASK |
1404                 UVD_CGC_GATE__JPEG_MASK |
1405                 UVD_CGC_GATE__JPEG2_MASK;
1406
1407         suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
1408                                 UVD_SUVD_CGC_GATE__SIT_MASK |
1409                                 UVD_SUVD_CGC_GATE__SMP_MASK |
1410                                 UVD_SUVD_CGC_GATE__SCM_MASK |
1411                                 UVD_SUVD_CGC_GATE__SDB_MASK;
1412
1413         data |= cgc_flags;
1414         data1 |= suvd_flags;
1415
1416         WREG32(mmUVD_CGC_GATE, data);
1417         WREG32(mmUVD_SUVD_CGC_GATE, data1);
1418 }
1419 #endif
1420
1421 static void uvd_v6_0_enable_mgcg(struct amdgpu_device *adev,
1422                                  bool enable)
1423 {
1424         u32 orig, data;
1425
1426         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) {
1427                 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
1428                 data |= 0xfff;
1429                 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
1430
1431                 orig = data = RREG32(mmUVD_CGC_CTRL);
1432                 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
1433                 if (orig != data)
1434                         WREG32(mmUVD_CGC_CTRL, data);
1435         } else {
1436                 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
1437                 data &= ~0xfff;
1438                 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
1439
1440                 orig = data = RREG32(mmUVD_CGC_CTRL);
1441                 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
1442                 if (orig != data)
1443                         WREG32(mmUVD_CGC_CTRL, data);
1444         }
1445 }
1446
1447 static int uvd_v6_0_set_clockgating_state(void *handle,
1448                                           enum amd_clockgating_state state)
1449 {
1450         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1451         bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
1452
1453         if (enable) {
1454                 /* wait for STATUS to clear */
1455                 if (uvd_v6_0_wait_for_idle(handle))
1456                         return -EBUSY;
1457                 uvd_v6_0_enable_clock_gating(adev, true);
1458                 /* enable HW gates because UVD is idle */
1459 /*              uvd_v6_0_set_hw_clock_gating(adev); */
1460         } else {
1461                 /* disable HW gating and enable Sw gating */
1462                 uvd_v6_0_enable_clock_gating(adev, false);
1463         }
1464         uvd_v6_0_set_sw_clock_gating(adev);
1465         return 0;
1466 }
1467
1468 static int uvd_v6_0_set_powergating_state(void *handle,
1469                                           enum amd_powergating_state state)
1470 {
1471         /* This doesn't actually powergate the UVD block.
1472          * That's done in the dpm code via the SMC.  This
1473          * just re-inits the block as necessary.  The actual
1474          * gating still happens in the dpm code.  We should
1475          * revisit this when there is a cleaner line between
1476          * the smc and the hw blocks
1477          */
1478         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1479         int ret = 0;
1480
1481         WREG32(mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK);
1482
1483         if (state == AMD_PG_STATE_GATE) {
1484                 uvd_v6_0_stop(adev);
1485         } else {
1486                 ret = uvd_v6_0_start(adev);
1487                 if (ret)
1488                         goto out;
1489         }
1490
1491 out:
1492         return ret;
1493 }
1494
1495 static void uvd_v6_0_get_clockgating_state(void *handle, u32 *flags)
1496 {
1497         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1498         int data;
1499
1500         mutex_lock(&adev->pm.mutex);
1501
1502         if (adev->flags & AMD_IS_APU)
1503                 data = RREG32_SMC(ixCURRENT_PG_STATUS_APU);
1504         else
1505                 data = RREG32_SMC(ixCURRENT_PG_STATUS);
1506
1507         if (data & CURRENT_PG_STATUS__UVD_PG_STATUS_MASK) {
1508                 DRM_INFO("Cannot get clockgating state when UVD is powergated.\n");
1509                 goto out;
1510         }
1511
1512         /* AMD_CG_SUPPORT_UVD_MGCG */
1513         data = RREG32(mmUVD_CGC_CTRL);
1514         if (data & UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK)
1515                 *flags |= AMD_CG_SUPPORT_UVD_MGCG;
1516
1517 out:
1518         mutex_unlock(&adev->pm.mutex);
1519 }
1520
1521 static const struct amd_ip_funcs uvd_v6_0_ip_funcs = {
1522         .name = "uvd_v6_0",
1523         .early_init = uvd_v6_0_early_init,
1524         .late_init = NULL,
1525         .sw_init = uvd_v6_0_sw_init,
1526         .sw_fini = uvd_v6_0_sw_fini,
1527         .hw_init = uvd_v6_0_hw_init,
1528         .hw_fini = uvd_v6_0_hw_fini,
1529         .suspend = uvd_v6_0_suspend,
1530         .resume = uvd_v6_0_resume,
1531         .is_idle = uvd_v6_0_is_idle,
1532         .wait_for_idle = uvd_v6_0_wait_for_idle,
1533         .check_soft_reset = uvd_v6_0_check_soft_reset,
1534         .pre_soft_reset = uvd_v6_0_pre_soft_reset,
1535         .soft_reset = uvd_v6_0_soft_reset,
1536         .post_soft_reset = uvd_v6_0_post_soft_reset,
1537         .set_clockgating_state = uvd_v6_0_set_clockgating_state,
1538         .set_powergating_state = uvd_v6_0_set_powergating_state,
1539         .get_clockgating_state = uvd_v6_0_get_clockgating_state,
1540 };
1541
1542 static const struct amdgpu_ring_funcs uvd_v6_0_ring_phys_funcs = {
1543         .type = AMDGPU_RING_TYPE_UVD,
1544         .align_mask = 0xf,
1545         .nop = PACKET0(mmUVD_NO_OP, 0),
1546         .support_64bit_ptrs = false,
1547         .get_rptr = uvd_v6_0_ring_get_rptr,
1548         .get_wptr = uvd_v6_0_ring_get_wptr,
1549         .set_wptr = uvd_v6_0_ring_set_wptr,
1550         .parse_cs = amdgpu_uvd_ring_parse_cs,
1551         .emit_frame_size =
1552                 2 + /* uvd_v6_0_ring_emit_hdp_flush */
1553                 2 + /* uvd_v6_0_ring_emit_hdp_invalidate */
1554                 10 + /* uvd_v6_0_ring_emit_pipeline_sync */
1555                 14, /* uvd_v6_0_ring_emit_fence x1 no user fence */
1556         .emit_ib_size = 8, /* uvd_v6_0_ring_emit_ib */
1557         .emit_ib = uvd_v6_0_ring_emit_ib,
1558         .emit_fence = uvd_v6_0_ring_emit_fence,
1559         .emit_hdp_flush = uvd_v6_0_ring_emit_hdp_flush,
1560         .emit_hdp_invalidate = uvd_v6_0_ring_emit_hdp_invalidate,
1561         .test_ring = uvd_v6_0_ring_test_ring,
1562         .test_ib = amdgpu_uvd_ring_test_ib,
1563         .insert_nop = amdgpu_ring_insert_nop,
1564         .pad_ib = amdgpu_ring_generic_pad_ib,
1565         .begin_use = amdgpu_uvd_ring_begin_use,
1566         .end_use = amdgpu_uvd_ring_end_use,
1567 };
1568
1569 static const struct amdgpu_ring_funcs uvd_v6_0_ring_vm_funcs = {
1570         .type = AMDGPU_RING_TYPE_UVD,
1571         .align_mask = 0xf,
1572         .nop = PACKET0(mmUVD_NO_OP, 0),
1573         .support_64bit_ptrs = false,
1574         .get_rptr = uvd_v6_0_ring_get_rptr,
1575         .get_wptr = uvd_v6_0_ring_get_wptr,
1576         .set_wptr = uvd_v6_0_ring_set_wptr,
1577         .emit_frame_size =
1578                 2 + /* uvd_v6_0_ring_emit_hdp_flush */
1579                 2 + /* uvd_v6_0_ring_emit_hdp_invalidate */
1580                 10 + /* uvd_v6_0_ring_emit_pipeline_sync */
1581                 20 + /* uvd_v6_0_ring_emit_vm_flush */
1582                 14 + 14, /* uvd_v6_0_ring_emit_fence x2 vm fence */
1583         .emit_ib_size = 8, /* uvd_v6_0_ring_emit_ib */
1584         .emit_ib = uvd_v6_0_ring_emit_ib,
1585         .emit_fence = uvd_v6_0_ring_emit_fence,
1586         .emit_vm_flush = uvd_v6_0_ring_emit_vm_flush,
1587         .emit_pipeline_sync = uvd_v6_0_ring_emit_pipeline_sync,
1588         .emit_hdp_flush = uvd_v6_0_ring_emit_hdp_flush,
1589         .emit_hdp_invalidate = uvd_v6_0_ring_emit_hdp_invalidate,
1590         .test_ring = uvd_v6_0_ring_test_ring,
1591         .test_ib = amdgpu_uvd_ring_test_ib,
1592         .insert_nop = amdgpu_ring_insert_nop,
1593         .pad_ib = amdgpu_ring_generic_pad_ib,
1594         .begin_use = amdgpu_uvd_ring_begin_use,
1595         .end_use = amdgpu_uvd_ring_end_use,
1596 };
1597
1598 static const struct amdgpu_ring_funcs uvd_v6_0_enc_ring_vm_funcs = {
1599         .type = AMDGPU_RING_TYPE_UVD_ENC,
1600         .align_mask = 0x3f,
1601         .nop = HEVC_ENC_CMD_NO_OP,
1602         .support_64bit_ptrs = false,
1603         .get_rptr = uvd_v6_0_enc_ring_get_rptr,
1604         .get_wptr = uvd_v6_0_enc_ring_get_wptr,
1605         .set_wptr = uvd_v6_0_enc_ring_set_wptr,
1606         .emit_frame_size =
1607                 4 + /* uvd_v6_0_enc_ring_emit_pipeline_sync */
1608                 6 + /* uvd_v6_0_enc_ring_emit_vm_flush */
1609                 5 + 5 + /* uvd_v6_0_enc_ring_emit_fence x2 vm fence */
1610                 1, /* uvd_v6_0_enc_ring_insert_end */
1611         .emit_ib_size = 5, /* uvd_v6_0_enc_ring_emit_ib */
1612         .emit_ib = uvd_v6_0_enc_ring_emit_ib,
1613         .emit_fence = uvd_v6_0_enc_ring_emit_fence,
1614         .emit_vm_flush = uvd_v6_0_enc_ring_emit_vm_flush,
1615         .emit_pipeline_sync = uvd_v6_0_enc_ring_emit_pipeline_sync,
1616         .test_ring = uvd_v6_0_enc_ring_test_ring,
1617         .test_ib = uvd_v6_0_enc_ring_test_ib,
1618         .insert_nop = amdgpu_ring_insert_nop,
1619         .insert_end = uvd_v6_0_enc_ring_insert_end,
1620         .pad_ib = amdgpu_ring_generic_pad_ib,
1621         .begin_use = amdgpu_uvd_ring_begin_use,
1622         .end_use = amdgpu_uvd_ring_end_use,
1623 };
1624
1625 static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev)
1626 {
1627         if (adev->asic_type >= CHIP_POLARIS10) {
1628                 adev->uvd.ring.funcs = &uvd_v6_0_ring_vm_funcs;
1629                 DRM_INFO("UVD is enabled in VM mode\n");
1630         } else {
1631                 adev->uvd.ring.funcs = &uvd_v6_0_ring_phys_funcs;
1632                 DRM_INFO("UVD is enabled in physical mode\n");
1633         }
1634 }
1635
1636 static void uvd_v6_0_set_enc_ring_funcs(struct amdgpu_device *adev)
1637 {
1638         int i;
1639
1640         for (i = 0; i < adev->uvd.num_enc_rings; ++i)
1641                 adev->uvd.ring_enc[i].funcs = &uvd_v6_0_enc_ring_vm_funcs;
1642
1643         DRM_INFO("UVD ENC is enabled in VM mode\n");
1644 }
1645
1646 static const struct amdgpu_irq_src_funcs uvd_v6_0_irq_funcs = {
1647         .set = uvd_v6_0_set_interrupt_state,
1648         .process = uvd_v6_0_process_interrupt,
1649 };
1650
1651 static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev)
1652 {
1653         if (uvd_v6_0_enc_support(adev))
1654                 adev->uvd.irq.num_types = adev->uvd.num_enc_rings + 1;
1655         else
1656                 adev->uvd.irq.num_types = 1;
1657
1658         adev->uvd.irq.funcs = &uvd_v6_0_irq_funcs;
1659 }
1660
1661 const struct amdgpu_ip_block_version uvd_v6_0_ip_block =
1662 {
1663                 .type = AMD_IP_BLOCK_TYPE_UVD,
1664                 .major = 6,
1665                 .minor = 0,
1666                 .rev = 0,
1667                 .funcs = &uvd_v6_0_ip_funcs,
1668 };
1669
1670 const struct amdgpu_ip_block_version uvd_v6_2_ip_block =
1671 {
1672                 .type = AMD_IP_BLOCK_TYPE_UVD,
1673                 .major = 6,
1674                 .minor = 2,
1675                 .rev = 0,
1676                 .funcs = &uvd_v6_0_ip_funcs,
1677 };
1678
1679 const struct amdgpu_ip_block_version uvd_v6_3_ip_block =
1680 {
1681                 .type = AMD_IP_BLOCK_TYPE_UVD,
1682                 .major = 6,
1683                 .minor = 3,
1684                 .rev = 0,
1685                 .funcs = &uvd_v6_0_ip_funcs,
1686 };