2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Christian König <christian.koenig@amd.com>
25 #include <linux/firmware.h>
28 #include "amdgpu_uvd.h"
31 #include "uvd/uvd_4_2_d.h"
32 #include "uvd/uvd_4_2_sh_mask.h"
34 #include "oss/oss_2_0_d.h"
35 #include "oss/oss_2_0_sh_mask.h"
37 static void uvd_v4_2_mc_resume(struct amdgpu_device *adev);
38 static void uvd_v4_2_init_cg(struct amdgpu_device *adev);
39 static void uvd_v4_2_set_ring_funcs(struct amdgpu_device *adev);
40 static void uvd_v4_2_set_irq_funcs(struct amdgpu_device *adev);
41 static int uvd_v4_2_start(struct amdgpu_device *adev);
42 static void uvd_v4_2_stop(struct amdgpu_device *adev);
45 * uvd_v4_2_ring_get_rptr - get read pointer
47 * @ring: amdgpu_ring pointer
49 * Returns the current hardware read pointer
51 static uint32_t uvd_v4_2_ring_get_rptr(struct amdgpu_ring *ring)
53 struct amdgpu_device *adev = ring->adev;
55 return RREG32(mmUVD_RBC_RB_RPTR);
59 * uvd_v4_2_ring_get_wptr - get write pointer
61 * @ring: amdgpu_ring pointer
63 * Returns the current hardware write pointer
65 static uint32_t uvd_v4_2_ring_get_wptr(struct amdgpu_ring *ring)
67 struct amdgpu_device *adev = ring->adev;
69 return RREG32(mmUVD_RBC_RB_WPTR);
73 * uvd_v4_2_ring_set_wptr - set write pointer
75 * @ring: amdgpu_ring pointer
77 * Commits the write pointer to the hardware
79 static void uvd_v4_2_ring_set_wptr(struct amdgpu_ring *ring)
81 struct amdgpu_device *adev = ring->adev;
83 WREG32(mmUVD_RBC_RB_WPTR, ring->wptr);
86 static int uvd_v4_2_early_init(void *handle)
88 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
90 uvd_v4_2_set_ring_funcs(adev);
91 uvd_v4_2_set_irq_funcs(adev);
96 static int uvd_v4_2_sw_init(void *handle)
98 struct amdgpu_ring *ring;
99 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
103 r = amdgpu_irq_add_id(adev, 124, &adev->uvd.irq);
107 r = amdgpu_uvd_sw_init(adev);
111 r = amdgpu_uvd_resume(adev);
115 ring = &adev->uvd.ring;
116 sprintf(ring->name, "uvd");
117 r = amdgpu_ring_init(adev, ring, 512, CP_PACKET2, 0xf,
118 &adev->uvd.irq, 0, AMDGPU_RING_TYPE_UVD);
123 static int uvd_v4_2_sw_fini(void *handle)
126 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
128 r = amdgpu_uvd_suspend(adev);
132 r = amdgpu_uvd_sw_fini(adev);
140 * uvd_v4_2_hw_init - start and test UVD block
142 * @adev: amdgpu_device pointer
144 * Initialize the hardware, boot up the VCPU and do some testing
146 static int uvd_v4_2_hw_init(void *handle)
148 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
149 struct amdgpu_ring *ring = &adev->uvd.ring;
153 /* raise clocks while booting up the VCPU */
154 amdgpu_asic_set_uvd_clocks(adev, 53300, 40000);
156 r = uvd_v4_2_start(adev);
161 r = amdgpu_ring_test_ring(ring);
167 r = amdgpu_ring_alloc(ring, 10);
169 DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r);
173 tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);
174 amdgpu_ring_write(ring, tmp);
175 amdgpu_ring_write(ring, 0xFFFFF);
177 tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0);
178 amdgpu_ring_write(ring, tmp);
179 amdgpu_ring_write(ring, 0xFFFFF);
181 tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0);
182 amdgpu_ring_write(ring, tmp);
183 amdgpu_ring_write(ring, 0xFFFFF);
185 /* Clear timeout status bits */
186 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0));
187 amdgpu_ring_write(ring, 0x8);
189 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0));
190 amdgpu_ring_write(ring, 3);
192 amdgpu_ring_commit(ring);
195 /* lower clocks again */
196 amdgpu_asic_set_uvd_clocks(adev, 0, 0);
199 DRM_INFO("UVD initialized successfully.\n");
205 * uvd_v4_2_hw_fini - stop the hardware block
207 * @adev: amdgpu_device pointer
209 * Stop the UVD block, mark ring as not ready any more
211 static int uvd_v4_2_hw_fini(void *handle)
213 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
214 struct amdgpu_ring *ring = &adev->uvd.ring;
222 static int uvd_v4_2_suspend(void *handle)
225 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
227 r = uvd_v4_2_hw_fini(adev);
231 r = amdgpu_uvd_suspend(adev);
238 static int uvd_v4_2_resume(void *handle)
241 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
243 r = amdgpu_uvd_resume(adev);
247 r = uvd_v4_2_hw_init(adev);
255 * uvd_v4_2_start - start UVD block
257 * @adev: amdgpu_device pointer
259 * Setup and start the UVD block
261 static int uvd_v4_2_start(struct amdgpu_device *adev)
263 struct amdgpu_ring *ring = &adev->uvd.ring;
267 /* disable byte swapping */
268 u32 lmi_swap_cntl = 0;
269 u32 mp_swap_cntl = 0;
271 uvd_v4_2_mc_resume(adev);
273 /* disable clock gating */
274 WREG32(mmUVD_CGC_GATE, 0);
276 /* disable interupt */
277 WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1));
279 /* Stall UMC and register bus before resetting VCPU */
280 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
283 /* put LMI, VCPU, RBC etc... into reset */
284 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
285 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
286 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
287 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
288 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
291 /* take UVD block out of reset */
292 WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK);
295 /* initialize UVD memory controller */
296 WREG32(mmUVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) |
297 (1 << 21) | (1 << 9) | (1 << 20));
300 /* swap (8 in 32) RB and IB */
304 WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
305 WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl);
307 WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040);
308 WREG32(mmUVD_MPC_SET_MUXA1, 0x0);
309 WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040);
310 WREG32(mmUVD_MPC_SET_MUXB1, 0x0);
311 WREG32(mmUVD_MPC_SET_ALU, 0);
312 WREG32(mmUVD_MPC_SET_MUX, 0x88);
314 /* take all subblocks out of reset, except VCPU */
315 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
318 /* enable VCPU clock */
319 WREG32(mmUVD_VCPU_CNTL, 1 << 9);
322 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));
324 /* boot up the VCPU */
325 WREG32(mmUVD_SOFT_RESET, 0);
328 for (i = 0; i < 10; ++i) {
330 for (j = 0; j < 100; ++j) {
331 status = RREG32(mmUVD_STATUS);
340 DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n");
341 WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
342 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
344 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
350 DRM_ERROR("UVD not responding, giving up!!!\n");
354 /* enable interupt */
355 WREG32_P(mmUVD_MASTINT_EN, 3<<1, ~(3 << 1));
357 /* force RBC into idle state */
358 WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);
360 /* Set the write pointer delay */
361 WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0);
363 /* programm the 4GB memory segment for rptr and ring buffer */
364 WREG32(mmUVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) |
365 (0x7 << 16) | (0x1 << 31));
367 /* Initialize the ring buffer's read and write pointers */
368 WREG32(mmUVD_RBC_RB_RPTR, 0x0);
370 ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);
371 WREG32(mmUVD_RBC_RB_WPTR, ring->wptr);
373 /* set the ring address */
374 WREG32(mmUVD_RBC_RB_BASE, ring->gpu_addr);
376 /* Set ring buffer size */
377 rb_bufsz = order_base_2(ring->ring_size);
378 rb_bufsz = (0x1 << 8) | rb_bufsz;
379 WREG32_P(mmUVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f);
385 * uvd_v4_2_stop - stop UVD block
387 * @adev: amdgpu_device pointer
391 static void uvd_v4_2_stop(struct amdgpu_device *adev)
393 /* force RBC into idle state */
394 WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);
396 /* Stall UMC and register bus before resetting VCPU */
397 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
400 /* put VCPU into reset */
401 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
404 /* disable VCPU clock */
405 WREG32(mmUVD_VCPU_CNTL, 0x0);
407 /* Unstall UMC and register bus */
408 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));
412 * uvd_v4_2_ring_emit_fence - emit an fence & trap command
414 * @ring: amdgpu_ring pointer
415 * @fence: fence to emit
417 * Write a fence and a trap command to the ring.
419 static void uvd_v4_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
422 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
424 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
425 amdgpu_ring_write(ring, seq);
426 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
427 amdgpu_ring_write(ring, addr & 0xffffffff);
428 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
429 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
430 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
431 amdgpu_ring_write(ring, 0);
433 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
434 amdgpu_ring_write(ring, 0);
435 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
436 amdgpu_ring_write(ring, 0);
437 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
438 amdgpu_ring_write(ring, 2);
442 * uvd_v4_2_ring_test_ring - register write test
444 * @ring: amdgpu_ring pointer
446 * Test if we can successfully write to the context register
448 static int uvd_v4_2_ring_test_ring(struct amdgpu_ring *ring)
450 struct amdgpu_device *adev = ring->adev;
455 WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD);
456 r = amdgpu_ring_alloc(ring, 3);
458 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
462 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
463 amdgpu_ring_write(ring, 0xDEADBEEF);
464 amdgpu_ring_commit(ring);
465 for (i = 0; i < adev->usec_timeout; i++) {
466 tmp = RREG32(mmUVD_CONTEXT_ID);
467 if (tmp == 0xDEADBEEF)
472 if (i < adev->usec_timeout) {
473 DRM_INFO("ring test on %d succeeded in %d usecs\n",
476 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
484 * uvd_v4_2_ring_emit_ib - execute indirect buffer
486 * @ring: amdgpu_ring pointer
487 * @ib: indirect buffer to execute
489 * Write ring commands to execute the indirect buffer
491 static void uvd_v4_2_ring_emit_ib(struct amdgpu_ring *ring,
492 struct amdgpu_ib *ib,
493 unsigned vm_id, bool ctx_switch)
495 amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_BASE, 0));
496 amdgpu_ring_write(ring, ib->gpu_addr);
497 amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0));
498 amdgpu_ring_write(ring, ib->length_dw);
502 * uvd_v4_2_ring_test_ib - test ib execution
504 * @ring: amdgpu_ring pointer
506 * Test if we can successfully execute an IB
508 static int uvd_v4_2_ring_test_ib(struct amdgpu_ring *ring)
510 struct amdgpu_device *adev = ring->adev;
511 struct fence *fence = NULL;
514 r = amdgpu_asic_set_uvd_clocks(adev, 53300, 40000);
516 DRM_ERROR("amdgpu: failed to raise UVD clocks (%d).\n", r);
520 r = amdgpu_uvd_get_create_msg(ring, 1, NULL);
522 DRM_ERROR("amdgpu: failed to get create msg (%d).\n", r);
526 r = amdgpu_uvd_get_destroy_msg(ring, 1, true, &fence);
528 DRM_ERROR("amdgpu: failed to get destroy ib (%d).\n", r);
532 r = fence_wait(fence, false);
534 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
537 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
540 amdgpu_asic_set_uvd_clocks(adev, 0, 0);
545 * uvd_v4_2_mc_resume - memory controller programming
547 * @adev: amdgpu_device pointer
549 * Let the UVD memory controller know it's offsets
551 static void uvd_v4_2_mc_resume(struct amdgpu_device *adev)
556 /* programm the VCPU memory controller bits 0-27 */
557 addr = (adev->uvd.gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3;
558 size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4) >> 3;
559 WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr);
560 WREG32(mmUVD_VCPU_CACHE_SIZE0, size);
563 size = AMDGPU_UVD_HEAP_SIZE >> 3;
564 WREG32(mmUVD_VCPU_CACHE_OFFSET1, addr);
565 WREG32(mmUVD_VCPU_CACHE_SIZE1, size);
568 size = (AMDGPU_UVD_STACK_SIZE +
569 (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles)) >> 3;
570 WREG32(mmUVD_VCPU_CACHE_OFFSET2, addr);
571 WREG32(mmUVD_VCPU_CACHE_SIZE2, size);
574 addr = (adev->uvd.gpu_addr >> 28) & 0xF;
575 WREG32(mmUVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0));
578 addr = (adev->uvd.gpu_addr >> 32) & 0xFF;
579 WREG32(mmUVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31));
581 WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
582 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
583 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
585 uvd_v4_2_init_cg(adev);
588 static void uvd_v4_2_enable_mgcg(struct amdgpu_device *adev,
593 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) {
594 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
596 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
598 orig = data = RREG32(mmUVD_CGC_CTRL);
599 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
601 WREG32(mmUVD_CGC_CTRL, data);
603 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
605 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
607 orig = data = RREG32(mmUVD_CGC_CTRL);
608 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
610 WREG32(mmUVD_CGC_CTRL, data);
614 static void uvd_v4_2_set_dcm(struct amdgpu_device *adev,
619 tmp = RREG32(mmUVD_CGC_CTRL);
620 tmp &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
621 tmp |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK |
622 (1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT) |
623 (4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT);
627 tmp2 = UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK |
628 UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK |
629 (7 << UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT);
635 WREG32(mmUVD_CGC_CTRL, tmp);
636 WREG32_UVD_CTX(ixUVD_CGC_CTRL2, tmp2);
639 static void uvd_v4_2_init_cg(struct amdgpu_device *adev)
644 uvd_v4_2_set_dcm(adev, false);
646 u32 tmp = RREG32(mmUVD_CGC_CTRL);
647 tmp &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
648 WREG32(mmUVD_CGC_CTRL, tmp);
652 static bool uvd_v4_2_is_idle(void *handle)
654 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
656 return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
659 static int uvd_v4_2_wait_for_idle(void *handle)
662 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
664 for (i = 0; i < adev->usec_timeout; i++) {
665 if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK))
671 static int uvd_v4_2_soft_reset(void *handle)
673 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
677 WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK,
678 ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK);
681 return uvd_v4_2_start(adev);
684 static int uvd_v4_2_set_interrupt_state(struct amdgpu_device *adev,
685 struct amdgpu_irq_src *source,
687 enum amdgpu_interrupt_state state)
693 static int uvd_v4_2_process_interrupt(struct amdgpu_device *adev,
694 struct amdgpu_irq_src *source,
695 struct amdgpu_iv_entry *entry)
697 DRM_DEBUG("IH: UVD TRAP\n");
698 amdgpu_fence_process(&adev->uvd.ring);
702 static int uvd_v4_2_set_clockgating_state(void *handle,
703 enum amd_clockgating_state state)
706 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
708 if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG))
711 if (state == AMD_CG_STATE_GATE)
714 uvd_v4_2_enable_mgcg(adev, gate);
719 static int uvd_v4_2_set_powergating_state(void *handle,
720 enum amd_powergating_state state)
722 /* This doesn't actually powergate the UVD block.
723 * That's done in the dpm code via the SMC. This
724 * just re-inits the block as necessary. The actual
725 * gating still happens in the dpm code. We should
726 * revisit this when there is a cleaner line between
727 * the smc and the hw blocks
729 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
731 if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD))
734 if (state == AMD_PG_STATE_GATE) {
738 return uvd_v4_2_start(adev);
742 const struct amd_ip_funcs uvd_v4_2_ip_funcs = {
744 .early_init = uvd_v4_2_early_init,
746 .sw_init = uvd_v4_2_sw_init,
747 .sw_fini = uvd_v4_2_sw_fini,
748 .hw_init = uvd_v4_2_hw_init,
749 .hw_fini = uvd_v4_2_hw_fini,
750 .suspend = uvd_v4_2_suspend,
751 .resume = uvd_v4_2_resume,
752 .is_idle = uvd_v4_2_is_idle,
753 .wait_for_idle = uvd_v4_2_wait_for_idle,
754 .soft_reset = uvd_v4_2_soft_reset,
755 .set_clockgating_state = uvd_v4_2_set_clockgating_state,
756 .set_powergating_state = uvd_v4_2_set_powergating_state,
759 static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs = {
760 .get_rptr = uvd_v4_2_ring_get_rptr,
761 .get_wptr = uvd_v4_2_ring_get_wptr,
762 .set_wptr = uvd_v4_2_ring_set_wptr,
763 .parse_cs = amdgpu_uvd_ring_parse_cs,
764 .emit_ib = uvd_v4_2_ring_emit_ib,
765 .emit_fence = uvd_v4_2_ring_emit_fence,
766 .test_ring = uvd_v4_2_ring_test_ring,
767 .test_ib = uvd_v4_2_ring_test_ib,
768 .insert_nop = amdgpu_ring_insert_nop,
769 .pad_ib = amdgpu_ring_generic_pad_ib,
772 static void uvd_v4_2_set_ring_funcs(struct amdgpu_device *adev)
774 adev->uvd.ring.funcs = &uvd_v4_2_ring_funcs;
777 static const struct amdgpu_irq_src_funcs uvd_v4_2_irq_funcs = {
778 .set = uvd_v4_2_set_interrupt_state,
779 .process = uvd_v4_2_process_interrupt,
782 static void uvd_v4_2_set_irq_funcs(struct amdgpu_device *adev)
784 adev->uvd.irq.num_types = 1;
785 adev->uvd.irq.funcs = &uvd_v4_2_irq_funcs;