drivers/gpu/drm/amd/amdgpu/soc15.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <linux/slab.h>
  25 #include <linux/module.h>
  26 #include <linux/pci.h>
  27
  28 #include <drm/amdgpu_drm.h>
  29
  30 #include "amdgpu.h"
  31 #include "amdgpu_atombios.h"
  32 #include "amdgpu_ih.h"
  33 #include "amdgpu_uvd.h"
  34 #include "amdgpu_vce.h"
  35 #include "amdgpu_ucode.h"
  36 #include "amdgpu_psp.h"
  37 #include "atom.h"
  38 #include "amd_pcie.h"
  39
  40 #include "uvd/uvd_7_0_offset.h"
  41 #include "gc/gc_9_0_offset.h"
  42 #include "gc/gc_9_0_sh_mask.h"
  43 #include "sdma0/sdma0_4_0_offset.h"
  44 #include "sdma1/sdma1_4_0_offset.h"
  45 #include "nbio/nbio_7_0_default.h"
  46 #include "nbio/nbio_7_0_offset.h"
  47 #include "nbio/nbio_7_0_sh_mask.h"
  48 #include "nbio/nbio_7_0_smn.h"
  49 #include "mp/mp_9_0_offset.h"
  50
  51 #include "soc15.h"
  52 #include "soc15_common.h"
  53 #include "gfx_v9_0.h"
  54 #include "gmc_v9_0.h"
  55 #include "gfxhub_v1_0.h"
  56 #include "mmhub_v1_0.h"
  57 #include "df_v1_7.h"
  58 #include "df_v3_6.h"
  59 #include "nbio_v6_1.h"
  60 #include "nbio_v7_0.h"
  61 #include "nbio_v7_4.h"
  62 #include "hdp_v4_0.h"
  63 #include "vega10_ih.h"
  64 #include "vega20_ih.h"
  65 #include "navi10_ih.h"
  66 #include "sdma_v4_0.h"
  67 #include "uvd_v7_0.h"
  68 #include "vce_v4_0.h"
  69 #include "vcn_v1_0.h"
  70 #include "vcn_v2_0.h"
  71 #include "jpeg_v2_0.h"
  72 #include "vcn_v2_5.h"
  73 #include "jpeg_v2_5.h"
  74 #include "smuio_v9_0.h"
  75 #include "smuio_v11_0.h"
  76 #include "smuio_v13_0.h"
  77 #include "amdgpu_vkms.h"
  78 #include "mxgpu_ai.h"
  79 #include "amdgpu_ras.h"
  80 #include "amdgpu_xgmi.h"
  81 #include <uapi/linux/kfd_ioctl.h>
  82
  83 #define mmMP0_MISC_CGTT_CTRL0                                                                   0x01b9
  84 #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX                                                          0
  85 #define mmMP0_MISC_LIGHT_SLEEP_CTRL                                                             0x01ba
  86 #define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX                                                    0
  87
  88 static const struct amd_ip_funcs soc15_common_ip_funcs;
  89
  90 /* Vega, Raven, Arcturus */
  91 static const struct amdgpu_video_codec_info vega_video_codecs_encode_array[] =
  92 {
  93         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
  94         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
  95 };
  96
  97 static const struct amdgpu_video_codecs vega_video_codecs_encode =
  98 {
  99         .codec_count = ARRAY_SIZE(vega_video_codecs_encode_array),
 100         .codec_array = vega_video_codecs_encode_array,
 101 };
 102
 103 /* Vega */
 104 static const struct amdgpu_video_codec_info vega_video_codecs_decode_array[] =
 105 {
 106         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
 107         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
 108         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
 109         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
 110         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 4096, 186)},
 111         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
 112 };
 113
 114 static const struct amdgpu_video_codecs vega_video_codecs_decode =
 115 {
 116         .codec_count = ARRAY_SIZE(vega_video_codecs_decode_array),
 117         .codec_array = vega_video_codecs_decode_array,
 118 };
 119
 120 /* Raven */
 121 static const struct amdgpu_video_codec_info rv_video_codecs_decode_array[] =
 122 {
 123         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
 124         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
 125         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
 126         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
 127         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 4096, 186)},
 128         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
 129         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 4096, 4096, 0)},
 130 };
 131
 132 static const struct amdgpu_video_codecs rv_video_codecs_decode =
 133 {
 134         .codec_count = ARRAY_SIZE(rv_video_codecs_decode_array),
 135         .codec_array = rv_video_codecs_decode_array,
 136 };
 137
 138 /* Renoir, Arcturus */
 139 static const struct amdgpu_video_codec_info rn_video_codecs_decode_array[] =
 140 {
 141         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
 142         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
 143         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
 144         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
 145         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
 146         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
 147         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
 148 };
 149
 150 static const struct amdgpu_video_codecs rn_video_codecs_decode =
 151 {
 152         .codec_count = ARRAY_SIZE(rn_video_codecs_decode_array),
 153         .codec_array = rn_video_codecs_decode_array,
 154 };
 155
 156 static int soc15_query_video_codecs(struct amdgpu_device *adev, bool encode,
 157                                     const struct amdgpu_video_codecs **codecs)
 158 {
 159         if (adev->ip_versions[VCE_HWIP][0]) {
 160                 switch (adev->ip_versions[VCE_HWIP][0]) {
 161                 case IP_VERSION(4, 0, 0):
 162                 case IP_VERSION(4, 1, 0):
 163                         if (encode)
 164                                 *codecs = &vega_video_codecs_encode;
 165                         else
 166                                 *codecs = &vega_video_codecs_decode;
 167                         return 0;
 168                 default:
 169                         return -EINVAL;
 170                 }
 171         } else {
 172                 switch (adev->ip_versions[UVD_HWIP][0]) {
 173                 case IP_VERSION(1, 0, 0):
 174                 case IP_VERSION(1, 0, 1):
 175                         if (encode)
 176                                 *codecs = &vega_video_codecs_encode;
 177                         else
 178                                 *codecs = &rv_video_codecs_decode;
 179                         return 0;
 180                 case IP_VERSION(2, 5, 0):
 181                 case IP_VERSION(2, 6, 0):
 182                 case IP_VERSION(2, 2, 0):
 183                         if (encode)
 184                                 *codecs = &vega_video_codecs_encode;
 185                         else
 186                                 *codecs = &rn_video_codecs_decode;
 187                         return 0;
 188                 default:
 189                         return -EINVAL;
 190                 }
 191         }
 192 }
 193
 194 /*
 195  * Indirect registers accessor
 196  */
 197 static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg)
 198 {
 199         unsigned long address, data;
 200         address = adev->nbio.funcs->get_pcie_index_offset(adev);
 201         data = adev->nbio.funcs->get_pcie_data_offset(adev);
 202
 203         return amdgpu_device_indirect_rreg(adev, address, data, reg);
 204 }
 205
 206 static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 207 {
 208         unsigned long address, data;
 209
 210         address = adev->nbio.funcs->get_pcie_index_offset(adev);
 211         data = adev->nbio.funcs->get_pcie_data_offset(adev);
 212
 213         amdgpu_device_indirect_wreg(adev, address, data, reg, v);
 214 }
 215
 216 static u64 soc15_pcie_rreg64(struct amdgpu_device *adev, u32 reg)
 217 {
 218         unsigned long address, data;
 219         address = adev->nbio.funcs->get_pcie_index_offset(adev);
 220         data = adev->nbio.funcs->get_pcie_data_offset(adev);
 221
 222         return amdgpu_device_indirect_rreg64(adev, address, data, reg);
 223 }
 224
 225 static void soc15_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v)
 226 {
 227         unsigned long address, data;
 228
 229         address = adev->nbio.funcs->get_pcie_index_offset(adev);
 230         data = adev->nbio.funcs->get_pcie_data_offset(adev);
 231
 232         amdgpu_device_indirect_wreg64(adev, address, data, reg, v);
 233 }
 234
 235 static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
 236 {
 237         unsigned long flags, address, data;
 238         u32 r;
 239
 240         address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
 241         data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
 242
 243         spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
 244         WREG32(address, ((reg) & 0x1ff));
 245         r = RREG32(data);
 246         spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
 247         return r;
 248 }
 249
 250 static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 251 {
 252         unsigned long flags, address, data;
 253
 254         address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
 255         data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
 256
 257         spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
 258         WREG32(address, ((reg) & 0x1ff));
 259         WREG32(data, (v));
 260         spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
 261 }
 262
 263 static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg)
 264 {
 265         unsigned long flags, address, data;
 266         u32 r;
 267
 268         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 269         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 270
 271         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 272         WREG32(address, (reg));
 273         r = RREG32(data);
 274         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 275         return r;
 276 }
 277
 278 static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 279 {
 280         unsigned long flags, address, data;
 281
 282         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 283         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 284
 285         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 286         WREG32(address, (reg));
 287         WREG32(data, (v));
 288         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 289 }
 290
 291 static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)
 292 {
 293         unsigned long flags;
 294         u32 r;
 295
 296         spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
 297         WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
 298         r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA);
 299         spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
 300         return r;
 301 }
 302
 303 static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 304 {
 305         unsigned long flags;
 306
 307         spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
 308         WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
 309         WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v));
 310         spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
 311 }
 312
 313 static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg)
 314 {
 315         unsigned long flags;
 316         u32 r;
 317
 318         spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
 319         WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
 320         r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA);
 321         spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
 322         return r;
 323 }
 324
 325 static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 326 {
 327         unsigned long flags;
 328
 329         spin_lock_irqsave(&adev->se_cac_idx_lock, flags);
 330         WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
 331         WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v));
 332         spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags);
 333 }
 334
 335 static u32 soc15_get_config_memsize(struct amdgpu_device *adev)
 336 {
 337         return adev->nbio.funcs->get_memsize(adev);
 338 }
 339
 340 static u32 soc15_get_xclk(struct amdgpu_device *adev)
 341 {
 342         u32 reference_clock = adev->clock.spll.reference_freq;
 343
 344         if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(12, 0, 0) ||
 345             adev->ip_versions[MP1_HWIP][0] == IP_VERSION(12, 0, 1))
 346                 return 10000;
 347         if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(10, 0, 0) ||
 348             adev->ip_versions[MP1_HWIP][0] == IP_VERSION(10, 0, 1))
 349                 return reference_clock / 4;
 350
 351         return reference_clock;
 352 }
 353
 354
 355 void soc15_grbm_select(struct amdgpu_device *adev,
 356                      u32 me, u32 pipe, u32 queue, u32 vmid)
 357 {
 358         u32 grbm_gfx_cntl = 0;
 359         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
 360         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
 361         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
 362         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
 363
 364         WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl);
 365 }
 366
 367 static void soc15_vga_set_state(struct amdgpu_device *adev, bool state)
 368 {
 369         /* todo */
 370 }
 371
 372 static bool soc15_read_disabled_bios(struct amdgpu_device *adev)
 373 {
 374         /* todo */
 375         return false;
 376 }
 377
 378 static struct soc15_allowed_register_entry soc15_allowed_read_registers[] = {
 379         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
 380         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
 381         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
 382         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
 383         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
 384         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
 385         { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
 386         { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
 387         { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
 388         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
 389         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
 390         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
 391         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
 392         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
 393         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
 394         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)},
 395         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
 396         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
 397         { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
 398         { SOC15_REG_ENTRY(GC, 0, mmDB_DEBUG2)},
 399 };
 400
 401 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
 402                                          u32 sh_num, u32 reg_offset)
 403 {
 404         uint32_t val;
 405
 406         mutex_lock(&adev->grbm_idx_mutex);
 407         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 408                 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
 409
 410         val = RREG32(reg_offset);
 411
 412         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 413                 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
 414         mutex_unlock(&adev->grbm_idx_mutex);
 415         return val;
 416 }
 417
 418 static uint32_t soc15_get_register_value(struct amdgpu_device *adev,
 419                                          bool indexed, u32 se_num,
 420                                          u32 sh_num, u32 reg_offset)
 421 {
 422         if (indexed) {
 423                 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
 424         } else {
 425                 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
 426                         return adev->gfx.config.gb_addr_config;
 427                 else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2))
 428                         return adev->gfx.config.db_debug2;
 429                 return RREG32(reg_offset);
 430         }
 431 }
 432
 433 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
 434                             u32 sh_num, u32 reg_offset, u32 *value)
 435 {
 436         uint32_t i;
 437         struct soc15_allowed_register_entry  *en;
 438
 439         *value = 0;
 440         for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) {
 441                 en = &soc15_allowed_read_registers[i];
 442                 if (!adev->reg_offset[en->hwip][en->inst])
 443                         continue;
 444                 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
 445                                         + en->reg_offset))
 446                         continue;
 447
 448                 *value = soc15_get_register_value(adev,
 449                                                   soc15_allowed_read_registers[i].grbm_indexed,
 450                                                   se_num, sh_num, reg_offset);
 451                 return 0;
 452         }
 453         return -EINVAL;
 454 }
 455
 456
 457 /**
 458  * soc15_program_register_sequence - program an array of registers.
 459  *
 460  * @adev: amdgpu_device pointer
 461  * @regs: pointer to the register array
 462  * @array_size: size of the register array
 463  *
 464  * Programs an array or registers with and and or masks.
 465  * This is a helper for setting golden registers.
 466  */
 467
 468 void soc15_program_register_sequence(struct amdgpu_device *adev,
 469                                              const struct soc15_reg_golden *regs,
 470                                              const u32 array_size)
 471 {
 472         const struct soc15_reg_golden *entry;
 473         u32 tmp, reg;
 474         int i;
 475
 476         for (i = 0; i < array_size; ++i) {
 477                 entry = &regs[i];
 478                 reg =  adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
 479
 480                 if (entry->and_mask == 0xffffffff) {
 481                         tmp = entry->or_mask;
 482                 } else {
 483                         tmp = (entry->hwip == GC_HWIP) ?
 484                                 RREG32_SOC15_IP(GC, reg) : RREG32(reg);
 485
 486                         tmp &= ~(entry->and_mask);
 487                         tmp |= (entry->or_mask & entry->and_mask);
 488                 }
 489
 490                 if (reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3) ||
 491                         reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE) ||
 492                         reg == SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1) ||
 493                         reg == SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG))
 494                         WREG32_RLC(reg, tmp);
 495                 else
 496                         (entry->hwip == GC_HWIP) ?
 497                                 WREG32_SOC15_IP(GC, reg, tmp) : WREG32(reg, tmp);
 498
 499         }
 500
 501 }
 502
 503 static int soc15_asic_baco_reset(struct amdgpu_device *adev)
 504 {
 505         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
 506         int ret = 0;
 507
 508         /* avoid NBIF got stuck when do RAS recovery in BACO reset */
 509         if (ras && adev->ras_enabled)
 510                 adev->nbio.funcs->enable_doorbell_interrupt(adev, false);
 511
 512         ret = amdgpu_dpm_baco_reset(adev);
 513         if (ret)
 514                 return ret;
 515
 516         /* re-enable doorbell interrupt after BACO exit */
 517         if (ras && adev->ras_enabled)
 518                 adev->nbio.funcs->enable_doorbell_interrupt(adev, true);
 519
 520         return 0;
 521 }
 522
 523 static enum amd_reset_method
 524 soc15_asic_reset_method(struct amdgpu_device *adev)
 525 {
 526         bool baco_reset = false;
 527         bool connected_to_cpu = false;
 528         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
 529
 530         if (adev->gmc.xgmi.supported && adev->gmc.xgmi.connected_to_cpu)
 531                 connected_to_cpu = true;
 532
 533         if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 ||
 534             amdgpu_reset_method == AMD_RESET_METHOD_MODE2 ||
 535             amdgpu_reset_method == AMD_RESET_METHOD_BACO ||
 536             amdgpu_reset_method == AMD_RESET_METHOD_PCI) {
 537                 /* If connected to cpu, driver only support mode2 */
 538                 if (connected_to_cpu)
 539                         return AMD_RESET_METHOD_MODE2;
 540                 return amdgpu_reset_method;
 541         }
 542
 543         if (amdgpu_reset_method != -1)
 544                 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
 545                                   amdgpu_reset_method);
 546
 547         switch (adev->ip_versions[MP1_HWIP][0]) {
 548         case IP_VERSION(10, 0, 0):
 549         case IP_VERSION(10, 0, 1):
 550         case IP_VERSION(12, 0, 0):
 551         case IP_VERSION(12, 0, 1):
 552                 return AMD_RESET_METHOD_MODE2;
 553         case IP_VERSION(9, 0, 0):
 554         case IP_VERSION(11, 0, 2):
 555                 if (adev->asic_type == CHIP_VEGA20) {
 556                         if (adev->psp.sos.fw_version >= 0x80067)
 557                                 baco_reset = amdgpu_dpm_is_baco_supported(adev);
 558                         /*
 559                          * 1. PMFW version > 0x284300: all cases use baco
 560                          * 2. PMFW version <= 0x284300: only sGPU w/o RAS use baco
 561                          */
 562                         if (ras && adev->ras_enabled &&
 563                             adev->pm.fw_version <= 0x283400)
 564                                 baco_reset = false;
 565                 } else {
 566                         baco_reset = amdgpu_dpm_is_baco_supported(adev);
 567                 }
 568                 break;
 569         case IP_VERSION(13, 0, 2):
 570                  /*
 571                  * 1.connected to cpu: driver issue mode2 reset
 572                  * 2.discret gpu: driver issue mode1 reset
 573                  */
 574                 if (connected_to_cpu)
 575                         return AMD_RESET_METHOD_MODE2;
 576                 break;
 577         default:
 578                 break;
 579         }
 580
 581         if (baco_reset)
 582                 return AMD_RESET_METHOD_BACO;
 583         else
 584                 return AMD_RESET_METHOD_MODE1;
 585 }
 586
 587 static int soc15_asic_reset(struct amdgpu_device *adev)
 588 {
 589         /* original raven doesn't have full asic reset */
 590         if ((adev->apu_flags & AMD_APU_IS_RAVEN) ||
 591             (adev->apu_flags & AMD_APU_IS_RAVEN2))
 592                 return 0;
 593
 594         switch (soc15_asic_reset_method(adev)) {
 595         case AMD_RESET_METHOD_PCI:
 596                 dev_info(adev->dev, "PCI reset\n");
 597                 return amdgpu_device_pci_reset(adev);
 598         case AMD_RESET_METHOD_BACO:
 599                 dev_info(adev->dev, "BACO reset\n");
 600                 return soc15_asic_baco_reset(adev);
 601         case AMD_RESET_METHOD_MODE2:
 602                 dev_info(adev->dev, "MODE2 reset\n");
 603                 return amdgpu_dpm_mode2_reset(adev);
 604         default:
 605                 dev_info(adev->dev, "MODE1 reset\n");
 606                 return amdgpu_device_mode1_reset(adev);
 607         }
 608 }
 609
 610 static bool soc15_supports_baco(struct amdgpu_device *adev)
 611 {
 612         switch (adev->ip_versions[MP1_HWIP][0]) {
 613         case IP_VERSION(9, 0, 0):
 614         case IP_VERSION(11, 0, 2):
 615                 if (adev->asic_type == CHIP_VEGA20) {
 616                         if (adev->psp.sos.fw_version >= 0x80067)
 617                                 return amdgpu_dpm_is_baco_supported(adev);
 618                         return false;
 619                 } else {
 620                         return amdgpu_dpm_is_baco_supported(adev);
 621                 }
 622                 break;
 623         default:
 624                 return false;
 625         }
 626 }
 627
 628 /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
 629                         u32 cntl_reg, u32 status_reg)
 630 {
 631         return 0;
 632 }*/
 633
 634 static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
 635 {
 636         /*int r;
 637
 638         r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
 639         if (r)
 640                 return r;
 641
 642         r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
 643         */
 644         return 0;
 645 }
 646
 647 static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
 648 {
 649         /* todo */
 650
 651         return 0;
 652 }
 653
 654 static void soc15_pcie_gen3_enable(struct amdgpu_device *adev)
 655 {
 656         if (pci_is_root_bus(adev->pdev->bus))
 657                 return;
 658
 659         if (amdgpu_pcie_gen2 == 0)
 660                 return;
 661
 662         if (adev->flags & AMD_IS_APU)
 663                 return;
 664
 665         if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
 666                                         CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
 667                 return;
 668
 669         /* todo */
 670 }
 671
 672 static void soc15_program_aspm(struct amdgpu_device *adev)
 673 {
 674         if (!amdgpu_device_should_use_aspm(adev))
 675                 return;
 676
 677         if (!(adev->flags & AMD_IS_APU) &&
 678             (adev->nbio.funcs->program_aspm))
 679                 adev->nbio.funcs->program_aspm(adev);
 680 }
 681
 682 static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev,
 683                                            bool enable)
 684 {
 685         adev->nbio.funcs->enable_doorbell_aperture(adev, enable);
 686         adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable);
 687 }
 688
 689 const struct amdgpu_ip_block_version vega10_common_ip_block =
 690 {
 691         .type = AMD_IP_BLOCK_TYPE_COMMON,
 692         .major = 2,
 693         .minor = 0,
 694         .rev = 0,
 695         .funcs = &soc15_common_ip_funcs,
 696 };
 697
 698 static uint32_t soc15_get_rev_id(struct amdgpu_device *adev)
 699 {
 700         return adev->nbio.funcs->get_rev_id(adev);
 701 }
 702
 703 static void soc15_reg_base_init(struct amdgpu_device *adev)
 704 {
 705         /* Set IP register base before any HW register access */
 706         switch (adev->asic_type) {
 707         case CHIP_VEGA10:
 708         case CHIP_VEGA12:
 709         case CHIP_RAVEN:
 710         case CHIP_RENOIR:
 711                 vega10_reg_base_init(adev);
 712                 break;
 713         case CHIP_VEGA20:
 714                 vega20_reg_base_init(adev);
 715                 break;
 716         case CHIP_ARCTURUS:
 717                 arct_reg_base_init(adev);
 718                 break;
 719         case CHIP_ALDEBARAN:
 720                 aldebaran_reg_base_init(adev);
 721                 break;
 722         default:
 723                 DRM_ERROR("Unsupported asic type: %d!\n", adev->asic_type);
 724                 break;
 725         }
 726 }
 727
 728 void soc15_set_virt_ops(struct amdgpu_device *adev)
 729 {
 730         adev->virt.ops = &xgpu_ai_virt_ops;
 731
 732         /* init soc15 reg base early enough so we can
 733          * request request full access for sriov before
 734          * set_ip_blocks. */
 735         soc15_reg_base_init(adev);
 736 }
 737
 738 static bool soc15_need_full_reset(struct amdgpu_device *adev)
 739 {
 740         /* change this when we implement soft reset */
 741         return true;
 742 }
 743
 744 static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
 745                                  uint64_t *count1)
 746 {
 747         uint32_t perfctr = 0;
 748         uint64_t cnt0_of, cnt1_of;
 749         int tmp;
 750
 751         /* This reports 0 on APUs, so return to avoid writing/reading registers
 752          * that may or may not be different from their GPU counterparts
 753          */
 754         if (adev->flags & AMD_IS_APU)
 755                 return;
 756
 757         /* Set the 2 events that we wish to watch, defined above */
 758         /* Reg 40 is # received msgs */
 759         /* Reg 104 is # of posted requests sent */
 760         perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40);
 761         perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104);
 762
 763         /* Write to enable desired perf counters */
 764         WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr);
 765         /* Zero out and enable the perf counters
 766          * Write 0x5:
 767          * Bit 0 = Start all counters(1)
 768          * Bit 2 = Global counter reset enable(1)
 769          */
 770         WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005);
 771
 772         msleep(1000);
 773
 774         /* Load the shadow and disable the perf counters
 775          * Write 0x2:
 776          * Bit 0 = Stop counters(0)
 777          * Bit 1 = Load the shadow counters(1)
 778          */
 779         WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002);
 780
 781         /* Read register values to get any >32bit overflow */
 782         tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK);
 783         cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER);
 784         cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER);
 785
 786         /* Get the values and add the overflow */
 787         *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32);
 788         *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32);
 789 }
 790
 791 static void vega20_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
 792                                  uint64_t *count1)
 793 {
 794         uint32_t perfctr = 0;
 795         uint64_t cnt0_of, cnt1_of;
 796         int tmp;
 797
 798         /* This reports 0 on APUs, so return to avoid writing/reading registers
 799          * that may or may not be different from their GPU counterparts
 800          */
 801         if (adev->flags & AMD_IS_APU)
 802                 return;
 803
 804         /* Set the 2 events that we wish to watch, defined above */
 805         /* Reg 40 is # received msgs */
 806         /* Reg 108 is # of posted requests sent on VG20 */
 807         perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3,
 808                                 EVENT0_SEL, 40);
 809         perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK3,
 810                                 EVENT1_SEL, 108);
 811
 812         /* Write to enable desired perf counters */
 813         WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3, perfctr);
 814         /* Zero out and enable the perf counters
 815          * Write 0x5:
 816          * Bit 0 = Start all counters(1)
 817          * Bit 2 = Global counter reset enable(1)
 818          */
 819         WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005);
 820
 821         msleep(1000);
 822
 823         /* Load the shadow and disable the perf counters
 824          * Write 0x2:
 825          * Bit 0 = Stop counters(0)
 826          * Bit 1 = Load the shadow counters(1)
 827          */
 828         WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002);
 829
 830         /* Read register values to get any >32bit overflow */
 831         tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3);
 832         cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER0_UPPER);
 833         cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK3, COUNTER1_UPPER);
 834
 835         /* Get the values and add the overflow */
 836         *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK3) | (cnt0_of << 32);
 837         *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK3) | (cnt1_of << 32);
 838 }
 839
 840 static bool soc15_need_reset_on_init(struct amdgpu_device *adev)
 841 {
 842         u32 sol_reg;
 843
 844         /* CP hangs in IGT reloading test on RN, reset to WA */
 845         if (adev->asic_type == CHIP_RENOIR)
 846                 return true;
 847
 848         /* Just return false for soc15 GPUs.  Reset does not seem to
 849          * be necessary.
 850          */
 851         if (!amdgpu_passthrough(adev))
 852                 return false;
 853
 854         if (adev->flags & AMD_IS_APU)
 855                 return false;
 856
 857         /* Check sOS sign of life register to confirm sys driver and sOS
 858          * are already been loaded.
 859          */
 860         sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
 861         if (sol_reg)
 862                 return true;
 863
 864         return false;
 865 }
 866
 867 static uint64_t soc15_get_pcie_replay_count(struct amdgpu_device *adev)
 868 {
 869         uint64_t nak_r, nak_g;
 870
 871         /* Get the number of NAKs received and generated */
 872         nak_r = RREG32_PCIE(smnPCIE_RX_NUM_NAK);
 873         nak_g = RREG32_PCIE(smnPCIE_RX_NUM_NAK_GENERATED);
 874
 875         /* Add the total number of NAKs, i.e the number of replays */
 876         return (nak_r + nak_g);
 877 }
 878
 879 static void soc15_pre_asic_init(struct amdgpu_device *adev)
 880 {
 881         gmc_v9_0_restore_registers(adev);
 882 }
 883
 884 static const struct amdgpu_asic_funcs soc15_asic_funcs =
 885 {
 886         .read_disabled_bios = &soc15_read_disabled_bios,
 887         .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom,
 888         .read_register = &soc15_read_register,
 889         .reset = &soc15_asic_reset,
 890         .reset_method = &soc15_asic_reset_method,
 891         .set_vga_state = &soc15_vga_set_state,
 892         .get_xclk = &soc15_get_xclk,
 893         .set_uvd_clocks = &soc15_set_uvd_clocks,
 894         .set_vce_clocks = &soc15_set_vce_clocks,
 895         .get_config_memsize = &soc15_get_config_memsize,
 896         .need_full_reset = &soc15_need_full_reset,
 897         .init_doorbell_index = &vega10_doorbell_index_init,
 898         .get_pcie_usage = &soc15_get_pcie_usage,
 899         .need_reset_on_init = &soc15_need_reset_on_init,
 900         .get_pcie_replay_count = &soc15_get_pcie_replay_count,
 901         .supports_baco = &soc15_supports_baco,
 902         .pre_asic_init = &soc15_pre_asic_init,
 903         .query_video_codecs = &soc15_query_video_codecs,
 904 };
 905
 906 static const struct amdgpu_asic_funcs vega20_asic_funcs =
 907 {
 908         .read_disabled_bios = &soc15_read_disabled_bios,
 909         .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom,
 910         .read_register = &soc15_read_register,
 911         .reset = &soc15_asic_reset,
 912         .reset_method = &soc15_asic_reset_method,
 913         .set_vga_state = &soc15_vga_set_state,
 914         .get_xclk = &soc15_get_xclk,
 915         .set_uvd_clocks = &soc15_set_uvd_clocks,
 916         .set_vce_clocks = &soc15_set_vce_clocks,
 917         .get_config_memsize = &soc15_get_config_memsize,
 918         .need_full_reset = &soc15_need_full_reset,
 919         .init_doorbell_index = &vega20_doorbell_index_init,
 920         .get_pcie_usage = &vega20_get_pcie_usage,
 921         .need_reset_on_init = &soc15_need_reset_on_init,
 922         .get_pcie_replay_count = &soc15_get_pcie_replay_count,
 923         .supports_baco = &soc15_supports_baco,
 924         .pre_asic_init = &soc15_pre_asic_init,
 925         .query_video_codecs = &soc15_query_video_codecs,
 926 };
 927
 928 static int soc15_common_early_init(void *handle)
 929 {
 930 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
 931         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 932
 933         if (!amdgpu_sriov_vf(adev)) {
 934                 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
 935                 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
 936         }
 937         adev->smc_rreg = NULL;
 938         adev->smc_wreg = NULL;
 939         adev->pcie_rreg = &soc15_pcie_rreg;
 940         adev->pcie_wreg = &soc15_pcie_wreg;
 941         adev->pcie_rreg64 = &soc15_pcie_rreg64;
 942         adev->pcie_wreg64 = &soc15_pcie_wreg64;
 943         adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg;
 944         adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg;
 945         adev->didt_rreg = &soc15_didt_rreg;
 946         adev->didt_wreg = &soc15_didt_wreg;
 947         adev->gc_cac_rreg = &soc15_gc_cac_rreg;
 948         adev->gc_cac_wreg = &soc15_gc_cac_wreg;
 949         adev->se_cac_rreg = &soc15_se_cac_rreg;
 950         adev->se_cac_wreg = &soc15_se_cac_wreg;
 951
 952         adev->rev_id = soc15_get_rev_id(adev);
 953         adev->external_rev_id = 0xFF;
 954         /* TODO: split the GC and PG flags based on the relevant IP version for which
 955          * they are relevant.
 956          */
 957         switch (adev->ip_versions[GC_HWIP][0]) {
 958         case IP_VERSION(9, 0, 1):
 959                 adev->asic_funcs = &soc15_asic_funcs;
 960                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 961                         AMD_CG_SUPPORT_GFX_MGLS |
 962                         AMD_CG_SUPPORT_GFX_RLC_LS |
 963                         AMD_CG_SUPPORT_GFX_CP_LS |
 964                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 965                         AMD_CG_SUPPORT_GFX_3D_CGLS |
 966                         AMD_CG_SUPPORT_GFX_CGCG |
 967                         AMD_CG_SUPPORT_GFX_CGLS |
 968                         AMD_CG_SUPPORT_BIF_MGCG |
 969                         AMD_CG_SUPPORT_BIF_LS |
 970                         AMD_CG_SUPPORT_HDP_LS |
 971                         AMD_CG_SUPPORT_DRM_MGCG |
 972                         AMD_CG_SUPPORT_DRM_LS |
 973                         AMD_CG_SUPPORT_ROM_MGCG |
 974                         AMD_CG_SUPPORT_DF_MGCG |
 975                         AMD_CG_SUPPORT_SDMA_MGCG |
 976                         AMD_CG_SUPPORT_SDMA_LS |
 977                         AMD_CG_SUPPORT_MC_MGCG |
 978                         AMD_CG_SUPPORT_MC_LS;
 979                 adev->pg_flags = 0;
 980                 adev->external_rev_id = 0x1;
 981                 break;
 982         case IP_VERSION(9, 2, 1):
 983                 adev->asic_funcs = &soc15_asic_funcs;
 984                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 985                         AMD_CG_SUPPORT_GFX_MGLS |
 986                         AMD_CG_SUPPORT_GFX_CGCG |
 987                         AMD_CG_SUPPORT_GFX_CGLS |
 988                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 989                         AMD_CG_SUPPORT_GFX_3D_CGLS |
 990                         AMD_CG_SUPPORT_GFX_CP_LS |
 991                         AMD_CG_SUPPORT_MC_LS |
 992                         AMD_CG_SUPPORT_MC_MGCG |
 993                         AMD_CG_SUPPORT_SDMA_MGCG |
 994                         AMD_CG_SUPPORT_SDMA_LS |
 995                         AMD_CG_SUPPORT_BIF_MGCG |
 996                         AMD_CG_SUPPORT_BIF_LS |
 997                         AMD_CG_SUPPORT_HDP_MGCG |
 998                         AMD_CG_SUPPORT_HDP_LS |
 999                         AMD_CG_SUPPORT_ROM_MGCG |
1000                         AMD_CG_SUPPORT_VCE_MGCG |
1001                         AMD_CG_SUPPORT_UVD_MGCG;
1002                 adev->pg_flags = 0;
1003                 adev->external_rev_id = adev->rev_id + 0x14;
1004                 break;
1005         case IP_VERSION(9, 4, 0):
1006                 adev->asic_funcs = &vega20_asic_funcs;
1007                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1008                         AMD_CG_SUPPORT_GFX_MGLS |
1009                         AMD_CG_SUPPORT_GFX_CGCG |
1010                         AMD_CG_SUPPORT_GFX_CGLS |
1011                         AMD_CG_SUPPORT_GFX_3D_CGCG |
1012                         AMD_CG_SUPPORT_GFX_3D_CGLS |
1013                         AMD_CG_SUPPORT_GFX_CP_LS |
1014                         AMD_CG_SUPPORT_MC_LS |
1015                         AMD_CG_SUPPORT_MC_MGCG |
1016                         AMD_CG_SUPPORT_SDMA_MGCG |
1017                         AMD_CG_SUPPORT_SDMA_LS |
1018                         AMD_CG_SUPPORT_BIF_MGCG |
1019                         AMD_CG_SUPPORT_BIF_LS |
1020                         AMD_CG_SUPPORT_HDP_MGCG |
1021                         AMD_CG_SUPPORT_HDP_LS |
1022                         AMD_CG_SUPPORT_ROM_MGCG |
1023                         AMD_CG_SUPPORT_VCE_MGCG |
1024                         AMD_CG_SUPPORT_UVD_MGCG;
1025                 adev->pg_flags = 0;
1026                 adev->external_rev_id = adev->rev_id + 0x28;
1027                 break;
1028         case IP_VERSION(9, 1, 0):
1029         case IP_VERSION(9, 2, 2):
1030                 adev->asic_funcs = &soc15_asic_funcs;
1031
1032                 if (adev->rev_id >= 0x8)
1033                         adev->apu_flags |= AMD_APU_IS_RAVEN2;
1034
1035                 if (adev->apu_flags & AMD_APU_IS_RAVEN2)
1036                         adev->external_rev_id = adev->rev_id + 0x79;
1037                 else if (adev->apu_flags & AMD_APU_IS_PICASSO)
1038                         adev->external_rev_id = adev->rev_id + 0x41;
1039                 else if (adev->rev_id == 1)
1040                         adev->external_rev_id = adev->rev_id + 0x20;
1041                 else
1042                         adev->external_rev_id = adev->rev_id + 0x01;
1043
1044                 if (adev->apu_flags & AMD_APU_IS_RAVEN2) {
1045                         adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1046                                 AMD_CG_SUPPORT_GFX_MGLS |
1047                                 AMD_CG_SUPPORT_GFX_CP_LS |
1048                                 AMD_CG_SUPPORT_GFX_3D_CGCG |
1049                                 AMD_CG_SUPPORT_GFX_3D_CGLS |
1050                                 AMD_CG_SUPPORT_GFX_CGCG |
1051                                 AMD_CG_SUPPORT_GFX_CGLS |
1052                                 AMD_CG_SUPPORT_BIF_LS |
1053                                 AMD_CG_SUPPORT_HDP_LS |
1054                                 AMD_CG_SUPPORT_MC_MGCG |
1055                                 AMD_CG_SUPPORT_MC_LS |
1056                                 AMD_CG_SUPPORT_SDMA_MGCG |
1057                                 AMD_CG_SUPPORT_SDMA_LS |
1058                                 AMD_CG_SUPPORT_VCN_MGCG;
1059
1060                         adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
1061                 } else if (adev->apu_flags & AMD_APU_IS_PICASSO) {
1062                         adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1063                                 AMD_CG_SUPPORT_GFX_MGLS |
1064                                 AMD_CG_SUPPORT_GFX_CP_LS |
1065                                 AMD_CG_SUPPORT_GFX_3D_CGLS |
1066                                 AMD_CG_SUPPORT_GFX_CGCG |
1067                                 AMD_CG_SUPPORT_GFX_CGLS |
1068                                 AMD_CG_SUPPORT_BIF_LS |
1069                                 AMD_CG_SUPPORT_HDP_LS |
1070                                 AMD_CG_SUPPORT_MC_MGCG |
1071                                 AMD_CG_SUPPORT_MC_LS |
1072                                 AMD_CG_SUPPORT_SDMA_MGCG |
1073                                 AMD_CG_SUPPORT_SDMA_LS |
1074                                 AMD_CG_SUPPORT_VCN_MGCG;
1075
1076                         /*
1077                          * MMHUB PG needs to be disabled for Picasso for
1078                          * stability reasons.
1079                          */
1080                         adev->pg_flags = AMD_PG_SUPPORT_SDMA |
1081                                 AMD_PG_SUPPORT_VCN;
1082                 } else {
1083                         adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1084                                 AMD_CG_SUPPORT_GFX_MGLS |
1085                                 AMD_CG_SUPPORT_GFX_RLC_LS |
1086                                 AMD_CG_SUPPORT_GFX_CP_LS |
1087                                 AMD_CG_SUPPORT_GFX_3D_CGLS |
1088                                 AMD_CG_SUPPORT_GFX_CGCG |
1089                                 AMD_CG_SUPPORT_GFX_CGLS |
1090                                 AMD_CG_SUPPORT_BIF_MGCG |
1091                                 AMD_CG_SUPPORT_BIF_LS |
1092                                 AMD_CG_SUPPORT_HDP_MGCG |
1093                                 AMD_CG_SUPPORT_HDP_LS |
1094                                 AMD_CG_SUPPORT_DRM_MGCG |
1095                                 AMD_CG_SUPPORT_DRM_LS |
1096                                 AMD_CG_SUPPORT_MC_MGCG |
1097                                 AMD_CG_SUPPORT_MC_LS |
1098                                 AMD_CG_SUPPORT_SDMA_MGCG |
1099                                 AMD_CG_SUPPORT_SDMA_LS |
1100                                 AMD_CG_SUPPORT_VCN_MGCG;
1101
1102                         adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
1103                 }
1104                 break;
1105         case IP_VERSION(9, 4, 1):
1106                 adev->asic_funcs = &vega20_asic_funcs;
1107                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1108                         AMD_CG_SUPPORT_GFX_MGLS |
1109                         AMD_CG_SUPPORT_GFX_CGCG |
1110                         AMD_CG_SUPPORT_GFX_CGLS |
1111                         AMD_CG_SUPPORT_GFX_CP_LS |
1112                         AMD_CG_SUPPORT_HDP_MGCG |
1113                         AMD_CG_SUPPORT_HDP_LS |
1114                         AMD_CG_SUPPORT_SDMA_MGCG |
1115                         AMD_CG_SUPPORT_SDMA_LS |
1116                         AMD_CG_SUPPORT_MC_MGCG |
1117                         AMD_CG_SUPPORT_MC_LS |
1118                         AMD_CG_SUPPORT_IH_CG |
1119                         AMD_CG_SUPPORT_VCN_MGCG |
1120                         AMD_CG_SUPPORT_JPEG_MGCG;
1121                 adev->pg_flags = AMD_PG_SUPPORT_VCN | AMD_PG_SUPPORT_VCN_DPG;
1122                 adev->external_rev_id = adev->rev_id + 0x32;
1123                 break;
1124         case IP_VERSION(9, 3, 0):
1125                 adev->asic_funcs = &soc15_asic_funcs;
1126
1127                 if (adev->apu_flags & AMD_APU_IS_RENOIR)
1128                         adev->external_rev_id = adev->rev_id + 0x91;
1129                 else
1130                         adev->external_rev_id = adev->rev_id + 0xa1;
1131                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1132                                  AMD_CG_SUPPORT_GFX_MGLS |
1133                                  AMD_CG_SUPPORT_GFX_3D_CGCG |
1134                                  AMD_CG_SUPPORT_GFX_3D_CGLS |
1135                                  AMD_CG_SUPPORT_GFX_CGCG |
1136                                  AMD_CG_SUPPORT_GFX_CGLS |
1137                                  AMD_CG_SUPPORT_GFX_CP_LS |
1138                                  AMD_CG_SUPPORT_MC_MGCG |
1139                                  AMD_CG_SUPPORT_MC_LS |
1140                                  AMD_CG_SUPPORT_SDMA_MGCG |
1141                                  AMD_CG_SUPPORT_SDMA_LS |
1142                                  AMD_CG_SUPPORT_BIF_LS |
1143                                  AMD_CG_SUPPORT_HDP_LS |
1144                                  AMD_CG_SUPPORT_VCN_MGCG |
1145                                  AMD_CG_SUPPORT_JPEG_MGCG |
1146                                  AMD_CG_SUPPORT_IH_CG |
1147                                  AMD_CG_SUPPORT_ATHUB_LS |
1148                                  AMD_CG_SUPPORT_ATHUB_MGCG |
1149                                  AMD_CG_SUPPORT_DF_MGCG;
1150                 adev->pg_flags = AMD_PG_SUPPORT_SDMA |
1151                                  AMD_PG_SUPPORT_VCN |
1152                                  AMD_PG_SUPPORT_JPEG |
1153                                  AMD_PG_SUPPORT_VCN_DPG;
1154                 break;
1155         case IP_VERSION(9, 4, 2):
1156                 adev->asic_funcs = &vega20_asic_funcs;
1157                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1158                         AMD_CG_SUPPORT_GFX_MGLS |
1159                         AMD_CG_SUPPORT_GFX_CP_LS |
1160                         AMD_CG_SUPPORT_HDP_LS |
1161                         AMD_CG_SUPPORT_SDMA_MGCG |
1162                         AMD_CG_SUPPORT_SDMA_LS |
1163                         AMD_CG_SUPPORT_IH_CG |
1164                         AMD_CG_SUPPORT_VCN_MGCG | AMD_CG_SUPPORT_JPEG_MGCG;
1165                 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG;
1166                 adev->external_rev_id = adev->rev_id + 0x3c;
1167                 break;
1168         default:
1169                 /* FIXME: not supported yet */
1170                 return -EINVAL;
1171         }
1172
1173         if (amdgpu_sriov_vf(adev)) {
1174                 amdgpu_virt_init_setting(adev);
1175                 xgpu_ai_mailbox_set_irq_funcs(adev);
1176         }
1177
1178         return 0;
1179 }
1180
1181 static int soc15_common_late_init(void *handle)
1182 {
1183         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1184
1185         if (amdgpu_sriov_vf(adev))
1186                 xgpu_ai_mailbox_get_irq(adev);
1187
1188         return 0;
1189 }
1190
1191 static int soc15_common_sw_init(void *handle)
1192 {
1193         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1194
1195         if (amdgpu_sriov_vf(adev))
1196                 xgpu_ai_mailbox_add_irq_id(adev);
1197
1198         if (adev->df.funcs &&
1199             adev->df.funcs->sw_init)
1200                 adev->df.funcs->sw_init(adev);
1201
1202         return 0;
1203 }
1204
1205 static int soc15_common_sw_fini(void *handle)
1206 {
1207         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1208
1209         if (adev->df.funcs &&
1210             adev->df.funcs->sw_fini)
1211                 adev->df.funcs->sw_fini(adev);
1212         return 0;
1213 }
1214
1215 static void soc15_sdma_doorbell_range_init(struct amdgpu_device *adev)
1216 {
1217         int i;
1218
1219         /* sdma doorbell range is programed by hypervisor */
1220         if (!amdgpu_sriov_vf(adev)) {
1221                 for (i = 0; i < adev->sdma.num_instances; i++) {
1222                         adev->nbio.funcs->sdma_doorbell_range(adev, i,
1223                                 true, adev->doorbell_index.sdma_engine[i] << 1,
1224                                 adev->doorbell_index.sdma_doorbell_range);
1225                 }
1226         }
1227 }
1228
1229 static int soc15_common_hw_init(void *handle)
1230 {
1231         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1232
1233         /* enable pcie gen2/3 link */
1234         soc15_pcie_gen3_enable(adev);
1235         /* enable aspm */
1236         soc15_program_aspm(adev);
1237         /* setup nbio registers */
1238         adev->nbio.funcs->init_registers(adev);
1239         /* remap HDP registers to a hole in mmio space,
1240          * for the purpose of expose those registers
1241          * to process space
1242          */
1243         if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev))
1244                 adev->nbio.funcs->remap_hdp_registers(adev);
1245
1246         /* enable the doorbell aperture */
1247         soc15_enable_doorbell_aperture(adev, true);
1248         /* HW doorbell routing policy: doorbell writing not
1249          * in SDMA/IH/MM/ACV range will be routed to CP. So
1250          * we need to init SDMA doorbell range prior
1251          * to CP ip block init and ring test.  IH already
1252          * happens before CP.
1253          */
1254         soc15_sdma_doorbell_range_init(adev);
1255
1256         return 0;
1257 }
1258
1259 static int soc15_common_hw_fini(void *handle)
1260 {
1261         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1262
1263         /* disable the doorbell aperture */
1264         soc15_enable_doorbell_aperture(adev, false);
1265         if (amdgpu_sriov_vf(adev))
1266                 xgpu_ai_mailbox_put_irq(adev);
1267
1268         if (adev->nbio.ras_if &&
1269             amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) {
1270                 if (adev->nbio.ras &&
1271                     adev->nbio.ras->init_ras_controller_interrupt)
1272                         amdgpu_irq_put(adev, &adev->nbio.ras_controller_irq, 0);
1273                 if (adev->nbio.ras &&
1274                     adev->nbio.ras->init_ras_err_event_athub_interrupt)
1275                         amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0);
1276         }
1277
1278         return 0;
1279 }
1280
1281 static int soc15_common_suspend(void *handle)
1282 {
1283         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1284
1285         return soc15_common_hw_fini(adev);
1286 }
1287
1288 static int soc15_common_resume(void *handle)
1289 {
1290         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1291
1292         return soc15_common_hw_init(adev);
1293 }
1294
1295 static bool soc15_common_is_idle(void *handle)
1296 {
1297         return true;
1298 }
1299
1300 static int soc15_common_wait_for_idle(void *handle)
1301 {
1302         return 0;
1303 }
1304
1305 static int soc15_common_soft_reset(void *handle)
1306 {
1307         return 0;
1308 }
1309
1310 static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable)
1311 {
1312         uint32_t def, data;
1313
1314         def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1315
1316         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG))
1317                 data &= ~(0x01000000 |
1318                           0x02000000 |
1319                           0x04000000 |
1320                           0x08000000 |
1321                           0x10000000 |
1322                           0x20000000 |
1323                           0x40000000 |
1324                           0x80000000);
1325         else
1326                 data |= (0x01000000 |
1327                          0x02000000 |
1328                          0x04000000 |
1329                          0x08000000 |
1330                          0x10000000 |
1331                          0x20000000 |
1332                          0x40000000 |
1333                          0x80000000);
1334
1335         if (def != data)
1336                 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data);
1337 }
1338
1339 static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable)
1340 {
1341         uint32_t def, data;
1342
1343         def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1344
1345         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))
1346                 data |= 1;
1347         else
1348                 data &= ~1;
1349
1350         if (def != data)
1351                 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data);
1352 }
1353
1354 static int soc15_common_set_clockgating_state(void *handle,
1355                                             enum amd_clockgating_state state)
1356 {
1357         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1358
1359         if (amdgpu_sriov_vf(adev))
1360                 return 0;
1361
1362         switch (adev->ip_versions[NBIO_HWIP][0]) {
1363         case IP_VERSION(6, 1, 0):
1364         case IP_VERSION(6, 2, 0):
1365         case IP_VERSION(7, 4, 0):
1366                 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1367                                 state == AMD_CG_STATE_GATE);
1368                 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1369                                 state == AMD_CG_STATE_GATE);
1370                 adev->hdp.funcs->update_clock_gating(adev,
1371                                 state == AMD_CG_STATE_GATE);
1372                 soc15_update_drm_clock_gating(adev,
1373                                 state == AMD_CG_STATE_GATE);
1374                 soc15_update_drm_light_sleep(adev,
1375                                 state == AMD_CG_STATE_GATE);
1376                 adev->smuio.funcs->update_rom_clock_gating(adev,
1377                                 state == AMD_CG_STATE_GATE);
1378                 adev->df.funcs->update_medium_grain_clock_gating(adev,
1379                                 state == AMD_CG_STATE_GATE);
1380                 break;
1381         case IP_VERSION(7, 0, 0):
1382         case IP_VERSION(7, 0, 1):
1383         case IP_VERSION(2, 5, 0):
1384                 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1385                                 state == AMD_CG_STATE_GATE);
1386                 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1387                                 state == AMD_CG_STATE_GATE);
1388                 adev->hdp.funcs->update_clock_gating(adev,
1389                                 state == AMD_CG_STATE_GATE);
1390                 soc15_update_drm_clock_gating(adev,
1391                                 state == AMD_CG_STATE_GATE);
1392                 soc15_update_drm_light_sleep(adev,
1393                                 state == AMD_CG_STATE_GATE);
1394                 break;
1395         case IP_VERSION(7, 4, 1):
1396         case IP_VERSION(7, 4, 4):
1397                 adev->hdp.funcs->update_clock_gating(adev,
1398                                 state == AMD_CG_STATE_GATE);
1399                 break;
1400         default:
1401                 break;
1402         }
1403         return 0;
1404 }
1405
1406 static void soc15_common_get_clockgating_state(void *handle, u64 *flags)
1407 {
1408         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1409         int data;
1410
1411         if (amdgpu_sriov_vf(adev))
1412                 *flags = 0;
1413
1414         adev->nbio.funcs->get_clockgating_state(adev, flags);
1415
1416         adev->hdp.funcs->get_clock_gating_state(adev, flags);
1417
1418         if (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 2)) {
1419
1420                 /* AMD_CG_SUPPORT_DRM_MGCG */
1421                 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
1422                 if (!(data & 0x01000000))
1423                         *flags |= AMD_CG_SUPPORT_DRM_MGCG;
1424
1425                 /* AMD_CG_SUPPORT_DRM_LS */
1426                 data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
1427                 if (data & 0x1)
1428                         *flags |= AMD_CG_SUPPORT_DRM_LS;
1429         }
1430
1431         /* AMD_CG_SUPPORT_ROM_MGCG */
1432         adev->smuio.funcs->get_clock_gating_state(adev, flags);
1433
1434         adev->df.funcs->get_clockgating_state(adev, flags);
1435 }
1436
1437 static int soc15_common_set_powergating_state(void *handle,
1438                                             enum amd_powergating_state state)
1439 {
1440         /* todo */
1441         return 0;
1442 }
1443
1444 static const struct amd_ip_funcs soc15_common_ip_funcs = {
1445         .name = "soc15_common",
1446         .early_init = soc15_common_early_init,
1447         .late_init = soc15_common_late_init,
1448         .sw_init = soc15_common_sw_init,
1449         .sw_fini = soc15_common_sw_fini,
1450         .hw_init = soc15_common_hw_init,
1451         .hw_fini = soc15_common_hw_fini,
1452         .suspend = soc15_common_suspend,
1453         .resume = soc15_common_resume,
1454         .is_idle = soc15_common_is_idle,
1455         .wait_for_idle = soc15_common_wait_for_idle,
1456         .soft_reset = soc15_common_soft_reset,
1457         .set_clockgating_state = soc15_common_set_clockgating_state,
1458         .set_powergating_state = soc15_common_set_powergating_state,
1459         .get_clockgating_state= soc15_common_get_clockgating_state,
1460 };