drivers/gpu/drm/amd/amdgpu/soc15.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <linux/slab.h>
  25 #include <linux/module.h>
  26 #include "drmP.h"
  27 #include "amdgpu.h"
  28 #include "amdgpu_atombios.h"
  29 #include "amdgpu_ih.h"
  30 #include "amdgpu_uvd.h"
  31 #include "amdgpu_vce.h"
  32 #include "amdgpu_ucode.h"
  33 #include "amdgpu_psp.h"
  34 #include "atom.h"
  35 #include "amd_pcie.h"
  36
  37 #include "vega10/soc15ip.h"
  38 #include "vega10/UVD/uvd_7_0_offset.h"
  39 #include "vega10/GC/gc_9_0_offset.h"
  40 #include "vega10/GC/gc_9_0_sh_mask.h"
  41 #include "vega10/SDMA0/sdma0_4_0_offset.h"
  42 #include "vega10/SDMA1/sdma1_4_0_offset.h"
  43 #include "vega10/HDP/hdp_4_0_offset.h"
  44 #include "vega10/HDP/hdp_4_0_sh_mask.h"
  45 #include "vega10/MP/mp_9_0_offset.h"
  46 #include "vega10/MP/mp_9_0_sh_mask.h"
  47 #include "vega10/SMUIO/smuio_9_0_offset.h"
  48 #include "vega10/SMUIO/smuio_9_0_sh_mask.h"
  49
  50 #include "soc15.h"
  51 #include "soc15_common.h"
  52 #include "gfx_v9_0.h"
  53 #include "gmc_v9_0.h"
  54 #include "gfxhub_v1_0.h"
  55 #include "mmhub_v1_0.h"
  56 #include "vega10_ih.h"
  57 #include "sdma_v4_0.h"
  58 #include "uvd_v7_0.h"
  59 #include "vce_v4_0.h"
  60 #include "amdgpu_powerplay.h"
  61 #include "dce_virtual.h"
  62 #include "mxgpu_ai.h"
  63
  64 MODULE_FIRMWARE("amdgpu/vega10_smc.bin");
  65
  66 #define mmFabricConfigAccessControl                                                                    0x0410
  67 #define mmFabricConfigAccessControl_BASE_IDX                                                           0
  68 #define mmFabricConfigAccessControl_DEFAULT                                      0x00000000
  69 //FabricConfigAccessControl
  70 #define FabricConfigAccessControl__CfgRegInstAccEn__SHIFT                                                     0x0
  71 #define FabricConfigAccessControl__CfgRegInstAccRegLock__SHIFT                                                0x1
  72 #define FabricConfigAccessControl__CfgRegInstID__SHIFT                                                        0x10
  73 #define FabricConfigAccessControl__CfgRegInstAccEn_MASK                                                       0x00000001L
  74 #define FabricConfigAccessControl__CfgRegInstAccRegLock_MASK                                                  0x00000002L
  75 #define FabricConfigAccessControl__CfgRegInstID_MASK                                                          0x00FF0000L
  76
  77
  78 #define mmDF_PIE_AON0_DfGlobalClkGater                                                                 0x00fc
  79 #define mmDF_PIE_AON0_DfGlobalClkGater_BASE_IDX                                                        0
  80 //DF_PIE_AON0_DfGlobalClkGater
  81 #define DF_PIE_AON0_DfGlobalClkGater__MGCGMode__SHIFT                                                         0x0
  82 #define DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK                                                           0x0000000FL
  83
  84 enum {
  85         DF_MGCG_DISABLE = 0,
  86         DF_MGCG_ENABLE_00_CYCLE_DELAY =1,
  87         DF_MGCG_ENABLE_01_CYCLE_DELAY =2,
  88         DF_MGCG_ENABLE_15_CYCLE_DELAY =13,
  89         DF_MGCG_ENABLE_31_CYCLE_DELAY =14,
  90         DF_MGCG_ENABLE_63_CYCLE_DELAY =15
  91 };
  92
  93 #define mmMP0_MISC_CGTT_CTRL0                                                                   0x01b9
  94 #define mmMP0_MISC_CGTT_CTRL0_BASE_IDX                                                          0
  95 #define mmMP0_MISC_LIGHT_SLEEP_CTRL                                                             0x01ba
  96 #define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX                                                    0
  97
  98 /*
  99  * Indirect registers accessor
 100  */
 101 static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg)
 102 {
 103         unsigned long flags, address, data;
 104         u32 r;
 105         struct nbio_pcie_index_data *nbio_pcie_id;
 106
 107         if (adev->asic_type == CHIP_VEGA10)
 108                 nbio_pcie_id = &nbio_v6_1_pcie_index_data;
 109
 110         address = nbio_pcie_id->index_offset;
 111         data = nbio_pcie_id->data_offset;
 112
 113         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 114         WREG32(address, reg);
 115         (void)RREG32(address);
 116         r = RREG32(data);
 117         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 118         return r;
 119 }
 120
 121 static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 122 {
 123         unsigned long flags, address, data;
 124         struct nbio_pcie_index_data *nbio_pcie_id;
 125
 126         if (adev->asic_type == CHIP_VEGA10)
 127                 nbio_pcie_id = &nbio_v6_1_pcie_index_data;
 128
 129         address = nbio_pcie_id->index_offset;
 130         data = nbio_pcie_id->data_offset;
 131
 132         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 133         WREG32(address, reg);
 134         (void)RREG32(address);
 135         WREG32(data, v);
 136         (void)RREG32(data);
 137         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 138 }
 139
 140 static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
 141 {
 142         unsigned long flags, address, data;
 143         u32 r;
 144
 145         address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
 146         data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
 147
 148         spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
 149         WREG32(address, ((reg) & 0x1ff));
 150         r = RREG32(data);
 151         spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
 152         return r;
 153 }
 154
 155 static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 156 {
 157         unsigned long flags, address, data;
 158
 159         address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
 160         data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
 161
 162         spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
 163         WREG32(address, ((reg) & 0x1ff));
 164         WREG32(data, (v));
 165         spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
 166 }
 167
 168 static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg)
 169 {
 170         unsigned long flags, address, data;
 171         u32 r;
 172
 173         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 174         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 175
 176         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 177         WREG32(address, (reg));
 178         r = RREG32(data);
 179         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 180         return r;
 181 }
 182
 183 static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 184 {
 185         unsigned long flags, address, data;
 186
 187         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 188         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 189
 190         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 191         WREG32(address, (reg));
 192         WREG32(data, (v));
 193         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 194 }
 195
 196 static u32 soc15_get_config_memsize(struct amdgpu_device *adev)
 197 {
 198         return nbio_v6_1_get_memsize(adev);
 199 }
 200
 201 static const u32 vega10_golden_init[] =
 202 {
 203 };
 204
 205 static void soc15_init_golden_registers(struct amdgpu_device *adev)
 206 {
 207         /* Some of the registers might be dependent on GRBM_GFX_INDEX */
 208         mutex_lock(&adev->grbm_idx_mutex);
 209
 210         switch (adev->asic_type) {
 211         case CHIP_VEGA10:
 212                 amdgpu_program_register_sequence(adev,
 213                                                  vega10_golden_init,
 214                                                  (const u32)ARRAY_SIZE(vega10_golden_init));
 215                 break;
 216         default:
 217                 break;
 218         }
 219         mutex_unlock(&adev->grbm_idx_mutex);
 220 }
 221 static u32 soc15_get_xclk(struct amdgpu_device *adev)
 222 {
 223         if (adev->asic_type == CHIP_VEGA10)
 224                 return adev->clock.spll.reference_freq/4;
 225         else
 226                 return adev->clock.spll.reference_freq;
 227 }
 228
 229
 230 void soc15_grbm_select(struct amdgpu_device *adev,
 231                      u32 me, u32 pipe, u32 queue, u32 vmid)
 232 {
 233         u32 grbm_gfx_cntl = 0;
 234         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
 235         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
 236         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
 237         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
 238
 239         WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl);
 240 }
 241
 242 static void soc15_vga_set_state(struct amdgpu_device *adev, bool state)
 243 {
 244         /* todo */
 245 }
 246
 247 static bool soc15_read_disabled_bios(struct amdgpu_device *adev)
 248 {
 249         /* todo */
 250         return false;
 251 }
 252
 253 static bool soc15_read_bios_from_rom(struct amdgpu_device *adev,
 254                                      u8 *bios, u32 length_bytes)
 255 {
 256         u32 *dw_ptr;
 257         u32 i, length_dw;
 258
 259         if (bios == NULL)
 260                 return false;
 261         if (length_bytes == 0)
 262                 return false;
 263         /* APU vbios image is part of sbios image */
 264         if (adev->flags & AMD_IS_APU)
 265                 return false;
 266
 267         dw_ptr = (u32 *)bios;
 268         length_dw = ALIGN(length_bytes, 4) / 4;
 269
 270         /* set rom index to 0 */
 271         WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0);
 272         /* read out the rom data */
 273         for (i = 0; i < length_dw; i++)
 274                 dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA));
 275
 276         return true;
 277 }
 278
 279 static struct amdgpu_allowed_register_entry vega10_allowed_read_registers[] = {
 280         /* todo */
 281 };
 282
 283 static struct amdgpu_allowed_register_entry soc15_allowed_read_registers[] = {
 284         { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS), false},
 285         { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS2), false},
 286         { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE0), false},
 287         { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE1), false},
 288         { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE2), false},
 289         { SOC15_REG_OFFSET(GC, 0, mmGRBM_STATUS_SE3), false},
 290         { SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_STATUS_REG), false},
 291         { SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_STATUS_REG), false},
 292         { SOC15_REG_OFFSET(GC, 0, mmCP_STAT), false},
 293         { SOC15_REG_OFFSET(GC, 0, mmCP_STALLED_STAT1), false},
 294         { SOC15_REG_OFFSET(GC, 0, mmCP_STALLED_STAT2), false},
 295         { SOC15_REG_OFFSET(GC, 0, mmCP_STALLED_STAT3), false},
 296         { SOC15_REG_OFFSET(GC, 0, mmCP_CPF_BUSY_STAT), false},
 297         { SOC15_REG_OFFSET(GC, 0, mmCP_CPF_STALLED_STAT1), false},
 298         { SOC15_REG_OFFSET(GC, 0, mmCP_CPF_STATUS), false},
 299         { SOC15_REG_OFFSET(GC, 0, mmCP_CPC_STALLED_STAT1), false},
 300         { SOC15_REG_OFFSET(GC, 0, mmCP_CPC_STATUS), false},
 301         { SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG), false},
 302 };
 303
 304 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
 305                                          u32 sh_num, u32 reg_offset)
 306 {
 307         uint32_t val;
 308
 309         mutex_lock(&adev->grbm_idx_mutex);
 310         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 311                 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
 312
 313         val = RREG32(reg_offset);
 314
 315         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 316                 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
 317         mutex_unlock(&adev->grbm_idx_mutex);
 318         return val;
 319 }
 320
 321 static uint32_t soc15_get_register_value(struct amdgpu_device *adev,
 322                                          bool indexed, u32 se_num,
 323                                          u32 sh_num, u32 reg_offset)
 324 {
 325         if (indexed) {
 326                 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
 327         } else {
 328                 switch (reg_offset) {
 329                 case SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG):
 330                         return adev->gfx.config.gb_addr_config;
 331                 default:
 332                         return RREG32(reg_offset);
 333                 }
 334         }
 335 }
 336
 337 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
 338                             u32 sh_num, u32 reg_offset, u32 *value)
 339 {
 340         struct amdgpu_allowed_register_entry *asic_register_table = NULL;
 341         struct amdgpu_allowed_register_entry *asic_register_entry;
 342         uint32_t size, i;
 343
 344         *value = 0;
 345         switch (adev->asic_type) {
 346         case CHIP_VEGA10:
 347                 asic_register_table = vega10_allowed_read_registers;
 348                 size = ARRAY_SIZE(vega10_allowed_read_registers);
 349                 break;
 350         default:
 351                 return -EINVAL;
 352         }
 353
 354         if (asic_register_table) {
 355                 for (i = 0; i < size; i++) {
 356                         asic_register_entry = asic_register_table + i;
 357                         if (reg_offset != asic_register_entry->reg_offset)
 358                                 continue;
 359                         if (!asic_register_entry->untouched)
 360                                 *value = soc15_get_register_value(adev,
 361                                                                   asic_register_entry->grbm_indexed,
 362                                                                   se_num, sh_num, reg_offset);
 363                         return 0;
 364                 }
 365         }
 366
 367         for (i = 0; i < ARRAY_SIZE(soc15_allowed_read_registers); i++) {
 368                 if (reg_offset != soc15_allowed_read_registers[i].reg_offset)
 369                         continue;
 370
 371                 if (!soc15_allowed_read_registers[i].untouched)
 372                         *value = soc15_get_register_value(adev,
 373                                                           soc15_allowed_read_registers[i].grbm_indexed,
 374                                                           se_num, sh_num, reg_offset);
 375                 return 0;
 376         }
 377         return -EINVAL;
 378 }
 379
 380 static void soc15_gpu_pci_config_reset(struct amdgpu_device *adev)
 381 {
 382         u32 i;
 383
 384         dev_info(adev->dev, "GPU pci config reset\n");
 385
 386         /* disable BM */
 387         pci_clear_master(adev->pdev);
 388         /* reset */
 389         amdgpu_pci_config_reset(adev);
 390
 391         udelay(100);
 392
 393         /* wait for asic to come out of reset */
 394         for (i = 0; i < adev->usec_timeout; i++) {
 395                 if (nbio_v6_1_get_memsize(adev) != 0xffffffff)
 396                         break;
 397                 udelay(1);
 398         }
 399
 400 }
 401
 402 static int soc15_asic_reset(struct amdgpu_device *adev)
 403 {
 404         amdgpu_atombios_scratch_regs_engine_hung(adev, true);
 405
 406         soc15_gpu_pci_config_reset(adev);
 407
 408         amdgpu_atombios_scratch_regs_engine_hung(adev, false);
 409
 410         return 0;
 411 }
 412
 413 /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
 414                         u32 cntl_reg, u32 status_reg)
 415 {
 416         return 0;
 417 }*/
 418
 419 static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
 420 {
 421         /*int r;
 422
 423         r = soc15_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
 424         if (r)
 425                 return r;
 426
 427         r = soc15_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
 428         */
 429         return 0;
 430 }
 431
 432 static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
 433 {
 434         /* todo */
 435
 436         return 0;
 437 }
 438
 439 static void soc15_pcie_gen3_enable(struct amdgpu_device *adev)
 440 {
 441         if (pci_is_root_bus(adev->pdev->bus))
 442                 return;
 443
 444         if (amdgpu_pcie_gen2 == 0)
 445                 return;
 446
 447         if (adev->flags & AMD_IS_APU)
 448                 return;
 449
 450         if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
 451                                         CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
 452                 return;
 453
 454         /* todo */
 455 }
 456
 457 static void soc15_program_aspm(struct amdgpu_device *adev)
 458 {
 459
 460         if (amdgpu_aspm == 0)
 461                 return;
 462
 463         /* todo */
 464 }
 465
 466 static void soc15_enable_doorbell_aperture(struct amdgpu_device *adev,
 467                                         bool enable)
 468 {
 469         nbio_v6_1_enable_doorbell_aperture(adev, enable);
 470         nbio_v6_1_enable_doorbell_selfring_aperture(adev, enable);
 471 }
 472
 473 static const struct amdgpu_ip_block_version vega10_common_ip_block =
 474 {
 475         .type = AMD_IP_BLOCK_TYPE_COMMON,
 476         .major = 2,
 477         .minor = 0,
 478         .rev = 0,
 479         .funcs = &soc15_common_ip_funcs,
 480 };
 481
 482 int soc15_set_ip_blocks(struct amdgpu_device *adev)
 483 {
 484         nbio_v6_1_detect_hw_virt(adev);
 485
 486         if (amdgpu_sriov_vf(adev))
 487                 adev->virt.ops = &xgpu_ai_virt_ops;
 488
 489         switch (adev->asic_type) {
 490         case CHIP_VEGA10:
 491                 amdgpu_ip_block_add(adev, &vega10_common_ip_block);
 492                 amdgpu_ip_block_add(adev, &gfxhub_v1_0_ip_block);
 493                 amdgpu_ip_block_add(adev, &mmhub_v1_0_ip_block);
 494                 amdgpu_ip_block_add(adev, &gmc_v9_0_ip_block);
 495                 amdgpu_ip_block_add(adev, &vega10_ih_ip_block);
 496                 amdgpu_ip_block_add(adev, &psp_v3_1_ip_block);
 497                 if (!amdgpu_sriov_vf(adev))
 498                         amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
 499                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 500                         amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
 501                 amdgpu_ip_block_add(adev, &gfx_v9_0_ip_block);
 502                 amdgpu_ip_block_add(adev, &sdma_v4_0_ip_block);
 503                 if (!amdgpu_sriov_vf(adev))
 504                         amdgpu_ip_block_add(adev, &uvd_v7_0_ip_block);
 505                 amdgpu_ip_block_add(adev, &vce_v4_0_ip_block);
 506                 break;
 507         default:
 508                 return -EINVAL;
 509         }
 510
 511         return 0;
 512 }
 513
 514 static uint32_t soc15_get_rev_id(struct amdgpu_device *adev)
 515 {
 516         return nbio_v6_1_get_rev_id(adev);
 517 }
 518
 519
 520 int gmc_v9_0_mc_wait_for_idle(struct amdgpu_device *adev)
 521 {
 522         /* to be implemented in MC IP*/
 523         return 0;
 524 }
 525
 526 static const struct amdgpu_asic_funcs soc15_asic_funcs =
 527 {
 528         .read_disabled_bios = &soc15_read_disabled_bios,
 529         .read_bios_from_rom = &soc15_read_bios_from_rom,
 530         .read_register = &soc15_read_register,
 531         .reset = &soc15_asic_reset,
 532         .set_vga_state = &soc15_vga_set_state,
 533         .get_xclk = &soc15_get_xclk,
 534         .set_uvd_clocks = &soc15_set_uvd_clocks,
 535         .set_vce_clocks = &soc15_set_vce_clocks,
 536         .get_config_memsize = &soc15_get_config_memsize,
 537 };
 538
 539 static int soc15_common_early_init(void *handle)
 540 {
 541         bool psp_enabled = false;
 542         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 543
 544         adev->smc_rreg = NULL;
 545         adev->smc_wreg = NULL;
 546         adev->pcie_rreg = &soc15_pcie_rreg;
 547         adev->pcie_wreg = &soc15_pcie_wreg;
 548         adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg;
 549         adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg;
 550         adev->didt_rreg = &soc15_didt_rreg;
 551         adev->didt_wreg = &soc15_didt_wreg;
 552
 553         adev->asic_funcs = &soc15_asic_funcs;
 554
 555         if (amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP) &&
 556                 (amdgpu_ip_block_mask & (1 << AMD_IP_BLOCK_TYPE_PSP)))
 557                 psp_enabled = true;
 558
 559         if (amdgpu_sriov_vf(adev)) {
 560                 amdgpu_virt_init_setting(adev);
 561         }
 562
 563         /*
 564          * nbio need be used for both sdma and gfx9, but only
 565          * initializes once
 566          */
 567         switch(adev->asic_type) {
 568         case CHIP_VEGA10:
 569                 nbio_v6_1_init(adev);
 570                 break;
 571         default:
 572                 return -EINVAL;
 573         }
 574
 575         adev->rev_id = soc15_get_rev_id(adev);
 576         adev->external_rev_id = 0xFF;
 577         switch (adev->asic_type) {
 578         case CHIP_VEGA10:
 579                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 580                         AMD_CG_SUPPORT_GFX_MGLS |
 581                         AMD_CG_SUPPORT_GFX_RLC_LS |
 582                         AMD_CG_SUPPORT_GFX_CP_LS |
 583                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 584                         AMD_CG_SUPPORT_GFX_3D_CGLS |
 585                         AMD_CG_SUPPORT_GFX_CGCG |
 586                         AMD_CG_SUPPORT_GFX_CGLS |
 587                         AMD_CG_SUPPORT_BIF_MGCG |
 588                         AMD_CG_SUPPORT_BIF_LS |
 589                         AMD_CG_SUPPORT_HDP_LS |
 590                         AMD_CG_SUPPORT_DRM_MGCG |
 591                         AMD_CG_SUPPORT_DRM_LS |
 592                         AMD_CG_SUPPORT_ROM_MGCG |
 593                         AMD_CG_SUPPORT_DF_MGCG |
 594                         AMD_CG_SUPPORT_SDMA_MGCG |
 595                         AMD_CG_SUPPORT_SDMA_LS |
 596                         AMD_CG_SUPPORT_MC_MGCG |
 597                         AMD_CG_SUPPORT_MC_LS;
 598                 adev->pg_flags = 0;
 599                 adev->external_rev_id = 0x1;
 600                 break;
 601         default:
 602                 /* FIXME: not supported yet */
 603                 return -EINVAL;
 604         }
 605
 606         adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type);
 607
 608         amdgpu_get_pcie_info(adev);
 609
 610         return 0;
 611 }
 612
 613 static int soc15_common_sw_init(void *handle)
 614 {
 615         return 0;
 616 }
 617
 618 static int soc15_common_sw_fini(void *handle)
 619 {
 620         return 0;
 621 }
 622
 623 static int soc15_common_hw_init(void *handle)
 624 {
 625         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 626
 627         /* move the golden regs per IP block */
 628         soc15_init_golden_registers(adev);
 629         /* enable pcie gen2/3 link */
 630         soc15_pcie_gen3_enable(adev);
 631         /* enable aspm */
 632         soc15_program_aspm(adev);
 633         /* enable the doorbell aperture */
 634         soc15_enable_doorbell_aperture(adev, true);
 635
 636         return 0;
 637 }
 638
 639 static int soc15_common_hw_fini(void *handle)
 640 {
 641         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 642
 643         /* disable the doorbell aperture */
 644         soc15_enable_doorbell_aperture(adev, false);
 645
 646         return 0;
 647 }
 648
 649 static int soc15_common_suspend(void *handle)
 650 {
 651         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 652
 653         return soc15_common_hw_fini(adev);
 654 }
 655
 656 static int soc15_common_resume(void *handle)
 657 {
 658         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 659
 660         return soc15_common_hw_init(adev);
 661 }
 662
 663 static bool soc15_common_is_idle(void *handle)
 664 {
 665         return true;
 666 }
 667
 668 static int soc15_common_wait_for_idle(void *handle)
 669 {
 670         return 0;
 671 }
 672
 673 static int soc15_common_soft_reset(void *handle)
 674 {
 675         return 0;
 676 }
 677
 678 static void soc15_update_hdp_light_sleep(struct amdgpu_device *adev, bool enable)
 679 {
 680         uint32_t def, data;
 681
 682         def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
 683
 684         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
 685                 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
 686         else
 687                 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
 688
 689         if (def != data)
 690                 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data);
 691 }
 692
 693 static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable)
 694 {
 695         uint32_t def, data;
 696
 697         def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
 698
 699         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG))
 700                 data &= ~(0x01000000 |
 701                           0x02000000 |
 702                           0x04000000 |
 703                           0x08000000 |
 704                           0x10000000 |
 705                           0x20000000 |
 706                           0x40000000 |
 707                           0x80000000);
 708         else
 709                 data |= (0x01000000 |
 710                          0x02000000 |
 711                          0x04000000 |
 712                          0x08000000 |
 713                          0x10000000 |
 714                          0x20000000 |
 715                          0x40000000 |
 716                          0x80000000);
 717
 718         if (def != data)
 719                 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data);
 720 }
 721
 722 static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable)
 723 {
 724         uint32_t def, data;
 725
 726         def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
 727
 728         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))
 729                 data |= 1;
 730         else
 731                 data &= ~1;
 732
 733         if (def != data)
 734                 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data);
 735 }
 736
 737 static void soc15_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,
 738                                                        bool enable)
 739 {
 740         uint32_t def, data;
 741
 742         def = data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
 743
 744         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))
 745                 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
 746                         CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK);
 747         else
 748                 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
 749                         CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK;
 750
 751         if (def != data)
 752                 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0), data);
 753 }
 754
 755 static void soc15_update_df_medium_grain_clock_gating(struct amdgpu_device *adev,
 756                                                        bool enable)
 757 {
 758         uint32_t data;
 759
 760         /* Put DF on broadcast mode */
 761         data = RREG32(SOC15_REG_OFFSET(DF, 0, mmFabricConfigAccessControl));
 762         data &= ~FabricConfigAccessControl__CfgRegInstAccEn_MASK;
 763         WREG32(SOC15_REG_OFFSET(DF, 0, mmFabricConfigAccessControl), data);
 764
 765         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DF_MGCG)) {
 766                 data = RREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater));
 767                 data &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
 768                 data |= DF_MGCG_ENABLE_15_CYCLE_DELAY;
 769                 WREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater), data);
 770         } else {
 771                 data = RREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater));
 772                 data &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
 773                 data |= DF_MGCG_DISABLE;
 774                 WREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater), data);
 775         }
 776
 777         WREG32(SOC15_REG_OFFSET(DF, 0, mmFabricConfigAccessControl),
 778                mmFabricConfigAccessControl_DEFAULT);
 779 }
 780
 781 static int soc15_common_set_clockgating_state(void *handle,
 782                                             enum amd_clockgating_state state)
 783 {
 784         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 785
 786         if (amdgpu_sriov_vf(adev))
 787                 return 0;
 788
 789         switch (adev->asic_type) {
 790         case CHIP_VEGA10:
 791                 nbio_v6_1_update_medium_grain_clock_gating(adev,
 792                                 state == AMD_CG_STATE_GATE ? true : false);
 793                 nbio_v6_1_update_medium_grain_light_sleep(adev,
 794                                 state == AMD_CG_STATE_GATE ? true : false);
 795                 soc15_update_hdp_light_sleep(adev,
 796                                 state == AMD_CG_STATE_GATE ? true : false);
 797                 soc15_update_drm_clock_gating(adev,
 798                                 state == AMD_CG_STATE_GATE ? true : false);
 799                 soc15_update_drm_light_sleep(adev,
 800                                 state == AMD_CG_STATE_GATE ? true : false);
 801                 soc15_update_rom_medium_grain_clock_gating(adev,
 802                                 state == AMD_CG_STATE_GATE ? true : false);
 803                 soc15_update_df_medium_grain_clock_gating(adev,
 804                                 state == AMD_CG_STATE_GATE ? true : false);
 805                 break;
 806         default:
 807                 break;
 808         }
 809         return 0;
 810 }
 811
 812 static void soc15_common_get_clockgating_state(void *handle, u32 *flags)
 813 {
 814         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 815         int data;
 816
 817         if (amdgpu_sriov_vf(adev))
 818                 *flags = 0;
 819
 820         nbio_v6_1_get_clockgating_state(adev, flags);
 821
 822         /* AMD_CG_SUPPORT_HDP_LS */
 823         data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
 824         if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK)
 825                 *flags |= AMD_CG_SUPPORT_HDP_LS;
 826
 827         /* AMD_CG_SUPPORT_DRM_MGCG */
 828         data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
 829         if (!(data & 0x01000000))
 830                 *flags |= AMD_CG_SUPPORT_DRM_MGCG;
 831
 832         /* AMD_CG_SUPPORT_DRM_LS */
 833         data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
 834         if (data & 0x1)
 835                 *flags |= AMD_CG_SUPPORT_DRM_LS;
 836
 837         /* AMD_CG_SUPPORT_ROM_MGCG */
 838         data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
 839         if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))
 840                 *flags |= AMD_CG_SUPPORT_ROM_MGCG;
 841
 842         /* AMD_CG_SUPPORT_DF_MGCG */
 843         data = RREG32(SOC15_REG_OFFSET(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater));
 844         if (data & DF_MGCG_ENABLE_15_CYCLE_DELAY)
 845                 *flags |= AMD_CG_SUPPORT_DF_MGCG;
 846 }
 847
 848 static int soc15_common_set_powergating_state(void *handle,
 849                                             enum amd_powergating_state state)
 850 {
 851         /* todo */
 852         return 0;
 853 }
 854
 855 const struct amd_ip_funcs soc15_common_ip_funcs = {
 856         .name = "soc15_common",
 857         .early_init = soc15_common_early_init,
 858         .late_init = NULL,
 859         .sw_init = soc15_common_sw_init,
 860         .sw_fini = soc15_common_sw_fini,
 861         .hw_init = soc15_common_hw_init,
 862         .hw_fini = soc15_common_hw_fini,
 863         .suspend = soc15_common_suspend,
 864         .resume = soc15_common_resume,
 865         .is_idle = soc15_common_is_idle,
 866         .wait_for_idle = soc15_common_wait_for_idle,
 867         .soft_reset = soc15_common_soft_reset,
 868         .set_clockgating_state = soc15_common_set_clockgating_state,
 869         .set_powergating_state = soc15_common_set_powergating_state,
 870         .get_clockgating_state= soc15_common_get_clockgating_state,
 871 };