2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include "amdgpu_ih.h"
29 static void si_ih_set_interrupt_funcs(struct amdgpu_device *adev);
31 static void si_ih_enable_interrupts(struct amdgpu_device *adev)
33 u32 ih_cntl = RREG32(IH_CNTL);
34 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
36 ih_cntl |= ENABLE_INTR;
37 ih_rb_cntl |= IH_RB_ENABLE;
38 WREG32(IH_CNTL, ih_cntl);
39 WREG32(IH_RB_CNTL, ih_rb_cntl);
40 adev->irq.ih.enabled = true;
43 static void si_ih_disable_interrupts(struct amdgpu_device *adev)
45 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
46 u32 ih_cntl = RREG32(IH_CNTL);
48 ih_rb_cntl &= ~IH_RB_ENABLE;
49 ih_cntl &= ~ENABLE_INTR;
50 WREG32(IH_RB_CNTL, ih_rb_cntl);
51 WREG32(IH_CNTL, ih_cntl);
52 WREG32(IH_RB_RPTR, 0);
53 WREG32(IH_RB_WPTR, 0);
54 adev->irq.ih.enabled = false;
55 adev->irq.ih.rptr = 0;
58 static int si_ih_irq_init(struct amdgpu_device *adev)
61 u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
64 si_ih_disable_interrupts(adev);
65 WREG32(INTERRUPT_CNTL2, adev->irq.ih.gpu_addr >> 8);
66 interrupt_cntl = RREG32(INTERRUPT_CNTL);
67 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
68 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
69 WREG32(INTERRUPT_CNTL, interrupt_cntl);
71 WREG32(IH_RB_BASE, adev->irq.ih.gpu_addr >> 8);
72 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4);
74 ih_rb_cntl = IH_WPTR_OVERFLOW_ENABLE |
75 IH_WPTR_OVERFLOW_CLEAR |
77 IH_WPTR_WRITEBACK_ENABLE;
79 wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4);
80 WREG32(IH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off));
81 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF);
82 WREG32(IH_RB_CNTL, ih_rb_cntl);
83 WREG32(IH_RB_RPTR, 0);
84 WREG32(IH_RB_WPTR, 0);
86 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10) | MC_VMID(0);
87 if (adev->irq.msi_enabled)
88 ih_cntl |= RPTR_REARM;
89 WREG32(IH_CNTL, ih_cntl);
91 pci_set_master(adev->pdev);
92 si_ih_enable_interrupts(adev);
97 static void si_ih_irq_disable(struct amdgpu_device *adev)
99 si_ih_disable_interrupts(adev);
103 static u32 si_ih_get_wptr(struct amdgpu_device *adev)
107 wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]);
109 if (wptr & IH_RB_WPTR__RB_OVERFLOW_MASK) {
110 wptr &= ~IH_RB_WPTR__RB_OVERFLOW_MASK;
111 dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
112 wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask);
113 adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask;
114 tmp = RREG32(IH_RB_CNTL);
115 tmp |= IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK;
116 WREG32(IH_RB_CNTL, tmp);
118 return (wptr & adev->irq.ih.ptr_mask);
121 static void si_ih_decode_iv(struct amdgpu_device *adev,
122 struct amdgpu_iv_entry *entry)
124 u32 ring_index = adev->irq.ih.rptr >> 2;
127 dw[0] = le32_to_cpu(adev->irq.ih.ring[ring_index + 0]);
128 dw[1] = le32_to_cpu(adev->irq.ih.ring[ring_index + 1]);
129 dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]);
130 dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]);
132 entry->src_id = dw[0] & 0xff;
133 entry->src_data = dw[1] & 0xfffffff;
134 entry->ring_id = dw[2] & 0xff;
135 entry->vm_id = (dw[2] >> 8) & 0xff;
137 adev->irq.ih.rptr += 16;
140 static void si_ih_set_rptr(struct amdgpu_device *adev)
142 WREG32(IH_RB_RPTR, adev->irq.ih.rptr);
145 static int si_ih_early_init(void *handle)
147 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
149 si_ih_set_interrupt_funcs(adev);
154 static int si_ih_sw_init(void *handle)
157 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
159 r = amdgpu_ih_ring_init(adev, 64 * 1024, false);
163 return amdgpu_irq_init(adev);
166 static int si_ih_sw_fini(void *handle)
168 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
170 amdgpu_irq_fini(adev);
171 amdgpu_ih_ring_fini(adev);
176 static int si_ih_hw_init(void *handle)
178 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
180 return si_ih_irq_init(adev);
183 static int si_ih_hw_fini(void *handle)
185 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
187 si_ih_irq_disable(adev);
192 static int si_ih_suspend(void *handle)
194 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
196 return si_ih_hw_fini(adev);
199 static int si_ih_resume(void *handle)
201 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
203 return si_ih_hw_init(adev);
206 static bool si_ih_is_idle(void *handle)
208 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
209 u32 tmp = RREG32(SRBM_STATUS);
211 if (tmp & SRBM_STATUS__IH_BUSY_MASK)
217 static int si_ih_wait_for_idle(void *handle)
220 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
222 for (i = 0; i < adev->usec_timeout; i++) {
223 if (si_ih_is_idle(handle))
230 static int si_ih_soft_reset(void *handle)
232 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
234 u32 srbm_soft_reset = 0;
235 u32 tmp = RREG32(SRBM_STATUS);
237 if (tmp & SRBM_STATUS__IH_BUSY_MASK)
238 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_IH_MASK;
240 if (srbm_soft_reset) {
241 tmp = RREG32(SRBM_SOFT_RESET);
242 tmp |= srbm_soft_reset;
243 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
244 WREG32(SRBM_SOFT_RESET, tmp);
245 tmp = RREG32(SRBM_SOFT_RESET);
249 tmp &= ~srbm_soft_reset;
250 WREG32(SRBM_SOFT_RESET, tmp);
251 tmp = RREG32(SRBM_SOFT_RESET);
259 static int si_ih_set_clockgating_state(void *handle,
260 enum amd_clockgating_state state)
265 static int si_ih_set_powergating_state(void *handle,
266 enum amd_powergating_state state)
271 static const struct amd_ip_funcs si_ih_ip_funcs = {
273 .early_init = si_ih_early_init,
275 .sw_init = si_ih_sw_init,
276 .sw_fini = si_ih_sw_fini,
277 .hw_init = si_ih_hw_init,
278 .hw_fini = si_ih_hw_fini,
279 .suspend = si_ih_suspend,
280 .resume = si_ih_resume,
281 .is_idle = si_ih_is_idle,
282 .wait_for_idle = si_ih_wait_for_idle,
283 .soft_reset = si_ih_soft_reset,
284 .set_clockgating_state = si_ih_set_clockgating_state,
285 .set_powergating_state = si_ih_set_powergating_state,
288 static const struct amdgpu_ih_funcs si_ih_funcs = {
289 .get_wptr = si_ih_get_wptr,
290 .decode_iv = si_ih_decode_iv,
291 .set_rptr = si_ih_set_rptr
294 static void si_ih_set_interrupt_funcs(struct amdgpu_device *adev)
296 if (adev->irq.ih_funcs == NULL)
297 adev->irq.ih_funcs = &si_ih_funcs;
300 const struct amdgpu_ip_block_version si_ih_ip_block =
302 .type = AMD_IP_BLOCK_TYPE_IH,
306 .funcs = &si_ih_ip_funcs,