drivers/gpu/drm/amd/amdgpu/si_dpm.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <drm/drmP.h>
  25 #include "amdgpu.h"
  26 #include "amdgpu_pm.h"
  27 #include "amdgpu_dpm.h"
  28 #include "amdgpu_atombios.h"
  29 #include "sid.h"
  30 #include "r600_dpm.h"
  31 #include "si_dpm.h"
  32 #include "atom.h"
  33 #include "../include/pptable.h"
  34 #include <linux/math64.h>
  35 #include <linux/seq_file.h>
  36 #include <linux/firmware.h>
  37
  38 #define MC_CG_ARB_FREQ_F0           0x0a
  39 #define MC_CG_ARB_FREQ_F1           0x0b
  40 #define MC_CG_ARB_FREQ_F2           0x0c
  41 #define MC_CG_ARB_FREQ_F3           0x0d
  42
  43 #define SMC_RAM_END                 0x20000
  44
  45 #define SCLK_MIN_DEEPSLEEP_FREQ     1350
  46
  47
  48 /* sizeof(ATOM_PPLIB_EXTENDEDHEADER) */
  49 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V2 12
  50 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V3 14
  51 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V4 16
  52 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V5 18
  53 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V6 20
  54 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V7 22
  55
  56 #define BIOS_SCRATCH_4                                    0x5cd
  57
  58 MODULE_FIRMWARE("radeon/tahiti_smc.bin");
  59 MODULE_FIRMWARE("radeon/pitcairn_smc.bin");
  60 MODULE_FIRMWARE("radeon/pitcairn_k_smc.bin");
  61 MODULE_FIRMWARE("radeon/verde_smc.bin");
  62 MODULE_FIRMWARE("radeon/verde_k_smc.bin");
  63 MODULE_FIRMWARE("radeon/oland_smc.bin");
  64 MODULE_FIRMWARE("radeon/oland_k_smc.bin");
  65 MODULE_FIRMWARE("radeon/hainan_smc.bin");
  66 MODULE_FIRMWARE("radeon/hainan_k_smc.bin");
  67 MODULE_FIRMWARE("radeon/banks_k_2_smc.bin");
  68
  69 union power_info {
  70         struct _ATOM_POWERPLAY_INFO info;
  71         struct _ATOM_POWERPLAY_INFO_V2 info_2;
  72         struct _ATOM_POWERPLAY_INFO_V3 info_3;
  73         struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
  74         struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
  75         struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
  76         struct _ATOM_PPLIB_POWERPLAYTABLE4 pplib4;
  77         struct _ATOM_PPLIB_POWERPLAYTABLE5 pplib5;
  78 };
  79
  80 union fan_info {
  81         struct _ATOM_PPLIB_FANTABLE fan;
  82         struct _ATOM_PPLIB_FANTABLE2 fan2;
  83         struct _ATOM_PPLIB_FANTABLE3 fan3;
  84 };
  85
  86 union pplib_clock_info {
  87         struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
  88         struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
  89         struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
  90         struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
  91         struct _ATOM_PPLIB_SI_CLOCK_INFO si;
  92 };
  93
  94 static const u32 r600_utc[R600_PM_NUMBER_OF_TC] =
  95 {
  96         R600_UTC_DFLT_00,
  97         R600_UTC_DFLT_01,
  98         R600_UTC_DFLT_02,
  99         R600_UTC_DFLT_03,
 100         R600_UTC_DFLT_04,
 101         R600_UTC_DFLT_05,
 102         R600_UTC_DFLT_06,
 103         R600_UTC_DFLT_07,
 104         R600_UTC_DFLT_08,
 105         R600_UTC_DFLT_09,
 106         R600_UTC_DFLT_10,
 107         R600_UTC_DFLT_11,
 108         R600_UTC_DFLT_12,
 109         R600_UTC_DFLT_13,
 110         R600_UTC_DFLT_14,
 111 };
 112
 113 static const u32 r600_dtc[R600_PM_NUMBER_OF_TC] =
 114 {
 115         R600_DTC_DFLT_00,
 116         R600_DTC_DFLT_01,
 117         R600_DTC_DFLT_02,
 118         R600_DTC_DFLT_03,
 119         R600_DTC_DFLT_04,
 120         R600_DTC_DFLT_05,
 121         R600_DTC_DFLT_06,
 122         R600_DTC_DFLT_07,
 123         R600_DTC_DFLT_08,
 124         R600_DTC_DFLT_09,
 125         R600_DTC_DFLT_10,
 126         R600_DTC_DFLT_11,
 127         R600_DTC_DFLT_12,
 128         R600_DTC_DFLT_13,
 129         R600_DTC_DFLT_14,
 130 };
 131
 132 static const struct si_cac_config_reg cac_weights_tahiti[] =
 133 {
 134         { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND },
 135         { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 136         { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND },
 137         { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND },
 138         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 139         { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 140         { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 141         { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 142         { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 143         { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND },
 144         { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 145         { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND },
 146         { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND },
 147         { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND },
 148         { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND },
 149         { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 150         { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 151         { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND },
 152         { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 153         { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND },
 154         { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND },
 155         { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND },
 156         { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 157         { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 158         { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 159         { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 160         { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 161         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 162         { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 163         { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 164         { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND },
 165         { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 166         { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 167         { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 168         { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 169         { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 170         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 171         { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
 172         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 173         { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND },
 174         { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 175         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 176         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 177         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 178         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 179         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 180         { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 181         { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 182         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 183         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 184         { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 185         { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 186         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 187         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 188         { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 189         { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 190         { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 191         { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 192         { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 193         { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND },
 194         { 0xFFFFFFFF }
 195 };
 196
 197 static const struct si_cac_config_reg lcac_tahiti[] =
 198 {
 199         { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 200         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 201         { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 202         { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 203         { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 204         { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 205         { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 206         { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 207         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 208         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 209         { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 210         { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 211         { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 212         { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 213         { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 214         { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 215         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 216         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 217         { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 218         { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 219         { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 220         { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 221         { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 222         { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 223         { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 224         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 225         { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 226         { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 227         { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 228         { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 229         { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 230         { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 231         { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 232         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 233         { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 234         { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 235         { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 236         { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 237         { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 238         { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 239         { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 240         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 241         { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 242         { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 243         { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 244         { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 245         { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 246         { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 247         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 248         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 249         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 250         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 251         { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 252         { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 253         { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 254         { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 255         { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 256         { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 257         { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 258         { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 259         { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 260         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 261         { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 262         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 263         { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 264         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 265         { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 266         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 267         { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 268         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 269         { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 270         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 271         { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
 272         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 273         { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 274         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 275         { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 276         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 277         { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 278         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 279         { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 280         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 281         { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 282         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 283         { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 284         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 285         { 0xFFFFFFFF }
 286
 287 };
 288
 289 static const struct si_cac_config_reg cac_override_tahiti[] =
 290 {
 291         { 0xFFFFFFFF }
 292 };
 293
 294 static const struct si_powertune_data powertune_data_tahiti =
 295 {
 296         ((1 << 16) | 27027),
 297         6,
 298         0,
 299         4,
 300         95,
 301         {
 302                 0UL,
 303                 0UL,
 304                 4521550UL,
 305                 309631529UL,
 306                 -1270850L,
 307                 4513710L,
 308                 40
 309         },
 310         595000000UL,
 311         12,
 312         {
 313                 0,
 314                 0,
 315                 0,
 316                 0,
 317                 0,
 318                 0,
 319                 0,
 320                 0
 321         },
 322         true
 323 };
 324
 325 static const struct si_dte_data dte_data_tahiti =
 326 {
 327         { 1159409, 0, 0, 0, 0 },
 328         { 777, 0, 0, 0, 0 },
 329         2,
 330         54000,
 331         127000,
 332         25,
 333         2,
 334         10,
 335         13,
 336         { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 },
 337         { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 },
 338         { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 },
 339         85,
 340         false
 341 };
 342
 343 #if 0
 344 static const struct si_dte_data dte_data_tahiti_le =
 345 {
 346         { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 },
 347         { 0x7D, 0x7D, 0x4E4, 0xB00, 0 },
 348         0x5,
 349         0xAFC8,
 350         0x64,
 351         0x32,
 352         1,
 353         0,
 354         0x10,
 355         { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 },
 356         { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 },
 357         { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 },
 358         85,
 359         true
 360 };
 361 #endif
 362
 363 static const struct si_dte_data dte_data_tahiti_pro =
 364 {
 365         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 366         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 367         5,
 368         45000,
 369         100,
 370         0xA,
 371         1,
 372         0,
 373         0x10,
 374         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 375         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 376         { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 377         90,
 378         true
 379 };
 380
 381 static const struct si_dte_data dte_data_new_zealand =
 382 {
 383         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 },
 384         { 0x29B, 0x3E9, 0x537, 0x7D2, 0 },
 385         0x5,
 386         0xAFC8,
 387         0x69,
 388         0x32,
 389         1,
 390         0,
 391         0x10,
 392         { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE },
 393         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 394         { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 },
 395         85,
 396         true
 397 };
 398
 399 static const struct si_dte_data dte_data_aruba_pro =
 400 {
 401         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 402         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 403         5,
 404         45000,
 405         100,
 406         0xA,
 407         1,
 408         0,
 409         0x10,
 410         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 411         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 412         { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 413         90,
 414         true
 415 };
 416
 417 static const struct si_dte_data dte_data_malta =
 418 {
 419         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 420         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 421         5,
 422         45000,
 423         100,
 424         0xA,
 425         1,
 426         0,
 427         0x10,
 428         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 429         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 430         { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 431         90,
 432         true
 433 };
 434
 435 static const struct si_cac_config_reg cac_weights_pitcairn[] =
 436 {
 437         { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND },
 438         { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 439         { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 440         { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND },
 441         { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND },
 442         { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 443         { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 444         { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
 445         { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 446         { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND },
 447         { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND },
 448         { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND },
 449         { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND },
 450         { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND },
 451         { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 452         { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 453         { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 454         { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND },
 455         { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND },
 456         { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND },
 457         { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND },
 458         { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND },
 459         { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND },
 460         { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 461         { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 462         { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
 463         { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND },
 464         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 465         { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 466         { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 467         { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND },
 468         { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 469         { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND },
 470         { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 471         { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND },
 472         { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND },
 473         { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND },
 474         { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 475         { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND },
 476         { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 477         { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 478         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 479         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 480         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 481         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 482         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 483         { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 484         { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 485         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 486         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 487         { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 488         { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 489         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 490         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 491         { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 492         { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 493         { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 494         { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 495         { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 496         { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND },
 497         { 0xFFFFFFFF }
 498 };
 499
 500 static const struct si_cac_config_reg lcac_pitcairn[] =
 501 {
 502         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 503         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 504         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 505         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 506         { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 507         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 508         { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 509         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 510         { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 511         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 512         { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 513         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 514         { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 515         { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 516         { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 517         { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 518         { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 519         { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 520         { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 521         { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 522         { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 523         { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 524         { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 525         { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 526         { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 527         { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 528         { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 529         { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 530         { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 531         { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 532         { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 533         { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 534         { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 535         { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 536         { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 537         { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 538         { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 539         { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 540         { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 541         { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 542         { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 543         { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 544         { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 545         { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 546         { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 547         { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 548         { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 549         { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 550         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 551         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 552         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 553         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 554         { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 555         { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 556         { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 557         { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 558         { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 559         { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 560         { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 561         { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 562         { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 563         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 564         { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 565         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 566         { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 567         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 568         { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 569         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 570         { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 571         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 572         { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 573         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 574         { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 575         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 576         { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 577         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 578         { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 579         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 580         { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 581         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 582         { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 583         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 584         { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 585         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 586         { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 587         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 588         { 0xFFFFFFFF }
 589 };
 590
 591 static const struct si_cac_config_reg cac_override_pitcairn[] =
 592 {
 593     { 0xFFFFFFFF }
 594 };
 595
 596 static const struct si_powertune_data powertune_data_pitcairn =
 597 {
 598         ((1 << 16) | 27027),
 599         5,
 600         0,
 601         6,
 602         100,
 603         {
 604                 51600000UL,
 605                 1800000UL,
 606                 7194395UL,
 607                 309631529UL,
 608                 -1270850L,
 609                 4513710L,
 610                 100
 611         },
 612         117830498UL,
 613         12,
 614         {
 615                 0,
 616                 0,
 617                 0,
 618                 0,
 619                 0,
 620                 0,
 621                 0,
 622                 0
 623         },
 624         true
 625 };
 626
 627 static const struct si_dte_data dte_data_pitcairn =
 628 {
 629         { 0, 0, 0, 0, 0 },
 630         { 0, 0, 0, 0, 0 },
 631         0,
 632         0,
 633         0,
 634         0,
 635         0,
 636         0,
 637         0,
 638         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
 639         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
 640         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
 641         0,
 642         false
 643 };
 644
 645 static const struct si_dte_data dte_data_curacao_xt =
 646 {
 647         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 648         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 649         5,
 650         45000,
 651         100,
 652         0xA,
 653         1,
 654         0,
 655         0x10,
 656         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 657         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 658         { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 659         90,
 660         true
 661 };
 662
 663 static const struct si_dte_data dte_data_curacao_pro =
 664 {
 665         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 666         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 667         5,
 668         45000,
 669         100,
 670         0xA,
 671         1,
 672         0,
 673         0x10,
 674         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 675         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 676         { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 677         90,
 678         true
 679 };
 680
 681 static const struct si_dte_data dte_data_neptune_xt =
 682 {
 683         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 684         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 685         5,
 686         45000,
 687         100,
 688         0xA,
 689         1,
 690         0,
 691         0x10,
 692         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 693         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 694         { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 695         90,
 696         true
 697 };
 698
 699 static const struct si_cac_config_reg cac_weights_chelsea_pro[] =
 700 {
 701         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 702         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 703         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 704         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 705         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 706         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 707         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 708         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 709         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 710         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 711         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 712         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 713         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 714         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 715         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 716         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 717         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 718         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 719         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 720         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 721         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 722         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 723         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 724         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 725         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 726         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 727         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 728         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 729         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 730         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 731         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 732         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 733         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 734         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 735         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 736         { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND },
 737         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 738         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 739         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 740         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 741         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 742         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 743         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 744         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 745         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 746         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 747         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 748         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 749         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 750         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 751         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 752         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 753         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 754         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 755         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 756         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 757         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 758         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 759         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 760         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 761         { 0xFFFFFFFF }
 762 };
 763
 764 static const struct si_cac_config_reg cac_weights_chelsea_xt[] =
 765 {
 766         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 767         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 768         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 769         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 770         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 771         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 772         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 773         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 774         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 775         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 776         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 777         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 778         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 779         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 780         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 781         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 782         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 783         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 784         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 785         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 786         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 787         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 788         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 789         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 790         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 791         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 792         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 793         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 794         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 795         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 796         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 797         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 798         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 799         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 800         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 801         { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND },
 802         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 803         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 804         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 805         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 806         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 807         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 808         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 809         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 810         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 811         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 812         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 813         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 814         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 815         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 816         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 817         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 818         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 819         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 820         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 821         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 822         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 823         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 824         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 825         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 826         { 0xFFFFFFFF }
 827 };
 828
 829 static const struct si_cac_config_reg cac_weights_heathrow[] =
 830 {
 831         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 832         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 833         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 834         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 835         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 836         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 837         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 838         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 839         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 840         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 841         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 842         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 843         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 844         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 845         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 846         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 847         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 848         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 849         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 850         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 851         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 852         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 853         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 854         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 855         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 856         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 857         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 858         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 859         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 860         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 861         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 862         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 863         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 864         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 865         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 866         { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND },
 867         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 868         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 869         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 870         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 871         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 872         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 873         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 874         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 875         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 876         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 877         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 878         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 879         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 880         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 881         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 882         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 883         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 884         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 885         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 886         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 887         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 888         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 889         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 890         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 891         { 0xFFFFFFFF }
 892 };
 893
 894 static const struct si_cac_config_reg cac_weights_cape_verde_pro[] =
 895 {
 896         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 897         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 898         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 899         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 900         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 901         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 902         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 903         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 904         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 905         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 906         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 907         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 908         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 909         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 910         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 911         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 912         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 913         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 914         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 915         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 916         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 917         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 918         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 919         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 920         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 921         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 922         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 923         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 924         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 925         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 926         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 927         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 928         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 929         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 930         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 931         { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND },
 932         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 933         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 934         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 935         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 936         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 937         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 938         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 939         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 940         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 941         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 942         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 943         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 944         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 945         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 946         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 947         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 948         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 949         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 950         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 951         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 952         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 953         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 954         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 955         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 956         { 0xFFFFFFFF }
 957 };
 958
 959 static const struct si_cac_config_reg cac_weights_cape_verde[] =
 960 {
 961         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 962         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 963         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 964         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 965         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 966         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 967         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 968         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 969         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 970         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 971         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 972         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 973         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 974         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 975         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 976         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 977         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 978         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 979         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 980         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 981         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 982         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 983         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 984         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 985         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 986         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 987         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 988         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 989         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 990         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 991         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 992         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 993         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 994         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 995         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 996         { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
 997         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 998         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 999         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1000         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1001         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
1002         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1003         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1004         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1005         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1006         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1007         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1008         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1009         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1010         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1011         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1012         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1013         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1014         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1015         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1016         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1017         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1018         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1019         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1020         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1021         { 0xFFFFFFFF }
1022 };
1023
1024 static const struct si_cac_config_reg lcac_cape_verde[] =
1025 {
1026         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1027         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1028         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1029         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1030         { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1031         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1032         { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1033         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1034         { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1035         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1036         { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1037         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1038         { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1039         { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1040         { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1041         { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1042         { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1043         { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1044         { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1045         { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1046         { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1047         { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1048         { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1049         { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1050         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1051         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1052         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1053         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1054         { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1055         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1056         { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1057         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1058         { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1059         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1060         { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1061         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1062         { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1063         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1064         { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1065         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1066         { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1067         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1068         { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1069         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1070         { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1071         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1072         { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1073         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1074         { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1075         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1076         { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1077         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1078         { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1079         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1080         { 0xFFFFFFFF }
1081 };
1082
1083 static const struct si_cac_config_reg cac_override_cape_verde[] =
1084 {
1085     { 0xFFFFFFFF }
1086 };
1087
1088 static const struct si_powertune_data powertune_data_cape_verde =
1089 {
1090         ((1 << 16) | 0x6993),
1091         5,
1092         0,
1093         7,
1094         105,
1095         {
1096                 0UL,
1097                 0UL,
1098                 7194395UL,
1099                 309631529UL,
1100                 -1270850L,
1101                 4513710L,
1102                 100
1103         },
1104         117830498UL,
1105         12,
1106         {
1107                 0,
1108                 0,
1109                 0,
1110                 0,
1111                 0,
1112                 0,
1113                 0,
1114                 0
1115         },
1116         true
1117 };
1118
1119 static const struct si_dte_data dte_data_cape_verde =
1120 {
1121         { 0, 0, 0, 0, 0 },
1122         { 0, 0, 0, 0, 0 },
1123         0,
1124         0,
1125         0,
1126         0,
1127         0,
1128         0,
1129         0,
1130         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1131         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1132         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1133         0,
1134         false
1135 };
1136
1137 static const struct si_dte_data dte_data_venus_xtx =
1138 {
1139         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1140         { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 },
1141         5,
1142         55000,
1143         0x69,
1144         0xA,
1145         1,
1146         0,
1147         0x3,
1148         { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1149         { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1150         { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1151         90,
1152         true
1153 };
1154
1155 static const struct si_dte_data dte_data_venus_xt =
1156 {
1157         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1158         { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 },
1159         5,
1160         55000,
1161         0x69,
1162         0xA,
1163         1,
1164         0,
1165         0x3,
1166         { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1167         { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1168         { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1169         90,
1170         true
1171 };
1172
1173 static const struct si_dte_data dte_data_venus_pro =
1174 {
1175         {  0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1176         { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 },
1177         5,
1178         55000,
1179         0x69,
1180         0xA,
1181         1,
1182         0,
1183         0x3,
1184         { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1185         { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1186         { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1187         90,
1188         true
1189 };
1190
1191 static const struct si_cac_config_reg cac_weights_oland[] =
1192 {
1193         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
1194         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1195         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
1196         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
1197         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1198         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1199         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1200         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1201         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
1202         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
1203         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
1204         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
1205         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
1206         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1207         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
1208         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
1209         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
1210         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
1211         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
1212         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
1213         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
1214         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
1215         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
1216         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
1217         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
1218         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1219         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1220         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1221         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1222         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
1223         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1224         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
1225         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
1226         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
1227         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1228         { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
1229         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1230         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1231         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1232         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1233         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
1234         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1235         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1236         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1237         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1238         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1239         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1240         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1241         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1242         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1243         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1244         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1245         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1246         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1247         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1248         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1249         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1250         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1251         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1252         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1253         { 0xFFFFFFFF }
1254 };
1255
1256 static const struct si_cac_config_reg cac_weights_mars_pro[] =
1257 {
1258         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1259         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1260         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1261         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1262         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1263         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1264         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1265         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1266         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1267         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1268         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1269         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1270         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1271         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1272         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1273         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1274         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1275         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1276         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1277         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1278         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1279         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1280         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1281         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1282         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1283         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1284         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1285         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1286         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1287         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1288         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1289         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1290         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1291         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1292         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1293         { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND },
1294         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1295         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1296         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1297         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1298         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1299         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1300         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1301         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1302         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1303         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1304         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1305         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1306         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1307         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1308         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1309         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1310         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1311         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1312         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1313         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1314         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1315         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1316         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1317         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1318         { 0xFFFFFFFF }
1319 };
1320
1321 static const struct si_cac_config_reg cac_weights_mars_xt[] =
1322 {
1323         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1324         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1325         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1326         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1327         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1328         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1329         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1330         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1331         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1332         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1333         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1334         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1335         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1336         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1337         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1338         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1339         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1340         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1341         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1342         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1343         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1344         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1345         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1346         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1347         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1348         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1349         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1350         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1351         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1352         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1353         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1354         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1355         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1356         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1357         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1358         { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND },
1359         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1360         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1361         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1362         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1363         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1364         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1365         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1366         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1367         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1368         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1369         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1370         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1371         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1372         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1373         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1374         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1375         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1376         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1377         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1378         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1379         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1380         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1381         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1382         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1383         { 0xFFFFFFFF }
1384 };
1385
1386 static const struct si_cac_config_reg cac_weights_oland_pro[] =
1387 {
1388         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1389         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1390         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1391         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1392         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1393         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1394         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1395         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1396         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1397         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1398         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1399         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1400         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1401         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1402         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1403         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1404         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1405         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1406         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1407         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1408         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1409         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1410         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1411         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1412         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1413         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1414         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1415         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1416         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1417         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1418         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1419         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1420         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1421         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1422         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1423         { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND },
1424         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1425         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1426         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1427         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1428         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1429         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1430         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1431         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1432         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1433         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1434         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1435         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1436         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1437         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1438         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1439         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1440         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1441         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1442         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1443         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1444         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1445         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1446         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1447         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1448         { 0xFFFFFFFF }
1449 };
1450
1451 static const struct si_cac_config_reg cac_weights_oland_xt[] =
1452 {
1453         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1454         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1455         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1456         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1457         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1458         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1459         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1460         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1461         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1462         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1463         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1464         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1465         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1466         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1467         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1468         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1469         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1470         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1471         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1472         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1473         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1474         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1475         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1476         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1477         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1478         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1479         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1480         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1481         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1482         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1483         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1484         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1485         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1486         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1487         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1488         { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND },
1489         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1490         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1491         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1492         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1493         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1494         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1495         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1496         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1497         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1498         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1499         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1500         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1501         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1502         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1503         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1504         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1505         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1506         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1507         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1508         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1509         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1510         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1511         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1512         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1513         { 0xFFFFFFFF }
1514 };
1515
1516 static const struct si_cac_config_reg lcac_oland[] =
1517 {
1518         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1519         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1520         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1521         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1522         { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1523         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1524         { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1525         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1526         { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1527         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1528         { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
1529         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1530         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1531         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1532         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1533         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1534         { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1535         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1536         { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1537         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1538         { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1539         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1540         { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1541         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1542         { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1543         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1544         { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1545         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1546         { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1547         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1548         { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1549         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1550         { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1551         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1552         { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1553         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1554         { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1555         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1556         { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1557         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1558         { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1559         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1560         { 0xFFFFFFFF }
1561 };
1562
1563 static const struct si_cac_config_reg lcac_mars_pro[] =
1564 {
1565         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1566         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1567         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1568         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1569         { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1570         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1571         { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1572         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1573         { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1574         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1575         { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1576         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1577         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1578         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1579         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1580         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1581         { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1582         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1583         { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1584         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1585         { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1586         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1587         { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1588         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1589         { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1590         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1591         { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1592         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1593         { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1594         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1595         { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1596         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1597         { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1598         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1599         { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1600         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1601         { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1602         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1603         { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1604         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1605         { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1606         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1607         { 0xFFFFFFFF }
1608 };
1609
1610 static const struct si_cac_config_reg cac_override_oland[] =
1611 {
1612         { 0xFFFFFFFF }
1613 };
1614
1615 static const struct si_powertune_data powertune_data_oland =
1616 {
1617         ((1 << 16) | 0x6993),
1618         5,
1619         0,
1620         7,
1621         105,
1622         {
1623                 0UL,
1624                 0UL,
1625                 7194395UL,
1626                 309631529UL,
1627                 -1270850L,
1628                 4513710L,
1629                 100
1630         },
1631         117830498UL,
1632         12,
1633         {
1634                 0,
1635                 0,
1636                 0,
1637                 0,
1638                 0,
1639                 0,
1640                 0,
1641                 0
1642         },
1643         true
1644 };
1645
1646 static const struct si_powertune_data powertune_data_mars_pro =
1647 {
1648         ((1 << 16) | 0x6993),
1649         5,
1650         0,
1651         7,
1652         105,
1653         {
1654                 0UL,
1655                 0UL,
1656                 7194395UL,
1657                 309631529UL,
1658                 -1270850L,
1659                 4513710L,
1660                 100
1661         },
1662         117830498UL,
1663         12,
1664         {
1665                 0,
1666                 0,
1667                 0,
1668                 0,
1669                 0,
1670                 0,
1671                 0,
1672                 0
1673         },
1674         true
1675 };
1676
1677 static const struct si_dte_data dte_data_oland =
1678 {
1679         { 0, 0, 0, 0, 0 },
1680         { 0, 0, 0, 0, 0 },
1681         0,
1682         0,
1683         0,
1684         0,
1685         0,
1686         0,
1687         0,
1688         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1689         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1690         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1691         0,
1692         false
1693 };
1694
1695 static const struct si_dte_data dte_data_mars_pro =
1696 {
1697         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1698         { 0x0, 0x0, 0x0, 0x0, 0x0 },
1699         5,
1700         55000,
1701         105,
1702         0xA,
1703         1,
1704         0,
1705         0x10,
1706         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1707         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1708         { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1709         90,
1710         true
1711 };
1712
1713 static const struct si_dte_data dte_data_sun_xt =
1714 {
1715         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1716         { 0x0, 0x0, 0x0, 0x0, 0x0 },
1717         5,
1718         55000,
1719         105,
1720         0xA,
1721         1,
1722         0,
1723         0x10,
1724         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1725         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1726         { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1727         90,
1728         true
1729 };
1730
1731
1732 static const struct si_cac_config_reg cac_weights_hainan[] =
1733 {
1734         { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND },
1735         { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND },
1736         { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND },
1737         { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND },
1738         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1739         { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND },
1740         { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1741         { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1742         { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1743         { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND },
1744         { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND },
1745         { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND },
1746         { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND },
1747         { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1748         { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND },
1749         { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1750         { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1751         { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND },
1752         { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND },
1753         { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND },
1754         { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND },
1755         { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND },
1756         { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND },
1757         { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND },
1758         { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1759         { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND },
1760         { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND },
1761         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1762         { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1763         { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1764         { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND },
1765         { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1766         { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1767         { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1768         { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND },
1769         { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND },
1770         { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
1771         { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1772         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1773         { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND },
1774         { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1775         { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND },
1776         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1777         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1778         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1779         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1780         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1781         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1782         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1783         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1784         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1785         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1786         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1787         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1788         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1789         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1790         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1791         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1792         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1793         { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND },
1794         { 0xFFFFFFFF }
1795 };
1796
1797 static const struct si_powertune_data powertune_data_hainan =
1798 {
1799         ((1 << 16) | 0x6993),
1800         5,
1801         0,
1802         9,
1803         105,
1804         {
1805                 0UL,
1806                 0UL,
1807                 7194395UL,
1808                 309631529UL,
1809                 -1270850L,
1810                 4513710L,
1811                 100
1812         },
1813         117830498UL,
1814         12,
1815         {
1816                 0,
1817                 0,
1818                 0,
1819                 0,
1820                 0,
1821                 0,
1822                 0,
1823                 0
1824         },
1825         true
1826 };
1827
1828 static struct rv7xx_power_info *rv770_get_pi(struct amdgpu_device *adev);
1829 static struct evergreen_power_info *evergreen_get_pi(struct amdgpu_device *adev);
1830 static struct ni_power_info *ni_get_pi(struct amdgpu_device *adev);
1831 static struct  si_ps *si_get_ps(struct amdgpu_ps *rps);
1832
1833 static int si_populate_voltage_value(struct amdgpu_device *adev,
1834                                      const struct atom_voltage_table *table,
1835                                      u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage);
1836 static int si_get_std_voltage_value(struct amdgpu_device *adev,
1837                                     SISLANDS_SMC_VOLTAGE_VALUE *voltage,
1838                                     u16 *std_voltage);
1839 static int si_write_smc_soft_register(struct amdgpu_device *adev,
1840                                       u16 reg_offset, u32 value);
1841 static int si_convert_power_level_to_smc(struct amdgpu_device *adev,
1842                                          struct rv7xx_pl *pl,
1843                                          SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level);
1844 static int si_calculate_sclk_params(struct amdgpu_device *adev,
1845                                     u32 engine_clock,
1846                                     SISLANDS_SMC_SCLK_VALUE *sclk);
1847
1848 static void si_thermal_start_smc_fan_control(struct amdgpu_device *adev);
1849 static void si_fan_ctrl_set_default_mode(struct amdgpu_device *adev);
1850 static void si_dpm_set_dpm_funcs(struct amdgpu_device *adev);
1851 static void si_dpm_set_irq_funcs(struct amdgpu_device *adev);
1852
1853 static struct si_power_info *si_get_pi(struct amdgpu_device *adev)
1854 {
1855         struct si_power_info *pi = adev->pm.dpm.priv;
1856         return pi;
1857 }
1858
1859 static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff,
1860                                                      u16 v, s32 t, u32 ileakage, u32 *leakage)
1861 {
1862         s64 kt, kv, leakage_w, i_leakage, vddc;
1863         s64 temperature, t_slope, t_intercept, av, bv, t_ref;
1864         s64 tmp;
1865
1866         i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1867         vddc = div64_s64(drm_int2fixp(v), 1000);
1868         temperature = div64_s64(drm_int2fixp(t), 1000);
1869
1870         t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000);
1871         t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000);
1872         av = div64_s64(drm_int2fixp(coeff->av), 100000000);
1873         bv = div64_s64(drm_int2fixp(coeff->bv), 100000000);
1874         t_ref = drm_int2fixp(coeff->t_ref);
1875
1876         tmp = drm_fixp_mul(t_slope, vddc) + t_intercept;
1877         kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature));
1878         kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref)));
1879         kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc)));
1880
1881         leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1882
1883         *leakage = drm_fixp2int(leakage_w * 1000);
1884 }
1885
1886 static void si_calculate_leakage_for_v_and_t(struct amdgpu_device *adev,
1887                                              const struct ni_leakage_coeffients *coeff,
1888                                              u16 v,
1889                                              s32 t,
1890                                              u32 i_leakage,
1891                                              u32 *leakage)
1892 {
1893         si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage);
1894 }
1895
1896 static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff,
1897                                                const u32 fixed_kt, u16 v,
1898                                                u32 ileakage, u32 *leakage)
1899 {
1900         s64 kt, kv, leakage_w, i_leakage, vddc;
1901
1902         i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1903         vddc = div64_s64(drm_int2fixp(v), 1000);
1904
1905         kt = div64_s64(drm_int2fixp(fixed_kt), 100000000);
1906         kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000),
1907                           drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc)));
1908
1909         leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1910
1911         *leakage = drm_fixp2int(leakage_w * 1000);
1912 }
1913
1914 static void si_calculate_leakage_for_v(struct amdgpu_device *adev,
1915                                        const struct ni_leakage_coeffients *coeff,
1916                                        const u32 fixed_kt,
1917                                        u16 v,
1918                                        u32 i_leakage,
1919                                        u32 *leakage)
1920 {
1921         si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage);
1922 }
1923
1924
1925 static void si_update_dte_from_pl2(struct amdgpu_device *adev,
1926                                    struct si_dte_data *dte_data)
1927 {
1928         u32 p_limit1 = adev->pm.dpm.tdp_limit;
1929         u32 p_limit2 = adev->pm.dpm.near_tdp_limit;
1930         u32 k = dte_data->k;
1931         u32 t_max = dte_data->max_t;
1932         u32 t_split[5] = { 10, 15, 20, 25, 30 };
1933         u32 t_0 = dte_data->t0;
1934         u32 i;
1935
1936         if (p_limit2 != 0 && p_limit2 <= p_limit1) {
1937                 dte_data->tdep_count = 3;
1938
1939                 for (i = 0; i < k; i++) {
1940                         dte_data->r[i] =
1941                                 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) /
1942                                 (p_limit2  * (u32)100);
1943                 }
1944
1945                 dte_data->tdep_r[1] = dte_data->r[4] * 2;
1946
1947                 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) {
1948                         dte_data->tdep_r[i] = dte_data->r[4];
1949                 }
1950         } else {
1951                 DRM_ERROR("Invalid PL2! DTE will not be updated.\n");
1952         }
1953 }
1954
1955 static struct rv7xx_power_info *rv770_get_pi(struct amdgpu_device *adev)
1956 {
1957         struct rv7xx_power_info *pi = adev->pm.dpm.priv;
1958
1959         return pi;
1960 }
1961
1962 static struct ni_power_info *ni_get_pi(struct amdgpu_device *adev)
1963 {
1964         struct ni_power_info *pi = adev->pm.dpm.priv;
1965
1966         return pi;
1967 }
1968
1969 static struct si_ps *si_get_ps(struct amdgpu_ps *aps)
1970 {
1971         struct  si_ps *ps = aps->ps_priv;
1972
1973         return ps;
1974 }
1975
1976 static void si_initialize_powertune_defaults(struct amdgpu_device *adev)
1977 {
1978         struct ni_power_info *ni_pi = ni_get_pi(adev);
1979         struct si_power_info *si_pi = si_get_pi(adev);
1980         bool update_dte_from_pl2 = false;
1981
1982         if (adev->asic_type == CHIP_TAHITI) {
1983                 si_pi->cac_weights = cac_weights_tahiti;
1984                 si_pi->lcac_config = lcac_tahiti;
1985                 si_pi->cac_override = cac_override_tahiti;
1986                 si_pi->powertune_data = &powertune_data_tahiti;
1987                 si_pi->dte_data = dte_data_tahiti;
1988
1989                 switch (adev->pdev->device) {
1990                 case 0x6798:
1991                         si_pi->dte_data.enable_dte_by_default = true;
1992                         break;
1993                 case 0x6799:
1994                         si_pi->dte_data = dte_data_new_zealand;
1995                         break;
1996                 case 0x6790:
1997                 case 0x6791:
1998                 case 0x6792:
1999                 case 0x679E:
2000                         si_pi->dte_data = dte_data_aruba_pro;
2001                         update_dte_from_pl2 = true;
2002                         break;
2003                 case 0x679B:
2004                         si_pi->dte_data = dte_data_malta;
2005                         update_dte_from_pl2 = true;
2006                         break;
2007                 case 0x679A:
2008                         si_pi->dte_data = dte_data_tahiti_pro;
2009                         update_dte_from_pl2 = true;
2010                         break;
2011                 default:
2012                         if (si_pi->dte_data.enable_dte_by_default == true)
2013                                 DRM_ERROR("DTE is not enabled!\n");
2014                         break;
2015                 }
2016         } else if (adev->asic_type == CHIP_PITCAIRN) {
2017                 si_pi->cac_weights = cac_weights_pitcairn;
2018                 si_pi->lcac_config = lcac_pitcairn;
2019                 si_pi->cac_override = cac_override_pitcairn;
2020                 si_pi->powertune_data = &powertune_data_pitcairn;
2021
2022                 switch (adev->pdev->device) {
2023                 case 0x6810:
2024                 case 0x6818:
2025                         si_pi->dte_data = dte_data_curacao_xt;
2026                         update_dte_from_pl2 = true;
2027                         break;
2028                 case 0x6819:
2029                 case 0x6811:
2030                         si_pi->dte_data = dte_data_curacao_pro;
2031                         update_dte_from_pl2 = true;
2032                         break;
2033                 case 0x6800:
2034                 case 0x6806:
2035                         si_pi->dte_data = dte_data_neptune_xt;
2036                         update_dte_from_pl2 = true;
2037                         break;
2038                 default:
2039                         si_pi->dte_data = dte_data_pitcairn;
2040                         break;
2041                 }
2042         } else if (adev->asic_type == CHIP_VERDE) {
2043                 si_pi->lcac_config = lcac_cape_verde;
2044                 si_pi->cac_override = cac_override_cape_verde;
2045                 si_pi->powertune_data = &powertune_data_cape_verde;
2046
2047                 switch (adev->pdev->device) {
2048                 case 0x683B:
2049                 case 0x683F:
2050                 case 0x6829:
2051                 case 0x6835:
2052                         si_pi->cac_weights = cac_weights_cape_verde_pro;
2053                         si_pi->dte_data = dte_data_cape_verde;
2054                         break;
2055                 case 0x682C:
2056                         si_pi->cac_weights = cac_weights_cape_verde_pro;
2057                         si_pi->dte_data = dte_data_sun_xt;
2058                         update_dte_from_pl2 = true;
2059                         break;
2060                 case 0x6825:
2061                 case 0x6827:
2062                         si_pi->cac_weights = cac_weights_heathrow;
2063                         si_pi->dte_data = dte_data_cape_verde;
2064                         break;
2065                 case 0x6824:
2066                 case 0x682D:
2067                         si_pi->cac_weights = cac_weights_chelsea_xt;
2068                         si_pi->dte_data = dte_data_cape_verde;
2069                         break;
2070                 case 0x682F:
2071                         si_pi->cac_weights = cac_weights_chelsea_pro;
2072                         si_pi->dte_data = dte_data_cape_verde;
2073                         break;
2074                 case 0x6820:
2075                         si_pi->cac_weights = cac_weights_heathrow;
2076                         si_pi->dte_data = dte_data_venus_xtx;
2077                         break;
2078                 case 0x6821:
2079                         si_pi->cac_weights = cac_weights_heathrow;
2080                         si_pi->dte_data = dte_data_venus_xt;
2081                         break;
2082                 case 0x6823:
2083                 case 0x682B:
2084                 case 0x6822:
2085                 case 0x682A:
2086                         si_pi->cac_weights = cac_weights_chelsea_pro;
2087                         si_pi->dte_data = dte_data_venus_pro;
2088                         break;
2089                 default:
2090                         si_pi->cac_weights = cac_weights_cape_verde;
2091                         si_pi->dte_data = dte_data_cape_verde;
2092                         break;
2093                 }
2094         } else if (adev->asic_type == CHIP_OLAND) {
2095                 si_pi->lcac_config = lcac_mars_pro;
2096                 si_pi->cac_override = cac_override_oland;
2097                 si_pi->powertune_data = &powertune_data_mars_pro;
2098                 si_pi->dte_data = dte_data_mars_pro;
2099
2100                 switch (adev->pdev->device) {
2101                 case 0x6601:
2102                 case 0x6621:
2103                 case 0x6603:
2104                 case 0x6605:
2105                         si_pi->cac_weights = cac_weights_mars_pro;
2106                         update_dte_from_pl2 = true;
2107                         break;
2108                 case 0x6600:
2109                 case 0x6606:
2110                 case 0x6620:
2111                 case 0x6604:
2112                         si_pi->cac_weights = cac_weights_mars_xt;
2113                         update_dte_from_pl2 = true;
2114                         break;
2115                 case 0x6611:
2116                 case 0x6613:
2117                 case 0x6608:
2118                         si_pi->cac_weights = cac_weights_oland_pro;
2119                         update_dte_from_pl2 = true;
2120                         break;
2121                 case 0x6610:
2122                         si_pi->cac_weights = cac_weights_oland_xt;
2123                         update_dte_from_pl2 = true;
2124                         break;
2125                 default:
2126                         si_pi->cac_weights = cac_weights_oland;
2127                         si_pi->lcac_config = lcac_oland;
2128                         si_pi->cac_override = cac_override_oland;
2129                         si_pi->powertune_data = &powertune_data_oland;
2130                         si_pi->dte_data = dte_data_oland;
2131                         break;
2132                 }
2133         } else if (adev->asic_type == CHIP_HAINAN) {
2134                 si_pi->cac_weights = cac_weights_hainan;
2135                 si_pi->lcac_config = lcac_oland;
2136                 si_pi->cac_override = cac_override_oland;
2137                 si_pi->powertune_data = &powertune_data_hainan;
2138                 si_pi->dte_data = dte_data_sun_xt;
2139                 update_dte_from_pl2 = true;
2140         } else {
2141                 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n");
2142                 return;
2143         }
2144
2145         ni_pi->enable_power_containment = false;
2146         ni_pi->enable_cac = false;
2147         ni_pi->enable_sq_ramping = false;
2148         si_pi->enable_dte = false;
2149
2150         if (si_pi->powertune_data->enable_powertune_by_default) {
2151                 ni_pi->enable_power_containment = true;
2152                 ni_pi->enable_cac = true;
2153                 if (si_pi->dte_data.enable_dte_by_default) {
2154                         si_pi->enable_dte = true;
2155                         if (update_dte_from_pl2)
2156                                 si_update_dte_from_pl2(adev, &si_pi->dte_data);
2157
2158                 }
2159                 ni_pi->enable_sq_ramping = true;
2160         }
2161
2162         ni_pi->driver_calculate_cac_leakage = true;
2163         ni_pi->cac_configuration_required = true;
2164
2165         if (ni_pi->cac_configuration_required) {
2166                 ni_pi->support_cac_long_term_average = true;
2167                 si_pi->dyn_powertune_data.l2_lta_window_size =
2168                         si_pi->powertune_data->l2_lta_window_size_default;
2169                 si_pi->dyn_powertune_data.lts_truncate =
2170                         si_pi->powertune_data->lts_truncate_default;
2171         } else {
2172                 ni_pi->support_cac_long_term_average = false;
2173                 si_pi->dyn_powertune_data.l2_lta_window_size = 0;
2174                 si_pi->dyn_powertune_data.lts_truncate = 0;
2175         }
2176
2177         si_pi->dyn_powertune_data.disable_uvd_powertune = false;
2178 }
2179
2180 static u32 si_get_smc_power_scaling_factor(struct amdgpu_device *adev)
2181 {
2182         return 1;
2183 }
2184
2185 static u32 si_calculate_cac_wintime(struct amdgpu_device *adev)
2186 {
2187         u32 xclk;
2188         u32 wintime;
2189         u32 cac_window;
2190         u32 cac_window_size;
2191
2192         xclk = amdgpu_asic_get_xclk(adev);
2193
2194         if (xclk == 0)
2195                 return 0;
2196
2197         cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK;
2198         cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF);
2199
2200         wintime = (cac_window_size * 100) / xclk;
2201
2202         return wintime;
2203 }
2204
2205 static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor)
2206 {
2207         return power_in_watts;
2208 }
2209
2210 static int si_calculate_adjusted_tdp_limits(struct amdgpu_device *adev,
2211                                             bool adjust_polarity,
2212                                             u32 tdp_adjustment,
2213                                             u32 *tdp_limit,
2214                                             u32 *near_tdp_limit)
2215 {
2216         u32 adjustment_delta, max_tdp_limit;
2217
2218         if (tdp_adjustment > (u32)adev->pm.dpm.tdp_od_limit)
2219                 return -EINVAL;
2220
2221         max_tdp_limit = ((100 + 100) * adev->pm.dpm.tdp_limit) / 100;
2222
2223         if (adjust_polarity) {
2224                 *tdp_limit = ((100 + tdp_adjustment) * adev->pm.dpm.tdp_limit) / 100;
2225                 *near_tdp_limit = adev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - adev->pm.dpm.tdp_limit);
2226         } else {
2227                 *tdp_limit = ((100 - tdp_adjustment) * adev->pm.dpm.tdp_limit) / 100;
2228                 adjustment_delta  = adev->pm.dpm.tdp_limit - *tdp_limit;
2229                 if (adjustment_delta < adev->pm.dpm.near_tdp_limit_adjusted)
2230                         *near_tdp_limit = adev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta;
2231                 else
2232                         *near_tdp_limit = 0;
2233         }
2234
2235         if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit))
2236                 return -EINVAL;
2237         if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit))
2238                 return -EINVAL;
2239
2240         return 0;
2241 }
2242
2243 static int si_populate_smc_tdp_limits(struct amdgpu_device *adev,
2244                                       struct amdgpu_ps *amdgpu_state)
2245 {
2246         struct ni_power_info *ni_pi = ni_get_pi(adev);
2247         struct si_power_info *si_pi = si_get_pi(adev);
2248
2249         if (ni_pi->enable_power_containment) {
2250                 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2251                 PP_SIslands_PAPMParameters *papm_parm;
2252                 struct amdgpu_ppm_table *ppm = adev->pm.dpm.dyn_state.ppm_table;
2253                 u32 scaling_factor = si_get_smc_power_scaling_factor(adev);
2254                 u32 tdp_limit;
2255                 u32 near_tdp_limit;
2256                 int ret;
2257
2258                 if (scaling_factor == 0)
2259                         return -EINVAL;
2260
2261                 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2262
2263                 ret = si_calculate_adjusted_tdp_limits(adev,
2264                                                        false, /* ??? */
2265                                                        adev->pm.dpm.tdp_adjustment,
2266                                                        &tdp_limit,
2267                                                        &near_tdp_limit);
2268                 if (ret)
2269                         return ret;
2270
2271                 smc_table->dpm2Params.TDPLimit =
2272                         cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000);
2273                 smc_table->dpm2Params.NearTDPLimit =
2274                         cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000);
2275                 smc_table->dpm2Params.SafePowerLimit =
2276                         cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2277
2278                 ret = amdgpu_si_copy_bytes_to_smc(adev,
2279                                                   (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2280                                                    offsetof(PP_SIslands_DPM2Parameters, TDPLimit)),
2281                                                   (u8 *)(&(smc_table->dpm2Params.TDPLimit)),
2282                                                   sizeof(u32) * 3,
2283                                                   si_pi->sram_end);
2284                 if (ret)
2285                         return ret;
2286
2287                 if (si_pi->enable_ppm) {
2288                         papm_parm = &si_pi->papm_parm;
2289                         memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters));
2290                         papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp);
2291                         papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max);
2292                         papm_parm->dGPU_T_Warning = cpu_to_be32(95);
2293                         papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5);
2294                         papm_parm->PlatformPowerLimit = 0xffffffff;
2295                         papm_parm->NearTDPLimitPAPM = 0xffffffff;
2296
2297                         ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->papm_cfg_table_start,
2298                                                           (u8 *)papm_parm,
2299                                                           sizeof(PP_SIslands_PAPMParameters),
2300                                                           si_pi->sram_end);
2301                         if (ret)
2302                                 return ret;
2303                 }
2304         }
2305         return 0;
2306 }
2307
2308 static int si_populate_smc_tdp_limits_2(struct amdgpu_device *adev,
2309                                         struct amdgpu_ps *amdgpu_state)
2310 {
2311         struct ni_power_info *ni_pi = ni_get_pi(adev);
2312         struct si_power_info *si_pi = si_get_pi(adev);
2313
2314         if (ni_pi->enable_power_containment) {
2315                 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2316                 u32 scaling_factor = si_get_smc_power_scaling_factor(adev);
2317                 int ret;
2318
2319                 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2320
2321                 smc_table->dpm2Params.NearTDPLimit =
2322                         cpu_to_be32(si_scale_power_for_smc(adev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000);
2323                 smc_table->dpm2Params.SafePowerLimit =
2324                         cpu_to_be32(si_scale_power_for_smc((adev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2325
2326                 ret = amdgpu_si_copy_bytes_to_smc(adev,
2327                                                   (si_pi->state_table_start +
2328                                                    offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2329                                                    offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)),
2330                                                   (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)),
2331                                                   sizeof(u32) * 2,
2332                                                   si_pi->sram_end);
2333                 if (ret)
2334                         return ret;
2335         }
2336
2337         return 0;
2338 }
2339
2340 static u16 si_calculate_power_efficiency_ratio(struct amdgpu_device *adev,
2341                                                const u16 prev_std_vddc,
2342                                                const u16 curr_std_vddc)
2343 {
2344         u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN;
2345         u64 prev_vddc = (u64)prev_std_vddc;
2346         u64 curr_vddc = (u64)curr_std_vddc;
2347         u64 pwr_efficiency_ratio, n, d;
2348
2349         if ((prev_vddc == 0) || (curr_vddc == 0))
2350                 return 0;
2351
2352         n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000);
2353         d = prev_vddc * prev_vddc;
2354         pwr_efficiency_ratio = div64_u64(n, d);
2355
2356         if (pwr_efficiency_ratio > (u64)0xFFFF)
2357                 return 0;
2358
2359         return (u16)pwr_efficiency_ratio;
2360 }
2361
2362 static bool si_should_disable_uvd_powertune(struct amdgpu_device *adev,
2363                                             struct amdgpu_ps *amdgpu_state)
2364 {
2365         struct si_power_info *si_pi = si_get_pi(adev);
2366
2367         if (si_pi->dyn_powertune_data.disable_uvd_powertune &&
2368             amdgpu_state->vclk && amdgpu_state->dclk)
2369                 return true;
2370
2371         return false;
2372 }
2373
2374 struct evergreen_power_info *evergreen_get_pi(struct amdgpu_device *adev)
2375 {
2376         struct evergreen_power_info *pi = adev->pm.dpm.priv;
2377
2378         return pi;
2379 }
2380
2381 static int si_populate_power_containment_values(struct amdgpu_device *adev,
2382                                                 struct amdgpu_ps *amdgpu_state,
2383                                                 SISLANDS_SMC_SWSTATE *smc_state)
2384 {
2385         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
2386         struct ni_power_info *ni_pi = ni_get_pi(adev);
2387         struct  si_ps *state = si_get_ps(amdgpu_state);
2388         SISLANDS_SMC_VOLTAGE_VALUE vddc;
2389         u32 prev_sclk;
2390         u32 max_sclk;
2391         u32 min_sclk;
2392         u16 prev_std_vddc;
2393         u16 curr_std_vddc;
2394         int i;
2395         u16 pwr_efficiency_ratio;
2396         u8 max_ps_percent;
2397         bool disable_uvd_power_tune;
2398         int ret;
2399
2400         if (ni_pi->enable_power_containment == false)
2401                 return 0;
2402
2403         if (state->performance_level_count == 0)
2404                 return -EINVAL;
2405
2406         if (smc_state->levelCount != state->performance_level_count)
2407                 return -EINVAL;
2408
2409         disable_uvd_power_tune = si_should_disable_uvd_powertune(adev, amdgpu_state);
2410
2411         smc_state->levels[0].dpm2.MaxPS = 0;
2412         smc_state->levels[0].dpm2.NearTDPDec = 0;
2413         smc_state->levels[0].dpm2.AboveSafeInc = 0;
2414         smc_state->levels[0].dpm2.BelowSafeInc = 0;
2415         smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0;
2416
2417         for (i = 1; i < state->performance_level_count; i++) {
2418                 prev_sclk = state->performance_levels[i-1].sclk;
2419                 max_sclk  = state->performance_levels[i].sclk;
2420                 if (i == 1)
2421                         max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M;
2422                 else
2423                         max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H;
2424
2425                 if (prev_sclk > max_sclk)
2426                         return -EINVAL;
2427
2428                 if ((max_ps_percent == 0) ||
2429                     (prev_sclk == max_sclk) ||
2430                     disable_uvd_power_tune)
2431                         min_sclk = max_sclk;
2432                 else if (i == 1)
2433                         min_sclk = prev_sclk;
2434                 else
2435                         min_sclk = (prev_sclk * (u32)max_ps_percent) / 100;
2436
2437                 if (min_sclk < state->performance_levels[0].sclk)
2438                         min_sclk = state->performance_levels[0].sclk;
2439
2440                 if (min_sclk == 0)
2441                         return -EINVAL;
2442
2443                 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
2444                                                 state->performance_levels[i-1].vddc, &vddc);
2445                 if (ret)
2446                         return ret;
2447
2448                 ret = si_get_std_voltage_value(adev, &vddc, &prev_std_vddc);
2449                 if (ret)
2450                         return ret;
2451
2452                 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
2453                                                 state->performance_levels[i].vddc, &vddc);
2454                 if (ret)
2455                         return ret;
2456
2457                 ret = si_get_std_voltage_value(adev, &vddc, &curr_std_vddc);
2458                 if (ret)
2459                         return ret;
2460
2461                 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(adev,
2462                                                                            prev_std_vddc, curr_std_vddc);
2463
2464                 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);
2465                 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC;
2466                 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC;
2467                 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC;
2468                 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio);
2469         }
2470
2471         return 0;
2472 }
2473
2474 static int si_populate_sq_ramping_values(struct amdgpu_device *adev,
2475                                          struct amdgpu_ps *amdgpu_state,
2476                                          SISLANDS_SMC_SWSTATE *smc_state)
2477 {
2478         struct ni_power_info *ni_pi = ni_get_pi(adev);
2479         struct  si_ps *state = si_get_ps(amdgpu_state);
2480         u32 sq_power_throttle, sq_power_throttle2;
2481         bool enable_sq_ramping = ni_pi->enable_sq_ramping;
2482         int i;
2483
2484         if (state->performance_level_count == 0)
2485                 return -EINVAL;
2486
2487         if (smc_state->levelCount != state->performance_level_count)
2488                 return -EINVAL;
2489
2490         if (adev->pm.dpm.sq_ramping_threshold == 0)
2491                 return -EINVAL;
2492
2493         if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT))
2494                 enable_sq_ramping = false;
2495
2496         if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT))
2497                 enable_sq_ramping = false;
2498
2499         if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT))
2500                 enable_sq_ramping = false;
2501
2502         if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT))
2503                 enable_sq_ramping = false;
2504
2505         if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT))
2506                 enable_sq_ramping = false;
2507
2508         for (i = 0; i < state->performance_level_count; i++) {
2509                 sq_power_throttle = 0;
2510                 sq_power_throttle2 = 0;
2511
2512                 if ((state->performance_levels[i].sclk >= adev->pm.dpm.sq_ramping_threshold) &&
2513                     enable_sq_ramping) {
2514                         sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER);
2515                         sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER);
2516                         sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA);
2517                         sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE);
2518                         sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO);
2519                 } else {
2520                         sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK;
2521                         sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
2522                 }
2523
2524                 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle);
2525                 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2);
2526         }
2527
2528         return 0;
2529 }
2530
2531 static int si_enable_power_containment(struct amdgpu_device *adev,
2532                                        struct amdgpu_ps *amdgpu_new_state,
2533                                        bool enable)
2534 {
2535         struct ni_power_info *ni_pi = ni_get_pi(adev);
2536         PPSMC_Result smc_result;
2537         int ret = 0;
2538
2539         if (ni_pi->enable_power_containment) {
2540                 if (enable) {
2541                         if (!si_should_disable_uvd_powertune(adev, amdgpu_new_state)) {
2542                                 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_TDPClampingActive);
2543                                 if (smc_result != PPSMC_Result_OK) {
2544                                         ret = -EINVAL;
2545                                         ni_pi->pc_enabled = false;
2546                                 } else {
2547                                         ni_pi->pc_enabled = true;
2548                                 }
2549                         }
2550                 } else {
2551                         smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_TDPClampingInactive);
2552                         if (smc_result != PPSMC_Result_OK)
2553                                 ret = -EINVAL;
2554                         ni_pi->pc_enabled = false;
2555                 }
2556         }
2557
2558         return ret;
2559 }
2560
2561 static int si_initialize_smc_dte_tables(struct amdgpu_device *adev)
2562 {
2563         struct si_power_info *si_pi = si_get_pi(adev);
2564         int ret = 0;
2565         struct si_dte_data *dte_data = &si_pi->dte_data;
2566         Smc_SIslands_DTE_Configuration *dte_tables = NULL;
2567         u32 table_size;
2568         u8 tdep_count;
2569         u32 i;
2570
2571         if (dte_data == NULL)
2572                 si_pi->enable_dte = false;
2573
2574         if (si_pi->enable_dte == false)
2575                 return 0;
2576
2577         if (dte_data->k <= 0)
2578                 return -EINVAL;
2579
2580         dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL);
2581         if (dte_tables == NULL) {
2582                 si_pi->enable_dte = false;
2583                 return -ENOMEM;
2584         }
2585
2586         table_size = dte_data->k;
2587
2588         if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES)
2589                 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES;
2590
2591         tdep_count = dte_data->tdep_count;
2592         if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE)
2593                 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE;
2594
2595         dte_tables->K = cpu_to_be32(table_size);
2596         dte_tables->T0 = cpu_to_be32(dte_data->t0);
2597         dte_tables->MaxT = cpu_to_be32(dte_data->max_t);
2598         dte_tables->WindowSize = dte_data->window_size;
2599         dte_tables->temp_select = dte_data->temp_select;
2600         dte_tables->DTE_mode = dte_data->dte_mode;
2601         dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold);
2602
2603         if (tdep_count > 0)
2604                 table_size--;
2605
2606         for (i = 0; i < table_size; i++) {
2607                 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]);
2608                 dte_tables->R[i]   = cpu_to_be32(dte_data->r[i]);
2609         }
2610
2611         dte_tables->Tdep_count = tdep_count;
2612
2613         for (i = 0; i < (u32)tdep_count; i++) {
2614                 dte_tables->T_limits[i] = dte_data->t_limits[i];
2615                 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]);
2616                 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]);
2617         }
2618
2619         ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->dte_table_start,
2620                                           (u8 *)dte_tables,
2621                                           sizeof(Smc_SIslands_DTE_Configuration),
2622                                           si_pi->sram_end);
2623         kfree(dte_tables);
2624
2625         return ret;
2626 }
2627
2628 static int si_get_cac_std_voltage_max_min(struct amdgpu_device *adev,
2629                                           u16 *max, u16 *min)
2630 {
2631         struct si_power_info *si_pi = si_get_pi(adev);
2632         struct amdgpu_cac_leakage_table *table =
2633                 &adev->pm.dpm.dyn_state.cac_leakage_table;
2634         u32 i;
2635         u32 v0_loadline;
2636
2637         if (table == NULL)
2638                 return -EINVAL;
2639
2640         *max = 0;
2641         *min = 0xFFFF;
2642
2643         for (i = 0; i < table->count; i++) {
2644                 if (table->entries[i].vddc > *max)
2645                         *max = table->entries[i].vddc;
2646                 if (table->entries[i].vddc < *min)
2647                         *min = table->entries[i].vddc;
2648         }
2649
2650         if (si_pi->powertune_data->lkge_lut_v0_percent > 100)
2651                 return -EINVAL;
2652
2653         v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100;
2654
2655         if (v0_loadline > 0xFFFFUL)
2656                 return -EINVAL;
2657
2658         *min = (u16)v0_loadline;
2659
2660         if ((*min > *max) || (*max == 0) || (*min == 0))
2661                 return -EINVAL;
2662
2663         return 0;
2664 }
2665
2666 static u16 si_get_cac_std_voltage_step(u16 max, u16 min)
2667 {
2668         return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) /
2669                 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES;
2670 }
2671
2672 static int si_init_dte_leakage_table(struct amdgpu_device *adev,
2673                                      PP_SIslands_CacConfig *cac_tables,
2674                                      u16 vddc_max, u16 vddc_min, u16 vddc_step,
2675                                      u16 t0, u16 t_step)
2676 {
2677         struct si_power_info *si_pi = si_get_pi(adev);
2678         u32 leakage;
2679         unsigned int i, j;
2680         s32 t;
2681         u32 smc_leakage;
2682         u32 scaling_factor;
2683         u16 voltage;
2684
2685         scaling_factor = si_get_smc_power_scaling_factor(adev);
2686
2687         for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) {
2688                 t = (1000 * (i * t_step + t0));
2689
2690                 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2691                         voltage = vddc_max - (vddc_step * j);
2692
2693                         si_calculate_leakage_for_v_and_t(adev,
2694                                                          &si_pi->powertune_data->leakage_coefficients,
2695                                                          voltage,
2696                                                          t,
2697                                                          si_pi->dyn_powertune_data.cac_leakage,
2698                                                          &leakage);
2699
2700                         smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2701
2702                         if (smc_leakage > 0xFFFF)
2703                                 smc_leakage = 0xFFFF;
2704
2705                         cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2706                                 cpu_to_be16((u16)smc_leakage);
2707                 }
2708         }
2709         return 0;
2710 }
2711
2712 static int si_init_simplified_leakage_table(struct amdgpu_device *adev,
2713                                             PP_SIslands_CacConfig *cac_tables,
2714                                             u16 vddc_max, u16 vddc_min, u16 vddc_step)
2715 {
2716         struct si_power_info *si_pi = si_get_pi(adev);
2717         u32 leakage;
2718         unsigned int i, j;
2719         u32 smc_leakage;
2720         u32 scaling_factor;
2721         u16 voltage;
2722
2723         scaling_factor = si_get_smc_power_scaling_factor(adev);
2724
2725         for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2726                 voltage = vddc_max - (vddc_step * j);
2727
2728                 si_calculate_leakage_for_v(adev,
2729                                            &si_pi->powertune_data->leakage_coefficients,
2730                                            si_pi->powertune_data->fixed_kt,
2731                                            voltage,
2732                                            si_pi->dyn_powertune_data.cac_leakage,
2733                                            &leakage);
2734
2735                 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2736
2737                 if (smc_leakage > 0xFFFF)
2738                         smc_leakage = 0xFFFF;
2739
2740                 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++)
2741                         cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2742                                 cpu_to_be16((u16)smc_leakage);
2743         }
2744         return 0;
2745 }
2746
2747 static int si_initialize_smc_cac_tables(struct amdgpu_device *adev)
2748 {
2749         struct ni_power_info *ni_pi = ni_get_pi(adev);
2750         struct si_power_info *si_pi = si_get_pi(adev);
2751         PP_SIslands_CacConfig *cac_tables = NULL;
2752         u16 vddc_max, vddc_min, vddc_step;
2753         u16 t0, t_step;
2754         u32 load_line_slope, reg;
2755         int ret = 0;
2756         u32 ticks_per_us = amdgpu_asic_get_xclk(adev) / 100;
2757
2758         if (ni_pi->enable_cac == false)
2759                 return 0;
2760
2761         cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL);
2762         if (!cac_tables)
2763                 return -ENOMEM;
2764
2765         reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK;
2766         reg |= CAC_WINDOW(si_pi->powertune_data->cac_window);
2767         WREG32(CG_CAC_CTRL, reg);
2768
2769         si_pi->dyn_powertune_data.cac_leakage = adev->pm.dpm.cac_leakage;
2770         si_pi->dyn_powertune_data.dc_pwr_value =
2771                 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0];
2772         si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(adev);
2773         si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default;
2774
2775         si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000;
2776
2777         ret = si_get_cac_std_voltage_max_min(adev, &vddc_max, &vddc_min);
2778         if (ret)
2779                 goto done_free;
2780
2781         vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min);
2782         vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1));
2783         t_step = 4;
2784         t0 = 60;
2785
2786         if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage)
2787                 ret = si_init_dte_leakage_table(adev, cac_tables,
2788                                                 vddc_max, vddc_min, vddc_step,
2789                                                 t0, t_step);
2790         else
2791                 ret = si_init_simplified_leakage_table(adev, cac_tables,
2792                                                        vddc_max, vddc_min, vddc_step);
2793         if (ret)
2794                 goto done_free;
2795
2796         load_line_slope = ((u32)adev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100;
2797
2798         cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size);
2799         cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate;
2800         cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n;
2801         cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min);
2802         cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step);
2803         cac_tables->R_LL = cpu_to_be32(load_line_slope);
2804         cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime);
2805         cac_tables->calculation_repeats = cpu_to_be32(2);
2806         cac_tables->dc_cac = cpu_to_be32(0);
2807         cac_tables->log2_PG_LKG_SCALE = 12;
2808         cac_tables->cac_temp = si_pi->powertune_data->operating_temp;
2809         cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0);
2810         cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step);
2811
2812         ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->cac_table_start,
2813                                           (u8 *)cac_tables,
2814                                           sizeof(PP_SIslands_CacConfig),
2815                                           si_pi->sram_end);
2816
2817         if (ret)
2818                 goto done_free;
2819
2820         ret = si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us);
2821
2822 done_free:
2823         if (ret) {
2824                 ni_pi->enable_cac = false;
2825                 ni_pi->enable_power_containment = false;
2826         }
2827
2828         kfree(cac_tables);
2829
2830         return ret;
2831 }
2832
2833 static int si_program_cac_config_registers(struct amdgpu_device *adev,
2834                                            const struct si_cac_config_reg *cac_config_regs)
2835 {
2836         const struct si_cac_config_reg *config_regs = cac_config_regs;
2837         u32 data = 0, offset;
2838
2839         if (!config_regs)
2840                 return -EINVAL;
2841
2842         while (config_regs->offset != 0xFFFFFFFF) {
2843                 switch (config_regs->type) {
2844                 case SISLANDS_CACCONFIG_CGIND:
2845                         offset = SMC_CG_IND_START + config_regs->offset;
2846                         if (offset < SMC_CG_IND_END)
2847                                 data = RREG32_SMC(offset);
2848                         break;
2849                 default:
2850                         data = RREG32(config_regs->offset);
2851                         break;
2852                 }
2853
2854                 data &= ~config_regs->mask;
2855                 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
2856
2857                 switch (config_regs->type) {
2858                 case SISLANDS_CACCONFIG_CGIND:
2859                         offset = SMC_CG_IND_START + config_regs->offset;
2860                         if (offset < SMC_CG_IND_END)
2861                                 WREG32_SMC(offset, data);
2862                         break;
2863                 default:
2864                         WREG32(config_regs->offset, data);
2865                         break;
2866                 }
2867                 config_regs++;
2868         }
2869         return 0;
2870 }
2871
2872 static int si_initialize_hardware_cac_manager(struct amdgpu_device *adev)
2873 {
2874         struct ni_power_info *ni_pi = ni_get_pi(adev);
2875         struct si_power_info *si_pi = si_get_pi(adev);
2876         int ret;
2877
2878         if ((ni_pi->enable_cac == false) ||
2879             (ni_pi->cac_configuration_required == false))
2880                 return 0;
2881
2882         ret = si_program_cac_config_registers(adev, si_pi->lcac_config);
2883         if (ret)
2884                 return ret;
2885         ret = si_program_cac_config_registers(adev, si_pi->cac_override);
2886         if (ret)
2887                 return ret;
2888         ret = si_program_cac_config_registers(adev, si_pi->cac_weights);
2889         if (ret)
2890                 return ret;
2891
2892         return 0;
2893 }
2894
2895 static int si_enable_smc_cac(struct amdgpu_device *adev,
2896                              struct amdgpu_ps *amdgpu_new_state,
2897                              bool enable)
2898 {
2899         struct ni_power_info *ni_pi = ni_get_pi(adev);
2900         struct si_power_info *si_pi = si_get_pi(adev);
2901         PPSMC_Result smc_result;
2902         int ret = 0;
2903
2904         if (ni_pi->enable_cac) {
2905                 if (enable) {
2906                         if (!si_should_disable_uvd_powertune(adev, amdgpu_new_state)) {
2907                                 if (ni_pi->support_cac_long_term_average) {
2908                                         smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgEnable);
2909                                         if (smc_result != PPSMC_Result_OK)
2910                                                 ni_pi->support_cac_long_term_average = false;
2911                                 }
2912
2913                                 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableCac);
2914                                 if (smc_result != PPSMC_Result_OK) {
2915                                         ret = -EINVAL;
2916                                         ni_pi->cac_enabled = false;
2917                                 } else {
2918                                         ni_pi->cac_enabled = true;
2919                                 }
2920
2921                                 if (si_pi->enable_dte) {
2922                                         smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableDTE);
2923                                         if (smc_result != PPSMC_Result_OK)
2924                                                 ret = -EINVAL;
2925                                 }
2926                         }
2927                 } else if (ni_pi->cac_enabled) {
2928                         if (si_pi->enable_dte)
2929                                 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableDTE);
2930
2931                         smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableCac);
2932
2933                         ni_pi->cac_enabled = false;
2934
2935                         if (ni_pi->support_cac_long_term_average)
2936                                 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgDisable);
2937                 }
2938         }
2939         return ret;
2940 }
2941
2942 static int si_init_smc_spll_table(struct amdgpu_device *adev)
2943 {
2944         struct ni_power_info *ni_pi = ni_get_pi(adev);
2945         struct si_power_info *si_pi = si_get_pi(adev);
2946         SMC_SISLANDS_SPLL_DIV_TABLE *spll_table;
2947         SISLANDS_SMC_SCLK_VALUE sclk_params;
2948         u32 fb_div, p_div;
2949         u32 clk_s, clk_v;
2950         u32 sclk = 0;
2951         int ret = 0;
2952         u32 tmp;
2953         int i;
2954
2955         if (si_pi->spll_table_start == 0)
2956                 return -EINVAL;
2957
2958         spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL);
2959         if (spll_table == NULL)
2960                 return -ENOMEM;
2961
2962         for (i = 0; i < 256; i++) {
2963                 ret = si_calculate_sclk_params(adev, sclk, &sclk_params);
2964                 if (ret)
2965                         break;
2966                 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT;
2967                 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
2968                 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT;
2969                 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT;
2970
2971                 fb_div &= ~0x00001FFF;
2972                 fb_div >>= 1;
2973                 clk_v >>= 6;
2974
2975                 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT))
2976                         ret = -EINVAL;
2977                 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT))
2978                         ret = -EINVAL;
2979                 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT))
2980                         ret = -EINVAL;
2981                 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT))
2982                         ret = -EINVAL;
2983
2984                 if (ret)
2985                         break;
2986
2987                 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) |
2988                         ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK);
2989                 spll_table->freq[i] = cpu_to_be32(tmp);
2990
2991                 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) |
2992                         ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK);
2993                 spll_table->ss[i] = cpu_to_be32(tmp);
2994
2995                 sclk += 512;
2996         }
2997
2998
2999         if (!ret)
3000                 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->spll_table_start,
3001                                                   (u8 *)spll_table,
3002                                                   sizeof(SMC_SISLANDS_SPLL_DIV_TABLE),
3003                                                   si_pi->sram_end);
3004
3005         if (ret)
3006                 ni_pi->enable_power_containment = false;
3007
3008         kfree(spll_table);
3009
3010         return ret;
3011 }
3012
3013 static u16 si_get_lower_of_leakage_and_vce_voltage(struct amdgpu_device *adev,
3014                                                    u16 vce_voltage)
3015 {
3016         u16 highest_leakage = 0;
3017         struct si_power_info *si_pi = si_get_pi(adev);
3018         int i;
3019
3020         for (i = 0; i < si_pi->leakage_voltage.count; i++){
3021                 if (highest_leakage < si_pi->leakage_voltage.entries[i].voltage)
3022                         highest_leakage = si_pi->leakage_voltage.entries[i].voltage;
3023         }
3024
3025         if (si_pi->leakage_voltage.count && (highest_leakage < vce_voltage))
3026                 return highest_leakage;
3027
3028         return vce_voltage;
3029 }
3030
3031 static int si_get_vce_clock_voltage(struct amdgpu_device *adev,
3032                                     u32 evclk, u32 ecclk, u16 *voltage)
3033 {
3034         u32 i;
3035         int ret = -EINVAL;
3036         struct amdgpu_vce_clock_voltage_dependency_table *table =
3037                 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
3038
3039         if (((evclk == 0) && (ecclk == 0)) ||
3040             (table && (table->count == 0))) {
3041                 *voltage = 0;
3042                 return 0;
3043         }
3044
3045         for (i = 0; i < table->count; i++) {
3046                 if ((evclk <= table->entries[i].evclk) &&
3047                     (ecclk <= table->entries[i].ecclk)) {
3048                         *voltage = table->entries[i].v;
3049                         ret = 0;
3050                         break;
3051                 }
3052         }
3053
3054         /* if no match return the highest voltage */
3055         if (ret)
3056                 *voltage = table->entries[table->count - 1].v;
3057
3058         *voltage = si_get_lower_of_leakage_and_vce_voltage(adev, *voltage);
3059
3060         return ret;
3061 }
3062
3063 static bool si_dpm_vblank_too_short(void *handle)
3064 {
3065         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3066         u32 vblank_time = amdgpu_dpm_get_vblank_time(adev);
3067         /* we never hit the non-gddr5 limit so disable it */
3068         u32 switch_limit = adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 0;
3069
3070         if (vblank_time < switch_limit)
3071                 return true;
3072         else
3073                 return false;
3074
3075 }
3076
3077 static int ni_copy_and_switch_arb_sets(struct amdgpu_device *adev,
3078                                 u32 arb_freq_src, u32 arb_freq_dest)
3079 {
3080         u32 mc_arb_dram_timing;
3081         u32 mc_arb_dram_timing2;
3082         u32 burst_time;
3083         u32 mc_cg_config;
3084
3085         switch (arb_freq_src) {
3086         case MC_CG_ARB_FREQ_F0:
3087                 mc_arb_dram_timing  = RREG32(MC_ARB_DRAM_TIMING);
3088                 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
3089                 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE0_MASK) >> STATE0_SHIFT;
3090                 break;
3091         case MC_CG_ARB_FREQ_F1:
3092                 mc_arb_dram_timing  = RREG32(MC_ARB_DRAM_TIMING_1);
3093                 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_1);
3094                 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE1_MASK) >> STATE1_SHIFT;
3095                 break;
3096         case MC_CG_ARB_FREQ_F2:
3097                 mc_arb_dram_timing  = RREG32(MC_ARB_DRAM_TIMING_2);
3098                 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_2);
3099                 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE2_MASK) >> STATE2_SHIFT;
3100                 break;
3101         case MC_CG_ARB_FREQ_F3:
3102                 mc_arb_dram_timing  = RREG32(MC_ARB_DRAM_TIMING_3);
3103                 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_3);
3104                 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE3_MASK) >> STATE3_SHIFT;
3105                 break;
3106         default:
3107                 return -EINVAL;
3108         }
3109
3110         switch (arb_freq_dest) {
3111         case MC_CG_ARB_FREQ_F0:
3112                 WREG32(MC_ARB_DRAM_TIMING, mc_arb_dram_timing);
3113                 WREG32(MC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
3114                 WREG32_P(MC_ARB_BURST_TIME, STATE0(burst_time), ~STATE0_MASK);
3115                 break;
3116         case MC_CG_ARB_FREQ_F1:
3117                 WREG32(MC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
3118                 WREG32(MC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
3119                 WREG32_P(MC_ARB_BURST_TIME, STATE1(burst_time), ~STATE1_MASK);
3120                 break;
3121         case MC_CG_ARB_FREQ_F2:
3122                 WREG32(MC_ARB_DRAM_TIMING_2, mc_arb_dram_timing);
3123                 WREG32(MC_ARB_DRAM_TIMING2_2, mc_arb_dram_timing2);
3124                 WREG32_P(MC_ARB_BURST_TIME, STATE2(burst_time), ~STATE2_MASK);
3125                 break;
3126         case MC_CG_ARB_FREQ_F3:
3127                 WREG32(MC_ARB_DRAM_TIMING_3, mc_arb_dram_timing);
3128                 WREG32(MC_ARB_DRAM_TIMING2_3, mc_arb_dram_timing2);
3129                 WREG32_P(MC_ARB_BURST_TIME, STATE3(burst_time), ~STATE3_MASK);
3130                 break;
3131         default:
3132                 return -EINVAL;
3133         }
3134
3135         mc_cg_config = RREG32(MC_CG_CONFIG) | 0x0000000F;
3136         WREG32(MC_CG_CONFIG, mc_cg_config);
3137         WREG32_P(MC_ARB_CG, CG_ARB_REQ(arb_freq_dest), ~CG_ARB_REQ_MASK);
3138
3139         return 0;
3140 }
3141
3142 static void ni_update_current_ps(struct amdgpu_device *adev,
3143                           struct amdgpu_ps *rps)
3144 {
3145         struct si_ps *new_ps = si_get_ps(rps);
3146         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
3147         struct ni_power_info *ni_pi = ni_get_pi(adev);
3148
3149         eg_pi->current_rps = *rps;
3150         ni_pi->current_ps = *new_ps;
3151         eg_pi->current_rps.ps_priv = &ni_pi->current_ps;
3152         adev->pm.dpm.current_ps = &eg_pi->current_rps;
3153 }
3154
3155 static void ni_update_requested_ps(struct amdgpu_device *adev,
3156                             struct amdgpu_ps *rps)
3157 {
3158         struct si_ps *new_ps = si_get_ps(rps);
3159         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
3160         struct ni_power_info *ni_pi = ni_get_pi(adev);
3161
3162         eg_pi->requested_rps = *rps;
3163         ni_pi->requested_ps = *new_ps;
3164         eg_pi->requested_rps.ps_priv = &ni_pi->requested_ps;
3165         adev->pm.dpm.requested_ps = &eg_pi->requested_rps;
3166 }
3167
3168 static void ni_set_uvd_clock_before_set_eng_clock(struct amdgpu_device *adev,
3169                                            struct amdgpu_ps *new_ps,
3170                                            struct amdgpu_ps *old_ps)
3171 {
3172         struct si_ps *new_state = si_get_ps(new_ps);
3173         struct si_ps *current_state = si_get_ps(old_ps);
3174
3175         if ((new_ps->vclk == old_ps->vclk) &&
3176             (new_ps->dclk == old_ps->dclk))
3177                 return;
3178
3179         if (new_state->performance_levels[new_state->performance_level_count - 1].sclk >=
3180             current_state->performance_levels[current_state->performance_level_count - 1].sclk)
3181                 return;
3182
3183         amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk);
3184 }
3185
3186 static void ni_set_uvd_clock_after_set_eng_clock(struct amdgpu_device *adev,
3187                                           struct amdgpu_ps *new_ps,
3188                                           struct amdgpu_ps *old_ps)
3189 {
3190         struct si_ps *new_state = si_get_ps(new_ps);
3191         struct si_ps *current_state = si_get_ps(old_ps);
3192
3193         if ((new_ps->vclk == old_ps->vclk) &&
3194             (new_ps->dclk == old_ps->dclk))
3195                 return;
3196
3197         if (new_state->performance_levels[new_state->performance_level_count - 1].sclk <
3198             current_state->performance_levels[current_state->performance_level_count - 1].sclk)
3199                 return;
3200
3201         amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk);
3202 }
3203
3204 static u16 btc_find_voltage(struct atom_voltage_table *table, u16 voltage)
3205 {
3206         unsigned int i;
3207
3208         for (i = 0; i < table->count; i++)
3209                 if (voltage <= table->entries[i].value)
3210                         return table->entries[i].value;
3211
3212         return table->entries[table->count - 1].value;
3213 }
3214
3215 static u32 btc_find_valid_clock(struct amdgpu_clock_array *clocks,
3216                                 u32 max_clock, u32 requested_clock)
3217 {
3218         unsigned int i;
3219
3220         if ((clocks == NULL) || (clocks->count == 0))
3221                 return (requested_clock < max_clock) ? requested_clock : max_clock;
3222
3223         for (i = 0; i < clocks->count; i++) {
3224                 if (clocks->values[i] >= requested_clock)
3225                         return (clocks->values[i] < max_clock) ? clocks->values[i] : max_clock;
3226         }
3227
3228         return (clocks->values[clocks->count - 1] < max_clock) ?
3229                 clocks->values[clocks->count - 1] : max_clock;
3230 }
3231
3232 static u32 btc_get_valid_mclk(struct amdgpu_device *adev,
3233                               u32 max_mclk, u32 requested_mclk)
3234 {
3235         return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_mclk_values,
3236                                     max_mclk, requested_mclk);
3237 }
3238
3239 static u32 btc_get_valid_sclk(struct amdgpu_device *adev,
3240                               u32 max_sclk, u32 requested_sclk)
3241 {
3242         return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_sclk_values,
3243                                     max_sclk, requested_sclk);
3244 }
3245
3246 static void btc_get_max_clock_from_voltage_dependency_table(struct amdgpu_clock_voltage_dependency_table *table,
3247                                                             u32 *max_clock)
3248 {
3249         u32 i, clock = 0;
3250
3251         if ((table == NULL) || (table->count == 0)) {
3252                 *max_clock = clock;
3253                 return;
3254         }
3255
3256         for (i = 0; i < table->count; i++) {
3257                 if (clock < table->entries[i].clk)
3258                         clock = table->entries[i].clk;
3259         }
3260         *max_clock = clock;
3261 }
3262
3263 static void btc_apply_voltage_dependency_rules(struct amdgpu_clock_voltage_dependency_table *table,
3264                                                u32 clock, u16 max_voltage, u16 *voltage)
3265 {
3266         u32 i;
3267
3268         if ((table == NULL) || (table->count == 0))
3269                 return;
3270
3271         for (i= 0; i < table->count; i++) {
3272                 if (clock <= table->entries[i].clk) {
3273                         if (*voltage < table->entries[i].v)
3274                                 *voltage = (u16)((table->entries[i].v < max_voltage) ?
3275                                            table->entries[i].v : max_voltage);
3276                         return;
3277                 }
3278         }
3279
3280         *voltage = (*voltage > max_voltage) ? *voltage : max_voltage;
3281 }
3282
3283 static void btc_adjust_clock_combinations(struct amdgpu_device *adev,
3284                                           const struct amdgpu_clock_and_voltage_limits *max_limits,
3285                                           struct rv7xx_pl *pl)
3286 {
3287
3288         if ((pl->mclk == 0) || (pl->sclk == 0))
3289                 return;
3290
3291         if (pl->mclk == pl->sclk)
3292                 return;
3293
3294         if (pl->mclk > pl->sclk) {
3295                 if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) > adev->pm.dpm.dyn_state.mclk_sclk_ratio)
3296                         pl->sclk = btc_get_valid_sclk(adev,
3297                                                       max_limits->sclk,
3298                                                       (pl->mclk +
3299                                                       (adev->pm.dpm.dyn_state.mclk_sclk_ratio - 1)) /
3300                                                       adev->pm.dpm.dyn_state.mclk_sclk_ratio);
3301         } else {
3302                 if ((pl->sclk - pl->mclk) > adev->pm.dpm.dyn_state.sclk_mclk_delta)
3303                         pl->mclk = btc_get_valid_mclk(adev,
3304                                                       max_limits->mclk,
3305                                                       pl->sclk -
3306                                                       adev->pm.dpm.dyn_state.sclk_mclk_delta);
3307         }
3308 }
3309
3310 static void btc_apply_voltage_delta_rules(struct amdgpu_device *adev,
3311                                           u16 max_vddc, u16 max_vddci,
3312                                           u16 *vddc, u16 *vddci)
3313 {
3314         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
3315         u16 new_voltage;
3316
3317         if ((0 == *vddc) || (0 == *vddci))
3318                 return;
3319
3320         if (*vddc > *vddci) {
3321                 if ((*vddc - *vddci) > adev->pm.dpm.dyn_state.vddc_vddci_delta) {
3322                         new_voltage = btc_find_voltage(&eg_pi->vddci_voltage_table,
3323                                                        (*vddc - adev->pm.dpm.dyn_state.vddc_vddci_delta));
3324                         *vddci = (new_voltage < max_vddci) ? new_voltage : max_vddci;
3325                 }
3326         } else {
3327                 if ((*vddci - *vddc) > adev->pm.dpm.dyn_state.vddc_vddci_delta) {
3328                         new_voltage = btc_find_voltage(&eg_pi->vddc_voltage_table,
3329                                                        (*vddci - adev->pm.dpm.dyn_state.vddc_vddci_delta));
3330                         *vddc = (new_voltage < max_vddc) ? new_voltage : max_vddc;
3331                 }
3332         }
3333 }
3334
3335 static enum amdgpu_pcie_gen r600_get_pcie_gen_support(struct amdgpu_device *adev,
3336                                                u32 sys_mask,
3337                                                enum amdgpu_pcie_gen asic_gen,
3338                                                enum amdgpu_pcie_gen default_gen)
3339 {
3340         switch (asic_gen) {
3341         case AMDGPU_PCIE_GEN1:
3342                 return AMDGPU_PCIE_GEN1;
3343         case AMDGPU_PCIE_GEN2:
3344                 return AMDGPU_PCIE_GEN2;
3345         case AMDGPU_PCIE_GEN3:
3346                 return AMDGPU_PCIE_GEN3;
3347         default:
3348                 if ((sys_mask & DRM_PCIE_SPEED_80) && (default_gen == AMDGPU_PCIE_GEN3))
3349                         return AMDGPU_PCIE_GEN3;
3350                 else if ((sys_mask & DRM_PCIE_SPEED_50) && (default_gen == AMDGPU_PCIE_GEN2))
3351                         return AMDGPU_PCIE_GEN2;
3352                 else
3353                         return AMDGPU_PCIE_GEN1;
3354         }
3355         return AMDGPU_PCIE_GEN1;
3356 }
3357
3358 static void r600_calculate_u_and_p(u32 i, u32 r_c, u32 p_b,
3359                             u32 *p, u32 *u)
3360 {
3361         u32 b_c = 0;
3362         u32 i_c;
3363         u32 tmp;
3364
3365         i_c = (i * r_c) / 100;
3366         tmp = i_c >> p_b;
3367
3368         while (tmp) {
3369                 b_c++;
3370                 tmp >>= 1;
3371         }
3372
3373         *u = (b_c + 1) / 2;
3374         *p = i_c / (1 << (2 * (*u)));
3375 }
3376
3377 static int r600_calculate_at(u32 t, u32 h, u32 fh, u32 fl, u32 *tl, u32 *th)
3378 {
3379         u32 k, a, ah, al;
3380         u32 t1;
3381
3382         if ((fl == 0) || (fh == 0) || (fl > fh))
3383                 return -EINVAL;
3384
3385         k = (100 * fh) / fl;
3386         t1 = (t * (k - 100));
3387         a = (1000 * (100 * h + t1)) / (10000 + (t1 / 100));
3388         a = (a + 5) / 10;
3389         ah = ((a * t) + 5000) / 10000;
3390         al = a - ah;
3391
3392         *th = t - ah;
3393         *tl = t + al;
3394
3395         return 0;
3396 }
3397
3398 static bool r600_is_uvd_state(u32 class, u32 class2)
3399 {
3400         if (class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
3401                 return true;
3402         if (class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
3403                 return true;
3404         if (class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
3405                 return true;
3406         if (class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
3407                 return true;
3408         if (class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
3409                 return true;
3410         return false;
3411 }
3412
3413 static u8 rv770_get_memory_module_index(struct amdgpu_device *adev)
3414 {
3415         return (u8) ((RREG32(BIOS_SCRATCH_4) >> 16) & 0xff);
3416 }
3417
3418 static void rv770_get_max_vddc(struct amdgpu_device *adev)
3419 {
3420         struct rv7xx_power_info *pi = rv770_get_pi(adev);
3421         u16 vddc;
3422
3423         if (amdgpu_atombios_get_max_vddc(adev, 0, 0, &vddc))
3424                 pi->max_vddc = 0;
3425         else
3426                 pi->max_vddc = vddc;
3427 }
3428
3429 static void rv770_get_engine_memory_ss(struct amdgpu_device *adev)
3430 {
3431         struct rv7xx_power_info *pi = rv770_get_pi(adev);
3432         struct amdgpu_atom_ss ss;
3433
3434         pi->sclk_ss = amdgpu_atombios_get_asic_ss_info(adev, &ss,
3435                                                        ASIC_INTERNAL_ENGINE_SS, 0);
3436         pi->mclk_ss = amdgpu_atombios_get_asic_ss_info(adev, &ss,
3437                                                        ASIC_INTERNAL_MEMORY_SS, 0);
3438
3439         if (pi->sclk_ss || pi->mclk_ss)
3440                 pi->dynamic_ss = true;
3441         else
3442                 pi->dynamic_ss = false;
3443 }
3444
3445
3446 static void si_apply_state_adjust_rules(struct amdgpu_device *adev,
3447                                         struct amdgpu_ps *rps)
3448 {
3449         struct  si_ps *ps = si_get_ps(rps);
3450         struct amdgpu_clock_and_voltage_limits *max_limits;
3451         bool disable_mclk_switching = false;
3452         bool disable_sclk_switching = false;
3453         u32 mclk, sclk;
3454         u16 vddc, vddci, min_vce_voltage = 0;
3455         u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
3456         u32 max_sclk = 0, max_mclk = 0;
3457         int i;
3458
3459         if (adev->asic_type == CHIP_HAINAN) {
3460                 if ((adev->pdev->revision == 0x81) ||
3461                     (adev->pdev->revision == 0x83) ||
3462                     (adev->pdev->revision == 0xC3) ||
3463                     (adev->pdev->device == 0x6664) ||
3464                     (adev->pdev->device == 0x6665) ||
3465                     (adev->pdev->device == 0x6667)) {
3466                         max_sclk = 75000;
3467                 }
3468         } else if (adev->asic_type == CHIP_OLAND) {
3469                 if ((adev->pdev->revision == 0xC7) ||
3470                     (adev->pdev->revision == 0x80) ||
3471                     (adev->pdev->revision == 0x81) ||
3472                     (adev->pdev->revision == 0x83) ||
3473                     (adev->pdev->revision == 0x87) ||
3474                     (adev->pdev->device == 0x6604) ||
3475                     (adev->pdev->device == 0x6605)) {
3476                         max_sclk = 75000;
3477                 }
3478         }
3479
3480         if (rps->vce_active) {
3481                 rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk;
3482                 rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk;
3483                 si_get_vce_clock_voltage(adev, rps->evclk, rps->ecclk,
3484                                          &min_vce_voltage);
3485         } else {
3486                 rps->evclk = 0;
3487                 rps->ecclk = 0;
3488         }
3489
3490         if ((adev->pm.dpm.new_active_crtc_count > 1) ||
3491             si_dpm_vblank_too_short(adev))
3492                 disable_mclk_switching = true;
3493
3494         if (rps->vclk || rps->dclk) {
3495                 disable_mclk_switching = true;
3496                 disable_sclk_switching = true;
3497         }
3498
3499         if (adev->pm.dpm.ac_power)
3500                 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3501         else
3502                 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3503
3504         for (i = ps->performance_level_count - 2; i >= 0; i--) {
3505                 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc)
3506                         ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc;
3507         }
3508         if (adev->pm.dpm.ac_power == false) {
3509                 for (i = 0; i < ps->performance_level_count; i++) {
3510                         if (ps->performance_levels[i].mclk > max_limits->mclk)
3511                                 ps->performance_levels[i].mclk = max_limits->mclk;
3512                         if (ps->performance_levels[i].sclk > max_limits->sclk)
3513                                 ps->performance_levels[i].sclk = max_limits->sclk;
3514                         if (ps->performance_levels[i].vddc > max_limits->vddc)
3515                                 ps->performance_levels[i].vddc = max_limits->vddc;
3516                         if (ps->performance_levels[i].vddci > max_limits->vddci)
3517                                 ps->performance_levels[i].vddci = max_limits->vddci;
3518                 }
3519         }
3520
3521         /* limit clocks to max supported clocks based on voltage dependency tables */
3522         btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3523                                                         &max_sclk_vddc);
3524         btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3525                                                         &max_mclk_vddci);
3526         btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3527                                                         &max_mclk_vddc);
3528
3529         for (i = 0; i < ps->performance_level_count; i++) {
3530                 if (max_sclk_vddc) {
3531                         if (ps->performance_levels[i].sclk > max_sclk_vddc)
3532                                 ps->performance_levels[i].sclk = max_sclk_vddc;
3533                 }
3534                 if (max_mclk_vddci) {
3535                         if (ps->performance_levels[i].mclk > max_mclk_vddci)
3536                                 ps->performance_levels[i].mclk = max_mclk_vddci;
3537                 }
3538                 if (max_mclk_vddc) {
3539                         if (ps->performance_levels[i].mclk > max_mclk_vddc)
3540                                 ps->performance_levels[i].mclk = max_mclk_vddc;
3541                 }
3542                 if (max_mclk) {
3543                         if (ps->performance_levels[i].mclk > max_mclk)
3544                                 ps->performance_levels[i].mclk = max_mclk;
3545                 }
3546                 if (max_sclk) {
3547                         if (ps->performance_levels[i].sclk > max_sclk)
3548                                 ps->performance_levels[i].sclk = max_sclk;
3549                 }
3550         }
3551
3552         /* XXX validate the min clocks required for display */
3553
3554         if (disable_mclk_switching) {
3555                 mclk  = ps->performance_levels[ps->performance_level_count - 1].mclk;
3556                 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci;
3557         } else {
3558                 mclk = ps->performance_levels[0].mclk;
3559                 vddci = ps->performance_levels[0].vddci;
3560         }
3561
3562         if (disable_sclk_switching) {
3563                 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk;
3564                 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc;
3565         } else {
3566                 sclk = ps->performance_levels[0].sclk;
3567                 vddc = ps->performance_levels[0].vddc;
3568         }
3569
3570         if (rps->vce_active) {
3571                 if (sclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk)
3572                         sclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk;
3573                 if (mclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk)
3574                         mclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk;
3575         }
3576
3577         /* adjusted low state */
3578         ps->performance_levels[0].sclk = sclk;
3579         ps->performance_levels[0].mclk = mclk;
3580         ps->performance_levels[0].vddc = vddc;
3581         ps->performance_levels[0].vddci = vddci;
3582
3583         if (disable_sclk_switching) {
3584                 sclk = ps->performance_levels[0].sclk;
3585                 for (i = 1; i < ps->performance_level_count; i++) {
3586                         if (sclk < ps->performance_levels[i].sclk)
3587                                 sclk = ps->performance_levels[i].sclk;
3588                 }
3589                 for (i = 0; i < ps->performance_level_count; i++) {
3590                         ps->performance_levels[i].sclk = sclk;
3591                         ps->performance_levels[i].vddc = vddc;
3592                 }
3593         } else {
3594                 for (i = 1; i < ps->performance_level_count; i++) {
3595                         if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk)
3596                                 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk;
3597                         if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc)
3598                                 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc;
3599                 }
3600         }
3601
3602         if (disable_mclk_switching) {
3603                 mclk = ps->performance_levels[0].mclk;
3604                 for (i = 1; i < ps->performance_level_count; i++) {
3605                         if (mclk < ps->performance_levels[i].mclk)
3606                                 mclk = ps->performance_levels[i].mclk;
3607                 }
3608                 for (i = 0; i < ps->performance_level_count; i++) {
3609                         ps->performance_levels[i].mclk = mclk;
3610                         ps->performance_levels[i].vddci = vddci;
3611                 }
3612         } else {
3613                 for (i = 1; i < ps->performance_level_count; i++) {
3614                         if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk)
3615                                 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk;
3616                         if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci)
3617                                 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci;
3618                 }
3619         }
3620
3621         for (i = 0; i < ps->performance_level_count; i++)
3622                 btc_adjust_clock_combinations(adev, max_limits,
3623                                               &ps->performance_levels[i]);
3624
3625         for (i = 0; i < ps->performance_level_count; i++) {
3626                 if (ps->performance_levels[i].vddc < min_vce_voltage)
3627                         ps->performance_levels[i].vddc = min_vce_voltage;
3628                 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3629                                                    ps->performance_levels[i].sclk,
3630                                                    max_limits->vddc,  &ps->performance_levels[i].vddc);
3631                 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3632                                                    ps->performance_levels[i].mclk,
3633                                                    max_limits->vddci, &ps->performance_levels[i].vddci);
3634                 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3635                                                    ps->performance_levels[i].mclk,
3636                                                    max_limits->vddc,  &ps->performance_levels[i].vddc);
3637                 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,
3638                                                    adev->clock.current_dispclk,
3639                                                    max_limits->vddc,  &ps->performance_levels[i].vddc);
3640         }
3641
3642         for (i = 0; i < ps->performance_level_count; i++) {
3643                 btc_apply_voltage_delta_rules(adev,
3644                                               max_limits->vddc, max_limits->vddci,
3645                                               &ps->performance_levels[i].vddc,
3646                                               &ps->performance_levels[i].vddci);
3647         }
3648
3649         ps->dc_compatible = true;
3650         for (i = 0; i < ps->performance_level_count; i++) {
3651                 if (ps->performance_levels[i].vddc > adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc)
3652                         ps->dc_compatible = false;
3653         }
3654 }
3655
3656 #if 0
3657 static int si_read_smc_soft_register(struct amdgpu_device *adev,
3658                                      u16 reg_offset, u32 *value)
3659 {
3660         struct si_power_info *si_pi = si_get_pi(adev);
3661
3662         return amdgpu_si_read_smc_sram_dword(adev,
3663                                              si_pi->soft_regs_start + reg_offset, value,
3664                                              si_pi->sram_end);
3665 }
3666 #endif
3667
3668 static int si_write_smc_soft_register(struct amdgpu_device *adev,
3669                                       u16 reg_offset, u32 value)
3670 {
3671         struct si_power_info *si_pi = si_get_pi(adev);
3672
3673         return amdgpu_si_write_smc_sram_dword(adev,
3674                                               si_pi->soft_regs_start + reg_offset,
3675                                               value, si_pi->sram_end);
3676 }
3677
3678 static bool si_is_special_1gb_platform(struct amdgpu_device *adev)
3679 {
3680         bool ret = false;
3681         u32 tmp, width, row, column, bank, density;
3682         bool is_memory_gddr5, is_special;
3683
3684         tmp = RREG32(MC_SEQ_MISC0);
3685         is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT));
3686         is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT))
3687                 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT));
3688
3689         WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb);
3690         width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32;
3691
3692         tmp = RREG32(MC_ARB_RAMCFG);
3693         row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10;
3694         column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8;
3695         bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2;
3696
3697         density = (1 << (row + column - 20 + bank)) * width;
3698
3699         if ((adev->pdev->device == 0x6819) &&
3700             is_memory_gddr5 && is_special && (density == 0x400))
3701                 ret = true;
3702
3703         return ret;
3704 }
3705
3706 static void si_get_leakage_vddc(struct amdgpu_device *adev)
3707 {
3708         struct si_power_info *si_pi = si_get_pi(adev);
3709         u16 vddc, count = 0;
3710         int i, ret;
3711
3712         for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) {
3713                 ret = amdgpu_atombios_get_leakage_vddc_based_on_leakage_idx(adev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i);
3714
3715                 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) {
3716                         si_pi->leakage_voltage.entries[count].voltage = vddc;
3717                         si_pi->leakage_voltage.entries[count].leakage_index =
3718                                 SISLANDS_LEAKAGE_INDEX0 + i;
3719                         count++;
3720                 }
3721         }
3722         si_pi->leakage_voltage.count = count;
3723 }
3724
3725 static int si_get_leakage_voltage_from_leakage_index(struct amdgpu_device *adev,
3726                                                      u32 index, u16 *leakage_voltage)
3727 {
3728         struct si_power_info *si_pi = si_get_pi(adev);
3729         int i;
3730
3731         if (leakage_voltage == NULL)
3732                 return -EINVAL;
3733
3734         if ((index & 0xff00) != 0xff00)
3735                 return -EINVAL;
3736
3737         if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1)
3738                 return -EINVAL;
3739
3740         if (index < SISLANDS_LEAKAGE_INDEX0)
3741                 return -EINVAL;
3742
3743         for (i = 0; i < si_pi->leakage_voltage.count; i++) {
3744                 if (si_pi->leakage_voltage.entries[i].leakage_index == index) {
3745                         *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage;
3746                         return 0;
3747                 }
3748         }
3749         return -EAGAIN;
3750 }
3751
3752 static void si_set_dpm_event_sources(struct amdgpu_device *adev, u32 sources)
3753 {
3754         struct rv7xx_power_info *pi = rv770_get_pi(adev);
3755         bool want_thermal_protection;
3756         enum amdgpu_dpm_event_src dpm_event_src;
3757
3758         switch (sources) {
3759         case 0:
3760         default:
3761                 want_thermal_protection = false;
3762                 break;
3763         case (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL):
3764                 want_thermal_protection = true;
3765                 dpm_event_src = AMDGPU_DPM_EVENT_SRC_DIGITAL;
3766                 break;
3767         case (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
3768                 want_thermal_protection = true;
3769                 dpm_event_src = AMDGPU_DPM_EVENT_SRC_EXTERNAL;
3770                 break;
3771         case ((1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
3772               (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL)):
3773                 want_thermal_protection = true;
3774                 dpm_event_src = AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
3775                 break;
3776         }
3777
3778         if (want_thermal_protection) {
3779                 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK);
3780                 if (pi->thermal_protection)
3781                         WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3782         } else {
3783                 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3784         }
3785 }
3786
3787 static void si_enable_auto_throttle_source(struct amdgpu_device *adev,
3788                                            enum amdgpu_dpm_auto_throttle_src source,
3789                                            bool enable)
3790 {
3791         struct rv7xx_power_info *pi = rv770_get_pi(adev);
3792
3793         if (enable) {
3794                 if (!(pi->active_auto_throttle_sources & (1 << source))) {
3795                         pi->active_auto_throttle_sources |= 1 << source;
3796                         si_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);
3797                 }
3798         } else {
3799                 if (pi->active_auto_throttle_sources & (1 << source)) {
3800                         pi->active_auto_throttle_sources &= ~(1 << source);
3801                         si_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);
3802                 }
3803         }
3804 }
3805
3806 static void si_start_dpm(struct amdgpu_device *adev)
3807 {
3808         WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
3809 }
3810
3811 static void si_stop_dpm(struct amdgpu_device *adev)
3812 {
3813         WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
3814 }
3815
3816 static void si_enable_sclk_control(struct amdgpu_device *adev, bool enable)
3817 {
3818         if (enable)
3819                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
3820         else
3821                 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
3822
3823 }
3824
3825 #if 0
3826 static int si_notify_hardware_of_thermal_state(struct amdgpu_device *adev,
3827                                                u32 thermal_level)
3828 {
3829         PPSMC_Result ret;
3830
3831         if (thermal_level == 0) {
3832                 ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt);
3833                 if (ret == PPSMC_Result_OK)
3834                         return 0;
3835                 else
3836                         return -EINVAL;
3837         }
3838         return 0;
3839 }
3840
3841 static void si_notify_hardware_vpu_recovery_event(struct amdgpu_device *adev)
3842 {
3843         si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true);
3844 }
3845 #endif
3846
3847 #if 0
3848 static int si_notify_hw_of_powersource(struct amdgpu_device *adev, bool ac_power)
3849 {
3850         if (ac_power)
3851                 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ?
3852                         0 : -EINVAL;
3853
3854         return 0;
3855 }
3856 #endif
3857
3858 static PPSMC_Result si_send_msg_to_smc_with_parameter(struct amdgpu_device *adev,
3859                                                       PPSMC_Msg msg, u32 parameter)
3860 {
3861         WREG32(SMC_SCRATCH0, parameter);
3862         return amdgpu_si_send_msg_to_smc(adev, msg);
3863 }
3864
3865 static int si_restrict_performance_levels_before_switch(struct amdgpu_device *adev)
3866 {
3867         if (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK)
3868                 return -EINVAL;
3869
3870         return (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ?
3871                 0 : -EINVAL;
3872 }
3873
3874 static int si_dpm_force_performance_level(void *handle,
3875                                    enum amd_dpm_forced_level level)
3876 {
3877         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3878         struct amdgpu_ps *rps = adev->pm.dpm.current_ps;
3879         struct  si_ps *ps = si_get_ps(rps);
3880         u32 levels = ps->performance_level_count;
3881
3882         if (level == AMD_DPM_FORCED_LEVEL_HIGH) {
3883                 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3884                         return -EINVAL;
3885
3886                 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK)
3887                         return -EINVAL;
3888         } else if (level == AMD_DPM_FORCED_LEVEL_LOW) {
3889                 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3890                         return -EINVAL;
3891
3892                 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK)
3893                         return -EINVAL;
3894         } else if (level == AMD_DPM_FORCED_LEVEL_AUTO) {
3895                 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3896                         return -EINVAL;
3897
3898                 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3899                         return -EINVAL;
3900         }
3901
3902         adev->pm.dpm.forced_level = level;
3903
3904         return 0;
3905 }
3906
3907 #if 0
3908 static int si_set_boot_state(struct amdgpu_device *adev)
3909 {
3910         return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ?
3911                 0 : -EINVAL;
3912 }
3913 #endif
3914
3915 static int si_set_sw_state(struct amdgpu_device *adev)
3916 {
3917         return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ?
3918                 0 : -EINVAL;
3919 }
3920
3921 static int si_halt_smc(struct amdgpu_device *adev)
3922 {
3923         if (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_Halt) != PPSMC_Result_OK)
3924                 return -EINVAL;
3925
3926         return (amdgpu_si_wait_for_smc_inactive(adev) == PPSMC_Result_OK) ?
3927                 0 : -EINVAL;
3928 }
3929
3930 static int si_resume_smc(struct amdgpu_device *adev)
3931 {
3932         if (amdgpu_si_send_msg_to_smc(adev, PPSMC_FlushDataCache) != PPSMC_Result_OK)
3933                 return -EINVAL;
3934
3935         return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ?
3936                 0 : -EINVAL;
3937 }
3938
3939 static void si_dpm_start_smc(struct amdgpu_device *adev)
3940 {
3941         amdgpu_si_program_jump_on_start(adev);
3942         amdgpu_si_start_smc(adev);
3943         amdgpu_si_smc_clock(adev, true);
3944 }
3945
3946 static void si_dpm_stop_smc(struct amdgpu_device *adev)
3947 {
3948         amdgpu_si_reset_smc(adev);
3949         amdgpu_si_smc_clock(adev, false);
3950 }
3951
3952 static int si_process_firmware_header(struct amdgpu_device *adev)
3953 {
3954         struct si_power_info *si_pi = si_get_pi(adev);
3955         u32 tmp;
3956         int ret;
3957
3958         ret = amdgpu_si_read_smc_sram_dword(adev,
3959                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3960                                             SISLANDS_SMC_FIRMWARE_HEADER_stateTable,
3961                                             &tmp, si_pi->sram_end);
3962         if (ret)
3963                 return ret;
3964
3965         si_pi->state_table_start = tmp;
3966
3967         ret = amdgpu_si_read_smc_sram_dword(adev,
3968                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3969                                             SISLANDS_SMC_FIRMWARE_HEADER_softRegisters,
3970                                             &tmp, si_pi->sram_end);
3971         if (ret)
3972                 return ret;
3973
3974         si_pi->soft_regs_start = tmp;
3975
3976         ret = amdgpu_si_read_smc_sram_dword(adev,
3977                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3978                                             SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable,
3979                                             &tmp, si_pi->sram_end);
3980         if (ret)
3981                 return ret;
3982
3983         si_pi->mc_reg_table_start = tmp;
3984
3985         ret = amdgpu_si_read_smc_sram_dword(adev,
3986                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3987                                             SISLANDS_SMC_FIRMWARE_HEADER_fanTable,
3988                                             &tmp, si_pi->sram_end);
3989         if (ret)
3990                 return ret;
3991
3992         si_pi->fan_table_start = tmp;
3993
3994         ret = amdgpu_si_read_smc_sram_dword(adev,
3995                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3996                                             SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable,
3997                                             &tmp, si_pi->sram_end);
3998         if (ret)
3999                 return ret;
4000
4001         si_pi->arb_table_start = tmp;
4002
4003         ret = amdgpu_si_read_smc_sram_dword(adev,
4004                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4005                                             SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable,
4006                                             &tmp, si_pi->sram_end);
4007         if (ret)
4008                 return ret;
4009
4010         si_pi->cac_table_start = tmp;
4011
4012         ret = amdgpu_si_read_smc_sram_dword(adev,
4013                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4014                                             SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration,
4015                                             &tmp, si_pi->sram_end);
4016         if (ret)
4017                 return ret;
4018
4019         si_pi->dte_table_start = tmp;
4020
4021         ret = amdgpu_si_read_smc_sram_dword(adev,
4022                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4023                                             SISLANDS_SMC_FIRMWARE_HEADER_spllTable,
4024                                             &tmp, si_pi->sram_end);
4025         if (ret)
4026                 return ret;
4027
4028         si_pi->spll_table_start = tmp;
4029
4030         ret = amdgpu_si_read_smc_sram_dword(adev,
4031                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4032                                             SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters,
4033                                             &tmp, si_pi->sram_end);
4034         if (ret)
4035                 return ret;
4036
4037         si_pi->papm_cfg_table_start = tmp;
4038
4039         return ret;
4040 }
4041
4042 static void si_read_clock_registers(struct amdgpu_device *adev)
4043 {
4044         struct si_power_info *si_pi = si_get_pi(adev);
4045
4046         si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
4047         si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2);
4048         si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);
4049         si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4);
4050         si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM);
4051         si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2);
4052         si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
4053         si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
4054         si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
4055         si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
4056         si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
4057         si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
4058         si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
4059         si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
4060         si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
4061 }
4062
4063 static void si_enable_thermal_protection(struct amdgpu_device *adev,
4064                                           bool enable)
4065 {
4066         if (enable)
4067                 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
4068         else
4069                 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
4070 }
4071
4072 static void si_enable_acpi_power_management(struct amdgpu_device *adev)
4073 {
4074         WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
4075 }
4076
4077 #if 0
4078 static int si_enter_ulp_state(struct amdgpu_device *adev)
4079 {
4080         WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
4081
4082         udelay(25000);
4083
4084         return 0;
4085 }
4086
4087 static int si_exit_ulp_state(struct amdgpu_device *adev)
4088 {
4089         int i;
4090
4091         WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
4092
4093         udelay(7000);
4094
4095         for (i = 0; i < adev->usec_timeout; i++) {
4096                 if (RREG32(SMC_RESP_0) == 1)
4097                         break;
4098                 udelay(1000);
4099         }
4100
4101         return 0;
4102 }
4103 #endif
4104
4105 static int si_notify_smc_display_change(struct amdgpu_device *adev,
4106                                      bool has_display)
4107 {
4108         PPSMC_Msg msg = has_display ?
4109                 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
4110
4111         return (amdgpu_si_send_msg_to_smc(adev, msg) == PPSMC_Result_OK) ?
4112                 0 : -EINVAL;
4113 }
4114
4115 static void si_program_response_times(struct amdgpu_device *adev)
4116 {
4117         u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out;
4118         u32 vddc_dly, acpi_dly, vbi_dly;
4119         u32 reference_clock;
4120
4121         si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1);
4122
4123         voltage_response_time = (u32)adev->pm.dpm.voltage_response_time;
4124         backbias_response_time = (u32)adev->pm.dpm.backbias_response_time;
4125
4126         if (voltage_response_time == 0)
4127                 voltage_response_time = 1000;
4128
4129         acpi_delay_time = 15000;
4130         vbi_time_out = 100000;
4131
4132         reference_clock = amdgpu_asic_get_xclk(adev);
4133
4134         vddc_dly = (voltage_response_time  * reference_clock) / 100;
4135         acpi_dly = (acpi_delay_time * reference_clock) / 100;
4136         vbi_dly  = (vbi_time_out * reference_clock) / 100;
4137
4138         si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_delay_vreg,  vddc_dly);
4139         si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_delay_acpi,  acpi_dly);
4140         si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly);
4141         si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA);
4142 }
4143
4144 static void si_program_ds_registers(struct amdgpu_device *adev)
4145 {
4146         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4147         u32 tmp;
4148
4149         /* DEEP_SLEEP_CLK_SEL field should be 0x10 on tahiti A0 */
4150         if (adev->asic_type == CHIP_TAHITI && adev->rev_id == 0x0)
4151                 tmp = 0x10;
4152         else
4153                 tmp = 0x1;
4154
4155         if (eg_pi->sclk_deep_sleep) {
4156                 WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK);
4157                 WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR,
4158                          ~AUTOSCALE_ON_SS_CLEAR);
4159         }
4160 }
4161
4162 static void si_program_display_gap(struct amdgpu_device *adev)
4163 {
4164         u32 tmp, pipe;
4165         int i;
4166
4167         tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
4168         if (adev->pm.dpm.new_active_crtc_count > 0)
4169                 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
4170         else
4171                 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE);
4172
4173         if (adev->pm.dpm.new_active_crtc_count > 1)
4174                 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
4175         else
4176                 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE);
4177
4178         WREG32(CG_DISPLAY_GAP_CNTL, tmp);
4179
4180         tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);
4181         pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT;
4182
4183         if ((adev->pm.dpm.new_active_crtc_count > 0) &&
4184             (!(adev->pm.dpm.new_active_crtcs & (1 << pipe)))) {
4185                 /* find the first active crtc */
4186                 for (i = 0; i < adev->mode_info.num_crtc; i++) {
4187                         if (adev->pm.dpm.new_active_crtcs & (1 << i))
4188                                 break;
4189                 }
4190                 if (i == adev->mode_info.num_crtc)
4191                         pipe = 0;
4192                 else
4193                         pipe = i;
4194
4195                 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK;
4196                 tmp |= DCCG_DISP1_SLOW_SELECT(pipe);
4197                 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp);
4198         }
4199
4200         /* Setting this to false forces the performance state to low if the crtcs are disabled.
4201          * This can be a problem on PowerXpress systems or if you want to use the card
4202          * for offscreen rendering or compute if there are no crtcs enabled.
4203          */
4204         si_notify_smc_display_change(adev, adev->pm.dpm.new_active_crtc_count > 0);
4205 }
4206
4207 static void si_enable_spread_spectrum(struct amdgpu_device *adev, bool enable)
4208 {
4209         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4210
4211         if (enable) {
4212                 if (pi->sclk_ss)
4213                         WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);
4214         } else {
4215                 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN);
4216                 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);
4217         }
4218 }
4219
4220 static void si_setup_bsp(struct amdgpu_device *adev)
4221 {
4222         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4223         u32 xclk = amdgpu_asic_get_xclk(adev);
4224
4225         r600_calculate_u_and_p(pi->asi,
4226                                xclk,
4227                                16,
4228                                &pi->bsp,
4229                                &pi->bsu);
4230
4231         r600_calculate_u_and_p(pi->pasi,
4232                                xclk,
4233                                16,
4234                                &pi->pbsp,
4235                                &pi->pbsu);
4236
4237
4238         pi->dsp = BSP(pi->bsp) | BSU(pi->bsu);
4239         pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu);
4240
4241         WREG32(CG_BSP, pi->dsp);
4242 }
4243
4244 static void si_program_git(struct amdgpu_device *adev)
4245 {
4246         WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK);
4247 }
4248
4249 static void si_program_tp(struct amdgpu_device *adev)
4250 {
4251         int i;
4252         enum r600_td td = R600_TD_DFLT;
4253
4254         for (i = 0; i < R600_PM_NUMBER_OF_TC; i++)
4255                 WREG32(CG_FFCT_0 + i, (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i])));
4256
4257         if (td == R600_TD_AUTO)
4258                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
4259         else
4260                 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
4261
4262         if (td == R600_TD_UP)
4263                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
4264
4265         if (td == R600_TD_DOWN)
4266                 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
4267 }
4268
4269 static void si_program_tpp(struct amdgpu_device *adev)
4270 {
4271         WREG32(CG_TPC, R600_TPC_DFLT);
4272 }
4273
4274 static void si_program_sstp(struct amdgpu_device *adev)
4275 {
4276         WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));
4277 }
4278
4279 static void si_enable_display_gap(struct amdgpu_device *adev)
4280 {
4281         u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
4282
4283         tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
4284         tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
4285                 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE));
4286
4287         tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
4288         tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) |
4289                 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE));
4290         WREG32(CG_DISPLAY_GAP_CNTL, tmp);
4291 }
4292
4293 static void si_program_vc(struct amdgpu_device *adev)
4294 {
4295         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4296
4297         WREG32(CG_FTV, pi->vrc);
4298 }
4299
4300 static void si_clear_vc(struct amdgpu_device *adev)
4301 {
4302         WREG32(CG_FTV, 0);
4303 }
4304
4305 static u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock)
4306 {
4307         u8 mc_para_index;
4308
4309         if (memory_clock < 10000)
4310                 mc_para_index = 0;
4311         else if (memory_clock >= 80000)
4312                 mc_para_index = 0x0f;
4313         else
4314                 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1);
4315         return mc_para_index;
4316 }
4317
4318 static u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)
4319 {
4320         u8 mc_para_index;
4321
4322         if (strobe_mode) {
4323                 if (memory_clock < 12500)
4324                         mc_para_index = 0x00;
4325                 else if (memory_clock > 47500)
4326                         mc_para_index = 0x0f;
4327                 else
4328                         mc_para_index = (u8)((memory_clock - 10000) / 2500);
4329         } else {
4330                 if (memory_clock < 65000)
4331                         mc_para_index = 0x00;
4332                 else if (memory_clock > 135000)
4333                         mc_para_index = 0x0f;
4334                 else
4335                         mc_para_index = (u8)((memory_clock - 60000) / 5000);
4336         }
4337         return mc_para_index;
4338 }
4339
4340 static u8 si_get_strobe_mode_settings(struct amdgpu_device *adev, u32 mclk)
4341 {
4342         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4343         bool strobe_mode = false;
4344         u8 result = 0;
4345
4346         if (mclk <= pi->mclk_strobe_mode_threshold)
4347                 strobe_mode = true;
4348
4349         if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
4350                 result = si_get_mclk_frequency_ratio(mclk, strobe_mode);
4351         else
4352                 result = si_get_ddr3_mclk_frequency_ratio(mclk);
4353
4354         if (strobe_mode)
4355                 result |= SISLANDS_SMC_STROBE_ENABLE;
4356
4357         return result;
4358 }
4359
4360 static int si_upload_firmware(struct amdgpu_device *adev)
4361 {
4362         struct si_power_info *si_pi = si_get_pi(adev);
4363
4364         amdgpu_si_reset_smc(adev);
4365         amdgpu_si_smc_clock(adev, false);
4366
4367         return amdgpu_si_load_smc_ucode(adev, si_pi->sram_end);
4368 }
4369
4370 static bool si_validate_phase_shedding_tables(struct amdgpu_device *adev,
4371                                               const struct atom_voltage_table *table,
4372                                               const struct amdgpu_phase_shedding_limits_table *limits)
4373 {
4374         u32 data, num_bits, num_levels;
4375
4376         if ((table == NULL) || (limits == NULL))
4377                 return false;
4378
4379         data = table->mask_low;
4380
4381         num_bits = hweight32(data);
4382
4383         if (num_bits == 0)
4384                 return false;
4385
4386         num_levels = (1 << num_bits);
4387
4388         if (table->count != num_levels)
4389                 return false;
4390
4391         if (limits->count != (num_levels - 1))
4392                 return false;
4393
4394         return true;
4395 }
4396
4397 static void si_trim_voltage_table_to_fit_state_table(struct amdgpu_device *adev,
4398                                               u32 max_voltage_steps,
4399                                               struct atom_voltage_table *voltage_table)
4400 {
4401         unsigned int i, diff;
4402
4403         if (voltage_table->count <= max_voltage_steps)
4404                 return;
4405
4406         diff = voltage_table->count - max_voltage_steps;
4407
4408         for (i= 0; i < max_voltage_steps; i++)
4409                 voltage_table->entries[i] = voltage_table->entries[i + diff];
4410
4411         voltage_table->count = max_voltage_steps;
4412 }
4413
4414 static int si_get_svi2_voltage_table(struct amdgpu_device *adev,
4415                                      struct amdgpu_clock_voltage_dependency_table *voltage_dependency_table,
4416                                      struct atom_voltage_table *voltage_table)
4417 {
4418         u32 i;
4419
4420         if (voltage_dependency_table == NULL)
4421                 return -EINVAL;
4422
4423         voltage_table->mask_low = 0;
4424         voltage_table->phase_delay = 0;
4425
4426         voltage_table->count = voltage_dependency_table->count;
4427         for (i = 0; i < voltage_table->count; i++) {
4428                 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
4429                 voltage_table->entries[i].smio_low = 0;
4430         }
4431
4432         return 0;
4433 }
4434
4435 static int si_construct_voltage_tables(struct amdgpu_device *adev)
4436 {
4437         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4438         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4439         struct si_power_info *si_pi = si_get_pi(adev);
4440         int ret;
4441
4442         if (pi->voltage_control) {
4443                 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDC,
4444                                                     VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table);
4445                 if (ret)
4446                         return ret;
4447
4448                 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4449                         si_trim_voltage_table_to_fit_state_table(adev,
4450                                                                  SISLANDS_MAX_NO_VREG_STEPS,
4451                                                                  &eg_pi->vddc_voltage_table);
4452         } else if (si_pi->voltage_control_svi2) {
4453                 ret = si_get_svi2_voltage_table(adev,
4454                                                 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
4455                                                 &eg_pi->vddc_voltage_table);
4456                 if (ret)
4457                         return ret;
4458         } else {
4459                 return -EINVAL;
4460         }
4461
4462         if (eg_pi->vddci_control) {
4463                 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDCI,
4464                                                     VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table);
4465                 if (ret)
4466                         return ret;
4467
4468                 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4469                         si_trim_voltage_table_to_fit_state_table(adev,
4470                                                                  SISLANDS_MAX_NO_VREG_STEPS,
4471                                                                  &eg_pi->vddci_voltage_table);
4472         }
4473         if (si_pi->vddci_control_svi2) {
4474                 ret = si_get_svi2_voltage_table(adev,
4475                                                 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
4476                                                 &eg_pi->vddci_voltage_table);
4477                 if (ret)
4478                         return ret;
4479         }
4480
4481         if (pi->mvdd_control) {
4482                 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_MVDDC,
4483                                                     VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table);
4484
4485                 if (ret) {
4486                         pi->mvdd_control = false;
4487                         return ret;
4488                 }
4489
4490                 if (si_pi->mvdd_voltage_table.count == 0) {
4491                         pi->mvdd_control = false;
4492                         return -EINVAL;
4493                 }
4494
4495                 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4496                         si_trim_voltage_table_to_fit_state_table(adev,
4497                                                                  SISLANDS_MAX_NO_VREG_STEPS,
4498                                                                  &si_pi->mvdd_voltage_table);
4499         }
4500
4501         if (si_pi->vddc_phase_shed_control) {
4502                 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDC,
4503                                                     VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table);
4504                 if (ret)
4505                         si_pi->vddc_phase_shed_control = false;
4506
4507                 if ((si_pi->vddc_phase_shed_table.count == 0) ||
4508                     (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS))
4509                         si_pi->vddc_phase_shed_control = false;
4510         }
4511
4512         return 0;
4513 }
4514
4515 static void si_populate_smc_voltage_table(struct amdgpu_device *adev,
4516                                           const struct atom_voltage_table *voltage_table,
4517                                           SISLANDS_SMC_STATETABLE *table)
4518 {
4519         unsigned int i;
4520
4521         for (i = 0; i < voltage_table->count; i++)
4522                 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low);
4523 }
4524
4525 static int si_populate_smc_voltage_tables(struct amdgpu_device *adev,
4526                                           SISLANDS_SMC_STATETABLE *table)
4527 {
4528         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4529         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4530         struct si_power_info *si_pi = si_get_pi(adev);
4531         u8 i;
4532
4533         if (si_pi->voltage_control_svi2) {
4534                 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc,
4535                         si_pi->svc_gpio_id);
4536                 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd,
4537                         si_pi->svd_gpio_id);
4538                 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type,
4539                                            2);
4540         } else {
4541                 if (eg_pi->vddc_voltage_table.count) {
4542                         si_populate_smc_voltage_table(adev, &eg_pi->vddc_voltage_table, table);
4543                         table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =
4544                                 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);
4545
4546                         for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) {
4547                                 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) {
4548                                         table->maxVDDCIndexInPPTable = i;
4549                                         break;
4550                                 }
4551                         }
4552                 }
4553
4554                 if (eg_pi->vddci_voltage_table.count) {
4555                         si_populate_smc_voltage_table(adev, &eg_pi->vddci_voltage_table, table);
4556
4557                         table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] =
4558                                 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low);
4559                 }
4560
4561
4562                 if (si_pi->mvdd_voltage_table.count) {
4563                         si_populate_smc_voltage_table(adev, &si_pi->mvdd_voltage_table, table);
4564
4565                         table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] =
4566                                 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low);
4567                 }
4568
4569                 if (si_pi->vddc_phase_shed_control) {
4570                         if (si_validate_phase_shedding_tables(adev, &si_pi->vddc_phase_shed_table,
4571                                                               &adev->pm.dpm.dyn_state.phase_shedding_limits_table)) {
4572                                 si_populate_smc_voltage_table(adev, &si_pi->vddc_phase_shed_table, table);
4573
4574                                 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING] =
4575                                         cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low);
4576
4577                                 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_phase_shedding_delay,
4578                                                            (u32)si_pi->vddc_phase_shed_table.phase_delay);
4579                         } else {
4580                                 si_pi->vddc_phase_shed_control = false;
4581                         }
4582                 }
4583         }
4584
4585         return 0;
4586 }
4587
4588 static int si_populate_voltage_value(struct amdgpu_device *adev,
4589                                      const struct atom_voltage_table *table,
4590                                      u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4591 {
4592         unsigned int i;
4593
4594         for (i = 0; i < table->count; i++) {
4595                 if (value <= table->entries[i].value) {
4596                         voltage->index = (u8)i;
4597                         voltage->value = cpu_to_be16(table->entries[i].value);
4598                         break;
4599                 }
4600         }
4601
4602         if (i >= table->count)
4603                 return -EINVAL;
4604
4605         return 0;
4606 }
4607
4608 static int si_populate_mvdd_value(struct amdgpu_device *adev, u32 mclk,
4609                                   SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4610 {
4611         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4612         struct si_power_info *si_pi = si_get_pi(adev);
4613
4614         if (pi->mvdd_control) {
4615                 if (mclk <= pi->mvdd_split_frequency)
4616                         voltage->index = 0;
4617                 else
4618                         voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1;
4619
4620                 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value);
4621         }
4622         return 0;
4623 }
4624
4625 static int si_get_std_voltage_value(struct amdgpu_device *adev,
4626                                     SISLANDS_SMC_VOLTAGE_VALUE *voltage,
4627                                     u16 *std_voltage)
4628 {
4629         u16 v_index;
4630         bool voltage_found = false;
4631         *std_voltage = be16_to_cpu(voltage->value);
4632
4633         if (adev->pm.dpm.dyn_state.cac_leakage_table.entries) {
4634                 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) {
4635                         if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
4636                                 return -EINVAL;
4637
4638                         for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4639                                 if (be16_to_cpu(voltage->value) ==
4640                                     (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4641                                         voltage_found = true;
4642                                         if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
4643                                                 *std_voltage =
4644                                                         adev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4645                                         else
4646                                                 *std_voltage =
4647                                                         adev->pm.dpm.dyn_state.cac_leakage_table.entries[adev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4648                                         break;
4649                                 }
4650                         }
4651
4652                         if (!voltage_found) {
4653                                 for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4654                                         if (be16_to_cpu(voltage->value) <=
4655                                             (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4656                                                 voltage_found = true;
4657                                                 if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
4658                                                         *std_voltage =
4659                                                                 adev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4660                                                 else
4661                                                         *std_voltage =
4662                                                                 adev->pm.dpm.dyn_state.cac_leakage_table.entries[adev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4663                                                 break;
4664                                         }
4665                                 }
4666                         }
4667                 } else {
4668                         if ((u32)voltage->index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
4669                                 *std_voltage = adev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc;
4670                 }
4671         }
4672
4673         return 0;
4674 }
4675
4676 static int si_populate_std_voltage_value(struct amdgpu_device *adev,
4677                                          u16 value, u8 index,
4678                                          SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4679 {
4680         voltage->index = index;
4681         voltage->value = cpu_to_be16(value);
4682
4683         return 0;
4684 }
4685
4686 static int si_populate_phase_shedding_value(struct amdgpu_device *adev,
4687                                             const struct amdgpu_phase_shedding_limits_table *limits,
4688                                             u16 voltage, u32 sclk, u32 mclk,
4689                                             SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage)
4690 {
4691         unsigned int i;
4692
4693         for (i = 0; i < limits->count; i++) {
4694                 if ((voltage <= limits->entries[i].voltage) &&
4695                     (sclk <= limits->entries[i].sclk) &&
4696                     (mclk <= limits->entries[i].mclk))
4697                         break;
4698         }
4699
4700         smc_voltage->phase_settings = (u8)i;
4701
4702         return 0;
4703 }
4704
4705 static int si_init_arb_table_index(struct amdgpu_device *adev)
4706 {
4707         struct si_power_info *si_pi = si_get_pi(adev);
4708         u32 tmp;
4709         int ret;
4710
4711         ret = amdgpu_si_read_smc_sram_dword(adev, si_pi->arb_table_start,
4712                                             &tmp, si_pi->sram_end);
4713         if (ret)
4714                 return ret;
4715
4716         tmp &= 0x00FFFFFF;
4717         tmp |= MC_CG_ARB_FREQ_F1 << 24;
4718
4719         return amdgpu_si_write_smc_sram_dword(adev, si_pi->arb_table_start,
4720                                               tmp, si_pi->sram_end);
4721 }
4722
4723 static int si_initial_switch_from_arb_f0_to_f1(struct amdgpu_device *adev)
4724 {
4725         return ni_copy_and_switch_arb_sets(adev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
4726 }
4727
4728 static int si_reset_to_default(struct amdgpu_device *adev)
4729 {
4730         return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
4731                 0 : -EINVAL;
4732 }
4733
4734 static int si_force_switch_to_arb_f0(struct amdgpu_device *adev)
4735 {
4736         struct si_power_info *si_pi = si_get_pi(adev);
4737         u32 tmp;
4738         int ret;
4739
4740         ret = amdgpu_si_read_smc_sram_dword(adev, si_pi->arb_table_start,
4741                                             &tmp, si_pi->sram_end);
4742         if (ret)
4743                 return ret;
4744
4745         tmp = (tmp >> 24) & 0xff;
4746
4747         if (tmp == MC_CG_ARB_FREQ_F0)
4748                 return 0;
4749
4750         return ni_copy_and_switch_arb_sets(adev, tmp, MC_CG_ARB_FREQ_F0);
4751 }
4752
4753 static u32 si_calculate_memory_refresh_rate(struct amdgpu_device *adev,
4754                                             u32 engine_clock)
4755 {
4756         u32 dram_rows;
4757         u32 dram_refresh_rate;
4758         u32 mc_arb_rfsh_rate;
4759         u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
4760
4761         if (tmp >= 4)
4762                 dram_rows = 16384;
4763         else
4764                 dram_rows = 1 << (tmp + 10);
4765
4766         dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3);
4767         mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64;
4768
4769         return mc_arb_rfsh_rate;
4770 }
4771
4772 static int si_populate_memory_timing_parameters(struct amdgpu_device *adev,
4773                                                 struct rv7xx_pl *pl,
4774                                                 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs)
4775 {
4776         u32 dram_timing;
4777         u32 dram_timing2;
4778         u32 burst_time;
4779
4780         arb_regs->mc_arb_rfsh_rate =
4781                 (u8)si_calculate_memory_refresh_rate(adev, pl->sclk);
4782
4783         amdgpu_atombios_set_engine_dram_timings(adev,
4784                                             pl->sclk,
4785                                             pl->mclk);
4786
4787         dram_timing  = RREG32(MC_ARB_DRAM_TIMING);
4788         dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
4789         burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
4790
4791         arb_regs->mc_arb_dram_timing  = cpu_to_be32(dram_timing);
4792         arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2);
4793         arb_regs->mc_arb_burst_time = (u8)burst_time;
4794
4795         return 0;
4796 }
4797
4798 static int si_do_program_memory_timing_parameters(struct amdgpu_device *adev,
4799                                                   struct amdgpu_ps *amdgpu_state,
4800                                                   unsigned int first_arb_set)
4801 {
4802         struct si_power_info *si_pi = si_get_pi(adev);
4803         struct  si_ps *state = si_get_ps(amdgpu_state);
4804         SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4805         int i, ret = 0;
4806
4807         for (i = 0; i < state->performance_level_count; i++) {
4808                 ret = si_populate_memory_timing_parameters(adev, &state->performance_levels[i], &arb_regs);
4809                 if (ret)
4810                         break;
4811                 ret = amdgpu_si_copy_bytes_to_smc(adev,
4812                                                   si_pi->arb_table_start +
4813                                                   offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4814                                                   sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i),
4815                                                   (u8 *)&arb_regs,
4816                                                   sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4817                                                   si_pi->sram_end);
4818                 if (ret)
4819                         break;
4820         }
4821
4822         return ret;
4823 }
4824
4825 static int si_program_memory_timing_parameters(struct amdgpu_device *adev,
4826                                                struct amdgpu_ps *amdgpu_new_state)
4827 {
4828         return si_do_program_memory_timing_parameters(adev, amdgpu_new_state,
4829                                                       SISLANDS_DRIVER_STATE_ARB_INDEX);
4830 }
4831
4832 static int si_populate_initial_mvdd_value(struct amdgpu_device *adev,
4833                                           struct SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4834 {
4835         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4836         struct si_power_info *si_pi = si_get_pi(adev);
4837
4838         if (pi->mvdd_control)
4839                 return si_populate_voltage_value(adev, &si_pi->mvdd_voltage_table,
4840                                                  si_pi->mvdd_bootup_value, voltage);
4841
4842         return 0;
4843 }
4844
4845 static int si_populate_smc_initial_state(struct amdgpu_device *adev,
4846                                          struct amdgpu_ps *amdgpu_initial_state,
4847                                          SISLANDS_SMC_STATETABLE *table)
4848 {
4849         struct  si_ps *initial_state = si_get_ps(amdgpu_initial_state);
4850         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4851         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4852         struct si_power_info *si_pi = si_get_pi(adev);
4853         u32 reg;
4854         int ret;
4855
4856         table->initialState.levels[0].mclk.vDLL_CNTL =
4857                 cpu_to_be32(si_pi->clock_registers.dll_cntl);
4858         table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4859                 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl);
4860         table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4861                 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl);
4862         table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4863                 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl);
4864         table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL =
4865                 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl);
4866         table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4867                 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1);
4868         table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4869                 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2);
4870         table->initialState.levels[0].mclk.vMPLL_SS =
4871                 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4872         table->initialState.levels[0].mclk.vMPLL_SS2 =
4873                 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4874
4875         table->initialState.levels[0].mclk.mclk_value =
4876                 cpu_to_be32(initial_state->performance_levels[0].mclk);
4877
4878         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4879                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl);
4880         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4881                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2);
4882         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4883                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3);
4884         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4885                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4);
4886         table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
4887                 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum);
4888         table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2  =
4889                 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2);
4890
4891         table->initialState.levels[0].sclk.sclk_value =
4892                 cpu_to_be32(initial_state->performance_levels[0].sclk);
4893
4894         table->initialState.levels[0].arbRefreshState =
4895                 SISLANDS_INITIAL_STATE_ARB_INDEX;
4896
4897         table->initialState.levels[0].ACIndex = 0;
4898
4899         ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
4900                                         initial_state->performance_levels[0].vddc,
4901                                         &table->initialState.levels[0].vddc);
4902
4903         if (!ret) {
4904                 u16 std_vddc;
4905
4906                 ret = si_get_std_voltage_value(adev,
4907                                                &table->initialState.levels[0].vddc,
4908                                                &std_vddc);
4909                 if (!ret)
4910                         si_populate_std_voltage_value(adev, std_vddc,
4911                                                       table->initialState.levels[0].vddc.index,
4912                                                       &table->initialState.levels[0].std_vddc);
4913         }
4914
4915         if (eg_pi->vddci_control)
4916                 si_populate_voltage_value(adev,
4917                                           &eg_pi->vddci_voltage_table,
4918                                           initial_state->performance_levels[0].vddci,
4919                                           &table->initialState.levels[0].vddci);
4920
4921         if (si_pi->vddc_phase_shed_control)
4922                 si_populate_phase_shedding_value(adev,
4923                                                  &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
4924                                                  initial_state->performance_levels[0].vddc,
4925                                                  initial_state->performance_levels[0].sclk,
4926                                                  initial_state->performance_levels[0].mclk,
4927                                                  &table->initialState.levels[0].vddc);
4928
4929         si_populate_initial_mvdd_value(adev, &table->initialState.levels[0].mvdd);
4930
4931         reg = CG_R(0xffff) | CG_L(0);
4932         table->initialState.levels[0].aT = cpu_to_be32(reg);
4933         table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
4934         table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen;
4935
4936         if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
4937                 table->initialState.levels[0].strobeMode =
4938                         si_get_strobe_mode_settings(adev,
4939                                                     initial_state->performance_levels[0].mclk);
4940
4941                 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold)
4942                         table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG;
4943                 else
4944                         table->initialState.levels[0].mcFlags =  0;
4945         }
4946
4947         table->initialState.levelCount = 1;
4948
4949         table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;
4950
4951         table->initialState.levels[0].dpm2.MaxPS = 0;
4952         table->initialState.levels[0].dpm2.NearTDPDec = 0;
4953         table->initialState.levels[0].dpm2.AboveSafeInc = 0;
4954         table->initialState.levels[0].dpm2.BelowSafeInc = 0;
4955         table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4956
4957         reg = MIN_POWER_MASK | MAX_POWER_MASK;
4958         table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4959
4960         reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
4961         table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4962
4963         return 0;
4964 }
4965
4966 static int si_populate_smc_acpi_state(struct amdgpu_device *adev,
4967                                       SISLANDS_SMC_STATETABLE *table)
4968 {
4969         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4970         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4971         struct si_power_info *si_pi = si_get_pi(adev);
4972         u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
4973         u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
4974         u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
4975         u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
4976         u32 dll_cntl = si_pi->clock_registers.dll_cntl;
4977         u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
4978         u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
4979         u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
4980         u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
4981         u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
4982         u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
4983         u32 reg;
4984         int ret;
4985
4986         table->ACPIState = table->initialState;
4987
4988         table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;
4989
4990         if (pi->acpi_vddc) {
4991                 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
4992                                                 pi->acpi_vddc, &table->ACPIState.levels[0].vddc);
4993                 if (!ret) {
4994                         u16 std_vddc;
4995
4996                         ret = si_get_std_voltage_value(adev,
4997                                                        &table->ACPIState.levels[0].vddc, &std_vddc);
4998                         if (!ret)
4999                                 si_populate_std_voltage_value(adev, std_vddc,
5000                                                               table->ACPIState.levels[0].vddc.index,
5001                                                               &table->ACPIState.levels[0].std_vddc);
5002                 }
5003                 table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen;
5004
5005                 if (si_pi->vddc_phase_shed_control) {
5006                         si_populate_phase_shedding_value(adev,
5007                                                          &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
5008                                                          pi->acpi_vddc,
5009                                                          0,
5010                                                          0,
5011                                                          &table->ACPIState.levels[0].vddc);
5012                 }
5013         } else {
5014                 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
5015                                                 pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc);
5016                 if (!ret) {
5017                         u16 std_vddc;
5018
5019                         ret = si_get_std_voltage_value(adev,
5020                                                        &table->ACPIState.levels[0].vddc, &std_vddc);
5021
5022                         if (!ret)
5023                                 si_populate_std_voltage_value(adev, std_vddc,
5024                                                               table->ACPIState.levels[0].vddc.index,
5025                                                               &table->ACPIState.levels[0].std_vddc);
5026                 }
5027                 table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(adev,
5028                                                                                     si_pi->sys_pcie_mask,
5029                                                                                     si_pi->boot_pcie_gen,
5030                                                                                     AMDGPU_PCIE_GEN1);
5031
5032                 if (si_pi->vddc_phase_shed_control)
5033                         si_populate_phase_shedding_value(adev,
5034                                                          &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
5035                                                          pi->min_vddc_in_table,
5036                                                          0,
5037                                                          0,
5038                                                          &table->ACPIState.levels[0].vddc);
5039         }
5040
5041         if (pi->acpi_vddc) {
5042                 if (eg_pi->acpi_vddci)
5043                         si_populate_voltage_value(adev, &eg_pi->vddci_voltage_table,
5044                                                   eg_pi->acpi_vddci,
5045                                                   &table->ACPIState.levels[0].vddci);
5046         }
5047
5048         mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET;
5049         mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
5050
5051         dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS);
5052
5053         spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
5054         spll_func_cntl_2 |= SCLK_MUX_SEL(4);
5055
5056         table->ACPIState.levels[0].mclk.vDLL_CNTL =
5057                 cpu_to_be32(dll_cntl);
5058         table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
5059                 cpu_to_be32(mclk_pwrmgt_cntl);
5060         table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
5061                 cpu_to_be32(mpll_ad_func_cntl);
5062         table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
5063                 cpu_to_be32(mpll_dq_func_cntl);
5064         table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL =
5065                 cpu_to_be32(mpll_func_cntl);
5066         table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
5067                 cpu_to_be32(mpll_func_cntl_1);
5068         table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
5069                 cpu_to_be32(mpll_func_cntl_2);
5070         table->ACPIState.levels[0].mclk.vMPLL_SS =
5071                 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
5072         table->ACPIState.levels[0].mclk.vMPLL_SS2 =
5073                 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
5074
5075         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
5076                 cpu_to_be32(spll_func_cntl);
5077         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
5078                 cpu_to_be32(spll_func_cntl_2);
5079         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
5080                 cpu_to_be32(spll_func_cntl_3);
5081         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
5082                 cpu_to_be32(spll_func_cntl_4);
5083
5084         table->ACPIState.levels[0].mclk.mclk_value = 0;
5085         table->ACPIState.levels[0].sclk.sclk_value = 0;
5086
5087         si_populate_mvdd_value(adev, 0, &table->ACPIState.levels[0].mvdd);
5088
5089         if (eg_pi->dynamic_ac_timing)
5090                 table->ACPIState.levels[0].ACIndex = 0;
5091
5092         table->ACPIState.levels[0].dpm2.MaxPS = 0;
5093         table->ACPIState.levels[0].dpm2.NearTDPDec = 0;
5094         table->ACPIState.levels[0].dpm2.AboveSafeInc = 0;
5095         table->ACPIState.levels[0].dpm2.BelowSafeInc = 0;
5096         table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0;
5097
5098         reg = MIN_POWER_MASK | MAX_POWER_MASK;
5099         table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
5100
5101         reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
5102         table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
5103
5104         return 0;
5105 }
5106
5107 static int si_populate_ulv_state(struct amdgpu_device *adev,
5108                                  SISLANDS_SMC_SWSTATE *state)
5109 {
5110         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5111         struct si_power_info *si_pi = si_get_pi(adev);
5112         struct si_ulv_param *ulv = &si_pi->ulv;
5113         u32 sclk_in_sr = 1350; /* ??? */
5114         int ret;
5115
5116         ret = si_convert_power_level_to_smc(adev, &ulv->pl,
5117                                             &state->levels[0]);
5118         if (!ret) {
5119                 if (eg_pi->sclk_deep_sleep) {
5120                         if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
5121                                 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
5122                         else
5123                                 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
5124                 }
5125                 if (ulv->one_pcie_lane_in_ulv)
5126                         state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1;
5127                 state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX);
5128                 state->levels[0].ACIndex = 1;
5129                 state->levels[0].std_vddc = state->levels[0].vddc;
5130                 state->levelCount = 1;
5131
5132                 state->flags |= PPSMC_SWSTATE_FLAG_DC;
5133         }
5134
5135         return ret;
5136 }
5137
5138 static int si_program_ulv_memory_timing_parameters(struct amdgpu_device *adev)
5139 {
5140         struct si_power_info *si_pi = si_get_pi(adev);
5141         struct si_ulv_param *ulv = &si_pi->ulv;
5142         SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
5143         int ret;
5144
5145         ret = si_populate_memory_timing_parameters(adev, &ulv->pl,
5146                                                    &arb_regs);
5147         if (ret)
5148                 return ret;
5149
5150         si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay,
5151                                    ulv->volt_change_delay);
5152
5153         ret = amdgpu_si_copy_bytes_to_smc(adev,
5154                                           si_pi->arb_table_start +
5155                                           offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
5156                                           sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX,
5157                                           (u8 *)&arb_regs,
5158                                           sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
5159                                           si_pi->sram_end);
5160
5161         return ret;
5162 }
5163
5164 static void si_get_mvdd_configuration(struct amdgpu_device *adev)
5165 {
5166         struct rv7xx_power_info *pi = rv770_get_pi(adev);
5167
5168         pi->mvdd_split_frequency = 30000;
5169 }
5170
5171 static int si_init_smc_table(struct amdgpu_device *adev)
5172 {
5173         struct si_power_info *si_pi = si_get_pi(adev);
5174         struct amdgpu_ps *amdgpu_boot_state = adev->pm.dpm.boot_ps;
5175         const struct si_ulv_param *ulv = &si_pi->ulv;
5176         SISLANDS_SMC_STATETABLE  *table = &si_pi->smc_statetable;
5177         int ret;
5178         u32 lane_width;
5179         u32 vr_hot_gpio;
5180
5181         si_populate_smc_voltage_tables(adev, table);
5182
5183         switch (adev->pm.int_thermal_type) {
5184         case THERMAL_TYPE_SI:
5185         case THERMAL_TYPE_EMC2103_WITH_INTERNAL:
5186                 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL;
5187                 break;
5188         case THERMAL_TYPE_NONE:
5189                 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE;
5190                 break;
5191         default:
5192                 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL;
5193                 break;
5194         }
5195
5196         if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
5197                 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
5198
5199         if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) {
5200                 if ((adev->pdev->device != 0x6818) && (adev->pdev->device != 0x6819))
5201                         table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT;
5202         }
5203
5204         if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
5205                 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
5206
5207         if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
5208                 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
5209
5210         if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY)
5211                 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH;
5212
5213         if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) {
5214                 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO;
5215                 vr_hot_gpio = adev->pm.dpm.backbias_response_time;
5216                 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_vr_hot_gpio,
5217                                            vr_hot_gpio);
5218         }
5219
5220         ret = si_populate_smc_initial_state(adev, amdgpu_boot_state, table);
5221         if (ret)
5222                 return ret;
5223
5224         ret = si_populate_smc_acpi_state(adev, table);
5225         if (ret)
5226                 return ret;
5227
5228         table->driverState = table->initialState;
5229
5230         ret = si_do_program_memory_timing_parameters(adev, amdgpu_boot_state,
5231                                                      SISLANDS_INITIAL_STATE_ARB_INDEX);
5232         if (ret)
5233                 return ret;
5234
5235         if (ulv->supported && ulv->pl.vddc) {
5236                 ret = si_populate_ulv_state(adev, &table->ULVState);
5237                 if (ret)
5238                         return ret;
5239
5240                 ret = si_program_ulv_memory_timing_parameters(adev);
5241                 if (ret)
5242                         return ret;
5243
5244                 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control);
5245                 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);
5246
5247                 lane_width = amdgpu_get_pcie_lanes(adev);
5248                 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
5249         } else {
5250                 table->ULVState = table->initialState;
5251         }
5252
5253         return amdgpu_si_copy_bytes_to_smc(adev, si_pi->state_table_start,
5254                                            (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE),
5255                                            si_pi->sram_end);
5256 }
5257
5258 static int si_calculate_sclk_params(struct amdgpu_device *adev,
5259                                     u32 engine_clock,
5260                                     SISLANDS_SMC_SCLK_VALUE *sclk)
5261 {
5262         struct rv7xx_power_info *pi = rv770_get_pi(adev);
5263         struct si_power_info *si_pi = si_get_pi(adev);
5264         struct atom_clock_dividers dividers;
5265         u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
5266         u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
5267         u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
5268         u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
5269         u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum;
5270         u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2;
5271         u64 tmp;
5272         u32 reference_clock = adev->clock.spll.reference_freq;
5273         u32 reference_divider;
5274         u32 fbdiv;
5275         int ret;
5276
5277         ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
5278                                              engine_clock, false, &dividers);
5279         if (ret)
5280                 return ret;
5281
5282         reference_divider = 1 + dividers.ref_div;
5283
5284         tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
5285         do_div(tmp, reference_clock);
5286         fbdiv = (u32) tmp;
5287
5288         spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK);
5289         spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
5290         spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);
5291
5292         spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
5293         spll_func_cntl_2 |= SCLK_MUX_SEL(2);
5294
5295         spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
5296         spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
5297         spll_func_cntl_3 |= SPLL_DITHEN;
5298
5299         if (pi->sclk_ss) {
5300                 struct amdgpu_atom_ss ss;
5301                 u32 vco_freq = engine_clock * dividers.post_div;
5302
5303                 if (amdgpu_atombios_get_asic_ss_info(adev, &ss,
5304                                                      ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
5305                         u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
5306                         u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
5307
5308                         cg_spll_spread_spectrum &= ~CLK_S_MASK;
5309                         cg_spll_spread_spectrum |= CLK_S(clk_s);
5310                         cg_spll_spread_spectrum |= SSEN;
5311
5312                         cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
5313                         cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
5314                 }
5315         }
5316
5317         sclk->sclk_value = engine_clock;
5318         sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl;
5319         sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2;
5320         sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3;
5321         sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4;
5322         sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum;
5323         sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2;
5324
5325         return 0;
5326 }
5327
5328 static int si_populate_sclk_value(struct amdgpu_device *adev,
5329                                   u32 engine_clock,
5330                                   SISLANDS_SMC_SCLK_VALUE *sclk)
5331 {
5332         SISLANDS_SMC_SCLK_VALUE sclk_tmp;
5333         int ret;
5334
5335         ret = si_calculate_sclk_params(adev, engine_clock, &sclk_tmp);
5336         if (!ret) {
5337                 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value);
5338                 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL);
5339                 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2);
5340                 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3);
5341                 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4);
5342                 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM);
5343                 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2);
5344         }
5345
5346         return ret;
5347 }
5348
5349 static int si_populate_mclk_value(struct amdgpu_device *adev,
5350                                   u32 engine_clock,
5351                                   u32 memory_clock,
5352                                   SISLANDS_SMC_MCLK_VALUE *mclk,
5353                                   bool strobe_mode,
5354                                   bool dll_state_on)
5355 {
5356         struct rv7xx_power_info *pi = rv770_get_pi(adev);
5357         struct si_power_info *si_pi = si_get_pi(adev);
5358         u32  dll_cntl = si_pi->clock_registers.dll_cntl;
5359         u32  mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
5360         u32  mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
5361         u32  mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
5362         u32  mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
5363         u32  mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
5364         u32  mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
5365         u32  mpll_ss1 = si_pi->clock_registers.mpll_ss1;
5366         u32  mpll_ss2 = si_pi->clock_registers.mpll_ss2;
5367         struct atom_mpll_param mpll_param;
5368         int ret;
5369
5370         ret = amdgpu_atombios_get_memory_pll_dividers(adev, memory_clock, strobe_mode, &mpll_param);
5371         if (ret)
5372                 return ret;
5373
5374         mpll_func_cntl &= ~BWCTRL_MASK;
5375         mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
5376
5377         mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
5378         mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
5379                 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
5380
5381         mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
5382         mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
5383
5384         if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
5385                 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
5386                 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
5387                         YCLK_POST_DIV(mpll_param.post_div);
5388         }
5389
5390         if (pi->mclk_ss) {
5391                 struct amdgpu_atom_ss ss;
5392                 u32 freq_nom;
5393                 u32 tmp;
5394                 u32 reference_clock = adev->clock.mpll.reference_freq;
5395
5396                 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
5397                         freq_nom = memory_clock * 4;
5398                 else
5399                         freq_nom = memory_clock * 2;
5400
5401                 tmp = freq_nom / reference_clock;
5402                 tmp = tmp * tmp;
5403                 if (amdgpu_atombios_get_asic_ss_info(adev, &ss,
5404                                                      ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
5405                         u32 clks = reference_clock * 5 / ss.rate;
5406                         u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
5407
5408                         mpll_ss1 &= ~CLKV_MASK;
5409                         mpll_ss1 |= CLKV(clkv);
5410
5411                         mpll_ss2 &= ~CLKS_MASK;
5412                         mpll_ss2 |= CLKS(clks);
5413                 }
5414         }
5415
5416         mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
5417         mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed);
5418
5419         if (dll_state_on)
5420                 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB;
5421         else
5422                 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
5423
5424         mclk->mclk_value = cpu_to_be32(memory_clock);
5425         mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl);
5426         mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1);
5427         mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2);
5428         mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
5429         mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
5430         mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
5431         mclk->vDLL_CNTL = cpu_to_be32(dll_cntl);
5432         mclk->vMPLL_SS = cpu_to_be32(mpll_ss1);
5433         mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2);
5434
5435         return 0;
5436 }
5437
5438 static void si_populate_smc_sp(struct amdgpu_device *adev,
5439                                struct amdgpu_ps *amdgpu_state,
5440                                SISLANDS_SMC_SWSTATE *smc_state)
5441 {
5442         struct  si_ps *ps = si_get_ps(amdgpu_state);
5443         struct rv7xx_power_info *pi = rv770_get_pi(adev);
5444         int i;
5445
5446         for (i = 0; i < ps->performance_level_count - 1; i++)
5447                 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);
5448
5449         smc_state->levels[ps->performance_level_count - 1].bSP =
5450                 cpu_to_be32(pi->psp);
5451 }
5452
5453 static int si_convert_power_level_to_smc(struct amdgpu_device *adev,
5454                                          struct rv7xx_pl *pl,
5455                                          SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level)
5456 {
5457         struct rv7xx_power_info *pi = rv770_get_pi(adev);
5458         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5459         struct si_power_info *si_pi = si_get_pi(adev);
5460         int ret;
5461         bool dll_state_on;
5462         u16 std_vddc;
5463         bool gmc_pg = false;
5464
5465         if (eg_pi->pcie_performance_request &&
5466             (si_pi->force_pcie_gen != AMDGPU_PCIE_GEN_INVALID))
5467                 level->gen2PCIE = (u8)si_pi->force_pcie_gen;
5468         else
5469                 level->gen2PCIE = (u8)pl->pcie_gen;
5470
5471         ret = si_populate_sclk_value(adev, pl->sclk, &level->sclk);
5472         if (ret)
5473                 return ret;
5474
5475         level->mcFlags =  0;
5476
5477         if (pi->mclk_stutter_mode_threshold &&
5478             (pl->mclk <= pi->mclk_stutter_mode_threshold) &&
5479             !eg_pi->uvd_enabled &&
5480             (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
5481             (adev->pm.dpm.new_active_crtc_count <= 2)) {
5482                 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN;
5483
5484                 if (gmc_pg)
5485                         level->mcFlags |= SISLANDS_SMC_MC_PG_EN;
5486         }
5487
5488         if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
5489                 if (pl->mclk > pi->mclk_edc_enable_threshold)
5490                         level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG;
5491
5492                 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)
5493                         level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG;
5494
5495                 level->strobeMode = si_get_strobe_mode_settings(adev, pl->mclk);
5496
5497                 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) {
5498                         if (si_get_mclk_frequency_ratio(pl->mclk, true) >=
5499                             ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
5500                                 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5501                         else
5502                                 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
5503                 } else {
5504                         dll_state_on = false;
5505                 }
5506         } else {
5507                 level->strobeMode = si_get_strobe_mode_settings(adev,
5508                                                                 pl->mclk);
5509
5510                 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5511         }
5512
5513         ret = si_populate_mclk_value(adev,
5514                                      pl->sclk,
5515                                      pl->mclk,
5516                                      &level->mclk,
5517                                      (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on);
5518         if (ret)
5519                 return ret;
5520
5521         ret = si_populate_voltage_value(adev,
5522                                         &eg_pi->vddc_voltage_table,
5523                                         pl->vddc, &level->vddc);
5524         if (ret)
5525                 return ret;
5526
5527
5528         ret = si_get_std_voltage_value(adev, &level->vddc, &std_vddc);
5529         if (ret)
5530                 return ret;
5531
5532         ret = si_populate_std_voltage_value(adev, std_vddc,
5533                                             level->vddc.index, &level->std_vddc);
5534         if (ret)
5535                 return ret;
5536
5537         if (eg_pi->vddci_control) {
5538                 ret = si_populate_voltage_value(adev, &eg_pi->vddci_voltage_table,
5539                                                 pl->vddci, &level->vddci);
5540                 if (ret)
5541                         return ret;
5542         }
5543
5544         if (si_pi->vddc_phase_shed_control) {
5545                 ret = si_populate_phase_shedding_value(adev,
5546                                                        &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
5547                                                        pl->vddc,
5548                                                        pl->sclk,
5549                                                        pl->mclk,
5550                                                        &level->vddc);
5551                 if (ret)
5552                         return ret;
5553         }
5554
5555         level->MaxPoweredUpCU = si_pi->max_cu;
5556
5557         ret = si_populate_mvdd_value(adev, pl->mclk, &level->mvdd);
5558
5559         return ret;
5560 }
5561
5562 static int si_populate_smc_t(struct amdgpu_device *adev,
5563                              struct amdgpu_ps *amdgpu_state,
5564                              SISLANDS_SMC_SWSTATE *smc_state)
5565 {
5566         struct rv7xx_power_info *pi = rv770_get_pi(adev);
5567         struct  si_ps *state = si_get_ps(amdgpu_state);
5568         u32 a_t;
5569         u32 t_l, t_h;
5570         u32 high_bsp;
5571         int i, ret;
5572
5573         if (state->performance_level_count >= 9)
5574                 return -EINVAL;
5575
5576         if (state->performance_level_count < 2) {
5577                 a_t = CG_R(0xffff) | CG_L(0);
5578                 smc_state->levels[0].aT = cpu_to_be32(a_t);
5579                 return 0;
5580         }
5581
5582         smc_state->levels[0].aT = cpu_to_be32(0);
5583
5584         for (i = 0; i <= state->performance_level_count - 2; i++) {
5585                 ret = r600_calculate_at(
5586                         (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1),
5587                         100 * R600_AH_DFLT,
5588                         state->performance_levels[i + 1].sclk,
5589                         state->performance_levels[i].sclk,
5590                         &t_l,
5591                         &t_h);
5592
5593                 if (ret) {
5594                         t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT;
5595                         t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT;
5596                 }
5597
5598                 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK;
5599                 a_t |= CG_R(t_l * pi->bsp / 20000);
5600                 smc_state->levels[i].aT = cpu_to_be32(a_t);
5601
5602                 high_bsp = (i == state->performance_level_count - 2) ?
5603                         pi->pbsp : pi->bsp;
5604                 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000);
5605                 smc_state->levels[i + 1].aT = cpu_to_be32(a_t);
5606         }
5607
5608         return 0;
5609 }
5610
5611 static int si_disable_ulv(struct amdgpu_device *adev)
5612 {
5613         struct si_power_info *si_pi = si_get_pi(adev);
5614         struct si_ulv_param *ulv = &si_pi->ulv;
5615
5616         if (ulv->supported)
5617                 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
5618                         0 : -EINVAL;
5619
5620         return 0;
5621 }
5622
5623 static bool si_is_state_ulv_compatible(struct amdgpu_device *adev,
5624                                        struct amdgpu_ps *amdgpu_state)
5625 {
5626         const struct si_power_info *si_pi = si_get_pi(adev);
5627         const struct si_ulv_param *ulv = &si_pi->ulv;
5628         const struct  si_ps *state = si_get_ps(amdgpu_state);
5629         int i;
5630
5631         if (state->performance_levels[0].mclk != ulv->pl.mclk)
5632                 return false;
5633
5634         /* XXX validate against display requirements! */
5635
5636         for (i = 0; i < adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) {
5637                 if (adev->clock.current_dispclk <=
5638                     adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) {
5639                         if (ulv->pl.vddc <
5640                             adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v)
5641                                 return false;
5642                 }
5643         }
5644
5645         if ((amdgpu_state->vclk != 0) || (amdgpu_state->dclk != 0))
5646                 return false;
5647
5648         return true;
5649 }
5650
5651 static int si_set_power_state_conditionally_enable_ulv(struct amdgpu_device *adev,
5652                                                        struct amdgpu_ps *amdgpu_new_state)
5653 {
5654         const struct si_power_info *si_pi = si_get_pi(adev);
5655         const struct si_ulv_param *ulv = &si_pi->ulv;
5656
5657         if (ulv->supported) {
5658                 if (si_is_state_ulv_compatible(adev, amdgpu_new_state))
5659                         return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
5660                                 0 : -EINVAL;
5661         }
5662         return 0;
5663 }
5664
5665 static int si_convert_power_state_to_smc(struct amdgpu_device *adev,
5666                                          struct amdgpu_ps *amdgpu_state,
5667                                          SISLANDS_SMC_SWSTATE *smc_state)
5668 {
5669         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5670         struct ni_power_info *ni_pi = ni_get_pi(adev);
5671         struct si_power_info *si_pi = si_get_pi(adev);
5672         struct  si_ps *state = si_get_ps(amdgpu_state);
5673         int i, ret;
5674         u32 threshold;
5675         u32 sclk_in_sr = 1350; /* ??? */
5676
5677         if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS)
5678                 return -EINVAL;
5679
5680         threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100;
5681
5682         if (amdgpu_state->vclk && amdgpu_state->dclk) {
5683                 eg_pi->uvd_enabled = true;
5684                 if (eg_pi->smu_uvd_hs)
5685                         smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD;
5686         } else {
5687                 eg_pi->uvd_enabled = false;
5688         }
5689
5690         if (state->dc_compatible)
5691                 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC;
5692
5693         smc_state->levelCount = 0;
5694         for (i = 0; i < state->performance_level_count; i++) {
5695                 if (eg_pi->sclk_deep_sleep) {
5696                         if ((i == 0) || si_pi->sclk_deep_sleep_above_low) {
5697                                 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
5698                                         smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
5699                                 else
5700                                         smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
5701                         }
5702                 }
5703
5704                 ret = si_convert_power_level_to_smc(adev, &state->performance_levels[i],
5705                                                     &smc_state->levels[i]);
5706                 smc_state->levels[i].arbRefreshState =
5707                         (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i);
5708
5709                 if (ret)
5710                         return ret;
5711
5712                 if (ni_pi->enable_power_containment)
5713                         smc_state->levels[i].displayWatermark =
5714                                 (state->performance_levels[i].sclk < threshold) ?
5715                                 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5716                 else
5717                         smc_state->levels[i].displayWatermark = (i < 2) ?
5718                                 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5719
5720                 if (eg_pi->dynamic_ac_timing)
5721                         smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i;
5722                 else
5723                         smc_state->levels[i].ACIndex = 0;
5724
5725                 smc_state->levelCount++;
5726         }
5727
5728         si_write_smc_soft_register(adev,
5729                                    SI_SMC_SOFT_REGISTER_watermark_threshold,
5730                                    threshold / 512);
5731
5732         si_populate_smc_sp(adev, amdgpu_state, smc_state);
5733
5734         ret = si_populate_power_containment_values(adev, amdgpu_state, smc_state);
5735         if (ret)
5736                 ni_pi->enable_power_containment = false;
5737
5738         ret = si_populate_sq_ramping_values(adev, amdgpu_state, smc_state);
5739         if (ret)
5740                 ni_pi->enable_sq_ramping = false;
5741
5742         return si_populate_smc_t(adev, amdgpu_state, smc_state);
5743 }
5744
5745 static int si_upload_sw_state(struct amdgpu_device *adev,
5746                               struct amdgpu_ps *amdgpu_new_state)
5747 {
5748         struct si_power_info *si_pi = si_get_pi(adev);
5749         struct  si_ps *new_state = si_get_ps(amdgpu_new_state);
5750         int ret;
5751         u32 address = si_pi->state_table_start +
5752                 offsetof(SISLANDS_SMC_STATETABLE, driverState);
5753         u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) +
5754                 ((new_state->performance_level_count - 1) *
5755                  sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL));
5756         SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState;
5757
5758         memset(smc_state, 0, state_size);
5759
5760         ret = si_convert_power_state_to_smc(adev, amdgpu_new_state, smc_state);
5761         if (ret)
5762                 return ret;
5763
5764         return amdgpu_si_copy_bytes_to_smc(adev, address, (u8 *)smc_state,
5765                                            state_size, si_pi->sram_end);
5766 }
5767
5768 static int si_upload_ulv_state(struct amdgpu_device *adev)
5769 {
5770         struct si_power_info *si_pi = si_get_pi(adev);
5771         struct si_ulv_param *ulv = &si_pi->ulv;
5772         int ret = 0;
5773
5774         if (ulv->supported && ulv->pl.vddc) {
5775                 u32 address = si_pi->state_table_start +
5776                         offsetof(SISLANDS_SMC_STATETABLE, ULVState);
5777                 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState;
5778                 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE);
5779
5780                 memset(smc_state, 0, state_size);
5781
5782                 ret = si_populate_ulv_state(adev, smc_state);
5783                 if (!ret)
5784                         ret = amdgpu_si_copy_bytes_to_smc(adev, address, (u8 *)smc_state,
5785                                                           state_size, si_pi->sram_end);
5786         }
5787
5788         return ret;
5789 }
5790
5791 static int si_upload_smc_data(struct amdgpu_device *adev)
5792 {
5793         struct amdgpu_crtc *amdgpu_crtc = NULL;
5794         int i;
5795
5796         if (adev->pm.dpm.new_active_crtc_count == 0)
5797                 return 0;
5798
5799         for (i = 0; i < adev->mode_info.num_crtc; i++) {
5800                 if (adev->pm.dpm.new_active_crtcs & (1 << i)) {
5801                         amdgpu_crtc = adev->mode_info.crtcs[i];
5802                         break;
5803                 }
5804         }
5805
5806         if (amdgpu_crtc == NULL)
5807                 return 0;
5808
5809         if (amdgpu_crtc->line_time <= 0)
5810                 return 0;
5811
5812         if (si_write_smc_soft_register(adev,
5813                                        SI_SMC_SOFT_REGISTER_crtc_index,
5814                                        amdgpu_crtc->crtc_id) != PPSMC_Result_OK)
5815                 return 0;
5816
5817         if (si_write_smc_soft_register(adev,
5818                                        SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min,
5819                                        amdgpu_crtc->wm_high / amdgpu_crtc->line_time) != PPSMC_Result_OK)
5820                 return 0;
5821
5822         if (si_write_smc_soft_register(adev,
5823                                        SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max,
5824                                        amdgpu_crtc->wm_low / amdgpu_crtc->line_time) != PPSMC_Result_OK)
5825                 return 0;
5826
5827         return 0;
5828 }
5829
5830 static int si_set_mc_special_registers(struct amdgpu_device *adev,
5831                                        struct si_mc_reg_table *table)
5832 {
5833         u8 i, j, k;
5834         u32 temp_reg;
5835
5836         for (i = 0, j = table->last; i < table->last; i++) {
5837                 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5838                         return -EINVAL;
5839                 switch (table->mc_reg_address[i].s1) {
5840                 case MC_SEQ_MISC1:
5841                         temp_reg = RREG32(MC_PMG_CMD_EMRS);
5842                         table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS;
5843                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP;
5844                         for (k = 0; k < table->num_entries; k++)
5845                                 table->mc_reg_table_entry[k].mc_data[j] =
5846                                         ((temp_reg & 0xffff0000)) |
5847                                         ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
5848                         j++;
5849                         if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5850                                 return -EINVAL;
5851
5852                         temp_reg = RREG32(MC_PMG_CMD_MRS);
5853                         table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS;
5854                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP;
5855                         for (k = 0; k < table->num_entries; k++) {
5856                                 table->mc_reg_table_entry[k].mc_data[j] =
5857                                         (temp_reg & 0xffff0000) |
5858                                         (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5859                                 if (adev->mc.vram_type != AMDGPU_VRAM_TYPE_GDDR5)
5860                                         table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
5861                         }
5862                         j++;
5863                         if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5864                                 return -EINVAL;
5865
5866                         if (adev->mc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) {
5867                                 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD;
5868                                 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD;
5869                                 for (k = 0; k < table->num_entries; k++)
5870                                         table->mc_reg_table_entry[k].mc_data[j] =
5871                                                 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
5872                                 j++;
5873                                 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5874                                         return -EINVAL;
5875                         }
5876                         break;
5877                 case MC_SEQ_RESERVE_M:
5878                         temp_reg = RREG32(MC_PMG_CMD_MRS1);
5879                         table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1;
5880                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP;
5881                         for(k = 0; k < table->num_entries; k++)
5882                                 table->mc_reg_table_entry[k].mc_data[j] =
5883                                         (temp_reg & 0xffff0000) |
5884                                         (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5885                         j++;
5886                         if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5887                                 return -EINVAL;
5888                         break;
5889                 default:
5890                         break;
5891                 }
5892         }
5893
5894         table->last = j;
5895
5896         return 0;
5897 }
5898
5899 static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
5900 {
5901         bool result = true;
5902         switch (in_reg) {
5903         case  MC_SEQ_RAS_TIMING:
5904                 *out_reg = MC_SEQ_RAS_TIMING_LP;
5905                 break;
5906         case MC_SEQ_CAS_TIMING:
5907                 *out_reg = MC_SEQ_CAS_TIMING_LP;
5908                 break;
5909         case MC_SEQ_MISC_TIMING:
5910                 *out_reg = MC_SEQ_MISC_TIMING_LP;
5911                 break;
5912         case MC_SEQ_MISC_TIMING2:
5913                 *out_reg = MC_SEQ_MISC_TIMING2_LP;
5914                 break;
5915         case MC_SEQ_RD_CTL_D0:
5916                 *out_reg = MC_SEQ_RD_CTL_D0_LP;
5917                 break;
5918         case MC_SEQ_RD_CTL_D1:
5919                 *out_reg = MC_SEQ_RD_CTL_D1_LP;
5920                 break;
5921         case MC_SEQ_WR_CTL_D0:
5922                 *out_reg = MC_SEQ_WR_CTL_D0_LP;
5923                 break;
5924         case MC_SEQ_WR_CTL_D1:
5925                 *out_reg = MC_SEQ_WR_CTL_D1_LP;
5926                 break;
5927         case MC_PMG_CMD_EMRS:
5928                 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP;
5929                 break;
5930         case MC_PMG_CMD_MRS:
5931                 *out_reg = MC_SEQ_PMG_CMD_MRS_LP;
5932                 break;
5933         case MC_PMG_CMD_MRS1:
5934                 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP;
5935                 break;
5936         case MC_SEQ_PMG_TIMING:
5937                 *out_reg = MC_SEQ_PMG_TIMING_LP;
5938                 break;
5939         case MC_PMG_CMD_MRS2:
5940                 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP;
5941                 break;
5942         case MC_SEQ_WR_CTL_2:
5943                 *out_reg = MC_SEQ_WR_CTL_2_LP;
5944                 break;
5945         default:
5946                 result = false;
5947                 break;
5948         }
5949
5950         return result;
5951 }
5952
5953 static void si_set_valid_flag(struct si_mc_reg_table *table)
5954 {
5955         u8 i, j;
5956
5957         for (i = 0; i < table->last; i++) {
5958                 for (j = 1; j < table->num_entries; j++) {
5959                         if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) {
5960                                 table->valid_flag |= 1 << i;
5961                                 break;
5962                         }
5963                 }
5964         }
5965 }
5966
5967 static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table)
5968 {
5969         u32 i;
5970         u16 address;
5971
5972         for (i = 0; i < table->last; i++)
5973                 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
5974                         address : table->mc_reg_address[i].s1;
5975
5976 }
5977
5978 static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table,
5979                                       struct si_mc_reg_table *si_table)
5980 {
5981         u8 i, j;
5982
5983         if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5984                 return -EINVAL;
5985         if (table->num_entries > MAX_AC_TIMING_ENTRIES)
5986                 return -EINVAL;
5987
5988         for (i = 0; i < table->last; i++)
5989                 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
5990         si_table->last = table->last;
5991
5992         for (i = 0; i < table->num_entries; i++) {
5993                 si_table->mc_reg_table_entry[i].mclk_max =
5994                         table->mc_reg_table_entry[i].mclk_max;
5995                 for (j = 0; j < table->last; j++) {
5996                         si_table->mc_reg_table_entry[i].mc_data[j] =
5997                                 table->mc_reg_table_entry[i].mc_data[j];
5998                 }
5999         }
6000         si_table->num_entries = table->num_entries;
6001
6002         return 0;
6003 }
6004
6005 static int si_initialize_mc_reg_table(struct amdgpu_device *adev)
6006 {
6007         struct si_power_info *si_pi = si_get_pi(adev);
6008         struct atom_mc_reg_table *table;
6009         struct si_mc_reg_table *si_table = &si_pi->mc_reg_table;
6010         u8 module_index = rv770_get_memory_module_index(adev);
6011         int ret;
6012
6013         table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
6014         if (!table)
6015                 return -ENOMEM;
6016
6017         WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
6018         WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
6019         WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
6020         WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
6021         WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
6022         WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
6023         WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
6024         WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
6025         WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
6026         WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
6027         WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
6028         WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
6029         WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
6030         WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
6031
6032         ret = amdgpu_atombios_init_mc_reg_table(adev, module_index, table);
6033         if (ret)
6034                 goto init_mc_done;
6035
6036         ret = si_copy_vbios_mc_reg_table(table, si_table);
6037         if (ret)
6038                 goto init_mc_done;
6039
6040         si_set_s0_mc_reg_index(si_table);
6041
6042         ret = si_set_mc_special_registers(adev, si_table);
6043         if (ret)
6044                 goto init_mc_done;
6045
6046         si_set_valid_flag(si_table);
6047
6048 init_mc_done:
6049         kfree(table);
6050
6051         return ret;
6052
6053 }
6054
6055 static void si_populate_mc_reg_addresses(struct amdgpu_device *adev,
6056                                          SMC_SIslands_MCRegisters *mc_reg_table)
6057 {
6058         struct si_power_info *si_pi = si_get_pi(adev);
6059         u32 i, j;
6060
6061         for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) {
6062                 if (si_pi->mc_reg_table.valid_flag & (1 << j)) {
6063                         if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
6064                                 break;
6065                         mc_reg_table->address[i].s0 =
6066                                 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0);
6067                         mc_reg_table->address[i].s1 =
6068                                 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1);
6069                         i++;
6070                 }
6071         }
6072         mc_reg_table->last = (u8)i;
6073 }
6074
6075 static void si_convert_mc_registers(const struct si_mc_reg_entry *entry,
6076                                     SMC_SIslands_MCRegisterSet *data,
6077                                     u32 num_entries, u32 valid_flag)
6078 {
6079         u32 i, j;
6080
6081         for(i = 0, j = 0; j < num_entries; j++) {
6082                 if (valid_flag & (1 << j)) {
6083                         data->value[i] = cpu_to_be32(entry->mc_data[j]);
6084                         i++;
6085                 }
6086         }
6087 }
6088
6089 static void si_convert_mc_reg_table_entry_to_smc(struct amdgpu_device *adev,
6090                                                  struct rv7xx_pl *pl,
6091                                                  SMC_SIslands_MCRegisterSet *mc_reg_table_data)
6092 {
6093         struct si_power_info *si_pi = si_get_pi(adev);
6094         u32 i = 0;
6095
6096         for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) {
6097                 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
6098                         break;
6099         }
6100
6101         if ((i == si_pi->mc_reg_table.num_entries) && (i > 0))
6102                 --i;
6103
6104         si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i],
6105                                 mc_reg_table_data, si_pi->mc_reg_table.last,
6106                                 si_pi->mc_reg_table.valid_flag);
6107 }
6108
6109 static void si_convert_mc_reg_table_to_smc(struct amdgpu_device *adev,
6110                                            struct amdgpu_ps *amdgpu_state,
6111                                            SMC_SIslands_MCRegisters *mc_reg_table)
6112 {
6113         struct si_ps *state = si_get_ps(amdgpu_state);
6114         int i;
6115
6116         for (i = 0; i < state->performance_level_count; i++) {
6117                 si_convert_mc_reg_table_entry_to_smc(adev,
6118                                                      &state->performance_levels[i],
6119                                                      &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]);
6120         }
6121 }
6122
6123 static int si_populate_mc_reg_table(struct amdgpu_device *adev,
6124                                     struct amdgpu_ps *amdgpu_boot_state)
6125 {
6126         struct  si_ps *boot_state = si_get_ps(amdgpu_boot_state);
6127         struct si_power_info *si_pi = si_get_pi(adev);
6128         struct si_ulv_param *ulv = &si_pi->ulv;
6129         SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
6130
6131         memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
6132
6133         si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_seq_index, 1);
6134
6135         si_populate_mc_reg_addresses(adev, smc_mc_reg_table);
6136
6137         si_convert_mc_reg_table_entry_to_smc(adev, &boot_state->performance_levels[0],
6138                                              &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]);
6139
6140         si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
6141                                 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT],
6142                                 si_pi->mc_reg_table.last,
6143                                 si_pi->mc_reg_table.valid_flag);
6144
6145         if (ulv->supported && ulv->pl.vddc != 0)
6146                 si_convert_mc_reg_table_entry_to_smc(adev, &ulv->pl,
6147                                                      &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]);
6148         else
6149                 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
6150                                         &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT],
6151                                         si_pi->mc_reg_table.last,
6152                                         si_pi->mc_reg_table.valid_flag);
6153
6154         si_convert_mc_reg_table_to_smc(adev, amdgpu_boot_state, smc_mc_reg_table);
6155
6156         return amdgpu_si_copy_bytes_to_smc(adev, si_pi->mc_reg_table_start,
6157                                            (u8 *)smc_mc_reg_table,
6158                                            sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end);
6159 }
6160
6161 static int si_upload_mc_reg_table(struct amdgpu_device *adev,
6162                                   struct amdgpu_ps *amdgpu_new_state)
6163 {
6164         struct si_ps *new_state = si_get_ps(amdgpu_new_state);
6165         struct si_power_info *si_pi = si_get_pi(adev);
6166         u32 address = si_pi->mc_reg_table_start +
6167                 offsetof(SMC_SIslands_MCRegisters,
6168                          data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]);
6169         SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
6170
6171         memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
6172
6173         si_convert_mc_reg_table_to_smc(adev, amdgpu_new_state, smc_mc_reg_table);
6174
6175         return amdgpu_si_copy_bytes_to_smc(adev, address,
6176                                            (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT],
6177                                            sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count,
6178                                            si_pi->sram_end);
6179 }
6180
6181 static void si_enable_voltage_control(struct amdgpu_device *adev, bool enable)
6182 {
6183         if (enable)
6184                 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN);
6185         else
6186                 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN);
6187 }
6188
6189 static enum amdgpu_pcie_gen si_get_maximum_link_speed(struct amdgpu_device *adev,
6190                                                       struct amdgpu_ps *amdgpu_state)
6191 {
6192         struct si_ps *state = si_get_ps(amdgpu_state);
6193         int i;
6194         u16 pcie_speed, max_speed = 0;
6195
6196         for (i = 0; i < state->performance_level_count; i++) {
6197                 pcie_speed = state->performance_levels[i].pcie_gen;
6198                 if (max_speed < pcie_speed)
6199                         max_speed = pcie_speed;
6200         }
6201         return max_speed;
6202 }
6203
6204 static u16 si_get_current_pcie_speed(struct amdgpu_device *adev)
6205 {
6206         u32 speed_cntl;
6207
6208         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK;
6209         speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT;
6210
6211         return (u16)speed_cntl;
6212 }
6213
6214 static void si_request_link_speed_change_before_state_change(struct amdgpu_device *adev,
6215                                                              struct amdgpu_ps *amdgpu_new_state,
6216                                                              struct amdgpu_ps *amdgpu_current_state)
6217 {
6218         struct si_power_info *si_pi = si_get_pi(adev);
6219         enum amdgpu_pcie_gen target_link_speed = si_get_maximum_link_speed(adev, amdgpu_new_state);
6220         enum amdgpu_pcie_gen current_link_speed;
6221
6222         if (si_pi->force_pcie_gen == AMDGPU_PCIE_GEN_INVALID)
6223                 current_link_speed = si_get_maximum_link_speed(adev, amdgpu_current_state);
6224         else
6225                 current_link_speed = si_pi->force_pcie_gen;
6226
6227         si_pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
6228         si_pi->pspp_notify_required = false;
6229         if (target_link_speed > current_link_speed) {
6230                 switch (target_link_speed) {
6231 #if defined(CONFIG_ACPI)
6232                 case AMDGPU_PCIE_GEN3:
6233                         if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
6234                                 break;
6235                         si_pi->force_pcie_gen = AMDGPU_PCIE_GEN2;
6236                         if (current_link_speed == AMDGPU_PCIE_GEN2)
6237                                 break;
6238                 case AMDGPU_PCIE_GEN2:
6239                         if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
6240                                 break;
6241 #endif
6242                 default:
6243                         si_pi->force_pcie_gen = si_get_current_pcie_speed(adev);
6244                         break;
6245                 }
6246         } else {
6247                 if (target_link_speed < current_link_speed)
6248                         si_pi->pspp_notify_required = true;
6249         }
6250 }
6251
6252 static void si_notify_link_speed_change_after_state_change(struct amdgpu_device *adev,
6253                                                            struct amdgpu_ps *amdgpu_new_state,
6254                                                            struct amdgpu_ps *amdgpu_current_state)
6255 {
6256         struct si_power_info *si_pi = si_get_pi(adev);
6257         enum amdgpu_pcie_gen target_link_speed = si_get_maximum_link_speed(adev, amdgpu_new_state);
6258         u8 request;
6259
6260         if (si_pi->pspp_notify_required) {
6261                 if (target_link_speed == AMDGPU_PCIE_GEN3)
6262                         request = PCIE_PERF_REQ_PECI_GEN3;
6263                 else if (target_link_speed == AMDGPU_PCIE_GEN2)
6264                         request = PCIE_PERF_REQ_PECI_GEN2;
6265                 else
6266                         request = PCIE_PERF_REQ_PECI_GEN1;
6267
6268                 if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
6269                     (si_get_current_pcie_speed(adev) > 0))
6270                         return;
6271
6272 #if defined(CONFIG_ACPI)
6273                 amdgpu_acpi_pcie_performance_request(adev, request, false);
6274 #endif
6275         }
6276 }
6277
6278 #if 0
6279 static int si_ds_request(struct amdgpu_device *adev,
6280                          bool ds_status_on, u32 count_write)
6281 {
6282         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6283
6284         if (eg_pi->sclk_deep_sleep) {
6285                 if (ds_status_on)
6286                         return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) ==
6287                                 PPSMC_Result_OK) ?
6288                                 0 : -EINVAL;
6289                 else
6290                         return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_ThrottleOVRDSCLKDS) ==
6291                                 PPSMC_Result_OK) ? 0 : -EINVAL;
6292         }
6293         return 0;
6294 }
6295 #endif
6296
6297 static void si_set_max_cu_value(struct amdgpu_device *adev)
6298 {
6299         struct si_power_info *si_pi = si_get_pi(adev);
6300
6301         if (adev->asic_type == CHIP_VERDE) {
6302                 switch (adev->pdev->device) {
6303                 case 0x6820:
6304                 case 0x6825:
6305                 case 0x6821:
6306                 case 0x6823:
6307                 case 0x6827:
6308                         si_pi->max_cu = 10;
6309                         break;
6310                 case 0x682D:
6311                 case 0x6824:
6312                 case 0x682F:
6313                 case 0x6826:
6314                         si_pi->max_cu = 8;
6315                         break;
6316                 case 0x6828:
6317                 case 0x6830:
6318                 case 0x6831:
6319                 case 0x6838:
6320                 case 0x6839:
6321                 case 0x683D:
6322                         si_pi->max_cu = 10;
6323                         break;
6324                 case 0x683B:
6325                 case 0x683F:
6326                 case 0x6829:
6327                         si_pi->max_cu = 8;
6328                         break;
6329                 default:
6330                         si_pi->max_cu = 0;
6331                         break;
6332                 }
6333         } else {
6334                 si_pi->max_cu = 0;
6335         }
6336 }
6337
6338 static int si_patch_single_dependency_table_based_on_leakage(struct amdgpu_device *adev,
6339                                                              struct amdgpu_clock_voltage_dependency_table *table)
6340 {
6341         u32 i;
6342         int j;
6343         u16 leakage_voltage;
6344
6345         if (table) {
6346                 for (i = 0; i < table->count; i++) {
6347                         switch (si_get_leakage_voltage_from_leakage_index(adev,
6348                                                                           table->entries[i].v,
6349                                                                           &leakage_voltage)) {
6350                         case 0:
6351                                 table->entries[i].v = leakage_voltage;
6352                                 break;
6353                         case -EAGAIN:
6354                                 return -EINVAL;
6355                         case -EINVAL:
6356                         default:
6357                                 break;
6358                         }
6359                 }
6360
6361                 for (j = (table->count - 2); j >= 0; j--) {
6362                         table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ?
6363                                 table->entries[j].v : table->entries[j + 1].v;
6364                 }
6365         }
6366         return 0;
6367 }
6368
6369 static int si_patch_dependency_tables_based_on_leakage(struct amdgpu_device *adev)
6370 {
6371         int ret = 0;
6372
6373         ret = si_patch_single_dependency_table_based_on_leakage(adev,
6374                                                                 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
6375         if (ret)
6376                 DRM_ERROR("Could not patch vddc_on_sclk leakage table\n");
6377         ret = si_patch_single_dependency_table_based_on_leakage(adev,
6378                                                                 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
6379         if (ret)
6380                 DRM_ERROR("Could not patch vddc_on_mclk leakage table\n");
6381         ret = si_patch_single_dependency_table_based_on_leakage(adev,
6382                                                                 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
6383         if (ret)
6384                 DRM_ERROR("Could not patch vddci_on_mclk leakage table\n");
6385         return ret;
6386 }
6387
6388 static void si_set_pcie_lane_width_in_smc(struct amdgpu_device *adev,
6389                                           struct amdgpu_ps *amdgpu_new_state,
6390                                           struct amdgpu_ps *amdgpu_current_state)
6391 {
6392         u32 lane_width;
6393         u32 new_lane_width =
6394                 (amdgpu_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
6395         u32 current_lane_width =
6396                 (amdgpu_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
6397
6398         if (new_lane_width != current_lane_width) {
6399                 amdgpu_set_pcie_lanes(adev, new_lane_width);
6400                 lane_width = amdgpu_get_pcie_lanes(adev);
6401                 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
6402         }
6403 }
6404
6405 static void si_dpm_setup_asic(struct amdgpu_device *adev)
6406 {
6407         si_read_clock_registers(adev);
6408         si_enable_acpi_power_management(adev);
6409 }
6410
6411 static int si_thermal_enable_alert(struct amdgpu_device *adev,
6412                                    bool enable)
6413 {
6414         u32 thermal_int = RREG32(CG_THERMAL_INT);
6415
6416         if (enable) {
6417                 PPSMC_Result result;
6418
6419                 thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
6420                 WREG32(CG_THERMAL_INT, thermal_int);
6421                 result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt);
6422                 if (result != PPSMC_Result_OK) {
6423                         DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
6424                         return -EINVAL;
6425                 }
6426         } else {
6427                 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
6428                 WREG32(CG_THERMAL_INT, thermal_int);
6429         }
6430
6431         return 0;
6432 }
6433
6434 static int si_thermal_set_temperature_range(struct amdgpu_device *adev,
6435                                             int min_temp, int max_temp)
6436 {
6437         int low_temp = 0 * 1000;
6438         int high_temp = 255 * 1000;
6439
6440         if (low_temp < min_temp)
6441                 low_temp = min_temp;
6442         if (high_temp > max_temp)
6443                 high_temp = max_temp;
6444         if (high_temp < low_temp) {
6445                 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
6446                 return -EINVAL;
6447         }
6448
6449         WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK);
6450         WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK);
6451         WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK);
6452
6453         adev->pm.dpm.thermal.min_temp = low_temp;
6454         adev->pm.dpm.thermal.max_temp = high_temp;
6455
6456         return 0;
6457 }
6458
6459 static void si_fan_ctrl_set_static_mode(struct amdgpu_device *adev, u32 mode)
6460 {
6461         struct si_power_info *si_pi = si_get_pi(adev);
6462         u32 tmp;
6463
6464         if (si_pi->fan_ctrl_is_in_default_mode) {
6465                 tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT;
6466                 si_pi->fan_ctrl_default_mode = tmp;
6467                 tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT;
6468                 si_pi->t_min = tmp;
6469                 si_pi->fan_ctrl_is_in_default_mode = false;
6470         }
6471
6472         tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6473         tmp |= TMIN(0);
6474         WREG32(CG_FDO_CTRL2, tmp);
6475
6476         tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6477         tmp |= FDO_PWM_MODE(mode);
6478         WREG32(CG_FDO_CTRL2, tmp);
6479 }
6480
6481 static int si_thermal_setup_fan_table(struct amdgpu_device *adev)
6482 {
6483         struct si_power_info *si_pi = si_get_pi(adev);
6484         PP_SIslands_FanTable fan_table = { FDO_MODE_HARDWARE };
6485         u32 duty100;
6486         u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2;
6487         u16 fdo_min, slope1, slope2;
6488         u32 reference_clock, tmp;
6489         int ret;
6490         u64 tmp64;
6491
6492         if (!si_pi->fan_table_start) {
6493                 adev->pm.dpm.fan.ucode_fan_control = false;
6494                 return 0;
6495         }
6496
6497         duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6498
6499         if (duty100 == 0) {
6500                 adev->pm.dpm.fan.ucode_fan_control = false;
6501                 return 0;
6502         }
6503
6504         tmp64 = (u64)adev->pm.dpm.fan.pwm_min * duty100;
6505         do_div(tmp64, 10000);
6506         fdo_min = (u16)tmp64;
6507
6508         t_diff1 = adev->pm.dpm.fan.t_med - adev->pm.dpm.fan.t_min;
6509         t_diff2 = adev->pm.dpm.fan.t_high - adev->pm.dpm.fan.t_med;
6510
6511         pwm_diff1 = adev->pm.dpm.fan.pwm_med - adev->pm.dpm.fan.pwm_min;
6512         pwm_diff2 = adev->pm.dpm.fan.pwm_high - adev->pm.dpm.fan.pwm_med;
6513
6514         slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
6515         slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
6516
6517         fan_table.temp_min = cpu_to_be16((50 + adev->pm.dpm.fan.t_min) / 100);
6518         fan_table.temp_med = cpu_to_be16((50 + adev->pm.dpm.fan.t_med) / 100);
6519         fan_table.temp_max = cpu_to_be16((50 + adev->pm.dpm.fan.t_max) / 100);
6520         fan_table.slope1 = cpu_to_be16(slope1);
6521         fan_table.slope2 = cpu_to_be16(slope2);
6522         fan_table.fdo_min = cpu_to_be16(fdo_min);
6523         fan_table.hys_down = cpu_to_be16(adev->pm.dpm.fan.t_hyst);
6524         fan_table.hys_up = cpu_to_be16(1);
6525         fan_table.hys_slope = cpu_to_be16(1);
6526         fan_table.temp_resp_lim = cpu_to_be16(5);
6527         reference_clock = amdgpu_asic_get_xclk(adev);
6528
6529         fan_table.refresh_period = cpu_to_be32((adev->pm.dpm.fan.cycle_delay *
6530                                                 reference_clock) / 1600);
6531         fan_table.fdo_max = cpu_to_be16((u16)duty100);
6532
6533         tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT;
6534         fan_table.temp_src = (uint8_t)tmp;
6535
6536         ret = amdgpu_si_copy_bytes_to_smc(adev,
6537                                           si_pi->fan_table_start,
6538                                           (u8 *)(&fan_table),
6539                                           sizeof(fan_table),
6540                                           si_pi->sram_end);
6541
6542         if (ret) {
6543                 DRM_ERROR("Failed to load fan table to the SMC.");
6544                 adev->pm.dpm.fan.ucode_fan_control = false;
6545         }
6546
6547         return ret;
6548 }
6549
6550 static int si_fan_ctrl_start_smc_fan_control(struct amdgpu_device *adev)
6551 {
6552         struct si_power_info *si_pi = si_get_pi(adev);
6553         PPSMC_Result ret;
6554
6555         ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_StartFanControl);
6556         if (ret == PPSMC_Result_OK) {
6557                 si_pi->fan_is_controlled_by_smc = true;
6558                 return 0;
6559         } else {
6560                 return -EINVAL;
6561         }
6562 }
6563
6564 static int si_fan_ctrl_stop_smc_fan_control(struct amdgpu_device *adev)
6565 {
6566         struct si_power_info *si_pi = si_get_pi(adev);
6567         PPSMC_Result ret;
6568
6569         ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_StopFanControl);
6570
6571         if (ret == PPSMC_Result_OK) {
6572                 si_pi->fan_is_controlled_by_smc = false;
6573                 return 0;
6574         } else {
6575                 return -EINVAL;
6576         }
6577 }
6578
6579 static int si_dpm_get_fan_speed_percent(void *handle,
6580                                       u32 *speed)
6581 {
6582         u32 duty, duty100;
6583         u64 tmp64;
6584         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6585
6586         if (adev->pm.no_fan)
6587                 return -ENOENT;
6588
6589         duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6590         duty = (RREG32(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT;
6591
6592         if (duty100 == 0)
6593                 return -EINVAL;
6594
6595         tmp64 = (u64)duty * 100;
6596         do_div(tmp64, duty100);
6597         *speed = (u32)tmp64;
6598
6599         if (*speed > 100)
6600                 *speed = 100;
6601
6602         return 0;
6603 }
6604
6605 static int si_dpm_set_fan_speed_percent(void *handle,
6606                                       u32 speed)
6607 {
6608         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6609         struct si_power_info *si_pi = si_get_pi(adev);
6610         u32 tmp;
6611         u32 duty, duty100;
6612         u64 tmp64;
6613
6614         if (adev->pm.no_fan)
6615                 return -ENOENT;
6616
6617         if (si_pi->fan_is_controlled_by_smc)
6618                 return -EINVAL;
6619
6620         if (speed > 100)
6621                 return -EINVAL;
6622
6623         duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6624
6625         if (duty100 == 0)
6626                 return -EINVAL;
6627
6628         tmp64 = (u64)speed * duty100;
6629         do_div(tmp64, 100);
6630         duty = (u32)tmp64;
6631
6632         tmp = RREG32(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK;
6633         tmp |= FDO_STATIC_DUTY(duty);
6634         WREG32(CG_FDO_CTRL0, tmp);
6635
6636         return 0;
6637 }
6638
6639 static void si_dpm_set_fan_control_mode(void *handle, u32 mode)
6640 {
6641         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6642
6643         if (mode) {
6644                 /* stop auto-manage */
6645                 if (adev->pm.dpm.fan.ucode_fan_control)
6646                         si_fan_ctrl_stop_smc_fan_control(adev);
6647                 si_fan_ctrl_set_static_mode(adev, mode);
6648         } else {
6649                 /* restart auto-manage */
6650                 if (adev->pm.dpm.fan.ucode_fan_control)
6651                         si_thermal_start_smc_fan_control(adev);
6652                 else
6653                         si_fan_ctrl_set_default_mode(adev);
6654         }
6655 }
6656
6657 static u32 si_dpm_get_fan_control_mode(void *handle)
6658 {
6659         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6660         struct si_power_info *si_pi = si_get_pi(adev);
6661         u32 tmp;
6662
6663         if (si_pi->fan_is_controlled_by_smc)
6664                 return 0;
6665
6666         tmp = RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK;
6667         return (tmp >> FDO_PWM_MODE_SHIFT);
6668 }
6669
6670 #if 0
6671 static int si_fan_ctrl_get_fan_speed_rpm(struct amdgpu_device *adev,
6672                                          u32 *speed)
6673 {
6674         u32 tach_period;
6675         u32 xclk = amdgpu_asic_get_xclk(adev);
6676
6677         if (adev->pm.no_fan)
6678                 return -ENOENT;
6679
6680         if (adev->pm.fan_pulses_per_revolution == 0)
6681                 return -ENOENT;
6682
6683         tach_period = (RREG32(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT;
6684         if (tach_period == 0)
6685                 return -ENOENT;
6686
6687         *speed = 60 * xclk * 10000 / tach_period;
6688
6689         return 0;
6690 }
6691
6692 static int si_fan_ctrl_set_fan_speed_rpm(struct amdgpu_device *adev,
6693                                          u32 speed)
6694 {
6695         u32 tach_period, tmp;
6696         u32 xclk = amdgpu_asic_get_xclk(adev);
6697
6698         if (adev->pm.no_fan)
6699                 return -ENOENT;
6700
6701         if (adev->pm.fan_pulses_per_revolution == 0)
6702                 return -ENOENT;
6703
6704         if ((speed < adev->pm.fan_min_rpm) ||
6705             (speed > adev->pm.fan_max_rpm))
6706                 return -EINVAL;
6707
6708         if (adev->pm.dpm.fan.ucode_fan_control)
6709                 si_fan_ctrl_stop_smc_fan_control(adev);
6710
6711         tach_period = 60 * xclk * 10000 / (8 * speed);
6712         tmp = RREG32(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK;
6713         tmp |= TARGET_PERIOD(tach_period);
6714         WREG32(CG_TACH_CTRL, tmp);
6715
6716         si_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC_RPM);
6717
6718         return 0;
6719 }
6720 #endif
6721
6722 static void si_fan_ctrl_set_default_mode(struct amdgpu_device *adev)
6723 {
6724         struct si_power_info *si_pi = si_get_pi(adev);
6725         u32 tmp;
6726
6727         if (!si_pi->fan_ctrl_is_in_default_mode) {
6728                 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6729                 tmp |= FDO_PWM_MODE(si_pi->fan_ctrl_default_mode);
6730                 WREG32(CG_FDO_CTRL2, tmp);
6731
6732                 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6733                 tmp |= TMIN(si_pi->t_min);
6734                 WREG32(CG_FDO_CTRL2, tmp);
6735                 si_pi->fan_ctrl_is_in_default_mode = true;
6736         }
6737 }
6738
6739 static void si_thermal_start_smc_fan_control(struct amdgpu_device *adev)
6740 {
6741         if (adev->pm.dpm.fan.ucode_fan_control) {
6742                 si_fan_ctrl_start_smc_fan_control(adev);
6743                 si_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC);
6744         }
6745 }
6746
6747 static void si_thermal_initialize(struct amdgpu_device *adev)
6748 {
6749         u32 tmp;
6750
6751         if (adev->pm.fan_pulses_per_revolution) {
6752                 tmp = RREG32(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK;
6753                 tmp |= EDGE_PER_REV(adev->pm.fan_pulses_per_revolution -1);
6754                 WREG32(CG_TACH_CTRL, tmp);
6755         }
6756
6757         tmp = RREG32(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK;
6758         tmp |= TACH_PWM_RESP_RATE(0x28);
6759         WREG32(CG_FDO_CTRL2, tmp);
6760 }
6761
6762 static int si_thermal_start_thermal_controller(struct amdgpu_device *adev)
6763 {
6764         int ret;
6765
6766         si_thermal_initialize(adev);
6767         ret = si_thermal_set_temperature_range(adev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6768         if (ret)
6769                 return ret;
6770         ret = si_thermal_enable_alert(adev, true);
6771         if (ret)
6772                 return ret;
6773         if (adev->pm.dpm.fan.ucode_fan_control) {
6774                 ret = si_halt_smc(adev);
6775                 if (ret)
6776                         return ret;
6777                 ret = si_thermal_setup_fan_table(adev);
6778                 if (ret)
6779                         return ret;
6780                 ret = si_resume_smc(adev);
6781                 if (ret)
6782                         return ret;
6783                 si_thermal_start_smc_fan_control(adev);
6784         }
6785
6786         return 0;
6787 }
6788
6789 static void si_thermal_stop_thermal_controller(struct amdgpu_device *adev)
6790 {
6791         if (!adev->pm.no_fan) {
6792                 si_fan_ctrl_set_default_mode(adev);
6793                 si_fan_ctrl_stop_smc_fan_control(adev);
6794         }
6795 }
6796
6797 static int si_dpm_enable(struct amdgpu_device *adev)
6798 {
6799         struct rv7xx_power_info *pi = rv770_get_pi(adev);
6800         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6801         struct si_power_info *si_pi = si_get_pi(adev);
6802         struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;
6803         int ret;
6804
6805         if (amdgpu_si_is_smc_running(adev))
6806                 return -EINVAL;
6807         if (pi->voltage_control || si_pi->voltage_control_svi2)
6808                 si_enable_voltage_control(adev, true);
6809         if (pi->mvdd_control)
6810                 si_get_mvdd_configuration(adev);
6811         if (pi->voltage_control || si_pi->voltage_control_svi2) {
6812                 ret = si_construct_voltage_tables(adev);
6813                 if (ret) {
6814                         DRM_ERROR("si_construct_voltage_tables failed\n");
6815                         return ret;
6816                 }
6817         }
6818         if (eg_pi->dynamic_ac_timing) {
6819                 ret = si_initialize_mc_reg_table(adev);
6820                 if (ret)
6821                         eg_pi->dynamic_ac_timing = false;
6822         }
6823         if (pi->dynamic_ss)
6824                 si_enable_spread_spectrum(adev, true);
6825         if (pi->thermal_protection)
6826                 si_enable_thermal_protection(adev, true);
6827         si_setup_bsp(adev);
6828         si_program_git(adev);
6829         si_program_tp(adev);
6830         si_program_tpp(adev);
6831         si_program_sstp(adev);
6832         si_enable_display_gap(adev);
6833         si_program_vc(adev);
6834         ret = si_upload_firmware(adev);
6835         if (ret) {
6836                 DRM_ERROR("si_upload_firmware failed\n");
6837                 return ret;
6838         }
6839         ret = si_process_firmware_header(adev);
6840         if (ret) {
6841                 DRM_ERROR("si_process_firmware_header failed\n");
6842                 return ret;
6843         }
6844         ret = si_initial_switch_from_arb_f0_to_f1(adev);
6845         if (ret) {
6846                 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n");
6847                 return ret;
6848         }
6849         ret = si_init_smc_table(adev);
6850         if (ret) {
6851                 DRM_ERROR("si_init_smc_table failed\n");
6852                 return ret;
6853         }
6854         ret = si_init_smc_spll_table(adev);
6855         if (ret) {
6856                 DRM_ERROR("si_init_smc_spll_table failed\n");
6857                 return ret;
6858         }
6859         ret = si_init_arb_table_index(adev);
6860         if (ret) {
6861                 DRM_ERROR("si_init_arb_table_index failed\n");
6862                 return ret;
6863         }
6864         if (eg_pi->dynamic_ac_timing) {
6865                 ret = si_populate_mc_reg_table(adev, boot_ps);
6866                 if (ret) {
6867                         DRM_ERROR("si_populate_mc_reg_table failed\n");
6868                         return ret;
6869                 }
6870         }
6871         ret = si_initialize_smc_cac_tables(adev);
6872         if (ret) {
6873                 DRM_ERROR("si_initialize_smc_cac_tables failed\n");
6874                 return ret;
6875         }
6876         ret = si_initialize_hardware_cac_manager(adev);
6877         if (ret) {
6878                 DRM_ERROR("si_initialize_hardware_cac_manager failed\n");
6879                 return ret;
6880         }
6881         ret = si_initialize_smc_dte_tables(adev);
6882         if (ret) {
6883                 DRM_ERROR("si_initialize_smc_dte_tables failed\n");
6884                 return ret;
6885         }
6886         ret = si_populate_smc_tdp_limits(adev, boot_ps);
6887         if (ret) {
6888                 DRM_ERROR("si_populate_smc_tdp_limits failed\n");
6889                 return ret;
6890         }
6891         ret = si_populate_smc_tdp_limits_2(adev, boot_ps);
6892         if (ret) {
6893                 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n");
6894                 return ret;
6895         }
6896         si_program_response_times(adev);
6897         si_program_ds_registers(adev);
6898         si_dpm_start_smc(adev);
6899         ret = si_notify_smc_display_change(adev, false);
6900         if (ret) {
6901                 DRM_ERROR("si_notify_smc_display_change failed\n");
6902                 return ret;
6903         }
6904         si_enable_sclk_control(adev, true);
6905         si_start_dpm(adev);
6906
6907         si_enable_auto_throttle_source(adev, AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
6908         si_thermal_start_thermal_controller(adev);
6909         ni_update_current_ps(adev, boot_ps);
6910
6911         return 0;
6912 }
6913
6914 static int si_set_temperature_range(struct amdgpu_device *adev)
6915 {
6916         int ret;
6917
6918         ret = si_thermal_enable_alert(adev, false);
6919         if (ret)
6920                 return ret;
6921         ret = si_thermal_set_temperature_range(adev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6922         if (ret)
6923                 return ret;
6924         ret = si_thermal_enable_alert(adev, true);
6925         if (ret)
6926                 return ret;
6927
6928         return ret;
6929 }
6930
6931 static void si_dpm_disable(struct amdgpu_device *adev)
6932 {
6933         struct rv7xx_power_info *pi = rv770_get_pi(adev);
6934         struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;
6935
6936         if (!amdgpu_si_is_smc_running(adev))
6937                 return;
6938         si_thermal_stop_thermal_controller(adev);
6939         si_disable_ulv(adev);
6940         si_clear_vc(adev);
6941         if (pi->thermal_protection)
6942                 si_enable_thermal_protection(adev, false);
6943         si_enable_power_containment(adev, boot_ps, false);
6944         si_enable_smc_cac(adev, boot_ps, false);
6945         si_enable_spread_spectrum(adev, false);
6946         si_enable_auto_throttle_source(adev, AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
6947         si_stop_dpm(adev);
6948         si_reset_to_default(adev);
6949         si_dpm_stop_smc(adev);
6950         si_force_switch_to_arb_f0(adev);
6951
6952         ni_update_current_ps(adev, boot_ps);
6953 }
6954
6955 static int si_dpm_pre_set_power_state(void *handle)
6956 {
6957         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6958         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6959         struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps;
6960         struct amdgpu_ps *new_ps = &requested_ps;
6961
6962         ni_update_requested_ps(adev, new_ps);
6963         si_apply_state_adjust_rules(adev, &eg_pi->requested_rps);
6964
6965         return 0;
6966 }
6967
6968 static int si_power_control_set_level(struct amdgpu_device *adev)
6969 {
6970         struct amdgpu_ps *new_ps = adev->pm.dpm.requested_ps;
6971         int ret;
6972
6973         ret = si_restrict_performance_levels_before_switch(adev);
6974         if (ret)
6975                 return ret;
6976         ret = si_halt_smc(adev);
6977         if (ret)
6978                 return ret;
6979         ret = si_populate_smc_tdp_limits(adev, new_ps);
6980         if (ret)
6981                 return ret;
6982         ret = si_populate_smc_tdp_limits_2(adev, new_ps);
6983         if (ret)
6984                 return ret;
6985         ret = si_resume_smc(adev);
6986         if (ret)
6987                 return ret;
6988         ret = si_set_sw_state(adev);
6989         if (ret)
6990                 return ret;
6991         return 0;
6992 }
6993
6994 static int si_dpm_set_power_state(void *handle)
6995 {
6996         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6997         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6998         struct amdgpu_ps *new_ps = &eg_pi->requested_rps;
6999         struct amdgpu_ps *old_ps = &eg_pi->current_rps;
7000         int ret;
7001
7002         ret = si_disable_ulv(adev);
7003         if (ret) {
7004                 DRM_ERROR("si_disable_ulv failed\n");
7005                 return ret;
7006         }
7007         ret = si_restrict_performance_levels_before_switch(adev);
7008         if (ret) {
7009                 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n");
7010                 return ret;
7011         }
7012         if (eg_pi->pcie_performance_request)
7013                 si_request_link_speed_change_before_state_change(adev, new_ps, old_ps);
7014         ni_set_uvd_clock_before_set_eng_clock(adev, new_ps, old_ps);
7015         ret = si_enable_power_containment(adev, new_ps, false);
7016         if (ret) {
7017                 DRM_ERROR("si_enable_power_containment failed\n");
7018                 return ret;
7019         }
7020         ret = si_enable_smc_cac(adev, new_ps, false);
7021         if (ret) {
7022                 DRM_ERROR("si_enable_smc_cac failed\n");
7023                 return ret;
7024         }
7025         ret = si_halt_smc(adev);
7026         if (ret) {
7027                 DRM_ERROR("si_halt_smc failed\n");
7028                 return ret;
7029         }
7030         ret = si_upload_sw_state(adev, new_ps);
7031         if (ret) {
7032                 DRM_ERROR("si_upload_sw_state failed\n");
7033                 return ret;
7034         }
7035         ret = si_upload_smc_data(adev);
7036         if (ret) {
7037                 DRM_ERROR("si_upload_smc_data failed\n");
7038                 return ret;
7039         }
7040         ret = si_upload_ulv_state(adev);
7041         if (ret) {
7042                 DRM_ERROR("si_upload_ulv_state failed\n");
7043                 return ret;
7044         }
7045         if (eg_pi->dynamic_ac_timing) {
7046                 ret = si_upload_mc_reg_table(adev, new_ps);
7047                 if (ret) {
7048                         DRM_ERROR("si_upload_mc_reg_table failed\n");
7049                         return ret;
7050                 }
7051         }
7052         ret = si_program_memory_timing_parameters(adev, new_ps);
7053         if (ret) {
7054                 DRM_ERROR("si_program_memory_timing_parameters failed\n");
7055                 return ret;
7056         }
7057         si_set_pcie_lane_width_in_smc(adev, new_ps, old_ps);
7058
7059         ret = si_resume_smc(adev);
7060         if (ret) {
7061                 DRM_ERROR("si_resume_smc failed\n");
7062                 return ret;
7063         }
7064         ret = si_set_sw_state(adev);
7065         if (ret) {
7066                 DRM_ERROR("si_set_sw_state failed\n");
7067                 return ret;
7068         }
7069         ni_set_uvd_clock_after_set_eng_clock(adev, new_ps, old_ps);
7070         if (eg_pi->pcie_performance_request)
7071                 si_notify_link_speed_change_after_state_change(adev, new_ps, old_ps);
7072         ret = si_set_power_state_conditionally_enable_ulv(adev, new_ps);
7073         if (ret) {
7074                 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n");
7075                 return ret;
7076         }
7077         ret = si_enable_smc_cac(adev, new_ps, true);
7078         if (ret) {
7079                 DRM_ERROR("si_enable_smc_cac failed\n");
7080                 return ret;
7081         }
7082         ret = si_enable_power_containment(adev, new_ps, true);
7083         if (ret) {
7084                 DRM_ERROR("si_enable_power_containment failed\n");
7085                 return ret;
7086         }
7087
7088         ret = si_power_control_set_level(adev);
7089         if (ret) {
7090                 DRM_ERROR("si_power_control_set_level failed\n");
7091                 return ret;
7092         }
7093
7094         return 0;
7095 }
7096
7097 static void si_dpm_post_set_power_state(void *handle)
7098 {
7099         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7100         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7101         struct amdgpu_ps *new_ps = &eg_pi->requested_rps;
7102
7103         ni_update_current_ps(adev, new_ps);
7104 }
7105
7106 #if 0
7107 void si_dpm_reset_asic(struct amdgpu_device *adev)
7108 {
7109         si_restrict_performance_levels_before_switch(adev);
7110         si_disable_ulv(adev);
7111         si_set_boot_state(adev);
7112 }
7113 #endif
7114
7115 static void si_dpm_display_configuration_changed(void *handle)
7116 {
7117         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7118
7119         si_program_display_gap(adev);
7120 }
7121
7122
7123 static void si_parse_pplib_non_clock_info(struct amdgpu_device *adev,
7124                                           struct amdgpu_ps *rps,
7125                                           struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
7126                                           u8 table_rev)
7127 {
7128         rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
7129         rps->class = le16_to_cpu(non_clock_info->usClassification);
7130         rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
7131
7132         if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
7133                 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
7134                 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
7135         } else if (r600_is_uvd_state(rps->class, rps->class2)) {
7136                 rps->vclk = RV770_DEFAULT_VCLK_FREQ;
7137                 rps->dclk = RV770_DEFAULT_DCLK_FREQ;
7138         } else {
7139                 rps->vclk = 0;
7140                 rps->dclk = 0;
7141         }
7142
7143         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
7144                 adev->pm.dpm.boot_ps = rps;
7145         if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
7146                 adev->pm.dpm.uvd_ps = rps;
7147 }
7148
7149 static void si_parse_pplib_clock_info(struct amdgpu_device *adev,
7150                                       struct amdgpu_ps *rps, int index,
7151                                       union pplib_clock_info *clock_info)
7152 {
7153         struct rv7xx_power_info *pi = rv770_get_pi(adev);
7154         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7155         struct si_power_info *si_pi = si_get_pi(adev);
7156         struct  si_ps *ps = si_get_ps(rps);
7157         u16 leakage_voltage;
7158         struct rv7xx_pl *pl = &ps->performance_levels[index];
7159         int ret;
7160
7161         ps->performance_level_count = index + 1;
7162
7163         pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
7164         pl->sclk |= clock_info->si.ucEngineClockHigh << 16;
7165         pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
7166         pl->mclk |= clock_info->si.ucMemoryClockHigh << 16;
7167
7168         pl->vddc = le16_to_cpu(clock_info->si.usVDDC);
7169         pl->vddci = le16_to_cpu(clock_info->si.usVDDCI);
7170         pl->flags = le32_to_cpu(clock_info->si.ulFlags);
7171         pl->pcie_gen = r600_get_pcie_gen_support(adev,
7172                                                  si_pi->sys_pcie_mask,
7173                                                  si_pi->boot_pcie_gen,
7174                                                  clock_info->si.ucPCIEGen);
7175
7176         /* patch up vddc if necessary */
7177         ret = si_get_leakage_voltage_from_leakage_index(adev, pl->vddc,
7178                                                         &leakage_voltage);
7179         if (ret == 0)
7180                 pl->vddc = leakage_voltage;
7181
7182         if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
7183                 pi->acpi_vddc = pl->vddc;
7184                 eg_pi->acpi_vddci = pl->vddci;
7185                 si_pi->acpi_pcie_gen = pl->pcie_gen;
7186         }
7187
7188         if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) &&
7189             index == 0) {
7190                 /* XXX disable for A0 tahiti */
7191                 si_pi->ulv.supported = false;
7192                 si_pi->ulv.pl = *pl;
7193                 si_pi->ulv.one_pcie_lane_in_ulv = false;
7194                 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT;
7195                 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT;
7196                 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT;
7197         }
7198
7199         if (pi->min_vddc_in_table > pl->vddc)
7200                 pi->min_vddc_in_table = pl->vddc;
7201
7202         if (pi->max_vddc_in_table < pl->vddc)
7203                 pi->max_vddc_in_table = pl->vddc;
7204
7205         /* patch up boot state */
7206         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
7207                 u16 vddc, vddci, mvdd;
7208                 amdgpu_atombios_get_default_voltages(adev, &vddc, &vddci, &mvdd);
7209                 pl->mclk = adev->clock.default_mclk;
7210                 pl->sclk = adev->clock.default_sclk;
7211                 pl->vddc = vddc;
7212                 pl->vddci = vddci;
7213                 si_pi->mvdd_bootup_value = mvdd;
7214         }
7215
7216         if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
7217             ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
7218                 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;
7219                 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;
7220                 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;
7221                 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;
7222         }
7223 }
7224
7225 union pplib_power_state {
7226         struct _ATOM_PPLIB_STATE v1;
7227         struct _ATOM_PPLIB_STATE_V2 v2;
7228 };
7229
7230 static int si_parse_power_table(struct amdgpu_device *adev)
7231 {
7232         struct amdgpu_mode_info *mode_info = &adev->mode_info;
7233         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
7234         union pplib_power_state *power_state;
7235         int i, j, k, non_clock_array_index, clock_array_index;
7236         union pplib_clock_info *clock_info;
7237         struct _StateArray *state_array;
7238         struct _ClockInfoArray *clock_info_array;
7239         struct _NonClockInfoArray *non_clock_info_array;
7240         union power_info *power_info;
7241         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
7242         u16 data_offset;
7243         u8 frev, crev;
7244         u8 *power_state_offset;
7245         struct  si_ps *ps;
7246
7247         if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
7248                                    &frev, &crev, &data_offset))
7249                 return -EINVAL;
7250         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
7251
7252         amdgpu_add_thermal_controller(adev);
7253
7254         state_array = (struct _StateArray *)
7255                 (mode_info->atom_context->bios + data_offset +
7256                  le16_to_cpu(power_info->pplib.usStateArrayOffset));
7257         clock_info_array = (struct _ClockInfoArray *)
7258                 (mode_info->atom_context->bios + data_offset +
7259                  le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
7260         non_clock_info_array = (struct _NonClockInfoArray *)
7261                 (mode_info->atom_context->bios + data_offset +
7262                  le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
7263
7264         adev->pm.dpm.ps = kzalloc(sizeof(struct amdgpu_ps) *
7265                                   state_array->ucNumEntries, GFP_KERNEL);
7266         if (!adev->pm.dpm.ps)
7267                 return -ENOMEM;
7268         power_state_offset = (u8 *)state_array->states;
7269         for (i = 0; i < state_array->ucNumEntries; i++) {
7270                 u8 *idx;
7271                 power_state = (union pplib_power_state *)power_state_offset;
7272                 non_clock_array_index = power_state->v2.nonClockInfoIndex;
7273                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
7274                         &non_clock_info_array->nonClockInfo[non_clock_array_index];
7275                 ps = kzalloc(sizeof(struct  si_ps), GFP_KERNEL);
7276                 if (ps == NULL) {
7277                         kfree(adev->pm.dpm.ps);
7278                         return -ENOMEM;
7279                 }
7280                 adev->pm.dpm.ps[i].ps_priv = ps;
7281                 si_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i],
7282                                               non_clock_info,
7283                                               non_clock_info_array->ucEntrySize);
7284                 k = 0;
7285                 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
7286                 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
7287                         clock_array_index = idx[j];
7288                         if (clock_array_index >= clock_info_array->ucNumEntries)
7289                                 continue;
7290                         if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS)
7291                                 break;
7292                         clock_info = (union pplib_clock_info *)
7293                                 ((u8 *)&clock_info_array->clockInfo[0] +
7294                                  (clock_array_index * clock_info_array->ucEntrySize));
7295                         si_parse_pplib_clock_info(adev,
7296                                                   &adev->pm.dpm.ps[i], k,
7297                                                   clock_info);
7298                         k++;
7299                 }
7300                 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
7301         }
7302         adev->pm.dpm.num_ps = state_array->ucNumEntries;
7303
7304         /* fill in the vce power states */
7305         for (i = 0; i < adev->pm.dpm.num_of_vce_states; i++) {
7306                 u32 sclk, mclk;
7307                 clock_array_index = adev->pm.dpm.vce_states[i].clk_idx;
7308                 clock_info = (union pplib_clock_info *)
7309                         &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
7310                 sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
7311                 sclk |= clock_info->si.ucEngineClockHigh << 16;
7312                 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
7313                 mclk |= clock_info->si.ucMemoryClockHigh << 16;
7314                 adev->pm.dpm.vce_states[i].sclk = sclk;
7315                 adev->pm.dpm.vce_states[i].mclk = mclk;
7316         }
7317
7318         return 0;
7319 }
7320
7321 static int si_dpm_init(struct amdgpu_device *adev)
7322 {
7323         struct rv7xx_power_info *pi;
7324         struct evergreen_power_info *eg_pi;
7325         struct ni_power_info *ni_pi;
7326         struct si_power_info *si_pi;
7327         struct atom_clock_dividers dividers;
7328         int ret;
7329         u32 mask;
7330
7331         si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL);
7332         if (si_pi == NULL)
7333                 return -ENOMEM;
7334         adev->pm.dpm.priv = si_pi;
7335         ni_pi = &si_pi->ni;
7336         eg_pi = &ni_pi->eg;
7337         pi = &eg_pi->rv7xx;
7338
7339         ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
7340         if (ret)
7341                 si_pi->sys_pcie_mask = 0;
7342         else
7343                 si_pi->sys_pcie_mask = mask;
7344         si_pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
7345         si_pi->boot_pcie_gen = si_get_current_pcie_speed(adev);
7346
7347         si_set_max_cu_value(adev);
7348
7349         rv770_get_max_vddc(adev);
7350         si_get_leakage_vddc(adev);
7351         si_patch_dependency_tables_based_on_leakage(adev);
7352
7353         pi->acpi_vddc = 0;
7354         eg_pi->acpi_vddci = 0;
7355         pi->min_vddc_in_table = 0;
7356         pi->max_vddc_in_table = 0;
7357
7358         ret = amdgpu_get_platform_caps(adev);
7359         if (ret)
7360                 return ret;
7361
7362         ret = amdgpu_parse_extended_power_table(adev);
7363         if (ret)
7364                 return ret;
7365
7366         ret = si_parse_power_table(adev);
7367         if (ret)
7368                 return ret;
7369
7370         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
7371                 kzalloc(4 * sizeof(struct amdgpu_clock_voltage_dependency_entry), GFP_KERNEL);
7372         if (!adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
7373                 amdgpu_free_extended_power_table(adev);
7374                 return -ENOMEM;
7375         }
7376         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
7377         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
7378         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
7379         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
7380         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
7381         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
7382         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
7383         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
7384         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
7385
7386         if (adev->pm.dpm.voltage_response_time == 0)
7387                 adev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
7388         if (adev->pm.dpm.backbias_response_time == 0)
7389                 adev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
7390
7391         ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
7392                                              0, false, &dividers);
7393         if (ret)
7394                 pi->ref_div = dividers.ref_div + 1;
7395         else
7396                 pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
7397
7398         eg_pi->smu_uvd_hs = false;
7399
7400         pi->mclk_strobe_mode_threshold = 40000;
7401         if (si_is_special_1gb_platform(adev))
7402                 pi->mclk_stutter_mode_threshold = 0;
7403         else
7404                 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold;
7405         pi->mclk_edc_enable_threshold = 40000;
7406         eg_pi->mclk_edc_wr_enable_threshold = 40000;
7407
7408         ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold;
7409
7410         pi->voltage_control =
7411                 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7412                                             VOLTAGE_OBJ_GPIO_LUT);
7413         if (!pi->voltage_control) {
7414                 si_pi->voltage_control_svi2 =
7415                         amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7416                                                     VOLTAGE_OBJ_SVID2);
7417                 if (si_pi->voltage_control_svi2)
7418                         amdgpu_atombios_get_svi2_info(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7419                                                   &si_pi->svd_gpio_id, &si_pi->svc_gpio_id);
7420         }
7421
7422         pi->mvdd_control =
7423                 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_MVDDC,
7424                                             VOLTAGE_OBJ_GPIO_LUT);
7425
7426         eg_pi->vddci_control =
7427                 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7428                                             VOLTAGE_OBJ_GPIO_LUT);
7429         if (!eg_pi->vddci_control)
7430                 si_pi->vddci_control_svi2 =
7431                         amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7432                                                     VOLTAGE_OBJ_SVID2);
7433
7434         si_pi->vddc_phase_shed_control =
7435                 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7436                                             VOLTAGE_OBJ_PHASE_LUT);
7437
7438         rv770_get_engine_memory_ss(adev);
7439
7440         pi->asi = RV770_ASI_DFLT;
7441         pi->pasi = CYPRESS_HASI_DFLT;
7442         pi->vrc = SISLANDS_VRC_DFLT;
7443
7444         pi->gfx_clock_gating = true;
7445
7446         eg_pi->sclk_deep_sleep = true;
7447         si_pi->sclk_deep_sleep_above_low = false;
7448
7449         if (adev->pm.int_thermal_type != THERMAL_TYPE_NONE)
7450                 pi->thermal_protection = true;
7451         else
7452                 pi->thermal_protection = false;
7453
7454         eg_pi->dynamic_ac_timing = true;
7455
7456         eg_pi->light_sleep = true;
7457 #if defined(CONFIG_ACPI)
7458         eg_pi->pcie_performance_request =
7459                 amdgpu_acpi_is_pcie_performance_request_supported(adev);
7460 #else
7461         eg_pi->pcie_performance_request = false;
7462 #endif
7463
7464         si_pi->sram_end = SMC_RAM_END;
7465
7466         adev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
7467         adev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
7468         adev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
7469         adev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
7470         adev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
7471         adev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
7472         adev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
7473
7474         si_initialize_powertune_defaults(adev);
7475
7476         /* make sure dc limits are valid */
7477         if ((adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
7478             (adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
7479                 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
7480                         adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
7481
7482         si_pi->fan_ctrl_is_in_default_mode = true;
7483
7484         return 0;
7485 }
7486
7487 static void si_dpm_fini(struct amdgpu_device *adev)
7488 {
7489         int i;
7490
7491         if (adev->pm.dpm.ps)
7492                 for (i = 0; i < adev->pm.dpm.num_ps; i++)
7493                         kfree(adev->pm.dpm.ps[i].ps_priv);
7494         kfree(adev->pm.dpm.ps);
7495         kfree(adev->pm.dpm.priv);
7496         kfree(adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
7497         amdgpu_free_extended_power_table(adev);
7498 }
7499
7500 static void si_dpm_debugfs_print_current_performance_level(void *handle,
7501                                                     struct seq_file *m)
7502 {
7503         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7504         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7505         struct amdgpu_ps *rps = &eg_pi->current_rps;
7506         struct  si_ps *ps = si_get_ps(rps);
7507         struct rv7xx_pl *pl;
7508         u32 current_index =
7509                 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7510                 CURRENT_STATE_INDEX_SHIFT;
7511
7512         if (current_index >= ps->performance_level_count) {
7513                 seq_printf(m, "invalid dpm profile %d\n", current_index);
7514         } else {
7515                 pl = &ps->performance_levels[current_index];
7516                 seq_printf(m, "uvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
7517                 seq_printf(m, "power level %d    sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
7518                            current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
7519         }
7520 }
7521
7522 static int si_dpm_set_interrupt_state(struct amdgpu_device *adev,
7523                                       struct amdgpu_irq_src *source,
7524                                       unsigned type,
7525                                       enum amdgpu_interrupt_state state)
7526 {
7527         u32 cg_thermal_int;
7528
7529         switch (type) {
7530         case AMDGPU_THERMAL_IRQ_LOW_TO_HIGH:
7531                 switch (state) {
7532                 case AMDGPU_IRQ_STATE_DISABLE:
7533                         cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7534                         cg_thermal_int |= THERM_INT_MASK_HIGH;
7535                         WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7536                         break;
7537                 case AMDGPU_IRQ_STATE_ENABLE:
7538                         cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7539                         cg_thermal_int &= ~THERM_INT_MASK_HIGH;
7540                         WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7541                         break;
7542                 default:
7543                         break;
7544                 }
7545                 break;
7546
7547         case AMDGPU_THERMAL_IRQ_HIGH_TO_LOW:
7548                 switch (state) {
7549                 case AMDGPU_IRQ_STATE_DISABLE:
7550                         cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7551                         cg_thermal_int |= THERM_INT_MASK_LOW;
7552                         WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7553                         break;
7554                 case AMDGPU_IRQ_STATE_ENABLE:
7555                         cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7556                         cg_thermal_int &= ~THERM_INT_MASK_LOW;
7557                         WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7558                         break;
7559                 default:
7560                         break;
7561                 }
7562                 break;
7563
7564         default:
7565                 break;
7566         }
7567         return 0;
7568 }
7569
7570 static int si_dpm_process_interrupt(struct amdgpu_device *adev,
7571                                     struct amdgpu_irq_src *source,
7572                                     struct amdgpu_iv_entry *entry)
7573 {
7574         bool queue_thermal = false;
7575
7576         if (entry == NULL)
7577                 return -EINVAL;
7578
7579         switch (entry->src_id) {
7580         case 230: /* thermal low to high */
7581                 DRM_DEBUG("IH: thermal low to high\n");
7582                 adev->pm.dpm.thermal.high_to_low = false;
7583                 queue_thermal = true;
7584                 break;
7585         case 231: /* thermal high to low */
7586                 DRM_DEBUG("IH: thermal high to low\n");
7587                 adev->pm.dpm.thermal.high_to_low = true;
7588                 queue_thermal = true;
7589                 break;
7590         default:
7591                 break;
7592         }
7593
7594         if (queue_thermal)
7595                 schedule_work(&adev->pm.dpm.thermal.work);
7596
7597         return 0;
7598 }
7599
7600 static int si_dpm_late_init(void *handle)
7601 {
7602         int ret;
7603         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7604
7605         if (!amdgpu_dpm)
7606                 return 0;
7607
7608         /* init the sysfs and debugfs files late */
7609         ret = amdgpu_pm_sysfs_init(adev);
7610         if (ret)
7611                 return ret;
7612
7613         ret = si_set_temperature_range(adev);
7614         if (ret)
7615                 return ret;
7616 #if 0 //TODO ?
7617         si_dpm_powergate_uvd(adev, true);
7618 #endif
7619         return 0;
7620 }
7621
7622 /**
7623  * si_dpm_init_microcode - load ucode images from disk
7624  *
7625  * @adev: amdgpu_device pointer
7626  *
7627  * Use the firmware interface to load the ucode images into
7628  * the driver (not loaded into hw).
7629  * Returns 0 on success, error on failure.
7630  */
7631 static int si_dpm_init_microcode(struct amdgpu_device *adev)
7632 {
7633         const char *chip_name;
7634         char fw_name[30];
7635         int err;
7636
7637         DRM_DEBUG("\n");
7638         switch (adev->asic_type) {
7639         case CHIP_TAHITI:
7640                 chip_name = "tahiti";
7641                 break;
7642         case CHIP_PITCAIRN:
7643                 if ((adev->pdev->revision == 0x81) &&
7644                     ((adev->pdev->device == 0x6810) ||
7645                     (adev->pdev->device == 0x6811)))
7646                         chip_name = "pitcairn_k";
7647                 else
7648                         chip_name = "pitcairn";
7649                 break;
7650         case CHIP_VERDE:
7651                 if (((adev->pdev->device == 0x6820) &&
7652                         ((adev->pdev->revision == 0x81) ||
7653                         (adev->pdev->revision == 0x83))) ||
7654                     ((adev->pdev->device == 0x6821) &&
7655                         ((adev->pdev->revision == 0x83) ||
7656                         (adev->pdev->revision == 0x87))) ||
7657                     ((adev->pdev->revision == 0x87) &&
7658                         ((adev->pdev->device == 0x6823) ||
7659                         (adev->pdev->device == 0x682b))))
7660                         chip_name = "verde_k";
7661                 else
7662                         chip_name = "verde";
7663                 break;
7664         case CHIP_OLAND:
7665                 if (((adev->pdev->revision == 0x81) &&
7666                         ((adev->pdev->device == 0x6600) ||
7667                         (adev->pdev->device == 0x6604) ||
7668                         (adev->pdev->device == 0x6605) ||
7669                         (adev->pdev->device == 0x6610))) ||
7670                     ((adev->pdev->revision == 0x83) &&
7671                         (adev->pdev->device == 0x6610)))
7672                         chip_name = "oland_k";
7673                 else
7674                         chip_name = "oland";
7675                 break;
7676         case CHIP_HAINAN:
7677                 if (((adev->pdev->revision == 0x81) &&
7678                         (adev->pdev->device == 0x6660)) ||
7679                     ((adev->pdev->revision == 0x83) &&
7680                         ((adev->pdev->device == 0x6660) ||
7681                         (adev->pdev->device == 0x6663) ||
7682                         (adev->pdev->device == 0x6665) ||
7683                          (adev->pdev->device == 0x6667))))
7684                         chip_name = "hainan_k";
7685                 else if ((adev->pdev->revision == 0xc3) &&
7686                          (adev->pdev->device == 0x6665))
7687                         chip_name = "banks_k_2";
7688                 else
7689                         chip_name = "hainan";
7690                 break;
7691         default: BUG();
7692         }
7693
7694         snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", chip_name);
7695         err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
7696         if (err)
7697                 goto out;
7698         err = amdgpu_ucode_validate(adev->pm.fw);
7699
7700 out:
7701         if (err) {
7702                 DRM_ERROR("si_smc: Failed to load firmware. err = %d\"%s\"\n",
7703                           err, fw_name);
7704                 release_firmware(adev->pm.fw);
7705                 adev->pm.fw = NULL;
7706         }
7707         return err;
7708
7709 }
7710
7711 static int si_dpm_sw_init(void *handle)
7712 {
7713         int ret;
7714         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7715
7716         ret = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 230, &adev->pm.dpm.thermal.irq);
7717         if (ret)
7718                 return ret;
7719
7720         ret = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 231, &adev->pm.dpm.thermal.irq);
7721         if (ret)
7722                 return ret;
7723
7724         /* default to balanced state */
7725         adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
7726         adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
7727         adev->pm.dpm.forced_level = AMD_DPM_FORCED_LEVEL_AUTO;
7728         adev->pm.default_sclk = adev->clock.default_sclk;
7729         adev->pm.default_mclk = adev->clock.default_mclk;
7730         adev->pm.current_sclk = adev->clock.default_sclk;
7731         adev->pm.current_mclk = adev->clock.default_mclk;
7732         adev->pm.int_thermal_type = THERMAL_TYPE_NONE;
7733
7734         if (amdgpu_dpm == 0)
7735                 return 0;
7736
7737         ret = si_dpm_init_microcode(adev);
7738         if (ret)
7739                 return ret;
7740
7741         INIT_WORK(&adev->pm.dpm.thermal.work, amdgpu_dpm_thermal_work_handler);
7742         mutex_lock(&adev->pm.mutex);
7743         ret = si_dpm_init(adev);
7744         if (ret)
7745                 goto dpm_failed;
7746         adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
7747         if (amdgpu_dpm == 1)
7748                 amdgpu_pm_print_power_states(adev);
7749         mutex_unlock(&adev->pm.mutex);
7750         DRM_INFO("amdgpu: dpm initialized\n");
7751
7752         return 0;
7753
7754 dpm_failed:
7755         si_dpm_fini(adev);
7756         mutex_unlock(&adev->pm.mutex);
7757         DRM_ERROR("amdgpu: dpm initialization failed\n");
7758         return ret;
7759 }
7760
7761 static int si_dpm_sw_fini(void *handle)
7762 {
7763         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7764
7765         flush_work(&adev->pm.dpm.thermal.work);
7766
7767         mutex_lock(&adev->pm.mutex);
7768         amdgpu_pm_sysfs_fini(adev);
7769         si_dpm_fini(adev);
7770         mutex_unlock(&adev->pm.mutex);
7771
7772         return 0;
7773 }
7774
7775 static int si_dpm_hw_init(void *handle)
7776 {
7777         int ret;
7778
7779         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7780
7781         if (!amdgpu_dpm)
7782                 return 0;
7783
7784         mutex_lock(&adev->pm.mutex);
7785         si_dpm_setup_asic(adev);
7786         ret = si_dpm_enable(adev);
7787         if (ret)
7788                 adev->pm.dpm_enabled = false;
7789         else
7790                 adev->pm.dpm_enabled = true;
7791         mutex_unlock(&adev->pm.mutex);
7792
7793         return ret;
7794 }
7795
7796 static int si_dpm_hw_fini(void *handle)
7797 {
7798         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7799
7800         if (adev->pm.dpm_enabled) {
7801                 mutex_lock(&adev->pm.mutex);
7802                 si_dpm_disable(adev);
7803                 mutex_unlock(&adev->pm.mutex);
7804         }
7805
7806         return 0;
7807 }
7808
7809 static int si_dpm_suspend(void *handle)
7810 {
7811         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7812
7813         if (adev->pm.dpm_enabled) {
7814                 mutex_lock(&adev->pm.mutex);
7815                 /* disable dpm */
7816                 si_dpm_disable(adev);
7817                 /* reset the power state */
7818                 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
7819                 mutex_unlock(&adev->pm.mutex);
7820         }
7821         return 0;
7822 }
7823
7824 static int si_dpm_resume(void *handle)
7825 {
7826         int ret;
7827         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7828
7829         if (adev->pm.dpm_enabled) {
7830                 /* asic init will reset to the boot state */
7831                 mutex_lock(&adev->pm.mutex);
7832                 si_dpm_setup_asic(adev);
7833                 ret = si_dpm_enable(adev);
7834                 if (ret)
7835                         adev->pm.dpm_enabled = false;
7836                 else
7837                         adev->pm.dpm_enabled = true;
7838                 mutex_unlock(&adev->pm.mutex);
7839                 if (adev->pm.dpm_enabled)
7840                         amdgpu_pm_compute_clocks(adev);
7841         }
7842         return 0;
7843 }
7844
7845 static bool si_dpm_is_idle(void *handle)
7846 {
7847         /* XXX */
7848         return true;
7849 }
7850
7851 static int si_dpm_wait_for_idle(void *handle)
7852 {
7853         /* XXX */
7854         return 0;
7855 }
7856
7857 static int si_dpm_soft_reset(void *handle)
7858 {
7859         return 0;
7860 }
7861
7862 static int si_dpm_set_clockgating_state(void *handle,
7863                                         enum amd_clockgating_state state)
7864 {
7865         return 0;
7866 }
7867
7868 static int si_dpm_set_powergating_state(void *handle,
7869                                         enum amd_powergating_state state)
7870 {
7871         return 0;
7872 }
7873
7874 /* get temperature in millidegrees */
7875 static int si_dpm_get_temp(void *handle)
7876 {
7877         u32 temp;
7878         int actual_temp = 0;
7879         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7880
7881         temp = (RREG32(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >>
7882                 CTF_TEMP_SHIFT;
7883
7884         if (temp & 0x200)
7885                 actual_temp = 255;
7886         else
7887                 actual_temp = temp & 0x1ff;
7888
7889         actual_temp = (actual_temp * 1000);
7890
7891         return actual_temp;
7892 }
7893
7894 static u32 si_dpm_get_sclk(void *handle, bool low)
7895 {
7896         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7897         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7898         struct  si_ps *requested_state = si_get_ps(&eg_pi->requested_rps);
7899
7900         if (low)
7901                 return requested_state->performance_levels[0].sclk;
7902         else
7903                 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk;
7904 }
7905
7906 static u32 si_dpm_get_mclk(void *handle, bool low)
7907 {
7908         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7909         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7910         struct  si_ps *requested_state = si_get_ps(&eg_pi->requested_rps);
7911
7912         if (low)
7913                 return requested_state->performance_levels[0].mclk;
7914         else
7915                 return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk;
7916 }
7917
7918 static void si_dpm_print_power_state(void *handle,
7919                                      void *current_ps)
7920 {
7921         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7922         struct amdgpu_ps *rps = (struct amdgpu_ps *)current_ps;
7923         struct  si_ps *ps = si_get_ps(rps);
7924         struct rv7xx_pl *pl;
7925         int i;
7926
7927         amdgpu_dpm_print_class_info(rps->class, rps->class2);
7928         amdgpu_dpm_print_cap_info(rps->caps);
7929         DRM_INFO("\tuvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
7930         for (i = 0; i < ps->performance_level_count; i++) {
7931                 pl = &ps->performance_levels[i];
7932                 if (adev->asic_type >= CHIP_TAHITI)
7933                         DRM_INFO("\t\tpower level %d    sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
7934                                  i, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
7935                 else
7936                         DRM_INFO("\t\tpower level %d    sclk: %u mclk: %u vddc: %u vddci: %u\n",
7937                                  i, pl->sclk, pl->mclk, pl->vddc, pl->vddci);
7938         }
7939         amdgpu_dpm_print_ps_status(adev, rps);
7940 }
7941
7942 static int si_dpm_early_init(void *handle)
7943 {
7944
7945         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7946
7947         si_dpm_set_dpm_funcs(adev);
7948         si_dpm_set_irq_funcs(adev);
7949         return 0;
7950 }
7951
7952 static inline bool si_are_power_levels_equal(const struct rv7xx_pl  *si_cpl1,
7953                                                 const struct rv7xx_pl *si_cpl2)
7954 {
7955         return ((si_cpl1->mclk == si_cpl2->mclk) &&
7956                   (si_cpl1->sclk == si_cpl2->sclk) &&
7957                   (si_cpl1->pcie_gen == si_cpl2->pcie_gen) &&
7958                   (si_cpl1->vddc == si_cpl2->vddc) &&
7959                   (si_cpl1->vddci == si_cpl2->vddci));
7960 }
7961
7962 static int si_check_state_equal(void *handle,
7963                                 void *current_ps,
7964                                 void *request_ps,
7965                                 bool *equal)
7966 {
7967         struct si_ps *si_cps;
7968         struct si_ps *si_rps;
7969         int i;
7970         struct amdgpu_ps *cps = (struct amdgpu_ps *)current_ps;
7971         struct amdgpu_ps *rps = (struct amdgpu_ps *)request_ps;
7972         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7973
7974         if (adev == NULL || cps == NULL || rps == NULL || equal == NULL)
7975                 return -EINVAL;
7976
7977         si_cps = si_get_ps((struct amdgpu_ps *)cps);
7978         si_rps = si_get_ps((struct amdgpu_ps *)rps);
7979
7980         if (si_cps == NULL) {
7981                 printk("si_cps is NULL\n");
7982                 *equal = false;
7983                 return 0;
7984         }
7985
7986         if (si_cps->performance_level_count != si_rps->performance_level_count) {
7987                 *equal = false;
7988                 return 0;
7989         }
7990
7991         for (i = 0; i < si_cps->performance_level_count; i++) {
7992                 if (!si_are_power_levels_equal(&(si_cps->performance_levels[i]),
7993                                         &(si_rps->performance_levels[i]))) {
7994                         *equal = false;
7995                         return 0;
7996                 }
7997         }
7998
7999         /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
8000         *equal = ((cps->vclk == rps->vclk) && (cps->dclk == rps->dclk));
8001         *equal &= ((cps->evclk == rps->evclk) && (cps->ecclk == rps->ecclk));
8002
8003         return 0;
8004 }
8005
8006 static int si_dpm_read_sensor(void *handle, int idx,
8007                               void *value, int *size)
8008 {
8009         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8010         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
8011         struct amdgpu_ps *rps = &eg_pi->current_rps;
8012         struct  si_ps *ps = si_get_ps(rps);
8013         uint32_t sclk, mclk;
8014         u32 pl_index =
8015                 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
8016                 CURRENT_STATE_INDEX_SHIFT;
8017
8018         /* size must be at least 4 bytes for all sensors */
8019         if (*size < 4)
8020                 return -EINVAL;
8021
8022         switch (idx) {
8023         case AMDGPU_PP_SENSOR_GFX_SCLK:
8024                 if (pl_index < ps->performance_level_count) {
8025                         sclk = ps->performance_levels[pl_index].sclk;
8026                         *((uint32_t *)value) = sclk;
8027                         *size = 4;
8028                         return 0;
8029                 }
8030                 return -EINVAL;
8031         case AMDGPU_PP_SENSOR_GFX_MCLK:
8032                 if (pl_index < ps->performance_level_count) {
8033                         mclk = ps->performance_levels[pl_index].mclk;
8034                         *((uint32_t *)value) = mclk;
8035                         *size = 4;
8036                         return 0;
8037                 }
8038                 return -EINVAL;
8039         case AMDGPU_PP_SENSOR_GPU_TEMP:
8040                 *((uint32_t *)value) = si_dpm_get_temp(adev);
8041                 *size = 4;
8042                 return 0;
8043         default:
8044                 return -EINVAL;
8045         }
8046 }
8047
8048 const struct amd_ip_funcs si_dpm_ip_funcs = {
8049         .name = "si_dpm",
8050         .early_init = si_dpm_early_init,
8051         .late_init = si_dpm_late_init,
8052         .sw_init = si_dpm_sw_init,
8053         .sw_fini = si_dpm_sw_fini,
8054         .hw_init = si_dpm_hw_init,
8055         .hw_fini = si_dpm_hw_fini,
8056         .suspend = si_dpm_suspend,
8057         .resume = si_dpm_resume,
8058         .is_idle = si_dpm_is_idle,
8059         .wait_for_idle = si_dpm_wait_for_idle,
8060         .soft_reset = si_dpm_soft_reset,
8061         .set_clockgating_state = si_dpm_set_clockgating_state,
8062         .set_powergating_state = si_dpm_set_powergating_state,
8063 };
8064
8065 static const struct amd_pm_funcs si_dpm_funcs = {
8066         .get_temperature = &si_dpm_get_temp,
8067         .pre_set_power_state = &si_dpm_pre_set_power_state,
8068         .set_power_state = &si_dpm_set_power_state,
8069         .post_set_power_state = &si_dpm_post_set_power_state,
8070         .display_configuration_changed = &si_dpm_display_configuration_changed,
8071         .get_sclk = &si_dpm_get_sclk,
8072         .get_mclk = &si_dpm_get_mclk,
8073         .print_power_state = &si_dpm_print_power_state,
8074         .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level,
8075         .force_performance_level = &si_dpm_force_performance_level,
8076         .vblank_too_short = &si_dpm_vblank_too_short,
8077         .set_fan_control_mode = &si_dpm_set_fan_control_mode,
8078         .get_fan_control_mode = &si_dpm_get_fan_control_mode,
8079         .set_fan_speed_percent = &si_dpm_set_fan_speed_percent,
8080         .get_fan_speed_percent = &si_dpm_get_fan_speed_percent,
8081         .check_state_equal = &si_check_state_equal,
8082         .get_vce_clock_state = amdgpu_get_vce_clock_state,
8083         .read_sensor = &si_dpm_read_sensor,
8084 };
8085
8086 static void si_dpm_set_dpm_funcs(struct amdgpu_device *adev)
8087 {
8088         if (adev->pm.funcs == NULL)
8089                 adev->pm.funcs = &si_dpm_funcs;
8090 }
8091
8092 static const struct amdgpu_irq_src_funcs si_dpm_irq_funcs = {
8093         .set = si_dpm_set_interrupt_state,
8094         .process = si_dpm_process_interrupt,
8095 };
8096
8097 static void si_dpm_set_irq_funcs(struct amdgpu_device *adev)
8098 {
8099         adev->pm.dpm.thermal.irq.num_types = AMDGPU_THERMAL_IRQ_LAST;
8100         adev->pm.dpm.thermal.irq.funcs = &si_dpm_irq_funcs;
8101 }
8102