2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/delay.h>
25 #include <linux/firmware.h>
26 #include <linux/module.h>
27 #include <linux/pci.h>
30 #include "amdgpu_ucode.h"
31 #include "amdgpu_trace.h"
33 #include "sdma0/sdma0_4_2_offset.h"
34 #include "sdma0/sdma0_4_2_sh_mask.h"
35 #include "sdma1/sdma1_4_2_offset.h"
36 #include "sdma1/sdma1_4_2_sh_mask.h"
37 #include "sdma2/sdma2_4_2_2_offset.h"
38 #include "sdma2/sdma2_4_2_2_sh_mask.h"
39 #include "sdma3/sdma3_4_2_2_offset.h"
40 #include "sdma3/sdma3_4_2_2_sh_mask.h"
41 #include "sdma4/sdma4_4_2_2_offset.h"
42 #include "sdma4/sdma4_4_2_2_sh_mask.h"
43 #include "sdma5/sdma5_4_2_2_offset.h"
44 #include "sdma5/sdma5_4_2_2_sh_mask.h"
45 #include "sdma6/sdma6_4_2_2_offset.h"
46 #include "sdma6/sdma6_4_2_2_sh_mask.h"
47 #include "sdma7/sdma7_4_2_2_offset.h"
48 #include "sdma7/sdma7_4_2_2_sh_mask.h"
49 #include "hdp/hdp_4_0_offset.h"
50 #include "sdma0/sdma0_4_1_default.h"
52 #include "soc15_common.h"
54 #include "vega10_sdma_pkt_open.h"
56 #include "ivsrcid/sdma0/irqsrcs_sdma0_4_0.h"
57 #include "ivsrcid/sdma1/irqsrcs_sdma1_4_0.h"
59 #include "amdgpu_ras.h"
61 MODULE_FIRMWARE("amdgpu/vega10_sdma.bin");
62 MODULE_FIRMWARE("amdgpu/vega10_sdma1.bin");
63 MODULE_FIRMWARE("amdgpu/vega12_sdma.bin");
64 MODULE_FIRMWARE("amdgpu/vega12_sdma1.bin");
65 MODULE_FIRMWARE("amdgpu/vega20_sdma.bin");
66 MODULE_FIRMWARE("amdgpu/vega20_sdma1.bin");
67 MODULE_FIRMWARE("amdgpu/raven_sdma.bin");
68 MODULE_FIRMWARE("amdgpu/picasso_sdma.bin");
69 MODULE_FIRMWARE("amdgpu/raven2_sdma.bin");
70 MODULE_FIRMWARE("amdgpu/arcturus_sdma.bin");
71 MODULE_FIRMWARE("amdgpu/renoir_sdma.bin");
73 #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L
74 #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L
76 #define WREG32_SDMA(instance, offset, value) \
77 WREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset)), value)
78 #define RREG32_SDMA(instance, offset) \
79 RREG32(sdma_v4_0_get_reg_offset(adev, (instance), (offset)))
81 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev);
82 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev);
83 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev);
84 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev);
85 static void sdma_v4_0_set_ras_funcs(struct amdgpu_device *adev);
87 static const struct soc15_reg_golden golden_settings_sdma_4[] = {
88 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
89 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xff000ff0, 0x3f000100),
90 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0100, 0x00000100),
91 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
92 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_IB_CNTL, 0x800f0100, 0x00000100),
93 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
94 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003ff006, 0x0003c000),
95 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0100, 0x00000100),
96 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
97 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0100, 0x00000100),
98 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
99 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
100 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000),
101 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100),
102 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_IB_CNTL, 0x800f0100, 0x00000100),
103 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
104 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_IB_CNTL, 0x800f0100, 0x00000100),
105 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
106 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_POWER_CNTL, 0x003ff000, 0x0003c000),
107 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_IB_CNTL, 0x800f0100, 0x00000100),
108 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
109 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_IB_CNTL, 0x800f0100, 0x00000100),
110 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
111 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0),
112 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_WATERMK, 0xfc000000, 0x00000000)
115 static const struct soc15_reg_golden golden_settings_sdma_vg10[] = {
116 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
117 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002),
118 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
119 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
120 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002)
123 static const struct soc15_reg_golden golden_settings_sdma_vg12[] = {
124 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104001),
125 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001),
126 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
127 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104001),
128 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001)
131 static const struct soc15_reg_golden golden_settings_sdma_4_1[] = {
132 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
133 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
134 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100),
135 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
136 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0xfc3fffff, 0x40000051),
137 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100),
138 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
139 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100),
140 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
141 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
142 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000)
145 static const struct soc15_reg_golden golden_settings_sdma0_4_2_init[] = {
146 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000),
149 static const struct soc15_reg_golden golden_settings_sdma0_4_2[] =
151 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
152 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
153 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
154 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
155 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
156 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
157 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
158 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
159 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RD_BURST_CNTL, 0x0000000f, 0x00000003),
160 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
161 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000),
162 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
163 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
164 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC2_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
165 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
166 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
167 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
168 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC4_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
169 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
170 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
171 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
172 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC6_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
173 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
174 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
175 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
176 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
179 static const struct soc15_reg_golden golden_settings_sdma1_4_2[] = {
180 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
181 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100),
182 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
183 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
184 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
185 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
186 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
187 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
188 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RD_BURST_CNTL, 0x0000000f, 0x00000003),
189 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
190 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000),
191 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
192 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
193 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC2_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
194 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
195 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC3_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
196 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
197 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC4_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
198 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
199 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC5_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
200 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
201 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC6_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
202 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
203 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_RPTR_ADDR_LO, 0xfffffffd, 0x00000001),
204 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
205 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0),
208 static const struct soc15_reg_golden golden_settings_sdma_rv1[] =
210 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002),
211 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002)
214 static const struct soc15_reg_golden golden_settings_sdma_rv2[] =
216 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00003001),
217 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00003001)
220 static const struct soc15_reg_golden golden_settings_sdma_arct[] =
222 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
223 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
224 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
225 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
226 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
227 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
228 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
229 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
230 SOC15_REG_GOLDEN_VALUE(SDMA2, 0, mmSDMA2_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
231 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
232 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
233 SOC15_REG_GOLDEN_VALUE(SDMA3, 0, mmSDMA3_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
234 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
235 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
236 SOC15_REG_GOLDEN_VALUE(SDMA4, 0, mmSDMA4_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
237 SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
238 SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
239 SOC15_REG_GOLDEN_VALUE(SDMA5, 0, mmSDMA5_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
240 SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
241 SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
242 SOC15_REG_GOLDEN_VALUE(SDMA6, 0, mmSDMA6_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
243 SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
244 SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
245 SOC15_REG_GOLDEN_VALUE(SDMA7, 0, mmSDMA7_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002)
248 static const struct soc15_reg_golden golden_settings_sdma_4_3[] = {
249 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
250 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
251 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002),
252 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002),
253 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
254 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003fff07, 0x40000051),
255 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
256 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
257 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
258 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x03fbe1fe)
261 static const struct soc15_ras_field_entry sdma_v4_0_ras_fields[] = {
262 { "SDMA_UCODE_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
263 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_UCODE_BUF_SED),
266 { "SDMA_RB_CMD_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
267 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_RB_CMD_BUF_SED),
270 { "SDMA_IB_CMD_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
271 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_IB_CMD_BUF_SED),
274 { "SDMA_UTCL1_RD_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
275 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_UTCL1_RD_FIFO_SED),
278 { "SDMA_UTCL1_RDBST_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
279 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_UTCL1_RDBST_FIFO_SED),
282 { "SDMA_DATA_LUT_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
283 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_DATA_LUT_FIFO_SED),
286 { "SDMA_MBANK_DATA_BUF0_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
287 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF0_SED),
290 { "SDMA_MBANK_DATA_BUF1_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
291 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF1_SED),
294 { "SDMA_MBANK_DATA_BUF2_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
295 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF2_SED),
298 { "SDMA_MBANK_DATA_BUF3_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
299 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF3_SED),
302 { "SDMA_MBANK_DATA_BUF4_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
303 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF4_SED),
306 { "SDMA_MBANK_DATA_BUF5_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
307 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF5_SED),
310 { "SDMA_MBANK_DATA_BUF6_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
311 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF6_SED),
314 { "SDMA_MBANK_DATA_BUF7_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
315 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF7_SED),
318 { "SDMA_MBANK_DATA_BUF8_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
319 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF8_SED),
322 { "SDMA_MBANK_DATA_BUF9_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
323 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF9_SED),
326 { "SDMA_MBANK_DATA_BUF10_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
327 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF10_SED),
330 { "SDMA_MBANK_DATA_BUF11_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
331 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF11_SED),
334 { "SDMA_MBANK_DATA_BUF12_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
335 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF12_SED),
338 { "SDMA_MBANK_DATA_BUF13_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
339 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF13_SED),
342 { "SDMA_MBANK_DATA_BUF14_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
343 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF14_SED),
346 { "SDMA_MBANK_DATA_BUF15_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
347 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MBANK_DATA_BUF15_SED),
350 { "SDMA_SPLIT_DAT_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
351 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_SPLIT_DAT_BUF_SED),
354 { "SDMA_MC_WR_ADDR_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER),
355 SOC15_REG_FIELD(SDMA0_EDC_COUNTER, SDMA_MC_WR_ADDR_FIFO_SED),
360 static u32 sdma_v4_0_get_reg_offset(struct amdgpu_device *adev,
361 u32 instance, u32 offset)
365 return (adev->reg_offset[SDMA0_HWIP][0][0] + offset);
367 return (adev->reg_offset[SDMA1_HWIP][0][0] + offset);
369 return (adev->reg_offset[SDMA2_HWIP][0][1] + offset);
371 return (adev->reg_offset[SDMA3_HWIP][0][1] + offset);
373 return (adev->reg_offset[SDMA4_HWIP][0][1] + offset);
375 return (adev->reg_offset[SDMA5_HWIP][0][1] + offset);
377 return (adev->reg_offset[SDMA6_HWIP][0][1] + offset);
379 return (adev->reg_offset[SDMA7_HWIP][0][1] + offset);
386 static unsigned sdma_v4_0_seq_to_irq_id(int seq_num)
390 return SOC15_IH_CLIENTID_SDMA0;
392 return SOC15_IH_CLIENTID_SDMA1;
394 return SOC15_IH_CLIENTID_SDMA2;
396 return SOC15_IH_CLIENTID_SDMA3;
398 return SOC15_IH_CLIENTID_SDMA4;
400 return SOC15_IH_CLIENTID_SDMA5;
402 return SOC15_IH_CLIENTID_SDMA6;
404 return SOC15_IH_CLIENTID_SDMA7;
411 static int sdma_v4_0_irq_id_to_seq(unsigned client_id)
414 case SOC15_IH_CLIENTID_SDMA0:
416 case SOC15_IH_CLIENTID_SDMA1:
418 case SOC15_IH_CLIENTID_SDMA2:
420 case SOC15_IH_CLIENTID_SDMA3:
422 case SOC15_IH_CLIENTID_SDMA4:
424 case SOC15_IH_CLIENTID_SDMA5:
426 case SOC15_IH_CLIENTID_SDMA6:
428 case SOC15_IH_CLIENTID_SDMA7:
436 static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev)
438 switch (adev->asic_type) {
440 soc15_program_register_sequence(adev,
441 golden_settings_sdma_4,
442 ARRAY_SIZE(golden_settings_sdma_4));
443 soc15_program_register_sequence(adev,
444 golden_settings_sdma_vg10,
445 ARRAY_SIZE(golden_settings_sdma_vg10));
448 soc15_program_register_sequence(adev,
449 golden_settings_sdma_4,
450 ARRAY_SIZE(golden_settings_sdma_4));
451 soc15_program_register_sequence(adev,
452 golden_settings_sdma_vg12,
453 ARRAY_SIZE(golden_settings_sdma_vg12));
456 soc15_program_register_sequence(adev,
457 golden_settings_sdma0_4_2_init,
458 ARRAY_SIZE(golden_settings_sdma0_4_2_init));
459 soc15_program_register_sequence(adev,
460 golden_settings_sdma0_4_2,
461 ARRAY_SIZE(golden_settings_sdma0_4_2));
462 soc15_program_register_sequence(adev,
463 golden_settings_sdma1_4_2,
464 ARRAY_SIZE(golden_settings_sdma1_4_2));
467 soc15_program_register_sequence(adev,
468 golden_settings_sdma_arct,
469 ARRAY_SIZE(golden_settings_sdma_arct));
472 soc15_program_register_sequence(adev,
473 golden_settings_sdma_4_1,
474 ARRAY_SIZE(golden_settings_sdma_4_1));
475 if (adev->rev_id >= 8)
476 soc15_program_register_sequence(adev,
477 golden_settings_sdma_rv2,
478 ARRAY_SIZE(golden_settings_sdma_rv2));
480 soc15_program_register_sequence(adev,
481 golden_settings_sdma_rv1,
482 ARRAY_SIZE(golden_settings_sdma_rv1));
485 soc15_program_register_sequence(adev,
486 golden_settings_sdma_4_3,
487 ARRAY_SIZE(golden_settings_sdma_4_3));
494 static int sdma_v4_0_init_inst_ctx(struct amdgpu_sdma_instance *sdma_inst)
497 const struct sdma_firmware_header_v1_0 *hdr;
499 err = amdgpu_ucode_validate(sdma_inst->fw);
503 hdr = (const struct sdma_firmware_header_v1_0 *)sdma_inst->fw->data;
504 sdma_inst->fw_version = le32_to_cpu(hdr->header.ucode_version);
505 sdma_inst->feature_version = le32_to_cpu(hdr->ucode_feature_version);
507 if (sdma_inst->feature_version >= 20)
508 sdma_inst->burst_nop = true;
513 static void sdma_v4_0_destroy_inst_ctx(struct amdgpu_device *adev)
517 for (i = 0; i < adev->sdma.num_instances; i++) {
518 if (adev->sdma.instance[i].fw != NULL)
519 release_firmware(adev->sdma.instance[i].fw);
521 /* arcturus shares the same FW memory across
522 all SDMA isntances */
523 if (adev->asic_type == CHIP_ARCTURUS)
527 memset((void*)adev->sdma.instance, 0,
528 sizeof(struct amdgpu_sdma_instance) * AMDGPU_MAX_SDMA_INSTANCES);
532 * sdma_v4_0_init_microcode - load ucode images from disk
534 * @adev: amdgpu_device pointer
536 * Use the firmware interface to load the ucode images into
537 * the driver (not loaded into hw).
538 * Returns 0 on success, error on failure.
541 // emulation only, won't work on real chip
542 // vega10 real chip need to use PSP to load firmware
543 static int sdma_v4_0_init_microcode(struct amdgpu_device *adev)
545 const char *chip_name;
548 struct amdgpu_firmware_info *info = NULL;
549 const struct common_firmware_header *header = NULL;
553 switch (adev->asic_type) {
555 chip_name = "vega10";
558 chip_name = "vega12";
561 chip_name = "vega20";
564 if (adev->rev_id >= 8)
565 chip_name = "raven2";
566 else if (adev->pdev->device == 0x15d8)
567 chip_name = "picasso";
572 chip_name = "arcturus";
575 chip_name = "renoir";
581 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
583 err = request_firmware(&adev->sdma.instance[0].fw, fw_name, adev->dev);
587 err = sdma_v4_0_init_inst_ctx(&adev->sdma.instance[0]);
591 for (i = 1; i < adev->sdma.num_instances; i++) {
592 if (adev->asic_type == CHIP_ARCTURUS) {
593 /* Acturus will leverage the same FW memory
594 for every SDMA instance */
595 memcpy((void*)&adev->sdma.instance[i],
596 (void*)&adev->sdma.instance[0],
597 sizeof(struct amdgpu_sdma_instance));
600 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma%d.bin", chip_name, i);
602 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
606 err = sdma_v4_0_init_inst_ctx(&adev->sdma.instance[i]);
612 DRM_DEBUG("psp_load == '%s'\n",
613 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false");
615 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
616 for (i = 0; i < adev->sdma.num_instances; i++) {
617 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
618 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
619 info->fw = adev->sdma.instance[i].fw;
620 header = (const struct common_firmware_header *)info->fw->data;
621 adev->firmware.fw_size +=
622 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
628 DRM_ERROR("sdma_v4_0: Failed to load firmware \"%s\"\n", fw_name);
629 sdma_v4_0_destroy_inst_ctx(adev);
635 * sdma_v4_0_ring_get_rptr - get the current read pointer
637 * @ring: amdgpu ring pointer
639 * Get the current rptr from the hardware (VEGA10+).
641 static uint64_t sdma_v4_0_ring_get_rptr(struct amdgpu_ring *ring)
645 /* XXX check if swapping is necessary on BE */
646 rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]);
648 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
649 return ((*rptr) >> 2);
653 * sdma_v4_0_ring_get_wptr - get the current write pointer
655 * @ring: amdgpu ring pointer
657 * Get the current wptr from the hardware (VEGA10+).
659 static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring)
661 struct amdgpu_device *adev = ring->adev;
664 if (ring->use_doorbell) {
665 /* XXX check if swapping is necessary on BE */
666 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
667 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
669 wptr = RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI);
671 wptr |= RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR);
672 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n",
680 * sdma_v4_0_page_ring_set_wptr - commit the write pointer
682 * @ring: amdgpu ring pointer
684 * Write the wptr back to the hardware (VEGA10+).
686 static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring)
688 struct amdgpu_device *adev = ring->adev;
690 DRM_DEBUG("Setting write pointer\n");
691 if (ring->use_doorbell) {
692 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs];
694 DRM_DEBUG("Using doorbell -- "
695 "wptr_offs == 0x%08x "
696 "lower_32_bits(ring->wptr) << 2 == 0x%08x "
697 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
699 lower_32_bits(ring->wptr << 2),
700 upper_32_bits(ring->wptr << 2));
701 /* XXX check if swapping is necessary on BE */
702 WRITE_ONCE(*wb, (ring->wptr << 2));
703 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
704 ring->doorbell_index, ring->wptr << 2);
705 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
707 DRM_DEBUG("Not using doorbell -- "
708 "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
709 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
711 lower_32_bits(ring->wptr << 2),
713 upper_32_bits(ring->wptr << 2));
714 WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR,
715 lower_32_bits(ring->wptr << 2));
716 WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI,
717 upper_32_bits(ring->wptr << 2));
722 * sdma_v4_0_page_ring_get_wptr - get the current write pointer
724 * @ring: amdgpu ring pointer
726 * Get the current wptr from the hardware (VEGA10+).
728 static uint64_t sdma_v4_0_page_ring_get_wptr(struct amdgpu_ring *ring)
730 struct amdgpu_device *adev = ring->adev;
733 if (ring->use_doorbell) {
734 /* XXX check if swapping is necessary on BE */
735 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
737 wptr = RREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR_HI);
739 wptr |= RREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR);
746 * sdma_v4_0_ring_set_wptr - commit the write pointer
748 * @ring: amdgpu ring pointer
750 * Write the wptr back to the hardware (VEGA10+).
752 static void sdma_v4_0_page_ring_set_wptr(struct amdgpu_ring *ring)
754 struct amdgpu_device *adev = ring->adev;
756 if (ring->use_doorbell) {
757 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs];
759 /* XXX check if swapping is necessary on BE */
760 WRITE_ONCE(*wb, (ring->wptr << 2));
761 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
763 uint64_t wptr = ring->wptr << 2;
765 WREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR,
766 lower_32_bits(wptr));
767 WREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR_HI,
768 upper_32_bits(wptr));
772 static void sdma_v4_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
774 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
777 for (i = 0; i < count; i++)
778 if (sdma && sdma->burst_nop && (i == 0))
779 amdgpu_ring_write(ring, ring->funcs->nop |
780 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
782 amdgpu_ring_write(ring, ring->funcs->nop);
786 * sdma_v4_0_ring_emit_ib - Schedule an IB on the DMA engine
788 * @ring: amdgpu ring pointer
789 * @ib: IB object to schedule
791 * Schedule an IB in the DMA ring (VEGA10).
793 static void sdma_v4_0_ring_emit_ib(struct amdgpu_ring *ring,
794 struct amdgpu_job *job,
795 struct amdgpu_ib *ib,
798 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
800 /* IB packet must end on a 8 DW boundary */
801 sdma_v4_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
803 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
804 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
805 /* base must be 32 byte aligned */
806 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
807 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
808 amdgpu_ring_write(ring, ib->length_dw);
809 amdgpu_ring_write(ring, 0);
810 amdgpu_ring_write(ring, 0);
814 static void sdma_v4_0_wait_reg_mem(struct amdgpu_ring *ring,
815 int mem_space, int hdp,
816 uint32_t addr0, uint32_t addr1,
817 uint32_t ref, uint32_t mask,
820 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
821 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(hdp) |
822 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(mem_space) |
823 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
826 amdgpu_ring_write(ring, addr0);
827 amdgpu_ring_write(ring, addr1);
830 amdgpu_ring_write(ring, addr0 << 2);
831 amdgpu_ring_write(ring, addr1 << 2);
833 amdgpu_ring_write(ring, ref); /* reference */
834 amdgpu_ring_write(ring, mask); /* mask */
835 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
836 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */
840 * sdma_v4_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
842 * @ring: amdgpu ring pointer
844 * Emit an hdp flush packet on the requested DMA ring.
846 static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
848 struct amdgpu_device *adev = ring->adev;
849 u32 ref_and_mask = 0;
850 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
852 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me;
854 sdma_v4_0_wait_reg_mem(ring, 0, 1,
855 adev->nbio.funcs->get_hdp_flush_done_offset(adev),
856 adev->nbio.funcs->get_hdp_flush_req_offset(adev),
857 ref_and_mask, ref_and_mask, 10);
861 * sdma_v4_0_ring_emit_fence - emit a fence on the DMA ring
863 * @ring: amdgpu ring pointer
864 * @fence: amdgpu fence object
866 * Add a DMA fence packet to the ring to write
867 * the fence seq number and DMA trap packet to generate
868 * an interrupt if needed (VEGA10).
870 static void sdma_v4_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
873 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
874 /* write the fence */
875 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
876 /* zero in first two bits */
878 amdgpu_ring_write(ring, lower_32_bits(addr));
879 amdgpu_ring_write(ring, upper_32_bits(addr));
880 amdgpu_ring_write(ring, lower_32_bits(seq));
882 /* optionally write high bits as well */
885 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
886 /* zero in first two bits */
888 amdgpu_ring_write(ring, lower_32_bits(addr));
889 amdgpu_ring_write(ring, upper_32_bits(addr));
890 amdgpu_ring_write(ring, upper_32_bits(seq));
893 /* generate an interrupt */
894 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
895 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
900 * sdma_v4_0_gfx_stop - stop the gfx async dma engines
902 * @adev: amdgpu_device pointer
904 * Stop the gfx async dma ring buffers (VEGA10).
906 static void sdma_v4_0_gfx_stop(struct amdgpu_device *adev)
908 struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES];
909 u32 rb_cntl, ib_cntl;
912 for (i = 0; i < adev->sdma.num_instances; i++) {
913 sdma[i] = &adev->sdma.instance[i].ring;
915 if ((adev->mman.buffer_funcs_ring == sdma[i]) && unset != 1) {
916 amdgpu_ttm_set_buffer_funcs_status(adev, false);
920 rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL);
921 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
922 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl);
923 ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL);
924 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
925 WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl);
927 sdma[i]->sched.ready = false;
932 * sdma_v4_0_rlc_stop - stop the compute async dma engines
934 * @adev: amdgpu_device pointer
936 * Stop the compute async dma queues (VEGA10).
938 static void sdma_v4_0_rlc_stop(struct amdgpu_device *adev)
944 * sdma_v4_0_page_stop - stop the page async dma engines
946 * @adev: amdgpu_device pointer
948 * Stop the page async dma ring buffers (VEGA10).
950 static void sdma_v4_0_page_stop(struct amdgpu_device *adev)
952 struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES];
953 u32 rb_cntl, ib_cntl;
957 for (i = 0; i < adev->sdma.num_instances; i++) {
958 sdma[i] = &adev->sdma.instance[i].page;
960 if ((adev->mman.buffer_funcs_ring == sdma[i]) &&
962 amdgpu_ttm_set_buffer_funcs_status(adev, false);
966 rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL);
967 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL,
969 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl);
970 ib_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL);
971 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL,
973 WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl);
975 sdma[i]->sched.ready = false;
980 * sdma_v4_0_ctx_switch_enable - stop the async dma engines context switch
982 * @adev: amdgpu_device pointer
983 * @enable: enable/disable the DMA MEs context switch.
985 * Halt or unhalt the async dma engines context switch (VEGA10).
987 static void sdma_v4_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
989 u32 f32_cntl, phase_quantum = 0;
992 if (amdgpu_sdma_phase_quantum) {
993 unsigned value = amdgpu_sdma_phase_quantum;
996 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
997 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
998 value = (value + 1) >> 1;
1001 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
1002 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
1003 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
1004 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
1005 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
1006 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
1008 "clamping sdma_phase_quantum to %uK clock cycles\n",
1012 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
1013 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
1016 for (i = 0; i < adev->sdma.num_instances; i++) {
1017 f32_cntl = RREG32_SDMA(i, mmSDMA0_CNTL);
1018 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
1019 AUTO_CTXSW_ENABLE, enable ? 1 : 0);
1020 if (enable && amdgpu_sdma_phase_quantum) {
1021 WREG32_SDMA(i, mmSDMA0_PHASE0_QUANTUM, phase_quantum);
1022 WREG32_SDMA(i, mmSDMA0_PHASE1_QUANTUM, phase_quantum);
1023 WREG32_SDMA(i, mmSDMA0_PHASE2_QUANTUM, phase_quantum);
1025 WREG32_SDMA(i, mmSDMA0_CNTL, f32_cntl);
1031 * sdma_v4_0_enable - stop the async dma engines
1033 * @adev: amdgpu_device pointer
1034 * @enable: enable/disable the DMA MEs.
1036 * Halt or unhalt the async dma engines (VEGA10).
1038 static void sdma_v4_0_enable(struct amdgpu_device *adev, bool enable)
1043 if (enable == false) {
1044 sdma_v4_0_gfx_stop(adev);
1045 sdma_v4_0_rlc_stop(adev);
1046 if (adev->sdma.has_page_queue)
1047 sdma_v4_0_page_stop(adev);
1050 for (i = 0; i < adev->sdma.num_instances; i++) {
1051 f32_cntl = RREG32_SDMA(i, mmSDMA0_F32_CNTL);
1052 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
1053 WREG32_SDMA(i, mmSDMA0_F32_CNTL, f32_cntl);
1058 * sdma_v4_0_rb_cntl - get parameters for rb_cntl
1060 static uint32_t sdma_v4_0_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl)
1062 /* Set ring buffer size in dwords */
1063 uint32_t rb_bufsz = order_base_2(ring->ring_size / 4);
1065 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
1067 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
1068 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
1069 RPTR_WRITEBACK_SWAP_ENABLE, 1);
1075 * sdma_v4_0_gfx_resume - setup and start the async dma engines
1077 * @adev: amdgpu_device pointer
1078 * @i: instance to resume
1080 * Set up the gfx DMA ring buffers and enable them (VEGA10).
1081 * Returns 0 for success, error for failure.
1083 static void sdma_v4_0_gfx_resume(struct amdgpu_device *adev, unsigned int i)
1085 struct amdgpu_ring *ring = &adev->sdma.instance[i].ring;
1086 u32 rb_cntl, ib_cntl, wptr_poll_cntl;
1089 u32 doorbell_offset;
1092 wb_offset = (ring->rptr_offs * 4);
1094 rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL);
1095 rb_cntl = sdma_v4_0_rb_cntl(ring, rb_cntl);
1096 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl);
1098 /* Initialize the ring buffer's read and write pointers */
1099 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR, 0);
1100 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_HI, 0);
1101 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR, 0);
1102 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_HI, 0);
1104 /* set the wb address whether it's enabled or not */
1105 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_HI,
1106 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
1107 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_ADDR_LO,
1108 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
1110 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
1111 RPTR_WRITEBACK_ENABLE, 1);
1113 WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE, ring->gpu_addr >> 8);
1114 WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE_HI, ring->gpu_addr >> 40);
1118 /* before programing wptr to a less value, need set minor_ptr_update first */
1119 WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 1);
1121 doorbell = RREG32_SDMA(i, mmSDMA0_GFX_DOORBELL);
1122 doorbell_offset = RREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET);
1124 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE,
1125 ring->use_doorbell);
1126 doorbell_offset = REG_SET_FIELD(doorbell_offset,
1127 SDMA0_GFX_DOORBELL_OFFSET,
1128 OFFSET, ring->doorbell_index);
1129 WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL, doorbell);
1130 WREG32_SDMA(i, mmSDMA0_GFX_DOORBELL_OFFSET, doorbell_offset);
1132 sdma_v4_0_ring_set_wptr(ring);
1134 /* set minor_ptr_update to 0 after wptr programed */
1135 WREG32_SDMA(i, mmSDMA0_GFX_MINOR_PTR_UPDATE, 0);
1137 /* setup the wptr shadow polling */
1138 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
1139 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO,
1140 lower_32_bits(wptr_gpu_addr));
1141 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI,
1142 upper_32_bits(wptr_gpu_addr));
1143 wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL);
1144 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
1145 SDMA0_GFX_RB_WPTR_POLL_CNTL,
1146 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0);
1147 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, wptr_poll_cntl);
1150 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
1151 WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl);
1153 ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL);
1154 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
1156 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
1158 /* enable DMA IBs */
1159 WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl);
1161 ring->sched.ready = true;
1165 * sdma_v4_0_page_resume - setup and start the async dma engines
1167 * @adev: amdgpu_device pointer
1168 * @i: instance to resume
1170 * Set up the page DMA ring buffers and enable them (VEGA10).
1171 * Returns 0 for success, error for failure.
1173 static void sdma_v4_0_page_resume(struct amdgpu_device *adev, unsigned int i)
1175 struct amdgpu_ring *ring = &adev->sdma.instance[i].page;
1176 u32 rb_cntl, ib_cntl, wptr_poll_cntl;
1179 u32 doorbell_offset;
1182 wb_offset = (ring->rptr_offs * 4);
1184 rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL);
1185 rb_cntl = sdma_v4_0_rb_cntl(ring, rb_cntl);
1186 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl);
1188 /* Initialize the ring buffer's read and write pointers */
1189 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR, 0);
1190 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_HI, 0);
1191 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR, 0);
1192 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_HI, 0);
1194 /* set the wb address whether it's enabled or not */
1195 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_ADDR_HI,
1196 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
1197 WREG32_SDMA(i, mmSDMA0_PAGE_RB_RPTR_ADDR_LO,
1198 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
1200 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL,
1201 RPTR_WRITEBACK_ENABLE, 1);
1203 WREG32_SDMA(i, mmSDMA0_PAGE_RB_BASE, ring->gpu_addr >> 8);
1204 WREG32_SDMA(i, mmSDMA0_PAGE_RB_BASE_HI, ring->gpu_addr >> 40);
1208 /* before programing wptr to a less value, need set minor_ptr_update first */
1209 WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 1);
1211 doorbell = RREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL);
1212 doorbell_offset = RREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET);
1214 doorbell = REG_SET_FIELD(doorbell, SDMA0_PAGE_DOORBELL, ENABLE,
1215 ring->use_doorbell);
1216 doorbell_offset = REG_SET_FIELD(doorbell_offset,
1217 SDMA0_PAGE_DOORBELL_OFFSET,
1218 OFFSET, ring->doorbell_index);
1219 WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL, doorbell);
1220 WREG32_SDMA(i, mmSDMA0_PAGE_DOORBELL_OFFSET, doorbell_offset);
1222 /* paging queue doorbell range is setup at sdma_v4_0_gfx_resume */
1223 sdma_v4_0_page_ring_set_wptr(ring);
1225 /* set minor_ptr_update to 0 after wptr programed */
1226 WREG32_SDMA(i, mmSDMA0_PAGE_MINOR_PTR_UPDATE, 0);
1228 /* setup the wptr shadow polling */
1229 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
1230 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO,
1231 lower_32_bits(wptr_gpu_addr));
1232 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI,
1233 upper_32_bits(wptr_gpu_addr));
1234 wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL);
1235 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
1236 SDMA0_PAGE_RB_WPTR_POLL_CNTL,
1237 F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0);
1238 WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, wptr_poll_cntl);
1241 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, RB_ENABLE, 1);
1242 WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl);
1244 ib_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL);
1245 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, IB_ENABLE, 1);
1247 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_PAGE_IB_CNTL, IB_SWAP_ENABLE, 1);
1249 /* enable DMA IBs */
1250 WREG32_SDMA(i, mmSDMA0_PAGE_IB_CNTL, ib_cntl);
1252 ring->sched.ready = true;
1256 sdma_v4_1_update_power_gating(struct amdgpu_device *adev, bool enable)
1260 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_SDMA)) {
1261 /* enable idle interrupt */
1262 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
1263 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
1266 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
1268 /* disable idle interrupt */
1269 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
1270 data &= ~SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
1272 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
1276 static void sdma_v4_1_init_power_gating(struct amdgpu_device *adev)
1280 /* Enable HW based PG. */
1281 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
1282 data |= SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK;
1284 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
1286 /* enable interrupt */
1287 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
1288 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
1290 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
1292 /* Configure hold time to filter in-valid power on/off request. Use default right now */
1293 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
1294 data &= ~SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK;
1295 data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK);
1296 /* Configure switch time for hysteresis purpose. Use default right now */
1297 data &= ~SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK;
1298 data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK);
1300 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
1303 static void sdma_v4_0_init_pg(struct amdgpu_device *adev)
1305 if (!(adev->pg_flags & AMD_PG_SUPPORT_SDMA))
1308 switch (adev->asic_type) {
1311 sdma_v4_1_init_power_gating(adev);
1312 sdma_v4_1_update_power_gating(adev, true);
1320 * sdma_v4_0_rlc_resume - setup and start the async dma engines
1322 * @adev: amdgpu_device pointer
1324 * Set up the compute DMA queues and enable them (VEGA10).
1325 * Returns 0 for success, error for failure.
1327 static int sdma_v4_0_rlc_resume(struct amdgpu_device *adev)
1329 sdma_v4_0_init_pg(adev);
1335 * sdma_v4_0_load_microcode - load the sDMA ME ucode
1337 * @adev: amdgpu_device pointer
1339 * Loads the sDMA0/1 ucode.
1340 * Returns 0 for success, -EINVAL if the ucode is not available.
1342 static int sdma_v4_0_load_microcode(struct amdgpu_device *adev)
1344 const struct sdma_firmware_header_v1_0 *hdr;
1345 const __le32 *fw_data;
1350 sdma_v4_0_enable(adev, false);
1352 for (i = 0; i < adev->sdma.num_instances; i++) {
1353 if (!adev->sdma.instance[i].fw)
1356 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
1357 amdgpu_ucode_print_sdma_hdr(&hdr->header);
1358 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
1360 fw_data = (const __le32 *)
1361 (adev->sdma.instance[i].fw->data +
1362 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1364 WREG32_SDMA(i, mmSDMA0_UCODE_ADDR, 0);
1366 for (j = 0; j < fw_size; j++)
1367 WREG32_SDMA(i, mmSDMA0_UCODE_DATA,
1368 le32_to_cpup(fw_data++));
1370 WREG32_SDMA(i, mmSDMA0_UCODE_ADDR,
1371 adev->sdma.instance[i].fw_version);
1378 * sdma_v4_0_start - setup and start the async dma engines
1380 * @adev: amdgpu_device pointer
1382 * Set up the DMA engines and enable them (VEGA10).
1383 * Returns 0 for success, error for failure.
1385 static int sdma_v4_0_start(struct amdgpu_device *adev)
1387 struct amdgpu_ring *ring;
1390 if (amdgpu_sriov_vf(adev)) {
1391 sdma_v4_0_ctx_switch_enable(adev, false);
1392 sdma_v4_0_enable(adev, false);
1395 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1396 r = sdma_v4_0_load_microcode(adev);
1401 /* unhalt the MEs */
1402 sdma_v4_0_enable(adev, true);
1403 /* enable sdma ring preemption */
1404 sdma_v4_0_ctx_switch_enable(adev, true);
1407 /* start the gfx rings and rlc compute queues */
1408 for (i = 0; i < adev->sdma.num_instances; i++) {
1411 WREG32_SDMA(i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL, 0);
1412 sdma_v4_0_gfx_resume(adev, i);
1413 if (adev->sdma.has_page_queue)
1414 sdma_v4_0_page_resume(adev, i);
1416 /* set utc l1 enable flag always to 1 */
1417 temp = RREG32_SDMA(i, mmSDMA0_CNTL);
1418 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
1419 WREG32_SDMA(i, mmSDMA0_CNTL, temp);
1421 if (!amdgpu_sriov_vf(adev)) {
1423 temp = RREG32_SDMA(i, mmSDMA0_F32_CNTL);
1424 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
1425 WREG32_SDMA(i, mmSDMA0_F32_CNTL, temp);
1429 if (amdgpu_sriov_vf(adev)) {
1430 sdma_v4_0_ctx_switch_enable(adev, true);
1431 sdma_v4_0_enable(adev, true);
1433 r = sdma_v4_0_rlc_resume(adev);
1438 for (i = 0; i < adev->sdma.num_instances; i++) {
1439 ring = &adev->sdma.instance[i].ring;
1441 r = amdgpu_ring_test_helper(ring);
1445 if (adev->sdma.has_page_queue) {
1446 struct amdgpu_ring *page = &adev->sdma.instance[i].page;
1448 r = amdgpu_ring_test_helper(page);
1452 if (adev->mman.buffer_funcs_ring == page)
1453 amdgpu_ttm_set_buffer_funcs_status(adev, true);
1456 if (adev->mman.buffer_funcs_ring == ring)
1457 amdgpu_ttm_set_buffer_funcs_status(adev, true);
1464 * sdma_v4_0_ring_test_ring - simple async dma engine test
1466 * @ring: amdgpu_ring structure holding ring information
1468 * Test the DMA engine by writing using it to write an
1469 * value to memory. (VEGA10).
1470 * Returns 0 for success, error for failure.
1472 static int sdma_v4_0_ring_test_ring(struct amdgpu_ring *ring)
1474 struct amdgpu_device *adev = ring->adev;
1481 r = amdgpu_device_wb_get(adev, &index);
1485 gpu_addr = adev->wb.gpu_addr + (index * 4);
1487 adev->wb.wb[index] = cpu_to_le32(tmp);
1489 r = amdgpu_ring_alloc(ring, 5);
1493 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1494 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
1495 amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
1496 amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
1497 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
1498 amdgpu_ring_write(ring, 0xDEADBEEF);
1499 amdgpu_ring_commit(ring);
1501 for (i = 0; i < adev->usec_timeout; i++) {
1502 tmp = le32_to_cpu(adev->wb.wb[index]);
1503 if (tmp == 0xDEADBEEF)
1508 if (i >= adev->usec_timeout)
1512 amdgpu_device_wb_free(adev, index);
1517 * sdma_v4_0_ring_test_ib - test an IB on the DMA engine
1519 * @ring: amdgpu_ring structure holding ring information
1521 * Test a simple IB in the DMA ring (VEGA10).
1522 * Returns 0 on success, error on failure.
1524 static int sdma_v4_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1526 struct amdgpu_device *adev = ring->adev;
1527 struct amdgpu_ib ib;
1528 struct dma_fence *f = NULL;
1534 r = amdgpu_device_wb_get(adev, &index);
1538 gpu_addr = adev->wb.gpu_addr + (index * 4);
1540 adev->wb.wb[index] = cpu_to_le32(tmp);
1541 memset(&ib, 0, sizeof(ib));
1542 r = amdgpu_ib_get(adev, NULL, 256, &ib);
1546 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1547 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1548 ib.ptr[1] = lower_32_bits(gpu_addr);
1549 ib.ptr[2] = upper_32_bits(gpu_addr);
1550 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
1551 ib.ptr[4] = 0xDEADBEEF;
1552 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1553 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1554 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1557 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1561 r = dma_fence_wait_timeout(f, false, timeout);
1568 tmp = le32_to_cpu(adev->wb.wb[index]);
1569 if (tmp == 0xDEADBEEF)
1575 amdgpu_ib_free(adev, &ib, NULL);
1578 amdgpu_device_wb_free(adev, index);
1584 * sdma_v4_0_vm_copy_pte - update PTEs by copying them from the GART
1586 * @ib: indirect buffer to fill with commands
1587 * @pe: addr of the page entry
1588 * @src: src addr to copy from
1589 * @count: number of page entries to update
1591 * Update PTEs by copying them from the GART using sDMA (VEGA10).
1593 static void sdma_v4_0_vm_copy_pte(struct amdgpu_ib *ib,
1594 uint64_t pe, uint64_t src,
1597 unsigned bytes = count * 8;
1599 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1600 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1601 ib->ptr[ib->length_dw++] = bytes - 1;
1602 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1603 ib->ptr[ib->length_dw++] = lower_32_bits(src);
1604 ib->ptr[ib->length_dw++] = upper_32_bits(src);
1605 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1606 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1611 * sdma_v4_0_vm_write_pte - update PTEs by writing them manually
1613 * @ib: indirect buffer to fill with commands
1614 * @pe: addr of the page entry
1615 * @addr: dst addr to write into pe
1616 * @count: number of page entries to update
1617 * @incr: increase next addr by incr bytes
1618 * @flags: access flags
1620 * Update PTEs by writing them manually using sDMA (VEGA10).
1622 static void sdma_v4_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1623 uint64_t value, unsigned count,
1626 unsigned ndw = count * 2;
1628 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1629 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1630 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1631 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1632 ib->ptr[ib->length_dw++] = ndw - 1;
1633 for (; ndw > 0; ndw -= 2) {
1634 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1635 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1641 * sdma_v4_0_vm_set_pte_pde - update the page tables using sDMA
1643 * @ib: indirect buffer to fill with commands
1644 * @pe: addr of the page entry
1645 * @addr: dst addr to write into pe
1646 * @count: number of page entries to update
1647 * @incr: increase next addr by incr bytes
1648 * @flags: access flags
1650 * Update the page tables using sDMA (VEGA10).
1652 static void sdma_v4_0_vm_set_pte_pde(struct amdgpu_ib *ib,
1654 uint64_t addr, unsigned count,
1655 uint32_t incr, uint64_t flags)
1657 /* for physically contiguous pages (vram) */
1658 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1659 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1660 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1661 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1662 ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1663 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1664 ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1665 ib->ptr[ib->length_dw++] = incr; /* increment size */
1666 ib->ptr[ib->length_dw++] = 0;
1667 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1671 * sdma_v4_0_ring_pad_ib - pad the IB to the required number of dw
1673 * @ib: indirect buffer to fill with padding
1676 static void sdma_v4_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1678 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1682 pad_count = (-ib->length_dw) & 7;
1683 for (i = 0; i < pad_count; i++)
1684 if (sdma && sdma->burst_nop && (i == 0))
1685 ib->ptr[ib->length_dw++] =
1686 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1687 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1689 ib->ptr[ib->length_dw++] =
1690 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1695 * sdma_v4_0_ring_emit_pipeline_sync - sync the pipeline
1697 * @ring: amdgpu_ring pointer
1699 * Make sure all previous operations are completed (CIK).
1701 static void sdma_v4_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1703 uint32_t seq = ring->fence_drv.sync_seq;
1704 uint64_t addr = ring->fence_drv.gpu_addr;
1707 sdma_v4_0_wait_reg_mem(ring, 1, 0,
1709 upper_32_bits(addr) & 0xffffffff,
1710 seq, 0xffffffff, 4);
1715 * sdma_v4_0_ring_emit_vm_flush - vm flush using sDMA
1717 * @ring: amdgpu_ring pointer
1718 * @vm: amdgpu_vm pointer
1720 * Update the page table base and flush the VM TLB
1721 * using sDMA (VEGA10).
1723 static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1724 unsigned vmid, uint64_t pd_addr)
1726 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1729 static void sdma_v4_0_ring_emit_wreg(struct amdgpu_ring *ring,
1730 uint32_t reg, uint32_t val)
1732 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1733 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1734 amdgpu_ring_write(ring, reg);
1735 amdgpu_ring_write(ring, val);
1738 static void sdma_v4_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1739 uint32_t val, uint32_t mask)
1741 sdma_v4_0_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10);
1744 static bool sdma_v4_0_fw_support_paging_queue(struct amdgpu_device *adev)
1746 uint fw_version = adev->sdma.instance[0].fw_version;
1748 switch (adev->asic_type) {
1750 return fw_version >= 430;
1752 /*return fw_version >= 31;*/
1755 return fw_version >= 123;
1761 static int sdma_v4_0_early_init(void *handle)
1763 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1766 if (adev->asic_type == CHIP_RAVEN || adev->asic_type == CHIP_RENOIR)
1767 adev->sdma.num_instances = 1;
1768 else if (adev->asic_type == CHIP_ARCTURUS)
1769 adev->sdma.num_instances = 8;
1771 adev->sdma.num_instances = 2;
1773 r = sdma_v4_0_init_microcode(adev);
1775 DRM_ERROR("Failed to load sdma firmware!\n");
1779 /* TODO: Page queue breaks driver reload under SRIOV */
1780 if ((adev->asic_type == CHIP_VEGA10) && amdgpu_sriov_vf((adev)))
1781 adev->sdma.has_page_queue = false;
1782 else if (sdma_v4_0_fw_support_paging_queue(adev))
1783 adev->sdma.has_page_queue = true;
1785 sdma_v4_0_set_ring_funcs(adev);
1786 sdma_v4_0_set_buffer_funcs(adev);
1787 sdma_v4_0_set_vm_pte_funcs(adev);
1788 sdma_v4_0_set_irq_funcs(adev);
1789 sdma_v4_0_set_ras_funcs(adev);
1794 static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev,
1796 struct amdgpu_iv_entry *entry);
1798 static int sdma_v4_0_late_init(void *handle)
1800 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1801 struct ras_ih_if ih_info = {
1802 .cb = sdma_v4_0_process_ras_data_cb,
1805 if (adev->sdma.funcs && adev->sdma.funcs->reset_ras_error_count)
1806 adev->sdma.funcs->reset_ras_error_count(adev);
1808 if (adev->sdma.funcs && adev->sdma.funcs->ras_late_init)
1809 return adev->sdma.funcs->ras_late_init(adev, &ih_info);
1814 static int sdma_v4_0_sw_init(void *handle)
1816 struct amdgpu_ring *ring;
1818 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1820 /* SDMA trap event */
1821 for (i = 0; i < adev->sdma.num_instances; i++) {
1822 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
1823 SDMA0_4_0__SRCID__SDMA_TRAP,
1824 &adev->sdma.trap_irq);
1829 /* SDMA SRAM ECC event */
1830 for (i = 0; i < adev->sdma.num_instances; i++) {
1831 r = amdgpu_irq_add_id(adev, sdma_v4_0_seq_to_irq_id(i),
1832 SDMA0_4_0__SRCID__SDMA_SRAM_ECC,
1833 &adev->sdma.ecc_irq);
1838 for (i = 0; i < adev->sdma.num_instances; i++) {
1839 ring = &adev->sdma.instance[i].ring;
1840 ring->ring_obj = NULL;
1841 ring->use_doorbell = true;
1843 DRM_INFO("use_doorbell being set to: [%s]\n",
1844 ring->use_doorbell?"true":"false");
1846 /* doorbell size is 2 dwords, get DWORD offset */
1847 ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1;
1849 sprintf(ring->name, "sdma%d", i);
1850 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq,
1851 AMDGPU_SDMA_IRQ_INSTANCE0 + i);
1855 if (adev->sdma.has_page_queue) {
1856 ring = &adev->sdma.instance[i].page;
1857 ring->ring_obj = NULL;
1858 ring->use_doorbell = true;
1860 /* paging queue use same doorbell index/routing as gfx queue
1861 * with 0x400 (4096 dwords) offset on second doorbell page
1863 ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1;
1864 ring->doorbell_index += 0x400;
1866 sprintf(ring->name, "page%d", i);
1867 r = amdgpu_ring_init(adev, ring, 1024,
1868 &adev->sdma.trap_irq,
1869 AMDGPU_SDMA_IRQ_INSTANCE0 + i);
1878 static int sdma_v4_0_sw_fini(void *handle)
1880 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1883 if (adev->sdma.funcs && adev->sdma.funcs->ras_fini)
1884 adev->sdma.funcs->ras_fini(adev);
1886 for (i = 0; i < adev->sdma.num_instances; i++) {
1887 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1888 if (adev->sdma.has_page_queue)
1889 amdgpu_ring_fini(&adev->sdma.instance[i].page);
1892 sdma_v4_0_destroy_inst_ctx(adev);
1897 static int sdma_v4_0_hw_init(void *handle)
1900 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1902 if ((adev->asic_type == CHIP_RAVEN && adev->powerplay.pp_funcs &&
1903 adev->powerplay.pp_funcs->set_powergating_by_smu) ||
1904 (adev->asic_type == CHIP_RENOIR && !adev->in_gpu_reset))
1905 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, false);
1907 if (!amdgpu_sriov_vf(adev))
1908 sdma_v4_0_init_golden_registers(adev);
1910 r = sdma_v4_0_start(adev);
1915 static int sdma_v4_0_hw_fini(void *handle)
1917 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1920 if (amdgpu_sriov_vf(adev))
1923 for (i = 0; i < adev->sdma.num_instances; i++) {
1924 amdgpu_irq_put(adev, &adev->sdma.ecc_irq,
1925 AMDGPU_SDMA_IRQ_INSTANCE0 + i);
1928 sdma_v4_0_ctx_switch_enable(adev, false);
1929 sdma_v4_0_enable(adev, false);
1931 if ((adev->asic_type == CHIP_RAVEN && adev->powerplay.pp_funcs
1932 && adev->powerplay.pp_funcs->set_powergating_by_smu) ||
1933 adev->asic_type == CHIP_RENOIR)
1934 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, true);
1939 static int sdma_v4_0_suspend(void *handle)
1941 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1943 return sdma_v4_0_hw_fini(adev);
1946 static int sdma_v4_0_resume(void *handle)
1948 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1950 return sdma_v4_0_hw_init(adev);
1953 static bool sdma_v4_0_is_idle(void *handle)
1955 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1958 for (i = 0; i < adev->sdma.num_instances; i++) {
1959 u32 tmp = RREG32_SDMA(i, mmSDMA0_STATUS_REG);
1961 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1968 static int sdma_v4_0_wait_for_idle(void *handle)
1971 u32 sdma[AMDGPU_MAX_SDMA_INSTANCES];
1972 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1974 for (i = 0; i < adev->usec_timeout; i++) {
1975 for (j = 0; j < adev->sdma.num_instances; j++) {
1976 sdma[j] = RREG32_SDMA(j, mmSDMA0_STATUS_REG);
1977 if (!(sdma[j] & SDMA0_STATUS_REG__IDLE_MASK))
1980 if (j == adev->sdma.num_instances)
1987 static int sdma_v4_0_soft_reset(void *handle)
1994 static int sdma_v4_0_set_trap_irq_state(struct amdgpu_device *adev,
1995 struct amdgpu_irq_src *source,
1997 enum amdgpu_interrupt_state state)
2001 sdma_cntl = RREG32_SDMA(type, mmSDMA0_CNTL);
2002 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
2003 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
2004 WREG32_SDMA(type, mmSDMA0_CNTL, sdma_cntl);
2009 static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev,
2010 struct amdgpu_irq_src *source,
2011 struct amdgpu_iv_entry *entry)
2015 DRM_DEBUG("IH: SDMA trap\n");
2016 instance = sdma_v4_0_irq_id_to_seq(entry->client_id);
2017 switch (entry->ring_id) {
2019 amdgpu_fence_process(&adev->sdma.instance[instance].ring);
2022 if (adev->asic_type == CHIP_VEGA20)
2023 amdgpu_fence_process(&adev->sdma.instance[instance].page);
2029 if (adev->asic_type != CHIP_VEGA20)
2030 amdgpu_fence_process(&adev->sdma.instance[instance].page);
2036 static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev,
2038 struct amdgpu_iv_entry *entry)
2042 /* When “Full RAS” is enabled, the per-IP interrupt sources should
2043 * be disabled and the driver should only look for the aggregated
2044 * interrupt via sync flood
2046 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
2049 instance = sdma_v4_0_irq_id_to_seq(entry->client_id);
2053 amdgpu_sdma_process_ras_data_cb(adev, err_data, entry);
2056 return AMDGPU_RAS_SUCCESS;
2059 static int sdma_v4_0_process_illegal_inst_irq(struct amdgpu_device *adev,
2060 struct amdgpu_irq_src *source,
2061 struct amdgpu_iv_entry *entry)
2065 DRM_ERROR("Illegal instruction in SDMA command stream\n");
2067 instance = sdma_v4_0_irq_id_to_seq(entry->client_id);
2071 switch (entry->ring_id) {
2073 drm_sched_fault(&adev->sdma.instance[instance].ring.sched);
2079 static int sdma_v4_0_set_ecc_irq_state(struct amdgpu_device *adev,
2080 struct amdgpu_irq_src *source,
2082 enum amdgpu_interrupt_state state)
2084 u32 sdma_edc_config;
2086 sdma_edc_config = RREG32_SDMA(type, mmSDMA0_EDC_CONFIG);
2087 sdma_edc_config = REG_SET_FIELD(sdma_edc_config, SDMA0_EDC_CONFIG, ECC_INT_ENABLE,
2088 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
2089 WREG32_SDMA(type, mmSDMA0_EDC_CONFIG, sdma_edc_config);
2094 static void sdma_v4_0_update_medium_grain_clock_gating(
2095 struct amdgpu_device *adev,
2101 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
2102 for (i = 0; i < adev->sdma.num_instances; i++) {
2103 def = data = RREG32_SDMA(i, mmSDMA0_CLK_CTRL);
2104 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
2105 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
2106 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
2107 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
2108 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
2109 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
2110 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
2111 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
2113 WREG32_SDMA(i, mmSDMA0_CLK_CTRL, data);
2116 for (i = 0; i < adev->sdma.num_instances; i++) {
2117 def = data = RREG32_SDMA(i, mmSDMA0_CLK_CTRL);
2118 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
2119 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
2120 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
2121 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
2122 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
2123 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
2124 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
2125 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
2127 WREG32_SDMA(i, mmSDMA0_CLK_CTRL, data);
2133 static void sdma_v4_0_update_medium_grain_light_sleep(
2134 struct amdgpu_device *adev,
2140 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
2141 for (i = 0; i < adev->sdma.num_instances; i++) {
2142 /* 1-not override: enable sdma mem light sleep */
2143 def = data = RREG32_SDMA(0, mmSDMA0_POWER_CNTL);
2144 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
2146 WREG32_SDMA(0, mmSDMA0_POWER_CNTL, data);
2149 for (i = 0; i < adev->sdma.num_instances; i++) {
2150 /* 0-override:disable sdma mem light sleep */
2151 def = data = RREG32_SDMA(0, mmSDMA0_POWER_CNTL);
2152 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
2154 WREG32_SDMA(0, mmSDMA0_POWER_CNTL, data);
2159 static int sdma_v4_0_set_clockgating_state(void *handle,
2160 enum amd_clockgating_state state)
2162 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2164 if (amdgpu_sriov_vf(adev))
2167 switch (adev->asic_type) {
2174 sdma_v4_0_update_medium_grain_clock_gating(adev,
2175 state == AMD_CG_STATE_GATE);
2176 sdma_v4_0_update_medium_grain_light_sleep(adev,
2177 state == AMD_CG_STATE_GATE);
2185 static int sdma_v4_0_set_powergating_state(void *handle,
2186 enum amd_powergating_state state)
2188 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2190 switch (adev->asic_type) {
2192 sdma_v4_1_update_power_gating(adev,
2193 state == AMD_PG_STATE_GATE ? true : false);
2202 static void sdma_v4_0_get_clockgating_state(void *handle, u32 *flags)
2204 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2207 if (amdgpu_sriov_vf(adev))
2210 /* AMD_CG_SUPPORT_SDMA_MGCG */
2211 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL));
2212 if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK))
2213 *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
2215 /* AMD_CG_SUPPORT_SDMA_LS */
2216 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
2217 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
2218 *flags |= AMD_CG_SUPPORT_SDMA_LS;
2221 const struct amd_ip_funcs sdma_v4_0_ip_funcs = {
2222 .name = "sdma_v4_0",
2223 .early_init = sdma_v4_0_early_init,
2224 .late_init = sdma_v4_0_late_init,
2225 .sw_init = sdma_v4_0_sw_init,
2226 .sw_fini = sdma_v4_0_sw_fini,
2227 .hw_init = sdma_v4_0_hw_init,
2228 .hw_fini = sdma_v4_0_hw_fini,
2229 .suspend = sdma_v4_0_suspend,
2230 .resume = sdma_v4_0_resume,
2231 .is_idle = sdma_v4_0_is_idle,
2232 .wait_for_idle = sdma_v4_0_wait_for_idle,
2233 .soft_reset = sdma_v4_0_soft_reset,
2234 .set_clockgating_state = sdma_v4_0_set_clockgating_state,
2235 .set_powergating_state = sdma_v4_0_set_powergating_state,
2236 .get_clockgating_state = sdma_v4_0_get_clockgating_state,
2239 static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = {
2240 .type = AMDGPU_RING_TYPE_SDMA,
2242 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
2243 .support_64bit_ptrs = true,
2244 .vmhub = AMDGPU_MMHUB_0,
2245 .get_rptr = sdma_v4_0_ring_get_rptr,
2246 .get_wptr = sdma_v4_0_ring_get_wptr,
2247 .set_wptr = sdma_v4_0_ring_set_wptr,
2249 6 + /* sdma_v4_0_ring_emit_hdp_flush */
2250 3 + /* hdp invalidate */
2251 6 + /* sdma_v4_0_ring_emit_pipeline_sync */
2252 /* sdma_v4_0_ring_emit_vm_flush */
2253 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2254 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
2255 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */
2256 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */
2257 .emit_ib = sdma_v4_0_ring_emit_ib,
2258 .emit_fence = sdma_v4_0_ring_emit_fence,
2259 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync,
2260 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush,
2261 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush,
2262 .test_ring = sdma_v4_0_ring_test_ring,
2263 .test_ib = sdma_v4_0_ring_test_ib,
2264 .insert_nop = sdma_v4_0_ring_insert_nop,
2265 .pad_ib = sdma_v4_0_ring_pad_ib,
2266 .emit_wreg = sdma_v4_0_ring_emit_wreg,
2267 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait,
2268 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2272 * On Arcturus, SDMA instance 5~7 has a different vmhub type(AMDGPU_MMHUB_1).
2273 * So create a individual constant ring_funcs for those instances.
2275 static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs_2nd_mmhub = {
2276 .type = AMDGPU_RING_TYPE_SDMA,
2278 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
2279 .support_64bit_ptrs = true,
2280 .vmhub = AMDGPU_MMHUB_1,
2281 .get_rptr = sdma_v4_0_ring_get_rptr,
2282 .get_wptr = sdma_v4_0_ring_get_wptr,
2283 .set_wptr = sdma_v4_0_ring_set_wptr,
2285 6 + /* sdma_v4_0_ring_emit_hdp_flush */
2286 3 + /* hdp invalidate */
2287 6 + /* sdma_v4_0_ring_emit_pipeline_sync */
2288 /* sdma_v4_0_ring_emit_vm_flush */
2289 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2290 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
2291 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */
2292 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */
2293 .emit_ib = sdma_v4_0_ring_emit_ib,
2294 .emit_fence = sdma_v4_0_ring_emit_fence,
2295 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync,
2296 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush,
2297 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush,
2298 .test_ring = sdma_v4_0_ring_test_ring,
2299 .test_ib = sdma_v4_0_ring_test_ib,
2300 .insert_nop = sdma_v4_0_ring_insert_nop,
2301 .pad_ib = sdma_v4_0_ring_pad_ib,
2302 .emit_wreg = sdma_v4_0_ring_emit_wreg,
2303 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait,
2304 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2307 static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs = {
2308 .type = AMDGPU_RING_TYPE_SDMA,
2310 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
2311 .support_64bit_ptrs = true,
2312 .vmhub = AMDGPU_MMHUB_0,
2313 .get_rptr = sdma_v4_0_ring_get_rptr,
2314 .get_wptr = sdma_v4_0_page_ring_get_wptr,
2315 .set_wptr = sdma_v4_0_page_ring_set_wptr,
2317 6 + /* sdma_v4_0_ring_emit_hdp_flush */
2318 3 + /* hdp invalidate */
2319 6 + /* sdma_v4_0_ring_emit_pipeline_sync */
2320 /* sdma_v4_0_ring_emit_vm_flush */
2321 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2322 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
2323 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */
2324 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */
2325 .emit_ib = sdma_v4_0_ring_emit_ib,
2326 .emit_fence = sdma_v4_0_ring_emit_fence,
2327 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync,
2328 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush,
2329 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush,
2330 .test_ring = sdma_v4_0_ring_test_ring,
2331 .test_ib = sdma_v4_0_ring_test_ib,
2332 .insert_nop = sdma_v4_0_ring_insert_nop,
2333 .pad_ib = sdma_v4_0_ring_pad_ib,
2334 .emit_wreg = sdma_v4_0_ring_emit_wreg,
2335 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait,
2336 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2339 static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs_2nd_mmhub = {
2340 .type = AMDGPU_RING_TYPE_SDMA,
2342 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
2343 .support_64bit_ptrs = true,
2344 .vmhub = AMDGPU_MMHUB_1,
2345 .get_rptr = sdma_v4_0_ring_get_rptr,
2346 .get_wptr = sdma_v4_0_page_ring_get_wptr,
2347 .set_wptr = sdma_v4_0_page_ring_set_wptr,
2349 6 + /* sdma_v4_0_ring_emit_hdp_flush */
2350 3 + /* hdp invalidate */
2351 6 + /* sdma_v4_0_ring_emit_pipeline_sync */
2352 /* sdma_v4_0_ring_emit_vm_flush */
2353 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
2354 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
2355 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */
2356 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */
2357 .emit_ib = sdma_v4_0_ring_emit_ib,
2358 .emit_fence = sdma_v4_0_ring_emit_fence,
2359 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync,
2360 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush,
2361 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush,
2362 .test_ring = sdma_v4_0_ring_test_ring,
2363 .test_ib = sdma_v4_0_ring_test_ib,
2364 .insert_nop = sdma_v4_0_ring_insert_nop,
2365 .pad_ib = sdma_v4_0_ring_pad_ib,
2366 .emit_wreg = sdma_v4_0_ring_emit_wreg,
2367 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait,
2368 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
2371 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev)
2375 for (i = 0; i < adev->sdma.num_instances; i++) {
2376 if (adev->asic_type == CHIP_ARCTURUS && i >= 5)
2377 adev->sdma.instance[i].ring.funcs =
2378 &sdma_v4_0_ring_funcs_2nd_mmhub;
2380 adev->sdma.instance[i].ring.funcs =
2381 &sdma_v4_0_ring_funcs;
2382 adev->sdma.instance[i].ring.me = i;
2383 if (adev->sdma.has_page_queue) {
2384 if (adev->asic_type == CHIP_ARCTURUS && i >= 5)
2385 adev->sdma.instance[i].page.funcs =
2386 &sdma_v4_0_page_ring_funcs_2nd_mmhub;
2388 adev->sdma.instance[i].page.funcs =
2389 &sdma_v4_0_page_ring_funcs;
2390 adev->sdma.instance[i].page.me = i;
2395 static const struct amdgpu_irq_src_funcs sdma_v4_0_trap_irq_funcs = {
2396 .set = sdma_v4_0_set_trap_irq_state,
2397 .process = sdma_v4_0_process_trap_irq,
2400 static const struct amdgpu_irq_src_funcs sdma_v4_0_illegal_inst_irq_funcs = {
2401 .process = sdma_v4_0_process_illegal_inst_irq,
2404 static const struct amdgpu_irq_src_funcs sdma_v4_0_ecc_irq_funcs = {
2405 .set = sdma_v4_0_set_ecc_irq_state,
2406 .process = amdgpu_sdma_process_ecc_irq,
2411 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev)
2413 switch (adev->sdma.num_instances) {
2415 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE1;
2416 adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE1;
2419 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
2420 adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
2424 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE2;
2425 adev->sdma.ecc_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE2;
2428 adev->sdma.trap_irq.funcs = &sdma_v4_0_trap_irq_funcs;
2429 adev->sdma.illegal_inst_irq.funcs = &sdma_v4_0_illegal_inst_irq_funcs;
2430 adev->sdma.ecc_irq.funcs = &sdma_v4_0_ecc_irq_funcs;
2434 * sdma_v4_0_emit_copy_buffer - copy buffer using the sDMA engine
2436 * @ring: amdgpu_ring structure holding ring information
2437 * @src_offset: src GPU address
2438 * @dst_offset: dst GPU address
2439 * @byte_count: number of bytes to xfer
2441 * Copy GPU buffers using the DMA engine (VEGA10/12).
2442 * Used by the amdgpu ttm implementation to move pages if
2443 * registered as the asic copy callback.
2445 static void sdma_v4_0_emit_copy_buffer(struct amdgpu_ib *ib,
2446 uint64_t src_offset,
2447 uint64_t dst_offset,
2448 uint32_t byte_count)
2450 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
2451 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
2452 ib->ptr[ib->length_dw++] = byte_count - 1;
2453 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
2454 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
2455 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
2456 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
2457 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
2461 * sdma_v4_0_emit_fill_buffer - fill buffer using the sDMA engine
2463 * @ring: amdgpu_ring structure holding ring information
2464 * @src_data: value to write to buffer
2465 * @dst_offset: dst GPU address
2466 * @byte_count: number of bytes to xfer
2468 * Fill GPU buffers using the DMA engine (VEGA10/12).
2470 static void sdma_v4_0_emit_fill_buffer(struct amdgpu_ib *ib,
2472 uint64_t dst_offset,
2473 uint32_t byte_count)
2475 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
2476 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
2477 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
2478 ib->ptr[ib->length_dw++] = src_data;
2479 ib->ptr[ib->length_dw++] = byte_count - 1;
2482 static const struct amdgpu_buffer_funcs sdma_v4_0_buffer_funcs = {
2483 .copy_max_bytes = 0x400000,
2485 .emit_copy_buffer = sdma_v4_0_emit_copy_buffer,
2487 .fill_max_bytes = 0x400000,
2489 .emit_fill_buffer = sdma_v4_0_emit_fill_buffer,
2492 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev)
2494 adev->mman.buffer_funcs = &sdma_v4_0_buffer_funcs;
2495 if (adev->sdma.has_page_queue)
2496 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].page;
2498 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
2501 static const struct amdgpu_vm_pte_funcs sdma_v4_0_vm_pte_funcs = {
2502 .copy_pte_num_dw = 7,
2503 .copy_pte = sdma_v4_0_vm_copy_pte,
2505 .write_pte = sdma_v4_0_vm_write_pte,
2506 .set_pte_pde = sdma_v4_0_vm_set_pte_pde,
2509 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev)
2511 struct drm_gpu_scheduler *sched;
2514 adev->vm_manager.vm_pte_funcs = &sdma_v4_0_vm_pte_funcs;
2515 for (i = 0; i < adev->sdma.num_instances; i++) {
2516 if (adev->sdma.has_page_queue)
2517 sched = &adev->sdma.instance[i].page.sched;
2519 sched = &adev->sdma.instance[i].ring.sched;
2520 adev->vm_manager.vm_pte_scheds[i] = sched;
2522 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
2525 static void sdma_v4_0_get_ras_error_count(uint32_t value,
2527 uint32_t *sec_count)
2532 /* double bits error (multiple bits) error detection is not supported */
2533 for (i = 0; i < ARRAY_SIZE(sdma_v4_0_ras_fields); i++) {
2534 /* the SDMA_EDC_COUNTER register in each sdma instance
2535 * shares the same sed shift_mask
2538 sdma_v4_0_ras_fields[i].sec_count_mask) >>
2539 sdma_v4_0_ras_fields[i].sec_count_shift;
2541 DRM_INFO("Detected %s in SDMA%d, SED %d\n",
2542 sdma_v4_0_ras_fields[i].name,
2544 *sec_count += sec_cnt;
2549 static int sdma_v4_0_query_ras_error_count(struct amdgpu_device *adev,
2550 uint32_t instance, void *ras_error_status)
2552 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
2553 uint32_t sec_count = 0;
2554 uint32_t reg_value = 0;
2556 reg_value = RREG32_SDMA(instance, mmSDMA0_EDC_COUNTER);
2557 /* double bit error is not supported */
2559 sdma_v4_0_get_ras_error_count(reg_value,
2560 instance, &sec_count);
2561 /* err_data->ce_count should be initialized to 0
2562 * before calling into this function */
2563 err_data->ce_count += sec_count;
2564 /* double bit error is not supported
2565 * set ue count to 0 */
2566 err_data->ue_count = 0;
2571 static void sdma_v4_0_reset_ras_error_count(struct amdgpu_device *adev)
2575 /* read back edc counter registers to clear the counters */
2576 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {
2577 for (i = 0; i < adev->sdma.num_instances; i++)
2578 RREG32_SDMA(i, mmSDMA0_EDC_COUNTER);
2582 static const struct amdgpu_sdma_ras_funcs sdma_v4_0_ras_funcs = {
2583 .ras_late_init = amdgpu_sdma_ras_late_init,
2584 .ras_fini = amdgpu_sdma_ras_fini,
2585 .query_ras_error_count = sdma_v4_0_query_ras_error_count,
2586 .reset_ras_error_count = sdma_v4_0_reset_ras_error_count,
2589 static void sdma_v4_0_set_ras_funcs(struct amdgpu_device *adev)
2591 switch (adev->asic_type) {
2594 adev->sdma.funcs = &sdma_v4_0_ras_funcs;
2601 const struct amdgpu_ip_block_version sdma_v4_0_ip_block = {
2602 .type = AMD_IP_BLOCK_TYPE_SDMA,
2606 .funcs = &sdma_v4_0_ip_funcs,