drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_ucode.h"
  28 #include "amdgpu_trace.h"
  29
  30 #include "sdma0/sdma0_4_0_offset.h"
  31 #include "sdma0/sdma0_4_0_sh_mask.h"
  32 #include "sdma1/sdma1_4_0_offset.h"
  33 #include "sdma1/sdma1_4_0_sh_mask.h"
  34 #include "mmhub/mmhub_1_0_offset.h"
  35 #include "mmhub/mmhub_1_0_sh_mask.h"
  36 #include "hdp/hdp_4_0_offset.h"
  37 #include "sdma0/sdma0_4_1_default.h"
  38
  39 #include "soc15_common.h"
  40 #include "soc15.h"
  41 #include "vega10_sdma_pkt_open.h"
  42
  43 MODULE_FIRMWARE("amdgpu/vega10_sdma.bin");
  44 MODULE_FIRMWARE("amdgpu/vega10_sdma1.bin");
  45 MODULE_FIRMWARE("amdgpu/raven_sdma.bin");
  46
  47 #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK  0x000000F8L
  48 #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L
  49
  50 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev);
  51 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev);
  52 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev);
  53 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev);
  54
  55 static const struct soc15_reg_golden golden_settings_sdma_4[] = {
  56         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
  57         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xff000ff0, 0x3f000100),
  58         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0100, 0x00000100),
  59         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  60         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_IB_CNTL, 0x800f0100, 0x00000100),
  61         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
  62         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003ff006, 0x0003c000),
  63         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0100, 0x00000100),
  64         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
  65         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0100, 0x00000100),
  66         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
  67         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0),
  68         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
  69         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100),
  70         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_IB_CNTL, 0x800f0100, 0x00000100),
  71         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
  72         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_IB_CNTL, 0x800f0100, 0x00000100),
  73         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
  74         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_POWER_CNTL, 0x003ff000, 0x0003c000),
  75         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_IB_CNTL, 0x800f0100, 0x00000100),
  76         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
  77         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_IB_CNTL, 0x800f0100, 0x00000100),
  78         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
  79         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0)
  80 };
  81
  82 static const struct soc15_reg_golden golden_settings_sdma_vg10[] = {
  83         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
  84         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002),
  85         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104002),
  86         SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002)
  87 };
  88
  89 static const struct soc15_reg_golden golden_settings_sdma_4_1[] =
  90 {
  91         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
  92         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
  93         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100),
  94         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  95         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0xfc3fffff, 0x40000051),
  96         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100),
  97         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
  98         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100),
  99         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
 100         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0)
 101 };
 102
 103 static const struct soc15_reg_golden golden_settings_sdma_rv1[] =
 104 {
 105         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002),
 106         SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002)
 107 };
 108
 109 static u32 sdma_v4_0_get_reg_offset(struct amdgpu_device *adev,
 110                 u32 instance, u32 offset)
 111 {
 112         return ( 0 == instance ? (adev->reg_offset[SDMA0_HWIP][0][0] + offset) :
 113                         (adev->reg_offset[SDMA1_HWIP][0][0] + offset));
 114 }
 115
 116 static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev)
 117 {
 118         switch (adev->asic_type) {
 119         case CHIP_VEGA10:
 120                 soc15_program_register_sequence(adev,
 121                                                  golden_settings_sdma_4,
 122                                                  ARRAY_SIZE(golden_settings_sdma_4));
 123                 soc15_program_register_sequence(adev,
 124                                                  golden_settings_sdma_vg10,
 125                                                  ARRAY_SIZE(golden_settings_sdma_vg10));
 126                 break;
 127         case CHIP_RAVEN:
 128                 soc15_program_register_sequence(adev,
 129                                                  golden_settings_sdma_4_1,
 130                                                  ARRAY_SIZE(golden_settings_sdma_4_1));
 131                 soc15_program_register_sequence(adev,
 132                                                  golden_settings_sdma_rv1,
 133                                                  ARRAY_SIZE(golden_settings_sdma_rv1));
 134                 break;
 135         default:
 136                 break;
 137         }
 138 }
 139
 140 /**
 141  * sdma_v4_0_init_microcode - load ucode images from disk
 142  *
 143  * @adev: amdgpu_device pointer
 144  *
 145  * Use the firmware interface to load the ucode images into
 146  * the driver (not loaded into hw).
 147  * Returns 0 on success, error on failure.
 148  */
 149
 150 // emulation only, won't work on real chip
 151 // vega10 real chip need to use PSP to load firmware
 152 static int sdma_v4_0_init_microcode(struct amdgpu_device *adev)
 153 {
 154         const char *chip_name;
 155         char fw_name[30];
 156         int err = 0, i;
 157         struct amdgpu_firmware_info *info = NULL;
 158         const struct common_firmware_header *header = NULL;
 159         const struct sdma_firmware_header_v1_0 *hdr;
 160
 161         DRM_DEBUG("\n");
 162
 163         switch (adev->asic_type) {
 164         case CHIP_VEGA10:
 165                 chip_name = "vega10";
 166                 break;
 167         case CHIP_RAVEN:
 168                 chip_name = "raven";
 169                 break;
 170         default:
 171                 BUG();
 172         }
 173
 174         for (i = 0; i < adev->sdma.num_instances; i++) {
 175                 if (i == 0)
 176                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
 177                 else
 178                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
 179                 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
 180                 if (err)
 181                         goto out;
 182                 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
 183                 if (err)
 184                         goto out;
 185                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 186                 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
 187                 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
 188                 if (adev->sdma.instance[i].feature_version >= 20)
 189                         adev->sdma.instance[i].burst_nop = true;
 190                 DRM_DEBUG("psp_load == '%s'\n",
 191                                 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false");
 192
 193                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 194                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
 195                         info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
 196                         info->fw = adev->sdma.instance[i].fw;
 197                         header = (const struct common_firmware_header *)info->fw->data;
 198                         adev->firmware.fw_size +=
 199                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 200                 }
 201         }
 202 out:
 203         if (err) {
 204                 DRM_ERROR("sdma_v4_0: Failed to load firmware \"%s\"\n", fw_name);
 205                 for (i = 0; i < adev->sdma.num_instances; i++) {
 206                         release_firmware(adev->sdma.instance[i].fw);
 207                         adev->sdma.instance[i].fw = NULL;
 208                 }
 209         }
 210         return err;
 211 }
 212
 213 /**
 214  * sdma_v4_0_ring_get_rptr - get the current read pointer
 215  *
 216  * @ring: amdgpu ring pointer
 217  *
 218  * Get the current rptr from the hardware (VEGA10+).
 219  */
 220 static uint64_t sdma_v4_0_ring_get_rptr(struct amdgpu_ring *ring)
 221 {
 222         u64 *rptr;
 223
 224         /* XXX check if swapping is necessary on BE */
 225         rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]);
 226
 227         DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
 228         return ((*rptr) >> 2);
 229 }
 230
 231 /**
 232  * sdma_v4_0_ring_get_wptr - get the current write pointer
 233  *
 234  * @ring: amdgpu ring pointer
 235  *
 236  * Get the current wptr from the hardware (VEGA10+).
 237  */
 238 static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring)
 239 {
 240         struct amdgpu_device *adev = ring->adev;
 241         u64 *wptr = NULL;
 242         uint64_t local_wptr = 0;
 243
 244         if (ring->use_doorbell) {
 245                 /* XXX check if swapping is necessary on BE */
 246                 wptr = ((u64 *)&adev->wb.wb[ring->wptr_offs]);
 247                 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", *wptr);
 248                 *wptr = (*wptr) >> 2;
 249                 DRM_DEBUG("wptr/doorbell after shift == 0x%016llx\n", *wptr);
 250         } else {
 251                 u32 lowbit, highbit;
 252                 int me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;
 253
 254                 wptr = &local_wptr;
 255                 lowbit = RREG32(sdma_v4_0_get_reg_offset(adev, me, mmSDMA0_GFX_RB_WPTR)) >> 2;
 256                 highbit = RREG32(sdma_v4_0_get_reg_offset(adev, me, mmSDMA0_GFX_RB_WPTR_HI)) >> 2;
 257
 258                 DRM_DEBUG("wptr [%i]high== 0x%08x low==0x%08x\n",
 259                                 me, highbit, lowbit);
 260                 *wptr = highbit;
 261                 *wptr = (*wptr) << 32;
 262                 *wptr |= lowbit;
 263         }
 264
 265         return *wptr;
 266 }
 267
 268 /**
 269  * sdma_v4_0_ring_set_wptr - commit the write pointer
 270  *
 271  * @ring: amdgpu ring pointer
 272  *
 273  * Write the wptr back to the hardware (VEGA10+).
 274  */
 275 static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring)
 276 {
 277         struct amdgpu_device *adev = ring->adev;
 278
 279         DRM_DEBUG("Setting write pointer\n");
 280         if (ring->use_doorbell) {
 281                 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs];
 282
 283                 DRM_DEBUG("Using doorbell -- "
 284                                 "wptr_offs == 0x%08x "
 285                                 "lower_32_bits(ring->wptr) << 2 == 0x%08x "
 286                                 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
 287                                 ring->wptr_offs,
 288                                 lower_32_bits(ring->wptr << 2),
 289                                 upper_32_bits(ring->wptr << 2));
 290                 /* XXX check if swapping is necessary on BE */
 291                 WRITE_ONCE(*wb, (ring->wptr << 2));
 292                 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
 293                                 ring->doorbell_index, ring->wptr << 2);
 294                 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
 295         } else {
 296                 int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
 297
 298                 DRM_DEBUG("Not using doorbell -- "
 299                                 "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
 300                                 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
 301                                 me,
 302                                 lower_32_bits(ring->wptr << 2),
 303                                 me,
 304                                 upper_32_bits(ring->wptr << 2));
 305                 WREG32(sdma_v4_0_get_reg_offset(adev, me, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2));
 306                 WREG32(sdma_v4_0_get_reg_offset(adev, me, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));
 307         }
 308 }
 309
 310 static void sdma_v4_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 311 {
 312         struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
 313         int i;
 314
 315         for (i = 0; i < count; i++)
 316                 if (sdma && sdma->burst_nop && (i == 0))
 317                         amdgpu_ring_write(ring, ring->funcs->nop |
 318                                 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
 319                 else
 320                         amdgpu_ring_write(ring, ring->funcs->nop);
 321 }
 322
 323 /**
 324  * sdma_v4_0_ring_emit_ib - Schedule an IB on the DMA engine
 325  *
 326  * @ring: amdgpu ring pointer
 327  * @ib: IB object to schedule
 328  *
 329  * Schedule an IB in the DMA ring (VEGA10).
 330  */
 331 static void sdma_v4_0_ring_emit_ib(struct amdgpu_ring *ring,
 332                                         struct amdgpu_ib *ib,
 333                                         unsigned vmid, bool ctx_switch)
 334 {
 335         /* IB packet must end on a 8 DW boundary */
 336         sdma_v4_0_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8);
 337
 338         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
 339                           SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
 340         /* base must be 32 byte aligned */
 341         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
 342         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 343         amdgpu_ring_write(ring, ib->length_dw);
 344         amdgpu_ring_write(ring, 0);
 345         amdgpu_ring_write(ring, 0);
 346
 347 }
 348
 349 /**
 350  * sdma_v4_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 351  *
 352  * @ring: amdgpu ring pointer
 353  *
 354  * Emit an hdp flush packet on the requested DMA ring.
 355  */
 356 static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 357 {
 358         struct amdgpu_device *adev = ring->adev;
 359         u32 ref_and_mask = 0;
 360         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio_funcs->hdp_flush_reg;
 361
 362         if (ring == &ring->adev->sdma.instance[0].ring)
 363                 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0;
 364         else
 365                 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1;
 366
 367         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 368                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
 369                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
 370         amdgpu_ring_write(ring, (adev->nbio_funcs->get_hdp_flush_done_offset(adev)) << 2);
 371         amdgpu_ring_write(ring, (adev->nbio_funcs->get_hdp_flush_req_offset(adev)) << 2);
 372         amdgpu_ring_write(ring, ref_and_mask); /* reference */
 373         amdgpu_ring_write(ring, ref_and_mask); /* mask */
 374         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 375                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 376 }
 377
 378 static void sdma_v4_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
 379 {
 380         struct amdgpu_device *adev = ring->adev;
 381
 382         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
 383                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
 384         amdgpu_ring_write(ring, SOC15_REG_OFFSET(HDP, 0, mmHDP_READ_CACHE_INVALIDATE));
 385         amdgpu_ring_write(ring, 1);
 386 }
 387
 388 /**
 389  * sdma_v4_0_ring_emit_fence - emit a fence on the DMA ring
 390  *
 391  * @ring: amdgpu ring pointer
 392  * @fence: amdgpu fence object
 393  *
 394  * Add a DMA fence packet to the ring to write
 395  * the fence seq number and DMA trap packet to generate
 396  * an interrupt if needed (VEGA10).
 397  */
 398 static void sdma_v4_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 399                                       unsigned flags)
 400 {
 401         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 402         /* write the fence */
 403         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 404         /* zero in first two bits */
 405         BUG_ON(addr & 0x3);
 406         amdgpu_ring_write(ring, lower_32_bits(addr));
 407         amdgpu_ring_write(ring, upper_32_bits(addr));
 408         amdgpu_ring_write(ring, lower_32_bits(seq));
 409
 410         /* optionally write high bits as well */
 411         if (write64bit) {
 412                 addr += 4;
 413                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 414                 /* zero in first two bits */
 415                 BUG_ON(addr & 0x3);
 416                 amdgpu_ring_write(ring, lower_32_bits(addr));
 417                 amdgpu_ring_write(ring, upper_32_bits(addr));
 418                 amdgpu_ring_write(ring, upper_32_bits(seq));
 419         }
 420
 421         /* generate an interrupt */
 422         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
 423         amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
 424 }
 425
 426
 427 /**
 428  * sdma_v4_0_gfx_stop - stop the gfx async dma engines
 429  *
 430  * @adev: amdgpu_device pointer
 431  *
 432  * Stop the gfx async dma ring buffers (VEGA10).
 433  */
 434 static void sdma_v4_0_gfx_stop(struct amdgpu_device *adev)
 435 {
 436         struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
 437         struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
 438         u32 rb_cntl, ib_cntl;
 439         int i;
 440
 441         if ((adev->mman.buffer_funcs_ring == sdma0) ||
 442             (adev->mman.buffer_funcs_ring == sdma1))
 443                 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
 444
 445         for (i = 0; i < adev->sdma.num_instances; i++) {
 446                 rb_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
 447                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
 448                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 449                 ib_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
 450                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
 451                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
 452         }
 453
 454         sdma0->ready = false;
 455         sdma1->ready = false;
 456 }
 457
 458 /**
 459  * sdma_v4_0_rlc_stop - stop the compute async dma engines
 460  *
 461  * @adev: amdgpu_device pointer
 462  *
 463  * Stop the compute async dma queues (VEGA10).
 464  */
 465 static void sdma_v4_0_rlc_stop(struct amdgpu_device *adev)
 466 {
 467         /* XXX todo */
 468 }
 469
 470 /**
 471  * sdma_v_0_ctx_switch_enable - stop the async dma engines context switch
 472  *
 473  * @adev: amdgpu_device pointer
 474  * @enable: enable/disable the DMA MEs context switch.
 475  *
 476  * Halt or unhalt the async dma engines context switch (VEGA10).
 477  */
 478 static void sdma_v4_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
 479 {
 480         u32 f32_cntl, phase_quantum = 0;
 481         int i;
 482
 483         if (amdgpu_sdma_phase_quantum) {
 484                 unsigned value = amdgpu_sdma_phase_quantum;
 485                 unsigned unit = 0;
 486
 487                 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 488                                 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
 489                         value = (value + 1) >> 1;
 490                         unit++;
 491                 }
 492                 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 493                             SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
 494                         value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 495                                  SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
 496                         unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 497                                 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
 498                         WARN_ONCE(1,
 499                         "clamping sdma_phase_quantum to %uK clock cycles\n",
 500                                   value << unit);
 501                 }
 502                 phase_quantum =
 503                         value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
 504                         unit  << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
 505         }
 506
 507         for (i = 0; i < adev->sdma.num_instances; i++) {
 508                 f32_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
 509                 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 510                                 AUTO_CTXSW_ENABLE, enable ? 1 : 0);
 511                 if (enable && amdgpu_sdma_phase_quantum) {
 512                         WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),
 513                                phase_quantum);
 514                         WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),
 515                                phase_quantum);
 516                         WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),
 517                                phase_quantum);
 518                 }
 519                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);
 520         }
 521
 522 }
 523
 524 /**
 525  * sdma_v4_0_enable - stop the async dma engines
 526  *
 527  * @adev: amdgpu_device pointer
 528  * @enable: enable/disable the DMA MEs.
 529  *
 530  * Halt or unhalt the async dma engines (VEGA10).
 531  */
 532 static void sdma_v4_0_enable(struct amdgpu_device *adev, bool enable)
 533 {
 534         u32 f32_cntl;
 535         int i;
 536
 537         if (enable == false) {
 538                 sdma_v4_0_gfx_stop(adev);
 539                 sdma_v4_0_rlc_stop(adev);
 540         }
 541
 542         for (i = 0; i < adev->sdma.num_instances; i++) {
 543                 f32_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
 544                 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
 545                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);
 546         }
 547 }
 548
 549 /**
 550  * sdma_v4_0_gfx_resume - setup and start the async dma engines
 551  *
 552  * @adev: amdgpu_device pointer
 553  *
 554  * Set up the gfx DMA ring buffers and enable them (VEGA10).
 555  * Returns 0 for success, error for failure.
 556  */
 557 static int sdma_v4_0_gfx_resume(struct amdgpu_device *adev)
 558 {
 559         struct amdgpu_ring *ring;
 560         u32 rb_cntl, ib_cntl, wptr_poll_cntl;
 561         u32 rb_bufsz;
 562         u32 wb_offset;
 563         u32 doorbell;
 564         u32 doorbell_offset;
 565         u32 temp;
 566         u64 wptr_gpu_addr;
 567         int i, r;
 568
 569         for (i = 0; i < adev->sdma.num_instances; i++) {
 570                 ring = &adev->sdma.instance[i].ring;
 571                 wb_offset = (ring->rptr_offs * 4);
 572
 573                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
 574
 575                 /* Set ring buffer size in dwords */
 576                 rb_bufsz = order_base_2(ring->ring_size / 4);
 577                 rb_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
 578                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
 579 #ifdef __BIG_ENDIAN
 580                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
 581                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
 582                                         RPTR_WRITEBACK_SWAP_ENABLE, 1);
 583 #endif
 584                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 585
 586                 /* Initialize the ring buffer's read and write pointers */
 587                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
 588                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
 589                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
 590                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
 591
 592                 /* set the wb address whether it's enabled or not */
 593                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
 594                        upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 595                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
 596                        lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
 597
 598                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
 599
 600                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8);
 601                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40);
 602
 603                 ring->wptr = 0;
 604
 605                 /* before programing wptr to a less value, need set minor_ptr_update first */
 606                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
 607
 608                 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
 609                         WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2);
 610                         WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);
 611                 }
 612
 613                 doorbell = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));
 614                 doorbell_offset = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET));
 615
 616                 if (ring->use_doorbell) {
 617                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
 618                         doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET,
 619                                         OFFSET, ring->doorbell_index);
 620                 } else {
 621                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
 622                 }
 623                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);
 624                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset);
 625                 adev->nbio_funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
 626                                                       ring->doorbell_index);
 627
 628                 if (amdgpu_sriov_vf(adev))
 629                         sdma_v4_0_ring_set_wptr(ring);
 630
 631                 /* set minor_ptr_update to 0 after wptr programed */
 632                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
 633
 634                 /* set utc l1 enable flag always to 1 */
 635                 temp = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
 636                 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
 637                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
 638
 639                 if (!amdgpu_sriov_vf(adev)) {
 640                         /* unhalt engine */
 641                         temp = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
 642                         temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
 643                         WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp);
 644                 }
 645
 646                 /* setup the wptr shadow polling */
 647                 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
 648                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
 649                        lower_32_bits(wptr_gpu_addr));
 650                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
 651                        upper_32_bits(wptr_gpu_addr));
 652                 wptr_poll_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
 653                 if (amdgpu_sriov_vf(adev))
 654                         wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 1);
 655                 else
 656                         wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 0);
 657                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), wptr_poll_cntl);
 658
 659                 /* enable DMA RB */
 660                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
 661                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 662
 663                 ib_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
 664                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
 665 #ifdef __BIG_ENDIAN
 666                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
 667 #endif
 668                 /* enable DMA IBs */
 669                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
 670
 671                 ring->ready = true;
 672
 673                 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */
 674                         sdma_v4_0_ctx_switch_enable(adev, true);
 675                         sdma_v4_0_enable(adev, true);
 676                 }
 677
 678                 r = amdgpu_ring_test_ring(ring);
 679                 if (r) {
 680                         ring->ready = false;
 681                         return r;
 682                 }
 683
 684                 if (adev->mman.buffer_funcs_ring == ring)
 685                         amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size);
 686
 687         }
 688
 689         return 0;
 690 }
 691
 692 static void
 693 sdma_v4_1_update_power_gating(struct amdgpu_device *adev, bool enable)
 694 {
 695         uint32_t def, data;
 696
 697         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_SDMA)) {
 698                 /* disable idle interrupt */
 699                 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
 700                 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
 701
 702                 if (data != def)
 703                         WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
 704         } else {
 705                 /* disable idle interrupt */
 706                 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
 707                 data &= ~SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
 708                 if (data != def)
 709                         WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
 710         }
 711 }
 712
 713 static void sdma_v4_1_init_power_gating(struct amdgpu_device *adev)
 714 {
 715         uint32_t def, data;
 716
 717         /* Enable HW based PG. */
 718         def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
 719         data |= SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK;
 720         if (data != def)
 721                 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
 722
 723         /* enable interrupt */
 724         def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
 725         data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
 726         if (data != def)
 727                 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
 728
 729         /* Configure hold time to filter in-valid power on/off request. Use default right now */
 730         def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
 731         data &= ~SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK;
 732         data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK);
 733         /* Configure switch time for hysteresis purpose. Use default right now */
 734         data &= ~SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK;
 735         data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK);
 736         if(data != def)
 737                 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
 738 }
 739
 740 static void sdma_v4_0_init_pg(struct amdgpu_device *adev)
 741 {
 742         if (!(adev->pg_flags & AMD_PG_SUPPORT_SDMA))
 743                 return;
 744
 745         switch (adev->asic_type) {
 746         case CHIP_RAVEN:
 747                 sdma_v4_1_init_power_gating(adev);
 748                 sdma_v4_1_update_power_gating(adev, true);
 749                 break;
 750         default:
 751                 break;
 752         }
 753 }
 754
 755 /**
 756  * sdma_v4_0_rlc_resume - setup and start the async dma engines
 757  *
 758  * @adev: amdgpu_device pointer
 759  *
 760  * Set up the compute DMA queues and enable them (VEGA10).
 761  * Returns 0 for success, error for failure.
 762  */
 763 static int sdma_v4_0_rlc_resume(struct amdgpu_device *adev)
 764 {
 765         sdma_v4_0_init_pg(adev);
 766
 767         return 0;
 768 }
 769
 770 /**
 771  * sdma_v4_0_load_microcode - load the sDMA ME ucode
 772  *
 773  * @adev: amdgpu_device pointer
 774  *
 775  * Loads the sDMA0/1 ucode.
 776  * Returns 0 for success, -EINVAL if the ucode is not available.
 777  */
 778 static int sdma_v4_0_load_microcode(struct amdgpu_device *adev)
 779 {
 780         const struct sdma_firmware_header_v1_0 *hdr;
 781         const __le32 *fw_data;
 782         u32 fw_size;
 783         int i, j;
 784
 785         /* halt the MEs */
 786         sdma_v4_0_enable(adev, false);
 787
 788         for (i = 0; i < adev->sdma.num_instances; i++) {
 789                 if (!adev->sdma.instance[i].fw)
 790                         return -EINVAL;
 791
 792                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 793                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
 794                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 795
 796                 fw_data = (const __le32 *)
 797                         (adev->sdma.instance[i].fw->data +
 798                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 799
 800                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0);
 801
 802                 for (j = 0; j < fw_size; j++)
 803                         WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
 804
 805                 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);
 806         }
 807
 808         return 0;
 809 }
 810
 811 /**
 812  * sdma_v4_0_start - setup and start the async dma engines
 813  *
 814  * @adev: amdgpu_device pointer
 815  *
 816  * Set up the DMA engines and enable them (VEGA10).
 817  * Returns 0 for success, error for failure.
 818  */
 819 static int sdma_v4_0_start(struct amdgpu_device *adev)
 820 {
 821         int r = 0;
 822
 823         if (amdgpu_sriov_vf(adev)) {
 824                 sdma_v4_0_ctx_switch_enable(adev, false);
 825                 sdma_v4_0_enable(adev, false);
 826
 827                 /* set RB registers */
 828                 r = sdma_v4_0_gfx_resume(adev);
 829                 return r;
 830         }
 831
 832         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
 833                 r = sdma_v4_0_load_microcode(adev);
 834                 if (r)
 835                         return r;
 836         }
 837
 838         /* unhalt the MEs */
 839         sdma_v4_0_enable(adev, true);
 840         /* enable sdma ring preemption */
 841         sdma_v4_0_ctx_switch_enable(adev, true);
 842
 843         /* start the gfx rings and rlc compute queues */
 844         r = sdma_v4_0_gfx_resume(adev);
 845         if (r)
 846                 return r;
 847         r = sdma_v4_0_rlc_resume(adev);
 848
 849         return r;
 850 }
 851
 852 /**
 853  * sdma_v4_0_ring_test_ring - simple async dma engine test
 854  *
 855  * @ring: amdgpu_ring structure holding ring information
 856  *
 857  * Test the DMA engine by writing using it to write an
 858  * value to memory. (VEGA10).
 859  * Returns 0 for success, error for failure.
 860  */
 861 static int sdma_v4_0_ring_test_ring(struct amdgpu_ring *ring)
 862 {
 863         struct amdgpu_device *adev = ring->adev;
 864         unsigned i;
 865         unsigned index;
 866         int r;
 867         u32 tmp;
 868         u64 gpu_addr;
 869
 870         r = amdgpu_device_wb_get(adev, &index);
 871         if (r) {
 872                 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 873                 return r;
 874         }
 875
 876         gpu_addr = adev->wb.gpu_addr + (index * 4);
 877         tmp = 0xCAFEDEAD;
 878         adev->wb.wb[index] = cpu_to_le32(tmp);
 879
 880         r = amdgpu_ring_alloc(ring, 5);
 881         if (r) {
 882                 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
 883                 amdgpu_device_wb_free(adev, index);
 884                 return r;
 885         }
 886
 887         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 888                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
 889         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 890         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 891         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
 892         amdgpu_ring_write(ring, 0xDEADBEEF);
 893         amdgpu_ring_commit(ring);
 894
 895         for (i = 0; i < adev->usec_timeout; i++) {
 896                 tmp = le32_to_cpu(adev->wb.wb[index]);
 897                 if (tmp == 0xDEADBEEF)
 898                         break;
 899                 DRM_UDELAY(1);
 900         }
 901
 902         if (i < adev->usec_timeout) {
 903                 DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i);
 904         } else {
 905                 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
 906                           ring->idx, tmp);
 907                 r = -EINVAL;
 908         }
 909         amdgpu_device_wb_free(adev, index);
 910
 911         return r;
 912 }
 913
 914 /**
 915  * sdma_v4_0_ring_test_ib - test an IB on the DMA engine
 916  *
 917  * @ring: amdgpu_ring structure holding ring information
 918  *
 919  * Test a simple IB in the DMA ring (VEGA10).
 920  * Returns 0 on success, error on failure.
 921  */
 922 static int sdma_v4_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 923 {
 924         struct amdgpu_device *adev = ring->adev;
 925         struct amdgpu_ib ib;
 926         struct dma_fence *f = NULL;
 927         unsigned index;
 928         long r;
 929         u32 tmp = 0;
 930         u64 gpu_addr;
 931
 932         r = amdgpu_device_wb_get(adev, &index);
 933         if (r) {
 934                 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
 935                 return r;
 936         }
 937
 938         gpu_addr = adev->wb.gpu_addr + (index * 4);
 939         tmp = 0xCAFEDEAD;
 940         adev->wb.wb[index] = cpu_to_le32(tmp);
 941         memset(&ib, 0, sizeof(ib));
 942         r = amdgpu_ib_get(adev, NULL, 256, &ib);
 943         if (r) {
 944                 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
 945                 goto err0;
 946         }
 947
 948         ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 949                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
 950         ib.ptr[1] = lower_32_bits(gpu_addr);
 951         ib.ptr[2] = upper_32_bits(gpu_addr);
 952         ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
 953         ib.ptr[4] = 0xDEADBEEF;
 954         ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 955         ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 956         ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 957         ib.length_dw = 8;
 958
 959         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
 960         if (r)
 961                 goto err1;
 962
 963         r = dma_fence_wait_timeout(f, false, timeout);
 964         if (r == 0) {
 965                 DRM_ERROR("amdgpu: IB test timed out\n");
 966                 r = -ETIMEDOUT;
 967                 goto err1;
 968         } else if (r < 0) {
 969                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
 970                 goto err1;
 971         }
 972         tmp = le32_to_cpu(adev->wb.wb[index]);
 973         if (tmp == 0xDEADBEEF) {
 974                 DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
 975                 r = 0;
 976         } else {
 977                 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
 978                 r = -EINVAL;
 979         }
 980 err1:
 981         amdgpu_ib_free(adev, &ib, NULL);
 982         dma_fence_put(f);
 983 err0:
 984         amdgpu_device_wb_free(adev, index);
 985         return r;
 986 }
 987
 988
 989 /**
 990  * sdma_v4_0_vm_copy_pte - update PTEs by copying them from the GART
 991  *
 992  * @ib: indirect buffer to fill with commands
 993  * @pe: addr of the page entry
 994  * @src: src addr to copy from
 995  * @count: number of page entries to update
 996  *
 997  * Update PTEs by copying them from the GART using sDMA (VEGA10).
 998  */
 999 static void sdma_v4_0_vm_copy_pte(struct amdgpu_ib *ib,
1000                                   uint64_t pe, uint64_t src,
1001                                   unsigned count)
1002 {
1003         unsigned bytes = count * 8;
1004
1005         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1006                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1007         ib->ptr[ib->length_dw++] = bytes - 1;
1008         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1009         ib->ptr[ib->length_dw++] = lower_32_bits(src);
1010         ib->ptr[ib->length_dw++] = upper_32_bits(src);
1011         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1012         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1013
1014 }
1015
1016 /**
1017  * sdma_v4_0_vm_write_pte - update PTEs by writing them manually
1018  *
1019  * @ib: indirect buffer to fill with commands
1020  * @pe: addr of the page entry
1021  * @addr: dst addr to write into pe
1022  * @count: number of page entries to update
1023  * @incr: increase next addr by incr bytes
1024  * @flags: access flags
1025  *
1026  * Update PTEs by writing them manually using sDMA (VEGA10).
1027  */
1028 static void sdma_v4_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1029                                    uint64_t value, unsigned count,
1030                                    uint32_t incr)
1031 {
1032         unsigned ndw = count * 2;
1033
1034         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1035                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1036         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1037         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1038         ib->ptr[ib->length_dw++] = ndw - 1;
1039         for (; ndw > 0; ndw -= 2) {
1040                 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1041                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1042                 value += incr;
1043         }
1044 }
1045
1046 /**
1047  * sdma_v4_0_vm_set_pte_pde - update the page tables using sDMA
1048  *
1049  * @ib: indirect buffer to fill with commands
1050  * @pe: addr of the page entry
1051  * @addr: dst addr to write into pe
1052  * @count: number of page entries to update
1053  * @incr: increase next addr by incr bytes
1054  * @flags: access flags
1055  *
1056  * Update the page tables using sDMA (VEGA10).
1057  */
1058 static void sdma_v4_0_vm_set_pte_pde(struct amdgpu_ib *ib,
1059                                      uint64_t pe,
1060                                      uint64_t addr, unsigned count,
1061                                      uint32_t incr, uint64_t flags)
1062 {
1063         /* for physically contiguous pages (vram) */
1064         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1065         ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1066         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1067         ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1068         ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1069         ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1070         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1071         ib->ptr[ib->length_dw++] = incr; /* increment size */
1072         ib->ptr[ib->length_dw++] = 0;
1073         ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1074 }
1075
1076 /**
1077  * sdma_v4_0_ring_pad_ib - pad the IB to the required number of dw
1078  *
1079  * @ib: indirect buffer to fill with padding
1080  *
1081  */
1082 static void sdma_v4_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1083 {
1084         struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
1085         u32 pad_count;
1086         int i;
1087
1088         pad_count = (8 - (ib->length_dw & 0x7)) % 8;
1089         for (i = 0; i < pad_count; i++)
1090                 if (sdma && sdma->burst_nop && (i == 0))
1091                         ib->ptr[ib->length_dw++] =
1092                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1093                                 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1094                 else
1095                         ib->ptr[ib->length_dw++] =
1096                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1097 }
1098
1099
1100 /**
1101  * sdma_v4_0_ring_emit_pipeline_sync - sync the pipeline
1102  *
1103  * @ring: amdgpu_ring pointer
1104  *
1105  * Make sure all previous operations are completed (CIK).
1106  */
1107 static void sdma_v4_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1108 {
1109         uint32_t seq = ring->fence_drv.sync_seq;
1110         uint64_t addr = ring->fence_drv.gpu_addr;
1111
1112         /* wait for idle */
1113         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1114                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1115                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1116                           SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1117         amdgpu_ring_write(ring, addr & 0xfffffffc);
1118         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1119         amdgpu_ring_write(ring, seq); /* reference */
1120         amdgpu_ring_write(ring, 0xfffffff); /* mask */
1121         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1122                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1123 }
1124
1125
1126 /**
1127  * sdma_v4_0_ring_emit_vm_flush - vm flush using sDMA
1128  *
1129  * @ring: amdgpu_ring pointer
1130  * @vm: amdgpu_vm pointer
1131  *
1132  * Update the page table base and flush the VM TLB
1133  * using sDMA (VEGA10).
1134  */
1135 static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1136                                          unsigned vmid, uint64_t pd_addr)
1137 {
1138         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1139         uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vmid);
1140         uint64_t flags = AMDGPU_PTE_VALID;
1141         unsigned eng = ring->vm_inv_eng;
1142
1143         amdgpu_gart_get_vm_pde(ring->adev, -1, &pd_addr, &flags);
1144         pd_addr |= flags;
1145
1146         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1147                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1148         amdgpu_ring_write(ring, hub->ctx0_ptb_addr_lo32 + vmid * 2);
1149         amdgpu_ring_write(ring, lower_32_bits(pd_addr));
1150
1151         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1152                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1153         amdgpu_ring_write(ring, hub->ctx0_ptb_addr_hi32 + vmid * 2);
1154         amdgpu_ring_write(ring, upper_32_bits(pd_addr));
1155
1156         /* flush TLB */
1157         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1158                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1159         amdgpu_ring_write(ring, hub->vm_inv_eng0_req + eng);
1160         amdgpu_ring_write(ring, req);
1161
1162         /* wait for flush */
1163         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1164                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1165                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
1166         amdgpu_ring_write(ring, (hub->vm_inv_eng0_ack + eng) << 2);
1167         amdgpu_ring_write(ring, 0);
1168         amdgpu_ring_write(ring, 1 << vmid); /* reference */
1169         amdgpu_ring_write(ring, 1 << vmid); /* mask */
1170         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1171                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
1172 }
1173
1174 static int sdma_v4_0_early_init(void *handle)
1175 {
1176         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1177
1178         if (adev->asic_type == CHIP_RAVEN)
1179                 adev->sdma.num_instances = 1;
1180         else
1181                 adev->sdma.num_instances = 2;
1182
1183         sdma_v4_0_set_ring_funcs(adev);
1184         sdma_v4_0_set_buffer_funcs(adev);
1185         sdma_v4_0_set_vm_pte_funcs(adev);
1186         sdma_v4_0_set_irq_funcs(adev);
1187
1188         return 0;
1189 }
1190
1191
1192 static int sdma_v4_0_sw_init(void *handle)
1193 {
1194         struct amdgpu_ring *ring;
1195         int r, i;
1196         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1197
1198         /* SDMA trap event */
1199         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_SDMA0, 224,
1200                               &adev->sdma.trap_irq);
1201         if (r)
1202                 return r;
1203
1204         /* SDMA trap event */
1205         r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_SDMA1, 224,
1206                               &adev->sdma.trap_irq);
1207         if (r)
1208                 return r;
1209
1210         r = sdma_v4_0_init_microcode(adev);
1211         if (r) {
1212                 DRM_ERROR("Failed to load sdma firmware!\n");
1213                 return r;
1214         }
1215
1216         for (i = 0; i < adev->sdma.num_instances; i++) {
1217                 ring = &adev->sdma.instance[i].ring;
1218                 ring->ring_obj = NULL;
1219                 ring->use_doorbell = true;
1220
1221                 DRM_INFO("use_doorbell being set to: [%s]\n",
1222                                 ring->use_doorbell?"true":"false");
1223
1224                 ring->doorbell_index = (i == 0) ?
1225                         (AMDGPU_DOORBELL64_sDMA_ENGINE0 << 1) //get DWORD offset
1226                         : (AMDGPU_DOORBELL64_sDMA_ENGINE1 << 1); // get DWORD offset
1227
1228                 sprintf(ring->name, "sdma%d", i);
1229                 r = amdgpu_ring_init(adev, ring, 1024,
1230                                      &adev->sdma.trap_irq,
1231                                      (i == 0) ?
1232                                      AMDGPU_SDMA_IRQ_TRAP0 :
1233                                      AMDGPU_SDMA_IRQ_TRAP1);
1234                 if (r)
1235                         return r;
1236         }
1237
1238         return r;
1239 }
1240
1241 static int sdma_v4_0_sw_fini(void *handle)
1242 {
1243         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1244         int i;
1245
1246         for (i = 0; i < adev->sdma.num_instances; i++)
1247                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1248
1249         for (i = 0; i < adev->sdma.num_instances; i++) {
1250                 release_firmware(adev->sdma.instance[i].fw);
1251                 adev->sdma.instance[i].fw = NULL;
1252         }
1253
1254         return 0;
1255 }
1256
1257 static int sdma_v4_0_hw_init(void *handle)
1258 {
1259         int r;
1260         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1261
1262         sdma_v4_0_init_golden_registers(adev);
1263
1264         r = sdma_v4_0_start(adev);
1265
1266         return r;
1267 }
1268
1269 static int sdma_v4_0_hw_fini(void *handle)
1270 {
1271         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1272
1273         if (amdgpu_sriov_vf(adev))
1274                 return 0;
1275
1276         sdma_v4_0_ctx_switch_enable(adev, false);
1277         sdma_v4_0_enable(adev, false);
1278
1279         return 0;
1280 }
1281
1282 static int sdma_v4_0_suspend(void *handle)
1283 {
1284         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1285
1286         return sdma_v4_0_hw_fini(adev);
1287 }
1288
1289 static int sdma_v4_0_resume(void *handle)
1290 {
1291         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1292
1293         return sdma_v4_0_hw_init(adev);
1294 }
1295
1296 static bool sdma_v4_0_is_idle(void *handle)
1297 {
1298         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1299         u32 i;
1300
1301         for (i = 0; i < adev->sdma.num_instances; i++) {
1302                 u32 tmp = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));
1303
1304                 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1305                         return false;
1306         }
1307
1308         return true;
1309 }
1310
1311 static int sdma_v4_0_wait_for_idle(void *handle)
1312 {
1313         unsigned i;
1314         u32 sdma0, sdma1;
1315         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1316
1317         for (i = 0; i < adev->usec_timeout; i++) {
1318                 sdma0 = RREG32(sdma_v4_0_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG));
1319                 sdma1 = RREG32(sdma_v4_0_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG));
1320
1321                 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK)
1322                         return 0;
1323                 udelay(1);
1324         }
1325         return -ETIMEDOUT;
1326 }
1327
1328 static int sdma_v4_0_soft_reset(void *handle)
1329 {
1330         /* todo */
1331
1332         return 0;
1333 }
1334
1335 static int sdma_v4_0_set_trap_irq_state(struct amdgpu_device *adev,
1336                                         struct amdgpu_irq_src *source,
1337                                         unsigned type,
1338                                         enum amdgpu_interrupt_state state)
1339 {
1340         u32 sdma_cntl;
1341
1342         u32 reg_offset = (type == AMDGPU_SDMA_IRQ_TRAP0) ?
1343                 sdma_v4_0_get_reg_offset(adev, 0, mmSDMA0_CNTL) :
1344                 sdma_v4_0_get_reg_offset(adev, 1, mmSDMA0_CNTL);
1345
1346         sdma_cntl = RREG32(reg_offset);
1347         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1348                        state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1349         WREG32(reg_offset, sdma_cntl);
1350
1351         return 0;
1352 }
1353
1354 static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev,
1355                                       struct amdgpu_irq_src *source,
1356                                       struct amdgpu_iv_entry *entry)
1357 {
1358         DRM_DEBUG("IH: SDMA trap\n");
1359         switch (entry->client_id) {
1360         case AMDGPU_IH_CLIENTID_SDMA0:
1361                 switch (entry->ring_id) {
1362                 case 0:
1363                         amdgpu_fence_process(&adev->sdma.instance[0].ring);
1364                         break;
1365                 case 1:
1366                         /* XXX compute */
1367                         break;
1368                 case 2:
1369                         /* XXX compute */
1370                         break;
1371                 case 3:
1372                         /* XXX page queue*/
1373                         break;
1374                 }
1375                 break;
1376         case AMDGPU_IH_CLIENTID_SDMA1:
1377                 switch (entry->ring_id) {
1378                 case 0:
1379                         amdgpu_fence_process(&adev->sdma.instance[1].ring);
1380                         break;
1381                 case 1:
1382                         /* XXX compute */
1383                         break;
1384                 case 2:
1385                         /* XXX compute */
1386                         break;
1387                 case 3:
1388                         /* XXX page queue*/
1389                         break;
1390                 }
1391                 break;
1392         }
1393         return 0;
1394 }
1395
1396 static int sdma_v4_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1397                                               struct amdgpu_irq_src *source,
1398                                               struct amdgpu_iv_entry *entry)
1399 {
1400         DRM_ERROR("Illegal instruction in SDMA command stream\n");
1401         schedule_work(&adev->reset_work);
1402         return 0;
1403 }
1404
1405
1406 static void sdma_v4_0_update_medium_grain_clock_gating(
1407                 struct amdgpu_device *adev,
1408                 bool enable)
1409 {
1410         uint32_t data, def;
1411
1412         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1413                 /* enable sdma0 clock gating */
1414                 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL));
1415                 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1416                           SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1417                           SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1418                           SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1419                           SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1420                           SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1421                           SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1422                           SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1423                 if (def != data)
1424                         WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data);
1425
1426                 if (adev->asic_type == CHIP_VEGA10) {
1427                         def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL));
1428                         data &= ~(SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1429                                   SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1430                                   SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1431                                   SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1432                                   SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1433                                   SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1434                                   SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1435                                   SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1436                         if (def != data)
1437                                 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), data);
1438                 }
1439         } else {
1440                 /* disable sdma0 clock gating */
1441                 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL));
1442                 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1443                          SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1444                          SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1445                          SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1446                          SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1447                          SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1448                          SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1449                          SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1450
1451                 if (def != data)
1452                         WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data);
1453
1454                 if (adev->asic_type == CHIP_VEGA10) {
1455                         def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL));
1456                         data |= (SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1457                                  SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1458                                  SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1459                                  SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1460                                  SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1461                                  SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1462                                  SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1463                                  SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1464                         if (def != data)
1465                                 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), data);
1466                 }
1467         }
1468 }
1469
1470
1471 static void sdma_v4_0_update_medium_grain_light_sleep(
1472                 struct amdgpu_device *adev,
1473                 bool enable)
1474 {
1475         uint32_t data, def;
1476
1477         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1478                 /* 1-not override: enable sdma0 mem light sleep */
1479                 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
1480                 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1481                 if (def != data)
1482                         WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
1483
1484                 /* 1-not override: enable sdma1 mem light sleep */
1485                 if (adev->asic_type == CHIP_VEGA10) {
1486                         def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL));
1487                         data |= SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1488                         if (def != data)
1489                                 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), data);
1490                 }
1491         } else {
1492                 /* 0-override:disable sdma0 mem light sleep */
1493                 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
1494                 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1495                 if (def != data)
1496                         WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);
1497
1498                 /* 0-override:disable sdma1 mem light sleep */
1499                 if (adev->asic_type == CHIP_VEGA10) {
1500                         def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL));
1501                         data &= ~SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1502                         if (def != data)
1503                                 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), data);
1504                 }
1505         }
1506 }
1507
1508 static int sdma_v4_0_set_clockgating_state(void *handle,
1509                                           enum amd_clockgating_state state)
1510 {
1511         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1512
1513         if (amdgpu_sriov_vf(adev))
1514                 return 0;
1515
1516         switch (adev->asic_type) {
1517         case CHIP_VEGA10:
1518         case CHIP_RAVEN:
1519                 sdma_v4_0_update_medium_grain_clock_gating(adev,
1520                                 state == AMD_CG_STATE_GATE ? true : false);
1521                 sdma_v4_0_update_medium_grain_light_sleep(adev,
1522                                 state == AMD_CG_STATE_GATE ? true : false);
1523                 break;
1524         default:
1525                 break;
1526         }
1527         return 0;
1528 }
1529
1530 static int sdma_v4_0_set_powergating_state(void *handle,
1531                                           enum amd_powergating_state state)
1532 {
1533         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1534
1535         switch (adev->asic_type) {
1536         case CHIP_RAVEN:
1537                 sdma_v4_1_update_power_gating(adev,
1538                                 state == AMD_PG_STATE_GATE ? true : false);
1539                 break;
1540         default:
1541                 break;
1542         }
1543
1544         return 0;
1545 }
1546
1547 static void sdma_v4_0_get_clockgating_state(void *handle, u32 *flags)
1548 {
1549         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1550         int data;
1551
1552         if (amdgpu_sriov_vf(adev))
1553                 *flags = 0;
1554
1555         /* AMD_CG_SUPPORT_SDMA_MGCG */
1556         data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL));
1557         if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK))
1558                 *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
1559
1560         /* AMD_CG_SUPPORT_SDMA_LS */
1561         data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
1562         if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1563                 *flags |= AMD_CG_SUPPORT_SDMA_LS;
1564 }
1565
1566 const struct amd_ip_funcs sdma_v4_0_ip_funcs = {
1567         .name = "sdma_v4_0",
1568         .early_init = sdma_v4_0_early_init,
1569         .late_init = NULL,
1570         .sw_init = sdma_v4_0_sw_init,
1571         .sw_fini = sdma_v4_0_sw_fini,
1572         .hw_init = sdma_v4_0_hw_init,
1573         .hw_fini = sdma_v4_0_hw_fini,
1574         .suspend = sdma_v4_0_suspend,
1575         .resume = sdma_v4_0_resume,
1576         .is_idle = sdma_v4_0_is_idle,
1577         .wait_for_idle = sdma_v4_0_wait_for_idle,
1578         .soft_reset = sdma_v4_0_soft_reset,
1579         .set_clockgating_state = sdma_v4_0_set_clockgating_state,
1580         .set_powergating_state = sdma_v4_0_set_powergating_state,
1581         .get_clockgating_state = sdma_v4_0_get_clockgating_state,
1582 };
1583
1584 static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = {
1585         .type = AMDGPU_RING_TYPE_SDMA,
1586         .align_mask = 0xf,
1587         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1588         .support_64bit_ptrs = true,
1589         .vmhub = AMDGPU_MMHUB,
1590         .get_rptr = sdma_v4_0_ring_get_rptr,
1591         .get_wptr = sdma_v4_0_ring_get_wptr,
1592         .set_wptr = sdma_v4_0_ring_set_wptr,
1593         .emit_frame_size =
1594                 6 + /* sdma_v4_0_ring_emit_hdp_flush */
1595                 3 + /* sdma_v4_0_ring_emit_hdp_invalidate */
1596                 6 + /* sdma_v4_0_ring_emit_pipeline_sync */
1597                 18 + /* sdma_v4_0_ring_emit_vm_flush */
1598                 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */
1599         .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */
1600         .emit_ib = sdma_v4_0_ring_emit_ib,
1601         .emit_fence = sdma_v4_0_ring_emit_fence,
1602         .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync,
1603         .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush,
1604         .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush,
1605         .emit_hdp_invalidate = sdma_v4_0_ring_emit_hdp_invalidate,
1606         .test_ring = sdma_v4_0_ring_test_ring,
1607         .test_ib = sdma_v4_0_ring_test_ib,
1608         .insert_nop = sdma_v4_0_ring_insert_nop,
1609         .pad_ib = sdma_v4_0_ring_pad_ib,
1610 };
1611
1612 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev)
1613 {
1614         int i;
1615
1616         for (i = 0; i < adev->sdma.num_instances; i++)
1617                 adev->sdma.instance[i].ring.funcs = &sdma_v4_0_ring_funcs;
1618 }
1619
1620 static const struct amdgpu_irq_src_funcs sdma_v4_0_trap_irq_funcs = {
1621         .set = sdma_v4_0_set_trap_irq_state,
1622         .process = sdma_v4_0_process_trap_irq,
1623 };
1624
1625 static const struct amdgpu_irq_src_funcs sdma_v4_0_illegal_inst_irq_funcs = {
1626         .process = sdma_v4_0_process_illegal_inst_irq,
1627 };
1628
1629 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev)
1630 {
1631         adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1632         adev->sdma.trap_irq.funcs = &sdma_v4_0_trap_irq_funcs;
1633         adev->sdma.illegal_inst_irq.funcs = &sdma_v4_0_illegal_inst_irq_funcs;
1634 }
1635
1636 /**
1637  * sdma_v4_0_emit_copy_buffer - copy buffer using the sDMA engine
1638  *
1639  * @ring: amdgpu_ring structure holding ring information
1640  * @src_offset: src GPU address
1641  * @dst_offset: dst GPU address
1642  * @byte_count: number of bytes to xfer
1643  *
1644  * Copy GPU buffers using the DMA engine (VEGA10).
1645  * Used by the amdgpu ttm implementation to move pages if
1646  * registered as the asic copy callback.
1647  */
1648 static void sdma_v4_0_emit_copy_buffer(struct amdgpu_ib *ib,
1649                                        uint64_t src_offset,
1650                                        uint64_t dst_offset,
1651                                        uint32_t byte_count)
1652 {
1653         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1654                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1655         ib->ptr[ib->length_dw++] = byte_count - 1;
1656         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1657         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1658         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1659         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1660         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1661 }
1662
1663 /**
1664  * sdma_v4_0_emit_fill_buffer - fill buffer using the sDMA engine
1665  *
1666  * @ring: amdgpu_ring structure holding ring information
1667  * @src_data: value to write to buffer
1668  * @dst_offset: dst GPU address
1669  * @byte_count: number of bytes to xfer
1670  *
1671  * Fill GPU buffers using the DMA engine (VEGA10).
1672  */
1673 static void sdma_v4_0_emit_fill_buffer(struct amdgpu_ib *ib,
1674                                        uint32_t src_data,
1675                                        uint64_t dst_offset,
1676                                        uint32_t byte_count)
1677 {
1678         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1679         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1680         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1681         ib->ptr[ib->length_dw++] = src_data;
1682         ib->ptr[ib->length_dw++] = byte_count - 1;
1683 }
1684
1685 static const struct amdgpu_buffer_funcs sdma_v4_0_buffer_funcs = {
1686         .copy_max_bytes = 0x400000,
1687         .copy_num_dw = 7,
1688         .emit_copy_buffer = sdma_v4_0_emit_copy_buffer,
1689
1690         .fill_max_bytes = 0x400000,
1691         .fill_num_dw = 5,
1692         .emit_fill_buffer = sdma_v4_0_emit_fill_buffer,
1693 };
1694
1695 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev)
1696 {
1697         if (adev->mman.buffer_funcs == NULL) {
1698                 adev->mman.buffer_funcs = &sdma_v4_0_buffer_funcs;
1699                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1700         }
1701 }
1702
1703 static const struct amdgpu_vm_pte_funcs sdma_v4_0_vm_pte_funcs = {
1704         .copy_pte_num_dw = 7,
1705         .copy_pte = sdma_v4_0_vm_copy_pte,
1706
1707         .write_pte = sdma_v4_0_vm_write_pte,
1708
1709         .set_max_nums_pte_pde = 0x400000 >> 3,
1710         .set_pte_pde_num_dw = 10,
1711         .set_pte_pde = sdma_v4_0_vm_set_pte_pde,
1712 };
1713
1714 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1715 {
1716         unsigned i;
1717
1718         if (adev->vm_manager.vm_pte_funcs == NULL) {
1719                 adev->vm_manager.vm_pte_funcs = &sdma_v4_0_vm_pte_funcs;
1720                 for (i = 0; i < adev->sdma.num_instances; i++)
1721                         adev->vm_manager.vm_pte_rings[i] =
1722                                 &adev->sdma.instance[i].ring;
1723
1724                 adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances;
1725         }
1726 }
1727
1728 const struct amdgpu_ip_block_version sdma_v4_0_ip_block = {
1729         .type = AMD_IP_BLOCK_TYPE_SDMA,
1730         .major = 4,
1731         .minor = 0,
1732         .rev = 0,
1733         .funcs = &sdma_v4_0_ip_funcs,
1734 };