2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Alex Deucher
24 #include <linux/firmware.h>
27 #include "amdgpu_ucode.h"
28 #include "amdgpu_trace.h"
32 #include "oss/oss_2_4_d.h"
33 #include "oss/oss_2_4_sh_mask.h"
35 #include "gmc/gmc_7_1_d.h"
36 #include "gmc/gmc_7_1_sh_mask.h"
38 #include "gca/gfx_8_0_d.h"
39 #include "gca/gfx_8_0_enum.h"
40 #include "gca/gfx_8_0_sh_mask.h"
42 #include "bif/bif_5_0_d.h"
43 #include "bif/bif_5_0_sh_mask.h"
45 #include "iceland_sdma_pkt_open.h"
47 static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev);
48 static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev);
49 static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev);
50 static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev);
52 MODULE_FIRMWARE("amdgpu/topaz_sdma.bin");
53 MODULE_FIRMWARE("amdgpu/topaz_sdma1.bin");
55 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
57 SDMA0_REGISTER_OFFSET,
61 static const u32 golden_settings_iceland_a11[] =
63 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
64 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
65 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
66 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
69 static const u32 iceland_mgcg_cgcg_init[] =
71 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
72 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
77 * Starting with CIK, the GPU has new asynchronous
78 * DMA engines. These engines are used for compute
79 * and gfx. There are two DMA engines (SDMA0, SDMA1)
80 * and each one supports 1 ring buffer used for gfx
81 * and 2 queues used for compute.
83 * The programming model is very similar to the CP
84 * (ring buffer, IBs, etc.), but sDMA has it's own
85 * packet format that is different from the PM4 format
86 * used by the CP. sDMA supports copying data, writing
87 * embedded data, solid fills, and a number of other
88 * things. It also has support for tiling/detiling of
92 static void sdma_v2_4_init_golden_registers(struct amdgpu_device *adev)
94 switch (adev->asic_type) {
96 amdgpu_program_register_sequence(adev,
97 iceland_mgcg_cgcg_init,
98 (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
99 amdgpu_program_register_sequence(adev,
100 golden_settings_iceland_a11,
101 (const u32)ARRAY_SIZE(golden_settings_iceland_a11));
109 * sdma_v2_4_init_microcode - load ucode images from disk
111 * @adev: amdgpu_device pointer
113 * Use the firmware interface to load the ucode images into
114 * the driver (not loaded into hw).
115 * Returns 0 on success, error on failure.
117 static int sdma_v2_4_init_microcode(struct amdgpu_device *adev)
119 const char *chip_name;
122 struct amdgpu_firmware_info *info = NULL;
123 const struct common_firmware_header *header = NULL;
124 const struct sdma_firmware_header_v1_0 *hdr;
128 switch (adev->asic_type) {
135 for (i = 0; i < adev->sdma.num_instances; i++) {
137 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
139 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
140 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
143 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
146 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
147 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
148 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
149 if (adev->sdma.instance[i].feature_version >= 20)
150 adev->sdma.instance[i].burst_nop = true;
152 if (adev->firmware.smu_load) {
153 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
154 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
155 info->fw = adev->sdma.instance[i].fw;
156 header = (const struct common_firmware_header *)info->fw->data;
157 adev->firmware.fw_size +=
158 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
165 "sdma_v2_4: Failed to load firmware \"%s\"\n",
167 for (i = 0; i < adev->sdma.num_instances; i++) {
168 release_firmware(adev->sdma.instance[i].fw);
169 adev->sdma.instance[i].fw = NULL;
176 * sdma_v2_4_ring_get_rptr - get the current read pointer
178 * @ring: amdgpu ring pointer
180 * Get the current rptr from the hardware (VI+).
182 static uint32_t sdma_v2_4_ring_get_rptr(struct amdgpu_ring *ring)
186 /* XXX check if swapping is necessary on BE */
187 rptr = ring->adev->wb.wb[ring->rptr_offs] >> 2;
193 * sdma_v2_4_ring_get_wptr - get the current write pointer
195 * @ring: amdgpu ring pointer
197 * Get the current wptr from the hardware (VI+).
199 static uint32_t sdma_v2_4_ring_get_wptr(struct amdgpu_ring *ring)
201 struct amdgpu_device *adev = ring->adev;
202 int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
203 u32 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2;
209 * sdma_v2_4_ring_set_wptr - commit the write pointer
211 * @ring: amdgpu ring pointer
213 * Write the wptr back to the hardware (VI+).
215 static void sdma_v2_4_ring_set_wptr(struct amdgpu_ring *ring)
217 struct amdgpu_device *adev = ring->adev;
218 int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
220 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], ring->wptr << 2);
223 static void sdma_v2_4_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
225 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
228 for (i = 0; i < count; i++)
229 if (sdma && sdma->burst_nop && (i == 0))
230 amdgpu_ring_write(ring, ring->nop |
231 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
233 amdgpu_ring_write(ring, ring->nop);
237 * sdma_v2_4_ring_emit_ib - Schedule an IB on the DMA engine
239 * @ring: amdgpu ring pointer
240 * @ib: IB object to schedule
242 * Schedule an IB in the DMA ring (VI).
244 static void sdma_v2_4_ring_emit_ib(struct amdgpu_ring *ring,
245 struct amdgpu_ib *ib,
246 unsigned vm_id, bool ctx_switch)
248 u32 vmid = vm_id & 0xf;
249 u32 next_rptr = ring->wptr + 5;
251 while ((next_rptr & 7) != 2)
256 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
257 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
258 amdgpu_ring_write(ring, lower_32_bits(ring->next_rptr_gpu_addr) & 0xfffffffc);
259 amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr));
260 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
261 amdgpu_ring_write(ring, next_rptr);
263 /* IB packet must end on a 8 DW boundary */
264 sdma_v2_4_ring_insert_nop(ring, (10 - (ring->wptr & 7)) % 8);
266 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
267 SDMA_PKT_INDIRECT_HEADER_VMID(vmid));
268 /* base must be 32 byte aligned */
269 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
270 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
271 amdgpu_ring_write(ring, ib->length_dw);
272 amdgpu_ring_write(ring, 0);
273 amdgpu_ring_write(ring, 0);
278 * sdma_v2_4_hdp_flush_ring_emit - emit an hdp flush on the DMA ring
280 * @ring: amdgpu ring pointer
282 * Emit an hdp flush packet on the requested DMA ring.
284 static void sdma_v2_4_ring_emit_hdp_flush(struct amdgpu_ring *ring)
286 u32 ref_and_mask = 0;
288 if (ring == &ring->adev->sdma.instance[0].ring)
289 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
291 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
293 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
294 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
295 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
296 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
297 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
298 amdgpu_ring_write(ring, ref_and_mask); /* reference */
299 amdgpu_ring_write(ring, ref_and_mask); /* mask */
300 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
301 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
304 static void sdma_v2_4_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
306 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
307 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
308 amdgpu_ring_write(ring, mmHDP_DEBUG0);
309 amdgpu_ring_write(ring, 1);
312 * sdma_v2_4_ring_emit_fence - emit a fence on the DMA ring
314 * @ring: amdgpu ring pointer
315 * @fence: amdgpu fence object
317 * Add a DMA fence packet to the ring to write
318 * the fence seq number and DMA trap packet to generate
319 * an interrupt if needed (VI).
321 static void sdma_v2_4_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
324 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
325 /* write the fence */
326 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
327 amdgpu_ring_write(ring, lower_32_bits(addr));
328 amdgpu_ring_write(ring, upper_32_bits(addr));
329 amdgpu_ring_write(ring, lower_32_bits(seq));
331 /* optionally write high bits as well */
334 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
335 amdgpu_ring_write(ring, lower_32_bits(addr));
336 amdgpu_ring_write(ring, upper_32_bits(addr));
337 amdgpu_ring_write(ring, upper_32_bits(seq));
340 /* generate an interrupt */
341 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
342 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
346 * sdma_v2_4_gfx_stop - stop the gfx async dma engines
348 * @adev: amdgpu_device pointer
350 * Stop the gfx async dma ring buffers (VI).
352 static void sdma_v2_4_gfx_stop(struct amdgpu_device *adev)
354 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
355 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
356 u32 rb_cntl, ib_cntl;
359 if ((adev->mman.buffer_funcs_ring == sdma0) ||
360 (adev->mman.buffer_funcs_ring == sdma1))
361 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
363 for (i = 0; i < adev->sdma.num_instances; i++) {
364 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
365 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
366 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
367 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
368 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
369 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
371 sdma0->ready = false;
372 sdma1->ready = false;
376 * sdma_v2_4_rlc_stop - stop the compute async dma engines
378 * @adev: amdgpu_device pointer
380 * Stop the compute async dma queues (VI).
382 static void sdma_v2_4_rlc_stop(struct amdgpu_device *adev)
388 * sdma_v2_4_enable - stop the async dma engines
390 * @adev: amdgpu_device pointer
391 * @enable: enable/disable the DMA MEs.
393 * Halt or unhalt the async dma engines (VI).
395 static void sdma_v2_4_enable(struct amdgpu_device *adev, bool enable)
400 if (enable == false) {
401 sdma_v2_4_gfx_stop(adev);
402 sdma_v2_4_rlc_stop(adev);
405 for (i = 0; i < adev->sdma.num_instances; i++) {
406 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
408 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);
410 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);
411 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl);
416 * sdma_v2_4_gfx_resume - setup and start the async dma engines
418 * @adev: amdgpu_device pointer
420 * Set up the gfx DMA ring buffers and enable them (VI).
421 * Returns 0 for success, error for failure.
423 static int sdma_v2_4_gfx_resume(struct amdgpu_device *adev)
425 struct amdgpu_ring *ring;
426 u32 rb_cntl, ib_cntl;
431 for (i = 0; i < adev->sdma.num_instances; i++) {
432 ring = &adev->sdma.instance[i].ring;
433 wb_offset = (ring->rptr_offs * 4);
435 mutex_lock(&adev->srbm_mutex);
436 for (j = 0; j < 16; j++) {
437 vi_srbm_select(adev, 0, 0, 0, j);
439 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
440 WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
442 vi_srbm_select(adev, 0, 0, 0, 0);
443 mutex_unlock(&adev->srbm_mutex);
445 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],
446 adev->gfx.config.gb_addr_config & 0x70);
448 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
450 /* Set ring buffer size in dwords */
451 rb_bufsz = order_base_2(ring->ring_size / 4);
452 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
453 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
455 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
456 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
457 RPTR_WRITEBACK_SWAP_ENABLE, 1);
459 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
461 /* Initialize the ring buffer's read and write pointers */
462 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
463 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
465 /* set the wb address whether it's enabled or not */
466 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
467 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
468 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
469 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
471 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
473 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
474 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
477 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
480 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
481 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
483 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
484 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
486 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
489 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
493 r = amdgpu_ring_test_ring(ring);
499 if (adev->mman.buffer_funcs_ring == ring)
500 amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size);
507 * sdma_v2_4_rlc_resume - setup and start the async dma engines
509 * @adev: amdgpu_device pointer
511 * Set up the compute DMA queues and enable them (VI).
512 * Returns 0 for success, error for failure.
514 static int sdma_v2_4_rlc_resume(struct amdgpu_device *adev)
521 * sdma_v2_4_load_microcode - load the sDMA ME ucode
523 * @adev: amdgpu_device pointer
525 * Loads the sDMA0/1 ucode.
526 * Returns 0 for success, -EINVAL if the ucode is not available.
528 static int sdma_v2_4_load_microcode(struct amdgpu_device *adev)
530 const struct sdma_firmware_header_v1_0 *hdr;
531 const __le32 *fw_data;
536 sdma_v2_4_enable(adev, false);
538 for (i = 0; i < adev->sdma.num_instances; i++) {
539 if (!adev->sdma.instance[i].fw)
541 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
542 amdgpu_ucode_print_sdma_hdr(&hdr->header);
543 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
544 fw_data = (const __le32 *)
545 (adev->sdma.instance[i].fw->data +
546 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
547 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
548 for (j = 0; j < fw_size; j++)
549 WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
550 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version);
557 * sdma_v2_4_start - setup and start the async dma engines
559 * @adev: amdgpu_device pointer
561 * Set up the DMA engines and enable them (VI).
562 * Returns 0 for success, error for failure.
564 static int sdma_v2_4_start(struct amdgpu_device *adev)
568 if (!adev->firmware.smu_load) {
569 r = sdma_v2_4_load_microcode(adev);
573 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
574 AMDGPU_UCODE_ID_SDMA0);
577 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
578 AMDGPU_UCODE_ID_SDMA1);
584 sdma_v2_4_enable(adev, true);
586 /* start the gfx rings and rlc compute queues */
587 r = sdma_v2_4_gfx_resume(adev);
590 r = sdma_v2_4_rlc_resume(adev);
598 * sdma_v2_4_ring_test_ring - simple async dma engine test
600 * @ring: amdgpu_ring structure holding ring information
602 * Test the DMA engine by writing using it to write an
603 * value to memory. (VI).
604 * Returns 0 for success, error for failure.
606 static int sdma_v2_4_ring_test_ring(struct amdgpu_ring *ring)
608 struct amdgpu_device *adev = ring->adev;
615 r = amdgpu_wb_get(adev, &index);
617 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
621 gpu_addr = adev->wb.gpu_addr + (index * 4);
623 adev->wb.wb[index] = cpu_to_le32(tmp);
625 r = amdgpu_ring_alloc(ring, 5);
627 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
628 amdgpu_wb_free(adev, index);
632 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
633 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
634 amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
635 amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
636 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
637 amdgpu_ring_write(ring, 0xDEADBEEF);
638 amdgpu_ring_commit(ring);
640 for (i = 0; i < adev->usec_timeout; i++) {
641 tmp = le32_to_cpu(adev->wb.wb[index]);
642 if (tmp == 0xDEADBEEF)
647 if (i < adev->usec_timeout) {
648 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
650 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
654 amdgpu_wb_free(adev, index);
660 * sdma_v2_4_ring_test_ib - test an IB on the DMA engine
662 * @ring: amdgpu_ring structure holding ring information
664 * Test a simple IB in the DMA ring (VI).
665 * Returns 0 on success, error on failure.
667 static int sdma_v2_4_ring_test_ib(struct amdgpu_ring *ring)
669 struct amdgpu_device *adev = ring->adev;
671 struct fence *f = NULL;
678 r = amdgpu_wb_get(adev, &index);
680 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
684 gpu_addr = adev->wb.gpu_addr + (index * 4);
686 adev->wb.wb[index] = cpu_to_le32(tmp);
687 memset(&ib, 0, sizeof(ib));
688 r = amdgpu_ib_get(adev, NULL, 256, &ib);
690 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
694 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
695 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
696 ib.ptr[1] = lower_32_bits(gpu_addr);
697 ib.ptr[2] = upper_32_bits(gpu_addr);
698 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1);
699 ib.ptr[4] = 0xDEADBEEF;
700 ib.ptr[5] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
701 ib.ptr[6] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
702 ib.ptr[7] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
705 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f);
709 r = fence_wait(f, false);
711 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
714 for (i = 0; i < adev->usec_timeout; i++) {
715 tmp = le32_to_cpu(adev->wb.wb[index]);
716 if (tmp == 0xDEADBEEF)
720 if (i < adev->usec_timeout) {
721 DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
725 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
731 amdgpu_ib_free(adev, &ib, NULL);
734 amdgpu_wb_free(adev, index);
739 * sdma_v2_4_vm_copy_pte - update PTEs by copying them from the GART
741 * @ib: indirect buffer to fill with commands
742 * @pe: addr of the page entry
743 * @src: src addr to copy from
744 * @count: number of page entries to update
746 * Update PTEs by copying them from the GART using sDMA (CIK).
748 static void sdma_v2_4_vm_copy_pte(struct amdgpu_ib *ib,
749 uint64_t pe, uint64_t src,
753 unsigned bytes = count * 8;
754 if (bytes > 0x1FFFF8)
757 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
758 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
759 ib->ptr[ib->length_dw++] = bytes;
760 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
761 ib->ptr[ib->length_dw++] = lower_32_bits(src);
762 ib->ptr[ib->length_dw++] = upper_32_bits(src);
763 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
764 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
773 * sdma_v2_4_vm_write_pte - update PTEs by writing them manually
775 * @ib: indirect buffer to fill with commands
776 * @pe: addr of the page entry
777 * @addr: dst addr to write into pe
778 * @count: number of page entries to update
779 * @incr: increase next addr by incr bytes
780 * @flags: access flags
782 * Update PTEs by writing them manually using sDMA (CIK).
784 static void sdma_v2_4_vm_write_pte(struct amdgpu_ib *ib,
785 const dma_addr_t *pages_addr, uint64_t pe,
786 uint64_t addr, unsigned count,
787 uint32_t incr, uint32_t flags)
797 /* for non-physically contiguous pages (system) */
798 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
799 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
800 ib->ptr[ib->length_dw++] = pe;
801 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
802 ib->ptr[ib->length_dw++] = ndw;
803 for (; ndw > 0; ndw -= 2, --count, pe += 8) {
804 value = amdgpu_vm_map_gart(pages_addr, addr);
807 ib->ptr[ib->length_dw++] = value;
808 ib->ptr[ib->length_dw++] = upper_32_bits(value);
814 * sdma_v2_4_vm_set_pte_pde - update the page tables using sDMA
816 * @ib: indirect buffer to fill with commands
817 * @pe: addr of the page entry
818 * @addr: dst addr to write into pe
819 * @count: number of page entries to update
820 * @incr: increase next addr by incr bytes
821 * @flags: access flags
823 * Update the page tables using sDMA (CIK).
825 static void sdma_v2_4_vm_set_pte_pde(struct amdgpu_ib *ib,
827 uint64_t addr, unsigned count,
828 uint32_t incr, uint32_t flags)
838 if (flags & AMDGPU_PTE_VALID)
843 /* for physically contiguous pages (vram) */
844 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE);
845 ib->ptr[ib->length_dw++] = pe; /* dst addr */
846 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
847 ib->ptr[ib->length_dw++] = flags; /* mask */
848 ib->ptr[ib->length_dw++] = 0;
849 ib->ptr[ib->length_dw++] = value; /* value */
850 ib->ptr[ib->length_dw++] = upper_32_bits(value);
851 ib->ptr[ib->length_dw++] = incr; /* increment size */
852 ib->ptr[ib->length_dw++] = 0;
853 ib->ptr[ib->length_dw++] = ndw; /* number of entries */
862 * sdma_v2_4_ring_pad_ib - pad the IB to the required number of dw
864 * @ib: indirect buffer to fill with padding
867 static void sdma_v2_4_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
869 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
873 pad_count = (8 - (ib->length_dw & 0x7)) % 8;
874 for (i = 0; i < pad_count; i++)
875 if (sdma && sdma->burst_nop && (i == 0))
876 ib->ptr[ib->length_dw++] =
877 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
878 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
880 ib->ptr[ib->length_dw++] =
881 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
885 * sdma_v2_4_ring_emit_pipeline_sync - sync the pipeline
887 * @ring: amdgpu_ring pointer
889 * Make sure all previous operations are completed (CIK).
891 static void sdma_v2_4_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
893 uint32_t seq = ring->fence_drv.sync_seq;
894 uint64_t addr = ring->fence_drv.gpu_addr;
897 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
898 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
899 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
900 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
901 amdgpu_ring_write(ring, addr & 0xfffffffc);
902 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
903 amdgpu_ring_write(ring, seq); /* reference */
904 amdgpu_ring_write(ring, 0xfffffff); /* mask */
905 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
906 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
910 * sdma_v2_4_ring_emit_vm_flush - cik vm flush using sDMA
912 * @ring: amdgpu_ring pointer
913 * @vm: amdgpu_vm pointer
915 * Update the page table base and flush the VM TLB
918 static void sdma_v2_4_ring_emit_vm_flush(struct amdgpu_ring *ring,
919 unsigned vm_id, uint64_t pd_addr)
921 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
922 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
924 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
926 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
928 amdgpu_ring_write(ring, pd_addr >> 12);
931 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
932 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
933 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
934 amdgpu_ring_write(ring, 1 << vm_id);
937 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
938 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
939 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */
940 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
941 amdgpu_ring_write(ring, 0);
942 amdgpu_ring_write(ring, 0); /* reference */
943 amdgpu_ring_write(ring, 0); /* mask */
944 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
945 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
948 static int sdma_v2_4_early_init(void *handle)
950 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
952 adev->sdma.num_instances = SDMA_MAX_INSTANCE;
954 sdma_v2_4_set_ring_funcs(adev);
955 sdma_v2_4_set_buffer_funcs(adev);
956 sdma_v2_4_set_vm_pte_funcs(adev);
957 sdma_v2_4_set_irq_funcs(adev);
962 static int sdma_v2_4_sw_init(void *handle)
964 struct amdgpu_ring *ring;
966 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
968 /* SDMA trap event */
969 r = amdgpu_irq_add_id(adev, 224, &adev->sdma.trap_irq);
973 /* SDMA Privileged inst */
974 r = amdgpu_irq_add_id(adev, 241, &adev->sdma.illegal_inst_irq);
978 /* SDMA Privileged inst */
979 r = amdgpu_irq_add_id(adev, 247, &adev->sdma.illegal_inst_irq);
983 r = sdma_v2_4_init_microcode(adev);
985 DRM_ERROR("Failed to load sdma firmware!\n");
989 for (i = 0; i < adev->sdma.num_instances; i++) {
990 ring = &adev->sdma.instance[i].ring;
991 ring->ring_obj = NULL;
992 ring->use_doorbell = false;
993 sprintf(ring->name, "sdma%d", i);
994 r = amdgpu_ring_init(adev, ring, 1024,
995 SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf,
996 &adev->sdma.trap_irq,
998 AMDGPU_SDMA_IRQ_TRAP0 : AMDGPU_SDMA_IRQ_TRAP1,
999 AMDGPU_RING_TYPE_SDMA);
1007 static int sdma_v2_4_sw_fini(void *handle)
1009 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1012 for (i = 0; i < adev->sdma.num_instances; i++)
1013 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1018 static int sdma_v2_4_hw_init(void *handle)
1021 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1023 sdma_v2_4_init_golden_registers(adev);
1025 r = sdma_v2_4_start(adev);
1032 static int sdma_v2_4_hw_fini(void *handle)
1034 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1036 sdma_v2_4_enable(adev, false);
1041 static int sdma_v2_4_suspend(void *handle)
1043 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1045 return sdma_v2_4_hw_fini(adev);
1048 static int sdma_v2_4_resume(void *handle)
1050 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1052 return sdma_v2_4_hw_init(adev);
1055 static bool sdma_v2_4_is_idle(void *handle)
1057 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1058 u32 tmp = RREG32(mmSRBM_STATUS2);
1060 if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
1061 SRBM_STATUS2__SDMA1_BUSY_MASK))
1067 static int sdma_v2_4_wait_for_idle(void *handle)
1071 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1073 for (i = 0; i < adev->usec_timeout; i++) {
1074 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
1075 SRBM_STATUS2__SDMA1_BUSY_MASK);
1084 static int sdma_v2_4_soft_reset(void *handle)
1086 u32 srbm_soft_reset = 0;
1087 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1088 u32 tmp = RREG32(mmSRBM_STATUS2);
1090 if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) {
1092 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
1093 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
1094 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
1095 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1097 if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) {
1099 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
1100 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
1101 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
1102 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1105 if (srbm_soft_reset) {
1106 tmp = RREG32(mmSRBM_SOFT_RESET);
1107 tmp |= srbm_soft_reset;
1108 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1109 WREG32(mmSRBM_SOFT_RESET, tmp);
1110 tmp = RREG32(mmSRBM_SOFT_RESET);
1114 tmp &= ~srbm_soft_reset;
1115 WREG32(mmSRBM_SOFT_RESET, tmp);
1116 tmp = RREG32(mmSRBM_SOFT_RESET);
1118 /* Wait a little for things to settle down */
1125 static int sdma_v2_4_set_trap_irq_state(struct amdgpu_device *adev,
1126 struct amdgpu_irq_src *src,
1128 enum amdgpu_interrupt_state state)
1133 case AMDGPU_SDMA_IRQ_TRAP0:
1135 case AMDGPU_IRQ_STATE_DISABLE:
1136 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1137 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1138 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1140 case AMDGPU_IRQ_STATE_ENABLE:
1141 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1142 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1143 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1149 case AMDGPU_SDMA_IRQ_TRAP1:
1151 case AMDGPU_IRQ_STATE_DISABLE:
1152 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1153 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1154 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1156 case AMDGPU_IRQ_STATE_ENABLE:
1157 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1158 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1159 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1171 static int sdma_v2_4_process_trap_irq(struct amdgpu_device *adev,
1172 struct amdgpu_irq_src *source,
1173 struct amdgpu_iv_entry *entry)
1175 u8 instance_id, queue_id;
1177 instance_id = (entry->ring_id & 0x3) >> 0;
1178 queue_id = (entry->ring_id & 0xc) >> 2;
1179 DRM_DEBUG("IH: SDMA trap\n");
1180 switch (instance_id) {
1184 amdgpu_fence_process(&adev->sdma.instance[0].ring);
1197 amdgpu_fence_process(&adev->sdma.instance[1].ring);
1211 static int sdma_v2_4_process_illegal_inst_irq(struct amdgpu_device *adev,
1212 struct amdgpu_irq_src *source,
1213 struct amdgpu_iv_entry *entry)
1215 DRM_ERROR("Illegal instruction in SDMA command stream\n");
1216 schedule_work(&adev->reset_work);
1220 static int sdma_v2_4_set_clockgating_state(void *handle,
1221 enum amd_clockgating_state state)
1223 /* XXX handled via the smc on VI */
1227 static int sdma_v2_4_set_powergating_state(void *handle,
1228 enum amd_powergating_state state)
1233 const struct amd_ip_funcs sdma_v2_4_ip_funcs = {
1234 .name = "sdma_v2_4",
1235 .early_init = sdma_v2_4_early_init,
1237 .sw_init = sdma_v2_4_sw_init,
1238 .sw_fini = sdma_v2_4_sw_fini,
1239 .hw_init = sdma_v2_4_hw_init,
1240 .hw_fini = sdma_v2_4_hw_fini,
1241 .suspend = sdma_v2_4_suspend,
1242 .resume = sdma_v2_4_resume,
1243 .is_idle = sdma_v2_4_is_idle,
1244 .wait_for_idle = sdma_v2_4_wait_for_idle,
1245 .soft_reset = sdma_v2_4_soft_reset,
1246 .set_clockgating_state = sdma_v2_4_set_clockgating_state,
1247 .set_powergating_state = sdma_v2_4_set_powergating_state,
1250 static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = {
1251 .get_rptr = sdma_v2_4_ring_get_rptr,
1252 .get_wptr = sdma_v2_4_ring_get_wptr,
1253 .set_wptr = sdma_v2_4_ring_set_wptr,
1255 .emit_ib = sdma_v2_4_ring_emit_ib,
1256 .emit_fence = sdma_v2_4_ring_emit_fence,
1257 .emit_pipeline_sync = sdma_v2_4_ring_emit_pipeline_sync,
1258 .emit_vm_flush = sdma_v2_4_ring_emit_vm_flush,
1259 .emit_hdp_flush = sdma_v2_4_ring_emit_hdp_flush,
1260 .emit_hdp_invalidate = sdma_v2_4_ring_emit_hdp_invalidate,
1261 .test_ring = sdma_v2_4_ring_test_ring,
1262 .test_ib = sdma_v2_4_ring_test_ib,
1263 .insert_nop = sdma_v2_4_ring_insert_nop,
1264 .pad_ib = sdma_v2_4_ring_pad_ib,
1267 static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev)
1271 for (i = 0; i < adev->sdma.num_instances; i++)
1272 adev->sdma.instance[i].ring.funcs = &sdma_v2_4_ring_funcs;
1275 static const struct amdgpu_irq_src_funcs sdma_v2_4_trap_irq_funcs = {
1276 .set = sdma_v2_4_set_trap_irq_state,
1277 .process = sdma_v2_4_process_trap_irq,
1280 static const struct amdgpu_irq_src_funcs sdma_v2_4_illegal_inst_irq_funcs = {
1281 .process = sdma_v2_4_process_illegal_inst_irq,
1284 static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev)
1286 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1287 adev->sdma.trap_irq.funcs = &sdma_v2_4_trap_irq_funcs;
1288 adev->sdma.illegal_inst_irq.funcs = &sdma_v2_4_illegal_inst_irq_funcs;
1292 * sdma_v2_4_emit_copy_buffer - copy buffer using the sDMA engine
1294 * @ring: amdgpu_ring structure holding ring information
1295 * @src_offset: src GPU address
1296 * @dst_offset: dst GPU address
1297 * @byte_count: number of bytes to xfer
1299 * Copy GPU buffers using the DMA engine (VI).
1300 * Used by the amdgpu ttm implementation to move pages if
1301 * registered as the asic copy callback.
1303 static void sdma_v2_4_emit_copy_buffer(struct amdgpu_ib *ib,
1304 uint64_t src_offset,
1305 uint64_t dst_offset,
1306 uint32_t byte_count)
1308 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1309 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1310 ib->ptr[ib->length_dw++] = byte_count;
1311 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1312 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1313 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1314 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1315 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1319 * sdma_v2_4_emit_fill_buffer - fill buffer using the sDMA engine
1321 * @ring: amdgpu_ring structure holding ring information
1322 * @src_data: value to write to buffer
1323 * @dst_offset: dst GPU address
1324 * @byte_count: number of bytes to xfer
1326 * Fill GPU buffers using the DMA engine (VI).
1328 static void sdma_v2_4_emit_fill_buffer(struct amdgpu_ib *ib,
1330 uint64_t dst_offset,
1331 uint32_t byte_count)
1333 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1334 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1335 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1336 ib->ptr[ib->length_dw++] = src_data;
1337 ib->ptr[ib->length_dw++] = byte_count;
1340 static const struct amdgpu_buffer_funcs sdma_v2_4_buffer_funcs = {
1341 .copy_max_bytes = 0x1fffff,
1343 .emit_copy_buffer = sdma_v2_4_emit_copy_buffer,
1345 .fill_max_bytes = 0x1fffff,
1347 .emit_fill_buffer = sdma_v2_4_emit_fill_buffer,
1350 static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev)
1352 if (adev->mman.buffer_funcs == NULL) {
1353 adev->mman.buffer_funcs = &sdma_v2_4_buffer_funcs;
1354 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1358 static const struct amdgpu_vm_pte_funcs sdma_v2_4_vm_pte_funcs = {
1359 .copy_pte = sdma_v2_4_vm_copy_pte,
1360 .write_pte = sdma_v2_4_vm_write_pte,
1361 .set_pte_pde = sdma_v2_4_vm_set_pte_pde,
1364 static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev)
1368 if (adev->vm_manager.vm_pte_funcs == NULL) {
1369 adev->vm_manager.vm_pte_funcs = &sdma_v2_4_vm_pte_funcs;
1370 for (i = 0; i < adev->sdma.num_instances; i++)
1371 adev->vm_manager.vm_pte_rings[i] =
1372 &adev->sdma.instance[i].ring;
1374 adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances;