drivers/gpu/drm/amd/amdgpu/psp_v13_0.c

   1 /*
   2  * Copyright 2020 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <drm/drm_drv.h>
  24 #include "amdgpu.h"
  25 #include "amdgpu_psp.h"
  26 #include "amdgpu_ucode.h"
  27 #include "soc15_common.h"
  28 #include "psp_v13_0.h"
  29
  30 #include "mp/mp_13_0_2_offset.h"
  31 #include "mp/mp_13_0_2_sh_mask.h"
  32
  33 MODULE_FIRMWARE("amdgpu/aldebaran_sos.bin");
  34 MODULE_FIRMWARE("amdgpu/aldebaran_ta.bin");
  35 MODULE_FIRMWARE("amdgpu/aldebaran_cap.bin");
  36 MODULE_FIRMWARE("amdgpu/yellow_carp_toc.bin");
  37 MODULE_FIRMWARE("amdgpu/yellow_carp_ta.bin");
  38 MODULE_FIRMWARE("amdgpu/psp_13_0_5_toc.bin");
  39 MODULE_FIRMWARE("amdgpu/psp_13_0_5_ta.bin");
  40 MODULE_FIRMWARE("amdgpu/psp_13_0_8_toc.bin");
  41 MODULE_FIRMWARE("amdgpu/psp_13_0_8_ta.bin");
  42 MODULE_FIRMWARE("amdgpu/psp_13_0_0_sos.bin");
  43 MODULE_FIRMWARE("amdgpu/psp_13_0_0_ta.bin");
  44 MODULE_FIRMWARE("amdgpu/psp_13_0_7_sos.bin");
  45 MODULE_FIRMWARE("amdgpu/psp_13_0_7_ta.bin");
  46
  47 /* For large FW files the time to complete can be very long */
  48 #define USBC_PD_POLLING_LIMIT_S 240
  49
  50 /* Read USB-PD from LFB */
  51 #define GFX_CMD_USB_PD_USE_LFB 0x480
  52
  53 /* VBIOS gfl defines */
  54 #define MBOX_READY_MASK 0x80000000
  55 #define MBOX_STATUS_MASK 0x0000FFFF
  56 #define MBOX_COMMAND_MASK 0x00FF0000
  57 #define MBOX_READY_FLAG 0x80000000
  58 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO 0x2
  59 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI 0x3
  60 #define C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE 0x4
  61
  62 /* memory training timeout define */
  63 #define MEM_TRAIN_SEND_MSG_TIMEOUT_US   3000000
  64
  65 static int psp_v13_0_init_microcode(struct psp_context *psp)
  66 {
  67         struct amdgpu_device *adev = psp->adev;
  68         const char *chip_name;
  69         char ucode_prefix[30];
  70         int err = 0;
  71
  72         switch (adev->ip_versions[MP0_HWIP][0]) {
  73         case IP_VERSION(13, 0, 2):
  74                 chip_name = "aldebaran";
  75                 break;
  76         case IP_VERSION(13, 0, 1):
  77         case IP_VERSION(13, 0, 3):
  78                 chip_name = "yellow_carp";
  79                 break;
  80         default:
  81                 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix));
  82                 chip_name = ucode_prefix;
  83                 break;
  84         }
  85
  86         switch (adev->ip_versions[MP0_HWIP][0]) {
  87         case IP_VERSION(13, 0, 2):
  88                 err = psp_init_sos_microcode(psp, chip_name);
  89                 if (err)
  90                         return err;
  91                 /* It's not necessary to load ras ta on Guest side */
  92                 if (!amdgpu_sriov_vf(adev)) {
  93                         err = psp_init_ta_microcode(&adev->psp, chip_name);
  94                         if (err)
  95                                 return err;
  96                 }
  97                 break;
  98         case IP_VERSION(13, 0, 1):
  99         case IP_VERSION(13, 0, 3):
 100         case IP_VERSION(13, 0, 5):
 101         case IP_VERSION(13, 0, 8):
 102                 err = psp_init_toc_microcode(psp, chip_name);
 103                 if (err)
 104                         return err;
 105                 err = psp_init_ta_microcode(psp, chip_name);
 106                 if (err)
 107                         return err;
 108                 break;
 109         case IP_VERSION(13, 0, 0):
 110         case IP_VERSION(13, 0, 7):
 111                 err = psp_init_sos_microcode(psp, chip_name);
 112                 if (err)
 113                         return err;
 114                 /* It's not necessary to load ras ta on Guest side */
 115                 err = psp_init_ta_microcode(psp, chip_name);
 116                 if (err)
 117                         return err;
 118                 break;
 119         default:
 120                 BUG();
 121         }
 122
 123         return 0;
 124 }
 125
 126 static bool psp_v13_0_is_sos_alive(struct psp_context *psp)
 127 {
 128         struct amdgpu_device *adev = psp->adev;
 129         uint32_t sol_reg;
 130
 131         sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
 132
 133         return sol_reg != 0x0;
 134 }
 135
 136 static int psp_v13_0_wait_for_bootloader(struct psp_context *psp)
 137 {
 138         struct amdgpu_device *adev = psp->adev;
 139
 140         int ret;
 141         int retry_loop;
 142
 143         for (retry_loop = 0; retry_loop < 10; retry_loop++) {
 144                 /* Wait for bootloader to signify that is
 145                     ready having bit 31 of C2PMSG_35 set to 1 */
 146                 ret = psp_wait_for(psp,
 147                                    SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
 148                                    0x80000000,
 149                                    0x80000000,
 150                                    false);
 151
 152                 if (ret == 0)
 153                         return 0;
 154         }
 155
 156         return ret;
 157 }
 158
 159 static int psp_v13_0_bootloader_load_component(struct psp_context       *psp,
 160                                                struct psp_bin_desc      *bin_desc,
 161                                                enum psp_bootloader_cmd  bl_cmd)
 162 {
 163         int ret;
 164         uint32_t psp_gfxdrv_command_reg = 0;
 165         struct amdgpu_device *adev = psp->adev;
 166
 167         /* Check tOS sign of life register to confirm sys driver and sOS
 168          * are already been loaded.
 169          */
 170         if (psp_v13_0_is_sos_alive(psp))
 171                 return 0;
 172
 173         ret = psp_v13_0_wait_for_bootloader(psp);
 174         if (ret)
 175                 return ret;
 176
 177         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 178
 179         /* Copy PSP KDB binary to memory */
 180         memcpy(psp->fw_pri_buf, bin_desc->start_addr, bin_desc->size_bytes);
 181
 182         /* Provide the PSP KDB to bootloader */
 183         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36,
 184                (uint32_t)(psp->fw_pri_mc_addr >> 20));
 185         psp_gfxdrv_command_reg = bl_cmd;
 186         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35,
 187                psp_gfxdrv_command_reg);
 188
 189         ret = psp_v13_0_wait_for_bootloader(psp);
 190
 191         return ret;
 192 }
 193
 194 static int psp_v13_0_bootloader_load_kdb(struct psp_context *psp)
 195 {
 196         return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_KEY_DATABASE);
 197 }
 198
 199 static int psp_v13_0_bootloader_load_spl(struct psp_context *psp)
 200 {
 201         return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_TOS_SPL_TABLE);
 202 }
 203
 204 static int psp_v13_0_bootloader_load_sysdrv(struct psp_context *psp)
 205 {
 206         return psp_v13_0_bootloader_load_component(psp, &psp->sys, PSP_BL__LOAD_SYSDRV);
 207 }
 208
 209 static int psp_v13_0_bootloader_load_soc_drv(struct psp_context *psp)
 210 {
 211         return psp_v13_0_bootloader_load_component(psp, &psp->soc_drv, PSP_BL__LOAD_SOCDRV);
 212 }
 213
 214 static int psp_v13_0_bootloader_load_intf_drv(struct psp_context *psp)
 215 {
 216         return psp_v13_0_bootloader_load_component(psp, &psp->intf_drv, PSP_BL__LOAD_INTFDRV);
 217 }
 218
 219 static int psp_v13_0_bootloader_load_dbg_drv(struct psp_context *psp)
 220 {
 221         return psp_v13_0_bootloader_load_component(psp, &psp->dbg_drv, PSP_BL__LOAD_DBGDRV);
 222 }
 223
 224 static int psp_v13_0_bootloader_load_sos(struct psp_context *psp)
 225 {
 226         int ret;
 227         unsigned int psp_gfxdrv_command_reg = 0;
 228         struct amdgpu_device *adev = psp->adev;
 229
 230         /* Check sOS sign of life register to confirm sys driver and sOS
 231          * are already been loaded.
 232          */
 233         if (psp_v13_0_is_sos_alive(psp))
 234                 return 0;
 235
 236         ret = psp_v13_0_wait_for_bootloader(psp);
 237         if (ret)
 238                 return ret;
 239
 240         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 241
 242         /* Copy Secure OS binary to PSP memory */
 243         memcpy(psp->fw_pri_buf, psp->sos.start_addr, psp->sos.size_bytes);
 244
 245         /* Provide the PSP secure OS to bootloader */
 246         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36,
 247                (uint32_t)(psp->fw_pri_mc_addr >> 20));
 248         psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV;
 249         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35,
 250                psp_gfxdrv_command_reg);
 251
 252         /* there might be handshake issue with hardware which needs delay */
 253         mdelay(20);
 254         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_81),
 255                            RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81),
 256                            0, true);
 257
 258         return ret;
 259 }
 260
 261 static int psp_v13_0_ring_init(struct psp_context *psp,
 262                               enum psp_ring_type ring_type)
 263 {
 264         int ret = 0;
 265         struct psp_ring *ring;
 266         struct amdgpu_device *adev = psp->adev;
 267
 268         ring = &psp->km_ring;
 269
 270         ring->ring_type = ring_type;
 271
 272         /* allocate 4k Page of Local Frame Buffer memory for ring */
 273         ring->ring_size = 0x1000;
 274         ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
 275                                       AMDGPU_GEM_DOMAIN_VRAM,
 276                                       &adev->firmware.rbuf,
 277                                       &ring->ring_mem_mc_addr,
 278                                       (void **)&ring->ring_mem);
 279         if (ret) {
 280                 ring->ring_size = 0;
 281                 return ret;
 282         }
 283
 284         return 0;
 285 }
 286
 287 static int psp_v13_0_ring_stop(struct psp_context *psp,
 288                                enum psp_ring_type ring_type)
 289 {
 290         int ret = 0;
 291         struct amdgpu_device *adev = psp->adev;
 292
 293         if (amdgpu_sriov_vf(adev)) {
 294                 /* Write the ring destroy command*/
 295                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
 296                              GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
 297                 /* there might be handshake issue with hardware which needs delay */
 298                 mdelay(20);
 299                 /* Wait for response flag (bit 31) */
 300                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
 301                                    0x80000000, 0x80000000, false);
 302         } else {
 303                 /* Write the ring destroy command*/
 304                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64,
 305                              GFX_CTRL_CMD_ID_DESTROY_RINGS);
 306                 /* there might be handshake issue with hardware which needs delay */
 307                 mdelay(20);
 308                 /* Wait for response flag (bit 31) */
 309                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
 310                                    0x80000000, 0x80000000, false);
 311         }
 312
 313         return ret;
 314 }
 315
 316 static int psp_v13_0_ring_create(struct psp_context *psp,
 317                                  enum psp_ring_type ring_type)
 318 {
 319         int ret = 0;
 320         unsigned int psp_ring_reg = 0;
 321         struct psp_ring *ring = &psp->km_ring;
 322         struct amdgpu_device *adev = psp->adev;
 323
 324         if (amdgpu_sriov_vf(adev)) {
 325                 ret = psp_v13_0_ring_stop(psp, ring_type);
 326                 if (ret) {
 327                         DRM_ERROR("psp_v13_0_ring_stop_sriov failed!\n");
 328                         return ret;
 329                 }
 330
 331                 /* Write low address of the ring to C2PMSG_102 */
 332                 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
 333                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, psp_ring_reg);
 334                 /* Write high address of the ring to C2PMSG_103 */
 335                 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
 336                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_103, psp_ring_reg);
 337
 338                 /* Write the ring initialization command to C2PMSG_101 */
 339                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
 340                              GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
 341
 342                 /* there might be handshake issue with hardware which needs delay */
 343                 mdelay(20);
 344
 345                 /* Wait for response flag (bit 31) in C2PMSG_101 */
 346                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
 347                                    0x80000000, 0x8000FFFF, false);
 348
 349         } else {
 350                 /* Wait for sOS ready for ring creation */
 351                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
 352                                    0x80000000, 0x80000000, false);
 353                 if (ret) {
 354                         DRM_ERROR("Failed to wait for trust OS ready for ring creation\n");
 355                         return ret;
 356                 }
 357
 358                 /* Write low address of the ring to C2PMSG_69 */
 359                 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
 360                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_69, psp_ring_reg);
 361                 /* Write high address of the ring to C2PMSG_70 */
 362                 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
 363                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_70, psp_ring_reg);
 364                 /* Write size of ring to C2PMSG_71 */
 365                 psp_ring_reg = ring->ring_size;
 366                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_71, psp_ring_reg);
 367                 /* Write the ring initialization command to C2PMSG_64 */
 368                 psp_ring_reg = ring_type;
 369                 psp_ring_reg = psp_ring_reg << 16;
 370                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, psp_ring_reg);
 371
 372                 /* there might be handshake issue with hardware which needs delay */
 373                 mdelay(20);
 374
 375                 /* Wait for response flag (bit 31) in C2PMSG_64 */
 376                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
 377                                    0x80000000, 0x8000FFFF, false);
 378         }
 379
 380         return ret;
 381 }
 382
 383 static int psp_v13_0_ring_destroy(struct psp_context *psp,
 384                                   enum psp_ring_type ring_type)
 385 {
 386         int ret = 0;
 387         struct psp_ring *ring = &psp->km_ring;
 388         struct amdgpu_device *adev = psp->adev;
 389
 390         ret = psp_v13_0_ring_stop(psp, ring_type);
 391         if (ret)
 392                 DRM_ERROR("Fail to stop psp ring\n");
 393
 394         amdgpu_bo_free_kernel(&adev->firmware.rbuf,
 395                               &ring->ring_mem_mc_addr,
 396                               (void **)&ring->ring_mem);
 397
 398         return ret;
 399 }
 400
 401 static uint32_t psp_v13_0_ring_get_wptr(struct psp_context *psp)
 402 {
 403         uint32_t data;
 404         struct amdgpu_device *adev = psp->adev;
 405
 406         if (amdgpu_sriov_vf(adev))
 407                 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102);
 408         else
 409                 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67);
 410
 411         return data;
 412 }
 413
 414 static void psp_v13_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
 415 {
 416         struct amdgpu_device *adev = psp->adev;
 417
 418         if (amdgpu_sriov_vf(adev)) {
 419                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, value);
 420                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
 421                              GFX_CTRL_CMD_ID_CONSUME_CMD);
 422         } else
 423                 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, value);
 424 }
 425
 426 static int psp_v13_0_memory_training_send_msg(struct psp_context *psp, int msg)
 427 {
 428         int ret;
 429         int i;
 430         uint32_t data_32;
 431         int max_wait;
 432         struct amdgpu_device *adev = psp->adev;
 433
 434         data_32 = (psp->mem_train_ctx.c2p_train_data_offset >> 20);
 435         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, data_32);
 436         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, msg);
 437
 438         max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout;
 439         for (i = 0; i < max_wait; i++) {
 440                 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
 441                                    0x80000000, 0x80000000, false);
 442                 if (ret == 0)
 443                         break;
 444         }
 445         if (i < max_wait)
 446                 ret = 0;
 447         else
 448                 ret = -ETIME;
 449
 450         dev_dbg(adev->dev, "training %s %s, cost %d @ %d ms\n",
 451                   (msg == PSP_BL__DRAM_SHORT_TRAIN) ? "short" : "long",
 452                   (ret == 0) ? "succeed" : "failed",
 453                   i, adev->usec_timeout/1000);
 454         return ret;
 455 }
 456
 457
 458 static int psp_v13_0_memory_training(struct psp_context *psp, uint32_t ops)
 459 {
 460         struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
 461         uint32_t *pcache = (uint32_t *)ctx->sys_cache;
 462         struct amdgpu_device *adev = psp->adev;
 463         uint32_t p2c_header[4];
 464         uint32_t sz;
 465         void *buf;
 466         int ret, idx;
 467
 468         if (ctx->init == PSP_MEM_TRAIN_NOT_SUPPORT) {
 469                 dev_dbg(adev->dev, "Memory training is not supported.\n");
 470                 return 0;
 471         } else if (ctx->init != PSP_MEM_TRAIN_INIT_SUCCESS) {
 472                 dev_err(adev->dev, "Memory training initialization failure.\n");
 473                 return -EINVAL;
 474         }
 475
 476         if (psp_v13_0_is_sos_alive(psp)) {
 477                 dev_dbg(adev->dev, "SOS is alive, skip memory training.\n");
 478                 return 0;
 479         }
 480
 481         amdgpu_device_vram_access(adev, ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false);
 482         dev_dbg(adev->dev, "sys_cache[%08x,%08x,%08x,%08x] p2c_header[%08x,%08x,%08x,%08x]\n",
 483                   pcache[0], pcache[1], pcache[2], pcache[3],
 484                   p2c_header[0], p2c_header[1], p2c_header[2], p2c_header[3]);
 485
 486         if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
 487                 dev_dbg(adev->dev, "Short training depends on restore.\n");
 488                 ops |= PSP_MEM_TRAIN_RESTORE;
 489         }
 490
 491         if ((ops & PSP_MEM_TRAIN_RESTORE) &&
 492             pcache[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
 493                 dev_dbg(adev->dev, "sys_cache[0] is invalid, restore depends on save.\n");
 494                 ops |= PSP_MEM_TRAIN_SAVE;
 495         }
 496
 497         if (p2c_header[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
 498             !(pcache[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
 499               pcache[3] == p2c_header[3])) {
 500                 dev_dbg(adev->dev, "sys_cache is invalid or out-of-date, need save training data to sys_cache.\n");
 501                 ops |= PSP_MEM_TRAIN_SAVE;
 502         }
 503
 504         if ((ops & PSP_MEM_TRAIN_SAVE) &&
 505             p2c_header[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
 506                 dev_dbg(adev->dev, "p2c_header[0] is invalid, save depends on long training.\n");
 507                 ops |= PSP_MEM_TRAIN_SEND_LONG_MSG;
 508         }
 509
 510         if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
 511                 ops &= ~PSP_MEM_TRAIN_SEND_SHORT_MSG;
 512                 ops |= PSP_MEM_TRAIN_SAVE;
 513         }
 514
 515         dev_dbg(adev->dev, "Memory training ops:%x.\n", ops);
 516
 517         if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
 518                 /*
 519                  * Long training will encroach a certain amount on the bottom of VRAM;
 520                  * save the content from the bottom of VRAM to system memory
 521                  * before training, and restore it after training to avoid
 522                  * VRAM corruption.
 523                  */
 524                 sz = GDDR6_MEM_TRAINING_ENCROACHED_SIZE;
 525
 526                 if (adev->gmc.visible_vram_size < sz || !adev->mman.aper_base_kaddr) {
 527                         dev_err(adev->dev, "visible_vram_size %llx or aper_base_kaddr %p is not initialized.\n",
 528                                   adev->gmc.visible_vram_size,
 529                                   adev->mman.aper_base_kaddr);
 530                         return -EINVAL;
 531                 }
 532
 533                 buf = vmalloc(sz);
 534                 if (!buf) {
 535                         dev_err(adev->dev, "failed to allocate system memory.\n");
 536                         return -ENOMEM;
 537                 }
 538
 539                 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
 540                         memcpy_fromio(buf, adev->mman.aper_base_kaddr, sz);
 541                         ret = psp_v13_0_memory_training_send_msg(psp, PSP_BL__DRAM_LONG_TRAIN);
 542                         if (ret) {
 543                                 DRM_ERROR("Send long training msg failed.\n");
 544                                 vfree(buf);
 545                                 drm_dev_exit(idx);
 546                                 return ret;
 547                         }
 548
 549                         memcpy_toio(adev->mman.aper_base_kaddr, buf, sz);
 550                         adev->hdp.funcs->flush_hdp(adev, NULL);
 551                         vfree(buf);
 552                         drm_dev_exit(idx);
 553                 } else {
 554                         vfree(buf);
 555                         return -ENODEV;
 556                 }
 557         }
 558
 559         if (ops & PSP_MEM_TRAIN_SAVE) {
 560                 amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, ctx->sys_cache, ctx->train_data_size, false);
 561         }
 562
 563         if (ops & PSP_MEM_TRAIN_RESTORE) {
 564                 amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offset, ctx->sys_cache, ctx->train_data_size, true);
 565         }
 566
 567         if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
 568                 ret = psp_v13_0_memory_training_send_msg(psp, (amdgpu_force_long_training > 0) ?
 569                                                          PSP_BL__DRAM_LONG_TRAIN : PSP_BL__DRAM_SHORT_TRAIN);
 570                 if (ret) {
 571                         dev_err(adev->dev, "send training msg failed.\n");
 572                         return ret;
 573                 }
 574         }
 575         ctx->training_cnt++;
 576         return 0;
 577 }
 578
 579 static int psp_v13_0_load_usbc_pd_fw(struct psp_context *psp, uint64_t fw_pri_mc_addr)
 580 {
 581         struct amdgpu_device *adev = psp->adev;
 582         uint32_t reg_status;
 583         int ret, i = 0;
 584
 585         /*
 586          * LFB address which is aligned to 1MB address and has to be
 587          * right-shifted by 20 so that LFB address can be passed on a 32-bit C2P
 588          * register
 589          */
 590         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, (fw_pri_mc_addr >> 20));
 591
 592         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
 593                              0x80000000, 0x80000000, false);
 594         if (ret)
 595                 return ret;
 596
 597         /* Fireup interrupt so PSP can pick up the address */
 598         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, (GFX_CMD_USB_PD_USE_LFB << 16));
 599
 600         /* FW load takes very long time */
 601         do {
 602                 msleep(1000);
 603                 reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35);
 604
 605                 if (reg_status & 0x80000000)
 606                         goto done;
 607
 608         } while (++i < USBC_PD_POLLING_LIMIT_S);
 609
 610         return -ETIME;
 611 done:
 612
 613         if ((reg_status & 0xFFFF) != 0) {
 614                 DRM_ERROR("Address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = %04x\n",
 615                                 reg_status & 0xFFFF);
 616                 return -EIO;
 617         }
 618
 619         return 0;
 620 }
 621
 622 static int psp_v13_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver)
 623 {
 624         struct amdgpu_device *adev = psp->adev;
 625         int ret;
 626
 627         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER);
 628
 629         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
 630                                      0x80000000, 0x80000000, false);
 631         if (!ret)
 632                 *fw_ver = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36);
 633
 634         return ret;
 635 }
 636
 637 static int psp_v13_0_exec_spi_cmd(struct psp_context *psp, int cmd)
 638 {
 639         uint32_t reg_status = 0, reg_val = 0;
 640         struct amdgpu_device *adev = psp->adev;
 641         int ret;
 642
 643         /* clear MBX ready (MBOX_READY_MASK bit is 0) and set update command */
 644         reg_val |= (cmd << 16);
 645         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115,  reg_val);
 646
 647         /* Ring the doorbell */
 648         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_73, 1);
 649
 650         if (cmd == C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE)
 651                 return 0;
 652
 653         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),
 654                                 MBOX_READY_FLAG, MBOX_READY_MASK, false);
 655         if (ret) {
 656                 dev_err(adev->dev, "SPI cmd %x timed out, ret = %d", cmd, ret);
 657                 return ret;
 658         }
 659
 660         reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115);
 661         if ((reg_status & 0xFFFF) != 0) {
 662                 dev_err(adev->dev, "SPI cmd %x failed, fail status = %04x\n",
 663                                 cmd, reg_status & 0xFFFF);
 664                 return -EIO;
 665         }
 666
 667         return 0;
 668 }
 669
 670 static int psp_v13_0_update_spirom(struct psp_context *psp,
 671                                    uint64_t fw_pri_mc_addr)
 672 {
 673         struct amdgpu_device *adev = psp->adev;
 674         int ret;
 675
 676         /* Confirm PSP is ready to start */
 677         ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),
 678                            MBOX_READY_FLAG, MBOX_READY_MASK, false);
 679         if (ret) {
 680                 dev_err(adev->dev, "PSP Not ready to start processing, ret = %d", ret);
 681                 return ret;
 682         }
 683
 684         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, lower_32_bits(fw_pri_mc_addr));
 685
 686         ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO);
 687         if (ret)
 688                 return ret;
 689
 690         WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, upper_32_bits(fw_pri_mc_addr));
 691
 692         ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI);
 693         if (ret)
 694                 return ret;
 695
 696         psp->vbflash_done = true;
 697
 698         ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE);
 699         if (ret)
 700                 return ret;
 701
 702         return 0;
 703 }
 704
 705 static int psp_v13_0_vbflash_status(struct psp_context *psp)
 706 {
 707         struct amdgpu_device *adev = psp->adev;
 708
 709         return RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115);
 710 }
 711
 712 static const struct psp_funcs psp_v13_0_funcs = {
 713         .init_microcode = psp_v13_0_init_microcode,
 714         .bootloader_load_kdb = psp_v13_0_bootloader_load_kdb,
 715         .bootloader_load_spl = psp_v13_0_bootloader_load_spl,
 716         .bootloader_load_sysdrv = psp_v13_0_bootloader_load_sysdrv,
 717         .bootloader_load_soc_drv = psp_v13_0_bootloader_load_soc_drv,
 718         .bootloader_load_intf_drv = psp_v13_0_bootloader_load_intf_drv,
 719         .bootloader_load_dbg_drv = psp_v13_0_bootloader_load_dbg_drv,
 720         .bootloader_load_sos = psp_v13_0_bootloader_load_sos,
 721         .ring_init = psp_v13_0_ring_init,
 722         .ring_create = psp_v13_0_ring_create,
 723         .ring_stop = psp_v13_0_ring_stop,
 724         .ring_destroy = psp_v13_0_ring_destroy,
 725         .ring_get_wptr = psp_v13_0_ring_get_wptr,
 726         .ring_set_wptr = psp_v13_0_ring_set_wptr,
 727         .mem_training = psp_v13_0_memory_training,
 728         .load_usbc_pd_fw = psp_v13_0_load_usbc_pd_fw,
 729         .read_usbc_pd_fw = psp_v13_0_read_usbc_pd_fw,
 730         .update_spirom = psp_v13_0_update_spirom,
 731         .vbflash_stat = psp_v13_0_vbflash_status
 732 };
 733
 734 void psp_v13_0_set_psp_funcs(struct psp_context *psp)
 735 {
 736         psp->funcs = &psp_v13_0_funcs;
 737 }