drivers/gpu/drm/amd/amdgpu/nv.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <linux/slab.h>
  25 #include <linux/module.h>
  26 #include <linux/pci.h>
  27
  28 #include <drm/amdgpu_drm.h>
  29
  30 #include "amdgpu.h"
  31 #include "amdgpu_atombios.h"
  32 #include "amdgpu_ih.h"
  33 #include "amdgpu_uvd.h"
  34 #include "amdgpu_vce.h"
  35 #include "amdgpu_ucode.h"
  36 #include "amdgpu_psp.h"
  37 #include "atom.h"
  38 #include "amd_pcie.h"
  39
  40 #include "gc/gc_10_1_0_offset.h"
  41 #include "gc/gc_10_1_0_sh_mask.h"
  42 #include "mp/mp_11_0_offset.h"
  43
  44 #include "soc15.h"
  45 #include "soc15_common.h"
  46 #include "gmc_v10_0.h"
  47 #include "gfxhub_v2_0.h"
  48 #include "mmhub_v2_0.h"
  49 #include "nbio_v2_3.h"
  50 #include "nbio_v7_2.h"
  51 #include "hdp_v5_0.h"
  52 #include "nv.h"
  53 #include "navi10_ih.h"
  54 #include "gfx_v10_0.h"
  55 #include "sdma_v5_0.h"
  56 #include "sdma_v5_2.h"
  57 #include "vcn_v2_0.h"
  58 #include "jpeg_v2_0.h"
  59 #include "vcn_v3_0.h"
  60 #include "jpeg_v3_0.h"
  61 #include "amdgpu_vkms.h"
  62 #include "mes_v10_1.h"
  63 #include "mxgpu_nv.h"
  64 #include "smuio_v11_0.h"
  65 #include "smuio_v11_0_6.h"
  66
  67 static const struct amd_ip_funcs nv_common_ip_funcs;
  68
  69 /* Navi */
  70 static const struct amdgpu_video_codec_info nv_video_codecs_encode_array[] =
  71 {
  72         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
  73         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
  74 };
  75
  76 static const struct amdgpu_video_codecs nv_video_codecs_encode =
  77 {
  78         .codec_count = ARRAY_SIZE(nv_video_codecs_encode_array),
  79         .codec_array = nv_video_codecs_encode_array,
  80 };
  81
  82 /* Navi1x */
  83 static const struct amdgpu_video_codec_info nv_video_codecs_decode_array[] =
  84 {
  85         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
  86         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
  87         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
  88         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
  89         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
  90         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
  91         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
  92 };
  93
  94 static const struct amdgpu_video_codecs nv_video_codecs_decode =
  95 {
  96         .codec_count = ARRAY_SIZE(nv_video_codecs_decode_array),
  97         .codec_array = nv_video_codecs_decode_array,
  98 };
  99
 100 /* Sienna Cichlid */
 101 static const struct amdgpu_video_codec_info sc_video_codecs_decode_array_vcn0[] =
 102 {
 103         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
 104         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
 105         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
 106         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
 107         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
 108         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
 109         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
 110         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
 111 };
 112
 113 static const struct amdgpu_video_codec_info sc_video_codecs_decode_array_vcn1[] =
 114 {
 115         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
 116         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
 117         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
 118         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
 119         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
 120         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
 121         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
 122 };
 123
 124 static const struct amdgpu_video_codecs sc_video_codecs_decode_vcn0 =
 125 {
 126         .codec_count = ARRAY_SIZE(sc_video_codecs_decode_array_vcn0),
 127         .codec_array = sc_video_codecs_decode_array_vcn0,
 128 };
 129
 130 static const struct amdgpu_video_codecs sc_video_codecs_decode_vcn1 =
 131 {
 132         .codec_count = ARRAY_SIZE(sc_video_codecs_decode_array_vcn1),
 133         .codec_array = sc_video_codecs_decode_array_vcn1,
 134 };
 135
 136 /* SRIOV Sienna Cichlid, not const since data is controlled by host */
 137 static struct amdgpu_video_codec_info sriov_sc_video_codecs_encode_array[] =
 138 {
 139         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
 140         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
 141 };
 142
 143 static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array_vcn0[] =
 144 {
 145         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
 146         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
 147         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
 148         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
 149         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
 150         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
 151         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
 152         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
 153 };
 154
 155 static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array_vcn1[] =
 156 {
 157         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)},
 158         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)},
 159         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
 160         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)},
 161         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
 162         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
 163         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
 164 };
 165
 166 static struct amdgpu_video_codecs sriov_sc_video_codecs_encode =
 167 {
 168         .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_encode_array),
 169         .codec_array = sriov_sc_video_codecs_encode_array,
 170 };
 171
 172 static struct amdgpu_video_codecs sriov_sc_video_codecs_decode_vcn0 =
 173 {
 174         .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_decode_array_vcn0),
 175         .codec_array = sriov_sc_video_codecs_decode_array_vcn0,
 176 };
 177
 178 static struct amdgpu_video_codecs sriov_sc_video_codecs_decode_vcn1 =
 179 {
 180         .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_decode_array_vcn1),
 181         .codec_array = sriov_sc_video_codecs_decode_array_vcn1,
 182 };
 183
 184 /* Beige Goby*/
 185 static const struct amdgpu_video_codec_info bg_video_codecs_decode_array[] = {
 186         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
 187         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
 188         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
 189 };
 190
 191 static const struct amdgpu_video_codecs bg_video_codecs_decode = {
 192         .codec_count = ARRAY_SIZE(bg_video_codecs_decode_array),
 193         .codec_array = bg_video_codecs_decode_array,
 194 };
 195
 196 static const struct amdgpu_video_codecs bg_video_codecs_encode = {
 197         .codec_count = 0,
 198         .codec_array = NULL,
 199 };
 200
 201 /* Yellow Carp*/
 202 static const struct amdgpu_video_codec_info yc_video_codecs_decode_array[] = {
 203         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
 204         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
 205         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
 206         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
 207         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
 208 };
 209
 210 static const struct amdgpu_video_codecs yc_video_codecs_decode = {
 211         .codec_count = ARRAY_SIZE(yc_video_codecs_decode_array),
 212         .codec_array = yc_video_codecs_decode_array,
 213 };
 214
 215 static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode,
 216                                  const struct amdgpu_video_codecs **codecs)
 217 {
 218         if (adev->vcn.num_vcn_inst == hweight8(adev->vcn.harvest_config))
 219                 return -EINVAL;
 220
 221         switch (adev->ip_versions[UVD_HWIP][0]) {
 222         case IP_VERSION(3, 0, 0):
 223         case IP_VERSION(3, 0, 64):
 224         case IP_VERSION(3, 0, 192):
 225                 if (amdgpu_sriov_vf(adev)) {
 226                         if (adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) {
 227                                 if (encode)
 228                                         *codecs = &sriov_sc_video_codecs_encode;
 229                                 else
 230                                         *codecs = &sriov_sc_video_codecs_decode_vcn1;
 231                         } else {
 232                                 if (encode)
 233                                         *codecs = &sriov_sc_video_codecs_encode;
 234                                 else
 235                                         *codecs = &sriov_sc_video_codecs_decode_vcn0;
 236                         }
 237                 } else {
 238                         if (adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) {
 239                                 if (encode)
 240                                         *codecs = &nv_video_codecs_encode;
 241                                 else
 242                                         *codecs = &sc_video_codecs_decode_vcn1;
 243                         } else {
 244                                 if (encode)
 245                                         *codecs = &nv_video_codecs_encode;
 246                                 else
 247                                         *codecs = &sc_video_codecs_decode_vcn0;
 248                         }
 249                 }
 250                 return 0;
 251         case IP_VERSION(3, 0, 16):
 252         case IP_VERSION(3, 0, 2):
 253                 if (encode)
 254                         *codecs = &nv_video_codecs_encode;
 255                 else
 256                         *codecs = &sc_video_codecs_decode_vcn0;
 257                 return 0;
 258         case IP_VERSION(3, 1, 1):
 259         case IP_VERSION(3, 1, 2):
 260                 if (encode)
 261                         *codecs = &nv_video_codecs_encode;
 262                 else
 263                         *codecs = &yc_video_codecs_decode;
 264                 return 0;
 265         case IP_VERSION(3, 0, 33):
 266                 if (encode)
 267                         *codecs = &bg_video_codecs_encode;
 268                 else
 269                         *codecs = &bg_video_codecs_decode;
 270                 return 0;
 271         case IP_VERSION(2, 0, 0):
 272         case IP_VERSION(2, 0, 2):
 273                 if (encode)
 274                         *codecs = &nv_video_codecs_encode;
 275                 else
 276                         *codecs = &nv_video_codecs_decode;
 277                 return 0;
 278         default:
 279                 return -EINVAL;
 280         }
 281 }
 282
 283 /*
 284  * Indirect registers accessor
 285  */
 286 static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg)
 287 {
 288         unsigned long address, data;
 289         address = adev->nbio.funcs->get_pcie_index_offset(adev);
 290         data = adev->nbio.funcs->get_pcie_data_offset(adev);
 291
 292         return amdgpu_device_indirect_rreg(adev, address, data, reg);
 293 }
 294
 295 static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 296 {
 297         unsigned long address, data;
 298
 299         address = adev->nbio.funcs->get_pcie_index_offset(adev);
 300         data = adev->nbio.funcs->get_pcie_data_offset(adev);
 301
 302         amdgpu_device_indirect_wreg(adev, address, data, reg, v);
 303 }
 304
 305 static u64 nv_pcie_rreg64(struct amdgpu_device *adev, u32 reg)
 306 {
 307         unsigned long address, data;
 308         address = adev->nbio.funcs->get_pcie_index_offset(adev);
 309         data = adev->nbio.funcs->get_pcie_data_offset(adev);
 310
 311         return amdgpu_device_indirect_rreg64(adev, address, data, reg);
 312 }
 313
 314 static void nv_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v)
 315 {
 316         unsigned long address, data;
 317
 318         address = adev->nbio.funcs->get_pcie_index_offset(adev);
 319         data = adev->nbio.funcs->get_pcie_data_offset(adev);
 320
 321         amdgpu_device_indirect_wreg64(adev, address, data, reg, v);
 322 }
 323
 324 static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg)
 325 {
 326         unsigned long flags, address, data;
 327         u32 r;
 328
 329         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 330         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 331
 332         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 333         WREG32(address, (reg));
 334         r = RREG32(data);
 335         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 336         return r;
 337 }
 338
 339 static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 340 {
 341         unsigned long flags, address, data;
 342
 343         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 344         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 345
 346         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 347         WREG32(address, (reg));
 348         WREG32(data, (v));
 349         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 350 }
 351
 352 static u32 nv_get_config_memsize(struct amdgpu_device *adev)
 353 {
 354         return adev->nbio.funcs->get_memsize(adev);
 355 }
 356
 357 static u32 nv_get_xclk(struct amdgpu_device *adev)
 358 {
 359         return adev->clock.spll.reference_freq;
 360 }
 361
 362
 363 void nv_grbm_select(struct amdgpu_device *adev,
 364                      u32 me, u32 pipe, u32 queue, u32 vmid)
 365 {
 366         u32 grbm_gfx_cntl = 0;
 367         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
 368         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
 369         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
 370         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
 371
 372         WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl);
 373 }
 374
 375 static void nv_vga_set_state(struct amdgpu_device *adev, bool state)
 376 {
 377         /* todo */
 378 }
 379
 380 static bool nv_read_disabled_bios(struct amdgpu_device *adev)
 381 {
 382         /* todo */
 383         return false;
 384 }
 385
 386 static struct soc15_allowed_register_entry nv_allowed_read_registers[] = {
 387         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
 388         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
 389         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
 390         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
 391         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
 392         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
 393         { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
 394         { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
 395         { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
 396         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
 397         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
 398         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
 399         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
 400         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
 401         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
 402         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)},
 403         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
 404         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
 405         { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
 406 };
 407
 408 static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
 409                                          u32 sh_num, u32 reg_offset)
 410 {
 411         uint32_t val;
 412
 413         mutex_lock(&adev->grbm_idx_mutex);
 414         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 415                 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
 416
 417         val = RREG32(reg_offset);
 418
 419         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 420                 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
 421         mutex_unlock(&adev->grbm_idx_mutex);
 422         return val;
 423 }
 424
 425 static uint32_t nv_get_register_value(struct amdgpu_device *adev,
 426                                       bool indexed, u32 se_num,
 427                                       u32 sh_num, u32 reg_offset)
 428 {
 429         if (indexed) {
 430                 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset);
 431         } else {
 432                 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
 433                         return adev->gfx.config.gb_addr_config;
 434                 return RREG32(reg_offset);
 435         }
 436 }
 437
 438 static int nv_read_register(struct amdgpu_device *adev, u32 se_num,
 439                             u32 sh_num, u32 reg_offset, u32 *value)
 440 {
 441         uint32_t i;
 442         struct soc15_allowed_register_entry  *en;
 443
 444         *value = 0;
 445         for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) {
 446                 en = &nv_allowed_read_registers[i];
 447                 if (adev->reg_offset[en->hwip][en->inst] &&
 448                     reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
 449                                    + en->reg_offset))
 450                         continue;
 451
 452                 *value = nv_get_register_value(adev,
 453                                                nv_allowed_read_registers[i].grbm_indexed,
 454                                                se_num, sh_num, reg_offset);
 455                 return 0;
 456         }
 457         return -EINVAL;
 458 }
 459
 460 static int nv_asic_mode2_reset(struct amdgpu_device *adev)
 461 {
 462         u32 i;
 463         int ret = 0;
 464
 465         amdgpu_atombios_scratch_regs_engine_hung(adev, true);
 466
 467         /* disable BM */
 468         pci_clear_master(adev->pdev);
 469
 470         amdgpu_device_cache_pci_state(adev->pdev);
 471
 472         ret = amdgpu_dpm_mode2_reset(adev);
 473         if (ret)
 474                 dev_err(adev->dev, "GPU mode2 reset failed\n");
 475
 476         amdgpu_device_load_pci_state(adev->pdev);
 477
 478         /* wait for asic to come out of reset */
 479         for (i = 0; i < adev->usec_timeout; i++) {
 480                 u32 memsize = adev->nbio.funcs->get_memsize(adev);
 481
 482                 if (memsize != 0xffffffff)
 483                         break;
 484                 udelay(1);
 485         }
 486
 487         amdgpu_atombios_scratch_regs_engine_hung(adev, false);
 488
 489         return ret;
 490 }
 491
 492 static enum amd_reset_method
 493 nv_asic_reset_method(struct amdgpu_device *adev)
 494 {
 495         if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 ||
 496             amdgpu_reset_method == AMD_RESET_METHOD_MODE2 ||
 497             amdgpu_reset_method == AMD_RESET_METHOD_BACO ||
 498             amdgpu_reset_method == AMD_RESET_METHOD_PCI)
 499                 return amdgpu_reset_method;
 500
 501         if (amdgpu_reset_method != -1)
 502                 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
 503                                   amdgpu_reset_method);
 504
 505         switch (adev->ip_versions[MP1_HWIP][0]) {
 506         case IP_VERSION(11, 5, 0):
 507         case IP_VERSION(13, 0, 1):
 508         case IP_VERSION(13, 0, 3):
 509         case IP_VERSION(13, 0, 5):
 510         case IP_VERSION(13, 0, 8):
 511                 return AMD_RESET_METHOD_MODE2;
 512         case IP_VERSION(11, 0, 7):
 513         case IP_VERSION(11, 0, 11):
 514         case IP_VERSION(11, 0, 12):
 515         case IP_VERSION(11, 0, 13):
 516                 return AMD_RESET_METHOD_MODE1;
 517         default:
 518                 if (amdgpu_dpm_is_baco_supported(adev))
 519                         return AMD_RESET_METHOD_BACO;
 520                 else
 521                         return AMD_RESET_METHOD_MODE1;
 522         }
 523 }
 524
 525 static int nv_asic_reset(struct amdgpu_device *adev)
 526 {
 527         int ret = 0;
 528
 529         switch (nv_asic_reset_method(adev)) {
 530         case AMD_RESET_METHOD_PCI:
 531                 dev_info(adev->dev, "PCI reset\n");
 532                 ret = amdgpu_device_pci_reset(adev);
 533                 break;
 534         case AMD_RESET_METHOD_BACO:
 535                 dev_info(adev->dev, "BACO reset\n");
 536                 ret = amdgpu_dpm_baco_reset(adev);
 537                 break;
 538         case AMD_RESET_METHOD_MODE2:
 539                 dev_info(adev->dev, "MODE2 reset\n");
 540                 ret = nv_asic_mode2_reset(adev);
 541                 break;
 542         default:
 543                 dev_info(adev->dev, "MODE1 reset\n");
 544                 ret = amdgpu_device_mode1_reset(adev);
 545                 break;
 546         }
 547
 548         return ret;
 549 }
 550
 551 static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
 552 {
 553         /* todo */
 554         return 0;
 555 }
 556
 557 static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
 558 {
 559         /* todo */
 560         return 0;
 561 }
 562
 563 static void nv_pcie_gen3_enable(struct amdgpu_device *adev)
 564 {
 565         if (pci_is_root_bus(adev->pdev->bus))
 566                 return;
 567
 568         if (amdgpu_pcie_gen2 == 0)
 569                 return;
 570
 571         if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
 572                                         CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
 573                 return;
 574
 575         /* todo */
 576 }
 577
 578 static void nv_program_aspm(struct amdgpu_device *adev)
 579 {
 580         if (!amdgpu_device_should_use_aspm(adev))
 581                 return;
 582
 583         if (!(adev->flags & AMD_IS_APU) &&
 584             (adev->nbio.funcs->program_aspm))
 585                 adev->nbio.funcs->program_aspm(adev);
 586
 587 }
 588
 589 static void nv_enable_doorbell_aperture(struct amdgpu_device *adev,
 590                                         bool enable)
 591 {
 592         adev->nbio.funcs->enable_doorbell_aperture(adev, enable);
 593         adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable);
 594 }
 595
 596 const struct amdgpu_ip_block_version nv_common_ip_block =
 597 {
 598         .type = AMD_IP_BLOCK_TYPE_COMMON,
 599         .major = 1,
 600         .minor = 0,
 601         .rev = 0,
 602         .funcs = &nv_common_ip_funcs,
 603 };
 604
 605 void nv_set_virt_ops(struct amdgpu_device *adev)
 606 {
 607         adev->virt.ops = &xgpu_nv_virt_ops;
 608 }
 609
 610 static uint32_t nv_get_rev_id(struct amdgpu_device *adev)
 611 {
 612         return adev->nbio.funcs->get_rev_id(adev);
 613 }
 614
 615 static bool nv_need_full_reset(struct amdgpu_device *adev)
 616 {
 617         return true;
 618 }
 619
 620 static bool nv_need_reset_on_init(struct amdgpu_device *adev)
 621 {
 622         u32 sol_reg;
 623
 624         if (adev->flags & AMD_IS_APU)
 625                 return false;
 626
 627         /* Check sOS sign of life register to confirm sys driver and sOS
 628          * are already been loaded.
 629          */
 630         sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
 631         if (sol_reg)
 632                 return true;
 633
 634         return false;
 635 }
 636
 637 static uint64_t nv_get_pcie_replay_count(struct amdgpu_device *adev)
 638 {
 639
 640         /* TODO
 641          * dummy implement for pcie_replay_count sysfs interface
 642          * */
 643
 644         return 0;
 645 }
 646
 647 static void nv_init_doorbell_index(struct amdgpu_device *adev)
 648 {
 649         adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ;
 650         adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0;
 651         adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1;
 652         adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2;
 653         adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3;
 654         adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4;
 655         adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5;
 656         adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6;
 657         adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7;
 658         adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START;
 659         adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END;
 660         adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0;
 661         adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1;
 662         adev->doorbell_index.gfx_userqueue_start =
 663                 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_START;
 664         adev->doorbell_index.gfx_userqueue_end =
 665                 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_END;
 666         adev->doorbell_index.mes_ring0 = AMDGPU_NAVI10_DOORBELL_MES_RING0;
 667         adev->doorbell_index.mes_ring1 = AMDGPU_NAVI10_DOORBELL_MES_RING1;
 668         adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0;
 669         adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1;
 670         adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2;
 671         adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3;
 672         adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH;
 673         adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1;
 674         adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3;
 675         adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5;
 676         adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7;
 677         adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP;
 678         adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP;
 679
 680         adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1;
 681         adev->doorbell_index.sdma_doorbell_range = 20;
 682 }
 683
 684 static void nv_pre_asic_init(struct amdgpu_device *adev)
 685 {
 686 }
 687
 688 static int nv_update_umd_stable_pstate(struct amdgpu_device *adev,
 689                                        bool enter)
 690 {
 691         if (enter)
 692                 amdgpu_gfx_rlc_enter_safe_mode(adev);
 693         else
 694                 amdgpu_gfx_rlc_exit_safe_mode(adev);
 695
 696         if (adev->gfx.funcs->update_perfmon_mgcg)
 697                 adev->gfx.funcs->update_perfmon_mgcg(adev, !enter);
 698
 699         if (!(adev->flags & AMD_IS_APU) &&
 700             (adev->nbio.funcs->enable_aspm) &&
 701              amdgpu_device_should_use_aspm(adev))
 702                 adev->nbio.funcs->enable_aspm(adev, !enter);
 703
 704         return 0;
 705 }
 706
 707 static const struct amdgpu_asic_funcs nv_asic_funcs =
 708 {
 709         .read_disabled_bios = &nv_read_disabled_bios,
 710         .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom,
 711         .read_register = &nv_read_register,
 712         .reset = &nv_asic_reset,
 713         .reset_method = &nv_asic_reset_method,
 714         .set_vga_state = &nv_vga_set_state,
 715         .get_xclk = &nv_get_xclk,
 716         .set_uvd_clocks = &nv_set_uvd_clocks,
 717         .set_vce_clocks = &nv_set_vce_clocks,
 718         .get_config_memsize = &nv_get_config_memsize,
 719         .init_doorbell_index = &nv_init_doorbell_index,
 720         .need_full_reset = &nv_need_full_reset,
 721         .need_reset_on_init = &nv_need_reset_on_init,
 722         .get_pcie_replay_count = &nv_get_pcie_replay_count,
 723         .supports_baco = &amdgpu_dpm_is_baco_supported,
 724         .pre_asic_init = &nv_pre_asic_init,
 725         .update_umd_stable_pstate = &nv_update_umd_stable_pstate,
 726         .query_video_codecs = &nv_query_video_codecs,
 727 };
 728
 729 static int nv_common_early_init(void *handle)
 730 {
 731 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
 732         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 733
 734         if (!amdgpu_sriov_vf(adev)) {
 735                 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
 736                 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
 737         }
 738         adev->smc_rreg = NULL;
 739         adev->smc_wreg = NULL;
 740         adev->pcie_rreg = &nv_pcie_rreg;
 741         adev->pcie_wreg = &nv_pcie_wreg;
 742         adev->pcie_rreg64 = &nv_pcie_rreg64;
 743         adev->pcie_wreg64 = &nv_pcie_wreg64;
 744         adev->pciep_rreg = amdgpu_device_pcie_port_rreg;
 745         adev->pciep_wreg = amdgpu_device_pcie_port_wreg;
 746
 747         /* TODO: will add them during VCN v2 implementation */
 748         adev->uvd_ctx_rreg = NULL;
 749         adev->uvd_ctx_wreg = NULL;
 750
 751         adev->didt_rreg = &nv_didt_rreg;
 752         adev->didt_wreg = &nv_didt_wreg;
 753
 754         adev->asic_funcs = &nv_asic_funcs;
 755
 756         adev->rev_id = nv_get_rev_id(adev);
 757         adev->external_rev_id = 0xff;
 758         /* TODO: split the GC and PG flags based on the relevant IP version for which
 759          * they are relevant.
 760          */
 761         switch (adev->ip_versions[GC_HWIP][0]) {
 762         case IP_VERSION(10, 1, 10):
 763                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 764                         AMD_CG_SUPPORT_GFX_CGCG |
 765                         AMD_CG_SUPPORT_IH_CG |
 766                         AMD_CG_SUPPORT_HDP_MGCG |
 767                         AMD_CG_SUPPORT_HDP_LS |
 768                         AMD_CG_SUPPORT_SDMA_MGCG |
 769                         AMD_CG_SUPPORT_SDMA_LS |
 770                         AMD_CG_SUPPORT_MC_MGCG |
 771                         AMD_CG_SUPPORT_MC_LS |
 772                         AMD_CG_SUPPORT_ATHUB_MGCG |
 773                         AMD_CG_SUPPORT_ATHUB_LS |
 774                         AMD_CG_SUPPORT_VCN_MGCG |
 775                         AMD_CG_SUPPORT_JPEG_MGCG |
 776                         AMD_CG_SUPPORT_BIF_MGCG |
 777                         AMD_CG_SUPPORT_BIF_LS;
 778                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 779                         AMD_PG_SUPPORT_VCN_DPG |
 780                         AMD_PG_SUPPORT_JPEG |
 781                         AMD_PG_SUPPORT_ATHUB;
 782                 adev->external_rev_id = adev->rev_id + 0x1;
 783                 break;
 784         case IP_VERSION(10, 1, 1):
 785                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 786                         AMD_CG_SUPPORT_GFX_CGCG |
 787                         AMD_CG_SUPPORT_IH_CG |
 788                         AMD_CG_SUPPORT_HDP_MGCG |
 789                         AMD_CG_SUPPORT_HDP_LS |
 790                         AMD_CG_SUPPORT_SDMA_MGCG |
 791                         AMD_CG_SUPPORT_SDMA_LS |
 792                         AMD_CG_SUPPORT_MC_MGCG |
 793                         AMD_CG_SUPPORT_MC_LS |
 794                         AMD_CG_SUPPORT_ATHUB_MGCG |
 795                         AMD_CG_SUPPORT_ATHUB_LS |
 796                         AMD_CG_SUPPORT_VCN_MGCG |
 797                         AMD_CG_SUPPORT_JPEG_MGCG |
 798                         AMD_CG_SUPPORT_BIF_MGCG |
 799                         AMD_CG_SUPPORT_BIF_LS;
 800                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 801                         AMD_PG_SUPPORT_JPEG |
 802                         AMD_PG_SUPPORT_VCN_DPG;
 803                 adev->external_rev_id = adev->rev_id + 20;
 804                 break;
 805         case IP_VERSION(10, 1, 2):
 806                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 807                         AMD_CG_SUPPORT_GFX_MGLS |
 808                         AMD_CG_SUPPORT_GFX_CGCG |
 809                         AMD_CG_SUPPORT_GFX_CP_LS |
 810                         AMD_CG_SUPPORT_GFX_RLC_LS |
 811                         AMD_CG_SUPPORT_IH_CG |
 812                         AMD_CG_SUPPORT_HDP_MGCG |
 813                         AMD_CG_SUPPORT_HDP_LS |
 814                         AMD_CG_SUPPORT_SDMA_MGCG |
 815                         AMD_CG_SUPPORT_SDMA_LS |
 816                         AMD_CG_SUPPORT_MC_MGCG |
 817                         AMD_CG_SUPPORT_MC_LS |
 818                         AMD_CG_SUPPORT_ATHUB_MGCG |
 819                         AMD_CG_SUPPORT_ATHUB_LS |
 820                         AMD_CG_SUPPORT_VCN_MGCG |
 821                         AMD_CG_SUPPORT_JPEG_MGCG;
 822                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 823                         AMD_PG_SUPPORT_VCN_DPG |
 824                         AMD_PG_SUPPORT_JPEG |
 825                         AMD_PG_SUPPORT_ATHUB;
 826                 /* guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0,
 827                  * as a consequence, the rev_id and external_rev_id are wrong.
 828                  * workaround it by hardcoding rev_id to 0 (default value).
 829                  */
 830                 if (amdgpu_sriov_vf(adev))
 831                         adev->rev_id = 0;
 832                 adev->external_rev_id = adev->rev_id + 0xa;
 833                 break;
 834         case IP_VERSION(10, 3, 0):
 835                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 836                         AMD_CG_SUPPORT_GFX_CGCG |
 837                         AMD_CG_SUPPORT_GFX_CGLS |
 838                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 839                         AMD_CG_SUPPORT_MC_MGCG |
 840                         AMD_CG_SUPPORT_VCN_MGCG |
 841                         AMD_CG_SUPPORT_JPEG_MGCG |
 842                         AMD_CG_SUPPORT_HDP_MGCG |
 843                         AMD_CG_SUPPORT_HDP_LS |
 844                         AMD_CG_SUPPORT_IH_CG |
 845                         AMD_CG_SUPPORT_MC_LS;
 846                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 847                         AMD_PG_SUPPORT_VCN_DPG |
 848                         AMD_PG_SUPPORT_JPEG |
 849                         AMD_PG_SUPPORT_ATHUB |
 850                         AMD_PG_SUPPORT_MMHUB;
 851                 if (amdgpu_sriov_vf(adev)) {
 852                         /* hypervisor control CG and PG enablement */
 853                         adev->cg_flags = 0;
 854                         adev->pg_flags = 0;
 855                 }
 856                 adev->external_rev_id = adev->rev_id + 0x28;
 857                 break;
 858         case IP_VERSION(10, 3, 2):
 859                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 860                         AMD_CG_SUPPORT_GFX_CGCG |
 861                         AMD_CG_SUPPORT_GFX_CGLS |
 862                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 863                         AMD_CG_SUPPORT_VCN_MGCG |
 864                         AMD_CG_SUPPORT_JPEG_MGCG |
 865                         AMD_CG_SUPPORT_MC_MGCG |
 866                         AMD_CG_SUPPORT_MC_LS |
 867                         AMD_CG_SUPPORT_HDP_MGCG |
 868                         AMD_CG_SUPPORT_HDP_LS |
 869                         AMD_CG_SUPPORT_IH_CG;
 870                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 871                         AMD_PG_SUPPORT_VCN_DPG |
 872                         AMD_PG_SUPPORT_JPEG |
 873                         AMD_PG_SUPPORT_ATHUB |
 874                         AMD_PG_SUPPORT_MMHUB;
 875                 adev->external_rev_id = adev->rev_id + 0x32;
 876                 break;
 877         case IP_VERSION(10, 3, 1):
 878                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 879                         AMD_CG_SUPPORT_GFX_MGLS |
 880                         AMD_CG_SUPPORT_GFX_CP_LS |
 881                         AMD_CG_SUPPORT_GFX_RLC_LS |
 882                         AMD_CG_SUPPORT_GFX_CGCG |
 883                         AMD_CG_SUPPORT_GFX_CGLS |
 884                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 885                         AMD_CG_SUPPORT_GFX_3D_CGLS |
 886                         AMD_CG_SUPPORT_MC_MGCG |
 887                         AMD_CG_SUPPORT_MC_LS |
 888                         AMD_CG_SUPPORT_GFX_FGCG |
 889                         AMD_CG_SUPPORT_VCN_MGCG |
 890                         AMD_CG_SUPPORT_SDMA_MGCG |
 891                         AMD_CG_SUPPORT_SDMA_LS |
 892                         AMD_CG_SUPPORT_JPEG_MGCG;
 893                 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG |
 894                         AMD_PG_SUPPORT_VCN |
 895                         AMD_PG_SUPPORT_VCN_DPG |
 896                         AMD_PG_SUPPORT_JPEG;
 897                 if (adev->apu_flags & AMD_APU_IS_VANGOGH)
 898                         adev->external_rev_id = adev->rev_id + 0x01;
 899                 break;
 900         case IP_VERSION(10, 3, 4):
 901                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 902                         AMD_CG_SUPPORT_GFX_CGCG |
 903                         AMD_CG_SUPPORT_GFX_CGLS |
 904                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 905                         AMD_CG_SUPPORT_VCN_MGCG |
 906                         AMD_CG_SUPPORT_JPEG_MGCG |
 907                         AMD_CG_SUPPORT_MC_MGCG |
 908                         AMD_CG_SUPPORT_MC_LS |
 909                         AMD_CG_SUPPORT_HDP_MGCG |
 910                         AMD_CG_SUPPORT_HDP_LS |
 911                         AMD_CG_SUPPORT_IH_CG;
 912                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 913                         AMD_PG_SUPPORT_VCN_DPG |
 914                         AMD_PG_SUPPORT_JPEG |
 915                         AMD_PG_SUPPORT_ATHUB |
 916                         AMD_PG_SUPPORT_MMHUB;
 917                 adev->external_rev_id = adev->rev_id + 0x3c;
 918                 break;
 919         case IP_VERSION(10, 3, 5):
 920                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 921                         AMD_CG_SUPPORT_GFX_CGCG |
 922                         AMD_CG_SUPPORT_GFX_CGLS |
 923                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 924                         AMD_CG_SUPPORT_MC_MGCG |
 925                         AMD_CG_SUPPORT_MC_LS |
 926                         AMD_CG_SUPPORT_HDP_MGCG |
 927                         AMD_CG_SUPPORT_HDP_LS |
 928                         AMD_CG_SUPPORT_IH_CG |
 929                         AMD_CG_SUPPORT_VCN_MGCG;
 930                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 931                         AMD_PG_SUPPORT_VCN_DPG |
 932                         AMD_PG_SUPPORT_ATHUB |
 933                         AMD_PG_SUPPORT_MMHUB;
 934                 adev->external_rev_id = adev->rev_id + 0x46;
 935                 break;
 936         case IP_VERSION(10, 3, 3):
 937                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 938                         AMD_CG_SUPPORT_GFX_MGLS |
 939                         AMD_CG_SUPPORT_GFX_CGCG |
 940                         AMD_CG_SUPPORT_GFX_CGLS |
 941                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 942                         AMD_CG_SUPPORT_GFX_3D_CGLS |
 943                         AMD_CG_SUPPORT_GFX_RLC_LS |
 944                         AMD_CG_SUPPORT_GFX_CP_LS |
 945                         AMD_CG_SUPPORT_GFX_FGCG |
 946                         AMD_CG_SUPPORT_MC_MGCG |
 947                         AMD_CG_SUPPORT_MC_LS |
 948                         AMD_CG_SUPPORT_SDMA_LS |
 949                         AMD_CG_SUPPORT_HDP_MGCG |
 950                         AMD_CG_SUPPORT_HDP_LS |
 951                         AMD_CG_SUPPORT_ATHUB_MGCG |
 952                         AMD_CG_SUPPORT_ATHUB_LS |
 953                         AMD_CG_SUPPORT_IH_CG |
 954                         AMD_CG_SUPPORT_VCN_MGCG |
 955                         AMD_CG_SUPPORT_JPEG_MGCG;
 956                 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG |
 957                         AMD_PG_SUPPORT_VCN |
 958                         AMD_PG_SUPPORT_VCN_DPG |
 959                         AMD_PG_SUPPORT_JPEG;
 960                 if (adev->pdev->device == 0x1681)
 961                         adev->external_rev_id = 0x20;
 962                 else
 963                         adev->external_rev_id = adev->rev_id + 0x01;
 964                 break;
 965         case IP_VERSION(10, 1, 3):
 966         case IP_VERSION(10, 1, 4):
 967                 adev->cg_flags = 0;
 968                 adev->pg_flags = 0;
 969                 adev->external_rev_id = adev->rev_id + 0x82;
 970                 break;
 971         case IP_VERSION(10, 3, 6):
 972                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 973                         AMD_CG_SUPPORT_GFX_MGLS |
 974                         AMD_CG_SUPPORT_GFX_CGCG |
 975                         AMD_CG_SUPPORT_GFX_CGLS |
 976                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 977                         AMD_CG_SUPPORT_GFX_3D_CGLS |
 978                         AMD_CG_SUPPORT_GFX_RLC_LS |
 979                         AMD_CG_SUPPORT_GFX_CP_LS |
 980                         AMD_CG_SUPPORT_GFX_FGCG |
 981                         AMD_CG_SUPPORT_MC_MGCG |
 982                         AMD_CG_SUPPORT_MC_LS |
 983                         AMD_CG_SUPPORT_SDMA_LS |
 984                         AMD_CG_SUPPORT_HDP_MGCG |
 985                         AMD_CG_SUPPORT_HDP_LS |
 986                         AMD_CG_SUPPORT_ATHUB_MGCG |
 987                         AMD_CG_SUPPORT_ATHUB_LS |
 988                         AMD_CG_SUPPORT_IH_CG |
 989                         AMD_CG_SUPPORT_VCN_MGCG |
 990                         AMD_CG_SUPPORT_JPEG_MGCG;
 991                 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG |
 992                         AMD_PG_SUPPORT_VCN |
 993                         AMD_PG_SUPPORT_VCN_DPG |
 994                         AMD_PG_SUPPORT_JPEG;
 995                 adev->external_rev_id = adev->rev_id + 0x01;
 996                 break;
 997         case IP_VERSION(10, 3, 7):
 998                 adev->cg_flags =  AMD_CG_SUPPORT_GFX_MGCG |
 999                         AMD_CG_SUPPORT_GFX_MGLS |
1000                         AMD_CG_SUPPORT_GFX_CGCG |
1001                         AMD_CG_SUPPORT_GFX_CGLS |
1002                         AMD_CG_SUPPORT_GFX_3D_CGCG |
1003                         AMD_CG_SUPPORT_GFX_3D_CGLS |
1004                         AMD_CG_SUPPORT_GFX_RLC_LS |
1005                         AMD_CG_SUPPORT_GFX_CP_LS |
1006                         AMD_CG_SUPPORT_GFX_FGCG |
1007                         AMD_CG_SUPPORT_MC_MGCG |
1008                         AMD_CG_SUPPORT_MC_LS |
1009                         AMD_CG_SUPPORT_SDMA_LS |
1010                         AMD_CG_SUPPORT_HDP_MGCG |
1011                         AMD_CG_SUPPORT_HDP_LS |
1012                         AMD_CG_SUPPORT_ATHUB_MGCG |
1013                         AMD_CG_SUPPORT_ATHUB_LS |
1014                         AMD_CG_SUPPORT_IH_CG |
1015                         AMD_CG_SUPPORT_VCN_MGCG |
1016                         AMD_CG_SUPPORT_JPEG_MGCG;
1017                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
1018                         AMD_PG_SUPPORT_VCN_DPG |
1019                         AMD_PG_SUPPORT_JPEG |
1020                         AMD_PG_SUPPORT_GFX_PG;
1021                 adev->external_rev_id = adev->rev_id + 0x01;
1022                 break;
1023         default:
1024                 /* FIXME: not supported yet */
1025                 return -EINVAL;
1026         }
1027
1028         if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK)
1029                 adev->pg_flags &= ~(AMD_PG_SUPPORT_VCN |
1030                                     AMD_PG_SUPPORT_VCN_DPG |
1031                                     AMD_PG_SUPPORT_JPEG);
1032
1033         if (amdgpu_sriov_vf(adev)) {
1034                 amdgpu_virt_init_setting(adev);
1035                 xgpu_nv_mailbox_set_irq_funcs(adev);
1036         }
1037
1038         return 0;
1039 }
1040
1041 static int nv_common_late_init(void *handle)
1042 {
1043         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1044
1045         if (amdgpu_sriov_vf(adev)) {
1046                 xgpu_nv_mailbox_get_irq(adev);
1047                 if (adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) {
1048                         amdgpu_virt_update_sriov_video_codec(adev,
1049                                                              sriov_sc_video_codecs_encode_array,
1050                                                              ARRAY_SIZE(sriov_sc_video_codecs_encode_array),
1051                                                              sriov_sc_video_codecs_decode_array_vcn1,
1052                                                              ARRAY_SIZE(sriov_sc_video_codecs_decode_array_vcn1));
1053                 } else {
1054                         amdgpu_virt_update_sriov_video_codec(adev,
1055                                                              sriov_sc_video_codecs_encode_array,
1056                                                              ARRAY_SIZE(sriov_sc_video_codecs_encode_array),
1057                                                              sriov_sc_video_codecs_decode_array_vcn1,
1058                                                              ARRAY_SIZE(sriov_sc_video_codecs_decode_array_vcn1));
1059                 }
1060         }
1061
1062         return 0;
1063 }
1064
1065 static int nv_common_sw_init(void *handle)
1066 {
1067         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1068
1069         if (amdgpu_sriov_vf(adev))
1070                 xgpu_nv_mailbox_add_irq_id(adev);
1071
1072         return 0;
1073 }
1074
1075 static int nv_common_sw_fini(void *handle)
1076 {
1077         return 0;
1078 }
1079
1080 static int nv_common_hw_init(void *handle)
1081 {
1082         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1083
1084         if (adev->nbio.funcs->apply_lc_spc_mode_wa)
1085                 adev->nbio.funcs->apply_lc_spc_mode_wa(adev);
1086
1087         if (adev->nbio.funcs->apply_l1_link_width_reconfig_wa)
1088                 adev->nbio.funcs->apply_l1_link_width_reconfig_wa(adev);
1089
1090         /* enable pcie gen2/3 link */
1091         nv_pcie_gen3_enable(adev);
1092         /* enable aspm */
1093         nv_program_aspm(adev);
1094         /* setup nbio registers */
1095         adev->nbio.funcs->init_registers(adev);
1096         /* remap HDP registers to a hole in mmio space,
1097          * for the purpose of expose those registers
1098          * to process space
1099          */
1100         if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev))
1101                 adev->nbio.funcs->remap_hdp_registers(adev);
1102         /* enable the doorbell aperture */
1103         nv_enable_doorbell_aperture(adev, true);
1104
1105         return 0;
1106 }
1107
1108 static int nv_common_hw_fini(void *handle)
1109 {
1110         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1111
1112         /* disable the doorbell aperture */
1113         nv_enable_doorbell_aperture(adev, false);
1114
1115         return 0;
1116 }
1117
1118 static int nv_common_suspend(void *handle)
1119 {
1120         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1121
1122         return nv_common_hw_fini(adev);
1123 }
1124
1125 static int nv_common_resume(void *handle)
1126 {
1127         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1128
1129         return nv_common_hw_init(adev);
1130 }
1131
1132 static bool nv_common_is_idle(void *handle)
1133 {
1134         return true;
1135 }
1136
1137 static int nv_common_wait_for_idle(void *handle)
1138 {
1139         return 0;
1140 }
1141
1142 static int nv_common_soft_reset(void *handle)
1143 {
1144         return 0;
1145 }
1146
1147 static int nv_common_set_clockgating_state(void *handle,
1148                                            enum amd_clockgating_state state)
1149 {
1150         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1151
1152         if (amdgpu_sriov_vf(adev))
1153                 return 0;
1154
1155         switch (adev->ip_versions[NBIO_HWIP][0]) {
1156         case IP_VERSION(2, 3, 0):
1157         case IP_VERSION(2, 3, 1):
1158         case IP_VERSION(2, 3, 2):
1159         case IP_VERSION(3, 3, 0):
1160         case IP_VERSION(3, 3, 1):
1161         case IP_VERSION(3, 3, 2):
1162         case IP_VERSION(3, 3, 3):
1163                 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1164                                 state == AMD_CG_STATE_GATE);
1165                 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1166                                 state == AMD_CG_STATE_GATE);
1167                 adev->hdp.funcs->update_clock_gating(adev,
1168                                 state == AMD_CG_STATE_GATE);
1169                 adev->smuio.funcs->update_rom_clock_gating(adev,
1170                                 state == AMD_CG_STATE_GATE);
1171                 break;
1172         default:
1173                 break;
1174         }
1175         return 0;
1176 }
1177
1178 static int nv_common_set_powergating_state(void *handle,
1179                                            enum amd_powergating_state state)
1180 {
1181         /* TODO */
1182         return 0;
1183 }
1184
1185 static void nv_common_get_clockgating_state(void *handle, u64 *flags)
1186 {
1187         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1188
1189         if (amdgpu_sriov_vf(adev))
1190                 *flags = 0;
1191
1192         adev->nbio.funcs->get_clockgating_state(adev, flags);
1193
1194         adev->hdp.funcs->get_clock_gating_state(adev, flags);
1195
1196         adev->smuio.funcs->get_clock_gating_state(adev, flags);
1197
1198         return;
1199 }
1200
1201 static const struct amd_ip_funcs nv_common_ip_funcs = {
1202         .name = "nv_common",
1203         .early_init = nv_common_early_init,
1204         .late_init = nv_common_late_init,
1205         .sw_init = nv_common_sw_init,
1206         .sw_fini = nv_common_sw_fini,
1207         .hw_init = nv_common_hw_init,
1208         .hw_fini = nv_common_hw_fini,
1209         .suspend = nv_common_suspend,
1210         .resume = nv_common_resume,
1211         .is_idle = nv_common_is_idle,
1212         .wait_for_idle = nv_common_wait_for_idle,
1213         .soft_reset = nv_common_soft_reset,
1214         .set_clockgating_state = nv_common_set_clockgating_state,
1215         .set_powergating_state = nv_common_set_powergating_state,
1216         .get_clockgating_state = nv_common_get_clockgating_state,
1217 };