drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "amdgpu.h"
  24 #include "amdgpu_ras.h"
  25 #include "mmhub_v1_7.h"
  26
  27 #include "mmhub/mmhub_1_7_offset.h"
  28 #include "mmhub/mmhub_1_7_sh_mask.h"
  29 #include "vega10_enum.h"
  30
  31 #include "soc15_common.h"
  32 #include "soc15.h"
  33
  34 #define regVM_L2_CNTL3_DEFAULT  0x80100007
  35 #define regVM_L2_CNTL4_DEFAULT  0x000000c1
  36
  37 static u64 mmhub_v1_7_get_fb_location(struct amdgpu_device *adev)
  38 {
  39         u64 base = RREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_BASE);
  40         u64 top = RREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_TOP);
  41
  42         base &= MC_VM_FB_LOCATION_BASE__FB_BASE_MASK;
  43         base <<= 24;
  44
  45         top &= MC_VM_FB_LOCATION_TOP__FB_TOP_MASK;
  46         top <<= 24;
  47
  48         adev->gmc.fb_start = base;
  49         adev->gmc.fb_end = top;
  50
  51         return base;
  52 }
  53
  54 static void mmhub_v1_7_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
  55                                 uint64_t page_table_base)
  56 {
  57         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
  58
  59         WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
  60                         hub->ctx_addr_distance * vmid, lower_32_bits(page_table_base));
  61
  62         WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
  63                         hub->ctx_addr_distance * vmid, upper_32_bits(page_table_base));
  64 }
  65
  66 static void mmhub_v1_7_init_gart_aperture_regs(struct amdgpu_device *adev)
  67 {
  68         uint64_t pt_base;
  69
  70         if (adev->gmc.pdb0_bo)
  71                 pt_base = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo);
  72         else
  73                 pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
  74
  75         mmhub_v1_7_setup_vm_pt_regs(adev, 0, pt_base);
  76
  77         /* If use GART for FB translation, vmid0 page table covers both
  78          * vram and system memory (gart)
  79          */
  80         if (adev->gmc.pdb0_bo) {
  81                 WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
  82                                 (u32)(adev->gmc.fb_start >> 12));
  83                 WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
  84                                 (u32)(adev->gmc.fb_start >> 44));
  85
  86                 WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
  87                                 (u32)(adev->gmc.gart_end >> 12));
  88                 WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
  89                                 (u32)(adev->gmc.gart_end >> 44));
  90
  91         } else {
  92                 WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
  93                                 (u32)(adev->gmc.gart_start >> 12));
  94                 WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
  95                                 (u32)(adev->gmc.gart_start >> 44));
  96
  97                 WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
  98                                 (u32)(adev->gmc.gart_end >> 12));
  99                 WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
 100                                 (u32)(adev->gmc.gart_end >> 44));
 101         }
 102 }
 103
 104 static void mmhub_v1_7_init_system_aperture_regs(struct amdgpu_device *adev)
 105 {
 106         uint64_t value;
 107         uint32_t tmp;
 108
 109         /* Program the AGP BAR */
 110         WREG32_SOC15(MMHUB, 0, regMC_VM_AGP_BASE, 0);
 111         WREG32_SOC15(MMHUB, 0, regMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
 112         WREG32_SOC15(MMHUB, 0, regMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
 113
 114         if (amdgpu_sriov_vf(adev))
 115                 return;
 116
 117         /* Program the system aperture low logical page number. */
 118         WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_LOW_ADDR,
 119                      min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
 120
 121         WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 122                      max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
 123
 124         /* In the case squeezing vram into GART aperture, we don't use
 125          * FB aperture and AGP aperture. Disable them.
 126          */
 127         if (adev->gmc.pdb0_bo) {
 128                 WREG32_SOC15(MMHUB, 0, regMC_VM_AGP_BOT, 0xFFFFFF);
 129                 WREG32_SOC15(MMHUB, 0, regMC_VM_AGP_TOP, 0);
 130                 WREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_TOP, 0);
 131                 WREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_BASE, 0x00FFFFFF);
 132                 WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_LOW_ADDR, 0x3FFFFFFF);
 133                 WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 0);
 134         }
 135
 136         /* Set default page address. */
 137         value = amdgpu_gmc_vram_mc2pa(adev, adev->vram_scratch.gpu_addr);
 138         WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
 139                      (u32)(value >> 12));
 140         WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
 141                      (u32)(value >> 44));
 142
 143         /* Program "protection fault". */
 144         WREG32_SOC15(MMHUB, 0, regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
 145                      (u32)(adev->dummy_page_addr >> 12));
 146         WREG32_SOC15(MMHUB, 0, regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
 147                      (u32)((u64)adev->dummy_page_addr >> 44));
 148
 149         tmp = RREG32_SOC15(MMHUB, 0, regVM_L2_PROTECTION_FAULT_CNTL2);
 150         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2,
 151                             ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
 152         WREG32_SOC15(MMHUB, 0, regVM_L2_PROTECTION_FAULT_CNTL2, tmp);
 153 }
 154
 155 static void mmhub_v1_7_init_tlb_regs(struct amdgpu_device *adev)
 156 {
 157         uint32_t tmp;
 158
 159         /* Setup TLB control */
 160         tmp = RREG32_SOC15(MMHUB, 0, regMC_VM_MX_L1_TLB_CNTL);
 161
 162         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
 163         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
 164         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
 165                             ENABLE_ADVANCED_DRIVER_MODEL, 1);
 166         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
 167                             SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
 168         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
 169         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
 170                             MTYPE, MTYPE_UC);/* XXX for emulation. */
 171         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);
 172
 173         WREG32_SOC15(MMHUB, 0, regMC_VM_MX_L1_TLB_CNTL, tmp);
 174 }
 175
 176 static void mmhub_v1_7_init_cache_regs(struct amdgpu_device *adev)
 177 {
 178         uint32_t tmp;
 179
 180         if (amdgpu_sriov_vf(adev))
 181                 return;
 182
 183         /* Setup L2 cache */
 184         tmp = RREG32_SOC15(MMHUB, 0, regVM_L2_CNTL);
 185         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
 186         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
 187         /* XXX for emulation, Refer to closed source code.*/
 188         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
 189                             0);
 190         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
 191         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
 192         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
 193         WREG32_SOC15(MMHUB, 0, regVM_L2_CNTL, tmp);
 194
 195         tmp = RREG32_SOC15(MMHUB, 0, regVM_L2_CNTL2);
 196         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
 197         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
 198         WREG32_SOC15(MMHUB, 0, regVM_L2_CNTL2, tmp);
 199
 200         tmp = regVM_L2_CNTL3_DEFAULT;
 201         if (adev->gmc.translate_further) {
 202                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);
 203                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
 204                                     L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
 205         } else {
 206                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);
 207                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
 208                                     L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
 209         }
 210         WREG32_SOC15(MMHUB, 0, regVM_L2_CNTL3, tmp);
 211
 212         tmp = regVM_L2_CNTL4_DEFAULT;
 213         if (adev->gmc.xgmi.connected_to_cpu) {
 214                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,
 215                                     VMC_TAP_PDE_REQUEST_PHYSICAL, 1);
 216                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,
 217                                     VMC_TAP_PTE_REQUEST_PHYSICAL, 1);
 218         } else {
 219                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,
 220                                     VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
 221                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,
 222                                     VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
 223         }
 224         WREG32_SOC15(MMHUB, 0, regVM_L2_CNTL4, tmp);
 225 }
 226
 227 static void mmhub_v1_7_enable_system_domain(struct amdgpu_device *adev)
 228 {
 229         uint32_t tmp;
 230
 231         tmp = RREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_CNTL);
 232         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
 233         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH,
 234                         adev->gmc.vmid0_page_table_depth);
 235         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_BLOCK_SIZE,
 236                         adev->gmc.vmid0_page_table_block_size);
 237         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL,
 238                             RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
 239         WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_CNTL, tmp);
 240 }
 241
 242 static void mmhub_v1_7_disable_identity_aperture(struct amdgpu_device *adev)
 243 {
 244         if (amdgpu_sriov_vf(adev))
 245                 return;
 246
 247         WREG32_SOC15(MMHUB, 0, regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
 248                      0XFFFFFFFF);
 249         WREG32_SOC15(MMHUB, 0, regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
 250                      0x0000000F);
 251
 252         WREG32_SOC15(MMHUB, 0,
 253                      regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0);
 254         WREG32_SOC15(MMHUB, 0,
 255                      regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0);
 256
 257         WREG32_SOC15(MMHUB, 0, regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32,
 258                      0);
 259         WREG32_SOC15(MMHUB, 0, regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32,
 260                      0);
 261 }
 262
 263 static void mmhub_v1_7_setup_vmid_config(struct amdgpu_device *adev)
 264 {
 265         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
 266         unsigned num_level, block_size;
 267         uint32_t tmp;
 268         int i;
 269
 270         num_level = adev->vm_manager.num_level;
 271         block_size = adev->vm_manager.block_size;
 272         if (adev->gmc.translate_further)
 273                 num_level -= 1;
 274         else
 275                 block_size -= 9;
 276
 277         for (i = 0; i <= 14; i++) {
 278                 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_CNTL, i);
 279                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
 280                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
 281                                     num_level);
 282                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 283                                     RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 284                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 285                                     DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
 286                                     1);
 287                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 288                                     PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 289                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 290                                     VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 291                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 292                                     READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 293                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 294                                     WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 295                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 296                                     EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 297                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 298                                     PAGE_TABLE_BLOCK_SIZE,
 299                                     block_size);
 300                 /* On Aldebaran, XNACK can be enabled in the SQ per-process.
 301                  * Retry faults need to be enabled for that to work.
 302                  */
 303                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 304                                     RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
 305                                     1);
 306                 WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_CNTL,
 307                                     i * hub->ctx_distance, tmp);
 308                 WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
 309                                     i * hub->ctx_addr_distance, 0);
 310                 WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
 311                                     i * hub->ctx_addr_distance, 0);
 312                 WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
 313                                     i * hub->ctx_addr_distance,
 314                                     lower_32_bits(adev->vm_manager.max_pfn - 1));
 315                 WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
 316                                     i * hub->ctx_addr_distance,
 317                                     upper_32_bits(adev->vm_manager.max_pfn - 1));
 318         }
 319 }
 320
 321 static void mmhub_v1_7_program_invalidation(struct amdgpu_device *adev)
 322 {
 323         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
 324         unsigned i;
 325
 326         for (i = 0; i < 18; ++i) {
 327                 WREG32_SOC15_OFFSET(MMHUB, 0, regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
 328                                     i * hub->eng_addr_distance, 0xffffffff);
 329                 WREG32_SOC15_OFFSET(MMHUB, 0, regVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
 330                                     i * hub->eng_addr_distance, 0x1f);
 331         }
 332 }
 333
 334 static int mmhub_v1_7_gart_enable(struct amdgpu_device *adev)
 335 {
 336         /* GART Enable. */
 337         mmhub_v1_7_init_gart_aperture_regs(adev);
 338         mmhub_v1_7_init_system_aperture_regs(adev);
 339         mmhub_v1_7_init_tlb_regs(adev);
 340         mmhub_v1_7_init_cache_regs(adev);
 341
 342         mmhub_v1_7_enable_system_domain(adev);
 343         mmhub_v1_7_disable_identity_aperture(adev);
 344         mmhub_v1_7_setup_vmid_config(adev);
 345         mmhub_v1_7_program_invalidation(adev);
 346
 347         return 0;
 348 }
 349
 350 static void mmhub_v1_7_gart_disable(struct amdgpu_device *adev)
 351 {
 352         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
 353         u32 tmp;
 354         u32 i;
 355
 356         /* Disable all tables */
 357         for (i = 0; i < 16; i++)
 358                 WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT0_CNTL,
 359                                     i * hub->ctx_distance, 0);
 360
 361         /* Setup TLB control */
 362         tmp = RREG32_SOC15(MMHUB, 0, regMC_VM_MX_L1_TLB_CNTL);
 363         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
 364         tmp = REG_SET_FIELD(tmp,
 365                                 MC_VM_MX_L1_TLB_CNTL,
 366                                 ENABLE_ADVANCED_DRIVER_MODEL,
 367                                 0);
 368         WREG32_SOC15(MMHUB, 0, regMC_VM_MX_L1_TLB_CNTL, tmp);
 369
 370         if (!amdgpu_sriov_vf(adev)) {
 371                 /* Setup L2 cache */
 372                 tmp = RREG32_SOC15(MMHUB, 0, regVM_L2_CNTL);
 373                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
 374                 WREG32_SOC15(MMHUB, 0, regVM_L2_CNTL, tmp);
 375                 WREG32_SOC15(MMHUB, 0, regVM_L2_CNTL3, 0);
 376         }
 377 }
 378
 379 /**
 380  * mmhub_v1_7_set_fault_enable_default - update GART/VM fault handling
 381  *
 382  * @adev: amdgpu_device pointer
 383  * @value: true redirects VM faults to the default page
 384  */
 385 static void mmhub_v1_7_set_fault_enable_default(struct amdgpu_device *adev, bool value)
 386 {
 387         u32 tmp;
 388
 389         if (amdgpu_sriov_vf(adev))
 390                 return;
 391
 392         tmp = RREG32_SOC15(MMHUB, 0, regVM_L2_PROTECTION_FAULT_CNTL);
 393         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 394                         RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 395         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 396                         PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 397         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 398                         PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 399         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 400                         PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 401         tmp = REG_SET_FIELD(tmp,
 402                         VM_L2_PROTECTION_FAULT_CNTL,
 403                         TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
 404                         value);
 405         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 406                         NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 407         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 408                         DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 409         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 410                         VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 411         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 412                         READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 413         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 414                         WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 415         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 416                         EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 417         if (!value) {
 418                 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 419                                 CRASH_ON_NO_RETRY_FAULT, 1);
 420                 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 421                                 CRASH_ON_RETRY_FAULT, 1);
 422     }
 423
 424         WREG32_SOC15(MMHUB, 0, regVM_L2_PROTECTION_FAULT_CNTL, tmp);
 425 }
 426
 427 static void mmhub_v1_7_init(struct amdgpu_device *adev)
 428 {
 429         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
 430
 431         hub->ctx0_ptb_addr_lo32 =
 432                 SOC15_REG_OFFSET(MMHUB, 0,
 433                                  regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
 434         hub->ctx0_ptb_addr_hi32 =
 435                 SOC15_REG_OFFSET(MMHUB, 0,
 436                                  regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
 437         hub->vm_inv_eng0_req =
 438                 SOC15_REG_OFFSET(MMHUB, 0, regVM_INVALIDATE_ENG0_REQ);
 439         hub->vm_inv_eng0_ack =
 440                 SOC15_REG_OFFSET(MMHUB, 0, regVM_INVALIDATE_ENG0_ACK);
 441         hub->vm_context0_cntl =
 442                 SOC15_REG_OFFSET(MMHUB, 0, regVM_CONTEXT0_CNTL);
 443         hub->vm_l2_pro_fault_status =
 444                 SOC15_REG_OFFSET(MMHUB, 0, regVM_L2_PROTECTION_FAULT_STATUS);
 445         hub->vm_l2_pro_fault_cntl =
 446                 SOC15_REG_OFFSET(MMHUB, 0, regVM_L2_PROTECTION_FAULT_CNTL);
 447
 448         hub->ctx_distance = regVM_CONTEXT1_CNTL - regVM_CONTEXT0_CNTL;
 449         hub->ctx_addr_distance = regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 -
 450                 regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
 451         hub->eng_distance = regVM_INVALIDATE_ENG1_REQ - regVM_INVALIDATE_ENG0_REQ;
 452         hub->eng_addr_distance = regVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -
 453                 regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;
 454
 455 }
 456
 457 static void mmhub_v1_7_update_medium_grain_clock_gating(struct amdgpu_device *adev,
 458                                                         bool enable)
 459 {
 460         uint32_t def, data, def1, data1, def2 = 0, data2 = 0;
 461
 462         def  = data  = RREG32_SOC15(MMHUB, 0, regATC_L2_MISC_CG);
 463
 464         def1 = data1 = RREG32_SOC15(MMHUB, 0, regDAGB0_CNTL_MISC2);
 465         def2 = data2 = RREG32_SOC15(MMHUB, 0, regDAGB1_CNTL_MISC2);
 466
 467         if (enable) {
 468                 data |= ATC_L2_MISC_CG__ENABLE_MASK;
 469
 470                 data1 &= ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
 471                            DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
 472                            DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
 473                            DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
 474                            DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
 475                            DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
 476
 477                 data2 &= ~(DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
 478                            DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
 479                            DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
 480                            DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
 481                            DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
 482                            DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
 483         } else {
 484                 data &= ~ATC_L2_MISC_CG__ENABLE_MASK;
 485
 486                 data1 |= (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
 487                           DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
 488                           DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
 489                           DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
 490                           DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
 491                           DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
 492
 493                 data2 |= (DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
 494                           DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
 495                           DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
 496                           DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
 497                           DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
 498                           DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
 499         }
 500
 501         if (def != data)
 502                 WREG32_SOC15(MMHUB, 0, regATC_L2_MISC_CG, data);
 503
 504         if (def1 != data1)
 505                 WREG32_SOC15(MMHUB, 0, regDAGB0_CNTL_MISC2, data1);
 506
 507         if (def2 != data2)
 508                 WREG32_SOC15(MMHUB, 0, regDAGB1_CNTL_MISC2, data2);
 509 }
 510
 511 static void mmhub_v1_7_update_medium_grain_light_sleep(struct amdgpu_device *adev,
 512                                                        bool enable)
 513 {
 514         uint32_t def, data;
 515
 516         def = data = RREG32_SOC15(MMHUB, 0, regATC_L2_MISC_CG);
 517
 518         if (enable)
 519                 data |= ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
 520         else
 521                 data &= ~ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
 522
 523         if (def != data)
 524                 WREG32_SOC15(MMHUB, 0, regATC_L2_MISC_CG, data);
 525 }
 526
 527 static int mmhub_v1_7_set_clockgating(struct amdgpu_device *adev,
 528                                enum amd_clockgating_state state)
 529 {
 530         if (amdgpu_sriov_vf(adev))
 531                 return 0;
 532
 533         /* Change state only if MCCG support is enabled through driver */
 534         if (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)
 535                 mmhub_v1_7_update_medium_grain_clock_gating(adev,
 536                                 state == AMD_CG_STATE_GATE);
 537
 538         /* Change state only if LS support is enabled through driver */
 539         if (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)
 540                 mmhub_v1_7_update_medium_grain_light_sleep(adev,
 541                                 state == AMD_CG_STATE_GATE);
 542
 543         return 0;
 544 }
 545
 546 static void mmhub_v1_7_get_clockgating(struct amdgpu_device *adev, u32 *flags)
 547 {
 548         int data, data1;
 549
 550         if (amdgpu_sriov_vf(adev))
 551                 *flags = 0;
 552
 553         data = RREG32_SOC15(MMHUB, 0, regATC_L2_MISC_CG);
 554
 555         data1 = RREG32_SOC15(MMHUB, 0, regDAGB0_CNTL_MISC2);
 556
 557         /* AMD_CG_SUPPORT_MC_MGCG */
 558         if ((data & ATC_L2_MISC_CG__ENABLE_MASK) &&
 559             !(data1 & (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
 560                        DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
 561                        DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
 562                        DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
 563                        DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
 564                        DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK)))
 565                 *flags |= AMD_CG_SUPPORT_MC_MGCG;
 566
 567         /* AMD_CG_SUPPORT_MC_LS */
 568         if (data & ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK)
 569                 *flags |= AMD_CG_SUPPORT_MC_LS;
 570 }
 571
 572 static const struct soc15_ras_field_entry mmhub_v1_7_ras_fields[] = {
 573         /* MMHUB Range 0 */
 574         { "MMEA0_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT),
 575         SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
 576         SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
 577         },
 578         { "MMEA0_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT),
 579         SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
 580         SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
 581         },
 582         { "MMEA0_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT),
 583         SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
 584         SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
 585         },
 586         { "MMEA0_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT),
 587         SOC15_REG_FIELD(MMEA0_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
 588         SOC15_REG_FIELD(MMEA0_EDC_CNT, RRET_TAGMEM_DED_COUNT),
 589         },
 590         { "MMEA0_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT),
 591         SOC15_REG_FIELD(MMEA0_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
 592         SOC15_REG_FIELD(MMEA0_EDC_CNT, WRET_TAGMEM_DED_COUNT),
 593         },
 594         { "MMEA0_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT),
 595         SOC15_REG_FIELD(MMEA0_EDC_CNT, IOWR_DATAMEM_SEC_COUNT),
 596         SOC15_REG_FIELD(MMEA0_EDC_CNT, IOWR_DATAMEM_DED_COUNT),
 597         },
 598         { "MMEA0_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT),
 599         SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
 600         0, 0,
 601         },
 602         { "MMEA0_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT),
 603         SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
 604         0, 0,
 605         },
 606         { "MMEA0_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT),
 607         SOC15_REG_FIELD(MMEA0_EDC_CNT, IORD_CMDMEM_SED_COUNT),
 608         0, 0,
 609         },
 610         { "MMEA0_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT),
 611         SOC15_REG_FIELD(MMEA0_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
 612         0, 0,
 613         },
 614         { "MMEA0_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2),
 615         SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
 616         SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
 617         },
 618         { "MMEA0_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2),
 619         SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
 620         SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
 621         },
 622         { "MMEA0_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2),
 623         SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
 624         SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
 625         },
 626         { "MMEA0_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2),
 627         SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
 628         0, 0,
 629         },
 630         { "MMEA0_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2),
 631         SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
 632         0, 0,
 633         },
 634         { "MMEA0_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2),
 635         SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D0MEM_SED_COUNT),
 636         SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D0MEM_DED_COUNT),
 637         },
 638         { "MMEA0_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2),
 639         SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D1MEM_SED_COUNT),
 640         SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D1MEM_DED_COUNT),
 641         },
 642         { "MMEA0_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2),
 643         SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D2MEM_SED_COUNT),
 644         SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D2MEM_DED_COUNT),
 645         },
 646         { "MMEA0_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2),
 647         SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D3MEM_SED_COUNT),
 648         SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D3MEM_DED_COUNT),
 649         },
 650         { "MMEA0_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT3),
 651         0, 0,
 652         SOC15_REG_FIELD(MMEA0_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
 653         },
 654         { "MMEA0_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT3),
 655         0, 0,
 656         SOC15_REG_FIELD(MMEA0_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
 657         },
 658         { "MMEA0_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT3),
 659         0, 0,
 660         SOC15_REG_FIELD(MMEA0_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
 661         },
 662         { "MMEA0_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT3),
 663         0, 0,
 664         SOC15_REG_FIELD(MMEA0_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
 665         },
 666         { "MMEA0_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT3),
 667         0, 0,
 668         SOC15_REG_FIELD(MMEA0_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
 669         },
 670         { "MMEA0_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT3),
 671         0, 0,
 672         SOC15_REG_FIELD(MMEA0_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
 673         },
 674
 675         /* MMHUB Range 1 */
 676         { "MMEA1_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT),
 677         SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
 678         SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
 679         },
 680         { "MMEA1_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT),
 681         SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
 682         SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
 683         },
 684         { "MMEA1_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT),
 685         SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
 686         SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
 687         },
 688         { "MMEA1_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT),
 689         SOC15_REG_FIELD(MMEA1_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
 690         SOC15_REG_FIELD(MMEA1_EDC_CNT, RRET_TAGMEM_DED_COUNT),
 691         },
 692         { "MMEA1_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT),
 693         SOC15_REG_FIELD(MMEA1_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
 694         SOC15_REG_FIELD(MMEA1_EDC_CNT, WRET_TAGMEM_DED_COUNT),
 695         },
 696         { "MMEA1_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT),
 697         SOC15_REG_FIELD(MMEA1_EDC_CNT, IOWR_DATAMEM_SEC_COUNT),
 698         SOC15_REG_FIELD(MMEA1_EDC_CNT, IOWR_DATAMEM_DED_COUNT),
 699         },
 700         { "MMEA1_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT),
 701         SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
 702         0, 0,
 703         },
 704         { "MMEA1_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT),
 705         SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
 706         0, 0,
 707         },
 708         { "MMEA1_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT),
 709         SOC15_REG_FIELD(MMEA1_EDC_CNT, IORD_CMDMEM_SED_COUNT),
 710         0, 0,
 711         },
 712         { "MMEA1_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT),
 713         SOC15_REG_FIELD(MMEA1_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
 714         0, 0,
 715         },
 716         { "MMEA1_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2),
 717         SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
 718         SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
 719         },
 720         { "MMEA1_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2),
 721         SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
 722         SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
 723         },
 724         { "MMEA1_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2),
 725         SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
 726         SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
 727         },
 728         { "MMEA1_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2),
 729         SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
 730         0, 0,
 731         },
 732         { "MMEA1_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2),
 733         SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
 734         0, 0,
 735         },
 736         { "MMEA1_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2),
 737         SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D0MEM_SED_COUNT),
 738         SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D0MEM_DED_COUNT),
 739         },
 740         { "MMEA1_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2),
 741         SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D1MEM_SED_COUNT),
 742         SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D1MEM_DED_COUNT),
 743         },
 744         { "MMEA1_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2),
 745         SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D2MEM_SED_COUNT),
 746         SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D2MEM_DED_COUNT),
 747         },
 748         { "MMEA1_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2),
 749         SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D3MEM_SED_COUNT),
 750         SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D3MEM_DED_COUNT),
 751         },
 752         { "MMEA1_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT3),
 753         0, 0,
 754         SOC15_REG_FIELD(MMEA1_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
 755         },
 756         { "MMEA1_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT3),
 757         0, 0,
 758         SOC15_REG_FIELD(MMEA1_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
 759         },
 760         { "MMEA1_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT3),
 761         0, 0,
 762         SOC15_REG_FIELD(MMEA1_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
 763         },
 764         { "MMEA1_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT3),
 765         0, 0,
 766         SOC15_REG_FIELD(MMEA1_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
 767         },
 768         { "MMEA1_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT3),
 769         0, 0,
 770         SOC15_REG_FIELD(MMEA1_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
 771         },
 772         { "MMEA1_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT3),
 773         0, 0,
 774         SOC15_REG_FIELD(MMEA1_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
 775         },
 776
 777         /* MMHAB Range 2*/
 778         { "MMEA2_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT),
 779         SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
 780         SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
 781         },
 782         { "MMEA2_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT),
 783         SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
 784         SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
 785         },
 786         { "MMEA2_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT),
 787         SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
 788         SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
 789         },
 790         { "MMEA2_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT),
 791         SOC15_REG_FIELD(MMEA2_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
 792         SOC15_REG_FIELD(MMEA2_EDC_CNT, RRET_TAGMEM_DED_COUNT),
 793         },
 794         { "MMEA2_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT),
 795         SOC15_REG_FIELD(MMEA2_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
 796         SOC15_REG_FIELD(MMEA2_EDC_CNT, WRET_TAGMEM_DED_COUNT),
 797         },
 798         { "MMEA2_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT),
 799         SOC15_REG_FIELD(MMEA2_EDC_CNT, IOWR_DATAMEM_SEC_COUNT),
 800         SOC15_REG_FIELD(MMEA2_EDC_CNT, IOWR_DATAMEM_DED_COUNT),
 801         },
 802         { "MMEA2_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT),
 803         SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
 804         0, 0,
 805         },
 806         { "MMEA2_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT),
 807         SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
 808         0, 0,
 809         },
 810         { "MMEA2_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT),
 811         SOC15_REG_FIELD(MMEA2_EDC_CNT, IORD_CMDMEM_SED_COUNT),
 812         0, 0,
 813         },
 814         { "MMEA2_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT),
 815         SOC15_REG_FIELD(MMEA2_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
 816         0, 0,
 817         },
 818         { "MMEA2_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2),
 819         SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
 820         SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
 821         },
 822         { "MMEA2_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2),
 823         SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
 824         SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
 825         },
 826         { "MMEA2_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2),
 827         SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
 828         SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
 829         },
 830         { "MMEA2_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2),
 831         SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
 832         0, 0,
 833         },
 834         { "MMEA2_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2),
 835         SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
 836         0, 0,
 837         },
 838         { "MMEA2_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2),
 839         SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D0MEM_SED_COUNT),
 840         SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D0MEM_DED_COUNT),
 841         },
 842         { "MMEA2_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2),
 843         SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D1MEM_SED_COUNT),
 844         SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D1MEM_DED_COUNT),
 845         },
 846         { "MMEA2_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2),
 847         SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D2MEM_SED_COUNT),
 848         SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D2MEM_DED_COUNT),
 849         },
 850         { "MMEA2_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2),
 851         SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D3MEM_SED_COUNT),
 852         SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D3MEM_DED_COUNT),
 853         },
 854         { "MMEA2_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT3),
 855         0, 0,
 856         SOC15_REG_FIELD(MMEA2_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
 857         },
 858         { "MMEA2_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT3),
 859         0, 0,
 860         SOC15_REG_FIELD(MMEA2_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
 861         },
 862         { "MMEA2_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT3),
 863         0, 0,
 864         SOC15_REG_FIELD(MMEA2_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
 865         },
 866         { "MMEA2_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT3),
 867         0, 0,
 868         SOC15_REG_FIELD(MMEA2_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
 869         },
 870         { "MMEA2_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT3),
 871         0, 0,
 872         SOC15_REG_FIELD(MMEA2_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
 873         },
 874         { "MMEA2_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT3),
 875         0, 0,
 876         SOC15_REG_FIELD(MMEA2_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
 877         },
 878
 879         /* MMHUB Rang 3 */
 880         { "MMEA3_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT),
 881         SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
 882         SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
 883         },
 884         { "MMEA3_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT),
 885         SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
 886         SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
 887         },
 888         { "MMEA3_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT),
 889         SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
 890         SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
 891         },
 892         { "MMEA3_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT),
 893         SOC15_REG_FIELD(MMEA3_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
 894         SOC15_REG_FIELD(MMEA3_EDC_CNT, RRET_TAGMEM_DED_COUNT),
 895         },
 896         { "MMEA3_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT),
 897         SOC15_REG_FIELD(MMEA3_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
 898         SOC15_REG_FIELD(MMEA3_EDC_CNT, WRET_TAGMEM_DED_COUNT),
 899         },
 900         { "MMEA3_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT),
 901         SOC15_REG_FIELD(MMEA3_EDC_CNT, IOWR_DATAMEM_SEC_COUNT),
 902         SOC15_REG_FIELD(MMEA3_EDC_CNT, IOWR_DATAMEM_DED_COUNT),
 903         },
 904         { "MMEA3_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT),
 905         SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
 906         0, 0,
 907         },
 908         { "MMEA3_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT),
 909         SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
 910         0, 0,
 911         },
 912         { "MMEA3_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT),
 913         SOC15_REG_FIELD(MMEA3_EDC_CNT, IORD_CMDMEM_SED_COUNT),
 914         0, 0,
 915         },
 916         { "MMEA3_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT),
 917         SOC15_REG_FIELD(MMEA3_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
 918         0, 0,
 919         },
 920         { "MMEA3_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2),
 921         SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
 922         SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
 923         },
 924         { "MMEA3_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2),
 925         SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
 926         SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
 927         },
 928         { "MMEA3_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2),
 929         SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
 930         SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
 931         },
 932         { "MMEA3_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2),
 933         SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
 934         0, 0,
 935         },
 936         { "MMEA3_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2),
 937         SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
 938         0, 0,
 939         },
 940         { "MMEA3_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2),
 941         SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D0MEM_SED_COUNT),
 942         SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D0MEM_DED_COUNT),
 943         },
 944         { "MMEA3_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2),
 945         SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D1MEM_SED_COUNT),
 946         SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D1MEM_DED_COUNT),
 947         },
 948         { "MMEA3_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2),
 949         SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D2MEM_SED_COUNT),
 950         SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D2MEM_DED_COUNT),
 951         },
 952         { "MMEA3_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2),
 953         SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D3MEM_SED_COUNT),
 954         SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D3MEM_DED_COUNT),
 955         },
 956         { "MMEA3_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT3),
 957         0, 0,
 958         SOC15_REG_FIELD(MMEA3_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
 959         },
 960         { "MMEA3_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT3),
 961         0, 0,
 962         SOC15_REG_FIELD(MMEA3_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
 963         },
 964         { "MMEA3_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT3),
 965         0, 0,
 966         SOC15_REG_FIELD(MMEA3_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
 967         },
 968         { "MMEA3_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT3),
 969         0, 0,
 970         SOC15_REG_FIELD(MMEA3_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
 971         },
 972         { "MMEA3_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT3),
 973         0, 0,
 974         SOC15_REG_FIELD(MMEA3_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
 975         },
 976         { "MMEA3_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT3),
 977         0, 0,
 978         SOC15_REG_FIELD(MMEA3_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
 979         },
 980
 981         /* MMHUB Range 4 */
 982         { "MMEA4_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT),
 983         SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
 984         SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
 985         },
 986         { "MMEA4_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT),
 987         SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
 988         SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
 989         },
 990         { "MMEA4_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT),
 991         SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
 992         SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
 993         },
 994         { "MMEA4_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT),
 995         SOC15_REG_FIELD(MMEA4_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
 996         SOC15_REG_FIELD(MMEA4_EDC_CNT, RRET_TAGMEM_DED_COUNT),
 997         },
 998         { "MMEA4_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT),
 999         SOC15_REG_FIELD(MMEA4_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
1000         SOC15_REG_FIELD(MMEA4_EDC_CNT, WRET_TAGMEM_DED_COUNT),
1001         },
1002         { "MMEA4_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT),
1003         SOC15_REG_FIELD(MMEA4_EDC_CNT, IOWR_DATAMEM_SEC_COUNT),
1004         SOC15_REG_FIELD(MMEA4_EDC_CNT, IOWR_DATAMEM_DED_COUNT),
1005         },
1006         { "MMEA4_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT),
1007         SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
1008         0, 0,
1009         },
1010         { "MMEA4_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT),
1011         SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
1012         0, 0,
1013         },
1014         { "MMEA4_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT),
1015         SOC15_REG_FIELD(MMEA4_EDC_CNT, IORD_CMDMEM_SED_COUNT),
1016         0, 0,
1017         },
1018         { "MMEA4_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT),
1019         SOC15_REG_FIELD(MMEA4_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
1020         0, 0,
1021         },
1022         { "MMEA4_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2),
1023         SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
1024         SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
1025         },
1026         { "MMEA4_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2),
1027         SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
1028         SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
1029         },
1030         { "MMEA4_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2),
1031         SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
1032         SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
1033         },
1034         { "MMEA4_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2),
1035         SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
1036         0, 0,
1037         },
1038         { "MMEA4_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2),
1039         SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
1040         0, 0,
1041         },
1042         { "MMEA4_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2),
1043         SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D0MEM_SED_COUNT),
1044         SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D0MEM_DED_COUNT),
1045         },
1046         { "MMEA4_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2),
1047         SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D1MEM_SED_COUNT),
1048         SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D1MEM_DED_COUNT),
1049         },
1050         { "MMEA4_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2),
1051         SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D2MEM_SED_COUNT),
1052         SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D2MEM_DED_COUNT),
1053         },
1054         { "MMEA4_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2),
1055         SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D3MEM_SED_COUNT),
1056         SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D3MEM_DED_COUNT),
1057         },
1058         { "MMEA4_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT3),
1059         0, 0,
1060         SOC15_REG_FIELD(MMEA4_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
1061         },
1062         { "MMEA4_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT3),
1063         0, 0,
1064         SOC15_REG_FIELD(MMEA4_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
1065         },
1066         { "MMEA4_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT3),
1067         0, 0,
1068         SOC15_REG_FIELD(MMEA4_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
1069         },
1070         { "MMEA4_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT3),
1071         0, 0,
1072         SOC15_REG_FIELD(MMEA4_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
1073         },
1074         { "MMEA4_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT3),
1075         0, 0,
1076         SOC15_REG_FIELD(MMEA4_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
1077         },
1078         { "MMEA4_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT3),
1079         0, 0,
1080         SOC15_REG_FIELD(MMEA4_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
1081         },
1082
1083         /* MMHUAB Range 5 */
1084         { "MMEA5_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT),
1085         SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
1086         SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
1087         },
1088         { "MMEA5_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT),
1089         SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
1090         SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
1091         },
1092         { "MMEA5_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT),
1093         SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
1094         SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
1095         },
1096         { "MMEA5_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT),
1097         SOC15_REG_FIELD(MMEA5_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
1098         SOC15_REG_FIELD(MMEA5_EDC_CNT, RRET_TAGMEM_DED_COUNT),
1099         },
1100         { "MMEA5_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT),
1101         SOC15_REG_FIELD(MMEA5_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
1102         SOC15_REG_FIELD(MMEA5_EDC_CNT, WRET_TAGMEM_DED_COUNT),
1103         },
1104         { "MMEA5_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT),
1105         SOC15_REG_FIELD(MMEA5_EDC_CNT, IOWR_DATAMEM_SEC_COUNT),
1106         SOC15_REG_FIELD(MMEA5_EDC_CNT, IOWR_DATAMEM_DED_COUNT),
1107         },
1108         { "MMEA5_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT),
1109         SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
1110         0, 0,
1111         },
1112         { "MMEA5_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT),
1113         SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
1114         0, 0,
1115         },
1116         { "MMEA5_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT),
1117         SOC15_REG_FIELD(MMEA5_EDC_CNT, IORD_CMDMEM_SED_COUNT),
1118         0, 0,
1119         },
1120         { "MMEA5_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT),
1121         SOC15_REG_FIELD(MMEA5_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
1122         0, 0,
1123         },
1124         { "MMEA5_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2),
1125         SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
1126         SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
1127         },
1128         { "MMEA5_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2),
1129         SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
1130         SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
1131         },
1132         { "MMEA5_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2),
1133         SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
1134         SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
1135         },
1136         { "MMEA5_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2),
1137         SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
1138         0, 0,
1139         },
1140         { "MMEA5_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2),
1141         SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
1142         0, 0,
1143         },
1144         { "MMEA5_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2),
1145         SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D0MEM_SED_COUNT),
1146         SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D0MEM_DED_COUNT),
1147         },
1148         { "MMEA5_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2),
1149         SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D1MEM_SED_COUNT),
1150         SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D1MEM_DED_COUNT),
1151         },
1152         { "MMEA5_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2),
1153         SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D2MEM_SED_COUNT),
1154         SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D2MEM_DED_COUNT),
1155         },
1156         { "MMEA5_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2),
1157         SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D3MEM_SED_COUNT),
1158         SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D3MEM_DED_COUNT),
1159         },
1160         { "MMEA5_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT3),
1161         0, 0,
1162         SOC15_REG_FIELD(MMEA5_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
1163         },
1164         { "MMEA5_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT3),
1165         0, 0,
1166         SOC15_REG_FIELD(MMEA5_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
1167         },
1168         { "MMEA5_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT3),
1169         0, 0,
1170         SOC15_REG_FIELD(MMEA5_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
1171         },
1172         { "MMEA5_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT3),
1173         0, 0,
1174         SOC15_REG_FIELD(MMEA5_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
1175         },
1176         { "MMEA5_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT3),
1177         0, 0,
1178         SOC15_REG_FIELD(MMEA5_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
1179         },
1180         { "MMEA5_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT3),
1181         0, 0,
1182         SOC15_REG_FIELD(MMEA5_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
1183         },
1184 };
1185
1186 static const struct soc15_reg_entry mmhub_v1_7_edc_cnt_regs[] = {
1187         { SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT), 0, 0, 0 },
1188         { SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2), 0, 0, 0 },
1189         { SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT3), 0, 0, 0 },
1190         { SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT), 0, 0, 0 },
1191         { SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2), 0, 0, 0 },
1192         { SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT3), 0, 0, 0 },
1193         { SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT), 0, 0, 0 },
1194         { SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2), 0, 0, 0 },
1195         { SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT3), 0, 0, 0 },
1196         { SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT), 0, 0, 0 },
1197         { SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2), 0, 0, 0 },
1198         { SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT3), 0, 0, 0 },
1199         { SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT), 0, 0, 0 },
1200         { SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2), 0, 0, 0 },
1201         { SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT3), 0, 0, 0 },
1202         { SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT), 0, 0, 0 },
1203         { SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2), 0, 0, 0 },
1204         { SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT3), 0, 0, 0 },
1205 };
1206
1207 static int mmhub_v1_7_get_ras_error_count(struct amdgpu_device *adev,
1208                                           const struct soc15_reg_entry *reg,
1209                                           uint32_t value,
1210                                           uint32_t *sec_count,
1211                                           uint32_t *ded_count)
1212 {
1213         uint32_t i;
1214         uint32_t sec_cnt, ded_cnt;
1215
1216         for (i = 0; i < ARRAY_SIZE(mmhub_v1_7_ras_fields); i++) {
1217                 if(mmhub_v1_7_ras_fields[i].reg_offset != reg->reg_offset)
1218                         continue;
1219
1220                 sec_cnt = (value &
1221                                 mmhub_v1_7_ras_fields[i].sec_count_mask) >>
1222                                 mmhub_v1_7_ras_fields[i].sec_count_shift;
1223                 if (sec_cnt) {
1224                         dev_info(adev->dev, "MMHUB SubBlock %s, SEC %d\n",
1225                                  mmhub_v1_7_ras_fields[i].name,
1226                                  sec_cnt);
1227                         *sec_count += sec_cnt;
1228                 }
1229
1230                 ded_cnt = (value &
1231                                 mmhub_v1_7_ras_fields[i].ded_count_mask) >>
1232                                 mmhub_v1_7_ras_fields[i].ded_count_shift;
1233                 if (ded_cnt) {
1234                         dev_info(adev->dev, "MMHUB SubBlock %s, DED %d\n",
1235                                  mmhub_v1_7_ras_fields[i].name,
1236                                  ded_cnt);
1237                         *ded_count += ded_cnt;
1238                 }
1239         }
1240
1241         return 0;
1242 }
1243
1244 static void mmhub_v1_7_query_ras_error_count(struct amdgpu_device *adev,
1245                                              void *ras_error_status)
1246 {
1247         struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
1248         uint32_t sec_count = 0, ded_count = 0;
1249         uint32_t i;
1250         uint32_t reg_value;
1251
1252         err_data->ue_count = 0;
1253         err_data->ce_count = 0;
1254
1255         for (i = 0; i < ARRAY_SIZE(mmhub_v1_7_edc_cnt_regs); i++) {
1256                 reg_value =
1257                         RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_7_edc_cnt_regs[i]));
1258                 if (reg_value)
1259                         mmhub_v1_7_get_ras_error_count(adev, &mmhub_v1_7_edc_cnt_regs[i],
1260                                 reg_value, &sec_count, &ded_count);
1261         }
1262
1263         err_data->ce_count += sec_count;
1264         err_data->ue_count += ded_count;
1265 }
1266
1267 static void mmhub_v1_7_reset_ras_error_count(struct amdgpu_device *adev)
1268 {
1269         uint32_t i;
1270
1271         /* write 0 to reset the edc counters */
1272         if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__MMHUB)) {
1273                 for (i = 0; i < ARRAY_SIZE(mmhub_v1_7_edc_cnt_regs); i++)
1274                         WREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_7_edc_cnt_regs[i]), 0);
1275         }
1276 }
1277
1278 static const struct soc15_reg_entry mmhub_v1_7_ea_err_status_regs[] = {
1279         { SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_ERR_STATUS), 0, 0, 0 },
1280         { SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_ERR_STATUS), 0, 0, 0 },
1281         { SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_ERR_STATUS), 0, 0, 0 },
1282         { SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_ERR_STATUS), 0, 0, 0 },
1283         { SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_ERR_STATUS), 0, 0, 0 },
1284         { SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_ERR_STATUS), 0, 0, 0 },
1285 };
1286
1287 static void mmhub_v1_7_query_ras_error_status(struct amdgpu_device *adev)
1288 {
1289         int i;
1290         uint32_t reg_value;
1291
1292         if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__MMHUB))
1293                 return;
1294
1295         for (i = 0; i < ARRAY_SIZE(mmhub_v1_7_ea_err_status_regs); i++) {
1296                 reg_value =
1297                         RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_7_ea_err_status_regs[i]));
1298                 if (REG_GET_FIELD(reg_value, MMEA0_ERR_STATUS, SDP_RDRSP_STATUS) ||
1299                     REG_GET_FIELD(reg_value, MMEA0_ERR_STATUS, SDP_WRRSP_STATUS) ||
1300                     REG_GET_FIELD(reg_value, MMEA0_ERR_STATUS, SDP_RDRSP_DATAPARITY_ERROR)) {
1301                         dev_warn(adev->dev, "MMHUB EA err detected at instance: %d, status: 0x%x!\n",
1302                                         i, reg_value);
1303                 }
1304         }
1305 }
1306
1307 static void mmhub_v1_7_reset_ras_error_status(struct amdgpu_device *adev)
1308 {
1309         int i;
1310         uint32_t reg_value;
1311
1312         if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__MMHUB))
1313                 return;
1314
1315         for (i = 0; i < ARRAY_SIZE(mmhub_v1_7_ea_err_status_regs); i++) {
1316                 reg_value = RREG32(SOC15_REG_ENTRY_OFFSET(
1317                         mmhub_v1_7_ea_err_status_regs[i]));
1318                 reg_value = REG_SET_FIELD(reg_value, MMEA0_ERR_STATUS,
1319                                           CLEAR_ERROR_STATUS, 0x01);
1320                 WREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_7_ea_err_status_regs[i]),
1321                        reg_value);
1322         }
1323 }
1324
1325 const struct amdgpu_mmhub_ras_funcs mmhub_v1_7_ras_funcs = {
1326         .ras_late_init = amdgpu_mmhub_ras_late_init,
1327         .ras_fini = amdgpu_mmhub_ras_fini,
1328         .query_ras_error_count = mmhub_v1_7_query_ras_error_count,
1329         .reset_ras_error_count = mmhub_v1_7_reset_ras_error_count,
1330         .query_ras_error_status = mmhub_v1_7_query_ras_error_status,
1331         .reset_ras_error_status = mmhub_v1_7_reset_ras_error_status,
1332 };
1333
1334 const struct amdgpu_mmhub_funcs mmhub_v1_7_funcs = {
1335         .get_fb_location = mmhub_v1_7_get_fb_location,
1336         .init = mmhub_v1_7_init,
1337         .gart_enable = mmhub_v1_7_gart_enable,
1338         .set_fault_enable_default = mmhub_v1_7_set_fault_enable_default,
1339         .gart_disable = mmhub_v1_7_gart_disable,
1340         .set_clockgating = mmhub_v1_7_set_clockgating,
1341         .get_clockgating = mmhub_v1_7_get_clockgating,
1342         .setup_vm_pt_regs = mmhub_v1_7_setup_vm_pt_regs,
1343 };