2 * Copyright 2016 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/firmware.h>
26 #include "amdgpu_atomfirmware.h"
28 #include "hdp/hdp_4_0_offset.h"
29 #include "hdp/hdp_4_0_sh_mask.h"
30 #include "gc/gc_9_0_sh_mask.h"
31 #include "dce/dce_12_0_offset.h"
32 #include "dce/dce_12_0_sh_mask.h"
33 #include "vega10_enum.h"
34 #include "mmhub/mmhub_1_0_offset.h"
35 #include "athub/athub_1_0_offset.h"
38 #include "soc15_common.h"
39 #include "umc/umc_6_0_sh_mask.h"
41 #include "gfxhub_v1_0.h"
42 #include "mmhub_v1_0.h"
44 #define mmDF_CS_AON0_DramBaseAddress0 0x0044
45 #define mmDF_CS_AON0_DramBaseAddress0_BASE_IDX 0
46 //DF_CS_AON0_DramBaseAddress0
47 #define DF_CS_AON0_DramBaseAddress0__AddrRngVal__SHIFT 0x0
48 #define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn__SHIFT 0x1
49 #define DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT 0x4
50 #define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel__SHIFT 0x8
51 #define DF_CS_AON0_DramBaseAddress0__DramBaseAddr__SHIFT 0xc
52 #define DF_CS_AON0_DramBaseAddress0__AddrRngVal_MASK 0x00000001L
53 #define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn_MASK 0x00000002L
54 #define DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK 0x000000F0L
55 #define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel_MASK 0x00000700L
56 #define DF_CS_AON0_DramBaseAddress0__DramBaseAddr_MASK 0xFFFFF000L
58 /* XXX Move this macro to VEGA10 header file, which is like vid.h for VI.*/
59 #define AMDGPU_NUM_OF_VMIDS 8
61 static const u32 golden_settings_vega10_hdp[] =
63 0xf64, 0x0fffffff, 0x00000000,
64 0xf65, 0x0fffffff, 0x00000000,
65 0xf66, 0x0fffffff, 0x00000000,
66 0xf67, 0x0fffffff, 0x00000000,
67 0xf68, 0x0fffffff, 0x00000000,
68 0xf6a, 0x0fffffff, 0x00000000,
69 0xf6b, 0x0fffffff, 0x00000000,
70 0xf6c, 0x0fffffff, 0x00000000,
71 0xf6d, 0x0fffffff, 0x00000000,
72 0xf6e, 0x0fffffff, 0x00000000,
75 static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] =
77 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa),
78 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0, 0x00000030, 0x55555565)
81 static const struct soc15_reg_golden golden_settings_athub_1_0_0[] =
83 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL, 0x0000ff00, 0x00000800),
84 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL2, 0x00ff00ff, 0x00080008)
87 /* Ecc related register addresses, (BASE + reg offset) */
88 /* Universal Memory Controller caps (may be fused). */
89 /* UMCCH:UmcLocalCap */
90 #define UMCLOCALCAPS_ADDR0 (0x00014306 + 0x00000000)
91 #define UMCLOCALCAPS_ADDR1 (0x00014306 + 0x00000800)
92 #define UMCLOCALCAPS_ADDR2 (0x00014306 + 0x00001000)
93 #define UMCLOCALCAPS_ADDR3 (0x00014306 + 0x00001800)
94 #define UMCLOCALCAPS_ADDR4 (0x00054306 + 0x00000000)
95 #define UMCLOCALCAPS_ADDR5 (0x00054306 + 0x00000800)
96 #define UMCLOCALCAPS_ADDR6 (0x00054306 + 0x00001000)
97 #define UMCLOCALCAPS_ADDR7 (0x00054306 + 0x00001800)
98 #define UMCLOCALCAPS_ADDR8 (0x00094306 + 0x00000000)
99 #define UMCLOCALCAPS_ADDR9 (0x00094306 + 0x00000800)
100 #define UMCLOCALCAPS_ADDR10 (0x00094306 + 0x00001000)
101 #define UMCLOCALCAPS_ADDR11 (0x00094306 + 0x00001800)
102 #define UMCLOCALCAPS_ADDR12 (0x000d4306 + 0x00000000)
103 #define UMCLOCALCAPS_ADDR13 (0x000d4306 + 0x00000800)
104 #define UMCLOCALCAPS_ADDR14 (0x000d4306 + 0x00001000)
105 #define UMCLOCALCAPS_ADDR15 (0x000d4306 + 0x00001800)
107 /* Universal Memory Controller Channel config. */
108 /* UMCCH:UMC_CONFIG */
109 #define UMCCH_UMC_CONFIG_ADDR0 (0x00014040 + 0x00000000)
110 #define UMCCH_UMC_CONFIG_ADDR1 (0x00014040 + 0x00000800)
111 #define UMCCH_UMC_CONFIG_ADDR2 (0x00014040 + 0x00001000)
112 #define UMCCH_UMC_CONFIG_ADDR3 (0x00014040 + 0x00001800)
113 #define UMCCH_UMC_CONFIG_ADDR4 (0x00054040 + 0x00000000)
114 #define UMCCH_UMC_CONFIG_ADDR5 (0x00054040 + 0x00000800)
115 #define UMCCH_UMC_CONFIG_ADDR6 (0x00054040 + 0x00001000)
116 #define UMCCH_UMC_CONFIG_ADDR7 (0x00054040 + 0x00001800)
117 #define UMCCH_UMC_CONFIG_ADDR8 (0x00094040 + 0x00000000)
118 #define UMCCH_UMC_CONFIG_ADDR9 (0x00094040 + 0x00000800)
119 #define UMCCH_UMC_CONFIG_ADDR10 (0x00094040 + 0x00001000)
120 #define UMCCH_UMC_CONFIG_ADDR11 (0x00094040 + 0x00001800)
121 #define UMCCH_UMC_CONFIG_ADDR12 (0x000d4040 + 0x00000000)
122 #define UMCCH_UMC_CONFIG_ADDR13 (0x000d4040 + 0x00000800)
123 #define UMCCH_UMC_CONFIG_ADDR14 (0x000d4040 + 0x00001000)
124 #define UMCCH_UMC_CONFIG_ADDR15 (0x000d4040 + 0x00001800)
126 /* Universal Memory Controller Channel Ecc config. */
128 #define UMCCH_ECCCTRL_ADDR0 (0x00014053 + 0x00000000)
129 #define UMCCH_ECCCTRL_ADDR1 (0x00014053 + 0x00000800)
130 #define UMCCH_ECCCTRL_ADDR2 (0x00014053 + 0x00001000)
131 #define UMCCH_ECCCTRL_ADDR3 (0x00014053 + 0x00001800)
132 #define UMCCH_ECCCTRL_ADDR4 (0x00054053 + 0x00000000)
133 #define UMCCH_ECCCTRL_ADDR5 (0x00054053 + 0x00000800)
134 #define UMCCH_ECCCTRL_ADDR6 (0x00054053 + 0x00001000)
135 #define UMCCH_ECCCTRL_ADDR7 (0x00054053 + 0x00001800)
136 #define UMCCH_ECCCTRL_ADDR8 (0x00094053 + 0x00000000)
137 #define UMCCH_ECCCTRL_ADDR9 (0x00094053 + 0x00000800)
138 #define UMCCH_ECCCTRL_ADDR10 (0x00094053 + 0x00001000)
139 #define UMCCH_ECCCTRL_ADDR11 (0x00094053 + 0x00001800)
140 #define UMCCH_ECCCTRL_ADDR12 (0x000d4053 + 0x00000000)
141 #define UMCCH_ECCCTRL_ADDR13 (0x000d4053 + 0x00000800)
142 #define UMCCH_ECCCTRL_ADDR14 (0x000d4053 + 0x00001000)
143 #define UMCCH_ECCCTRL_ADDR15 (0x000d4053 + 0x00001800)
145 static const uint32_t ecc_umclocalcap_addrs[] = {
164 static const uint32_t ecc_umcch_umc_config_addrs[] = {
165 UMCCH_UMC_CONFIG_ADDR0,
166 UMCCH_UMC_CONFIG_ADDR1,
167 UMCCH_UMC_CONFIG_ADDR2,
168 UMCCH_UMC_CONFIG_ADDR3,
169 UMCCH_UMC_CONFIG_ADDR4,
170 UMCCH_UMC_CONFIG_ADDR5,
171 UMCCH_UMC_CONFIG_ADDR6,
172 UMCCH_UMC_CONFIG_ADDR7,
173 UMCCH_UMC_CONFIG_ADDR8,
174 UMCCH_UMC_CONFIG_ADDR9,
175 UMCCH_UMC_CONFIG_ADDR10,
176 UMCCH_UMC_CONFIG_ADDR11,
177 UMCCH_UMC_CONFIG_ADDR12,
178 UMCCH_UMC_CONFIG_ADDR13,
179 UMCCH_UMC_CONFIG_ADDR14,
180 UMCCH_UMC_CONFIG_ADDR15,
183 static const uint32_t ecc_umcch_eccctrl_addrs[] = {
194 UMCCH_ECCCTRL_ADDR10,
195 UMCCH_ECCCTRL_ADDR11,
196 UMCCH_ECCCTRL_ADDR12,
197 UMCCH_ECCCTRL_ADDR13,
198 UMCCH_ECCCTRL_ADDR14,
199 UMCCH_ECCCTRL_ADDR15,
202 static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
203 struct amdgpu_irq_src *src,
205 enum amdgpu_interrupt_state state)
207 struct amdgpu_vmhub *hub;
208 u32 tmp, reg, bits, i, j;
210 bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
211 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
212 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
213 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
214 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
215 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
216 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
219 case AMDGPU_IRQ_STATE_DISABLE:
220 for (j = 0; j < AMDGPU_MAX_VMHUBS; j++) {
221 hub = &adev->vmhub[j];
222 for (i = 0; i < 16; i++) {
223 reg = hub->vm_context0_cntl + i;
230 case AMDGPU_IRQ_STATE_ENABLE:
231 for (j = 0; j < AMDGPU_MAX_VMHUBS; j++) {
232 hub = &adev->vmhub[j];
233 for (i = 0; i < 16; i++) {
234 reg = hub->vm_context0_cntl + i;
247 static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,
248 struct amdgpu_irq_src *source,
249 struct amdgpu_iv_entry *entry)
251 struct amdgpu_vmhub *hub = &adev->vmhub[entry->vmid_src];
255 addr = (u64)entry->src_data[0] << 12;
256 addr |= ((u64)entry->src_data[1] & 0xf) << 44;
258 if (!amdgpu_sriov_vf(adev)) {
259 status = RREG32(hub->vm_l2_pro_fault_status);
260 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
263 if (printk_ratelimit()) {
265 "[%s] VMC page fault (src_id:%u ring:%u vmid:%u pas_id:%u)\n",
266 entry->vmid_src ? "mmhub" : "gfxhub",
267 entry->src_id, entry->ring_id, entry->vmid,
269 dev_err(adev->dev, " at page 0x%016llx from %d\n",
270 addr, entry->client_id);
271 if (!amdgpu_sriov_vf(adev))
273 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
280 static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = {
281 .set = gmc_v9_0_vm_fault_interrupt_state,
282 .process = gmc_v9_0_process_interrupt,
285 static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev)
287 adev->mc.vm_fault.num_types = 1;
288 adev->mc.vm_fault.funcs = &gmc_v9_0_irq_funcs;
291 static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid)
295 /* invalidate using legacy mode on vmid*/
296 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
297 PER_VMID_INVALIDATE_REQ, 1 << vmid);
298 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, 0);
299 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
300 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
301 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
302 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
303 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
304 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
305 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
312 * VMID 0 is the physical GPU addresses as used by the kernel.
313 * VMIDs 1-15 are used for userspace clients and are handled
314 * by the amdgpu vm/hsa code.
318 * gmc_v9_0_gart_flush_gpu_tlb - gart tlb flush callback
320 * @adev: amdgpu_device pointer
321 * @vmid: vm instance to flush
323 * Flush the TLB for the requested page table.
325 static void gmc_v9_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
328 /* Use register 17 for GART */
329 const unsigned eng = 17;
332 /* flush hdp cache */
333 adev->nbio_funcs->hdp_flush(adev);
335 spin_lock(&adev->mc.invalidate_lock);
337 for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {
338 struct amdgpu_vmhub *hub = &adev->vmhub[i];
339 u32 tmp = gmc_v9_0_get_invalidate_req(vmid);
341 WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp);
343 /* Busy wait for ACK.*/
344 for (j = 0; j < 100; j++) {
345 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng);
354 /* Wait for ACK with a delay.*/
355 for (j = 0; j < adev->usec_timeout; j++) {
356 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng);
362 if (j < adev->usec_timeout)
365 DRM_ERROR("Timeout waiting for VM flush ACK!\n");
368 spin_unlock(&adev->mc.invalidate_lock);
372 * gmc_v9_0_gart_set_pte_pde - update the page tables using MMIO
374 * @adev: amdgpu_device pointer
375 * @cpu_pt_addr: cpu address of the page table
376 * @gpu_page_idx: entry in the page table to update
377 * @addr: dst addr to write into pte/pde
378 * @flags: access flags
380 * Update the page tables using the CPU.
382 static int gmc_v9_0_gart_set_pte_pde(struct amdgpu_device *adev,
384 uint32_t gpu_page_idx,
388 void __iomem *ptr = (void *)cpu_pt_addr;
392 * PTE format on VEGA 10:
401 * 47:12 4k physical page base address
411 * PDE format on VEGA 10:
412 * 63:59 block fragment size
416 * 47:6 physical base address of PD or PTE
424 * The following is for PTE only. GART does not have PDEs.
426 value = addr & 0x0000FFFFFFFFF000ULL;
428 writeq(value, ptr + (gpu_page_idx * 8));
432 static uint64_t gmc_v9_0_get_vm_pte_flags(struct amdgpu_device *adev,
436 uint64_t pte_flag = 0;
438 if (flags & AMDGPU_VM_PAGE_EXECUTABLE)
439 pte_flag |= AMDGPU_PTE_EXECUTABLE;
440 if (flags & AMDGPU_VM_PAGE_READABLE)
441 pte_flag |= AMDGPU_PTE_READABLE;
442 if (flags & AMDGPU_VM_PAGE_WRITEABLE)
443 pte_flag |= AMDGPU_PTE_WRITEABLE;
445 switch (flags & AMDGPU_VM_MTYPE_MASK) {
446 case AMDGPU_VM_MTYPE_DEFAULT:
447 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC);
449 case AMDGPU_VM_MTYPE_NC:
450 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC);
452 case AMDGPU_VM_MTYPE_WC:
453 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_WC);
455 case AMDGPU_VM_MTYPE_CC:
456 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_CC);
458 case AMDGPU_VM_MTYPE_UC:
459 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_UC);
462 pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC);
466 if (flags & AMDGPU_VM_PAGE_PRT)
467 pte_flag |= AMDGPU_PTE_PRT;
472 static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level,
473 uint64_t *addr, uint64_t *flags)
475 if (!(*flags & AMDGPU_PDE_PTE))
476 *addr = adev->vm_manager.vram_base_offset + *addr -
478 BUG_ON(*addr & 0xFFFF00000000003FULL);
480 if (!adev->mc.translate_further)
483 if (level == AMDGPU_VM_PDB1) {
484 /* Set the block fragment size */
485 if (!(*flags & AMDGPU_PDE_PTE))
486 *flags |= AMDGPU_PDE_BFS(0x9);
488 } else if (level == AMDGPU_VM_PDB0) {
489 if (*flags & AMDGPU_PDE_PTE)
490 *flags &= ~AMDGPU_PDE_PTE;
492 *flags |= AMDGPU_PTE_TF;
496 static const struct amdgpu_gart_funcs gmc_v9_0_gart_funcs = {
497 .flush_gpu_tlb = gmc_v9_0_gart_flush_gpu_tlb,
498 .set_pte_pde = gmc_v9_0_gart_set_pte_pde,
499 .get_invalidate_req = gmc_v9_0_get_invalidate_req,
500 .get_vm_pte_flags = gmc_v9_0_get_vm_pte_flags,
501 .get_vm_pde = gmc_v9_0_get_vm_pde
504 static void gmc_v9_0_set_gart_funcs(struct amdgpu_device *adev)
506 if (adev->gart.gart_funcs == NULL)
507 adev->gart.gart_funcs = &gmc_v9_0_gart_funcs;
510 static int gmc_v9_0_early_init(void *handle)
512 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
514 gmc_v9_0_set_gart_funcs(adev);
515 gmc_v9_0_set_irq_funcs(adev);
517 adev->mc.shared_aperture_start = 0x2000000000000000ULL;
518 adev->mc.shared_aperture_end =
519 adev->mc.shared_aperture_start + (4ULL << 30) - 1;
520 adev->mc.private_aperture_start =
521 adev->mc.shared_aperture_end + 1;
522 adev->mc.private_aperture_end =
523 adev->mc.private_aperture_start + (4ULL << 30) - 1;
528 static int gmc_v9_0_ecc_available(struct amdgpu_device *adev)
537 DRM_DEBUG("ecc: gmc_v9_0_ecc_available()\n");
540 for (i = 0; i < ARRAY_SIZE(ecc_umclocalcap_addrs); ++i) {
541 reg_addr = ecc_umclocalcap_addrs[i];
543 "UMCCH_UmcLocalCap[%zu]: reg_addr: 0x%08x\n",
545 reg_val = RREG32(reg_addr);
546 field_val = REG_GET_FIELD(reg_val, UMCCH0_0_UmcLocalCap,
553 DRM_ERROR("ecc: UmcLocalCap:EccDis is set.\n");
558 for (i = 0; i < ARRAY_SIZE(ecc_umcch_umc_config_addrs); ++i) {
559 reg_addr = ecc_umcch_umc_config_addrs[i];
561 "UMCCH0_0_UMC_CONFIG[%zu]: reg_addr: 0x%08x",
563 reg_val = RREG32(reg_addr);
564 field_val = REG_GET_FIELD(reg_val, UMCCH0_0_UMC_CONFIG,
568 "DramReady: 0x%08x\n",
572 DRM_ERROR("ecc: UMC_CONFIG:DramReady is not set.\n");
577 for (i = 0; i < ARRAY_SIZE(ecc_umcch_eccctrl_addrs); ++i) {
578 reg_addr = ecc_umcch_eccctrl_addrs[i];
580 "UMCCH_EccCtrl[%zu]: reg_addr: 0x%08x, ",
582 reg_val = RREG32(reg_addr);
583 field_val = REG_GET_FIELD(reg_val, UMCCH0_0_EccCtrl,
585 fv2 = REG_GET_FIELD(reg_val, UMCCH0_0_EccCtrl,
591 reg_val, field_val, fv2);
594 DRM_DEBUG("ecc: WrEccEn is not set\n");
598 DRM_DEBUG("ecc: RdEccEn is not set\n");
603 DRM_DEBUG("ecc: lost_sheep: %zu\n", lost_sheep);
604 return lost_sheep == 0;
607 static int gmc_v9_0_late_init(void *handle)
609 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
611 * The latest engine allocation on gfx9 is:
613 * Engine 2, 3: firmware
614 * Engine 4~13: amdgpu ring, subject to change when ring number changes
616 * Engine 16: kfd tlb invalidation
617 * Engine 17: Gart flushes
619 unsigned vm_inv_eng[AMDGPU_MAX_VMHUBS] = { 4, 4 };
623 for(i = 0; i < adev->num_rings; ++i) {
624 struct amdgpu_ring *ring = adev->rings[i];
625 unsigned vmhub = ring->funcs->vmhub;
627 ring->vm_inv_eng = vm_inv_eng[vmhub]++;
628 dev_info(adev->dev, "ring %u(%s) uses VM inv eng %u on hub %u\n",
629 ring->idx, ring->name, ring->vm_inv_eng,
633 /* Engine 16 is used for KFD and 17 for GART flushes */
634 for(i = 0; i < AMDGPU_MAX_VMHUBS; ++i)
635 BUG_ON(vm_inv_eng[i] > 16);
637 if (adev->asic_type == CHIP_VEGA10 && !amdgpu_sriov_vf(adev)) {
638 r = gmc_v9_0_ecc_available(adev);
640 DRM_INFO("ECC is active.\n");
642 DRM_INFO("ECC is not present.\n");
644 DRM_ERROR("gmc_v9_0_ecc_available() failed. r: %d\n", r);
649 return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
652 static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev,
653 struct amdgpu_mc *mc)
656 if (!amdgpu_sriov_vf(adev))
657 base = mmhub_v1_0_get_fb_location(adev);
658 amdgpu_device_vram_location(adev, &adev->mc, base);
659 amdgpu_device_gart_location(adev, mc);
660 /* base offset of vram pages */
661 if (adev->flags & AMD_IS_APU)
662 adev->vm_manager.vram_base_offset = gfxhub_v1_0_get_mc_fb_offset(adev);
664 adev->vm_manager.vram_base_offset = 0;
668 * gmc_v9_0_mc_init - initialize the memory controller driver params
670 * @adev: amdgpu_device pointer
672 * Look up the amount of vram, vram width, and decide how to place
673 * vram and gart within the GPU's physical address space.
674 * Returns 0 for success.
676 static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
679 int chansize, numchan;
682 adev->mc.vram_width = amdgpu_atomfirmware_get_vram_width(adev);
683 if (!adev->mc.vram_width) {
684 /* hbm memory channel size */
685 if (adev->flags & AMD_IS_APU)
690 tmp = RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0);
691 tmp &= DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK;
692 tmp >>= DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT;
723 adev->mc.vram_width = numchan * chansize;
726 /* size in MB on si */
727 adev->mc.mc_vram_size =
728 adev->nbio_funcs->get_memsize(adev) * 1024ULL * 1024ULL;
729 adev->mc.real_vram_size = adev->mc.mc_vram_size;
731 if (!(adev->flags & AMD_IS_APU)) {
732 r = amdgpu_device_resize_fb_bar(adev);
736 adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
737 adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
739 /* In case the PCI BAR is larger than the actual amount of vram */
740 adev->mc.visible_vram_size = adev->mc.aper_size;
741 if (adev->mc.visible_vram_size > adev->mc.real_vram_size)
742 adev->mc.visible_vram_size = adev->mc.real_vram_size;
744 /* set the gart size */
745 if (amdgpu_gart_size == -1) {
746 switch (adev->asic_type) {
747 case CHIP_VEGA10: /* all engines support GPUVM */
749 adev->mc.gart_size = 256ULL << 20;
751 case CHIP_RAVEN: /* DCE SG support */
752 adev->mc.gart_size = 1024ULL << 20;
756 adev->mc.gart_size = (u64)amdgpu_gart_size << 20;
759 gmc_v9_0_vram_gtt_location(adev, &adev->mc);
764 static int gmc_v9_0_gart_init(struct amdgpu_device *adev)
768 if (adev->gart.robj) {
769 WARN(1, "VEGA10 PCIE GART already initialized\n");
772 /* Initialize common gart structure */
773 r = amdgpu_gart_init(adev);
776 adev->gart.table_size = adev->gart.num_gpu_pages * 8;
777 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE(MTYPE_UC) |
778 AMDGPU_PTE_EXECUTABLE;
779 return amdgpu_gart_table_vram_alloc(adev);
782 static int gmc_v9_0_sw_init(void *handle)
786 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
788 gfxhub_v1_0_init(adev);
789 mmhub_v1_0_init(adev);
791 spin_lock_init(&adev->mc.invalidate_lock);
793 switch (adev->asic_type) {
795 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
796 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) {
797 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
799 /* vm_size is 128TB + 512GB for legacy 3-level page support */
800 amdgpu_vm_adjust_size(adev, 128 * 1024 + 512, 9, 2, 48);
801 adev->mc.translate_further =
802 adev->vm_manager.num_level > 1;
806 /* XXX Don't know how to get VRAM type yet. */
807 adev->mc.vram_type = AMDGPU_VRAM_TYPE_HBM;
809 * To fulfill 4-level page support,
810 * vm size is 256TB (48bit), maximum size of Vega10,
811 * block size 512 (9bit)
813 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
819 /* This interrupt is VMC page fault.*/
820 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_VMC, 0,
822 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_UTCL2, 0,
828 /* Set the internal MC address mask
829 * This is the max address of the GPU's
830 * internal address space.
832 adev->mc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
835 * It needs to reserve 8M stolen memory for vega10
836 * TODO: Figure out how to avoid that...
838 adev->mc.stolen_size = 8 * 1024 * 1024;
840 /* set DMA mask + need_dma32 flags.
841 * PCIE - can handle 44-bits.
842 * IGP - can handle 44-bits
843 * PCI - dma32 for legacy pci gart, 44 bits on vega10
845 adev->need_dma32 = false;
846 dma_bits = adev->need_dma32 ? 32 : 44;
847 r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
849 adev->need_dma32 = true;
851 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
853 r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
855 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
856 printk(KERN_WARNING "amdgpu: No coherent DMA available.\n");
859 r = gmc_v9_0_mc_init(adev);
864 r = amdgpu_bo_init(adev);
868 r = gmc_v9_0_gart_init(adev);
874 * VMID 0 is reserved for System
875 * amdgpu graphics/compute will use VMIDs 1-7
876 * amdkfd will use VMIDs 8-15
878 adev->vm_manager.id_mgr[AMDGPU_GFXHUB].num_ids = AMDGPU_NUM_OF_VMIDS;
879 adev->vm_manager.id_mgr[AMDGPU_MMHUB].num_ids = AMDGPU_NUM_OF_VMIDS;
881 amdgpu_vm_manager_init(adev);
887 * gmc_v9_0_gart_fini - vm fini callback
889 * @adev: amdgpu_device pointer
891 * Tears down the driver GART/VM setup (CIK).
893 static void gmc_v9_0_gart_fini(struct amdgpu_device *adev)
895 amdgpu_gart_table_vram_free(adev);
896 amdgpu_gart_fini(adev);
899 static int gmc_v9_0_sw_fini(void *handle)
901 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
903 amdgpu_gem_force_release(adev);
904 amdgpu_vm_manager_fini(adev);
905 gmc_v9_0_gart_fini(adev);
906 amdgpu_bo_fini(adev);
911 static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev)
914 switch (adev->asic_type) {
916 soc15_program_register_sequence(adev,
917 golden_settings_mmhub_1_0_0,
918 ARRAY_SIZE(golden_settings_mmhub_1_0_0));
919 soc15_program_register_sequence(adev,
920 golden_settings_athub_1_0_0,
921 ARRAY_SIZE(golden_settings_athub_1_0_0));
924 soc15_program_register_sequence(adev,
925 golden_settings_athub_1_0_0,
926 ARRAY_SIZE(golden_settings_athub_1_0_0));
934 * gmc_v9_0_gart_enable - gart enable
936 * @adev: amdgpu_device pointer
938 static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
944 amdgpu_device_program_register_sequence(adev,
945 golden_settings_vega10_hdp,
946 ARRAY_SIZE(golden_settings_vega10_hdp));
948 if (adev->gart.robj == NULL) {
949 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
952 r = amdgpu_gart_table_vram_pin(adev);
956 switch (adev->asic_type) {
958 mmhub_v1_0_initialize_power_gating(adev);
959 mmhub_v1_0_update_power_gating(adev, true);
965 r = gfxhub_v1_0_gart_enable(adev);
969 r = mmhub_v1_0_gart_enable(adev);
973 WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1);
975 tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL);
976 WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp);
978 /* After HDP is initialized, flush HDP.*/
979 adev->nbio_funcs->hdp_flush(adev);
981 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
986 gfxhub_v1_0_set_fault_enable_default(adev, value);
987 mmhub_v1_0_set_fault_enable_default(adev, value);
988 gmc_v9_0_gart_flush_gpu_tlb(adev, 0);
990 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
991 (unsigned)(adev->mc.gart_size >> 20),
992 (unsigned long long)adev->gart.table_addr);
993 adev->gart.ready = true;
997 static int gmc_v9_0_hw_init(void *handle)
1000 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1002 /* The sequence of these two function calls matters.*/
1003 gmc_v9_0_init_golden_registers(adev);
1005 if (adev->mode_info.num_crtc) {
1006 /* Lockout access through VGA aperture*/
1007 WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
1009 /* disable VGA render */
1010 WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
1013 r = gmc_v9_0_gart_enable(adev);
1019 * gmc_v9_0_gart_disable - gart disable
1021 * @adev: amdgpu_device pointer
1023 * This disables all VM page table.
1025 static void gmc_v9_0_gart_disable(struct amdgpu_device *adev)
1027 gfxhub_v1_0_gart_disable(adev);
1028 mmhub_v1_0_gart_disable(adev);
1029 amdgpu_gart_table_vram_unpin(adev);
1032 static int gmc_v9_0_hw_fini(void *handle)
1034 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1036 if (amdgpu_sriov_vf(adev)) {
1037 /* full access mode, so don't touch any GMC register */
1038 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
1042 amdgpu_irq_put(adev, &adev->mc.vm_fault, 0);
1043 gmc_v9_0_gart_disable(adev);
1048 static int gmc_v9_0_suspend(void *handle)
1050 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1052 return gmc_v9_0_hw_fini(adev);
1055 static int gmc_v9_0_resume(void *handle)
1058 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1060 r = gmc_v9_0_hw_init(adev);
1064 amdgpu_vmid_reset_all(adev);
1069 static bool gmc_v9_0_is_idle(void *handle)
1071 /* MC is always ready in GMC v9.*/
1075 static int gmc_v9_0_wait_for_idle(void *handle)
1077 /* There is no need to wait for MC idle in GMC v9.*/
1081 static int gmc_v9_0_soft_reset(void *handle)
1083 /* XXX for emulation.*/
1087 static int gmc_v9_0_set_clockgating_state(void *handle,
1088 enum amd_clockgating_state state)
1090 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1092 return mmhub_v1_0_set_clockgating(adev, state);
1095 static void gmc_v9_0_get_clockgating_state(void *handle, u32 *flags)
1097 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1099 mmhub_v1_0_get_clockgating(adev, flags);
1102 static int gmc_v9_0_set_powergating_state(void *handle,
1103 enum amd_powergating_state state)
1108 const struct amd_ip_funcs gmc_v9_0_ip_funcs = {
1110 .early_init = gmc_v9_0_early_init,
1111 .late_init = gmc_v9_0_late_init,
1112 .sw_init = gmc_v9_0_sw_init,
1113 .sw_fini = gmc_v9_0_sw_fini,
1114 .hw_init = gmc_v9_0_hw_init,
1115 .hw_fini = gmc_v9_0_hw_fini,
1116 .suspend = gmc_v9_0_suspend,
1117 .resume = gmc_v9_0_resume,
1118 .is_idle = gmc_v9_0_is_idle,
1119 .wait_for_idle = gmc_v9_0_wait_for_idle,
1120 .soft_reset = gmc_v9_0_soft_reset,
1121 .set_clockgating_state = gmc_v9_0_set_clockgating_state,
1122 .set_powergating_state = gmc_v9_0_set_powergating_state,
1123 .get_clockgating_state = gmc_v9_0_get_clockgating_state,
1126 const struct amdgpu_ip_block_version gmc_v9_0_ip_block =
1128 .type = AMD_IP_BLOCK_TYPE_GMC,
1132 .funcs = &gmc_v9_0_ip_funcs,