2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/firmware.h>
24 #include <linux/pci.h>
26 #include "amdgpu_atomfirmware.h"
27 #include "gmc_v10_0.h"
29 #include "hdp/hdp_5_0_0_offset.h"
30 #include "hdp/hdp_5_0_0_sh_mask.h"
31 #include "gc/gc_10_1_0_sh_mask.h"
32 #include "mmhub/mmhub_2_0_0_sh_mask.h"
33 #include "athub/athub_2_0_0_sh_mask.h"
34 #include "athub/athub_2_0_0_offset.h"
35 #include "dcn/dcn_2_0_0_offset.h"
36 #include "dcn/dcn_2_0_0_sh_mask.h"
37 #include "oss/osssys_5_0_0_offset.h"
38 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h"
39 #include "navi10_enum.h"
43 #include "soc15_common.h"
45 #include "nbio_v2_3.h"
47 #include "gfxhub_v2_0.h"
48 #include "mmhub_v2_0.h"
49 #include "athub_v2_0.h"
50 /* XXX Move this macro to navi10 header file, which is like vid.h for VI.*/
51 #define AMDGPU_NUM_OF_VMIDS 8
54 static const struct soc15_reg_golden golden_settings_navi10_hdp[] =
56 /* TODO add golden setting for hdp */
61 gmc_v10_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
62 struct amdgpu_irq_src *src, unsigned type,
63 enum amdgpu_interrupt_state state)
65 struct amdgpu_vmhub *hub;
66 u32 tmp, reg, bits[AMDGPU_MAX_VMHUBS], i;
68 bits[AMDGPU_GFXHUB_0] = GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
69 GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
70 GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
71 GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
72 GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
73 GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
74 GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
76 bits[AMDGPU_MMHUB_0] = MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
77 MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
78 MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
79 MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
80 MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
81 MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
82 MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
85 case AMDGPU_IRQ_STATE_DISABLE:
87 hub = &adev->vmhub[AMDGPU_MMHUB_0];
88 for (i = 0; i < 16; i++) {
89 reg = hub->vm_context0_cntl + i;
91 tmp &= ~bits[AMDGPU_MMHUB_0];
96 hub = &adev->vmhub[AMDGPU_GFXHUB_0];
97 for (i = 0; i < 16; i++) {
98 reg = hub->vm_context0_cntl + i;
100 tmp &= ~bits[AMDGPU_GFXHUB_0];
104 case AMDGPU_IRQ_STATE_ENABLE:
106 hub = &adev->vmhub[AMDGPU_MMHUB_0];
107 for (i = 0; i < 16; i++) {
108 reg = hub->vm_context0_cntl + i;
110 tmp |= bits[AMDGPU_MMHUB_0];
115 hub = &adev->vmhub[AMDGPU_GFXHUB_0];
116 for (i = 0; i < 16; i++) {
117 reg = hub->vm_context0_cntl + i;
119 tmp |= bits[AMDGPU_GFXHUB_0];
130 static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev,
131 struct amdgpu_irq_src *source,
132 struct amdgpu_iv_entry *entry)
134 struct amdgpu_vmhub *hub = &adev->vmhub[entry->vmid_src];
138 addr = (u64)entry->src_data[0] << 12;
139 addr |= ((u64)entry->src_data[1] & 0xf) << 44;
141 if (!amdgpu_sriov_vf(adev)) {
143 * Issue a dummy read to wait for the status register to
144 * be updated to avoid reading an incorrect value due to
145 * the new fast GRBM interface.
147 if (entry->vmid_src == AMDGPU_GFXHUB_0)
148 RREG32(hub->vm_l2_pro_fault_status);
150 status = RREG32(hub->vm_l2_pro_fault_status);
151 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
154 if (printk_ratelimit()) {
155 struct amdgpu_task_info task_info;
157 memset(&task_info, 0, sizeof(struct amdgpu_task_info));
158 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
161 "[%s] page fault (src_id:%u ring:%u vmid:%u pasid:%u, "
162 "for process %s pid %d thread %s pid %d)\n",
163 entry->vmid_src ? "mmhub" : "gfxhub",
164 entry->src_id, entry->ring_id, entry->vmid,
165 entry->pasid, task_info.process_name, task_info.tgid,
166 task_info.task_name, task_info.pid);
167 dev_err(adev->dev, " in page starting at address 0x%016llx from client %d\n",
168 addr, entry->client_id);
169 if (!amdgpu_sriov_vf(adev)) {
171 "GCVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
173 dev_err(adev->dev, "\t Faulty UTCL2 client ID: 0x%lx\n",
174 REG_GET_FIELD(status,
175 GCVM_L2_PROTECTION_FAULT_STATUS, CID));
176 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
177 REG_GET_FIELD(status,
178 GCVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
179 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
180 REG_GET_FIELD(status,
181 GCVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
182 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
183 REG_GET_FIELD(status,
184 GCVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
185 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
186 REG_GET_FIELD(status,
187 GCVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
188 dev_err(adev->dev, "\t RW: 0x%lx\n",
189 REG_GET_FIELD(status,
190 GCVM_L2_PROTECTION_FAULT_STATUS, RW));
197 static const struct amdgpu_irq_src_funcs gmc_v10_0_irq_funcs = {
198 .set = gmc_v10_0_vm_fault_interrupt_state,
199 .process = gmc_v10_0_process_interrupt,
202 static void gmc_v10_0_set_irq_funcs(struct amdgpu_device *adev)
204 adev->gmc.vm_fault.num_types = 1;
205 adev->gmc.vm_fault.funcs = &gmc_v10_0_irq_funcs;
208 static uint32_t gmc_v10_0_get_invalidate_req(unsigned int vmid,
213 /* invalidate using legacy mode on vmid*/
214 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,
215 PER_VMID_INVALIDATE_REQ, 1 << vmid);
216 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
217 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
218 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
219 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
220 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
221 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
222 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,
223 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
229 * gmc_v10_0_use_invalidate_semaphore - judge whether to use semaphore
231 * @adev: amdgpu_device pointer
235 static bool gmc_v10_0_use_invalidate_semaphore(struct amdgpu_device *adev,
238 return ((vmhub == AMDGPU_MMHUB_0 ||
239 vmhub == AMDGPU_MMHUB_1) &&
240 (!amdgpu_sriov_vf(adev)));
243 static bool gmc_v10_0_get_atc_vmid_pasid_mapping_info(
244 struct amdgpu_device *adev,
245 uint8_t vmid, uint16_t *p_pasid)
249 value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
251 *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK;
253 return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
258 * VMID 0 is the physical GPU addresses as used by the kernel.
259 * VMIDs 1-15 are used for userspace clients and are handled
260 * by the amdgpu vm/hsa code.
263 static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid,
264 unsigned int vmhub, uint32_t flush_type)
266 bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(adev, vmhub);
267 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub];
268 u32 inv_req = gmc_v10_0_get_invalidate_req(vmid, flush_type);
270 /* Use register 17 for GART */
271 const unsigned eng = 17;
274 spin_lock(&adev->gmc.invalidate_lock);
276 * It may lose gpuvm invalidate acknowldege state across power-gating
277 * off cycle, add semaphore acquire before invalidation and semaphore
278 * release after invalidation to avoid entering power gated state
282 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
284 for (i = 0; i < adev->usec_timeout; i++) {
285 /* a read return value of 1 means semaphore acuqire */
286 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem + eng);
292 if (i >= adev->usec_timeout)
293 DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n");
296 WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, inv_req);
299 * Issue a dummy read to wait for the ACK register to be cleared
300 * to avoid a false ACK due to the new fast GRBM interface.
302 if (vmhub == AMDGPU_GFXHUB_0)
303 RREG32_NO_KIQ(hub->vm_inv_eng0_req + eng);
305 /* Wait for ACK with a delay.*/
306 for (i = 0; i < adev->usec_timeout; i++) {
307 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng);
315 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
318 * add semaphore release after invalidation,
319 * write with 0 means semaphore release
321 WREG32_NO_KIQ(hub->vm_inv_eng0_sem + eng, 0);
323 spin_unlock(&adev->gmc.invalidate_lock);
325 if (i < adev->usec_timeout)
328 DRM_ERROR("Timeout waiting for VM flush ACK!\n");
332 * gmc_v10_0_flush_gpu_tlb - gart tlb flush callback
334 * @adev: amdgpu_device pointer
335 * @vmid: vm instance to flush
337 * Flush the TLB for the requested page table.
339 static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
340 uint32_t vmhub, uint32_t flush_type)
342 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
343 struct dma_fence *fence;
344 struct amdgpu_job *job;
348 /* flush hdp cache */
349 adev->nbio.funcs->hdp_flush(adev, NULL);
351 mutex_lock(&adev->mman.gtt_window_lock);
353 if (vmhub == AMDGPU_MMHUB_0) {
354 gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_MMHUB_0, 0);
355 mutex_unlock(&adev->mman.gtt_window_lock);
359 BUG_ON(vmhub != AMDGPU_GFXHUB_0);
361 if (!adev->mman.buffer_funcs_enabled ||
362 !adev->ib_pool_ready ||
363 adev->in_gpu_reset ||
364 ring->sched.ready == false) {
365 gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_GFXHUB_0, 0);
366 mutex_unlock(&adev->mman.gtt_window_lock);
370 /* The SDMA on Navi has a bug which can theoretically result in memory
371 * corruption if an invalidation happens at the same time as an VA
372 * translation. Avoid this by doing the invalidation from the SDMA
375 r = amdgpu_job_alloc_with_ib(adev, 16 * 4, AMDGPU_IB_POOL_IMMEDIATE,
380 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo);
381 job->vm_needs_flush = true;
382 job->ibs->ptr[job->ibs->length_dw++] = ring->funcs->nop;
383 amdgpu_ring_pad_ib(ring, &job->ibs[0]);
384 r = amdgpu_job_submit(job, &adev->mman.entity,
385 AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
389 mutex_unlock(&adev->mman.gtt_window_lock);
391 dma_fence_wait(fence, false);
392 dma_fence_put(fence);
397 amdgpu_job_free(job);
400 mutex_unlock(&adev->mman.gtt_window_lock);
401 DRM_ERROR("Error flushing GPU TLB using the SDMA (%d)!\n", r);
405 * gmc_v10_0_flush_gpu_tlb_pasid - tlb flush via pasid
407 * @adev: amdgpu_device pointer
408 * @pasid: pasid to be flush
410 * Flush the TLB for the requested pasid.
412 static int gmc_v10_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
413 uint16_t pasid, uint32_t flush_type,
419 uint16_t queried_pasid;
421 struct amdgpu_ring *ring = &adev->gfx.kiq.ring;
422 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
424 if (amdgpu_emu_mode == 0 && ring->sched.ready) {
425 spin_lock(&adev->gfx.kiq.ring_lock);
426 /* 2 dwords flush + 8 dwords fence */
427 amdgpu_ring_alloc(ring, kiq->pmf->invalidate_tlbs_size + 8);
428 kiq->pmf->kiq_invalidate_tlbs(ring,
429 pasid, flush_type, all_hub);
430 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT);
432 amdgpu_ring_undo(ring);
433 spin_unlock(&adev->gfx.kiq.ring_lock);
437 amdgpu_ring_commit(ring);
438 spin_unlock(&adev->gfx.kiq.ring_lock);
439 r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout);
441 DRM_ERROR("wait for kiq fence error: %ld.\n", r);
448 for (vmid = 1; vmid < 16; vmid++) {
450 ret = gmc_v10_0_get_atc_vmid_pasid_mapping_info(adev, vmid,
452 if (ret && queried_pasid == pasid) {
454 for (i = 0; i < adev->num_vmhubs; i++)
455 gmc_v10_0_flush_gpu_tlb(adev, vmid,
458 gmc_v10_0_flush_gpu_tlb(adev, vmid,
459 AMDGPU_GFXHUB_0, flush_type);
468 static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
469 unsigned vmid, uint64_t pd_addr)
471 bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(ring->adev, ring->funcs->vmhub);
472 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
473 uint32_t req = gmc_v10_0_get_invalidate_req(vmid, 0);
474 unsigned eng = ring->vm_inv_eng;
477 * It may lose gpuvm invalidate acknowldege state across power-gating
478 * off cycle, add semaphore acquire before invalidation and semaphore
479 * release after invalidation to avoid entering power gated state
483 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
485 /* a read return value of 1 means semaphore acuqire */
486 amdgpu_ring_emit_reg_wait(ring,
487 hub->vm_inv_eng0_sem + eng, 0x1, 0x1);
489 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + (2 * vmid),
490 lower_32_bits(pd_addr));
492 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + (2 * vmid),
493 upper_32_bits(pd_addr));
495 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + eng,
496 hub->vm_inv_eng0_ack + eng,
499 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
502 * add semaphore release after invalidation,
503 * write with 0 means semaphore release
505 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + eng, 0);
510 static void gmc_v10_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid,
513 struct amdgpu_device *adev = ring->adev;
516 if (ring->funcs->vmhub == AMDGPU_GFXHUB_0)
517 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
519 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
521 amdgpu_ring_emit_wreg(ring, reg, pasid);
525 * PTE format on NAVI 10:
534 * 47:12 4k physical page base address
544 * PDE format on NAVI 10:
545 * 63:59 block fragment size
549 * 47:6 physical base address of PD or PTE
556 static uint64_t gmc_v10_0_map_mtype(struct amdgpu_device *adev, uint32_t flags)
559 case AMDGPU_VM_MTYPE_DEFAULT:
560 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);
561 case AMDGPU_VM_MTYPE_NC:
562 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);
563 case AMDGPU_VM_MTYPE_WC:
564 return AMDGPU_PTE_MTYPE_NV10(MTYPE_WC);
565 case AMDGPU_VM_MTYPE_CC:
566 return AMDGPU_PTE_MTYPE_NV10(MTYPE_CC);
567 case AMDGPU_VM_MTYPE_UC:
568 return AMDGPU_PTE_MTYPE_NV10(MTYPE_UC);
570 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);
574 static void gmc_v10_0_get_vm_pde(struct amdgpu_device *adev, int level,
575 uint64_t *addr, uint64_t *flags)
577 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM))
578 *addr = adev->vm_manager.vram_base_offset + *addr -
579 adev->gmc.vram_start;
580 BUG_ON(*addr & 0xFFFF00000000003FULL);
582 if (!adev->gmc.translate_further)
585 if (level == AMDGPU_VM_PDB1) {
586 /* Set the block fragment size */
587 if (!(*flags & AMDGPU_PDE_PTE))
588 *flags |= AMDGPU_PDE_BFS(0x9);
590 } else if (level == AMDGPU_VM_PDB0) {
591 if (*flags & AMDGPU_PDE_PTE)
592 *flags &= ~AMDGPU_PDE_PTE;
594 *flags |= AMDGPU_PTE_TF;
598 static void gmc_v10_0_get_vm_pte(struct amdgpu_device *adev,
599 struct amdgpu_bo_va_mapping *mapping,
602 *flags &= ~AMDGPU_PTE_EXECUTABLE;
603 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
605 *flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK;
606 *flags |= (mapping->flags & AMDGPU_PTE_MTYPE_NV10_MASK);
608 if (mapping->flags & AMDGPU_PTE_PRT) {
609 *flags |= AMDGPU_PTE_PRT;
610 *flags |= AMDGPU_PTE_SNOOPED;
611 *flags |= AMDGPU_PTE_LOG;
612 *flags |= AMDGPU_PTE_SYSTEM;
613 *flags &= ~AMDGPU_PTE_VALID;
617 static const struct amdgpu_gmc_funcs gmc_v10_0_gmc_funcs = {
618 .flush_gpu_tlb = gmc_v10_0_flush_gpu_tlb,
619 .flush_gpu_tlb_pasid = gmc_v10_0_flush_gpu_tlb_pasid,
620 .emit_flush_gpu_tlb = gmc_v10_0_emit_flush_gpu_tlb,
621 .emit_pasid_mapping = gmc_v10_0_emit_pasid_mapping,
622 .map_mtype = gmc_v10_0_map_mtype,
623 .get_vm_pde = gmc_v10_0_get_vm_pde,
624 .get_vm_pte = gmc_v10_0_get_vm_pte
627 static void gmc_v10_0_set_gmc_funcs(struct amdgpu_device *adev)
629 if (adev->gmc.gmc_funcs == NULL)
630 adev->gmc.gmc_funcs = &gmc_v10_0_gmc_funcs;
633 static int gmc_v10_0_early_init(void *handle)
635 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
637 gmc_v10_0_set_gmc_funcs(adev);
638 gmc_v10_0_set_irq_funcs(adev);
640 adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
641 adev->gmc.shared_aperture_end =
642 adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
643 adev->gmc.private_aperture_start = 0x1000000000000000ULL;
644 adev->gmc.private_aperture_end =
645 adev->gmc.private_aperture_start + (4ULL << 30) - 1;
650 static int gmc_v10_0_late_init(void *handle)
652 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
655 amdgpu_bo_late_init(adev);
657 r = amdgpu_gmc_allocate_vm_inv_eng(adev);
661 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
664 static void gmc_v10_0_vram_gtt_location(struct amdgpu_device *adev,
665 struct amdgpu_gmc *mc)
669 base = gfxhub_v2_0_get_fb_location(adev);
671 amdgpu_gmc_vram_location(adev, &adev->gmc, base);
672 amdgpu_gmc_gart_location(adev, mc);
674 /* base offset of vram pages */
675 adev->vm_manager.vram_base_offset = gfxhub_v2_0_get_mc_fb_offset(adev);
679 * gmc_v10_0_mc_init - initialize the memory controller driver params
681 * @adev: amdgpu_device pointer
683 * Look up the amount of vram, vram width, and decide how to place
684 * vram and gart within the GPU's physical address space.
685 * Returns 0 for success.
687 static int gmc_v10_0_mc_init(struct amdgpu_device *adev)
689 /* Could aper size report 0 ? */
690 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
691 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
693 /* size in MB on si */
694 adev->gmc.mc_vram_size =
695 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL;
696 adev->gmc.real_vram_size = adev->gmc.mc_vram_size;
697 adev->gmc.visible_vram_size = adev->gmc.aper_size;
699 /* In case the PCI BAR is larger than the actual amount of vram */
700 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
701 adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
703 /* set the gart size */
704 if (amdgpu_gart_size == -1) {
705 switch (adev->asic_type) {
710 adev->gmc.gart_size = 512ULL << 20;
714 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
716 gmc_v10_0_vram_gtt_location(adev, &adev->gmc);
721 static int gmc_v10_0_gart_init(struct amdgpu_device *adev)
726 WARN(1, "NAVI10 PCIE GART already initialized\n");
730 /* Initialize common gart structure */
731 r = amdgpu_gart_init(adev);
735 adev->gart.table_size = adev->gart.num_gpu_pages * 8;
736 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(MTYPE_UC) |
737 AMDGPU_PTE_EXECUTABLE;
739 return amdgpu_gart_table_vram_alloc(adev);
742 static unsigned gmc_v10_0_get_vbios_fb_size(struct amdgpu_device *adev)
744 u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);
747 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
748 size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */
753 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);
754 pitch = RREG32_SOC15(DCE, 0, mmHUBPREQ0_DCSURF_SURFACE_PITCH);
755 size = (REG_GET_FIELD(viewport,
756 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
757 REG_GET_FIELD(pitch, HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH) *
760 /* return 0 if the pre-OS buffer uses up most of vram */
761 if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024)) {
762 DRM_ERROR("Warning: pre-OS buffer uses most of vram, \
763 be aware of gart table overwrite\n");
772 static int gmc_v10_0_sw_init(void *handle)
774 int r, vram_width = 0, vram_type = 0, vram_vendor = 0;
775 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
777 gfxhub_v2_0_init(adev);
778 mmhub_v2_0_init(adev);
780 spin_lock_init(&adev->gmc.invalidate_lock);
782 r = amdgpu_atomfirmware_get_vram_info(adev,
783 &vram_width, &vram_type, &vram_vendor);
784 if (!amdgpu_emu_mode)
785 adev->gmc.vram_width = vram_width;
787 adev->gmc.vram_width = 1 * 128; /* numchan * chansize */
789 adev->gmc.vram_type = vram_type;
790 adev->gmc.vram_vendor = vram_vendor;
791 switch (adev->asic_type) {
795 adev->num_vmhubs = 2;
797 * To fulfill 4-level page support,
798 * vm size is 256TB (48bit), maximum size of Navi10/Navi14/Navi12,
799 * block size 512 (9bit)
801 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
807 /* This interrupt is VMC page fault.*/
808 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC,
809 VMC_1_0__SRCID__VM_FAULT,
810 &adev->gmc.vm_fault);
815 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2,
816 UTCL2_1_0__SRCID__FAULT,
817 &adev->gmc.vm_fault);
822 * Set the internal MC address mask This is the max address of the GPU's
823 * internal address space.
825 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
827 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44));
829 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
833 r = gmc_v10_0_mc_init(adev);
837 adev->gmc.stolen_size = gmc_v10_0_get_vbios_fb_size(adev);
840 r = amdgpu_bo_init(adev);
844 r = gmc_v10_0_gart_init(adev);
850 * VMID 0 is reserved for System
851 * amdgpu graphics/compute will use VMIDs 1-7
852 * amdkfd will use VMIDs 8-15
854 adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS;
855 adev->vm_manager.id_mgr[AMDGPU_MMHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS;
857 amdgpu_vm_manager_init(adev);
863 * gmc_v8_0_gart_fini - vm fini callback
865 * @adev: amdgpu_device pointer
867 * Tears down the driver GART/VM setup (CIK).
869 static void gmc_v10_0_gart_fini(struct amdgpu_device *adev)
871 amdgpu_gart_table_vram_free(adev);
872 amdgpu_gart_fini(adev);
875 static int gmc_v10_0_sw_fini(void *handle)
877 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
879 amdgpu_vm_manager_fini(adev);
880 gmc_v10_0_gart_fini(adev);
881 amdgpu_gem_force_release(adev);
882 amdgpu_bo_fini(adev);
887 static void gmc_v10_0_init_golden_registers(struct amdgpu_device *adev)
889 switch (adev->asic_type) {
900 * gmc_v10_0_gart_enable - gart enable
902 * @adev: amdgpu_device pointer
904 static int gmc_v10_0_gart_enable(struct amdgpu_device *adev)
910 if (adev->gart.bo == NULL) {
911 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
915 r = amdgpu_gart_table_vram_pin(adev);
919 r = gfxhub_v2_0_gart_enable(adev);
923 r = mmhub_v2_0_gart_enable(adev);
927 tmp = RREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL);
928 tmp |= HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK;
929 WREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL, tmp);
931 tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL);
932 WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp);
934 /* Flush HDP after it is initialized */
935 adev->nbio.funcs->hdp_flush(adev, NULL);
937 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ?
940 gfxhub_v2_0_set_fault_enable_default(adev, value);
941 mmhub_v2_0_set_fault_enable_default(adev, value);
942 gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB_0, 0);
943 gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB_0, 0);
945 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
946 (unsigned)(adev->gmc.gart_size >> 20),
947 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo));
949 adev->gart.ready = true;
954 static int gmc_v10_0_hw_init(void *handle)
957 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
959 /* The sequence of these two function calls matters.*/
960 gmc_v10_0_init_golden_registers(adev);
962 r = gmc_v10_0_gart_enable(adev);
970 * gmc_v10_0_gart_disable - gart disable
972 * @adev: amdgpu_device pointer
974 * This disables all VM page table.
976 static void gmc_v10_0_gart_disable(struct amdgpu_device *adev)
978 gfxhub_v2_0_gart_disable(adev);
979 mmhub_v2_0_gart_disable(adev);
980 amdgpu_gart_table_vram_unpin(adev);
983 static int gmc_v10_0_hw_fini(void *handle)
985 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
987 if (amdgpu_sriov_vf(adev)) {
988 /* full access mode, so don't touch any GMC register */
989 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
993 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
994 gmc_v10_0_gart_disable(adev);
999 static int gmc_v10_0_suspend(void *handle)
1001 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1003 gmc_v10_0_hw_fini(adev);
1008 static int gmc_v10_0_resume(void *handle)
1011 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1013 r = gmc_v10_0_hw_init(adev);
1017 amdgpu_vmid_reset_all(adev);
1022 static bool gmc_v10_0_is_idle(void *handle)
1024 /* MC is always ready in GMC v10.*/
1028 static int gmc_v10_0_wait_for_idle(void *handle)
1030 /* There is no need to wait for MC idle in GMC v10.*/
1034 static int gmc_v10_0_soft_reset(void *handle)
1039 static int gmc_v10_0_set_clockgating_state(void *handle,
1040 enum amd_clockgating_state state)
1043 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1045 r = mmhub_v2_0_set_clockgating(adev, state);
1049 return athub_v2_0_set_clockgating(adev, state);
1052 static void gmc_v10_0_get_clockgating_state(void *handle, u32 *flags)
1054 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1056 mmhub_v2_0_get_clockgating(adev, flags);
1058 athub_v2_0_get_clockgating(adev, flags);
1061 static int gmc_v10_0_set_powergating_state(void *handle,
1062 enum amd_powergating_state state)
1067 const struct amd_ip_funcs gmc_v10_0_ip_funcs = {
1068 .name = "gmc_v10_0",
1069 .early_init = gmc_v10_0_early_init,
1070 .late_init = gmc_v10_0_late_init,
1071 .sw_init = gmc_v10_0_sw_init,
1072 .sw_fini = gmc_v10_0_sw_fini,
1073 .hw_init = gmc_v10_0_hw_init,
1074 .hw_fini = gmc_v10_0_hw_fini,
1075 .suspend = gmc_v10_0_suspend,
1076 .resume = gmc_v10_0_resume,
1077 .is_idle = gmc_v10_0_is_idle,
1078 .wait_for_idle = gmc_v10_0_wait_for_idle,
1079 .soft_reset = gmc_v10_0_soft_reset,
1080 .set_clockgating_state = gmc_v10_0_set_clockgating_state,
1081 .set_powergating_state = gmc_v10_0_set_powergating_state,
1082 .get_clockgating_state = gmc_v10_0_get_clockgating_state,
1085 const struct amdgpu_ip_block_version gmc_v10_0_ip_block =
1087 .type = AMD_IP_BLOCK_TYPE_GMC,
1091 .funcs = &gmc_v10_0_ip_funcs,