drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include "drmP.h"
  25 #include "amdgpu.h"
  26 #include "amdgpu_gfx.h"
  27 #include "vi.h"
  28 #include "vid.h"
  29 #include "amdgpu_ucode.h"
  30 #include "clearstate_vi.h"
  31
  32 #include "gmc/gmc_8_2_d.h"
  33 #include "gmc/gmc_8_2_sh_mask.h"
  34
  35 #include "oss/oss_3_0_d.h"
  36 #include "oss/oss_3_0_sh_mask.h"
  37
  38 #include "bif/bif_5_0_d.h"
  39 #include "bif/bif_5_0_sh_mask.h"
  40
  41 #include "gca/gfx_8_0_d.h"
  42 #include "gca/gfx_8_0_enum.h"
  43 #include "gca/gfx_8_0_sh_mask.h"
  44 #include "gca/gfx_8_0_enum.h"
  45
  46 #include "uvd/uvd_5_0_d.h"
  47 #include "uvd/uvd_5_0_sh_mask.h"
  48
  49 #include "dce/dce_10_0_d.h"
  50 #include "dce/dce_10_0_sh_mask.h"
  51
  52 #define GFX8_NUM_GFX_RINGS     1
  53 #define GFX8_NUM_COMPUTE_RINGS 8
  54
  55 #define TOPAZ_GB_ADDR_CONFIG_GOLDEN 0x22010001
  56 #define CARRIZO_GB_ADDR_CONFIG_GOLDEN 0x22010001
  57 #define TONGA_GB_ADDR_CONFIG_GOLDEN 0x22011003
  58
  59 #define ARRAY_MODE(x)                                   ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT)
  60 #define PIPE_CONFIG(x)                                  ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT)
  61 #define TILE_SPLIT(x)                                   ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT)
  62 #define MICRO_TILE_MODE_NEW(x)                          ((x) << GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT)
  63 #define SAMPLE_SPLIT(x)                                 ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT)
  64 #define BANK_WIDTH(x)                                   ((x) << GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT)
  65 #define BANK_HEIGHT(x)                                  ((x) << GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT)
  66 #define MACRO_TILE_ASPECT(x)                            ((x) << GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT)
  67 #define NUM_BANKS(x)                                    ((x) << GB_MACROTILE_MODE0__NUM_BANKS__SHIFT)
  68
  69 MODULE_FIRMWARE("amdgpu/carrizo_ce.bin");
  70 MODULE_FIRMWARE("amdgpu/carrizo_pfp.bin");
  71 MODULE_FIRMWARE("amdgpu/carrizo_me.bin");
  72 MODULE_FIRMWARE("amdgpu/carrizo_mec.bin");
  73 MODULE_FIRMWARE("amdgpu/carrizo_mec2.bin");
  74 MODULE_FIRMWARE("amdgpu/carrizo_rlc.bin");
  75
  76 MODULE_FIRMWARE("amdgpu/tonga_ce.bin");
  77 MODULE_FIRMWARE("amdgpu/tonga_pfp.bin");
  78 MODULE_FIRMWARE("amdgpu/tonga_me.bin");
  79 MODULE_FIRMWARE("amdgpu/tonga_mec.bin");
  80 MODULE_FIRMWARE("amdgpu/tonga_mec2.bin");
  81 MODULE_FIRMWARE("amdgpu/tonga_rlc.bin");
  82
  83 MODULE_FIRMWARE("amdgpu/topaz_ce.bin");
  84 MODULE_FIRMWARE("amdgpu/topaz_pfp.bin");
  85 MODULE_FIRMWARE("amdgpu/topaz_me.bin");
  86 MODULE_FIRMWARE("amdgpu/topaz_mec.bin");
  87 MODULE_FIRMWARE("amdgpu/topaz_mec2.bin");
  88 MODULE_FIRMWARE("amdgpu/topaz_rlc.bin");
  89
  90 MODULE_FIRMWARE("amdgpu/fiji_ce.bin");
  91 MODULE_FIRMWARE("amdgpu/fiji_pfp.bin");
  92 MODULE_FIRMWARE("amdgpu/fiji_me.bin");
  93 MODULE_FIRMWARE("amdgpu/fiji_mec.bin");
  94 MODULE_FIRMWARE("amdgpu/fiji_mec2.bin");
  95 MODULE_FIRMWARE("amdgpu/fiji_rlc.bin");
  96
  97 static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
  98 {
  99         {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
 100         {mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1},
 101         {mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2},
 102         {mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3},
 103         {mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4},
 104         {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5},
 105         {mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6},
 106         {mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7},
 107         {mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8},
 108         {mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9},
 109         {mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10},
 110         {mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11},
 111         {mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12},
 112         {mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13},
 113         {mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14},
 114         {mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15}
 115 };
 116
 117 static const u32 golden_settings_tonga_a11[] =
 118 {
 119         mmCB_HW_CONTROL, 0xfffdf3cf, 0x00007208,
 120         mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
 121         mmDB_DEBUG2, 0xf00fffff, 0x00000400,
 122         mmGB_GPU_ID, 0x0000000f, 0x00000000,
 123         mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
 124         mmPA_SC_FIFO_DEPTH_CNTL, 0x000003ff, 0x000000fc,
 125         mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
 126         mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
 127         mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
 128         mmTCC_CTRL, 0x00100000, 0xf31fff7f,
 129         mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
 130         mmTCP_ADDR_CONFIG, 0x000003ff, 0x000002fb,
 131         mmTCP_CHAN_STEER_HI, 0xffffffff, 0x0000543b,
 132         mmTCP_CHAN_STEER_LO, 0xffffffff, 0xa9210876,
 133         mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
 134 };
 135
 136 static const u32 tonga_golden_common_all[] =
 137 {
 138         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 139         mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012,
 140         mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002A,
 141         mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
 142         mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
 143         mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
 144         mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
 145         mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
 146 };
 147
 148 static const u32 tonga_mgcg_cgcg_init[] =
 149 {
 150         mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
 151         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 152         mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 153         mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
 154         mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
 155         mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
 156         mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
 157         mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
 158         mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
 159         mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
 160         mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
 161         mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
 162         mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
 163         mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
 164         mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
 165         mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
 166         mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
 167         mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
 168         mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
 169         mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
 170         mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
 171         mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
 172         mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
 173         mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
 174         mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
 175         mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
 176         mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
 177         mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 178         mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 179         mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
 180         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 181         mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 182         mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 183         mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
 184         mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 185         mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 186         mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 187         mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 188         mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
 189         mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 190         mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 191         mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 192         mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 193         mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
 194         mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 195         mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 196         mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 197         mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 198         mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
 199         mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 200         mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 201         mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 202         mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 203         mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
 204         mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 205         mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 206         mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 207         mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 208         mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
 209         mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 210         mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 211         mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 212         mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 213         mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
 214         mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 215         mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 216         mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 217         mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 218         mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
 219         mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 220         mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 221         mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
 222         mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
 223         mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
 224         mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
 225 };
 226
 227 static const u32 fiji_golden_common_all[] =
 228 {
 229         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 230         mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x3a00161a,
 231         mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002e,
 232         mmGB_ADDR_CONFIG, 0xffffffff, 0x12011003,
 233         mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
 234         mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
 235         mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
 236         mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
 237 };
 238
 239 static const u32 golden_settings_fiji_a10[] =
 240 {
 241         mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
 242         mmDB_DEBUG2, 0xf00fffff, 0x00000400,
 243         mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
 244         mmPA_SC_FIFO_DEPTH_CNTL, 0x000003ff, 0x00000100,
 245         mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
 246         mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
 247         mmTCC_CTRL, 0x00100000, 0xf30fff7f,
 248         mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000ff,
 249         mmTCP_CHAN_STEER_HI, 0xffffffff, 0x7d6cf5e4,
 250         mmTCP_CHAN_STEER_LO, 0xffffffff, 0x3928b1a0,
 251 };
 252
 253 static const u32 fiji_mgcg_cgcg_init[] =
 254 {
 255         mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffc0,
 256         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 257         mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 258         mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
 259         mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
 260         mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
 261         mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
 262         mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
 263         mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
 264         mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
 265         mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
 266         mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
 267         mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
 268         mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
 269         mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
 270         mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
 271         mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
 272         mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
 273         mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
 274         mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
 275         mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
 276         mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
 277         mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
 278         mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
 279         mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
 280         mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
 281         mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
 282         mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 283         mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 284         mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
 285         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 286         mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
 287         mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
 288         mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
 289         mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
 290 };
 291
 292 static const u32 golden_settings_iceland_a11[] =
 293 {
 294         mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
 295         mmDB_DEBUG2, 0xf00fffff, 0x00000400,
 296         mmDB_DEBUG3, 0xc0000000, 0xc0000000,
 297         mmGB_GPU_ID, 0x0000000f, 0x00000000,
 298         mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
 299         mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
 300         mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x00000002,
 301         mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000,
 302         mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
 303         mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
 304         mmTCC_CTRL, 0x00100000, 0xf31fff7f,
 305         mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
 306         mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f1,
 307         mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
 308         mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010,
 309 };
 310
 311 static const u32 iceland_golden_common_all[] =
 312 {
 313         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 314         mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
 315         mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
 316         mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
 317         mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
 318         mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
 319         mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
 320         mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
 321 };
 322
 323 static const u32 iceland_mgcg_cgcg_init[] =
 324 {
 325         mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
 326         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 327         mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 328         mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
 329         mmCGTT_CP_CLK_CTRL, 0xffffffff, 0xc0000100,
 330         mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0xc0000100,
 331         mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0xc0000100,
 332         mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
 333         mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
 334         mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
 335         mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
 336         mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
 337         mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
 338         mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
 339         mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
 340         mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
 341         mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
 342         mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
 343         mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
 344         mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
 345         mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
 346         mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
 347         mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0xff000100,
 348         mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
 349         mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
 350         mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
 351         mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
 352         mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 353         mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 354         mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
 355         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 356         mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 357         mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 358         mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
 359         mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 360         mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 361         mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 362         mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 363         mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
 364         mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 365         mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 366         mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 367         mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 368         mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
 369         mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 370         mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 371         mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 372         mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 373         mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
 374         mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 375         mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 376         mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 377         mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 378         mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
 379         mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 380         mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 381         mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 382         mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 383         mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
 384         mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 385         mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 386         mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
 387         mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
 388         mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
 389 };
 390
 391 static const u32 cz_golden_settings_a11[] =
 392 {
 393         mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
 394         mmDB_DEBUG2, 0xf00fffff, 0x00000400,
 395         mmGB_GPU_ID, 0x0000000f, 0x00000000,
 396         mmPA_SC_ENHANCE, 0xffffffff, 0x00000001,
 397         mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
 398         mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
 399         mmTA_CNTL_AUX, 0x000f000f, 0x00010000,
 400         mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
 401         mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f3,
 402         mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00001302
 403 };
 404
 405 static const u32 cz_golden_common_all[] =
 406 {
 407         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 408         mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
 409         mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
 410         mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
 411         mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
 412         mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
 413         mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
 414         mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
 415 };
 416
 417 static const u32 cz_mgcg_cgcg_init[] =
 418 {
 419         mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
 420         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 421         mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 422         mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
 423         mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
 424         mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
 425         mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x00000100,
 426         mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
 427         mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
 428         mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
 429         mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
 430         mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
 431         mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
 432         mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
 433         mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
 434         mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
 435         mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
 436         mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
 437         mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
 438         mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
 439         mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
 440         mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
 441         mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
 442         mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
 443         mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
 444         mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
 445         mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
 446         mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 447         mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 448         mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
 449         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 450         mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 451         mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 452         mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
 453         mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 454         mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 455         mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 456         mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 457         mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
 458         mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 459         mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 460         mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 461         mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 462         mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
 463         mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 464         mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 465         mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 466         mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 467         mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
 468         mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 469         mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 470         mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 471         mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 472         mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
 473         mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 474         mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 475         mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 476         mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 477         mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
 478         mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 479         mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 480         mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 481         mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 482         mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
 483         mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 484         mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 485         mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 486         mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 487         mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
 488         mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 489         mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 490         mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
 491         mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
 492         mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
 493         mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
 494 };
 495
 496 static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev);
 497 static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev);
 498 static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev);
 499
 500 static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev)
 501 {
 502         switch (adev->asic_type) {
 503         case CHIP_TOPAZ:
 504                 amdgpu_program_register_sequence(adev,
 505                                                  iceland_mgcg_cgcg_init,
 506                                                  (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
 507                 amdgpu_program_register_sequence(adev,
 508                                                  golden_settings_iceland_a11,
 509                                                  (const u32)ARRAY_SIZE(golden_settings_iceland_a11));
 510                 amdgpu_program_register_sequence(adev,
 511                                                  iceland_golden_common_all,
 512                                                  (const u32)ARRAY_SIZE(iceland_golden_common_all));
 513                 break;
 514         case CHIP_FIJI:
 515                 amdgpu_program_register_sequence(adev,
 516                                                  fiji_mgcg_cgcg_init,
 517                                                  (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
 518                 amdgpu_program_register_sequence(adev,
 519                                                  golden_settings_fiji_a10,
 520                                                  (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
 521                 amdgpu_program_register_sequence(adev,
 522                                                  fiji_golden_common_all,
 523                                                  (const u32)ARRAY_SIZE(fiji_golden_common_all));
 524                 break;
 525
 526         case CHIP_TONGA:
 527                 amdgpu_program_register_sequence(adev,
 528                                                  tonga_mgcg_cgcg_init,
 529                                                  (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
 530                 amdgpu_program_register_sequence(adev,
 531                                                  golden_settings_tonga_a11,
 532                                                  (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
 533                 amdgpu_program_register_sequence(adev,
 534                                                  tonga_golden_common_all,
 535                                                  (const u32)ARRAY_SIZE(tonga_golden_common_all));
 536                 break;
 537         case CHIP_CARRIZO:
 538                 amdgpu_program_register_sequence(adev,
 539                                                  cz_mgcg_cgcg_init,
 540                                                  (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
 541                 amdgpu_program_register_sequence(adev,
 542                                                  cz_golden_settings_a11,
 543                                                  (const u32)ARRAY_SIZE(cz_golden_settings_a11));
 544                 amdgpu_program_register_sequence(adev,
 545                                                  cz_golden_common_all,
 546                                                  (const u32)ARRAY_SIZE(cz_golden_common_all));
 547                 break;
 548         default:
 549                 break;
 550         }
 551 }
 552
 553 static void gfx_v8_0_scratch_init(struct amdgpu_device *adev)
 554 {
 555         int i;
 556
 557         adev->gfx.scratch.num_reg = 7;
 558         adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
 559         for (i = 0; i < adev->gfx.scratch.num_reg; i++) {
 560                 adev->gfx.scratch.free[i] = true;
 561                 adev->gfx.scratch.reg[i] = adev->gfx.scratch.reg_base + i;
 562         }
 563 }
 564
 565 static int gfx_v8_0_ring_test_ring(struct amdgpu_ring *ring)
 566 {
 567         struct amdgpu_device *adev = ring->adev;
 568         uint32_t scratch;
 569         uint32_t tmp = 0;
 570         unsigned i;
 571         int r;
 572
 573         r = amdgpu_gfx_scratch_get(adev, &scratch);
 574         if (r) {
 575                 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
 576                 return r;
 577         }
 578         WREG32(scratch, 0xCAFEDEAD);
 579         r = amdgpu_ring_lock(ring, 3);
 580         if (r) {
 581                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
 582                           ring->idx, r);
 583                 amdgpu_gfx_scratch_free(adev, scratch);
 584                 return r;
 585         }
 586         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
 587         amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
 588         amdgpu_ring_write(ring, 0xDEADBEEF);
 589         amdgpu_ring_unlock_commit(ring);
 590
 591         for (i = 0; i < adev->usec_timeout; i++) {
 592                 tmp = RREG32(scratch);
 593                 if (tmp == 0xDEADBEEF)
 594                         break;
 595                 DRM_UDELAY(1);
 596         }
 597         if (i < adev->usec_timeout) {
 598                 DRM_INFO("ring test on %d succeeded in %d usecs\n",
 599                          ring->idx, i);
 600         } else {
 601                 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
 602                           ring->idx, scratch, tmp);
 603                 r = -EINVAL;
 604         }
 605         amdgpu_gfx_scratch_free(adev, scratch);
 606         return r;
 607 }
 608
 609 static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring)
 610 {
 611         struct amdgpu_device *adev = ring->adev;
 612         struct amdgpu_ib ib;
 613         struct fence *f = NULL;
 614         uint32_t scratch;
 615         uint32_t tmp = 0;
 616         unsigned i;
 617         int r;
 618
 619         r = amdgpu_gfx_scratch_get(adev, &scratch);
 620         if (r) {
 621                 DRM_ERROR("amdgpu: failed to get scratch reg (%d).\n", r);
 622                 return r;
 623         }
 624         WREG32(scratch, 0xCAFEDEAD);
 625         memset(&ib, 0, sizeof(ib));
 626         r = amdgpu_ib_get(ring, NULL, 256, &ib);
 627         if (r) {
 628                 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
 629                 goto err1;
 630         }
 631         ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
 632         ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
 633         ib.ptr[2] = 0xDEADBEEF;
 634         ib.length_dw = 3;
 635
 636         r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, &ib, 1, NULL,
 637                                                  AMDGPU_FENCE_OWNER_UNDEFINED,
 638                                                  &f);
 639         if (r)
 640                 goto err2;
 641
 642         r = fence_wait(f, false);
 643         if (r) {
 644                 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
 645                 goto err2;
 646         }
 647         for (i = 0; i < adev->usec_timeout; i++) {
 648                 tmp = RREG32(scratch);
 649                 if (tmp == 0xDEADBEEF)
 650                         break;
 651                 DRM_UDELAY(1);
 652         }
 653         if (i < adev->usec_timeout) {
 654                 DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
 655                          ring->idx, i);
 656                 goto err2;
 657         } else {
 658                 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
 659                           scratch, tmp);
 660                 r = -EINVAL;
 661         }
 662 err2:
 663         fence_put(f);
 664         amdgpu_ib_free(adev, &ib);
 665 err1:
 666         amdgpu_gfx_scratch_free(adev, scratch);
 667         return r;
 668 }
 669
 670 static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
 671 {
 672         const char *chip_name;
 673         char fw_name[30];
 674         int err;
 675         struct amdgpu_firmware_info *info = NULL;
 676         const struct common_firmware_header *header = NULL;
 677         const struct gfx_firmware_header_v1_0 *cp_hdr;
 678
 679         DRM_DEBUG("\n");
 680
 681         switch (adev->asic_type) {
 682         case CHIP_TOPAZ:
 683                 chip_name = "topaz";
 684                 break;
 685         case CHIP_TONGA:
 686                 chip_name = "tonga";
 687                 break;
 688         case CHIP_CARRIZO:
 689                 chip_name = "carrizo";
 690                 break;
 691         case CHIP_FIJI:
 692                 chip_name = "fiji";
 693                 break;
 694         default:
 695                 BUG();
 696         }
 697
 698         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
 699         err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
 700         if (err)
 701                 goto out;
 702         err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
 703         if (err)
 704                 goto out;
 705         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
 706         adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 707         adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 708
 709         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
 710         err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
 711         if (err)
 712                 goto out;
 713         err = amdgpu_ucode_validate(adev->gfx.me_fw);
 714         if (err)
 715                 goto out;
 716         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
 717         adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 718         adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 719
 720         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
 721         err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
 722         if (err)
 723                 goto out;
 724         err = amdgpu_ucode_validate(adev->gfx.ce_fw);
 725         if (err)
 726                 goto out;
 727         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
 728         adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 729         adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 730
 731         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
 732         err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
 733         if (err)
 734                 goto out;
 735         err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
 736         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
 737         adev->gfx.rlc_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 738         adev->gfx.rlc_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 739
 740         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
 741         err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
 742         if (err)
 743                 goto out;
 744         err = amdgpu_ucode_validate(adev->gfx.mec_fw);
 745         if (err)
 746                 goto out;
 747         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
 748         adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 749         adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 750
 751         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
 752         err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
 753         if (!err) {
 754                 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
 755                 if (err)
 756                         goto out;
 757                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
 758                                                 adev->gfx.mec2_fw->data;
 759                 adev->gfx.mec2_fw_version = le32_to_cpu(
 760                                                 cp_hdr->header.ucode_version);
 761                 adev->gfx.mec2_feature_version = le32_to_cpu(
 762                                                 cp_hdr->ucode_feature_version);
 763         } else {
 764                 err = 0;
 765                 adev->gfx.mec2_fw = NULL;
 766         }
 767
 768         if (adev->firmware.smu_load) {
 769                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
 770                 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
 771                 info->fw = adev->gfx.pfp_fw;
 772                 header = (const struct common_firmware_header *)info->fw->data;
 773                 adev->firmware.fw_size +=
 774                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 775
 776                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
 777                 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
 778                 info->fw = adev->gfx.me_fw;
 779                 header = (const struct common_firmware_header *)info->fw->data;
 780                 adev->firmware.fw_size +=
 781                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 782
 783                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
 784                 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
 785                 info->fw = adev->gfx.ce_fw;
 786                 header = (const struct common_firmware_header *)info->fw->data;
 787                 adev->firmware.fw_size +=
 788                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 789
 790                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
 791                 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
 792                 info->fw = adev->gfx.rlc_fw;
 793                 header = (const struct common_firmware_header *)info->fw->data;
 794                 adev->firmware.fw_size +=
 795                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 796
 797                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
 798                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
 799                 info->fw = adev->gfx.mec_fw;
 800                 header = (const struct common_firmware_header *)info->fw->data;
 801                 adev->firmware.fw_size +=
 802                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 803
 804                 if (adev->gfx.mec2_fw) {
 805                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
 806                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
 807                         info->fw = adev->gfx.mec2_fw;
 808                         header = (const struct common_firmware_header *)info->fw->data;
 809                         adev->firmware.fw_size +=
 810                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 811                 }
 812
 813         }
 814
 815 out:
 816         if (err) {
 817                 dev_err(adev->dev,
 818                         "gfx8: Failed to load firmware \"%s\"\n",
 819                         fw_name);
 820                 release_firmware(adev->gfx.pfp_fw);
 821                 adev->gfx.pfp_fw = NULL;
 822                 release_firmware(adev->gfx.me_fw);
 823                 adev->gfx.me_fw = NULL;
 824                 release_firmware(adev->gfx.ce_fw);
 825                 adev->gfx.ce_fw = NULL;
 826                 release_firmware(adev->gfx.rlc_fw);
 827                 adev->gfx.rlc_fw = NULL;
 828                 release_firmware(adev->gfx.mec_fw);
 829                 adev->gfx.mec_fw = NULL;
 830                 release_firmware(adev->gfx.mec2_fw);
 831                 adev->gfx.mec2_fw = NULL;
 832         }
 833         return err;
 834 }
 835
 836 static void gfx_v8_0_mec_fini(struct amdgpu_device *adev)
 837 {
 838         int r;
 839
 840         if (adev->gfx.mec.hpd_eop_obj) {
 841                 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
 842                 if (unlikely(r != 0))
 843                         dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r);
 844                 amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj);
 845                 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
 846
 847                 amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj);
 848                 adev->gfx.mec.hpd_eop_obj = NULL;
 849         }
 850 }
 851
 852 #define MEC_HPD_SIZE 2048
 853
 854 static int gfx_v8_0_mec_init(struct amdgpu_device *adev)
 855 {
 856         int r;
 857         u32 *hpd;
 858
 859         /*
 860          * we assign only 1 pipe because all other pipes will
 861          * be handled by KFD
 862          */
 863         adev->gfx.mec.num_mec = 1;
 864         adev->gfx.mec.num_pipe = 1;
 865         adev->gfx.mec.num_queue = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * 8;
 866
 867         if (adev->gfx.mec.hpd_eop_obj == NULL) {
 868                 r = amdgpu_bo_create(adev,
 869                                      adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2,
 870                                      PAGE_SIZE, true,
 871                                      AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
 872                                      &adev->gfx.mec.hpd_eop_obj);
 873                 if (r) {
 874                         dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
 875                         return r;
 876                 }
 877         }
 878
 879         r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
 880         if (unlikely(r != 0)) {
 881                 gfx_v8_0_mec_fini(adev);
 882                 return r;
 883         }
 884         r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT,
 885                           &adev->gfx.mec.hpd_eop_gpu_addr);
 886         if (r) {
 887                 dev_warn(adev->dev, "(%d) pin HDP EOP bo failed\n", r);
 888                 gfx_v8_0_mec_fini(adev);
 889                 return r;
 890         }
 891         r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd);
 892         if (r) {
 893                 dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r);
 894                 gfx_v8_0_mec_fini(adev);
 895                 return r;
 896         }
 897
 898         memset(hpd, 0, adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2);
 899
 900         amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
 901         amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
 902
 903         return 0;
 904 }
 905
 906 static void gfx_v8_0_gpu_early_init(struct amdgpu_device *adev)
 907 {
 908         u32 gb_addr_config;
 909         u32 mc_shared_chmap, mc_arb_ramcfg;
 910         u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
 911         u32 tmp;
 912
 913         switch (adev->asic_type) {
 914         case CHIP_TOPAZ:
 915                 adev->gfx.config.max_shader_engines = 1;
 916                 adev->gfx.config.max_tile_pipes = 2;
 917                 adev->gfx.config.max_cu_per_sh = 6;
 918                 adev->gfx.config.max_sh_per_se = 1;
 919                 adev->gfx.config.max_backends_per_se = 2;
 920                 adev->gfx.config.max_texture_channel_caches = 2;
 921                 adev->gfx.config.max_gprs = 256;
 922                 adev->gfx.config.max_gs_threads = 32;
 923                 adev->gfx.config.max_hw_contexts = 8;
 924
 925                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
 926                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
 927                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
 928                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
 929                 gb_addr_config = TOPAZ_GB_ADDR_CONFIG_GOLDEN;
 930                 break;
 931         case CHIP_FIJI:
 932                 adev->gfx.config.max_shader_engines = 4;
 933                 adev->gfx.config.max_tile_pipes = 16;
 934                 adev->gfx.config.max_cu_per_sh = 16;
 935                 adev->gfx.config.max_sh_per_se = 1;
 936                 adev->gfx.config.max_backends_per_se = 4;
 937                 adev->gfx.config.max_texture_channel_caches = 8;
 938                 adev->gfx.config.max_gprs = 256;
 939                 adev->gfx.config.max_gs_threads = 32;
 940                 adev->gfx.config.max_hw_contexts = 8;
 941
 942                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
 943                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
 944                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
 945                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
 946                 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
 947                 break;
 948         case CHIP_TONGA:
 949                 adev->gfx.config.max_shader_engines = 4;
 950                 adev->gfx.config.max_tile_pipes = 8;
 951                 adev->gfx.config.max_cu_per_sh = 8;
 952                 adev->gfx.config.max_sh_per_se = 1;
 953                 adev->gfx.config.max_backends_per_se = 2;
 954                 adev->gfx.config.max_texture_channel_caches = 8;
 955                 adev->gfx.config.max_gprs = 256;
 956                 adev->gfx.config.max_gs_threads = 32;
 957                 adev->gfx.config.max_hw_contexts = 8;
 958
 959                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
 960                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
 961                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
 962                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
 963                 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
 964                 break;
 965         case CHIP_CARRIZO:
 966                 adev->gfx.config.max_shader_engines = 1;
 967                 adev->gfx.config.max_tile_pipes = 2;
 968                 adev->gfx.config.max_sh_per_se = 1;
 969                 adev->gfx.config.max_backends_per_se = 2;
 970
 971                 switch (adev->pdev->revision) {
 972                 case 0xc4:
 973                 case 0x84:
 974                 case 0xc8:
 975                 case 0xcc:
 976                         /* B10 */
 977                         adev->gfx.config.max_cu_per_sh = 8;
 978                         break;
 979                 case 0xc5:
 980                 case 0x81:
 981                 case 0x85:
 982                 case 0xc9:
 983                 case 0xcd:
 984                         /* B8 */
 985                         adev->gfx.config.max_cu_per_sh = 6;
 986                         break;
 987                 case 0xc6:
 988                 case 0xca:
 989                 case 0xce:
 990                         /* B6 */
 991                         adev->gfx.config.max_cu_per_sh = 6;
 992                         break;
 993                 case 0xc7:
 994                 case 0x87:
 995                 case 0xcb:
 996                 default:
 997                         /* B4 */
 998                         adev->gfx.config.max_cu_per_sh = 4;
 999                         break;
1000                 }
1001
1002                 adev->gfx.config.max_texture_channel_caches = 2;
1003                 adev->gfx.config.max_gprs = 256;
1004                 adev->gfx.config.max_gs_threads = 32;
1005                 adev->gfx.config.max_hw_contexts = 8;
1006
1007                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1008                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1009                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1010                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1011                 gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN;
1012                 break;
1013         default:
1014                 adev->gfx.config.max_shader_engines = 2;
1015                 adev->gfx.config.max_tile_pipes = 4;
1016                 adev->gfx.config.max_cu_per_sh = 2;
1017                 adev->gfx.config.max_sh_per_se = 1;
1018                 adev->gfx.config.max_backends_per_se = 2;
1019                 adev->gfx.config.max_texture_channel_caches = 4;
1020                 adev->gfx.config.max_gprs = 256;
1021                 adev->gfx.config.max_gs_threads = 32;
1022                 adev->gfx.config.max_hw_contexts = 8;
1023
1024                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1025                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1026                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1027                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1028                 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1029                 break;
1030         }
1031
1032         mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
1033         adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
1034         mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
1035
1036         adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
1037         adev->gfx.config.mem_max_burst_length_bytes = 256;
1038         if (adev->flags & AMD_IS_APU) {
1039                 /* Get memory bank mapping mode. */
1040                 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
1041                 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
1042                 dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
1043
1044                 tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
1045                 dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
1046                 dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
1047
1048                 /* Validate settings in case only one DIMM installed. */
1049                 if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12))
1050                         dimm00_addr_map = 0;
1051                 if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12))
1052                         dimm01_addr_map = 0;
1053                 if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12))
1054                         dimm10_addr_map = 0;
1055                 if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12))
1056                         dimm11_addr_map = 0;
1057
1058                 /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */
1059                 /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */
1060                 if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11))
1061                         adev->gfx.config.mem_row_size_in_kb = 2;
1062                 else
1063                         adev->gfx.config.mem_row_size_in_kb = 1;
1064         } else {
1065                 tmp = REG_GET_FIELD(mc_arb_ramcfg, MC_ARB_RAMCFG, NOOFCOLS);
1066                 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
1067                 if (adev->gfx.config.mem_row_size_in_kb > 4)
1068                         adev->gfx.config.mem_row_size_in_kb = 4;
1069         }
1070
1071         adev->gfx.config.shader_engine_tile_size = 32;
1072         adev->gfx.config.num_gpus = 1;
1073         adev->gfx.config.multi_gpu_tile_size = 64;
1074
1075         /* fix up row size */
1076         switch (adev->gfx.config.mem_row_size_in_kb) {
1077         case 1:
1078         default:
1079                 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 0);
1080                 break;
1081         case 2:
1082                 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 1);
1083                 break;
1084         case 4:
1085                 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 2);
1086                 break;
1087         }
1088         adev->gfx.config.gb_addr_config = gb_addr_config;
1089 }
1090
1091 static int gfx_v8_0_sw_init(void *handle)
1092 {
1093         int i, r;
1094         struct amdgpu_ring *ring;
1095         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1096
1097         /* EOP Event */
1098         r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq);
1099         if (r)
1100                 return r;
1101
1102         /* Privileged reg */
1103         r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq);
1104         if (r)
1105                 return r;
1106
1107         /* Privileged inst */
1108         r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq);
1109         if (r)
1110                 return r;
1111
1112         adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
1113
1114         gfx_v8_0_scratch_init(adev);
1115
1116         r = gfx_v8_0_init_microcode(adev);
1117         if (r) {
1118                 DRM_ERROR("Failed to load gfx firmware!\n");
1119                 return r;
1120         }
1121
1122         r = gfx_v8_0_mec_init(adev);
1123         if (r) {
1124                 DRM_ERROR("Failed to init MEC BOs!\n");
1125                 return r;
1126         }
1127
1128         /* set up the gfx ring */
1129         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
1130                 ring = &adev->gfx.gfx_ring[i];
1131                 ring->ring_obj = NULL;
1132                 sprintf(ring->name, "gfx");
1133                 /* no gfx doorbells on iceland */
1134                 if (adev->asic_type != CHIP_TOPAZ) {
1135                         ring->use_doorbell = true;
1136                         ring->doorbell_index = AMDGPU_DOORBELL_GFX_RING0;
1137                 }
1138
1139                 r = amdgpu_ring_init(adev, ring, 1024 * 1024,
1140                                      PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
1141                                      &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP,
1142                                      AMDGPU_RING_TYPE_GFX);
1143                 if (r)
1144                         return r;
1145         }
1146
1147         /* set up the compute queues */
1148         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
1149                 unsigned irq_type;
1150
1151                 /* max 32 queues per MEC */
1152                 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) {
1153                         DRM_ERROR("Too many (%d) compute rings!\n", i);
1154                         break;
1155                 }
1156                 ring = &adev->gfx.compute_ring[i];
1157                 ring->ring_obj = NULL;
1158                 ring->use_doorbell = true;
1159                 ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + i;
1160                 ring->me = 1; /* first MEC */
1161                 ring->pipe = i / 8;
1162                 ring->queue = i % 8;
1163                 sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, ring->queue);
1164                 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
1165                 /* type-2 packets are deprecated on MEC, use type-3 instead */
1166                 r = amdgpu_ring_init(adev, ring, 1024 * 1024,
1167                                      PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
1168                                      &adev->gfx.eop_irq, irq_type,
1169                                      AMDGPU_RING_TYPE_COMPUTE);
1170                 if (r)
1171                         return r;
1172         }
1173
1174         /* reserve GDS, GWS and OA resource for gfx */
1175         r = amdgpu_bo_create(adev, adev->gds.mem.gfx_partition_size,
1176                         PAGE_SIZE, true,
1177                         AMDGPU_GEM_DOMAIN_GDS, 0, NULL,
1178                         NULL, &adev->gds.gds_gfx_bo);
1179         if (r)
1180                 return r;
1181
1182         r = amdgpu_bo_create(adev, adev->gds.gws.gfx_partition_size,
1183                 PAGE_SIZE, true,
1184                 AMDGPU_GEM_DOMAIN_GWS, 0, NULL,
1185                 NULL, &adev->gds.gws_gfx_bo);
1186         if (r)
1187                 return r;
1188
1189         r = amdgpu_bo_create(adev, adev->gds.oa.gfx_partition_size,
1190                         PAGE_SIZE, true,
1191                         AMDGPU_GEM_DOMAIN_OA, 0, NULL,
1192                         NULL, &adev->gds.oa_gfx_bo);
1193         if (r)
1194                 return r;
1195
1196         adev->gfx.ce_ram_size = 0x8000;
1197
1198         gfx_v8_0_gpu_early_init(adev);
1199
1200         return 0;
1201 }
1202
1203 static int gfx_v8_0_sw_fini(void *handle)
1204 {
1205         int i;
1206         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1207
1208         amdgpu_bo_unref(&adev->gds.oa_gfx_bo);
1209         amdgpu_bo_unref(&adev->gds.gws_gfx_bo);
1210         amdgpu_bo_unref(&adev->gds.gds_gfx_bo);
1211
1212         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1213                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
1214         for (i = 0; i < adev->gfx.num_compute_rings; i++)
1215                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
1216
1217         gfx_v8_0_mec_fini(adev);
1218
1219         return 0;
1220 }
1221
1222 static void gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev)
1223 {
1224         const u32 num_tile_mode_states = 32;
1225         const u32 num_secondary_tile_mode_states = 16;
1226         u32 reg_offset, gb_tile_moden, split_equal_to_row_size;
1227
1228         switch (adev->gfx.config.mem_row_size_in_kb) {
1229         case 1:
1230                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
1231                 break;
1232         case 2:
1233         default:
1234                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
1235                 break;
1236         case 4:
1237                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
1238                 break;
1239         }
1240
1241         switch (adev->asic_type) {
1242         case CHIP_TOPAZ:
1243                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
1244                         switch (reg_offset) {
1245                         case 0:
1246                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1247                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1248                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1249                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1250                                 break;
1251                         case 1:
1252                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1253                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1254                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1255                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1256                                 break;
1257                         case 2:
1258                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1259                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1260                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1261                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1262                                 break;
1263                         case 3:
1264                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1265                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1266                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1267                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1268                                 break;
1269                         case 4:
1270                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1271                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1272                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1273                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1274                                 break;
1275                         case 5:
1276                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1277                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1278                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1279                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1280                                 break;
1281                         case 6:
1282                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1283                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1284                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1285                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1286                                 break;
1287                         case 8:
1288                                 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1289                                                 PIPE_CONFIG(ADDR_SURF_P2));
1290                                 break;
1291                         case 9:
1292                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1293                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1294                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1295                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1296                                 break;
1297                         case 10:
1298                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1299                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1300                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1301                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1302                                 break;
1303                         case 11:
1304                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1305                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1306                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1307                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1308                                 break;
1309                         case 13:
1310                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1311                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1312                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1313                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1314                                 break;
1315                         case 14:
1316                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1317                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1318                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1319                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1320                                 break;
1321                         case 15:
1322                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1323                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1324                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1325                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1326                                 break;
1327                         case 16:
1328                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1329                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1330                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1331                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1332                                 break;
1333                         case 18:
1334                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1335                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1336                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1337                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1338                                 break;
1339                         case 19:
1340                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1341                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1342                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1343                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1344                                 break;
1345                         case 20:
1346                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1347                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1348                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1349                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1350                                 break;
1351                         case 21:
1352                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1353                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1354                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1355                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1356                                 break;
1357                         case 22:
1358                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1359                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1360                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1361                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1362                                 break;
1363                         case 24:
1364                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1365                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1366                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1367                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1368                                 break;
1369                         case 25:
1370                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1371                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1372                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1373                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1374                                 break;
1375                         case 26:
1376                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1377                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1378                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1379                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1380                                 break;
1381                         case 27:
1382                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1383                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1384                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1385                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1386                                 break;
1387                         case 28:
1388                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1389                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1390                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1391                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1392                                 break;
1393                         case 29:
1394                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1395                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1396                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1397                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1398                                 break;
1399                         case 7:
1400                         case 12:
1401                         case 17:
1402                         case 23:
1403                                 /* unused idx */
1404                                 continue;
1405                         default:
1406                                 gb_tile_moden = 0;
1407                                 break;
1408                         };
1409                         adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
1410                         WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
1411                 }
1412                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
1413                         switch (reg_offset) {
1414                         case 0:
1415                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1416                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1417                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1418                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1419                                 break;
1420                         case 1:
1421                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1422                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1423                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1424                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1425                                 break;
1426                         case 2:
1427                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1428                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1429                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1430                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1431                                 break;
1432                         case 3:
1433                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1434                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1435                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1436                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1437                                 break;
1438                         case 4:
1439                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1440                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1441                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1442                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1443                                 break;
1444                         case 5:
1445                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1446                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1447                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1448                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1449                                 break;
1450                         case 6:
1451                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1452                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1453                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1454                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1455                                 break;
1456                         case 8:
1457                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1458                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1459                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1460                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1461                                 break;
1462                         case 9:
1463                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1464                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1465                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1466                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1467                                 break;
1468                         case 10:
1469                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1470                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1471                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1472                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1473                                 break;
1474                         case 11:
1475                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1476                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1477                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1478                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1479                                 break;
1480                         case 12:
1481                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1482                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1483                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1484                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1485                                 break;
1486                         case 13:
1487                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1488                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1489                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1490                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1491                                 break;
1492                         case 14:
1493                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1494                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1495                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1496                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1497                                 break;
1498                         case 7:
1499                                 /* unused idx */
1500                                 continue;
1501                         default:
1502                                 gb_tile_moden = 0;
1503                                 break;
1504                         };
1505                         adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
1506                         WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
1507                 }
1508         case CHIP_FIJI:
1509         case CHIP_TONGA:
1510                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
1511                         switch (reg_offset) {
1512                         case 0:
1513                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1514                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1515                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1516                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1517                                 break;
1518                         case 1:
1519                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1520                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1521                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1522                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1523                                 break;
1524                         case 2:
1525                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1526                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1527                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1528                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1529                                 break;
1530                         case 3:
1531                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1532                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1533                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1534                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1535                                 break;
1536                         case 4:
1537                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1538                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1539                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1540                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1541                                 break;
1542                         case 5:
1543                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1544                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1545                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1546                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1547                                 break;
1548                         case 6:
1549                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1550                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1551                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1552                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1553                                 break;
1554                         case 7:
1555                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1556                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1557                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1558                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1559                                 break;
1560                         case 8:
1561                                 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1562                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16));
1563                                 break;
1564                         case 9:
1565                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1566                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1567                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1568                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1569                                 break;
1570                         case 10:
1571                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1572                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1573                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1574                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1575                                 break;
1576                         case 11:
1577                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1578                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1579                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1580                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1581                                 break;
1582                         case 12:
1583                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1584                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1585                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1586                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1587                                 break;
1588                         case 13:
1589                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1590                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1591                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1592                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1593                                 break;
1594                         case 14:
1595                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1596                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1597                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1598                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1599                                 break;
1600                         case 15:
1601                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1602                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1603                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1604                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1605                                 break;
1606                         case 16:
1607                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1608                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1609                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1610                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1611                                 break;
1612                         case 17:
1613                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1614                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1615                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1616                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1617                                 break;
1618                         case 18:
1619                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1620                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1621                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1622                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1623                                 break;
1624                         case 19:
1625                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1626                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1627                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1628                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1629                                 break;
1630                         case 20:
1631                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1632                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1633                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1634                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1635                                 break;
1636                         case 21:
1637                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1638                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1639                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1640                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1641                                 break;
1642                         case 22:
1643                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1644                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1645                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1646                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1647                                 break;
1648                         case 23:
1649                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1650                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1651                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1652                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1653                                 break;
1654                         case 24:
1655                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1656                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1657                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1658                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1659                                 break;
1660                         case 25:
1661                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1662                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1663                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1664                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1665                                 break;
1666                         case 26:
1667                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1668                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1669                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1670                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1671                                 break;
1672                         case 27:
1673                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1674                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1675                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1676                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1677                                 break;
1678                         case 28:
1679                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1680                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1681                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1682                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1683                                 break;
1684                         case 29:
1685                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1686                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1687                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1688                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1689                                 break;
1690                         case 30:
1691                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1692                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1693                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1694                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1695                                 break;
1696                         default:
1697                                 gb_tile_moden = 0;
1698                                 break;
1699                         };
1700                         adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
1701                         WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
1702                 }
1703                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
1704                         switch (reg_offset) {
1705                         case 0:
1706                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1707                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1708                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1709                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1710                                 break;
1711                         case 1:
1712                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1713                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1714                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1715                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1716                                 break;
1717                         case 2:
1718                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1719                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1720                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1721                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1722                                 break;
1723                         case 3:
1724                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1725                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1726                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1727                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1728                                 break;
1729                         case 4:
1730                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1731                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1732                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1733                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1734                                 break;
1735                         case 5:
1736                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1737                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1738                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1739                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1740                                 break;
1741                         case 6:
1742                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1743                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1744                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1745                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1746                                 break;
1747                         case 8:
1748                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1749                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1750                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1751                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1752                                 break;
1753                         case 9:
1754                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1755                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1756                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1757                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1758                                 break;
1759                         case 10:
1760                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1761                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1762                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1763                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1764                                 break;
1765                         case 11:
1766                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1767                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1768                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1769                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1770                                 break;
1771                         case 12:
1772                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1773                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1774                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1775                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1776                                 break;
1777                         case 13:
1778                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1779                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1780                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1781                                                 NUM_BANKS(ADDR_SURF_4_BANK));
1782                                 break;
1783                         case 14:
1784                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1785                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1786                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1787                                                 NUM_BANKS(ADDR_SURF_4_BANK));
1788                                 break;
1789                         case 7:
1790                                 /* unused idx */
1791                                 continue;
1792                         default:
1793                                 gb_tile_moden = 0;
1794                                 break;
1795                         };
1796                         adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
1797                         WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
1798                 }
1799                 break;
1800         case CHIP_CARRIZO:
1801         default:
1802                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
1803                         switch (reg_offset) {
1804                         case 0:
1805                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1806                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1807                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1808                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1809                                 break;
1810                         case 1:
1811                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1812                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1813                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1814                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1815                                 break;
1816                         case 2:
1817                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1818                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1819                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1820                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1821                                 break;
1822                         case 3:
1823                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1824                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1825                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1826                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1827                                 break;
1828                         case 4:
1829                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1830                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1831                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1832                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1833                                 break;
1834                         case 5:
1835                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1836                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1837                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1838                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1839                                 break;
1840                         case 6:
1841                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1842                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1843                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1844                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1845                                 break;
1846                         case 8:
1847                                 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1848                                                 PIPE_CONFIG(ADDR_SURF_P2));
1849                                 break;
1850                         case 9:
1851                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1852                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1853                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1854                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1855                                 break;
1856                         case 10:
1857                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1858                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1859                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1860                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1861                                 break;
1862                         case 11:
1863                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1864                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1865                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1866                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1867                                 break;
1868                         case 13:
1869                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1870                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1871                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1872                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1873                                 break;
1874                         case 14:
1875                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1876                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1877                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1878                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1879                                 break;
1880                         case 15:
1881                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1882                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1883                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1884                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1885                                 break;
1886                         case 16:
1887                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1888                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1889                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1890                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1891                                 break;
1892                         case 18:
1893                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1894                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1895                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1896                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1897                                 break;
1898                         case 19:
1899                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1900                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1901                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1902                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1903                                 break;
1904                         case 20:
1905                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1906                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1907                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1908                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1909                                 break;
1910                         case 21:
1911                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1912                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1913                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1914                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1915                                 break;
1916                         case 22:
1917                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1918                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1919                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1920                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1921                                 break;
1922                         case 24:
1923                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1924                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1925                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1926                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1927                                 break;
1928                         case 25:
1929                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1930                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1931                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1932                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1933                                 break;
1934                         case 26:
1935                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1936                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1937                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1938                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1939                                 break;
1940                         case 27:
1941                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1942                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1943                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1944                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1945                                 break;
1946                         case 28:
1947                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1948                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1949                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1950                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1951                                 break;
1952                         case 29:
1953                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1954                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1955                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1956                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1957                                 break;
1958                         case 7:
1959                         case 12:
1960                         case 17:
1961                         case 23:
1962                                 /* unused idx */
1963                                 continue;
1964                         default:
1965                                 gb_tile_moden = 0;
1966                                 break;
1967                         };
1968                         adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
1969                         WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
1970                 }
1971                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
1972                         switch (reg_offset) {
1973                         case 0:
1974                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1975                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1976                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1977                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1978                                 break;
1979                         case 1:
1980                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1981                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1982                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1983                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1984                                 break;
1985                         case 2:
1986                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1987                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1988                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1989                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1990                                 break;
1991                         case 3:
1992                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1993                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1994                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1995                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1996                                 break;
1997                         case 4:
1998                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1999                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2000                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2001                                                 NUM_BANKS(ADDR_SURF_8_BANK));
2002                                 break;
2003                         case 5:
2004                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2005                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2006                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2007                                                 NUM_BANKS(ADDR_SURF_8_BANK));
2008                                 break;
2009                         case 6:
2010                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2011                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2012                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2013                                                 NUM_BANKS(ADDR_SURF_8_BANK));
2014                                 break;
2015                         case 8:
2016                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2017                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2018                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2019                                                 NUM_BANKS(ADDR_SURF_16_BANK));
2020                                 break;
2021                         case 9:
2022                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2023                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2024                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2025                                                 NUM_BANKS(ADDR_SURF_16_BANK));
2026                                 break;
2027                         case 10:
2028                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2029                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2030                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2031                                                 NUM_BANKS(ADDR_SURF_16_BANK));
2032                                 break;
2033                         case 11:
2034                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2035                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2036                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2037                                                 NUM_BANKS(ADDR_SURF_16_BANK));
2038                                 break;
2039                         case 12:
2040                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2041                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2042                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2043                                                 NUM_BANKS(ADDR_SURF_16_BANK));
2044                                 break;
2045                         case 13:
2046                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2047                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2048                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2049                                                 NUM_BANKS(ADDR_SURF_16_BANK));
2050                                 break;
2051                         case 14:
2052                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2053                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2054                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2055                                                 NUM_BANKS(ADDR_SURF_8_BANK));
2056                                 break;
2057                         case 7:
2058                                 /* unused idx */
2059                                 continue;
2060                         default:
2061                                 gb_tile_moden = 0;
2062                                 break;
2063                         };
2064                         adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
2065                         WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
2066                 }
2067         }
2068 }
2069
2070 static u32 gfx_v8_0_create_bitmask(u32 bit_width)
2071 {
2072         u32 i, mask = 0;
2073
2074         for (i = 0; i < bit_width; i++) {
2075                 mask <<= 1;
2076                 mask |= 1;
2077         }
2078         return mask;
2079 }
2080
2081 void gfx_v8_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num)
2082 {
2083         u32 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
2084
2085         if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) {
2086                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
2087                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
2088         } else if (se_num == 0xffffffff) {
2089                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
2090                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
2091         } else if (sh_num == 0xffffffff) {
2092                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
2093                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
2094         } else {
2095                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
2096                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
2097         }
2098         WREG32(mmGRBM_GFX_INDEX, data);
2099 }
2100
2101 static u32 gfx_v8_0_get_rb_disabled(struct amdgpu_device *adev,
2102                                     u32 max_rb_num_per_se,
2103                                     u32 sh_per_se)
2104 {
2105         u32 data, mask;
2106
2107         data = RREG32(mmCC_RB_BACKEND_DISABLE);
2108         data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
2109
2110         data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE);
2111
2112         data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
2113
2114         mask = gfx_v8_0_create_bitmask(max_rb_num_per_se / sh_per_se);
2115
2116         return data & mask;
2117 }
2118
2119 static void gfx_v8_0_setup_rb(struct amdgpu_device *adev,
2120                               u32 se_num, u32 sh_per_se,
2121                               u32 max_rb_num_per_se)
2122 {
2123         int i, j;
2124         u32 data, mask;
2125         u32 disabled_rbs = 0;
2126         u32 enabled_rbs = 0;
2127
2128         mutex_lock(&adev->grbm_idx_mutex);
2129         for (i = 0; i < se_num; i++) {
2130                 for (j = 0; j < sh_per_se; j++) {
2131                         gfx_v8_0_select_se_sh(adev, i, j);
2132                         data = gfx_v8_0_get_rb_disabled(adev,
2133                                               max_rb_num_per_se, sh_per_se);
2134                         disabled_rbs |= data << ((i * sh_per_se + j) *
2135                                                  RB_BITMAP_WIDTH_PER_SH);
2136                 }
2137         }
2138         gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
2139         mutex_unlock(&adev->grbm_idx_mutex);
2140
2141         mask = 1;
2142         for (i = 0; i < max_rb_num_per_se * se_num; i++) {
2143                 if (!(disabled_rbs & mask))
2144                         enabled_rbs |= mask;
2145                 mask <<= 1;
2146         }
2147
2148         adev->gfx.config.backend_enable_mask = enabled_rbs;
2149
2150         mutex_lock(&adev->grbm_idx_mutex);
2151         for (i = 0; i < se_num; i++) {
2152                 gfx_v8_0_select_se_sh(adev, i, 0xffffffff);
2153                 data = 0;
2154                 for (j = 0; j < sh_per_se; j++) {
2155                         switch (enabled_rbs & 3) {
2156                         case 0:
2157                                 if (j == 0)
2158                                         data |= (RASTER_CONFIG_RB_MAP_3 <<
2159                                                  PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT);
2160                                 else
2161                                         data |= (RASTER_CONFIG_RB_MAP_0 <<
2162                                                  PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT);
2163                                 break;
2164                         case 1:
2165                                 data |= (RASTER_CONFIG_RB_MAP_0 <<
2166                                          (i * sh_per_se + j) * 2);
2167                                 break;
2168                         case 2:
2169                                 data |= (RASTER_CONFIG_RB_MAP_3 <<
2170                                          (i * sh_per_se + j) * 2);
2171                                 break;
2172                         case 3:
2173                         default:
2174                                 data |= (RASTER_CONFIG_RB_MAP_2 <<
2175                                          (i * sh_per_se + j) * 2);
2176                                 break;
2177                         }
2178                         enabled_rbs >>= 2;
2179                 }
2180                 WREG32(mmPA_SC_RASTER_CONFIG, data);
2181         }
2182         gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
2183         mutex_unlock(&adev->grbm_idx_mutex);
2184 }
2185
2186 /**
2187  * gfx_v8_0_init_compute_vmid - gart enable
2188  *
2189  * @rdev: amdgpu_device pointer
2190  *
2191  * Initialize compute vmid sh_mem registers
2192  *
2193  */
2194 #define DEFAULT_SH_MEM_BASES    (0x6000)
2195 #define FIRST_COMPUTE_VMID      (8)
2196 #define LAST_COMPUTE_VMID       (16)
2197 static void gfx_v8_0_init_compute_vmid(struct amdgpu_device *adev)
2198 {
2199         int i;
2200         uint32_t sh_mem_config;
2201         uint32_t sh_mem_bases;
2202
2203         /*
2204          * Configure apertures:
2205          * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
2206          * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
2207          * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
2208          */
2209         sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
2210
2211         sh_mem_config = SH_MEM_ADDRESS_MODE_HSA64 <<
2212                         SH_MEM_CONFIG__ADDRESS_MODE__SHIFT |
2213                         SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
2214                         SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT |
2215                         MTYPE_CC << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT |
2216                         SH_MEM_CONFIG__PRIVATE_ATC_MASK;
2217
2218         mutex_lock(&adev->srbm_mutex);
2219         for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
2220                 vi_srbm_select(adev, 0, 0, 0, i);
2221                 /* CP and shaders */
2222                 WREG32(mmSH_MEM_CONFIG, sh_mem_config);
2223                 WREG32(mmSH_MEM_APE1_BASE, 1);
2224                 WREG32(mmSH_MEM_APE1_LIMIT, 0);
2225                 WREG32(mmSH_MEM_BASES, sh_mem_bases);
2226         }
2227         vi_srbm_select(adev, 0, 0, 0, 0);
2228         mutex_unlock(&adev->srbm_mutex);
2229 }
2230
2231 static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
2232 {
2233         u32 tmp;
2234         int i;
2235
2236         tmp = RREG32(mmGRBM_CNTL);
2237         tmp = REG_SET_FIELD(tmp, GRBM_CNTL, READ_TIMEOUT, 0xff);
2238         WREG32(mmGRBM_CNTL, tmp);
2239
2240         WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
2241         WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
2242         WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config);
2243         WREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET,
2244                adev->gfx.config.gb_addr_config & 0x70);
2245         WREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET,
2246                adev->gfx.config.gb_addr_config & 0x70);
2247         WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
2248         WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
2249         WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
2250
2251         gfx_v8_0_tiling_mode_table_init(adev);
2252
2253         gfx_v8_0_setup_rb(adev, adev->gfx.config.max_shader_engines,
2254                                  adev->gfx.config.max_sh_per_se,
2255                                  adev->gfx.config.max_backends_per_se);
2256
2257         /* XXX SH_MEM regs */
2258         /* where to put LDS, scratch, GPUVM in FSA64 space */
2259         mutex_lock(&adev->srbm_mutex);
2260         for (i = 0; i < 16; i++) {
2261                 vi_srbm_select(adev, 0, 0, 0, i);
2262                 /* CP and shaders */
2263                 if (i == 0) {
2264                         tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_UC);
2265                         tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC);
2266                         tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
2267                                             SH_MEM_ALIGNMENT_MODE_UNALIGNED);
2268                         WREG32(mmSH_MEM_CONFIG, tmp);
2269                 } else {
2270                         tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_NC);
2271                         tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_NC);
2272                         tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
2273                                             SH_MEM_ALIGNMENT_MODE_UNALIGNED);
2274                         WREG32(mmSH_MEM_CONFIG, tmp);
2275                 }
2276
2277                 WREG32(mmSH_MEM_APE1_BASE, 1);
2278                 WREG32(mmSH_MEM_APE1_LIMIT, 0);
2279                 WREG32(mmSH_MEM_BASES, 0);
2280         }
2281         vi_srbm_select(adev, 0, 0, 0, 0);
2282         mutex_unlock(&adev->srbm_mutex);
2283
2284         gfx_v8_0_init_compute_vmid(adev);
2285
2286         mutex_lock(&adev->grbm_idx_mutex);
2287         /*
2288          * making sure that the following register writes will be broadcasted
2289          * to all the shaders
2290          */
2291         gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
2292
2293         WREG32(mmPA_SC_FIFO_SIZE,
2294                    (adev->gfx.config.sc_prim_fifo_size_frontend <<
2295                         PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
2296                    (adev->gfx.config.sc_prim_fifo_size_backend <<
2297                         PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
2298                    (adev->gfx.config.sc_hiz_tile_fifo_size <<
2299                         PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
2300                    (adev->gfx.config.sc_earlyz_tile_fifo_size <<
2301                         PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT));
2302         mutex_unlock(&adev->grbm_idx_mutex);
2303
2304 }
2305
2306 static void gfx_v8_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
2307 {
2308         u32 i, j, k;
2309         u32 mask;
2310
2311         mutex_lock(&adev->grbm_idx_mutex);
2312         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
2313                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
2314                         gfx_v8_0_select_se_sh(adev, i, j);
2315                         for (k = 0; k < adev->usec_timeout; k++) {
2316                                 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0)
2317                                         break;
2318                                 udelay(1);
2319                         }
2320                 }
2321         }
2322         gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
2323         mutex_unlock(&adev->grbm_idx_mutex);
2324
2325         mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
2326                 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
2327                 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
2328                 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
2329         for (k = 0; k < adev->usec_timeout; k++) {
2330                 if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
2331                         break;
2332                 udelay(1);
2333         }
2334 }
2335
2336 static void gfx_v8_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
2337                                                bool enable)
2338 {
2339         u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
2340
2341         if (enable) {
2342                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 1);
2343                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 1);
2344                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 1);
2345                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 1);
2346         } else {
2347                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 0);
2348                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 0);
2349                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 0);
2350                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 0);
2351         }
2352         WREG32(mmCP_INT_CNTL_RING0, tmp);
2353 }
2354
2355 void gfx_v8_0_rlc_stop(struct amdgpu_device *adev)
2356 {
2357         u32 tmp = RREG32(mmRLC_CNTL);
2358
2359         tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
2360         WREG32(mmRLC_CNTL, tmp);
2361
2362         gfx_v8_0_enable_gui_idle_interrupt(adev, false);
2363
2364         gfx_v8_0_wait_for_rlc_serdes(adev);
2365 }
2366
2367 static void gfx_v8_0_rlc_reset(struct amdgpu_device *adev)
2368 {
2369         u32 tmp = RREG32(mmGRBM_SOFT_RESET);
2370
2371         tmp = REG_SET_FIELD(tmp, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
2372         WREG32(mmGRBM_SOFT_RESET, tmp);
2373         udelay(50);
2374         tmp = REG_SET_FIELD(tmp, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
2375         WREG32(mmGRBM_SOFT_RESET, tmp);
2376         udelay(50);
2377 }
2378
2379 static void gfx_v8_0_rlc_start(struct amdgpu_device *adev)
2380 {
2381         u32 tmp = RREG32(mmRLC_CNTL);
2382
2383         tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 1);
2384         WREG32(mmRLC_CNTL, tmp);
2385
2386         /* carrizo do enable cp interrupt after cp inited */
2387         if (adev->asic_type != CHIP_CARRIZO)
2388                 gfx_v8_0_enable_gui_idle_interrupt(adev, true);
2389
2390         udelay(50);
2391 }
2392
2393 static int gfx_v8_0_rlc_load_microcode(struct amdgpu_device *adev)
2394 {
2395         const struct rlc_firmware_header_v2_0 *hdr;
2396         const __le32 *fw_data;
2397         unsigned i, fw_size;
2398
2399         if (!adev->gfx.rlc_fw)
2400                 return -EINVAL;
2401
2402         hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
2403         amdgpu_ucode_print_rlc_hdr(&hdr->header);
2404
2405         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
2406                            le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2407         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
2408
2409         WREG32(mmRLC_GPM_UCODE_ADDR, 0);
2410         for (i = 0; i < fw_size; i++)
2411                 WREG32(mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
2412         WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
2413
2414         return 0;
2415 }
2416
2417 static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev)
2418 {
2419         int r;
2420
2421         gfx_v8_0_rlc_stop(adev);
2422
2423         /* disable CG */
2424         WREG32(mmRLC_CGCG_CGLS_CTRL, 0);
2425
2426         /* disable PG */
2427         WREG32(mmRLC_PG_CNTL, 0);
2428
2429         gfx_v8_0_rlc_reset(adev);
2430
2431         if (!adev->firmware.smu_load) {
2432                 /* legacy rlc firmware loading */
2433                 r = gfx_v8_0_rlc_load_microcode(adev);
2434                 if (r)
2435                         return r;
2436         } else {
2437                 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
2438                                                 AMDGPU_UCODE_ID_RLC_G);
2439                 if (r)
2440                         return -EINVAL;
2441         }
2442
2443         gfx_v8_0_rlc_start(adev);
2444
2445         return 0;
2446 }
2447
2448 static void gfx_v8_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2449 {
2450         int i;
2451         u32 tmp = RREG32(mmCP_ME_CNTL);
2452
2453         if (enable) {
2454                 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 0);
2455                 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 0);
2456                 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 0);
2457         } else {
2458                 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1);
2459                 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1);
2460                 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1);
2461                 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2462                         adev->gfx.gfx_ring[i].ready = false;
2463         }
2464         WREG32(mmCP_ME_CNTL, tmp);
2465         udelay(50);
2466 }
2467
2468 static int gfx_v8_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2469 {
2470         const struct gfx_firmware_header_v1_0 *pfp_hdr;
2471         const struct gfx_firmware_header_v1_0 *ce_hdr;
2472         const struct gfx_firmware_header_v1_0 *me_hdr;
2473         const __le32 *fw_data;
2474         unsigned i, fw_size;
2475
2476         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2477                 return -EINVAL;
2478
2479         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
2480                 adev->gfx.pfp_fw->data;
2481         ce_hdr = (const struct gfx_firmware_header_v1_0 *)
2482                 adev->gfx.ce_fw->data;
2483         me_hdr = (const struct gfx_firmware_header_v1_0 *)
2484                 adev->gfx.me_fw->data;
2485
2486         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2487         amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2488         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2489
2490         gfx_v8_0_cp_gfx_enable(adev, false);
2491
2492         /* PFP */
2493         fw_data = (const __le32 *)
2494                 (adev->gfx.pfp_fw->data +
2495                  le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2496         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
2497         WREG32(mmCP_PFP_UCODE_ADDR, 0);
2498         for (i = 0; i < fw_size; i++)
2499                 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
2500         WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
2501
2502         /* CE */
2503         fw_data = (const __le32 *)
2504                 (adev->gfx.ce_fw->data +
2505                  le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2506         fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
2507         WREG32(mmCP_CE_UCODE_ADDR, 0);
2508         for (i = 0; i < fw_size; i++)
2509                 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
2510         WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
2511
2512         /* ME */
2513         fw_data = (const __le32 *)
2514                 (adev->gfx.me_fw->data +
2515                  le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2516         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
2517         WREG32(mmCP_ME_RAM_WADDR, 0);
2518         for (i = 0; i < fw_size; i++)
2519                 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2520         WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
2521
2522         return 0;
2523 }
2524
2525 static u32 gfx_v8_0_get_csb_size(struct amdgpu_device *adev)
2526 {
2527         u32 count = 0;
2528         const struct cs_section_def *sect = NULL;
2529         const struct cs_extent_def *ext = NULL;
2530
2531         /* begin clear state */
2532         count += 2;
2533         /* context control state */
2534         count += 3;
2535
2536         for (sect = vi_cs_data; sect->section != NULL; ++sect) {
2537                 for (ext = sect->section; ext->extent != NULL; ++ext) {
2538                         if (sect->id == SECT_CONTEXT)
2539                                 count += 2 + ext->reg_count;
2540                         else
2541                                 return 0;
2542                 }
2543         }
2544         /* pa_sc_raster_config/pa_sc_raster_config1 */
2545         count += 4;
2546         /* end clear state */
2547         count += 2;
2548         /* clear state */
2549         count += 2;
2550
2551         return count;
2552 }
2553
2554 static int gfx_v8_0_cp_gfx_start(struct amdgpu_device *adev)
2555 {
2556         struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2557         const struct cs_section_def *sect = NULL;
2558         const struct cs_extent_def *ext = NULL;
2559         int r, i;
2560
2561         /* init the CP */
2562         WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
2563         WREG32(mmCP_ENDIAN_SWAP, 0);
2564         WREG32(mmCP_DEVICE_ID, 1);
2565
2566         gfx_v8_0_cp_gfx_enable(adev, true);
2567
2568         r = amdgpu_ring_lock(ring, gfx_v8_0_get_csb_size(adev) + 4);
2569         if (r) {
2570                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2571                 return r;
2572         }
2573
2574         /* clear state buffer */
2575         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2576         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2577
2578         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2579         amdgpu_ring_write(ring, 0x80000000);
2580         amdgpu_ring_write(ring, 0x80000000);
2581
2582         for (sect = vi_cs_data; sect->section != NULL; ++sect) {
2583                 for (ext = sect->section; ext->extent != NULL; ++ext) {
2584                         if (sect->id == SECT_CONTEXT) {
2585                                 amdgpu_ring_write(ring,
2586                                        PACKET3(PACKET3_SET_CONTEXT_REG,
2587                                                ext->reg_count));
2588                                 amdgpu_ring_write(ring,
2589                                        ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2590                                 for (i = 0; i < ext->reg_count; i++)
2591                                         amdgpu_ring_write(ring, ext->extent[i]);
2592                         }
2593                 }
2594         }
2595
2596         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2597         amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
2598         switch (adev->asic_type) {
2599         case CHIP_TONGA:
2600         case CHIP_FIJI:
2601                 amdgpu_ring_write(ring, 0x16000012);
2602                 amdgpu_ring_write(ring, 0x0000002A);
2603                 break;
2604         case CHIP_TOPAZ:
2605         case CHIP_CARRIZO:
2606                 amdgpu_ring_write(ring, 0x00000002);
2607                 amdgpu_ring_write(ring, 0x00000000);
2608                 break;
2609         default:
2610                 BUG();
2611         }
2612
2613         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2614         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2615
2616         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2617         amdgpu_ring_write(ring, 0);
2618
2619         /* init the CE partitions */
2620         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2621         amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2622         amdgpu_ring_write(ring, 0x8000);
2623         amdgpu_ring_write(ring, 0x8000);
2624
2625         amdgpu_ring_unlock_commit(ring);
2626
2627         return 0;
2628 }
2629
2630 static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device *adev)
2631 {
2632         struct amdgpu_ring *ring;
2633         u32 tmp;
2634         u32 rb_bufsz;
2635         u64 rb_addr, rptr_addr;
2636         int r;
2637
2638         /* Set the write pointer delay */
2639         WREG32(mmCP_RB_WPTR_DELAY, 0);
2640
2641         /* set the RB to use vmid 0 */
2642         WREG32(mmCP_RB_VMID, 0);
2643
2644         /* Set ring buffer size */
2645         ring = &adev->gfx.gfx_ring[0];
2646         rb_bufsz = order_base_2(ring->ring_size / 8);
2647         tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
2648         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
2649         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MTYPE, 3);
2650         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MIN_IB_AVAILSZ, 1);
2651 #ifdef __BIG_ENDIAN
2652         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
2653 #endif
2654         WREG32(mmCP_RB0_CNTL, tmp);
2655
2656         /* Initialize the ring buffer's read and write pointers */
2657         WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
2658         ring->wptr = 0;
2659         WREG32(mmCP_RB0_WPTR, ring->wptr);
2660
2661         /* set the wb address wether it's enabled or not */
2662         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2663         WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2664         WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2665
2666         mdelay(1);
2667         WREG32(mmCP_RB0_CNTL, tmp);
2668
2669         rb_addr = ring->gpu_addr >> 8;
2670         WREG32(mmCP_RB0_BASE, rb_addr);
2671         WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
2672
2673         /* no gfx doorbells on iceland */
2674         if (adev->asic_type != CHIP_TOPAZ) {
2675                 tmp = RREG32(mmCP_RB_DOORBELL_CONTROL);
2676                 if (ring->use_doorbell) {
2677                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2678                                             DOORBELL_OFFSET, ring->doorbell_index);
2679                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2680                                             DOORBELL_EN, 1);
2681                 } else {
2682                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2683                                             DOORBELL_EN, 0);
2684                 }
2685                 WREG32(mmCP_RB_DOORBELL_CONTROL, tmp);
2686
2687                 if (adev->asic_type == CHIP_TONGA) {
2688                         tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
2689                                             DOORBELL_RANGE_LOWER,
2690                                             AMDGPU_DOORBELL_GFX_RING0);
2691                         WREG32(mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
2692
2693                         WREG32(mmCP_RB_DOORBELL_RANGE_UPPER,
2694                                CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
2695                 }
2696
2697         }
2698
2699         /* start the ring */
2700         gfx_v8_0_cp_gfx_start(adev);
2701         ring->ready = true;
2702         r = amdgpu_ring_test_ring(ring);
2703         if (r) {
2704                 ring->ready = false;
2705                 return r;
2706         }
2707
2708         return 0;
2709 }
2710
2711 static void gfx_v8_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
2712 {
2713         int i;
2714
2715         if (enable) {
2716                 WREG32(mmCP_MEC_CNTL, 0);
2717         } else {
2718                 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
2719                 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2720                         adev->gfx.compute_ring[i].ready = false;
2721         }
2722         udelay(50);
2723 }
2724
2725 static int gfx_v8_0_cp_compute_start(struct amdgpu_device *adev)
2726 {
2727         gfx_v8_0_cp_compute_enable(adev, true);
2728
2729         return 0;
2730 }
2731
2732 static int gfx_v8_0_cp_compute_load_microcode(struct amdgpu_device *adev)
2733 {
2734         const struct gfx_firmware_header_v1_0 *mec_hdr;
2735         const __le32 *fw_data;
2736         unsigned i, fw_size;
2737
2738         if (!adev->gfx.mec_fw)
2739                 return -EINVAL;
2740
2741         gfx_v8_0_cp_compute_enable(adev, false);
2742
2743         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2744         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
2745
2746         fw_data = (const __le32 *)
2747                 (adev->gfx.mec_fw->data +
2748                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
2749         fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
2750
2751         /* MEC1 */
2752         WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
2753         for (i = 0; i < fw_size; i++)
2754                 WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data+i));
2755         WREG32(mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
2756
2757         /* Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */
2758         if (adev->gfx.mec2_fw) {
2759                 const struct gfx_firmware_header_v1_0 *mec2_hdr;
2760
2761                 mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
2762                 amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header);
2763
2764                 fw_data = (const __le32 *)
2765                         (adev->gfx.mec2_fw->data +
2766                          le32_to_cpu(mec2_hdr->header.ucode_array_offset_bytes));
2767                 fw_size = le32_to_cpu(mec2_hdr->header.ucode_size_bytes) / 4;
2768
2769                 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
2770                 for (i = 0; i < fw_size; i++)
2771                         WREG32(mmCP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data+i));
2772                 WREG32(mmCP_MEC_ME2_UCODE_ADDR, adev->gfx.mec2_fw_version);
2773         }
2774
2775         return 0;
2776 }
2777
2778 struct vi_mqd {
2779         uint32_t header;  /* ordinal0 */
2780         uint32_t compute_dispatch_initiator;  /* ordinal1 */
2781         uint32_t compute_dim_x;  /* ordinal2 */
2782         uint32_t compute_dim_y;  /* ordinal3 */
2783         uint32_t compute_dim_z;  /* ordinal4 */
2784         uint32_t compute_start_x;  /* ordinal5 */
2785         uint32_t compute_start_y;  /* ordinal6 */
2786         uint32_t compute_start_z;  /* ordinal7 */
2787         uint32_t compute_num_thread_x;  /* ordinal8 */
2788         uint32_t compute_num_thread_y;  /* ordinal9 */
2789         uint32_t compute_num_thread_z;  /* ordinal10 */
2790         uint32_t compute_pipelinestat_enable;  /* ordinal11 */
2791         uint32_t compute_perfcount_enable;  /* ordinal12 */
2792         uint32_t compute_pgm_lo;  /* ordinal13 */
2793         uint32_t compute_pgm_hi;  /* ordinal14 */
2794         uint32_t compute_tba_lo;  /* ordinal15 */
2795         uint32_t compute_tba_hi;  /* ordinal16 */
2796         uint32_t compute_tma_lo;  /* ordinal17 */
2797         uint32_t compute_tma_hi;  /* ordinal18 */
2798         uint32_t compute_pgm_rsrc1;  /* ordinal19 */
2799         uint32_t compute_pgm_rsrc2;  /* ordinal20 */
2800         uint32_t compute_vmid;  /* ordinal21 */
2801         uint32_t compute_resource_limits;  /* ordinal22 */
2802         uint32_t compute_static_thread_mgmt_se0;  /* ordinal23 */
2803         uint32_t compute_static_thread_mgmt_se1;  /* ordinal24 */
2804         uint32_t compute_tmpring_size;  /* ordinal25 */
2805         uint32_t compute_static_thread_mgmt_se2;  /* ordinal26 */
2806         uint32_t compute_static_thread_mgmt_se3;  /* ordinal27 */
2807         uint32_t compute_restart_x;  /* ordinal28 */
2808         uint32_t compute_restart_y;  /* ordinal29 */
2809         uint32_t compute_restart_z;  /* ordinal30 */
2810         uint32_t compute_thread_trace_enable;  /* ordinal31 */
2811         uint32_t compute_misc_reserved;  /* ordinal32 */
2812         uint32_t compute_dispatch_id;  /* ordinal33 */
2813         uint32_t compute_threadgroup_id;  /* ordinal34 */
2814         uint32_t compute_relaunch;  /* ordinal35 */
2815         uint32_t compute_wave_restore_addr_lo;  /* ordinal36 */
2816         uint32_t compute_wave_restore_addr_hi;  /* ordinal37 */
2817         uint32_t compute_wave_restore_control;  /* ordinal38 */
2818         uint32_t reserved9;  /* ordinal39 */
2819         uint32_t reserved10;  /* ordinal40 */
2820         uint32_t reserved11;  /* ordinal41 */
2821         uint32_t reserved12;  /* ordinal42 */
2822         uint32_t reserved13;  /* ordinal43 */
2823         uint32_t reserved14;  /* ordinal44 */
2824         uint32_t reserved15;  /* ordinal45 */
2825         uint32_t reserved16;  /* ordinal46 */
2826         uint32_t reserved17;  /* ordinal47 */
2827         uint32_t reserved18;  /* ordinal48 */
2828         uint32_t reserved19;  /* ordinal49 */
2829         uint32_t reserved20;  /* ordinal50 */
2830         uint32_t reserved21;  /* ordinal51 */
2831         uint32_t reserved22;  /* ordinal52 */
2832         uint32_t reserved23;  /* ordinal53 */
2833         uint32_t reserved24;  /* ordinal54 */
2834         uint32_t reserved25;  /* ordinal55 */
2835         uint32_t reserved26;  /* ordinal56 */
2836         uint32_t reserved27;  /* ordinal57 */
2837         uint32_t reserved28;  /* ordinal58 */
2838         uint32_t reserved29;  /* ordinal59 */
2839         uint32_t reserved30;  /* ordinal60 */
2840         uint32_t reserved31;  /* ordinal61 */
2841         uint32_t reserved32;  /* ordinal62 */
2842         uint32_t reserved33;  /* ordinal63 */
2843         uint32_t reserved34;  /* ordinal64 */
2844         uint32_t compute_user_data_0;  /* ordinal65 */
2845         uint32_t compute_user_data_1;  /* ordinal66 */
2846         uint32_t compute_user_data_2;  /* ordinal67 */
2847         uint32_t compute_user_data_3;  /* ordinal68 */
2848         uint32_t compute_user_data_4;  /* ordinal69 */
2849         uint32_t compute_user_data_5;  /* ordinal70 */
2850         uint32_t compute_user_data_6;  /* ordinal71 */
2851         uint32_t compute_user_data_7;  /* ordinal72 */
2852         uint32_t compute_user_data_8;  /* ordinal73 */
2853         uint32_t compute_user_data_9;  /* ordinal74 */
2854         uint32_t compute_user_data_10;  /* ordinal75 */
2855         uint32_t compute_user_data_11;  /* ordinal76 */
2856         uint32_t compute_user_data_12;  /* ordinal77 */
2857         uint32_t compute_user_data_13;  /* ordinal78 */
2858         uint32_t compute_user_data_14;  /* ordinal79 */
2859         uint32_t compute_user_data_15;  /* ordinal80 */
2860         uint32_t cp_compute_csinvoc_count_lo;  /* ordinal81 */
2861         uint32_t cp_compute_csinvoc_count_hi;  /* ordinal82 */
2862         uint32_t reserved35;  /* ordinal83 */
2863         uint32_t reserved36;  /* ordinal84 */
2864         uint32_t reserved37;  /* ordinal85 */
2865         uint32_t cp_mqd_query_time_lo;  /* ordinal86 */
2866         uint32_t cp_mqd_query_time_hi;  /* ordinal87 */
2867         uint32_t cp_mqd_connect_start_time_lo;  /* ordinal88 */
2868         uint32_t cp_mqd_connect_start_time_hi;  /* ordinal89 */
2869         uint32_t cp_mqd_connect_end_time_lo;  /* ordinal90 */
2870         uint32_t cp_mqd_connect_end_time_hi;  /* ordinal91 */
2871         uint32_t cp_mqd_connect_end_wf_count;  /* ordinal92 */
2872         uint32_t cp_mqd_connect_end_pq_rptr;  /* ordinal93 */
2873         uint32_t cp_mqd_connect_end_pq_wptr;  /* ordinal94 */
2874         uint32_t cp_mqd_connect_end_ib_rptr;  /* ordinal95 */
2875         uint32_t reserved38;  /* ordinal96 */
2876         uint32_t reserved39;  /* ordinal97 */
2877         uint32_t cp_mqd_save_start_time_lo;  /* ordinal98 */
2878         uint32_t cp_mqd_save_start_time_hi;  /* ordinal99 */
2879         uint32_t cp_mqd_save_end_time_lo;  /* ordinal100 */
2880         uint32_t cp_mqd_save_end_time_hi;  /* ordinal101 */
2881         uint32_t cp_mqd_restore_start_time_lo;  /* ordinal102 */
2882         uint32_t cp_mqd_restore_start_time_hi;  /* ordinal103 */
2883         uint32_t cp_mqd_restore_end_time_lo;  /* ordinal104 */
2884         uint32_t cp_mqd_restore_end_time_hi;  /* ordinal105 */
2885         uint32_t reserved40;  /* ordinal106 */
2886         uint32_t reserved41;  /* ordinal107 */
2887         uint32_t gds_cs_ctxsw_cnt0;  /* ordinal108 */
2888         uint32_t gds_cs_ctxsw_cnt1;  /* ordinal109 */
2889         uint32_t gds_cs_ctxsw_cnt2;  /* ordinal110 */
2890         uint32_t gds_cs_ctxsw_cnt3;  /* ordinal111 */
2891         uint32_t reserved42;  /* ordinal112 */
2892         uint32_t reserved43;  /* ordinal113 */
2893         uint32_t cp_pq_exe_status_lo;  /* ordinal114 */
2894         uint32_t cp_pq_exe_status_hi;  /* ordinal115 */
2895         uint32_t cp_packet_id_lo;  /* ordinal116 */
2896         uint32_t cp_packet_id_hi;  /* ordinal117 */
2897         uint32_t cp_packet_exe_status_lo;  /* ordinal118 */
2898         uint32_t cp_packet_exe_status_hi;  /* ordinal119 */
2899         uint32_t gds_save_base_addr_lo;  /* ordinal120 */
2900         uint32_t gds_save_base_addr_hi;  /* ordinal121 */
2901         uint32_t gds_save_mask_lo;  /* ordinal122 */
2902         uint32_t gds_save_mask_hi;  /* ordinal123 */
2903         uint32_t ctx_save_base_addr_lo;  /* ordinal124 */
2904         uint32_t ctx_save_base_addr_hi;  /* ordinal125 */
2905         uint32_t reserved44;  /* ordinal126 */
2906         uint32_t reserved45;  /* ordinal127 */
2907         uint32_t cp_mqd_base_addr_lo;  /* ordinal128 */
2908         uint32_t cp_mqd_base_addr_hi;  /* ordinal129 */
2909         uint32_t cp_hqd_active;  /* ordinal130 */
2910         uint32_t cp_hqd_vmid;  /* ordinal131 */
2911         uint32_t cp_hqd_persistent_state;  /* ordinal132 */
2912         uint32_t cp_hqd_pipe_priority;  /* ordinal133 */
2913         uint32_t cp_hqd_queue_priority;  /* ordinal134 */
2914         uint32_t cp_hqd_quantum;  /* ordinal135 */
2915         uint32_t cp_hqd_pq_base_lo;  /* ordinal136 */
2916         uint32_t cp_hqd_pq_base_hi;  /* ordinal137 */
2917         uint32_t cp_hqd_pq_rptr;  /* ordinal138 */
2918         uint32_t cp_hqd_pq_rptr_report_addr_lo;  /* ordinal139 */
2919         uint32_t cp_hqd_pq_rptr_report_addr_hi;  /* ordinal140 */
2920         uint32_t cp_hqd_pq_wptr_poll_addr;  /* ordinal141 */
2921         uint32_t cp_hqd_pq_wptr_poll_addr_hi;  /* ordinal142 */
2922         uint32_t cp_hqd_pq_doorbell_control;  /* ordinal143 */
2923         uint32_t cp_hqd_pq_wptr;  /* ordinal144 */
2924         uint32_t cp_hqd_pq_control;  /* ordinal145 */
2925         uint32_t cp_hqd_ib_base_addr_lo;  /* ordinal146 */
2926         uint32_t cp_hqd_ib_base_addr_hi;  /* ordinal147 */
2927         uint32_t cp_hqd_ib_rptr;  /* ordinal148 */
2928         uint32_t cp_hqd_ib_control;  /* ordinal149 */
2929         uint32_t cp_hqd_iq_timer;  /* ordinal150 */
2930         uint32_t cp_hqd_iq_rptr;  /* ordinal151 */
2931         uint32_t cp_hqd_dequeue_request;  /* ordinal152 */
2932         uint32_t cp_hqd_dma_offload;  /* ordinal153 */
2933         uint32_t cp_hqd_sema_cmd;  /* ordinal154 */
2934         uint32_t cp_hqd_msg_type;  /* ordinal155 */
2935         uint32_t cp_hqd_atomic0_preop_lo;  /* ordinal156 */
2936         uint32_t cp_hqd_atomic0_preop_hi;  /* ordinal157 */
2937         uint32_t cp_hqd_atomic1_preop_lo;  /* ordinal158 */
2938         uint32_t cp_hqd_atomic1_preop_hi;  /* ordinal159 */
2939         uint32_t cp_hqd_hq_status0;  /* ordinal160 */
2940         uint32_t cp_hqd_hq_control0;  /* ordinal161 */
2941         uint32_t cp_mqd_control;  /* ordinal162 */
2942         uint32_t cp_hqd_hq_status1;  /* ordinal163 */
2943         uint32_t cp_hqd_hq_control1;  /* ordinal164 */
2944         uint32_t cp_hqd_eop_base_addr_lo;  /* ordinal165 */
2945         uint32_t cp_hqd_eop_base_addr_hi;  /* ordinal166 */
2946         uint32_t cp_hqd_eop_control;  /* ordinal167 */
2947         uint32_t cp_hqd_eop_rptr;  /* ordinal168 */
2948         uint32_t cp_hqd_eop_wptr;  /* ordinal169 */
2949         uint32_t cp_hqd_eop_done_events;  /* ordinal170 */
2950         uint32_t cp_hqd_ctx_save_base_addr_lo;  /* ordinal171 */
2951         uint32_t cp_hqd_ctx_save_base_addr_hi;  /* ordinal172 */
2952         uint32_t cp_hqd_ctx_save_control;  /* ordinal173 */
2953         uint32_t cp_hqd_cntl_stack_offset;  /* ordinal174 */
2954         uint32_t cp_hqd_cntl_stack_size;  /* ordinal175 */
2955         uint32_t cp_hqd_wg_state_offset;  /* ordinal176 */
2956         uint32_t cp_hqd_ctx_save_size;  /* ordinal177 */
2957         uint32_t cp_hqd_gds_resource_state;  /* ordinal178 */
2958         uint32_t cp_hqd_error;  /* ordinal179 */
2959         uint32_t cp_hqd_eop_wptr_mem;  /* ordinal180 */
2960         uint32_t cp_hqd_eop_dones;  /* ordinal181 */
2961         uint32_t reserved46;  /* ordinal182 */
2962         uint32_t reserved47;  /* ordinal183 */
2963         uint32_t reserved48;  /* ordinal184 */
2964         uint32_t reserved49;  /* ordinal185 */
2965         uint32_t reserved50;  /* ordinal186 */
2966         uint32_t reserved51;  /* ordinal187 */
2967         uint32_t reserved52;  /* ordinal188 */
2968         uint32_t reserved53;  /* ordinal189 */
2969         uint32_t reserved54;  /* ordinal190 */
2970         uint32_t reserved55;  /* ordinal191 */
2971         uint32_t iqtimer_pkt_header;  /* ordinal192 */
2972         uint32_t iqtimer_pkt_dw0;  /* ordinal193 */
2973         uint32_t iqtimer_pkt_dw1;  /* ordinal194 */
2974         uint32_t iqtimer_pkt_dw2;  /* ordinal195 */
2975         uint32_t iqtimer_pkt_dw3;  /* ordinal196 */
2976         uint32_t iqtimer_pkt_dw4;  /* ordinal197 */
2977         uint32_t iqtimer_pkt_dw5;  /* ordinal198 */
2978         uint32_t iqtimer_pkt_dw6;  /* ordinal199 */
2979         uint32_t iqtimer_pkt_dw7;  /* ordinal200 */
2980         uint32_t iqtimer_pkt_dw8;  /* ordinal201 */
2981         uint32_t iqtimer_pkt_dw9;  /* ordinal202 */
2982         uint32_t iqtimer_pkt_dw10;  /* ordinal203 */
2983         uint32_t iqtimer_pkt_dw11;  /* ordinal204 */
2984         uint32_t iqtimer_pkt_dw12;  /* ordinal205 */
2985         uint32_t iqtimer_pkt_dw13;  /* ordinal206 */
2986         uint32_t iqtimer_pkt_dw14;  /* ordinal207 */
2987         uint32_t iqtimer_pkt_dw15;  /* ordinal208 */
2988         uint32_t iqtimer_pkt_dw16;  /* ordinal209 */
2989         uint32_t iqtimer_pkt_dw17;  /* ordinal210 */
2990         uint32_t iqtimer_pkt_dw18;  /* ordinal211 */
2991         uint32_t iqtimer_pkt_dw19;  /* ordinal212 */
2992         uint32_t iqtimer_pkt_dw20;  /* ordinal213 */
2993         uint32_t iqtimer_pkt_dw21;  /* ordinal214 */
2994         uint32_t iqtimer_pkt_dw22;  /* ordinal215 */
2995         uint32_t iqtimer_pkt_dw23;  /* ordinal216 */
2996         uint32_t iqtimer_pkt_dw24;  /* ordinal217 */
2997         uint32_t iqtimer_pkt_dw25;  /* ordinal218 */
2998         uint32_t iqtimer_pkt_dw26;  /* ordinal219 */
2999         uint32_t iqtimer_pkt_dw27;  /* ordinal220 */
3000         uint32_t iqtimer_pkt_dw28;  /* ordinal221 */
3001         uint32_t iqtimer_pkt_dw29;  /* ordinal222 */
3002         uint32_t iqtimer_pkt_dw30;  /* ordinal223 */
3003         uint32_t iqtimer_pkt_dw31;  /* ordinal224 */
3004         uint32_t reserved56;  /* ordinal225 */
3005         uint32_t reserved57;  /* ordinal226 */
3006         uint32_t reserved58;  /* ordinal227 */
3007         uint32_t set_resources_header;  /* ordinal228 */
3008         uint32_t set_resources_dw1;  /* ordinal229 */
3009         uint32_t set_resources_dw2;  /* ordinal230 */
3010         uint32_t set_resources_dw3;  /* ordinal231 */
3011         uint32_t set_resources_dw4;  /* ordinal232 */
3012         uint32_t set_resources_dw5;  /* ordinal233 */
3013         uint32_t set_resources_dw6;  /* ordinal234 */
3014         uint32_t set_resources_dw7;  /* ordinal235 */
3015         uint32_t reserved59;  /* ordinal236 */
3016         uint32_t reserved60;  /* ordinal237 */
3017         uint32_t reserved61;  /* ordinal238 */
3018         uint32_t reserved62;  /* ordinal239 */
3019         uint32_t reserved63;  /* ordinal240 */
3020         uint32_t reserved64;  /* ordinal241 */
3021         uint32_t reserved65;  /* ordinal242 */
3022         uint32_t reserved66;  /* ordinal243 */
3023         uint32_t reserved67;  /* ordinal244 */
3024         uint32_t reserved68;  /* ordinal245 */
3025         uint32_t reserved69;  /* ordinal246 */
3026         uint32_t reserved70;  /* ordinal247 */
3027         uint32_t reserved71;  /* ordinal248 */
3028         uint32_t reserved72;  /* ordinal249 */
3029         uint32_t reserved73;  /* ordinal250 */
3030         uint32_t reserved74;  /* ordinal251 */
3031         uint32_t reserved75;  /* ordinal252 */
3032         uint32_t reserved76;  /* ordinal253 */
3033         uint32_t reserved77;  /* ordinal254 */
3034         uint32_t reserved78;  /* ordinal255 */
3035
3036         uint32_t reserved_t[256]; /* Reserve 256 dword buffer used by ucode */
3037 };
3038
3039 static void gfx_v8_0_cp_compute_fini(struct amdgpu_device *adev)
3040 {
3041         int i, r;
3042
3043         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3044                 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
3045
3046                 if (ring->mqd_obj) {
3047                         r = amdgpu_bo_reserve(ring->mqd_obj, false);
3048                         if (unlikely(r != 0))
3049                                 dev_warn(adev->dev, "(%d) reserve MQD bo failed\n", r);
3050
3051                         amdgpu_bo_unpin(ring->mqd_obj);
3052                         amdgpu_bo_unreserve(ring->mqd_obj);
3053
3054                         amdgpu_bo_unref(&ring->mqd_obj);
3055                         ring->mqd_obj = NULL;
3056                 }
3057         }
3058 }
3059
3060 static int gfx_v8_0_cp_compute_resume(struct amdgpu_device *adev)
3061 {
3062         int r, i, j;
3063         u32 tmp;
3064         bool use_doorbell = true;
3065         u64 hqd_gpu_addr;
3066         u64 mqd_gpu_addr;
3067         u64 eop_gpu_addr;
3068         u64 wb_gpu_addr;
3069         u32 *buf;
3070         struct vi_mqd *mqd;
3071
3072         /* init the pipes */
3073         mutex_lock(&adev->srbm_mutex);
3074         for (i = 0; i < (adev->gfx.mec.num_pipe * adev->gfx.mec.num_mec); i++) {
3075                 int me = (i < 4) ? 1 : 2;
3076                 int pipe = (i < 4) ? i : (i - 4);
3077
3078                 eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE);
3079                 eop_gpu_addr >>= 8;
3080
3081                 vi_srbm_select(adev, me, pipe, 0, 0);
3082
3083                 /* write the EOP addr */
3084                 WREG32(mmCP_HQD_EOP_BASE_ADDR, eop_gpu_addr);
3085                 WREG32(mmCP_HQD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr));
3086
3087                 /* set the VMID assigned */
3088                 WREG32(mmCP_HQD_VMID, 0);
3089
3090                 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
3091                 tmp = RREG32(mmCP_HQD_EOP_CONTROL);
3092                 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
3093                                     (order_base_2(MEC_HPD_SIZE / 4) - 1));
3094                 WREG32(mmCP_HQD_EOP_CONTROL, tmp);
3095         }
3096         vi_srbm_select(adev, 0, 0, 0, 0);
3097         mutex_unlock(&adev->srbm_mutex);
3098
3099         /* init the queues.  Just two for now. */
3100         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3101                 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
3102
3103                 if (ring->mqd_obj == NULL) {
3104                         r = amdgpu_bo_create(adev,
3105                                              sizeof(struct vi_mqd),
3106                                              PAGE_SIZE, true,
3107                                              AMDGPU_GEM_DOMAIN_GTT, 0, NULL,
3108                                              NULL, &ring->mqd_obj);
3109                         if (r) {
3110                                 dev_warn(adev->dev, "(%d) create MQD bo failed\n", r);
3111                                 return r;
3112                         }
3113                 }
3114
3115                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
3116                 if (unlikely(r != 0)) {
3117                         gfx_v8_0_cp_compute_fini(adev);
3118                         return r;
3119                 }
3120                 r = amdgpu_bo_pin(ring->mqd_obj, AMDGPU_GEM_DOMAIN_GTT,
3121                                   &mqd_gpu_addr);
3122                 if (r) {
3123                         dev_warn(adev->dev, "(%d) pin MQD bo failed\n", r);
3124                         gfx_v8_0_cp_compute_fini(adev);
3125                         return r;
3126                 }
3127                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&buf);
3128                 if (r) {
3129                         dev_warn(adev->dev, "(%d) map MQD bo failed\n", r);
3130                         gfx_v8_0_cp_compute_fini(adev);
3131                         return r;
3132                 }
3133
3134                 /* init the mqd struct */
3135                 memset(buf, 0, sizeof(struct vi_mqd));
3136
3137                 mqd = (struct vi_mqd *)buf;
3138                 mqd->header = 0xC0310800;
3139                 mqd->compute_pipelinestat_enable = 0x00000001;
3140                 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
3141                 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
3142                 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
3143                 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
3144                 mqd->compute_misc_reserved = 0x00000003;
3145
3146                 mutex_lock(&adev->srbm_mutex);
3147                 vi_srbm_select(adev, ring->me,
3148                                ring->pipe,
3149                                ring->queue, 0);
3150
3151                 /* disable wptr polling */
3152                 tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL);
3153                 tmp = REG_SET_FIELD(tmp, CP_PQ_WPTR_POLL_CNTL, EN, 0);
3154                 WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp);
3155
3156                 mqd->cp_hqd_eop_base_addr_lo =
3157                         RREG32(mmCP_HQD_EOP_BASE_ADDR);
3158                 mqd->cp_hqd_eop_base_addr_hi =
3159                         RREG32(mmCP_HQD_EOP_BASE_ADDR_HI);
3160
3161                 /* enable doorbell? */
3162                 tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
3163                 if (use_doorbell) {
3164                         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
3165                 } else {
3166                         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 0);
3167                 }
3168                 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, tmp);
3169                 mqd->cp_hqd_pq_doorbell_control = tmp;
3170
3171                 /* disable the queue if it's active */
3172                 mqd->cp_hqd_dequeue_request = 0;
3173                 mqd->cp_hqd_pq_rptr = 0;
3174                 mqd->cp_hqd_pq_wptr= 0;
3175                 if (RREG32(mmCP_HQD_ACTIVE) & 1) {
3176                         WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1);
3177                         for (j = 0; j < adev->usec_timeout; j++) {
3178                                 if (!(RREG32(mmCP_HQD_ACTIVE) & 1))
3179                                         break;
3180                                 udelay(1);
3181                         }
3182                         WREG32(mmCP_HQD_DEQUEUE_REQUEST, mqd->cp_hqd_dequeue_request);
3183                         WREG32(mmCP_HQD_PQ_RPTR, mqd->cp_hqd_pq_rptr);
3184                         WREG32(mmCP_HQD_PQ_WPTR, mqd->cp_hqd_pq_wptr);
3185                 }
3186
3187                 /* set the pointer to the MQD */
3188                 mqd->cp_mqd_base_addr_lo = mqd_gpu_addr & 0xfffffffc;
3189                 mqd->cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);
3190                 WREG32(mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo);
3191                 WREG32(mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
3192
3193                 /* set MQD vmid to 0 */
3194                 tmp = RREG32(mmCP_MQD_CONTROL);
3195                 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
3196                 WREG32(mmCP_MQD_CONTROL, tmp);
3197                 mqd->cp_mqd_control = tmp;
3198
3199                 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3200                 hqd_gpu_addr = ring->gpu_addr >> 8;
3201                 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
3202                 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
3203                 WREG32(mmCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo);
3204                 WREG32(mmCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi);
3205
3206                 /* set up the HQD, this is similar to CP_RB0_CNTL */
3207                 tmp = RREG32(mmCP_HQD_PQ_CONTROL);
3208                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
3209                                     (order_base_2(ring->ring_size / 4) - 1));
3210                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
3211                                ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
3212 #ifdef __BIG_ENDIAN
3213                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
3214 #endif
3215                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
3216                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
3217                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
3218                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
3219                 WREG32(mmCP_HQD_PQ_CONTROL, tmp);
3220                 mqd->cp_hqd_pq_control = tmp;
3221
3222                 /* set the wb address wether it's enabled or not */
3223                 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
3224                 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
3225                 mqd->cp_hqd_pq_rptr_report_addr_hi =
3226                         upper_32_bits(wb_gpu_addr) & 0xffff;
3227                 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR,
3228                        mqd->cp_hqd_pq_rptr_report_addr_lo);
3229                 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
3230                        mqd->cp_hqd_pq_rptr_report_addr_hi);
3231
3232                 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3233                 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3234                 mqd->cp_hqd_pq_wptr_poll_addr = wb_gpu_addr & 0xfffffffc;
3235                 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
3236                 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, mqd->cp_hqd_pq_wptr_poll_addr);
3237                 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
3238                        mqd->cp_hqd_pq_wptr_poll_addr_hi);
3239
3240                 /* enable the doorbell if requested */
3241                 if (use_doorbell) {
3242                         if ((adev->asic_type == CHIP_CARRIZO) ||
3243                             (adev->asic_type == CHIP_FIJI)) {
3244                                 WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER,
3245                                        AMDGPU_DOORBELL_KIQ << 2);
3246                                 WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER,
3247                                        AMDGPU_DOORBELL_MEC_RING7 << 2);
3248                         }
3249                         tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
3250                         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3251                                             DOORBELL_OFFSET, ring->doorbell_index);
3252                         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
3253                         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_SOURCE, 0);
3254                         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_HIT, 0);
3255                         mqd->cp_hqd_pq_doorbell_control = tmp;
3256
3257                 } else {
3258                         mqd->cp_hqd_pq_doorbell_control = 0;
3259                 }
3260                 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL,
3261                        mqd->cp_hqd_pq_doorbell_control);
3262
3263                 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3264                 ring->wptr = 0;
3265                 mqd->cp_hqd_pq_wptr = ring->wptr;
3266                 WREG32(mmCP_HQD_PQ_WPTR, mqd->cp_hqd_pq_wptr);
3267                 mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
3268
3269                 /* set the vmid for the queue */
3270                 mqd->cp_hqd_vmid = 0;
3271                 WREG32(mmCP_HQD_VMID, mqd->cp_hqd_vmid);
3272
3273                 tmp = RREG32(mmCP_HQD_PERSISTENT_STATE);
3274                 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
3275                 WREG32(mmCP_HQD_PERSISTENT_STATE, tmp);
3276                 mqd->cp_hqd_persistent_state = tmp;
3277
3278                 /* activate the queue */
3279                 mqd->cp_hqd_active = 1;
3280                 WREG32(mmCP_HQD_ACTIVE, mqd->cp_hqd_active);
3281
3282                 vi_srbm_select(adev, 0, 0, 0, 0);
3283                 mutex_unlock(&adev->srbm_mutex);
3284
3285                 amdgpu_bo_kunmap(ring->mqd_obj);
3286                 amdgpu_bo_unreserve(ring->mqd_obj);
3287         }
3288
3289         if (use_doorbell) {
3290                 tmp = RREG32(mmCP_PQ_STATUS);
3291                 tmp = REG_SET_FIELD(tmp, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
3292                 WREG32(mmCP_PQ_STATUS, tmp);
3293         }
3294
3295         r = gfx_v8_0_cp_compute_start(adev);
3296         if (r)
3297                 return r;
3298
3299         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3300                 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
3301
3302                 ring->ready = true;
3303                 r = amdgpu_ring_test_ring(ring);
3304                 if (r)
3305                         ring->ready = false;
3306         }
3307
3308         return 0;
3309 }
3310
3311 static int gfx_v8_0_cp_resume(struct amdgpu_device *adev)
3312 {
3313         int r;
3314
3315         if (adev->asic_type != CHIP_CARRIZO)
3316                 gfx_v8_0_enable_gui_idle_interrupt(adev, false);
3317
3318         if (!adev->firmware.smu_load) {
3319                 /* legacy firmware loading */
3320                 r = gfx_v8_0_cp_gfx_load_microcode(adev);
3321                 if (r)
3322                         return r;
3323
3324                 r = gfx_v8_0_cp_compute_load_microcode(adev);
3325                 if (r)
3326                         return r;
3327         } else {
3328                 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
3329                                                 AMDGPU_UCODE_ID_CP_CE);
3330                 if (r)
3331                         return -EINVAL;
3332
3333                 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
3334                                                 AMDGPU_UCODE_ID_CP_PFP);
3335                 if (r)
3336                         return -EINVAL;
3337
3338                 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
3339                                                 AMDGPU_UCODE_ID_CP_ME);
3340                 if (r)
3341                         return -EINVAL;
3342
3343                 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
3344                                                 AMDGPU_UCODE_ID_CP_MEC1);
3345                 if (r)
3346                         return -EINVAL;
3347         }
3348
3349         r = gfx_v8_0_cp_gfx_resume(adev);
3350         if (r)
3351                 return r;
3352
3353         r = gfx_v8_0_cp_compute_resume(adev);
3354         if (r)
3355                 return r;
3356
3357         gfx_v8_0_enable_gui_idle_interrupt(adev, true);
3358
3359         return 0;
3360 }
3361
3362 static void gfx_v8_0_cp_enable(struct amdgpu_device *adev, bool enable)
3363 {
3364         gfx_v8_0_cp_gfx_enable(adev, enable);
3365         gfx_v8_0_cp_compute_enable(adev, enable);
3366 }
3367
3368 static int gfx_v8_0_hw_init(void *handle)
3369 {
3370         int r;
3371         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3372
3373         gfx_v8_0_init_golden_registers(adev);
3374
3375         gfx_v8_0_gpu_init(adev);
3376
3377         r = gfx_v8_0_rlc_resume(adev);
3378         if (r)
3379                 return r;
3380
3381         r = gfx_v8_0_cp_resume(adev);
3382         if (r)
3383                 return r;
3384
3385         return r;
3386 }
3387
3388 static int gfx_v8_0_hw_fini(void *handle)
3389 {
3390         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3391
3392         gfx_v8_0_cp_enable(adev, false);
3393         gfx_v8_0_rlc_stop(adev);
3394         gfx_v8_0_cp_compute_fini(adev);
3395
3396         return 0;
3397 }
3398
3399 static int gfx_v8_0_suspend(void *handle)
3400 {
3401         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3402
3403         return gfx_v8_0_hw_fini(adev);
3404 }
3405
3406 static int gfx_v8_0_resume(void *handle)
3407 {
3408         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3409
3410         return gfx_v8_0_hw_init(adev);
3411 }
3412
3413 static bool gfx_v8_0_is_idle(void *handle)
3414 {
3415         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3416
3417         if (REG_GET_FIELD(RREG32(mmGRBM_STATUS), GRBM_STATUS, GUI_ACTIVE))
3418                 return false;
3419         else
3420                 return true;
3421 }
3422
3423 static int gfx_v8_0_wait_for_idle(void *handle)
3424 {
3425         unsigned i;
3426         u32 tmp;
3427         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3428
3429         for (i = 0; i < adev->usec_timeout; i++) {
3430                 /* read MC_STATUS */
3431                 tmp = RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK;
3432
3433                 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
3434                         return 0;
3435                 udelay(1);
3436         }
3437         return -ETIMEDOUT;
3438 }
3439
3440 static void gfx_v8_0_print_status(void *handle)
3441 {
3442         int i;
3443         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3444
3445         dev_info(adev->dev, "GFX 8.x registers\n");
3446         dev_info(adev->dev, "  GRBM_STATUS=0x%08X\n",
3447                  RREG32(mmGRBM_STATUS));
3448         dev_info(adev->dev, "  GRBM_STATUS2=0x%08X\n",
3449                  RREG32(mmGRBM_STATUS2));
3450         dev_info(adev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
3451                  RREG32(mmGRBM_STATUS_SE0));
3452         dev_info(adev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
3453                  RREG32(mmGRBM_STATUS_SE1));
3454         dev_info(adev->dev, "  GRBM_STATUS_SE2=0x%08X\n",
3455                  RREG32(mmGRBM_STATUS_SE2));
3456         dev_info(adev->dev, "  GRBM_STATUS_SE3=0x%08X\n",
3457                  RREG32(mmGRBM_STATUS_SE3));
3458         dev_info(adev->dev, "  CP_STAT = 0x%08x\n", RREG32(mmCP_STAT));
3459         dev_info(adev->dev, "  CP_STALLED_STAT1 = 0x%08x\n",
3460                  RREG32(mmCP_STALLED_STAT1));
3461         dev_info(adev->dev, "  CP_STALLED_STAT2 = 0x%08x\n",
3462                  RREG32(mmCP_STALLED_STAT2));
3463         dev_info(adev->dev, "  CP_STALLED_STAT3 = 0x%08x\n",
3464                  RREG32(mmCP_STALLED_STAT3));
3465         dev_info(adev->dev, "  CP_CPF_BUSY_STAT = 0x%08x\n",
3466                  RREG32(mmCP_CPF_BUSY_STAT));
3467         dev_info(adev->dev, "  CP_CPF_STALLED_STAT1 = 0x%08x\n",
3468                  RREG32(mmCP_CPF_STALLED_STAT1));
3469         dev_info(adev->dev, "  CP_CPF_STATUS = 0x%08x\n", RREG32(mmCP_CPF_STATUS));
3470         dev_info(adev->dev, "  CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(mmCP_CPC_BUSY_STAT));
3471         dev_info(adev->dev, "  CP_CPC_STALLED_STAT1 = 0x%08x\n",
3472                  RREG32(mmCP_CPC_STALLED_STAT1));
3473         dev_info(adev->dev, "  CP_CPC_STATUS = 0x%08x\n", RREG32(mmCP_CPC_STATUS));
3474
3475         for (i = 0; i < 32; i++) {
3476                 dev_info(adev->dev, "  GB_TILE_MODE%d=0x%08X\n",
3477                          i, RREG32(mmGB_TILE_MODE0 + (i * 4)));
3478         }
3479         for (i = 0; i < 16; i++) {
3480                 dev_info(adev->dev, "  GB_MACROTILE_MODE%d=0x%08X\n",
3481                          i, RREG32(mmGB_MACROTILE_MODE0 + (i * 4)));
3482         }
3483         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3484                 dev_info(adev->dev, "  se: %d\n", i);
3485                 gfx_v8_0_select_se_sh(adev, i, 0xffffffff);
3486                 dev_info(adev->dev, "  PA_SC_RASTER_CONFIG=0x%08X\n",
3487                          RREG32(mmPA_SC_RASTER_CONFIG));
3488                 dev_info(adev->dev, "  PA_SC_RASTER_CONFIG_1=0x%08X\n",
3489                          RREG32(mmPA_SC_RASTER_CONFIG_1));
3490         }
3491         gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
3492
3493         dev_info(adev->dev, "  GB_ADDR_CONFIG=0x%08X\n",
3494                  RREG32(mmGB_ADDR_CONFIG));
3495         dev_info(adev->dev, "  HDP_ADDR_CONFIG=0x%08X\n",
3496                  RREG32(mmHDP_ADDR_CONFIG));
3497         dev_info(adev->dev, "  DMIF_ADDR_CALC=0x%08X\n",
3498                  RREG32(mmDMIF_ADDR_CALC));
3499         dev_info(adev->dev, "  SDMA0_TILING_CONFIG=0x%08X\n",
3500                  RREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET));
3501         dev_info(adev->dev, "  SDMA1_TILING_CONFIG=0x%08X\n",
3502                  RREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET));
3503         dev_info(adev->dev, "  UVD_UDEC_ADDR_CONFIG=0x%08X\n",
3504                  RREG32(mmUVD_UDEC_ADDR_CONFIG));
3505         dev_info(adev->dev, "  UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n",
3506                  RREG32(mmUVD_UDEC_DB_ADDR_CONFIG));
3507         dev_info(adev->dev, "  UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n",
3508                  RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG));
3509
3510         dev_info(adev->dev, "  CP_MEQ_THRESHOLDS=0x%08X\n",
3511                  RREG32(mmCP_MEQ_THRESHOLDS));
3512         dev_info(adev->dev, "  SX_DEBUG_1=0x%08X\n",
3513                  RREG32(mmSX_DEBUG_1));
3514         dev_info(adev->dev, "  TA_CNTL_AUX=0x%08X\n",
3515                  RREG32(mmTA_CNTL_AUX));
3516         dev_info(adev->dev, "  SPI_CONFIG_CNTL=0x%08X\n",
3517                  RREG32(mmSPI_CONFIG_CNTL));
3518         dev_info(adev->dev, "  SQ_CONFIG=0x%08X\n",
3519                  RREG32(mmSQ_CONFIG));
3520         dev_info(adev->dev, "  DB_DEBUG=0x%08X\n",
3521                  RREG32(mmDB_DEBUG));
3522         dev_info(adev->dev, "  DB_DEBUG2=0x%08X\n",
3523                  RREG32(mmDB_DEBUG2));
3524         dev_info(adev->dev, "  DB_DEBUG3=0x%08X\n",
3525                  RREG32(mmDB_DEBUG3));
3526         dev_info(adev->dev, "  CB_HW_CONTROL=0x%08X\n",
3527                  RREG32(mmCB_HW_CONTROL));
3528         dev_info(adev->dev, "  SPI_CONFIG_CNTL_1=0x%08X\n",
3529                  RREG32(mmSPI_CONFIG_CNTL_1));
3530         dev_info(adev->dev, "  PA_SC_FIFO_SIZE=0x%08X\n",
3531                  RREG32(mmPA_SC_FIFO_SIZE));
3532         dev_info(adev->dev, "  VGT_NUM_INSTANCES=0x%08X\n",
3533                  RREG32(mmVGT_NUM_INSTANCES));
3534         dev_info(adev->dev, "  CP_PERFMON_CNTL=0x%08X\n",
3535                  RREG32(mmCP_PERFMON_CNTL));
3536         dev_info(adev->dev, "  PA_SC_FORCE_EOV_MAX_CNTS=0x%08X\n",
3537                  RREG32(mmPA_SC_FORCE_EOV_MAX_CNTS));
3538         dev_info(adev->dev, "  VGT_CACHE_INVALIDATION=0x%08X\n",
3539                  RREG32(mmVGT_CACHE_INVALIDATION));
3540         dev_info(adev->dev, "  VGT_GS_VERTEX_REUSE=0x%08X\n",
3541                  RREG32(mmVGT_GS_VERTEX_REUSE));
3542         dev_info(adev->dev, "  PA_SC_LINE_STIPPLE_STATE=0x%08X\n",
3543                  RREG32(mmPA_SC_LINE_STIPPLE_STATE));
3544         dev_info(adev->dev, "  PA_CL_ENHANCE=0x%08X\n",
3545                  RREG32(mmPA_CL_ENHANCE));
3546         dev_info(adev->dev, "  PA_SC_ENHANCE=0x%08X\n",
3547                  RREG32(mmPA_SC_ENHANCE));
3548
3549         dev_info(adev->dev, "  CP_ME_CNTL=0x%08X\n",
3550                  RREG32(mmCP_ME_CNTL));
3551         dev_info(adev->dev, "  CP_MAX_CONTEXT=0x%08X\n",
3552                  RREG32(mmCP_MAX_CONTEXT));
3553         dev_info(adev->dev, "  CP_ENDIAN_SWAP=0x%08X\n",
3554                  RREG32(mmCP_ENDIAN_SWAP));
3555         dev_info(adev->dev, "  CP_DEVICE_ID=0x%08X\n",
3556                  RREG32(mmCP_DEVICE_ID));
3557
3558         dev_info(adev->dev, "  CP_SEM_WAIT_TIMER=0x%08X\n",
3559                  RREG32(mmCP_SEM_WAIT_TIMER));
3560
3561         dev_info(adev->dev, "  CP_RB_WPTR_DELAY=0x%08X\n",
3562                  RREG32(mmCP_RB_WPTR_DELAY));
3563         dev_info(adev->dev, "  CP_RB_VMID=0x%08X\n",
3564                  RREG32(mmCP_RB_VMID));
3565         dev_info(adev->dev, "  CP_RB0_CNTL=0x%08X\n",
3566                  RREG32(mmCP_RB0_CNTL));
3567         dev_info(adev->dev, "  CP_RB0_WPTR=0x%08X\n",
3568                  RREG32(mmCP_RB0_WPTR));
3569         dev_info(adev->dev, "  CP_RB0_RPTR_ADDR=0x%08X\n",
3570                  RREG32(mmCP_RB0_RPTR_ADDR));
3571         dev_info(adev->dev, "  CP_RB0_RPTR_ADDR_HI=0x%08X\n",
3572                  RREG32(mmCP_RB0_RPTR_ADDR_HI));
3573         dev_info(adev->dev, "  CP_RB0_CNTL=0x%08X\n",
3574                  RREG32(mmCP_RB0_CNTL));
3575         dev_info(adev->dev, "  CP_RB0_BASE=0x%08X\n",
3576                  RREG32(mmCP_RB0_BASE));
3577         dev_info(adev->dev, "  CP_RB0_BASE_HI=0x%08X\n",
3578                  RREG32(mmCP_RB0_BASE_HI));
3579         dev_info(adev->dev, "  CP_MEC_CNTL=0x%08X\n",
3580                  RREG32(mmCP_MEC_CNTL));
3581         dev_info(adev->dev, "  CP_CPF_DEBUG=0x%08X\n",
3582                  RREG32(mmCP_CPF_DEBUG));
3583
3584         dev_info(adev->dev, "  SCRATCH_ADDR=0x%08X\n",
3585                  RREG32(mmSCRATCH_ADDR));
3586         dev_info(adev->dev, "  SCRATCH_UMSK=0x%08X\n",
3587                  RREG32(mmSCRATCH_UMSK));
3588
3589         dev_info(adev->dev, "  CP_INT_CNTL_RING0=0x%08X\n",
3590                  RREG32(mmCP_INT_CNTL_RING0));
3591         dev_info(adev->dev, "  RLC_LB_CNTL=0x%08X\n",
3592                  RREG32(mmRLC_LB_CNTL));
3593         dev_info(adev->dev, "  RLC_CNTL=0x%08X\n",
3594                  RREG32(mmRLC_CNTL));
3595         dev_info(adev->dev, "  RLC_CGCG_CGLS_CTRL=0x%08X\n",
3596                  RREG32(mmRLC_CGCG_CGLS_CTRL));
3597         dev_info(adev->dev, "  RLC_LB_CNTR_INIT=0x%08X\n",
3598                  RREG32(mmRLC_LB_CNTR_INIT));
3599         dev_info(adev->dev, "  RLC_LB_CNTR_MAX=0x%08X\n",
3600                  RREG32(mmRLC_LB_CNTR_MAX));
3601         dev_info(adev->dev, "  RLC_LB_INIT_CU_MASK=0x%08X\n",
3602                  RREG32(mmRLC_LB_INIT_CU_MASK));
3603         dev_info(adev->dev, "  RLC_LB_PARAMS=0x%08X\n",
3604                  RREG32(mmRLC_LB_PARAMS));
3605         dev_info(adev->dev, "  RLC_LB_CNTL=0x%08X\n",
3606                  RREG32(mmRLC_LB_CNTL));
3607         dev_info(adev->dev, "  RLC_MC_CNTL=0x%08X\n",
3608                  RREG32(mmRLC_MC_CNTL));
3609         dev_info(adev->dev, "  RLC_UCODE_CNTL=0x%08X\n",
3610                  RREG32(mmRLC_UCODE_CNTL));
3611
3612         mutex_lock(&adev->srbm_mutex);
3613         for (i = 0; i < 16; i++) {
3614                 vi_srbm_select(adev, 0, 0, 0, i);
3615                 dev_info(adev->dev, "  VM %d:\n", i);
3616                 dev_info(adev->dev, "  SH_MEM_CONFIG=0x%08X\n",
3617                          RREG32(mmSH_MEM_CONFIG));
3618                 dev_info(adev->dev, "  SH_MEM_APE1_BASE=0x%08X\n",
3619                          RREG32(mmSH_MEM_APE1_BASE));
3620                 dev_info(adev->dev, "  SH_MEM_APE1_LIMIT=0x%08X\n",
3621                          RREG32(mmSH_MEM_APE1_LIMIT));
3622                 dev_info(adev->dev, "  SH_MEM_BASES=0x%08X\n",
3623                          RREG32(mmSH_MEM_BASES));
3624         }
3625         vi_srbm_select(adev, 0, 0, 0, 0);
3626         mutex_unlock(&adev->srbm_mutex);
3627 }
3628
3629 static int gfx_v8_0_soft_reset(void *handle)
3630 {
3631         u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
3632         u32 tmp;
3633         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3634
3635         /* GRBM_STATUS */
3636         tmp = RREG32(mmGRBM_STATUS);
3637         if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
3638                    GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
3639                    GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
3640                    GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
3641                    GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
3642                    GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) {
3643                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3644                                                 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
3645                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3646                                                 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
3647         }
3648
3649         if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
3650                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3651                                                 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
3652                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
3653                                                 SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
3654         }
3655
3656         /* GRBM_STATUS2 */
3657         tmp = RREG32(mmGRBM_STATUS2);
3658         if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
3659                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3660                                                 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
3661
3662         /* SRBM_STATUS */
3663         tmp = RREG32(mmSRBM_STATUS);
3664         if (REG_GET_FIELD(tmp, SRBM_STATUS, GRBM_RQ_PENDING))
3665                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
3666                                                 SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
3667
3668         if (grbm_soft_reset || srbm_soft_reset) {
3669                 gfx_v8_0_print_status((void *)adev);
3670                 /* stop the rlc */
3671                 gfx_v8_0_rlc_stop(adev);
3672
3673                 /* Disable GFX parsing/prefetching */
3674                 gfx_v8_0_cp_gfx_enable(adev, false);
3675
3676                 /* Disable MEC parsing/prefetching */
3677                 /* XXX todo */
3678
3679                 if (grbm_soft_reset) {
3680                         tmp = RREG32(mmGRBM_SOFT_RESET);
3681                         tmp |= grbm_soft_reset;
3682                         dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
3683                         WREG32(mmGRBM_SOFT_RESET, tmp);
3684                         tmp = RREG32(mmGRBM_SOFT_RESET);
3685
3686                         udelay(50);
3687
3688                         tmp &= ~grbm_soft_reset;
3689                         WREG32(mmGRBM_SOFT_RESET, tmp);
3690                         tmp = RREG32(mmGRBM_SOFT_RESET);
3691                 }
3692
3693                 if (srbm_soft_reset) {
3694                         tmp = RREG32(mmSRBM_SOFT_RESET);
3695                         tmp |= srbm_soft_reset;
3696                         dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
3697                         WREG32(mmSRBM_SOFT_RESET, tmp);
3698                         tmp = RREG32(mmSRBM_SOFT_RESET);
3699
3700                         udelay(50);
3701
3702                         tmp &= ~srbm_soft_reset;
3703                         WREG32(mmSRBM_SOFT_RESET, tmp);
3704                         tmp = RREG32(mmSRBM_SOFT_RESET);
3705                 }
3706                 /* Wait a little for things to settle down */
3707                 udelay(50);
3708                 gfx_v8_0_print_status((void *)adev);
3709         }
3710         return 0;
3711 }
3712
3713 /**
3714  * gfx_v8_0_get_gpu_clock_counter - return GPU clock counter snapshot
3715  *
3716  * @adev: amdgpu_device pointer
3717  *
3718  * Fetches a GPU clock counter snapshot.
3719  * Returns the 64 bit clock counter snapshot.
3720  */
3721 uint64_t gfx_v8_0_get_gpu_clock_counter(struct amdgpu_device *adev)
3722 {
3723         uint64_t clock;
3724
3725         mutex_lock(&adev->gfx.gpu_clock_mutex);
3726         WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
3727         clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
3728                 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
3729         mutex_unlock(&adev->gfx.gpu_clock_mutex);
3730         return clock;
3731 }
3732
3733 static void gfx_v8_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
3734                                           uint32_t vmid,
3735                                           uint32_t gds_base, uint32_t gds_size,
3736                                           uint32_t gws_base, uint32_t gws_size,
3737                                           uint32_t oa_base, uint32_t oa_size)
3738 {
3739         gds_base = gds_base >> AMDGPU_GDS_SHIFT;
3740         gds_size = gds_size >> AMDGPU_GDS_SHIFT;
3741
3742         gws_base = gws_base >> AMDGPU_GWS_SHIFT;
3743         gws_size = gws_size >> AMDGPU_GWS_SHIFT;
3744
3745         oa_base = oa_base >> AMDGPU_OA_SHIFT;
3746         oa_size = oa_size >> AMDGPU_OA_SHIFT;
3747
3748         /* GDS Base */
3749         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3750         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3751                                 WRITE_DATA_DST_SEL(0)));
3752         amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_base);
3753         amdgpu_ring_write(ring, 0);
3754         amdgpu_ring_write(ring, gds_base);
3755
3756         /* GDS Size */
3757         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3758         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3759                                 WRITE_DATA_DST_SEL(0)));
3760         amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_size);
3761         amdgpu_ring_write(ring, 0);
3762         amdgpu_ring_write(ring, gds_size);
3763
3764         /* GWS */
3765         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3766         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3767                                 WRITE_DATA_DST_SEL(0)));
3768         amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].gws);
3769         amdgpu_ring_write(ring, 0);
3770         amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
3771
3772         /* OA */
3773         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3774         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3775                                 WRITE_DATA_DST_SEL(0)));
3776         amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].oa);
3777         amdgpu_ring_write(ring, 0);
3778         amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base));
3779 }
3780
3781 static int gfx_v8_0_early_init(void *handle)
3782 {
3783         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3784
3785         adev->gfx.num_gfx_rings = GFX8_NUM_GFX_RINGS;
3786         adev->gfx.num_compute_rings = GFX8_NUM_COMPUTE_RINGS;
3787         gfx_v8_0_set_ring_funcs(adev);
3788         gfx_v8_0_set_irq_funcs(adev);
3789         gfx_v8_0_set_gds_init(adev);
3790
3791         return 0;
3792 }
3793
3794 static int gfx_v8_0_set_powergating_state(void *handle,
3795                                           enum amd_powergating_state state)
3796 {
3797         return 0;
3798 }
3799
3800 static int gfx_v8_0_set_clockgating_state(void *handle,
3801                                           enum amd_clockgating_state state)
3802 {
3803         return 0;
3804 }
3805
3806 static u32 gfx_v8_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
3807 {
3808         u32 rptr;
3809
3810         rptr = ring->adev->wb.wb[ring->rptr_offs];
3811
3812         return rptr;
3813 }
3814
3815 static u32 gfx_v8_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
3816 {
3817         struct amdgpu_device *adev = ring->adev;
3818         u32 wptr;
3819
3820         if (ring->use_doorbell)
3821                 /* XXX check if swapping is necessary on BE */
3822                 wptr = ring->adev->wb.wb[ring->wptr_offs];
3823         else
3824                 wptr = RREG32(mmCP_RB0_WPTR);
3825
3826         return wptr;
3827 }
3828
3829 static void gfx_v8_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
3830 {
3831         struct amdgpu_device *adev = ring->adev;
3832
3833         if (ring->use_doorbell) {
3834                 /* XXX check if swapping is necessary on BE */
3835                 adev->wb.wb[ring->wptr_offs] = ring->wptr;
3836                 WDOORBELL32(ring->doorbell_index, ring->wptr);
3837         } else {
3838                 WREG32(mmCP_RB0_WPTR, ring->wptr);
3839                 (void)RREG32(mmCP_RB0_WPTR);
3840         }
3841 }
3842
3843 static void gfx_v8_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
3844 {
3845         u32 ref_and_mask, reg_mem_engine;
3846
3847         if (ring->type == AMDGPU_RING_TYPE_COMPUTE) {
3848                 switch (ring->me) {
3849                 case 1:
3850                         ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe;
3851                         break;
3852                 case 2:
3853                         ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe;
3854                         break;
3855                 default:
3856                         return;
3857                 }
3858                 reg_mem_engine = 0;
3859         } else {
3860                 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK;
3861                 reg_mem_engine = WAIT_REG_MEM_ENGINE(1); /* pfp */
3862         }
3863
3864         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3865         amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */
3866                                  WAIT_REG_MEM_FUNCTION(3) |  /* == */
3867                                  reg_mem_engine));
3868         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ);
3869         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE);
3870         amdgpu_ring_write(ring, ref_and_mask);
3871         amdgpu_ring_write(ring, ref_and_mask);
3872         amdgpu_ring_write(ring, 0x20); /* poll interval */
3873 }
3874
3875 static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
3876                                   struct amdgpu_ib *ib)
3877 {
3878         bool need_ctx_switch = ring->current_ctx != ib->ctx;
3879         u32 header, control = 0;
3880         u32 next_rptr = ring->wptr + 5;
3881
3882         /* drop the CE preamble IB for the same context */
3883         if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) && !need_ctx_switch)
3884                 return;
3885
3886         if (need_ctx_switch)
3887                 next_rptr += 2;
3888
3889         next_rptr += 4;
3890         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3891         amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM);
3892         amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3893         amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
3894         amdgpu_ring_write(ring, next_rptr);
3895
3896         /* insert SWITCH_BUFFER packet before first IB in the ring frame */
3897         if (need_ctx_switch) {
3898                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3899                 amdgpu_ring_write(ring, 0);
3900         }
3901
3902         if (ib->flags & AMDGPU_IB_FLAG_CE)
3903                 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
3904         else
3905                 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
3906
3907         control |= ib->length_dw |
3908                 (ib->vm ? (ib->vm->ids[ring->idx].id << 24) : 0);
3909
3910         amdgpu_ring_write(ring, header);
3911         amdgpu_ring_write(ring,
3912 #ifdef __BIG_ENDIAN
3913                           (2 << 0) |
3914 #endif
3915                           (ib->gpu_addr & 0xFFFFFFFC));
3916         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
3917         amdgpu_ring_write(ring, control);
3918 }
3919
3920 static void gfx_v8_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
3921                                   struct amdgpu_ib *ib)
3922 {
3923         u32 header, control = 0;
3924         u32 next_rptr = ring->wptr + 5;
3925
3926         control |= INDIRECT_BUFFER_VALID;
3927
3928         next_rptr += 4;
3929         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3930         amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM);
3931         amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3932         amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
3933         amdgpu_ring_write(ring, next_rptr);
3934
3935         header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
3936
3937         control |= ib->length_dw |
3938                            (ib->vm ? (ib->vm->ids[ring->idx].id << 24) : 0);
3939
3940         amdgpu_ring_write(ring, header);
3941         amdgpu_ring_write(ring,
3942 #ifdef __BIG_ENDIAN
3943                                           (2 << 0) |
3944 #endif
3945                                           (ib->gpu_addr & 0xFFFFFFFC));
3946         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
3947         amdgpu_ring_write(ring, control);
3948 }
3949
3950 static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
3951                                          u64 seq, unsigned flags)
3952 {
3953         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
3954         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
3955
3956         /* EVENT_WRITE_EOP - flush caches, send int */
3957         amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
3958         amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
3959                                  EOP_TC_ACTION_EN |
3960                                  EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
3961                                  EVENT_INDEX(5)));
3962         amdgpu_ring_write(ring, addr & 0xfffffffc);
3963         amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
3964                           DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
3965         amdgpu_ring_write(ring, lower_32_bits(seq));
3966         amdgpu_ring_write(ring, upper_32_bits(seq));
3967
3968 }
3969
3970 /**
3971  * gfx_v8_0_ring_emit_semaphore - emit a semaphore on the CP ring
3972  *
3973  * @ring: amdgpu ring buffer object
3974  * @semaphore: amdgpu semaphore object
3975  * @emit_wait: Is this a sempahore wait?
3976  *
3977  * Emits a semaphore signal/wait packet to the CP ring and prevents the PFP
3978  * from running ahead of semaphore waits.
3979  */
3980 static bool gfx_v8_0_ring_emit_semaphore(struct amdgpu_ring *ring,
3981                                          struct amdgpu_semaphore *semaphore,
3982                                          bool emit_wait)
3983 {
3984         uint64_t addr = semaphore->gpu_addr;
3985         unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
3986
3987         if (ring->adev->asic_type == CHIP_TOPAZ ||
3988             ring->adev->asic_type == CHIP_TONGA ||
3989             ring->adev->asic_type == CHIP_FIJI)
3990                 /* we got a hw semaphore bug in VI TONGA, return false to switch back to sw fence wait */
3991                 return false;
3992         else {
3993                 amdgpu_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 2));
3994                 amdgpu_ring_write(ring, lower_32_bits(addr));
3995                 amdgpu_ring_write(ring, upper_32_bits(addr));
3996                 amdgpu_ring_write(ring, sel);
3997         }
3998
3999         if (emit_wait && (ring->type == AMDGPU_RING_TYPE_GFX)) {
4000                 /* Prevent the PFP from running ahead of the semaphore wait */
4001                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
4002                 amdgpu_ring_write(ring, 0x0);
4003         }
4004
4005         return true;
4006 }
4007
4008 static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
4009                                         unsigned vm_id, uint64_t pd_addr)
4010 {
4011         int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
4012         uint32_t seq = ring->fence_drv.sync_seq[ring->idx];
4013         uint64_t addr = ring->fence_drv.gpu_addr;
4014
4015         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
4016         amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
4017                  WAIT_REG_MEM_FUNCTION(3))); /* equal */
4018         amdgpu_ring_write(ring, addr & 0xfffffffc);
4019         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
4020         amdgpu_ring_write(ring, seq);
4021         amdgpu_ring_write(ring, 0xffffffff);
4022         amdgpu_ring_write(ring, 4); /* poll interval */
4023
4024         if (usepfp) {
4025                 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
4026                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
4027                 amdgpu_ring_write(ring, 0);
4028                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
4029                 amdgpu_ring_write(ring, 0);
4030         }
4031
4032         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4033         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
4034                                  WRITE_DATA_DST_SEL(0)) |
4035                                  WR_CONFIRM);
4036         if (vm_id < 8) {
4037                 amdgpu_ring_write(ring,
4038                                   (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
4039         } else {
4040                 amdgpu_ring_write(ring,
4041                                   (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
4042         }
4043         amdgpu_ring_write(ring, 0);
4044         amdgpu_ring_write(ring, pd_addr >> 12);
4045
4046         /* bits 0-15 are the VM contexts0-15 */
4047         /* invalidate the cache */
4048         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4049         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4050                                  WRITE_DATA_DST_SEL(0)));
4051         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
4052         amdgpu_ring_write(ring, 0);
4053         amdgpu_ring_write(ring, 1 << vm_id);
4054
4055         /* wait for the invalidate to complete */
4056         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
4057         amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */
4058                                  WAIT_REG_MEM_FUNCTION(0) |  /* always */
4059                                  WAIT_REG_MEM_ENGINE(0))); /* me */
4060         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
4061         amdgpu_ring_write(ring, 0);
4062         amdgpu_ring_write(ring, 0); /* ref */
4063         amdgpu_ring_write(ring, 0); /* mask */
4064         amdgpu_ring_write(ring, 0x20); /* poll interval */
4065
4066         /* compute doesn't have PFP */
4067         if (usepfp) {
4068                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
4069                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
4070                 amdgpu_ring_write(ring, 0x0);
4071                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
4072                 amdgpu_ring_write(ring, 0);
4073                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
4074                 amdgpu_ring_write(ring, 0);
4075         }
4076 }
4077
4078 static bool gfx_v8_0_ring_is_lockup(struct amdgpu_ring *ring)
4079 {
4080         if (gfx_v8_0_is_idle(ring->adev)) {
4081                 amdgpu_ring_lockup_update(ring);
4082                 return false;
4083         }
4084         return amdgpu_ring_test_lockup(ring);
4085 }
4086
4087 static u32 gfx_v8_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
4088 {
4089         return ring->adev->wb.wb[ring->rptr_offs];
4090 }
4091
4092 static u32 gfx_v8_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
4093 {
4094         return ring->adev->wb.wb[ring->wptr_offs];
4095 }
4096
4097 static void gfx_v8_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
4098 {
4099         struct amdgpu_device *adev = ring->adev;
4100
4101         /* XXX check if swapping is necessary on BE */
4102         adev->wb.wb[ring->wptr_offs] = ring->wptr;
4103         WDOORBELL32(ring->doorbell_index, ring->wptr);
4104 }
4105
4106 static void gfx_v8_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
4107                                              u64 addr, u64 seq,
4108                                              unsigned flags)
4109 {
4110         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
4111         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
4112
4113         /* RELEASE_MEM - flush caches, send int */
4114         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));
4115         amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
4116                                  EOP_TC_ACTION_EN |
4117                                  EOP_TC_WB_ACTION_EN |
4118                                  EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
4119                                  EVENT_INDEX(5)));
4120         amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
4121         amdgpu_ring_write(ring, addr & 0xfffffffc);
4122         amdgpu_ring_write(ring, upper_32_bits(addr));
4123         amdgpu_ring_write(ring, lower_32_bits(seq));
4124         amdgpu_ring_write(ring, upper_32_bits(seq));
4125 }
4126
4127 static void gfx_v8_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
4128                                                  enum amdgpu_interrupt_state state)
4129 {
4130         u32 cp_int_cntl;
4131
4132         switch (state) {
4133         case AMDGPU_IRQ_STATE_DISABLE:
4134                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4135                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4136                                             TIME_STAMP_INT_ENABLE, 0);
4137                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4138                 break;
4139         case AMDGPU_IRQ_STATE_ENABLE:
4140                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4141                 cp_int_cntl =
4142                         REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4143                                       TIME_STAMP_INT_ENABLE, 1);
4144                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4145                 break;
4146         default:
4147                 break;
4148         }
4149 }
4150
4151 static void gfx_v8_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
4152                                                      int me, int pipe,
4153                                                      enum amdgpu_interrupt_state state)
4154 {
4155         u32 mec_int_cntl, mec_int_cntl_reg;
4156
4157         /*
4158          * amdgpu controls only pipe 0 of MEC1. That's why this function only
4159          * handles the setting of interrupts for this specific pipe. All other
4160          * pipes' interrupts are set by amdkfd.
4161          */
4162
4163         if (me == 1) {
4164                 switch (pipe) {
4165                 case 0:
4166                         mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL;
4167                         break;
4168                 default:
4169                         DRM_DEBUG("invalid pipe %d\n", pipe);
4170                         return;
4171                 }
4172         } else {
4173                 DRM_DEBUG("invalid me %d\n", me);
4174                 return;
4175         }
4176
4177         switch (state) {
4178         case AMDGPU_IRQ_STATE_DISABLE:
4179                 mec_int_cntl = RREG32(mec_int_cntl_reg);
4180                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4181                                              TIME_STAMP_INT_ENABLE, 0);
4182                 WREG32(mec_int_cntl_reg, mec_int_cntl);
4183                 break;
4184         case AMDGPU_IRQ_STATE_ENABLE:
4185                 mec_int_cntl = RREG32(mec_int_cntl_reg);
4186                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4187                                              TIME_STAMP_INT_ENABLE, 1);
4188                 WREG32(mec_int_cntl_reg, mec_int_cntl);
4189                 break;
4190         default:
4191                 break;
4192         }
4193 }
4194
4195 static int gfx_v8_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
4196                                              struct amdgpu_irq_src *source,
4197                                              unsigned type,
4198                                              enum amdgpu_interrupt_state state)
4199 {
4200         u32 cp_int_cntl;
4201
4202         switch (state) {
4203         case AMDGPU_IRQ_STATE_DISABLE:
4204                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4205                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4206                                             PRIV_REG_INT_ENABLE, 0);
4207                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4208                 break;
4209         case AMDGPU_IRQ_STATE_ENABLE:
4210                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4211                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4212                                             PRIV_REG_INT_ENABLE, 0);
4213                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4214                 break;
4215         default:
4216                 break;
4217         }
4218
4219         return 0;
4220 }
4221
4222 static int gfx_v8_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
4223                                               struct amdgpu_irq_src *source,
4224                                               unsigned type,
4225                                               enum amdgpu_interrupt_state state)
4226 {
4227         u32 cp_int_cntl;
4228
4229         switch (state) {
4230         case AMDGPU_IRQ_STATE_DISABLE:
4231                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4232                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4233                                             PRIV_INSTR_INT_ENABLE, 0);
4234                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4235                 break;
4236         case AMDGPU_IRQ_STATE_ENABLE:
4237                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4238                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4239                                             PRIV_INSTR_INT_ENABLE, 1);
4240                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4241                 break;
4242         default:
4243                 break;
4244         }
4245
4246         return 0;
4247 }
4248
4249 static int gfx_v8_0_set_eop_interrupt_state(struct amdgpu_device *adev,
4250                                             struct amdgpu_irq_src *src,
4251                                             unsigned type,
4252                                             enum amdgpu_interrupt_state state)
4253 {
4254         switch (type) {
4255         case AMDGPU_CP_IRQ_GFX_EOP:
4256                 gfx_v8_0_set_gfx_eop_interrupt_state(adev, state);
4257                 break;
4258         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
4259                 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
4260                 break;
4261         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
4262                 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
4263                 break;
4264         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
4265                 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
4266                 break;
4267         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
4268                 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
4269                 break;
4270         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
4271                 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
4272                 break;
4273         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
4274                 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
4275                 break;
4276         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
4277                 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
4278                 break;
4279         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
4280                 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
4281                 break;
4282         default:
4283                 break;
4284         }
4285         return 0;
4286 }
4287
4288 static int gfx_v8_0_eop_irq(struct amdgpu_device *adev,
4289                             struct amdgpu_irq_src *source,
4290                             struct amdgpu_iv_entry *entry)
4291 {
4292         int i;
4293         u8 me_id, pipe_id, queue_id;
4294         struct amdgpu_ring *ring;
4295
4296         DRM_DEBUG("IH: CP EOP\n");
4297         me_id = (entry->ring_id & 0x0c) >> 2;
4298         pipe_id = (entry->ring_id & 0x03) >> 0;
4299         queue_id = (entry->ring_id & 0x70) >> 4;
4300
4301         switch (me_id) {
4302         case 0:
4303                 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
4304                 break;
4305         case 1:
4306         case 2:
4307                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4308                         ring = &adev->gfx.compute_ring[i];
4309                         /* Per-queue interrupt is supported for MEC starting from VI.
4310                           * The interrupt can only be enabled/disabled per pipe instead of per queue.
4311                           */
4312                         if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
4313                                 amdgpu_fence_process(ring);
4314                 }
4315                 break;
4316         }
4317         return 0;
4318 }
4319
4320 static int gfx_v8_0_priv_reg_irq(struct amdgpu_device *adev,
4321                                  struct amdgpu_irq_src *source,
4322                                  struct amdgpu_iv_entry *entry)
4323 {
4324         DRM_ERROR("Illegal register access in command stream\n");
4325         schedule_work(&adev->reset_work);
4326         return 0;
4327 }
4328
4329 static int gfx_v8_0_priv_inst_irq(struct amdgpu_device *adev,
4330                                   struct amdgpu_irq_src *source,
4331                                   struct amdgpu_iv_entry *entry)
4332 {
4333         DRM_ERROR("Illegal instruction in command stream\n");
4334         schedule_work(&adev->reset_work);
4335         return 0;
4336 }
4337
4338 const struct amd_ip_funcs gfx_v8_0_ip_funcs = {
4339         .early_init = gfx_v8_0_early_init,
4340         .late_init = NULL,
4341         .sw_init = gfx_v8_0_sw_init,
4342         .sw_fini = gfx_v8_0_sw_fini,
4343         .hw_init = gfx_v8_0_hw_init,
4344         .hw_fini = gfx_v8_0_hw_fini,
4345         .suspend = gfx_v8_0_suspend,
4346         .resume = gfx_v8_0_resume,
4347         .is_idle = gfx_v8_0_is_idle,
4348         .wait_for_idle = gfx_v8_0_wait_for_idle,
4349         .soft_reset = gfx_v8_0_soft_reset,
4350         .print_status = gfx_v8_0_print_status,
4351         .set_clockgating_state = gfx_v8_0_set_clockgating_state,
4352         .set_powergating_state = gfx_v8_0_set_powergating_state,
4353 };
4354
4355 static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = {
4356         .get_rptr = gfx_v8_0_ring_get_rptr_gfx,
4357         .get_wptr = gfx_v8_0_ring_get_wptr_gfx,
4358         .set_wptr = gfx_v8_0_ring_set_wptr_gfx,
4359         .parse_cs = NULL,
4360         .emit_ib = gfx_v8_0_ring_emit_ib_gfx,
4361         .emit_fence = gfx_v8_0_ring_emit_fence_gfx,
4362         .emit_semaphore = gfx_v8_0_ring_emit_semaphore,
4363         .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
4364         .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
4365         .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
4366         .test_ring = gfx_v8_0_ring_test_ring,
4367         .test_ib = gfx_v8_0_ring_test_ib,
4368         .is_lockup = gfx_v8_0_ring_is_lockup,
4369         .insert_nop = amdgpu_ring_insert_nop,
4370 };
4371
4372 static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = {
4373         .get_rptr = gfx_v8_0_ring_get_rptr_compute,
4374         .get_wptr = gfx_v8_0_ring_get_wptr_compute,
4375         .set_wptr = gfx_v8_0_ring_set_wptr_compute,
4376         .parse_cs = NULL,
4377         .emit_ib = gfx_v8_0_ring_emit_ib_compute,
4378         .emit_fence = gfx_v8_0_ring_emit_fence_compute,
4379         .emit_semaphore = gfx_v8_0_ring_emit_semaphore,
4380         .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
4381         .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
4382         .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
4383         .test_ring = gfx_v8_0_ring_test_ring,
4384         .test_ib = gfx_v8_0_ring_test_ib,
4385         .is_lockup = gfx_v8_0_ring_is_lockup,
4386         .insert_nop = amdgpu_ring_insert_nop,
4387 };
4388
4389 static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev)
4390 {
4391         int i;
4392
4393         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4394                 adev->gfx.gfx_ring[i].funcs = &gfx_v8_0_ring_funcs_gfx;
4395
4396         for (i = 0; i < adev->gfx.num_compute_rings; i++)
4397                 adev->gfx.compute_ring[i].funcs = &gfx_v8_0_ring_funcs_compute;
4398 }
4399
4400 static const struct amdgpu_irq_src_funcs gfx_v8_0_eop_irq_funcs = {
4401         .set = gfx_v8_0_set_eop_interrupt_state,
4402         .process = gfx_v8_0_eop_irq,
4403 };
4404
4405 static const struct amdgpu_irq_src_funcs gfx_v8_0_priv_reg_irq_funcs = {
4406         .set = gfx_v8_0_set_priv_reg_fault_state,
4407         .process = gfx_v8_0_priv_reg_irq,
4408 };
4409
4410 static const struct amdgpu_irq_src_funcs gfx_v8_0_priv_inst_irq_funcs = {
4411         .set = gfx_v8_0_set_priv_inst_fault_state,
4412         .process = gfx_v8_0_priv_inst_irq,
4413 };
4414
4415 static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev)
4416 {
4417         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
4418         adev->gfx.eop_irq.funcs = &gfx_v8_0_eop_irq_funcs;
4419
4420         adev->gfx.priv_reg_irq.num_types = 1;
4421         adev->gfx.priv_reg_irq.funcs = &gfx_v8_0_priv_reg_irq_funcs;
4422
4423         adev->gfx.priv_inst_irq.num_types = 1;
4424         adev->gfx.priv_inst_irq.funcs = &gfx_v8_0_priv_inst_irq_funcs;
4425 }
4426
4427 static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev)
4428 {
4429         /* init asci gds info */
4430         adev->gds.mem.total_size = RREG32(mmGDS_VMID0_SIZE);
4431         adev->gds.gws.total_size = 64;
4432         adev->gds.oa.total_size = 16;
4433
4434         if (adev->gds.mem.total_size == 64 * 1024) {
4435                 adev->gds.mem.gfx_partition_size = 4096;
4436                 adev->gds.mem.cs_partition_size = 4096;
4437
4438                 adev->gds.gws.gfx_partition_size = 4;
4439                 adev->gds.gws.cs_partition_size = 4;
4440
4441                 adev->gds.oa.gfx_partition_size = 4;
4442                 adev->gds.oa.cs_partition_size = 1;
4443         } else {
4444                 adev->gds.mem.gfx_partition_size = 1024;
4445                 adev->gds.mem.cs_partition_size = 1024;
4446
4447                 adev->gds.gws.gfx_partition_size = 16;
4448                 adev->gds.gws.cs_partition_size = 16;
4449
4450                 adev->gds.oa.gfx_partition_size = 4;
4451                 adev->gds.oa.cs_partition_size = 4;
4452         }
4453 }
4454
4455 static u32 gfx_v8_0_get_cu_active_bitmap(struct amdgpu_device *adev,
4456                 u32 se, u32 sh)
4457 {
4458         u32 mask = 0, tmp, tmp1;
4459         int i;
4460
4461         gfx_v8_0_select_se_sh(adev, se, sh);
4462         tmp = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG);
4463         tmp1 = RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
4464         gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
4465
4466         tmp &= 0xffff0000;
4467
4468         tmp |= tmp1;
4469         tmp >>= 16;
4470
4471         for (i = 0; i < adev->gfx.config.max_cu_per_sh; i ++) {
4472                 mask <<= 1;
4473                 mask |= 1;
4474         }
4475
4476         return (~tmp) & mask;
4477 }
4478
4479 int gfx_v8_0_get_cu_info(struct amdgpu_device *adev,
4480                                                  struct amdgpu_cu_info *cu_info)
4481 {
4482         int i, j, k, counter, active_cu_number = 0;
4483         u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
4484
4485         if (!adev || !cu_info)
4486                 return -EINVAL;
4487
4488         mutex_lock(&adev->grbm_idx_mutex);
4489         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4490                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4491                         mask = 1;
4492                         ao_bitmap = 0;
4493                         counter = 0;
4494                         bitmap = gfx_v8_0_get_cu_active_bitmap(adev, i, j);
4495                         cu_info->bitmap[i][j] = bitmap;
4496
4497                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
4498                                 if (bitmap & mask) {
4499                                         if (counter < 2)
4500                                                 ao_bitmap |= mask;
4501                                         counter ++;
4502                                 }
4503                                 mask <<= 1;
4504                         }
4505                         active_cu_number += counter;
4506                         ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
4507                 }
4508         }
4509
4510         cu_info->number = active_cu_number;
4511         cu_info->ao_cu_mask = ao_cu_mask;
4512         mutex_unlock(&adev->grbm_idx_mutex);
4513         return 0;
4514 }