drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include "drmP.h"
  25 #include "amdgpu.h"
  26 #include "amdgpu_gfx.h"
  27 #include "vi.h"
  28 #include "vid.h"
  29 #include "amdgpu_ucode.h"
  30 #include "clearstate_vi.h"
  31
  32 #include "gmc/gmc_8_2_d.h"
  33 #include "gmc/gmc_8_2_sh_mask.h"
  34
  35 #include "oss/oss_3_0_d.h"
  36 #include "oss/oss_3_0_sh_mask.h"
  37
  38 #include "bif/bif_5_0_d.h"
  39 #include "bif/bif_5_0_sh_mask.h"
  40
  41 #include "gca/gfx_8_0_d.h"
  42 #include "gca/gfx_8_0_enum.h"
  43 #include "gca/gfx_8_0_sh_mask.h"
  44 #include "gca/gfx_8_0_enum.h"
  45
  46 #include "uvd/uvd_5_0_d.h"
  47 #include "uvd/uvd_5_0_sh_mask.h"
  48
  49 #include "dce/dce_10_0_d.h"
  50 #include "dce/dce_10_0_sh_mask.h"
  51
  52 #define GFX8_NUM_GFX_RINGS     1
  53 #define GFX8_NUM_COMPUTE_RINGS 8
  54
  55 #define TOPAZ_GB_ADDR_CONFIG_GOLDEN 0x22010001
  56 #define CARRIZO_GB_ADDR_CONFIG_GOLDEN 0x22010001
  57 #define TONGA_GB_ADDR_CONFIG_GOLDEN 0x22011003
  58
  59 #define ARRAY_MODE(x)                                   ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT)
  60 #define PIPE_CONFIG(x)                                  ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT)
  61 #define TILE_SPLIT(x)                                   ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT)
  62 #define MICRO_TILE_MODE_NEW(x)                          ((x) << GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT)
  63 #define SAMPLE_SPLIT(x)                                 ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT)
  64 #define BANK_WIDTH(x)                                   ((x) << GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT)
  65 #define BANK_HEIGHT(x)                                  ((x) << GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT)
  66 #define MACRO_TILE_ASPECT(x)                            ((x) << GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT)
  67 #define NUM_BANKS(x)                                    ((x) << GB_MACROTILE_MODE0__NUM_BANKS__SHIFT)
  68
  69 MODULE_FIRMWARE("amdgpu/carrizo_ce.bin");
  70 MODULE_FIRMWARE("amdgpu/carrizo_pfp.bin");
  71 MODULE_FIRMWARE("amdgpu/carrizo_me.bin");
  72 MODULE_FIRMWARE("amdgpu/carrizo_mec.bin");
  73 MODULE_FIRMWARE("amdgpu/carrizo_mec2.bin");
  74 MODULE_FIRMWARE("amdgpu/carrizo_rlc.bin");
  75
  76 MODULE_FIRMWARE("amdgpu/tonga_ce.bin");
  77 MODULE_FIRMWARE("amdgpu/tonga_pfp.bin");
  78 MODULE_FIRMWARE("amdgpu/tonga_me.bin");
  79 MODULE_FIRMWARE("amdgpu/tonga_mec.bin");
  80 MODULE_FIRMWARE("amdgpu/tonga_mec2.bin");
  81 MODULE_FIRMWARE("amdgpu/tonga_rlc.bin");
  82
  83 MODULE_FIRMWARE("amdgpu/topaz_ce.bin");
  84 MODULE_FIRMWARE("amdgpu/topaz_pfp.bin");
  85 MODULE_FIRMWARE("amdgpu/topaz_me.bin");
  86 MODULE_FIRMWARE("amdgpu/topaz_mec.bin");
  87 MODULE_FIRMWARE("amdgpu/topaz_mec2.bin");
  88 MODULE_FIRMWARE("amdgpu/topaz_rlc.bin");
  89
  90 static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
  91 {
  92         {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
  93         {mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1},
  94         {mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2},
  95         {mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3},
  96         {mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4},
  97         {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5},
  98         {mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6},
  99         {mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7},
 100         {mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8},
 101         {mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9},
 102         {mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10},
 103         {mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11},
 104         {mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12},
 105         {mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13},
 106         {mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14},
 107         {mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15}
 108 };
 109
 110 static const u32 golden_settings_tonga_a11[] =
 111 {
 112         mmCB_HW_CONTROL, 0xfffdf3cf, 0x00007208,
 113         mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
 114         mmDB_DEBUG2, 0xf00fffff, 0x00000400,
 115         mmGB_GPU_ID, 0x0000000f, 0x00000000,
 116         mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
 117         mmPA_SC_FIFO_DEPTH_CNTL, 0x000003ff, 0x000000fc,
 118         mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
 119         mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
 120         mmTCC_CTRL, 0x00100000, 0xf31fff7f,
 121         mmTCP_ADDR_CONFIG, 0x000003ff, 0x000002fb,
 122         mmTCP_CHAN_STEER_HI, 0xffffffff, 0x0000543b,
 123         mmTCP_CHAN_STEER_LO, 0xffffffff, 0xa9210876,
 124 };
 125
 126 static const u32 tonga_golden_common_all[] =
 127 {
 128         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 129         mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012,
 130         mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002A,
 131         mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
 132         mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
 133         mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
 134         mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
 135         mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
 136 };
 137
 138 static const u32 tonga_mgcg_cgcg_init[] =
 139 {
 140         mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
 141         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 142         mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 143         mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
 144         mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
 145         mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
 146         mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
 147         mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
 148         mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
 149         mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
 150         mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
 151         mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
 152         mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
 153         mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
 154         mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
 155         mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
 156         mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
 157         mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
 158         mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
 159         mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
 160         mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
 161         mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
 162         mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
 163         mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
 164         mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
 165         mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
 166         mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
 167         mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 168         mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 169         mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
 170         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 171         mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 172         mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 173         mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
 174         mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 175         mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 176         mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 177         mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 178         mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
 179         mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 180         mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 181         mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 182         mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 183         mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
 184         mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 185         mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 186         mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 187         mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 188         mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
 189         mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 190         mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 191         mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 192         mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 193         mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
 194         mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 195         mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 196         mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 197         mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 198         mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
 199         mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 200         mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 201         mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 202         mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 203         mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
 204         mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 205         mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 206         mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 207         mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 208         mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
 209         mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 210         mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 211         mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
 212         mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
 213         mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
 214         mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
 215 };
 216
 217 static const u32 golden_settings_iceland_a11[] =
 218 {
 219         mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
 220         mmDB_DEBUG2, 0xf00fffff, 0x00000400,
 221         mmDB_DEBUG3, 0xc0000000, 0xc0000000,
 222         mmGB_GPU_ID, 0x0000000f, 0x00000000,
 223         mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
 224         mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
 225         mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x00000002,
 226         mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000,
 227         mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
 228         mmTCC_CTRL, 0x00100000, 0xf31fff7f,
 229         mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f1,
 230         mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
 231         mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010,
 232 };
 233
 234 static const u32 iceland_golden_common_all[] =
 235 {
 236         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 237         mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
 238         mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
 239         mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
 240         mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
 241         mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
 242         mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
 243         mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
 244 };
 245
 246 static const u32 iceland_mgcg_cgcg_init[] =
 247 {
 248         mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
 249         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 250         mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 251         mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
 252         mmCGTT_CP_CLK_CTRL, 0xffffffff, 0xc0000100,
 253         mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0xc0000100,
 254         mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0xc0000100,
 255         mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
 256         mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
 257         mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
 258         mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
 259         mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
 260         mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
 261         mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
 262         mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
 263         mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
 264         mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
 265         mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
 266         mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
 267         mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
 268         mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
 269         mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
 270         mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0xff000100,
 271         mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
 272         mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
 273         mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
 274         mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
 275         mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 276         mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 277         mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
 278         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 279         mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 280         mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 281         mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
 282         mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 283         mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 284         mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 285         mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 286         mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
 287         mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 288         mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 289         mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 290         mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 291         mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
 292         mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 293         mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 294         mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 295         mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 296         mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
 297         mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 298         mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 299         mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 300         mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 301         mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
 302         mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 303         mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 304         mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 305         mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 306         mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
 307         mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 308         mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 309         mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
 310         mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
 311         mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
 312 };
 313
 314 static const u32 cz_golden_settings_a11[] =
 315 {
 316         mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
 317         mmDB_DEBUG2, 0xf00fffff, 0x00000400,
 318         mmGB_GPU_ID, 0x0000000f, 0x00000000,
 319         mmPA_SC_ENHANCE, 0xffffffff, 0x00000001,
 320         mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
 321         mmTA_CNTL_AUX, 0x000f000f, 0x00010000,
 322         mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f3,
 323         mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00001302
 324 };
 325
 326 static const u32 cz_golden_common_all[] =
 327 {
 328         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 329         mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
 330         mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
 331         mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
 332         mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
 333         mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
 334         mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
 335         mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
 336 };
 337
 338 static const u32 cz_mgcg_cgcg_init[] =
 339 {
 340         mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
 341         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 342         mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 343         mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
 344         mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
 345         mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
 346         mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x00000100,
 347         mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
 348         mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
 349         mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
 350         mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
 351         mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
 352         mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
 353         mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
 354         mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
 355         mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
 356         mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
 357         mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
 358         mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
 359         mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
 360         mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
 361         mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
 362         mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
 363         mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
 364         mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
 365         mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
 366         mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
 367         mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 368         mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
 369         mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
 370         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
 371         mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 372         mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 373         mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
 374         mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 375         mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 376         mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 377         mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 378         mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
 379         mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 380         mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 381         mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 382         mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 383         mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
 384         mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 385         mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 386         mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 387         mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 388         mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
 389         mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 390         mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 391         mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 392         mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 393         mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
 394         mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 395         mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 396         mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 397         mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 398         mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
 399         mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 400         mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 401         mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 402         mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 403         mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
 404         mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 405         mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 406         mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
 407         mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
 408         mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
 409         mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
 410         mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
 411         mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
 412         mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
 413         mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
 414         mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
 415 };
 416
 417 static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev);
 418 static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev);
 419 static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev);
 420
 421 static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev)
 422 {
 423         switch (adev->asic_type) {
 424         case CHIP_TOPAZ:
 425                 amdgpu_program_register_sequence(adev,
 426                                                  iceland_mgcg_cgcg_init,
 427                                                  (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
 428                 amdgpu_program_register_sequence(adev,
 429                                                  golden_settings_iceland_a11,
 430                                                  (const u32)ARRAY_SIZE(golden_settings_iceland_a11));
 431                 amdgpu_program_register_sequence(adev,
 432                                                  iceland_golden_common_all,
 433                                                  (const u32)ARRAY_SIZE(iceland_golden_common_all));
 434                 break;
 435         case CHIP_TONGA:
 436                 amdgpu_program_register_sequence(adev,
 437                                                  tonga_mgcg_cgcg_init,
 438                                                  (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
 439                 amdgpu_program_register_sequence(adev,
 440                                                  golden_settings_tonga_a11,
 441                                                  (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
 442                 amdgpu_program_register_sequence(adev,
 443                                                  tonga_golden_common_all,
 444                                                  (const u32)ARRAY_SIZE(tonga_golden_common_all));
 445                 break;
 446         case CHIP_CARRIZO:
 447                 amdgpu_program_register_sequence(adev,
 448                                                  cz_mgcg_cgcg_init,
 449                                                  (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
 450                 amdgpu_program_register_sequence(adev,
 451                                                  cz_golden_settings_a11,
 452                                                  (const u32)ARRAY_SIZE(cz_golden_settings_a11));
 453                 amdgpu_program_register_sequence(adev,
 454                                                  cz_golden_common_all,
 455                                                  (const u32)ARRAY_SIZE(cz_golden_common_all));
 456                 break;
 457         default:
 458                 break;
 459         }
 460 }
 461
 462 static void gfx_v8_0_scratch_init(struct amdgpu_device *adev)
 463 {
 464         int i;
 465
 466         adev->gfx.scratch.num_reg = 7;
 467         adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
 468         for (i = 0; i < adev->gfx.scratch.num_reg; i++) {
 469                 adev->gfx.scratch.free[i] = true;
 470                 adev->gfx.scratch.reg[i] = adev->gfx.scratch.reg_base + i;
 471         }
 472 }
 473
 474 static int gfx_v8_0_ring_test_ring(struct amdgpu_ring *ring)
 475 {
 476         struct amdgpu_device *adev = ring->adev;
 477         uint32_t scratch;
 478         uint32_t tmp = 0;
 479         unsigned i;
 480         int r;
 481
 482         r = amdgpu_gfx_scratch_get(adev, &scratch);
 483         if (r) {
 484                 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
 485                 return r;
 486         }
 487         WREG32(scratch, 0xCAFEDEAD);
 488         r = amdgpu_ring_lock(ring, 3);
 489         if (r) {
 490                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
 491                           ring->idx, r);
 492                 amdgpu_gfx_scratch_free(adev, scratch);
 493                 return r;
 494         }
 495         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
 496         amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
 497         amdgpu_ring_write(ring, 0xDEADBEEF);
 498         amdgpu_ring_unlock_commit(ring);
 499
 500         for (i = 0; i < adev->usec_timeout; i++) {
 501                 tmp = RREG32(scratch);
 502                 if (tmp == 0xDEADBEEF)
 503                         break;
 504                 DRM_UDELAY(1);
 505         }
 506         if (i < adev->usec_timeout) {
 507                 DRM_INFO("ring test on %d succeeded in %d usecs\n",
 508                          ring->idx, i);
 509         } else {
 510                 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
 511                           ring->idx, scratch, tmp);
 512                 r = -EINVAL;
 513         }
 514         amdgpu_gfx_scratch_free(adev, scratch);
 515         return r;
 516 }
 517
 518 static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring)
 519 {
 520         struct amdgpu_device *adev = ring->adev;
 521         struct amdgpu_ib ib;
 522         uint32_t scratch;
 523         uint32_t tmp = 0;
 524         unsigned i;
 525         int r;
 526
 527         r = amdgpu_gfx_scratch_get(adev, &scratch);
 528         if (r) {
 529                 DRM_ERROR("amdgpu: failed to get scratch reg (%d).\n", r);
 530                 return r;
 531         }
 532         WREG32(scratch, 0xCAFEDEAD);
 533         r = amdgpu_ib_get(ring, NULL, 256, &ib);
 534         if (r) {
 535                 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
 536                 amdgpu_gfx_scratch_free(adev, scratch);
 537                 return r;
 538         }
 539         ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
 540         ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
 541         ib.ptr[2] = 0xDEADBEEF;
 542         ib.length_dw = 3;
 543         r = amdgpu_ib_schedule(adev, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED);
 544         if (r) {
 545                 amdgpu_gfx_scratch_free(adev, scratch);
 546                 amdgpu_ib_free(adev, &ib);
 547                 DRM_ERROR("amdgpu: failed to schedule ib (%d).\n", r);
 548                 return r;
 549         }
 550         r = amdgpu_fence_wait(ib.fence, false);
 551         if (r) {
 552                 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
 553                 amdgpu_gfx_scratch_free(adev, scratch);
 554                 amdgpu_ib_free(adev, &ib);
 555                 return r;
 556         }
 557         for (i = 0; i < adev->usec_timeout; i++) {
 558                 tmp = RREG32(scratch);
 559                 if (tmp == 0xDEADBEEF)
 560                         break;
 561                 DRM_UDELAY(1);
 562         }
 563         if (i < adev->usec_timeout) {
 564                 DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
 565                          ib.fence->ring->idx, i);
 566         } else {
 567                 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
 568                           scratch, tmp);
 569                 r = -EINVAL;
 570         }
 571         amdgpu_gfx_scratch_free(adev, scratch);
 572         amdgpu_ib_free(adev, &ib);
 573         return r;
 574 }
 575
 576 static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
 577 {
 578         const char *chip_name;
 579         char fw_name[30];
 580         int err;
 581         struct amdgpu_firmware_info *info = NULL;
 582         const struct common_firmware_header *header = NULL;
 583
 584         DRM_DEBUG("\n");
 585
 586         switch (adev->asic_type) {
 587         case CHIP_TOPAZ:
 588                 chip_name = "topaz";
 589                 break;
 590         case CHIP_TONGA:
 591                 chip_name = "tonga";
 592                 break;
 593         case CHIP_CARRIZO:
 594                 chip_name = "carrizo";
 595                 break;
 596         default:
 597                 BUG();
 598         }
 599
 600         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
 601         err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
 602         if (err)
 603                 goto out;
 604         err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
 605         if (err)
 606                 goto out;
 607
 608         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
 609         err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
 610         if (err)
 611                 goto out;
 612         err = amdgpu_ucode_validate(adev->gfx.me_fw);
 613         if (err)
 614                 goto out;
 615
 616         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
 617         err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
 618         if (err)
 619                 goto out;
 620         err = amdgpu_ucode_validate(adev->gfx.ce_fw);
 621         if (err)
 622                 goto out;
 623
 624         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
 625         err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
 626         if (err)
 627                 goto out;
 628         err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
 629
 630         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
 631         err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
 632         if (err)
 633                 goto out;
 634         err = amdgpu_ucode_validate(adev->gfx.mec_fw);
 635         if (err)
 636                 goto out;
 637
 638         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
 639         err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
 640         if (!err) {
 641                 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
 642                 if (err)
 643                         goto out;
 644         } else {
 645                 err = 0;
 646                 adev->gfx.mec2_fw = NULL;
 647         }
 648
 649         if (adev->firmware.smu_load) {
 650                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
 651                 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
 652                 info->fw = adev->gfx.pfp_fw;
 653                 header = (const struct common_firmware_header *)info->fw->data;
 654                 adev->firmware.fw_size +=
 655                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 656
 657                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
 658                 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
 659                 info->fw = adev->gfx.me_fw;
 660                 header = (const struct common_firmware_header *)info->fw->data;
 661                 adev->firmware.fw_size +=
 662                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 663
 664                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
 665                 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
 666                 info->fw = adev->gfx.ce_fw;
 667                 header = (const struct common_firmware_header *)info->fw->data;
 668                 adev->firmware.fw_size +=
 669                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 670
 671                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
 672                 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
 673                 info->fw = adev->gfx.rlc_fw;
 674                 header = (const struct common_firmware_header *)info->fw->data;
 675                 adev->firmware.fw_size +=
 676                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 677
 678                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
 679                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
 680                 info->fw = adev->gfx.mec_fw;
 681                 header = (const struct common_firmware_header *)info->fw->data;
 682                 adev->firmware.fw_size +=
 683                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 684
 685                 if (adev->gfx.mec2_fw) {
 686                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
 687                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
 688                         info->fw = adev->gfx.mec2_fw;
 689                         header = (const struct common_firmware_header *)info->fw->data;
 690                         adev->firmware.fw_size +=
 691                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 692                 }
 693
 694         }
 695
 696 out:
 697         if (err) {
 698                 dev_err(adev->dev,
 699                         "gfx8: Failed to load firmware \"%s\"\n",
 700                         fw_name);
 701                 release_firmware(adev->gfx.pfp_fw);
 702                 adev->gfx.pfp_fw = NULL;
 703                 release_firmware(adev->gfx.me_fw);
 704                 adev->gfx.me_fw = NULL;
 705                 release_firmware(adev->gfx.ce_fw);
 706                 adev->gfx.ce_fw = NULL;
 707                 release_firmware(adev->gfx.rlc_fw);
 708                 adev->gfx.rlc_fw = NULL;
 709                 release_firmware(adev->gfx.mec_fw);
 710                 adev->gfx.mec_fw = NULL;
 711                 release_firmware(adev->gfx.mec2_fw);
 712                 adev->gfx.mec2_fw = NULL;
 713         }
 714         return err;
 715 }
 716
 717 static void gfx_v8_0_mec_fini(struct amdgpu_device *adev)
 718 {
 719         int r;
 720
 721         if (adev->gfx.mec.hpd_eop_obj) {
 722                 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
 723                 if (unlikely(r != 0))
 724                         dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r);
 725                 amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj);
 726                 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
 727
 728                 amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj);
 729                 adev->gfx.mec.hpd_eop_obj = NULL;
 730         }
 731 }
 732
 733 #define MEC_HPD_SIZE 2048
 734
 735 static int gfx_v8_0_mec_init(struct amdgpu_device *adev)
 736 {
 737         int r;
 738         u32 *hpd;
 739
 740         /*
 741          * we assign only 1 pipe because all other pipes will
 742          * be handled by KFD
 743          */
 744         adev->gfx.mec.num_mec = 1;
 745         adev->gfx.mec.num_pipe = 1;
 746         adev->gfx.mec.num_queue = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * 8;
 747
 748         if (adev->gfx.mec.hpd_eop_obj == NULL) {
 749                 r = amdgpu_bo_create(adev,
 750                                      adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2,
 751                                      PAGE_SIZE, true,
 752                                      AMDGPU_GEM_DOMAIN_GTT, 0, NULL,
 753                                      &adev->gfx.mec.hpd_eop_obj);
 754                 if (r) {
 755                         dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
 756                         return r;
 757                 }
 758         }
 759
 760         r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
 761         if (unlikely(r != 0)) {
 762                 gfx_v8_0_mec_fini(adev);
 763                 return r;
 764         }
 765         r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT,
 766                           &adev->gfx.mec.hpd_eop_gpu_addr);
 767         if (r) {
 768                 dev_warn(adev->dev, "(%d) pin HDP EOP bo failed\n", r);
 769                 gfx_v8_0_mec_fini(adev);
 770                 return r;
 771         }
 772         r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd);
 773         if (r) {
 774                 dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r);
 775                 gfx_v8_0_mec_fini(adev);
 776                 return r;
 777         }
 778
 779         memset(hpd, 0, adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2);
 780
 781         amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
 782         amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
 783
 784         return 0;
 785 }
 786
 787 static int gfx_v8_0_sw_init(void *handle)
 788 {
 789         int i, r;
 790         struct amdgpu_ring *ring;
 791         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 792
 793         /* EOP Event */
 794         r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq);
 795         if (r)
 796                 return r;
 797
 798         /* Privileged reg */
 799         r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq);
 800         if (r)
 801                 return r;
 802
 803         /* Privileged inst */
 804         r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq);
 805         if (r)
 806                 return r;
 807
 808         adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
 809
 810         gfx_v8_0_scratch_init(adev);
 811
 812         r = gfx_v8_0_init_microcode(adev);
 813         if (r) {
 814                 DRM_ERROR("Failed to load gfx firmware!\n");
 815                 return r;
 816         }
 817
 818         r = gfx_v8_0_mec_init(adev);
 819         if (r) {
 820                 DRM_ERROR("Failed to init MEC BOs!\n");
 821                 return r;
 822         }
 823
 824         r = amdgpu_wb_get(adev, &adev->gfx.ce_sync_offs);
 825         if (r) {
 826                 DRM_ERROR("(%d) gfx.ce_sync_offs wb alloc failed\n", r);
 827                 return r;
 828         }
 829
 830         /* set up the gfx ring */
 831         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
 832                 ring = &adev->gfx.gfx_ring[i];
 833                 ring->ring_obj = NULL;
 834                 sprintf(ring->name, "gfx");
 835                 /* no gfx doorbells on iceland */
 836                 if (adev->asic_type != CHIP_TOPAZ) {
 837                         ring->use_doorbell = true;
 838                         ring->doorbell_index = AMDGPU_DOORBELL_GFX_RING0;
 839                 }
 840
 841                 r = amdgpu_ring_init(adev, ring, 1024 * 1024,
 842                                      PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
 843                                      &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP,
 844                                      AMDGPU_RING_TYPE_GFX);
 845                 if (r)
 846                         return r;
 847         }
 848
 849         /* set up the compute queues */
 850         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
 851                 unsigned irq_type;
 852
 853                 /* max 32 queues per MEC */
 854                 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) {
 855                         DRM_ERROR("Too many (%d) compute rings!\n", i);
 856                         break;
 857                 }
 858                 ring = &adev->gfx.compute_ring[i];
 859                 ring->ring_obj = NULL;
 860                 ring->use_doorbell = true;
 861                 ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + i;
 862                 ring->me = 1; /* first MEC */
 863                 ring->pipe = i / 8;
 864                 ring->queue = i % 8;
 865                 sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, ring->queue);
 866                 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
 867                 /* type-2 packets are deprecated on MEC, use type-3 instead */
 868                 r = amdgpu_ring_init(adev, ring, 1024 * 1024,
 869                                      PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
 870                                      &adev->gfx.eop_irq, irq_type,
 871                                      AMDGPU_RING_TYPE_COMPUTE);
 872                 if (r)
 873                         return r;
 874         }
 875
 876         /* reserve GDS, GWS and OA resource for gfx */
 877         r = amdgpu_bo_create(adev, adev->gds.mem.gfx_partition_size,
 878                         PAGE_SIZE, true,
 879                         AMDGPU_GEM_DOMAIN_GDS, 0,
 880                         NULL, &adev->gds.gds_gfx_bo);
 881         if (r)
 882                 return r;
 883
 884         r = amdgpu_bo_create(adev, adev->gds.gws.gfx_partition_size,
 885                 PAGE_SIZE, true,
 886                 AMDGPU_GEM_DOMAIN_GWS, 0,
 887                 NULL, &adev->gds.gws_gfx_bo);
 888         if (r)
 889                 return r;
 890
 891         r = amdgpu_bo_create(adev, adev->gds.oa.gfx_partition_size,
 892                         PAGE_SIZE, true,
 893                         AMDGPU_GEM_DOMAIN_OA, 0,
 894                         NULL, &adev->gds.oa_gfx_bo);
 895         if (r)
 896                 return r;
 897
 898         adev->gfx.ce_ram_size = 0x8000;
 899
 900         return 0;
 901 }
 902
 903 static int gfx_v8_0_sw_fini(void *handle)
 904 {
 905         int i;
 906         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 907
 908         amdgpu_bo_unref(&adev->gds.oa_gfx_bo);
 909         amdgpu_bo_unref(&adev->gds.gws_gfx_bo);
 910         amdgpu_bo_unref(&adev->gds.gds_gfx_bo);
 911
 912         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
 913                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
 914         for (i = 0; i < adev->gfx.num_compute_rings; i++)
 915                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
 916
 917         amdgpu_wb_free(adev, adev->gfx.ce_sync_offs);
 918
 919         gfx_v8_0_mec_fini(adev);
 920
 921         return 0;
 922 }
 923
 924 static void gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev)
 925 {
 926         const u32 num_tile_mode_states = 32;
 927         const u32 num_secondary_tile_mode_states = 16;
 928         u32 reg_offset, gb_tile_moden, split_equal_to_row_size;
 929
 930         switch (adev->gfx.config.mem_row_size_in_kb) {
 931         case 1:
 932                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
 933                 break;
 934         case 2:
 935         default:
 936                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
 937                 break;
 938         case 4:
 939                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
 940                 break;
 941         }
 942
 943         switch (adev->asic_type) {
 944         case CHIP_TOPAZ:
 945                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
 946                         switch (reg_offset) {
 947                         case 0:
 948                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 949                                                 PIPE_CONFIG(ADDR_SURF_P2) |
 950                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
 951                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
 952                                 break;
 953                         case 1:
 954                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 955                                                 PIPE_CONFIG(ADDR_SURF_P2) |
 956                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
 957                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
 958                                 break;
 959                         case 2:
 960                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 961                                                 PIPE_CONFIG(ADDR_SURF_P2) |
 962                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
 963                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
 964                                 break;
 965                         case 3:
 966                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 967                                                 PIPE_CONFIG(ADDR_SURF_P2) |
 968                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
 969                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
 970                                 break;
 971                         case 4:
 972                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 973                                                 PIPE_CONFIG(ADDR_SURF_P2) |
 974                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
 975                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
 976                                 break;
 977                         case 5:
 978                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 979                                                 PIPE_CONFIG(ADDR_SURF_P2) |
 980                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
 981                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
 982                                 break;
 983                         case 6:
 984                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
 985                                                 PIPE_CONFIG(ADDR_SURF_P2) |
 986                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
 987                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
 988                                 break;
 989                         case 8:
 990                                 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
 991                                                 PIPE_CONFIG(ADDR_SURF_P2));
 992                                 break;
 993                         case 9:
 994                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 995                                                 PIPE_CONFIG(ADDR_SURF_P2) |
 996                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
 997                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 998                                 break;
 999                         case 10:
1000                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1001                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1002                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1003                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1004                                 break;
1005                         case 11:
1006                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1007                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1008                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1009                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1010                                 break;
1011                         case 13:
1012                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1013                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1014                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1015                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1016                                 break;
1017                         case 14:
1018                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1019                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1020                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1021                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1022                                 break;
1023                         case 15:
1024                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1025                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1026                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1027                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1028                                 break;
1029                         case 16:
1030                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1031                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1032                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1033                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1034                                 break;
1035                         case 18:
1036                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1037                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1038                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1039                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1040                                 break;
1041                         case 19:
1042                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1043                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1044                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1045                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1046                                 break;
1047                         case 20:
1048                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1049                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1050                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1051                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1052                                 break;
1053                         case 21:
1054                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1055                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1056                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1057                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1058                                 break;
1059                         case 22:
1060                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1061                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1062                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1063                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1064                                 break;
1065                         case 24:
1066                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1067                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1068                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1069                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1070                                 break;
1071                         case 25:
1072                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1073                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1074                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1075                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1076                                 break;
1077                         case 26:
1078                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1079                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1080                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1081                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1082                                 break;
1083                         case 27:
1084                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1085                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1086                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1087                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1088                                 break;
1089                         case 28:
1090                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1091                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1092                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1093                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1094                                 break;
1095                         case 29:
1096                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1097                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1098                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1099                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1100                                 break;
1101                         case 7:
1102                         case 12:
1103                         case 17:
1104                         case 23:
1105                                 /* unused idx */
1106                                 continue;
1107                         default:
1108                                 gb_tile_moden = 0;
1109                                 break;
1110                         };
1111                         adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
1112                         WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
1113                 }
1114                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
1115                         switch (reg_offset) {
1116                         case 0:
1117                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1118                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1119                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1120                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1121                                 break;
1122                         case 1:
1123                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1124                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1125                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1126                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1127                                 break;
1128                         case 2:
1129                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1130                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1131                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1132                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1133                                 break;
1134                         case 3:
1135                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1136                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1137                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1138                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1139                                 break;
1140                         case 4:
1141                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1142                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1143                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1144                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1145                                 break;
1146                         case 5:
1147                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1148                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1149                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1150                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1151                                 break;
1152                         case 6:
1153                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1154                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1155                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1156                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1157                                 break;
1158                         case 8:
1159                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1160                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1161                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1162                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1163                                 break;
1164                         case 9:
1165                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1166                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1167                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1168                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1169                                 break;
1170                         case 10:
1171                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1172                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1173                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1174                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1175                                 break;
1176                         case 11:
1177                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1178                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1179                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1180                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1181                                 break;
1182                         case 12:
1183                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1184                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1185                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1186                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1187                                 break;
1188                         case 13:
1189                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1190                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1191                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1192                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1193                                 break;
1194                         case 14:
1195                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1196                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1197                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1198                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1199                                 break;
1200                         case 7:
1201                                 /* unused idx */
1202                                 continue;
1203                         default:
1204                                 gb_tile_moden = 0;
1205                                 break;
1206                         };
1207                         adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
1208                         WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
1209                 }
1210         case CHIP_TONGA:
1211                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
1212                         switch (reg_offset) {
1213                         case 0:
1214                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1215                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1216                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1217                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1218                                 break;
1219                         case 1:
1220                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1221                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1222                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1223                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1224                                 break;
1225                         case 2:
1226                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1227                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1228                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1229                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1230                                 break;
1231                         case 3:
1232                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1233                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1234                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1235                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1236                                 break;
1237                         case 4:
1238                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1239                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1240                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1241                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1242                                 break;
1243                         case 5:
1244                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1245                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1246                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1247                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1248                                 break;
1249                         case 6:
1250                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1251                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1252                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1253                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1254                                 break;
1255                         case 7:
1256                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1257                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1258                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1259                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1260                                 break;
1261                         case 8:
1262                                 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1263                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16));
1264                                 break;
1265                         case 9:
1266                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1267                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1268                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1269                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1270                                 break;
1271                         case 10:
1272                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1273                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1274                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1275                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1276                                 break;
1277                         case 11:
1278                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1279                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1280                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1281                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1282                                 break;
1283                         case 12:
1284                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1285                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1286                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1287                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1288                                 break;
1289                         case 13:
1290                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1291                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1292                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1293                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1294                                 break;
1295                         case 14:
1296                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1297                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1298                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1299                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1300                                 break;
1301                         case 15:
1302                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1303                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1304                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1305                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1306                                 break;
1307                         case 16:
1308                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1309                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1310                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1311                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1312                                 break;
1313                         case 17:
1314                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1315                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1316                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1317                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1318                                 break;
1319                         case 18:
1320                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1321                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1322                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1323                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1324                                 break;
1325                         case 19:
1326                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1327                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1328                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1329                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1330                                 break;
1331                         case 20:
1332                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1333                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1334                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1335                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1336                                 break;
1337                         case 21:
1338                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1339                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1340                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1341                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1342                                 break;
1343                         case 22:
1344                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1345                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1346                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1347                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1348                                 break;
1349                         case 23:
1350                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1351                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1352                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1353                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1354                                 break;
1355                         case 24:
1356                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1357                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1358                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1359                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1360                                 break;
1361                         case 25:
1362                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1363                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1364                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1365                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1366                                 break;
1367                         case 26:
1368                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1369                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1370                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1371                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1372                                 break;
1373                         case 27:
1374                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1375                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1376                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1377                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1378                                 break;
1379                         case 28:
1380                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1381                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1382                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1383                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1384                                 break;
1385                         case 29:
1386                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1387                                                 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1388                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1389                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1390                                 break;
1391                         case 30:
1392                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1393                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1394                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1395                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1396                                 break;
1397                         default:
1398                                 gb_tile_moden = 0;
1399                                 break;
1400                         };
1401                         adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
1402                         WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
1403                 }
1404                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
1405                         switch (reg_offset) {
1406                         case 0:
1407                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1408                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1409                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1410                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1411                                 break;
1412                         case 1:
1413                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1414                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1415                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1416                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1417                                 break;
1418                         case 2:
1419                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1420                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1421                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1422                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1423                                 break;
1424                         case 3:
1425                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1426                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1427                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1428                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1429                                 break;
1430                         case 4:
1431                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1432                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1433                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1434                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1435                                 break;
1436                         case 5:
1437                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1438                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1439                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1440                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1441                                 break;
1442                         case 6:
1443                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1444                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1445                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1446                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1447                                 break;
1448                         case 8:
1449                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1450                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1451                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1452                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1453                                 break;
1454                         case 9:
1455                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1456                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1457                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1458                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1459                                 break;
1460                         case 10:
1461                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1462                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1463                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1464                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1465                                 break;
1466                         case 11:
1467                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1468                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1469                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1470                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1471                                 break;
1472                         case 12:
1473                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1474                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1475                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1476                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1477                                 break;
1478                         case 13:
1479                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1480                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1481                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1482                                                 NUM_BANKS(ADDR_SURF_4_BANK));
1483                                 break;
1484                         case 14:
1485                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1486                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1487                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1488                                                 NUM_BANKS(ADDR_SURF_4_BANK));
1489                                 break;
1490                         case 7:
1491                                 /* unused idx */
1492                                 continue;
1493                         default:
1494                                 gb_tile_moden = 0;
1495                                 break;
1496                         };
1497                         adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
1498                         WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
1499                 }
1500                 break;
1501         case CHIP_CARRIZO:
1502         default:
1503                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
1504                         switch (reg_offset) {
1505                         case 0:
1506                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1507                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1508                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1509                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1510                                 break;
1511                         case 1:
1512                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1513                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1514                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1515                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1516                                 break;
1517                         case 2:
1518                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1519                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1520                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1521                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1522                                 break;
1523                         case 3:
1524                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1525                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1526                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1527                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1528                                 break;
1529                         case 4:
1530                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1531                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1532                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1533                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1534                                 break;
1535                         case 5:
1536                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1537                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1538                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1539                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1540                                 break;
1541                         case 6:
1542                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1543                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1544                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1545                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1546                                 break;
1547                         case 8:
1548                                 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1549                                                 PIPE_CONFIG(ADDR_SURF_P2));
1550                                 break;
1551                         case 9:
1552                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1553                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1554                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1555                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1556                                 break;
1557                         case 10:
1558                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1559                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1560                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1561                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1562                                 break;
1563                         case 11:
1564                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1565                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1566                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1567                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1568                                 break;
1569                         case 13:
1570                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1571                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1572                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1573                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1574                                 break;
1575                         case 14:
1576                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1577                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1578                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1579                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1580                                 break;
1581                         case 15:
1582                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1583                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1584                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1585                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1586                                 break;
1587                         case 16:
1588                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1589                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1590                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1591                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1592                                 break;
1593                         case 18:
1594                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1595                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1596                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1597                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1598                                 break;
1599                         case 19:
1600                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1601                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1602                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1603                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1604                                 break;
1605                         case 20:
1606                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1607                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1608                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1609                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1610                                 break;
1611                         case 21:
1612                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1613                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1614                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1615                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1616                                 break;
1617                         case 22:
1618                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1619                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1620                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1621                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1622                                 break;
1623                         case 24:
1624                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1625                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1626                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1627                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1628                                 break;
1629                         case 25:
1630                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1631                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1632                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1633                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1634                                 break;
1635                         case 26:
1636                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1637                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1638                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1639                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1640                                 break;
1641                         case 27:
1642                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1643                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1644                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1645                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1646                                 break;
1647                         case 28:
1648                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1649                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1650                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1651                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1652                                 break;
1653                         case 29:
1654                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1655                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1656                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1657                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1658                                 break;
1659                         case 7:
1660                         case 12:
1661                         case 17:
1662                         case 23:
1663                                 /* unused idx */
1664                                 continue;
1665                         default:
1666                                 gb_tile_moden = 0;
1667                                 break;
1668                         };
1669                         adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
1670                         WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
1671                 }
1672                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
1673                         switch (reg_offset) {
1674                         case 0:
1675                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1676                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1677                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1678                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1679                                 break;
1680                         case 1:
1681                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1682                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1683                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1684                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1685                                 break;
1686                         case 2:
1687                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1688                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1689                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1690                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1691                                 break;
1692                         case 3:
1693                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1694                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1695                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1696                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1697                                 break;
1698                         case 4:
1699                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1700                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1701                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1702                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1703                                 break;
1704                         case 5:
1705                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1706                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1707                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1708                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1709                                 break;
1710                         case 6:
1711                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1712                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1713                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1714                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1715                                 break;
1716                         case 8:
1717                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1718                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1719                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1720                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1721                                 break;
1722                         case 9:
1723                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1724                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1725                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1726                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1727                                 break;
1728                         case 10:
1729                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1730                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1731                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1732                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1733                                 break;
1734                         case 11:
1735                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1736                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1737                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1738                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1739                                 break;
1740                         case 12:
1741                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1742                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1743                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1744                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1745                                 break;
1746                         case 13:
1747                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1748                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1749                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1750                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1751                                 break;
1752                         case 14:
1753                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1754                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1755                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1756                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1757                                 break;
1758                         case 7:
1759                                 /* unused idx */
1760                                 continue;
1761                         default:
1762                                 gb_tile_moden = 0;
1763                                 break;
1764                         };
1765                         adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
1766                         WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
1767                 }
1768         }
1769 }
1770
1771 static u32 gfx_v8_0_create_bitmask(u32 bit_width)
1772 {
1773         u32 i, mask = 0;
1774
1775         for (i = 0; i < bit_width; i++) {
1776                 mask <<= 1;
1777                 mask |= 1;
1778         }
1779         return mask;
1780 }
1781
1782 void gfx_v8_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num)
1783 {
1784         u32 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
1785
1786         if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) {
1787                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
1788                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
1789         } else if (se_num == 0xffffffff) {
1790                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
1791                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
1792         } else if (sh_num == 0xffffffff) {
1793                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
1794                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1795         } else {
1796                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
1797                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1798         }
1799         WREG32(mmGRBM_GFX_INDEX, data);
1800 }
1801
1802 static u32 gfx_v8_0_get_rb_disabled(struct amdgpu_device *adev,
1803                                     u32 max_rb_num_per_se,
1804                                     u32 sh_per_se)
1805 {
1806         u32 data, mask;
1807
1808         data = RREG32(mmCC_RB_BACKEND_DISABLE);
1809         if (data & 1)
1810                 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
1811         else
1812                 data = 0;
1813
1814         data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1815
1816         data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1817
1818         mask = gfx_v8_0_create_bitmask(max_rb_num_per_se / sh_per_se);
1819
1820         return data & mask;
1821 }
1822
1823 static void gfx_v8_0_setup_rb(struct amdgpu_device *adev,
1824                               u32 se_num, u32 sh_per_se,
1825                               u32 max_rb_num_per_se)
1826 {
1827         int i, j;
1828         u32 data, mask;
1829         u32 disabled_rbs = 0;
1830         u32 enabled_rbs = 0;
1831
1832         mutex_lock(&adev->grbm_idx_mutex);
1833         for (i = 0; i < se_num; i++) {
1834                 for (j = 0; j < sh_per_se; j++) {
1835                         gfx_v8_0_select_se_sh(adev, i, j);
1836                         data = gfx_v8_0_get_rb_disabled(adev,
1837                                               max_rb_num_per_se, sh_per_se);
1838                         disabled_rbs |= data << ((i * sh_per_se + j) *
1839                                                  RB_BITMAP_WIDTH_PER_SH);
1840                 }
1841         }
1842         gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
1843         mutex_unlock(&adev->grbm_idx_mutex);
1844
1845         mask = 1;
1846         for (i = 0; i < max_rb_num_per_se * se_num; i++) {
1847                 if (!(disabled_rbs & mask))
1848                         enabled_rbs |= mask;
1849                 mask <<= 1;
1850         }
1851
1852         adev->gfx.config.backend_enable_mask = enabled_rbs;
1853
1854         mutex_lock(&adev->grbm_idx_mutex);
1855         for (i = 0; i < se_num; i++) {
1856                 gfx_v8_0_select_se_sh(adev, i, 0xffffffff);
1857                 data = 0;
1858                 for (j = 0; j < sh_per_se; j++) {
1859                         switch (enabled_rbs & 3) {
1860                         case 0:
1861                                 if (j == 0)
1862                                         data |= (RASTER_CONFIG_RB_MAP_3 <<
1863                                                  PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT);
1864                                 else
1865                                         data |= (RASTER_CONFIG_RB_MAP_0 <<
1866                                                  PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT);
1867                                 break;
1868                         case 1:
1869                                 data |= (RASTER_CONFIG_RB_MAP_0 <<
1870                                          (i * sh_per_se + j) * 2);
1871                                 break;
1872                         case 2:
1873                                 data |= (RASTER_CONFIG_RB_MAP_3 <<
1874                                          (i * sh_per_se + j) * 2);
1875                                 break;
1876                         case 3:
1877                         default:
1878                                 data |= (RASTER_CONFIG_RB_MAP_2 <<
1879                                          (i * sh_per_se + j) * 2);
1880                                 break;
1881                         }
1882                         enabled_rbs >>= 2;
1883                 }
1884                 WREG32(mmPA_SC_RASTER_CONFIG, data);
1885         }
1886         gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
1887         mutex_unlock(&adev->grbm_idx_mutex);
1888 }
1889
1890 static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
1891 {
1892         u32 gb_addr_config;
1893         u32 mc_shared_chmap, mc_arb_ramcfg;
1894         u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
1895         u32 tmp;
1896         int i;
1897
1898         switch (adev->asic_type) {
1899         case CHIP_TOPAZ:
1900                 adev->gfx.config.max_shader_engines = 1;
1901                 adev->gfx.config.max_tile_pipes = 2;
1902                 adev->gfx.config.max_cu_per_sh = 6;
1903                 adev->gfx.config.max_sh_per_se = 1;
1904                 adev->gfx.config.max_backends_per_se = 2;
1905                 adev->gfx.config.max_texture_channel_caches = 2;
1906                 adev->gfx.config.max_gprs = 256;
1907                 adev->gfx.config.max_gs_threads = 32;
1908                 adev->gfx.config.max_hw_contexts = 8;
1909
1910                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1911                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1912                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1913                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1914                 gb_addr_config = TOPAZ_GB_ADDR_CONFIG_GOLDEN;
1915                 break;
1916         case CHIP_TONGA:
1917                 adev->gfx.config.max_shader_engines = 4;
1918                 adev->gfx.config.max_tile_pipes = 8;
1919                 adev->gfx.config.max_cu_per_sh = 8;
1920                 adev->gfx.config.max_sh_per_se = 1;
1921                 adev->gfx.config.max_backends_per_se = 2;
1922                 adev->gfx.config.max_texture_channel_caches = 8;
1923                 adev->gfx.config.max_gprs = 256;
1924                 adev->gfx.config.max_gs_threads = 32;
1925                 adev->gfx.config.max_hw_contexts = 8;
1926
1927                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1928                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1929                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1930                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1931                 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1932                 break;
1933         case CHIP_CARRIZO:
1934                 adev->gfx.config.max_shader_engines = 1;
1935                 adev->gfx.config.max_tile_pipes = 2;
1936                 adev->gfx.config.max_sh_per_se = 1;
1937
1938                 switch (adev->pdev->revision) {
1939                 case 0xc4:
1940                 case 0x84:
1941                 case 0xc8:
1942                 case 0xcc:
1943                         /* B10 */
1944                         adev->gfx.config.max_cu_per_sh = 8;
1945                         adev->gfx.config.max_backends_per_se = 2;
1946                         break;
1947                 case 0xc5:
1948                 case 0x81:
1949                 case 0x85:
1950                 case 0xc9:
1951                 case 0xcd:
1952                         /* B8 */
1953                         adev->gfx.config.max_cu_per_sh = 6;
1954                         adev->gfx.config.max_backends_per_se = 2;
1955                         break;
1956                 case 0xc6:
1957                 case 0xca:
1958                 case 0xce:
1959                         /* B6 */
1960                         adev->gfx.config.max_cu_per_sh = 6;
1961                         adev->gfx.config.max_backends_per_se = 2;
1962                         break;
1963                 case 0xc7:
1964                 case 0x87:
1965                 case 0xcb:
1966                 default:
1967                         /* B4 */
1968                         adev->gfx.config.max_cu_per_sh = 4;
1969                         adev->gfx.config.max_backends_per_se = 1;
1970                         break;
1971                 }
1972
1973                 adev->gfx.config.max_texture_channel_caches = 2;
1974                 adev->gfx.config.max_gprs = 256;
1975                 adev->gfx.config.max_gs_threads = 32;
1976                 adev->gfx.config.max_hw_contexts = 8;
1977
1978                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1979                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1980                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1981                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1982                 gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN;
1983                 break;
1984         default:
1985                 adev->gfx.config.max_shader_engines = 2;
1986                 adev->gfx.config.max_tile_pipes = 4;
1987                 adev->gfx.config.max_cu_per_sh = 2;
1988                 adev->gfx.config.max_sh_per_se = 1;
1989                 adev->gfx.config.max_backends_per_se = 2;
1990                 adev->gfx.config.max_texture_channel_caches = 4;
1991                 adev->gfx.config.max_gprs = 256;
1992                 adev->gfx.config.max_gs_threads = 32;
1993                 adev->gfx.config.max_hw_contexts = 8;
1994
1995                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1996                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1997                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1998                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1999                 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
2000                 break;
2001         }
2002
2003         tmp = RREG32(mmGRBM_CNTL);
2004         tmp = REG_SET_FIELD(tmp, GRBM_CNTL, READ_TIMEOUT, 0xff);
2005         WREG32(mmGRBM_CNTL, tmp);
2006
2007         mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
2008         adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
2009         mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
2010
2011         adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
2012         adev->gfx.config.mem_max_burst_length_bytes = 256;
2013         if (adev->flags & AMDGPU_IS_APU) {
2014                 /* Get memory bank mapping mode. */
2015                 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
2016                 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
2017                 dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
2018
2019                 tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
2020                 dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
2021                 dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
2022
2023                 /* Validate settings in case only one DIMM installed. */
2024                 if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12))
2025                         dimm00_addr_map = 0;
2026                 if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12))
2027                         dimm01_addr_map = 0;
2028                 if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12))
2029                         dimm10_addr_map = 0;
2030                 if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12))
2031                         dimm11_addr_map = 0;
2032
2033                 /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */
2034                 /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */
2035                 if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11))
2036                         adev->gfx.config.mem_row_size_in_kb = 2;
2037                 else
2038                         adev->gfx.config.mem_row_size_in_kb = 1;
2039         } else {
2040                 tmp = REG_GET_FIELD(mc_arb_ramcfg, MC_ARB_RAMCFG, NOOFCOLS);
2041                 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
2042                 if (adev->gfx.config.mem_row_size_in_kb > 4)
2043                         adev->gfx.config.mem_row_size_in_kb = 4;
2044         }
2045
2046         adev->gfx.config.shader_engine_tile_size = 32;
2047         adev->gfx.config.num_gpus = 1;
2048         adev->gfx.config.multi_gpu_tile_size = 64;
2049
2050         /* fix up row size */
2051         switch (adev->gfx.config.mem_row_size_in_kb) {
2052         case 1:
2053         default:
2054                 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 0);
2055                 break;
2056         case 2:
2057                 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 1);
2058                 break;
2059         case 4:
2060                 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 2);
2061                 break;
2062         }
2063         adev->gfx.config.gb_addr_config = gb_addr_config;
2064
2065         WREG32(mmGB_ADDR_CONFIG, gb_addr_config);
2066         WREG32(mmHDP_ADDR_CONFIG, gb_addr_config);
2067         WREG32(mmDMIF_ADDR_CALC, gb_addr_config);
2068         WREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET,
2069                gb_addr_config & 0x70);
2070         WREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET,
2071                gb_addr_config & 0x70);
2072         WREG32(mmUVD_UDEC_ADDR_CONFIG, gb_addr_config);
2073         WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
2074         WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
2075
2076         gfx_v8_0_tiling_mode_table_init(adev);
2077
2078         gfx_v8_0_setup_rb(adev, adev->gfx.config.max_shader_engines,
2079                                  adev->gfx.config.max_sh_per_se,
2080                                  adev->gfx.config.max_backends_per_se);
2081
2082         /* XXX SH_MEM regs */
2083         /* where to put LDS, scratch, GPUVM in FSA64 space */
2084         mutex_lock(&adev->srbm_mutex);
2085         for (i = 0; i < 16; i++) {
2086                 vi_srbm_select(adev, 0, 0, 0, i);
2087                 /* CP and shaders */
2088                 if (i == 0) {
2089                         tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_UC);
2090                         tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC);
2091                         tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
2092                                             SH_MEM_ALIGNMENT_MODE_UNALIGNED);
2093                         WREG32(mmSH_MEM_CONFIG, tmp);
2094                 } else {
2095                         tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_NC);
2096                         tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_NC);
2097                         tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
2098                                             SH_MEM_ALIGNMENT_MODE_UNALIGNED);
2099                         WREG32(mmSH_MEM_CONFIG, tmp);
2100                 }
2101
2102                 WREG32(mmSH_MEM_APE1_BASE, 1);
2103                 WREG32(mmSH_MEM_APE1_LIMIT, 0);
2104                 WREG32(mmSH_MEM_BASES, 0);
2105         }
2106         vi_srbm_select(adev, 0, 0, 0, 0);
2107         mutex_unlock(&adev->srbm_mutex);
2108
2109         mutex_lock(&adev->grbm_idx_mutex);
2110         /*
2111          * making sure that the following register writes will be broadcasted
2112          * to all the shaders
2113          */
2114         gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
2115
2116         WREG32(mmPA_SC_FIFO_SIZE,
2117                    (adev->gfx.config.sc_prim_fifo_size_frontend <<
2118                         PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
2119                    (adev->gfx.config.sc_prim_fifo_size_backend <<
2120                         PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
2121                    (adev->gfx.config.sc_hiz_tile_fifo_size <<
2122                         PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
2123                    (adev->gfx.config.sc_earlyz_tile_fifo_size <<
2124                         PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT));
2125         mutex_unlock(&adev->grbm_idx_mutex);
2126
2127 }
2128
2129 static void gfx_v8_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
2130 {
2131         u32 i, j, k;
2132         u32 mask;
2133
2134         mutex_lock(&adev->grbm_idx_mutex);
2135         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
2136                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
2137                         gfx_v8_0_select_se_sh(adev, i, j);
2138                         for (k = 0; k < adev->usec_timeout; k++) {
2139                                 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0)
2140                                         break;
2141                                 udelay(1);
2142                         }
2143                 }
2144         }
2145         gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
2146         mutex_unlock(&adev->grbm_idx_mutex);
2147
2148         mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
2149                 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
2150                 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
2151                 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
2152         for (k = 0; k < adev->usec_timeout; k++) {
2153                 if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
2154                         break;
2155                 udelay(1);
2156         }
2157 }
2158
2159 static void gfx_v8_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
2160                                                bool enable)
2161 {
2162         u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
2163
2164         if (enable) {
2165                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 1);
2166                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 1);
2167                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 1);
2168                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 1);
2169         } else {
2170                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 0);
2171                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 0);
2172                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 0);
2173                 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 0);
2174         }
2175         WREG32(mmCP_INT_CNTL_RING0, tmp);
2176 }
2177
2178 void gfx_v8_0_rlc_stop(struct amdgpu_device *adev)
2179 {
2180         u32 tmp = RREG32(mmRLC_CNTL);
2181
2182         tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
2183         WREG32(mmRLC_CNTL, tmp);
2184
2185         gfx_v8_0_enable_gui_idle_interrupt(adev, false);
2186
2187         gfx_v8_0_wait_for_rlc_serdes(adev);
2188 }
2189
2190 static void gfx_v8_0_rlc_reset(struct amdgpu_device *adev)
2191 {
2192         u32 tmp = RREG32(mmGRBM_SOFT_RESET);
2193
2194         tmp = REG_SET_FIELD(tmp, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
2195         WREG32(mmGRBM_SOFT_RESET, tmp);
2196         udelay(50);
2197         tmp = REG_SET_FIELD(tmp, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
2198         WREG32(mmGRBM_SOFT_RESET, tmp);
2199         udelay(50);
2200 }
2201
2202 static void gfx_v8_0_rlc_start(struct amdgpu_device *adev)
2203 {
2204         u32 tmp = RREG32(mmRLC_CNTL);
2205
2206         tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 1);
2207         WREG32(mmRLC_CNTL, tmp);
2208
2209         /* carrizo do enable cp interrupt after cp inited */
2210         if (adev->asic_type != CHIP_CARRIZO)
2211                 gfx_v8_0_enable_gui_idle_interrupt(adev, true);
2212
2213         udelay(50);
2214 }
2215
2216 static int gfx_v8_0_rlc_load_microcode(struct amdgpu_device *adev)
2217 {
2218         const struct rlc_firmware_header_v2_0 *hdr;
2219         const __le32 *fw_data;
2220         unsigned i, fw_size;
2221
2222         if (!adev->gfx.rlc_fw)
2223                 return -EINVAL;
2224
2225         hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
2226         amdgpu_ucode_print_rlc_hdr(&hdr->header);
2227         adev->gfx.rlc_fw_version = le32_to_cpu(hdr->header.ucode_version);
2228
2229         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
2230                            le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2231         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
2232
2233         WREG32(mmRLC_GPM_UCODE_ADDR, 0);
2234         for (i = 0; i < fw_size; i++)
2235                 WREG32(mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
2236         WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
2237
2238         return 0;
2239 }
2240
2241 static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev)
2242 {
2243         int r;
2244
2245         gfx_v8_0_rlc_stop(adev);
2246
2247         /* disable CG */
2248         WREG32(mmRLC_CGCG_CGLS_CTRL, 0);
2249
2250         /* disable PG */
2251         WREG32(mmRLC_PG_CNTL, 0);
2252
2253         gfx_v8_0_rlc_reset(adev);
2254
2255         if (!adev->firmware.smu_load) {
2256                 /* legacy rlc firmware loading */
2257                 r = gfx_v8_0_rlc_load_microcode(adev);
2258                 if (r)
2259                         return r;
2260         } else {
2261                 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
2262                                                 AMDGPU_UCODE_ID_RLC_G);
2263                 if (r)
2264                         return -EINVAL;
2265         }
2266
2267         gfx_v8_0_rlc_start(adev);
2268
2269         return 0;
2270 }
2271
2272 static void gfx_v8_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2273 {
2274         int i;
2275         u32 tmp = RREG32(mmCP_ME_CNTL);
2276
2277         if (enable) {
2278                 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 0);
2279                 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 0);
2280                 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 0);
2281         } else {
2282                 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1);
2283                 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1);
2284                 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1);
2285                 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2286                         adev->gfx.gfx_ring[i].ready = false;
2287         }
2288         WREG32(mmCP_ME_CNTL, tmp);
2289         udelay(50);
2290 }
2291
2292 static int gfx_v8_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2293 {
2294         const struct gfx_firmware_header_v1_0 *pfp_hdr;
2295         const struct gfx_firmware_header_v1_0 *ce_hdr;
2296         const struct gfx_firmware_header_v1_0 *me_hdr;
2297         const __le32 *fw_data;
2298         unsigned i, fw_size;
2299
2300         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2301                 return -EINVAL;
2302
2303         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
2304                 adev->gfx.pfp_fw->data;
2305         ce_hdr = (const struct gfx_firmware_header_v1_0 *)
2306                 adev->gfx.ce_fw->data;
2307         me_hdr = (const struct gfx_firmware_header_v1_0 *)
2308                 adev->gfx.me_fw->data;
2309
2310         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2311         amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2312         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2313         adev->gfx.pfp_fw_version = le32_to_cpu(pfp_hdr->header.ucode_version);
2314         adev->gfx.ce_fw_version = le32_to_cpu(ce_hdr->header.ucode_version);
2315         adev->gfx.me_fw_version = le32_to_cpu(me_hdr->header.ucode_version);
2316         adev->gfx.me_feature_version = le32_to_cpu(me_hdr->ucode_feature_version);
2317         adev->gfx.ce_feature_version = le32_to_cpu(ce_hdr->ucode_feature_version);
2318         adev->gfx.pfp_feature_version = le32_to_cpu(pfp_hdr->ucode_feature_version);
2319
2320         gfx_v8_0_cp_gfx_enable(adev, false);
2321
2322         /* PFP */
2323         fw_data = (const __le32 *)
2324                 (adev->gfx.pfp_fw->data +
2325                  le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2326         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
2327         WREG32(mmCP_PFP_UCODE_ADDR, 0);
2328         for (i = 0; i < fw_size; i++)
2329                 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
2330         WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
2331
2332         /* CE */
2333         fw_data = (const __le32 *)
2334                 (adev->gfx.ce_fw->data +
2335                  le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2336         fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
2337         WREG32(mmCP_CE_UCODE_ADDR, 0);
2338         for (i = 0; i < fw_size; i++)
2339                 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
2340         WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
2341
2342         /* ME */
2343         fw_data = (const __le32 *)
2344                 (adev->gfx.me_fw->data +
2345                  le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2346         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
2347         WREG32(mmCP_ME_RAM_WADDR, 0);
2348         for (i = 0; i < fw_size; i++)
2349                 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2350         WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
2351
2352         return 0;
2353 }
2354
2355 static u32 gfx_v8_0_get_csb_size(struct amdgpu_device *adev)
2356 {
2357         u32 count = 0;
2358         const struct cs_section_def *sect = NULL;
2359         const struct cs_extent_def *ext = NULL;
2360
2361         /* begin clear state */
2362         count += 2;
2363         /* context control state */
2364         count += 3;
2365
2366         for (sect = vi_cs_data; sect->section != NULL; ++sect) {
2367                 for (ext = sect->section; ext->extent != NULL; ++ext) {
2368                         if (sect->id == SECT_CONTEXT)
2369                                 count += 2 + ext->reg_count;
2370                         else
2371                                 return 0;
2372                 }
2373         }
2374         /* pa_sc_raster_config/pa_sc_raster_config1 */
2375         count += 4;
2376         /* end clear state */
2377         count += 2;
2378         /* clear state */
2379         count += 2;
2380
2381         return count;
2382 }
2383
2384 static int gfx_v8_0_cp_gfx_start(struct amdgpu_device *adev)
2385 {
2386         struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2387         const struct cs_section_def *sect = NULL;
2388         const struct cs_extent_def *ext = NULL;
2389         int r, i;
2390
2391         /* init the CP */
2392         WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
2393         WREG32(mmCP_ENDIAN_SWAP, 0);
2394         WREG32(mmCP_DEVICE_ID, 1);
2395
2396         gfx_v8_0_cp_gfx_enable(adev, true);
2397
2398         r = amdgpu_ring_lock(ring, gfx_v8_0_get_csb_size(adev) + 4);
2399         if (r) {
2400                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2401                 return r;
2402         }
2403
2404         /* clear state buffer */
2405         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2406         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2407
2408         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2409         amdgpu_ring_write(ring, 0x80000000);
2410         amdgpu_ring_write(ring, 0x80000000);
2411
2412         for (sect = vi_cs_data; sect->section != NULL; ++sect) {
2413                 for (ext = sect->section; ext->extent != NULL; ++ext) {
2414                         if (sect->id == SECT_CONTEXT) {
2415                                 amdgpu_ring_write(ring,
2416                                        PACKET3(PACKET3_SET_CONTEXT_REG,
2417                                                ext->reg_count));
2418                                 amdgpu_ring_write(ring,
2419                                        ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2420                                 for (i = 0; i < ext->reg_count; i++)
2421                                         amdgpu_ring_write(ring, ext->extent[i]);
2422                         }
2423                 }
2424         }
2425
2426         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2427         amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
2428         switch (adev->asic_type) {
2429         case CHIP_TONGA:
2430                 amdgpu_ring_write(ring, 0x16000012);
2431                 amdgpu_ring_write(ring, 0x0000002A);
2432                 break;
2433         case CHIP_TOPAZ:
2434         case CHIP_CARRIZO:
2435                 amdgpu_ring_write(ring, 0x00000002);
2436                 amdgpu_ring_write(ring, 0x00000000);
2437                 break;
2438         default:
2439                 BUG();
2440         }
2441
2442         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2443         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2444
2445         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2446         amdgpu_ring_write(ring, 0);
2447
2448         /* init the CE partitions */
2449         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2450         amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2451         amdgpu_ring_write(ring, 0x8000);
2452         amdgpu_ring_write(ring, 0x8000);
2453
2454         amdgpu_ring_unlock_commit(ring);
2455
2456         return 0;
2457 }
2458
2459 static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device *adev)
2460 {
2461         struct amdgpu_ring *ring;
2462         u32 tmp;
2463         u32 rb_bufsz;
2464         u64 rb_addr, rptr_addr;
2465         int r;
2466
2467         /* Set the write pointer delay */
2468         WREG32(mmCP_RB_WPTR_DELAY, 0);
2469
2470         /* set the RB to use vmid 0 */
2471         WREG32(mmCP_RB_VMID, 0);
2472
2473         /* Set ring buffer size */
2474         ring = &adev->gfx.gfx_ring[0];
2475         rb_bufsz = order_base_2(ring->ring_size / 8);
2476         tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
2477         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
2478         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MTYPE, 3);
2479         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MIN_IB_AVAILSZ, 1);
2480 #ifdef __BIG_ENDIAN
2481         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
2482 #endif
2483         WREG32(mmCP_RB0_CNTL, tmp);
2484
2485         /* Initialize the ring buffer's read and write pointers */
2486         WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
2487         ring->wptr = 0;
2488         WREG32(mmCP_RB0_WPTR, ring->wptr);
2489
2490         /* set the wb address wether it's enabled or not */
2491         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2492         WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2493         WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2494
2495         mdelay(1);
2496         WREG32(mmCP_RB0_CNTL, tmp);
2497
2498         rb_addr = ring->gpu_addr >> 8;
2499         WREG32(mmCP_RB0_BASE, rb_addr);
2500         WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
2501
2502         /* no gfx doorbells on iceland */
2503         if (adev->asic_type != CHIP_TOPAZ) {
2504                 tmp = RREG32(mmCP_RB_DOORBELL_CONTROL);
2505                 if (ring->use_doorbell) {
2506                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2507                                             DOORBELL_OFFSET, ring->doorbell_index);
2508                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2509                                             DOORBELL_EN, 1);
2510                 } else {
2511                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2512                                             DOORBELL_EN, 0);
2513                 }
2514                 WREG32(mmCP_RB_DOORBELL_CONTROL, tmp);
2515
2516                 if (adev->asic_type == CHIP_TONGA) {
2517                         tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
2518                                             DOORBELL_RANGE_LOWER,
2519                                             AMDGPU_DOORBELL_GFX_RING0);
2520                         WREG32(mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
2521
2522                         WREG32(mmCP_RB_DOORBELL_RANGE_UPPER,
2523                                CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
2524                 }
2525
2526         }
2527
2528         /* start the ring */
2529         gfx_v8_0_cp_gfx_start(adev);
2530         ring->ready = true;
2531         r = amdgpu_ring_test_ring(ring);
2532         if (r) {
2533                 ring->ready = false;
2534                 return r;
2535         }
2536
2537         return 0;
2538 }
2539
2540 static void gfx_v8_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
2541 {
2542         int i;
2543
2544         if (enable) {
2545                 WREG32(mmCP_MEC_CNTL, 0);
2546         } else {
2547                 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
2548                 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2549                         adev->gfx.compute_ring[i].ready = false;
2550         }
2551         udelay(50);
2552 }
2553
2554 static int gfx_v8_0_cp_compute_start(struct amdgpu_device *adev)
2555 {
2556         gfx_v8_0_cp_compute_enable(adev, true);
2557
2558         return 0;
2559 }
2560
2561 static int gfx_v8_0_cp_compute_load_microcode(struct amdgpu_device *adev)
2562 {
2563         const struct gfx_firmware_header_v1_0 *mec_hdr;
2564         const __le32 *fw_data;
2565         unsigned i, fw_size;
2566
2567         if (!adev->gfx.mec_fw)
2568                 return -EINVAL;
2569
2570         gfx_v8_0_cp_compute_enable(adev, false);
2571
2572         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2573         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
2574         adev->gfx.mec_fw_version = le32_to_cpu(mec_hdr->header.ucode_version);
2575
2576         fw_data = (const __le32 *)
2577                 (adev->gfx.mec_fw->data +
2578                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
2579         fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
2580
2581         /* MEC1 */
2582         WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
2583         for (i = 0; i < fw_size; i++)
2584                 WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data+i));
2585         WREG32(mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
2586
2587         /* Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */
2588         if (adev->gfx.mec2_fw) {
2589                 const struct gfx_firmware_header_v1_0 *mec2_hdr;
2590
2591                 mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
2592                 amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header);
2593                 adev->gfx.mec2_fw_version = le32_to_cpu(mec2_hdr->header.ucode_version);
2594
2595                 fw_data = (const __le32 *)
2596                         (adev->gfx.mec2_fw->data +
2597                          le32_to_cpu(mec2_hdr->header.ucode_array_offset_bytes));
2598                 fw_size = le32_to_cpu(mec2_hdr->header.ucode_size_bytes) / 4;
2599
2600                 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
2601                 for (i = 0; i < fw_size; i++)
2602                         WREG32(mmCP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data+i));
2603                 WREG32(mmCP_MEC_ME2_UCODE_ADDR, adev->gfx.mec2_fw_version);
2604         }
2605
2606         return 0;
2607 }
2608
2609 struct vi_mqd {
2610         uint32_t header;  /* ordinal0 */
2611         uint32_t compute_dispatch_initiator;  /* ordinal1 */
2612         uint32_t compute_dim_x;  /* ordinal2 */
2613         uint32_t compute_dim_y;  /* ordinal3 */
2614         uint32_t compute_dim_z;  /* ordinal4 */
2615         uint32_t compute_start_x;  /* ordinal5 */
2616         uint32_t compute_start_y;  /* ordinal6 */
2617         uint32_t compute_start_z;  /* ordinal7 */
2618         uint32_t compute_num_thread_x;  /* ordinal8 */
2619         uint32_t compute_num_thread_y;  /* ordinal9 */
2620         uint32_t compute_num_thread_z;  /* ordinal10 */
2621         uint32_t compute_pipelinestat_enable;  /* ordinal11 */
2622         uint32_t compute_perfcount_enable;  /* ordinal12 */
2623         uint32_t compute_pgm_lo;  /* ordinal13 */
2624         uint32_t compute_pgm_hi;  /* ordinal14 */
2625         uint32_t compute_tba_lo;  /* ordinal15 */
2626         uint32_t compute_tba_hi;  /* ordinal16 */
2627         uint32_t compute_tma_lo;  /* ordinal17 */
2628         uint32_t compute_tma_hi;  /* ordinal18 */
2629         uint32_t compute_pgm_rsrc1;  /* ordinal19 */
2630         uint32_t compute_pgm_rsrc2;  /* ordinal20 */
2631         uint32_t compute_vmid;  /* ordinal21 */
2632         uint32_t compute_resource_limits;  /* ordinal22 */
2633         uint32_t compute_static_thread_mgmt_se0;  /* ordinal23 */
2634         uint32_t compute_static_thread_mgmt_se1;  /* ordinal24 */
2635         uint32_t compute_tmpring_size;  /* ordinal25 */
2636         uint32_t compute_static_thread_mgmt_se2;  /* ordinal26 */
2637         uint32_t compute_static_thread_mgmt_se3;  /* ordinal27 */
2638         uint32_t compute_restart_x;  /* ordinal28 */
2639         uint32_t compute_restart_y;  /* ordinal29 */
2640         uint32_t compute_restart_z;  /* ordinal30 */
2641         uint32_t compute_thread_trace_enable;  /* ordinal31 */
2642         uint32_t compute_misc_reserved;  /* ordinal32 */
2643         uint32_t compute_dispatch_id;  /* ordinal33 */
2644         uint32_t compute_threadgroup_id;  /* ordinal34 */
2645         uint32_t compute_relaunch;  /* ordinal35 */
2646         uint32_t compute_wave_restore_addr_lo;  /* ordinal36 */
2647         uint32_t compute_wave_restore_addr_hi;  /* ordinal37 */
2648         uint32_t compute_wave_restore_control;  /* ordinal38 */
2649         uint32_t reserved9;  /* ordinal39 */
2650         uint32_t reserved10;  /* ordinal40 */
2651         uint32_t reserved11;  /* ordinal41 */
2652         uint32_t reserved12;  /* ordinal42 */
2653         uint32_t reserved13;  /* ordinal43 */
2654         uint32_t reserved14;  /* ordinal44 */
2655         uint32_t reserved15;  /* ordinal45 */
2656         uint32_t reserved16;  /* ordinal46 */
2657         uint32_t reserved17;  /* ordinal47 */
2658         uint32_t reserved18;  /* ordinal48 */
2659         uint32_t reserved19;  /* ordinal49 */
2660         uint32_t reserved20;  /* ordinal50 */
2661         uint32_t reserved21;  /* ordinal51 */
2662         uint32_t reserved22;  /* ordinal52 */
2663         uint32_t reserved23;  /* ordinal53 */
2664         uint32_t reserved24;  /* ordinal54 */
2665         uint32_t reserved25;  /* ordinal55 */
2666         uint32_t reserved26;  /* ordinal56 */
2667         uint32_t reserved27;  /* ordinal57 */
2668         uint32_t reserved28;  /* ordinal58 */
2669         uint32_t reserved29;  /* ordinal59 */
2670         uint32_t reserved30;  /* ordinal60 */
2671         uint32_t reserved31;  /* ordinal61 */
2672         uint32_t reserved32;  /* ordinal62 */
2673         uint32_t reserved33;  /* ordinal63 */
2674         uint32_t reserved34;  /* ordinal64 */
2675         uint32_t compute_user_data_0;  /* ordinal65 */
2676         uint32_t compute_user_data_1;  /* ordinal66 */
2677         uint32_t compute_user_data_2;  /* ordinal67 */
2678         uint32_t compute_user_data_3;  /* ordinal68 */
2679         uint32_t compute_user_data_4;  /* ordinal69 */
2680         uint32_t compute_user_data_5;  /* ordinal70 */
2681         uint32_t compute_user_data_6;  /* ordinal71 */
2682         uint32_t compute_user_data_7;  /* ordinal72 */
2683         uint32_t compute_user_data_8;  /* ordinal73 */
2684         uint32_t compute_user_data_9;  /* ordinal74 */
2685         uint32_t compute_user_data_10;  /* ordinal75 */
2686         uint32_t compute_user_data_11;  /* ordinal76 */
2687         uint32_t compute_user_data_12;  /* ordinal77 */
2688         uint32_t compute_user_data_13;  /* ordinal78 */
2689         uint32_t compute_user_data_14;  /* ordinal79 */
2690         uint32_t compute_user_data_15;  /* ordinal80 */
2691         uint32_t cp_compute_csinvoc_count_lo;  /* ordinal81 */
2692         uint32_t cp_compute_csinvoc_count_hi;  /* ordinal82 */
2693         uint32_t reserved35;  /* ordinal83 */
2694         uint32_t reserved36;  /* ordinal84 */
2695         uint32_t reserved37;  /* ordinal85 */
2696         uint32_t cp_mqd_query_time_lo;  /* ordinal86 */
2697         uint32_t cp_mqd_query_time_hi;  /* ordinal87 */
2698         uint32_t cp_mqd_connect_start_time_lo;  /* ordinal88 */
2699         uint32_t cp_mqd_connect_start_time_hi;  /* ordinal89 */
2700         uint32_t cp_mqd_connect_end_time_lo;  /* ordinal90 */
2701         uint32_t cp_mqd_connect_end_time_hi;  /* ordinal91 */
2702         uint32_t cp_mqd_connect_end_wf_count;  /* ordinal92 */
2703         uint32_t cp_mqd_connect_end_pq_rptr;  /* ordinal93 */
2704         uint32_t cp_mqd_connect_end_pq_wptr;  /* ordinal94 */
2705         uint32_t cp_mqd_connect_end_ib_rptr;  /* ordinal95 */
2706         uint32_t reserved38;  /* ordinal96 */
2707         uint32_t reserved39;  /* ordinal97 */
2708         uint32_t cp_mqd_save_start_time_lo;  /* ordinal98 */
2709         uint32_t cp_mqd_save_start_time_hi;  /* ordinal99 */
2710         uint32_t cp_mqd_save_end_time_lo;  /* ordinal100 */
2711         uint32_t cp_mqd_save_end_time_hi;  /* ordinal101 */
2712         uint32_t cp_mqd_restore_start_time_lo;  /* ordinal102 */
2713         uint32_t cp_mqd_restore_start_time_hi;  /* ordinal103 */
2714         uint32_t cp_mqd_restore_end_time_lo;  /* ordinal104 */
2715         uint32_t cp_mqd_restore_end_time_hi;  /* ordinal105 */
2716         uint32_t reserved40;  /* ordinal106 */
2717         uint32_t reserved41;  /* ordinal107 */
2718         uint32_t gds_cs_ctxsw_cnt0;  /* ordinal108 */
2719         uint32_t gds_cs_ctxsw_cnt1;  /* ordinal109 */
2720         uint32_t gds_cs_ctxsw_cnt2;  /* ordinal110 */
2721         uint32_t gds_cs_ctxsw_cnt3;  /* ordinal111 */
2722         uint32_t reserved42;  /* ordinal112 */
2723         uint32_t reserved43;  /* ordinal113 */
2724         uint32_t cp_pq_exe_status_lo;  /* ordinal114 */
2725         uint32_t cp_pq_exe_status_hi;  /* ordinal115 */
2726         uint32_t cp_packet_id_lo;  /* ordinal116 */
2727         uint32_t cp_packet_id_hi;  /* ordinal117 */
2728         uint32_t cp_packet_exe_status_lo;  /* ordinal118 */
2729         uint32_t cp_packet_exe_status_hi;  /* ordinal119 */
2730         uint32_t gds_save_base_addr_lo;  /* ordinal120 */
2731         uint32_t gds_save_base_addr_hi;  /* ordinal121 */
2732         uint32_t gds_save_mask_lo;  /* ordinal122 */
2733         uint32_t gds_save_mask_hi;  /* ordinal123 */
2734         uint32_t ctx_save_base_addr_lo;  /* ordinal124 */
2735         uint32_t ctx_save_base_addr_hi;  /* ordinal125 */
2736         uint32_t reserved44;  /* ordinal126 */
2737         uint32_t reserved45;  /* ordinal127 */
2738         uint32_t cp_mqd_base_addr_lo;  /* ordinal128 */
2739         uint32_t cp_mqd_base_addr_hi;  /* ordinal129 */
2740         uint32_t cp_hqd_active;  /* ordinal130 */
2741         uint32_t cp_hqd_vmid;  /* ordinal131 */
2742         uint32_t cp_hqd_persistent_state;  /* ordinal132 */
2743         uint32_t cp_hqd_pipe_priority;  /* ordinal133 */
2744         uint32_t cp_hqd_queue_priority;  /* ordinal134 */
2745         uint32_t cp_hqd_quantum;  /* ordinal135 */
2746         uint32_t cp_hqd_pq_base_lo;  /* ordinal136 */
2747         uint32_t cp_hqd_pq_base_hi;  /* ordinal137 */
2748         uint32_t cp_hqd_pq_rptr;  /* ordinal138 */
2749         uint32_t cp_hqd_pq_rptr_report_addr_lo;  /* ordinal139 */
2750         uint32_t cp_hqd_pq_rptr_report_addr_hi;  /* ordinal140 */
2751         uint32_t cp_hqd_pq_wptr_poll_addr;  /* ordinal141 */
2752         uint32_t cp_hqd_pq_wptr_poll_addr_hi;  /* ordinal142 */
2753         uint32_t cp_hqd_pq_doorbell_control;  /* ordinal143 */
2754         uint32_t cp_hqd_pq_wptr;  /* ordinal144 */
2755         uint32_t cp_hqd_pq_control;  /* ordinal145 */
2756         uint32_t cp_hqd_ib_base_addr_lo;  /* ordinal146 */
2757         uint32_t cp_hqd_ib_base_addr_hi;  /* ordinal147 */
2758         uint32_t cp_hqd_ib_rptr;  /* ordinal148 */
2759         uint32_t cp_hqd_ib_control;  /* ordinal149 */
2760         uint32_t cp_hqd_iq_timer;  /* ordinal150 */
2761         uint32_t cp_hqd_iq_rptr;  /* ordinal151 */
2762         uint32_t cp_hqd_dequeue_request;  /* ordinal152 */
2763         uint32_t cp_hqd_dma_offload;  /* ordinal153 */
2764         uint32_t cp_hqd_sema_cmd;  /* ordinal154 */
2765         uint32_t cp_hqd_msg_type;  /* ordinal155 */
2766         uint32_t cp_hqd_atomic0_preop_lo;  /* ordinal156 */
2767         uint32_t cp_hqd_atomic0_preop_hi;  /* ordinal157 */
2768         uint32_t cp_hqd_atomic1_preop_lo;  /* ordinal158 */
2769         uint32_t cp_hqd_atomic1_preop_hi;  /* ordinal159 */
2770         uint32_t cp_hqd_hq_status0;  /* ordinal160 */
2771         uint32_t cp_hqd_hq_control0;  /* ordinal161 */
2772         uint32_t cp_mqd_control;  /* ordinal162 */
2773         uint32_t cp_hqd_hq_status1;  /* ordinal163 */
2774         uint32_t cp_hqd_hq_control1;  /* ordinal164 */
2775         uint32_t cp_hqd_eop_base_addr_lo;  /* ordinal165 */
2776         uint32_t cp_hqd_eop_base_addr_hi;  /* ordinal166 */
2777         uint32_t cp_hqd_eop_control;  /* ordinal167 */
2778         uint32_t cp_hqd_eop_rptr;  /* ordinal168 */
2779         uint32_t cp_hqd_eop_wptr;  /* ordinal169 */
2780         uint32_t cp_hqd_eop_done_events;  /* ordinal170 */
2781         uint32_t cp_hqd_ctx_save_base_addr_lo;  /* ordinal171 */
2782         uint32_t cp_hqd_ctx_save_base_addr_hi;  /* ordinal172 */
2783         uint32_t cp_hqd_ctx_save_control;  /* ordinal173 */
2784         uint32_t cp_hqd_cntl_stack_offset;  /* ordinal174 */
2785         uint32_t cp_hqd_cntl_stack_size;  /* ordinal175 */
2786         uint32_t cp_hqd_wg_state_offset;  /* ordinal176 */
2787         uint32_t cp_hqd_ctx_save_size;  /* ordinal177 */
2788         uint32_t cp_hqd_gds_resource_state;  /* ordinal178 */
2789         uint32_t cp_hqd_error;  /* ordinal179 */
2790         uint32_t cp_hqd_eop_wptr_mem;  /* ordinal180 */
2791         uint32_t cp_hqd_eop_dones;  /* ordinal181 */
2792         uint32_t reserved46;  /* ordinal182 */
2793         uint32_t reserved47;  /* ordinal183 */
2794         uint32_t reserved48;  /* ordinal184 */
2795         uint32_t reserved49;  /* ordinal185 */
2796         uint32_t reserved50;  /* ordinal186 */
2797         uint32_t reserved51;  /* ordinal187 */
2798         uint32_t reserved52;  /* ordinal188 */
2799         uint32_t reserved53;  /* ordinal189 */
2800         uint32_t reserved54;  /* ordinal190 */
2801         uint32_t reserved55;  /* ordinal191 */
2802         uint32_t iqtimer_pkt_header;  /* ordinal192 */
2803         uint32_t iqtimer_pkt_dw0;  /* ordinal193 */
2804         uint32_t iqtimer_pkt_dw1;  /* ordinal194 */
2805         uint32_t iqtimer_pkt_dw2;  /* ordinal195 */
2806         uint32_t iqtimer_pkt_dw3;  /* ordinal196 */
2807         uint32_t iqtimer_pkt_dw4;  /* ordinal197 */
2808         uint32_t iqtimer_pkt_dw5;  /* ordinal198 */
2809         uint32_t iqtimer_pkt_dw6;  /* ordinal199 */
2810         uint32_t iqtimer_pkt_dw7;  /* ordinal200 */
2811         uint32_t iqtimer_pkt_dw8;  /* ordinal201 */
2812         uint32_t iqtimer_pkt_dw9;  /* ordinal202 */
2813         uint32_t iqtimer_pkt_dw10;  /* ordinal203 */
2814         uint32_t iqtimer_pkt_dw11;  /* ordinal204 */
2815         uint32_t iqtimer_pkt_dw12;  /* ordinal205 */
2816         uint32_t iqtimer_pkt_dw13;  /* ordinal206 */
2817         uint32_t iqtimer_pkt_dw14;  /* ordinal207 */
2818         uint32_t iqtimer_pkt_dw15;  /* ordinal208 */
2819         uint32_t iqtimer_pkt_dw16;  /* ordinal209 */
2820         uint32_t iqtimer_pkt_dw17;  /* ordinal210 */
2821         uint32_t iqtimer_pkt_dw18;  /* ordinal211 */
2822         uint32_t iqtimer_pkt_dw19;  /* ordinal212 */
2823         uint32_t iqtimer_pkt_dw20;  /* ordinal213 */
2824         uint32_t iqtimer_pkt_dw21;  /* ordinal214 */
2825         uint32_t iqtimer_pkt_dw22;  /* ordinal215 */
2826         uint32_t iqtimer_pkt_dw23;  /* ordinal216 */
2827         uint32_t iqtimer_pkt_dw24;  /* ordinal217 */
2828         uint32_t iqtimer_pkt_dw25;  /* ordinal218 */
2829         uint32_t iqtimer_pkt_dw26;  /* ordinal219 */
2830         uint32_t iqtimer_pkt_dw27;  /* ordinal220 */
2831         uint32_t iqtimer_pkt_dw28;  /* ordinal221 */
2832         uint32_t iqtimer_pkt_dw29;  /* ordinal222 */
2833         uint32_t iqtimer_pkt_dw30;  /* ordinal223 */
2834         uint32_t iqtimer_pkt_dw31;  /* ordinal224 */
2835         uint32_t reserved56;  /* ordinal225 */
2836         uint32_t reserved57;  /* ordinal226 */
2837         uint32_t reserved58;  /* ordinal227 */
2838         uint32_t set_resources_header;  /* ordinal228 */
2839         uint32_t set_resources_dw1;  /* ordinal229 */
2840         uint32_t set_resources_dw2;  /* ordinal230 */
2841         uint32_t set_resources_dw3;  /* ordinal231 */
2842         uint32_t set_resources_dw4;  /* ordinal232 */
2843         uint32_t set_resources_dw5;  /* ordinal233 */
2844         uint32_t set_resources_dw6;  /* ordinal234 */
2845         uint32_t set_resources_dw7;  /* ordinal235 */
2846         uint32_t reserved59;  /* ordinal236 */
2847         uint32_t reserved60;  /* ordinal237 */
2848         uint32_t reserved61;  /* ordinal238 */
2849         uint32_t reserved62;  /* ordinal239 */
2850         uint32_t reserved63;  /* ordinal240 */
2851         uint32_t reserved64;  /* ordinal241 */
2852         uint32_t reserved65;  /* ordinal242 */
2853         uint32_t reserved66;  /* ordinal243 */
2854         uint32_t reserved67;  /* ordinal244 */
2855         uint32_t reserved68;  /* ordinal245 */
2856         uint32_t reserved69;  /* ordinal246 */
2857         uint32_t reserved70;  /* ordinal247 */
2858         uint32_t reserved71;  /* ordinal248 */
2859         uint32_t reserved72;  /* ordinal249 */
2860         uint32_t reserved73;  /* ordinal250 */
2861         uint32_t reserved74;  /* ordinal251 */
2862         uint32_t reserved75;  /* ordinal252 */
2863         uint32_t reserved76;  /* ordinal253 */
2864         uint32_t reserved77;  /* ordinal254 */
2865         uint32_t reserved78;  /* ordinal255 */
2866
2867         uint32_t reserved_t[256]; /* Reserve 256 dword buffer used by ucode */
2868 };
2869
2870 static void gfx_v8_0_cp_compute_fini(struct amdgpu_device *adev)
2871 {
2872         int i, r;
2873
2874         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2875                 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
2876
2877                 if (ring->mqd_obj) {
2878                         r = amdgpu_bo_reserve(ring->mqd_obj, false);
2879                         if (unlikely(r != 0))
2880                                 dev_warn(adev->dev, "(%d) reserve MQD bo failed\n", r);
2881
2882                         amdgpu_bo_unpin(ring->mqd_obj);
2883                         amdgpu_bo_unreserve(ring->mqd_obj);
2884
2885                         amdgpu_bo_unref(&ring->mqd_obj);
2886                         ring->mqd_obj = NULL;
2887                 }
2888         }
2889 }
2890
2891 static int gfx_v8_0_cp_compute_resume(struct amdgpu_device *adev)
2892 {
2893         int r, i, j;
2894         u32 tmp;
2895         bool use_doorbell = true;
2896         u64 hqd_gpu_addr;
2897         u64 mqd_gpu_addr;
2898         u64 eop_gpu_addr;
2899         u64 wb_gpu_addr;
2900         u32 *buf;
2901         struct vi_mqd *mqd;
2902
2903         /* init the pipes */
2904         mutex_lock(&adev->srbm_mutex);
2905         for (i = 0; i < (adev->gfx.mec.num_pipe * adev->gfx.mec.num_mec); i++) {
2906                 int me = (i < 4) ? 1 : 2;
2907                 int pipe = (i < 4) ? i : (i - 4);
2908
2909                 eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE);
2910                 eop_gpu_addr >>= 8;
2911
2912                 vi_srbm_select(adev, me, pipe, 0, 0);
2913
2914                 /* write the EOP addr */
2915                 WREG32(mmCP_HQD_EOP_BASE_ADDR, eop_gpu_addr);
2916                 WREG32(mmCP_HQD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr));
2917
2918                 /* set the VMID assigned */
2919                 WREG32(mmCP_HQD_VMID, 0);
2920
2921                 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
2922                 tmp = RREG32(mmCP_HQD_EOP_CONTROL);
2923                 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
2924                                     (order_base_2(MEC_HPD_SIZE / 4) - 1));
2925                 WREG32(mmCP_HQD_EOP_CONTROL, tmp);
2926         }
2927         vi_srbm_select(adev, 0, 0, 0, 0);
2928         mutex_unlock(&adev->srbm_mutex);
2929
2930         /* init the queues.  Just two for now. */
2931         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2932                 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
2933
2934                 if (ring->mqd_obj == NULL) {
2935                         r = amdgpu_bo_create(adev,
2936                                              sizeof(struct vi_mqd),
2937                                              PAGE_SIZE, true,
2938                                              AMDGPU_GEM_DOMAIN_GTT, 0, NULL,
2939                                              &ring->mqd_obj);
2940                         if (r) {
2941                                 dev_warn(adev->dev, "(%d) create MQD bo failed\n", r);
2942                                 return r;
2943                         }
2944                 }
2945
2946                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
2947                 if (unlikely(r != 0)) {
2948                         gfx_v8_0_cp_compute_fini(adev);
2949                         return r;
2950                 }
2951                 r = amdgpu_bo_pin(ring->mqd_obj, AMDGPU_GEM_DOMAIN_GTT,
2952                                   &mqd_gpu_addr);
2953                 if (r) {
2954                         dev_warn(adev->dev, "(%d) pin MQD bo failed\n", r);
2955                         gfx_v8_0_cp_compute_fini(adev);
2956                         return r;
2957                 }
2958                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&buf);
2959                 if (r) {
2960                         dev_warn(adev->dev, "(%d) map MQD bo failed\n", r);
2961                         gfx_v8_0_cp_compute_fini(adev);
2962                         return r;
2963                 }
2964
2965                 /* init the mqd struct */
2966                 memset(buf, 0, sizeof(struct vi_mqd));
2967
2968                 mqd = (struct vi_mqd *)buf;
2969                 mqd->header = 0xC0310800;
2970                 mqd->compute_pipelinestat_enable = 0x00000001;
2971                 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
2972                 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
2973                 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
2974                 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
2975                 mqd->compute_misc_reserved = 0x00000003;
2976
2977                 mutex_lock(&adev->srbm_mutex);
2978                 vi_srbm_select(adev, ring->me,
2979                                ring->pipe,
2980                                ring->queue, 0);
2981
2982                 /* disable wptr polling */
2983                 tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL);
2984                 tmp = REG_SET_FIELD(tmp, CP_PQ_WPTR_POLL_CNTL, EN, 0);
2985                 WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp);
2986
2987                 mqd->cp_hqd_eop_base_addr_lo =
2988                         RREG32(mmCP_HQD_EOP_BASE_ADDR);
2989                 mqd->cp_hqd_eop_base_addr_hi =
2990                         RREG32(mmCP_HQD_EOP_BASE_ADDR_HI);
2991
2992                 /* enable doorbell? */
2993                 tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
2994                 if (use_doorbell) {
2995                         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
2996                 } else {
2997                         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 0);
2998                 }
2999                 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, tmp);
3000                 mqd->cp_hqd_pq_doorbell_control = tmp;
3001
3002                 /* disable the queue if it's active */
3003                 mqd->cp_hqd_dequeue_request = 0;
3004                 mqd->cp_hqd_pq_rptr = 0;
3005                 mqd->cp_hqd_pq_wptr= 0;
3006                 if (RREG32(mmCP_HQD_ACTIVE) & 1) {
3007                         WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1);
3008                         for (j = 0; j < adev->usec_timeout; j++) {
3009                                 if (!(RREG32(mmCP_HQD_ACTIVE) & 1))
3010                                         break;
3011                                 udelay(1);
3012                         }
3013                         WREG32(mmCP_HQD_DEQUEUE_REQUEST, mqd->cp_hqd_dequeue_request);
3014                         WREG32(mmCP_HQD_PQ_RPTR, mqd->cp_hqd_pq_rptr);
3015                         WREG32(mmCP_HQD_PQ_WPTR, mqd->cp_hqd_pq_wptr);
3016                 }
3017
3018                 /* set the pointer to the MQD */
3019                 mqd->cp_mqd_base_addr_lo = mqd_gpu_addr & 0xfffffffc;
3020                 mqd->cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);
3021                 WREG32(mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo);
3022                 WREG32(mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
3023
3024                 /* set MQD vmid to 0 */
3025                 tmp = RREG32(mmCP_MQD_CONTROL);
3026                 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
3027                 WREG32(mmCP_MQD_CONTROL, tmp);
3028                 mqd->cp_mqd_control = tmp;
3029
3030                 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3031                 hqd_gpu_addr = ring->gpu_addr >> 8;
3032                 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
3033                 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
3034                 WREG32(mmCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo);
3035                 WREG32(mmCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi);
3036
3037                 /* set up the HQD, this is similar to CP_RB0_CNTL */
3038                 tmp = RREG32(mmCP_HQD_PQ_CONTROL);
3039                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
3040                                     (order_base_2(ring->ring_size / 4) - 1));
3041                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
3042                                ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
3043 #ifdef __BIG_ENDIAN
3044                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
3045 #endif
3046                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
3047                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
3048                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
3049                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
3050                 WREG32(mmCP_HQD_PQ_CONTROL, tmp);
3051                 mqd->cp_hqd_pq_control = tmp;
3052
3053                 /* set the wb address wether it's enabled or not */
3054                 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
3055                 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
3056                 mqd->cp_hqd_pq_rptr_report_addr_hi =
3057                         upper_32_bits(wb_gpu_addr) & 0xffff;
3058                 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR,
3059                        mqd->cp_hqd_pq_rptr_report_addr_lo);
3060                 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
3061                        mqd->cp_hqd_pq_rptr_report_addr_hi);
3062
3063                 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3064                 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3065                 mqd->cp_hqd_pq_wptr_poll_addr = wb_gpu_addr & 0xfffffffc;
3066                 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
3067                 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, mqd->cp_hqd_pq_wptr_poll_addr);
3068                 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
3069                        mqd->cp_hqd_pq_wptr_poll_addr_hi);
3070
3071                 /* enable the doorbell if requested */
3072                 if (use_doorbell) {
3073                         if (adev->asic_type == CHIP_CARRIZO) {
3074                                 WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER,
3075                                        AMDGPU_DOORBELL_KIQ << 2);
3076                                 WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER,
3077                                        AMDGPU_DOORBELL_MEC_RING7 << 2);
3078                         }
3079                         tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
3080                         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3081                                             DOORBELL_OFFSET, ring->doorbell_index);
3082                         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
3083                         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_SOURCE, 0);
3084                         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_HIT, 0);
3085                         mqd->cp_hqd_pq_doorbell_control = tmp;
3086
3087                 } else {
3088                         mqd->cp_hqd_pq_doorbell_control = 0;
3089                 }
3090                 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL,
3091                        mqd->cp_hqd_pq_doorbell_control);
3092
3093                 /* set the vmid for the queue */
3094                 mqd->cp_hqd_vmid = 0;
3095                 WREG32(mmCP_HQD_VMID, mqd->cp_hqd_vmid);
3096
3097                 tmp = RREG32(mmCP_HQD_PERSISTENT_STATE);
3098                 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
3099                 WREG32(mmCP_HQD_PERSISTENT_STATE, tmp);
3100                 mqd->cp_hqd_persistent_state = tmp;
3101
3102                 /* activate the queue */
3103                 mqd->cp_hqd_active = 1;
3104                 WREG32(mmCP_HQD_ACTIVE, mqd->cp_hqd_active);
3105
3106                 vi_srbm_select(adev, 0, 0, 0, 0);
3107                 mutex_unlock(&adev->srbm_mutex);
3108
3109                 amdgpu_bo_kunmap(ring->mqd_obj);
3110                 amdgpu_bo_unreserve(ring->mqd_obj);
3111         }
3112
3113         if (use_doorbell) {
3114                 tmp = RREG32(mmCP_PQ_STATUS);
3115                 tmp = REG_SET_FIELD(tmp, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
3116                 WREG32(mmCP_PQ_STATUS, tmp);
3117         }
3118
3119         r = gfx_v8_0_cp_compute_start(adev);
3120         if (r)
3121                 return r;
3122
3123         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3124                 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
3125
3126                 ring->ready = true;
3127                 r = amdgpu_ring_test_ring(ring);
3128                 if (r)
3129                         ring->ready = false;
3130         }
3131
3132         return 0;
3133 }
3134
3135 static int gfx_v8_0_cp_resume(struct amdgpu_device *adev)
3136 {
3137         int r;
3138
3139         if (adev->asic_type != CHIP_CARRIZO)
3140                 gfx_v8_0_enable_gui_idle_interrupt(adev, false);
3141
3142         if (!adev->firmware.smu_load) {
3143                 /* legacy firmware loading */
3144                 r = gfx_v8_0_cp_gfx_load_microcode(adev);
3145                 if (r)
3146                         return r;
3147
3148                 r = gfx_v8_0_cp_compute_load_microcode(adev);
3149                 if (r)
3150                         return r;
3151         } else {
3152                 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
3153                                                 AMDGPU_UCODE_ID_CP_CE);
3154                 if (r)
3155                         return -EINVAL;
3156
3157                 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
3158                                                 AMDGPU_UCODE_ID_CP_PFP);
3159                 if (r)
3160                         return -EINVAL;
3161
3162                 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
3163                                                 AMDGPU_UCODE_ID_CP_ME);
3164                 if (r)
3165                         return -EINVAL;
3166
3167                 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
3168                                                 AMDGPU_UCODE_ID_CP_MEC1);
3169                 if (r)
3170                         return -EINVAL;
3171         }
3172
3173         r = gfx_v8_0_cp_gfx_resume(adev);
3174         if (r)
3175                 return r;
3176
3177         r = gfx_v8_0_cp_compute_resume(adev);
3178         if (r)
3179                 return r;
3180
3181         gfx_v8_0_enable_gui_idle_interrupt(adev, true);
3182
3183         return 0;
3184 }
3185
3186 static void gfx_v8_0_cp_enable(struct amdgpu_device *adev, bool enable)
3187 {
3188         gfx_v8_0_cp_gfx_enable(adev, enable);
3189         gfx_v8_0_cp_compute_enable(adev, enable);
3190 }
3191
3192 static int gfx_v8_0_hw_init(void *handle)
3193 {
3194         int r;
3195         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3196
3197         gfx_v8_0_init_golden_registers(adev);
3198
3199         gfx_v8_0_gpu_init(adev);
3200
3201         r = gfx_v8_0_rlc_resume(adev);
3202         if (r)
3203                 return r;
3204
3205         r = gfx_v8_0_cp_resume(adev);
3206         if (r)
3207                 return r;
3208
3209         return r;
3210 }
3211
3212 static int gfx_v8_0_hw_fini(void *handle)
3213 {
3214         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3215
3216         gfx_v8_0_cp_enable(adev, false);
3217         gfx_v8_0_rlc_stop(adev);
3218         gfx_v8_0_cp_compute_fini(adev);
3219
3220         return 0;
3221 }
3222
3223 static int gfx_v8_0_suspend(void *handle)
3224 {
3225         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3226
3227         return gfx_v8_0_hw_fini(adev);
3228 }
3229
3230 static int gfx_v8_0_resume(void *handle)
3231 {
3232         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3233
3234         return gfx_v8_0_hw_init(adev);
3235 }
3236
3237 static bool gfx_v8_0_is_idle(void *handle)
3238 {
3239         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3240
3241         if (REG_GET_FIELD(RREG32(mmGRBM_STATUS), GRBM_STATUS, GUI_ACTIVE))
3242                 return false;
3243         else
3244                 return true;
3245 }
3246
3247 static int gfx_v8_0_wait_for_idle(void *handle)
3248 {
3249         unsigned i;
3250         u32 tmp;
3251         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3252
3253         for (i = 0; i < adev->usec_timeout; i++) {
3254                 /* read MC_STATUS */
3255                 tmp = RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK;
3256
3257                 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
3258                         return 0;
3259                 udelay(1);
3260         }
3261         return -ETIMEDOUT;
3262 }
3263
3264 static void gfx_v8_0_print_status(void *handle)
3265 {
3266         int i;
3267         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3268
3269         dev_info(adev->dev, "GFX 8.x registers\n");
3270         dev_info(adev->dev, "  GRBM_STATUS=0x%08X\n",
3271                  RREG32(mmGRBM_STATUS));
3272         dev_info(adev->dev, "  GRBM_STATUS2=0x%08X\n",
3273                  RREG32(mmGRBM_STATUS2));
3274         dev_info(adev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
3275                  RREG32(mmGRBM_STATUS_SE0));
3276         dev_info(adev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
3277                  RREG32(mmGRBM_STATUS_SE1));
3278         dev_info(adev->dev, "  GRBM_STATUS_SE2=0x%08X\n",
3279                  RREG32(mmGRBM_STATUS_SE2));
3280         dev_info(adev->dev, "  GRBM_STATUS_SE3=0x%08X\n",
3281                  RREG32(mmGRBM_STATUS_SE3));
3282         dev_info(adev->dev, "  CP_STAT = 0x%08x\n", RREG32(mmCP_STAT));
3283         dev_info(adev->dev, "  CP_STALLED_STAT1 = 0x%08x\n",
3284                  RREG32(mmCP_STALLED_STAT1));
3285         dev_info(adev->dev, "  CP_STALLED_STAT2 = 0x%08x\n",
3286                  RREG32(mmCP_STALLED_STAT2));
3287         dev_info(adev->dev, "  CP_STALLED_STAT3 = 0x%08x\n",
3288                  RREG32(mmCP_STALLED_STAT3));
3289         dev_info(adev->dev, "  CP_CPF_BUSY_STAT = 0x%08x\n",
3290                  RREG32(mmCP_CPF_BUSY_STAT));
3291         dev_info(adev->dev, "  CP_CPF_STALLED_STAT1 = 0x%08x\n",
3292                  RREG32(mmCP_CPF_STALLED_STAT1));
3293         dev_info(adev->dev, "  CP_CPF_STATUS = 0x%08x\n", RREG32(mmCP_CPF_STATUS));
3294         dev_info(adev->dev, "  CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(mmCP_CPC_BUSY_STAT));
3295         dev_info(adev->dev, "  CP_CPC_STALLED_STAT1 = 0x%08x\n",
3296                  RREG32(mmCP_CPC_STALLED_STAT1));
3297         dev_info(adev->dev, "  CP_CPC_STATUS = 0x%08x\n", RREG32(mmCP_CPC_STATUS));
3298
3299         for (i = 0; i < 32; i++) {
3300                 dev_info(adev->dev, "  GB_TILE_MODE%d=0x%08X\n",
3301                          i, RREG32(mmGB_TILE_MODE0 + (i * 4)));
3302         }
3303         for (i = 0; i < 16; i++) {
3304                 dev_info(adev->dev, "  GB_MACROTILE_MODE%d=0x%08X\n",
3305                          i, RREG32(mmGB_MACROTILE_MODE0 + (i * 4)));
3306         }
3307         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3308                 dev_info(adev->dev, "  se: %d\n", i);
3309                 gfx_v8_0_select_se_sh(adev, i, 0xffffffff);
3310                 dev_info(adev->dev, "  PA_SC_RASTER_CONFIG=0x%08X\n",
3311                          RREG32(mmPA_SC_RASTER_CONFIG));
3312                 dev_info(adev->dev, "  PA_SC_RASTER_CONFIG_1=0x%08X\n",
3313                          RREG32(mmPA_SC_RASTER_CONFIG_1));
3314         }
3315         gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
3316
3317         dev_info(adev->dev, "  GB_ADDR_CONFIG=0x%08X\n",
3318                  RREG32(mmGB_ADDR_CONFIG));
3319         dev_info(adev->dev, "  HDP_ADDR_CONFIG=0x%08X\n",
3320                  RREG32(mmHDP_ADDR_CONFIG));
3321         dev_info(adev->dev, "  DMIF_ADDR_CALC=0x%08X\n",
3322                  RREG32(mmDMIF_ADDR_CALC));
3323         dev_info(adev->dev, "  SDMA0_TILING_CONFIG=0x%08X\n",
3324                  RREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET));
3325         dev_info(adev->dev, "  SDMA1_TILING_CONFIG=0x%08X\n",
3326                  RREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET));
3327         dev_info(adev->dev, "  UVD_UDEC_ADDR_CONFIG=0x%08X\n",
3328                  RREG32(mmUVD_UDEC_ADDR_CONFIG));
3329         dev_info(adev->dev, "  UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n",
3330                  RREG32(mmUVD_UDEC_DB_ADDR_CONFIG));
3331         dev_info(adev->dev, "  UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n",
3332                  RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG));
3333
3334         dev_info(adev->dev, "  CP_MEQ_THRESHOLDS=0x%08X\n",
3335                  RREG32(mmCP_MEQ_THRESHOLDS));
3336         dev_info(adev->dev, "  SX_DEBUG_1=0x%08X\n",
3337                  RREG32(mmSX_DEBUG_1));
3338         dev_info(adev->dev, "  TA_CNTL_AUX=0x%08X\n",
3339                  RREG32(mmTA_CNTL_AUX));
3340         dev_info(adev->dev, "  SPI_CONFIG_CNTL=0x%08X\n",
3341                  RREG32(mmSPI_CONFIG_CNTL));
3342         dev_info(adev->dev, "  SQ_CONFIG=0x%08X\n",
3343                  RREG32(mmSQ_CONFIG));
3344         dev_info(adev->dev, "  DB_DEBUG=0x%08X\n",
3345                  RREG32(mmDB_DEBUG));
3346         dev_info(adev->dev, "  DB_DEBUG2=0x%08X\n",
3347                  RREG32(mmDB_DEBUG2));
3348         dev_info(adev->dev, "  DB_DEBUG3=0x%08X\n",
3349                  RREG32(mmDB_DEBUG3));
3350         dev_info(adev->dev, "  CB_HW_CONTROL=0x%08X\n",
3351                  RREG32(mmCB_HW_CONTROL));
3352         dev_info(adev->dev, "  SPI_CONFIG_CNTL_1=0x%08X\n",
3353                  RREG32(mmSPI_CONFIG_CNTL_1));
3354         dev_info(adev->dev, "  PA_SC_FIFO_SIZE=0x%08X\n",
3355                  RREG32(mmPA_SC_FIFO_SIZE));
3356         dev_info(adev->dev, "  VGT_NUM_INSTANCES=0x%08X\n",
3357                  RREG32(mmVGT_NUM_INSTANCES));
3358         dev_info(adev->dev, "  CP_PERFMON_CNTL=0x%08X\n",
3359                  RREG32(mmCP_PERFMON_CNTL));
3360         dev_info(adev->dev, "  PA_SC_FORCE_EOV_MAX_CNTS=0x%08X\n",
3361                  RREG32(mmPA_SC_FORCE_EOV_MAX_CNTS));
3362         dev_info(adev->dev, "  VGT_CACHE_INVALIDATION=0x%08X\n",
3363                  RREG32(mmVGT_CACHE_INVALIDATION));
3364         dev_info(adev->dev, "  VGT_GS_VERTEX_REUSE=0x%08X\n",
3365                  RREG32(mmVGT_GS_VERTEX_REUSE));
3366         dev_info(adev->dev, "  PA_SC_LINE_STIPPLE_STATE=0x%08X\n",
3367                  RREG32(mmPA_SC_LINE_STIPPLE_STATE));
3368         dev_info(adev->dev, "  PA_CL_ENHANCE=0x%08X\n",
3369                  RREG32(mmPA_CL_ENHANCE));
3370         dev_info(adev->dev, "  PA_SC_ENHANCE=0x%08X\n",
3371                  RREG32(mmPA_SC_ENHANCE));
3372
3373         dev_info(adev->dev, "  CP_ME_CNTL=0x%08X\n",
3374                  RREG32(mmCP_ME_CNTL));
3375         dev_info(adev->dev, "  CP_MAX_CONTEXT=0x%08X\n",
3376                  RREG32(mmCP_MAX_CONTEXT));
3377         dev_info(adev->dev, "  CP_ENDIAN_SWAP=0x%08X\n",
3378                  RREG32(mmCP_ENDIAN_SWAP));
3379         dev_info(adev->dev, "  CP_DEVICE_ID=0x%08X\n",
3380                  RREG32(mmCP_DEVICE_ID));
3381
3382         dev_info(adev->dev, "  CP_SEM_WAIT_TIMER=0x%08X\n",
3383                  RREG32(mmCP_SEM_WAIT_TIMER));
3384
3385         dev_info(adev->dev, "  CP_RB_WPTR_DELAY=0x%08X\n",
3386                  RREG32(mmCP_RB_WPTR_DELAY));
3387         dev_info(adev->dev, "  CP_RB_VMID=0x%08X\n",
3388                  RREG32(mmCP_RB_VMID));
3389         dev_info(adev->dev, "  CP_RB0_CNTL=0x%08X\n",
3390                  RREG32(mmCP_RB0_CNTL));
3391         dev_info(adev->dev, "  CP_RB0_WPTR=0x%08X\n",
3392                  RREG32(mmCP_RB0_WPTR));
3393         dev_info(adev->dev, "  CP_RB0_RPTR_ADDR=0x%08X\n",
3394                  RREG32(mmCP_RB0_RPTR_ADDR));
3395         dev_info(adev->dev, "  CP_RB0_RPTR_ADDR_HI=0x%08X\n",
3396                  RREG32(mmCP_RB0_RPTR_ADDR_HI));
3397         dev_info(adev->dev, "  CP_RB0_CNTL=0x%08X\n",
3398                  RREG32(mmCP_RB0_CNTL));
3399         dev_info(adev->dev, "  CP_RB0_BASE=0x%08X\n",
3400                  RREG32(mmCP_RB0_BASE));
3401         dev_info(adev->dev, "  CP_RB0_BASE_HI=0x%08X\n",
3402                  RREG32(mmCP_RB0_BASE_HI));
3403         dev_info(adev->dev, "  CP_MEC_CNTL=0x%08X\n",
3404                  RREG32(mmCP_MEC_CNTL));
3405         dev_info(adev->dev, "  CP_CPF_DEBUG=0x%08X\n",
3406                  RREG32(mmCP_CPF_DEBUG));
3407
3408         dev_info(adev->dev, "  SCRATCH_ADDR=0x%08X\n",
3409                  RREG32(mmSCRATCH_ADDR));
3410         dev_info(adev->dev, "  SCRATCH_UMSK=0x%08X\n",
3411                  RREG32(mmSCRATCH_UMSK));
3412
3413         dev_info(adev->dev, "  CP_INT_CNTL_RING0=0x%08X\n",
3414                  RREG32(mmCP_INT_CNTL_RING0));
3415         dev_info(adev->dev, "  RLC_LB_CNTL=0x%08X\n",
3416                  RREG32(mmRLC_LB_CNTL));
3417         dev_info(adev->dev, "  RLC_CNTL=0x%08X\n",
3418                  RREG32(mmRLC_CNTL));
3419         dev_info(adev->dev, "  RLC_CGCG_CGLS_CTRL=0x%08X\n",
3420                  RREG32(mmRLC_CGCG_CGLS_CTRL));
3421         dev_info(adev->dev, "  RLC_LB_CNTR_INIT=0x%08X\n",
3422                  RREG32(mmRLC_LB_CNTR_INIT));
3423         dev_info(adev->dev, "  RLC_LB_CNTR_MAX=0x%08X\n",
3424                  RREG32(mmRLC_LB_CNTR_MAX));
3425         dev_info(adev->dev, "  RLC_LB_INIT_CU_MASK=0x%08X\n",
3426                  RREG32(mmRLC_LB_INIT_CU_MASK));
3427         dev_info(adev->dev, "  RLC_LB_PARAMS=0x%08X\n",
3428                  RREG32(mmRLC_LB_PARAMS));
3429         dev_info(adev->dev, "  RLC_LB_CNTL=0x%08X\n",
3430                  RREG32(mmRLC_LB_CNTL));
3431         dev_info(adev->dev, "  RLC_MC_CNTL=0x%08X\n",
3432                  RREG32(mmRLC_MC_CNTL));
3433         dev_info(adev->dev, "  RLC_UCODE_CNTL=0x%08X\n",
3434                  RREG32(mmRLC_UCODE_CNTL));
3435
3436         mutex_lock(&adev->srbm_mutex);
3437         for (i = 0; i < 16; i++) {
3438                 vi_srbm_select(adev, 0, 0, 0, i);
3439                 dev_info(adev->dev, "  VM %d:\n", i);
3440                 dev_info(adev->dev, "  SH_MEM_CONFIG=0x%08X\n",
3441                          RREG32(mmSH_MEM_CONFIG));
3442                 dev_info(adev->dev, "  SH_MEM_APE1_BASE=0x%08X\n",
3443                          RREG32(mmSH_MEM_APE1_BASE));
3444                 dev_info(adev->dev, "  SH_MEM_APE1_LIMIT=0x%08X\n",
3445                          RREG32(mmSH_MEM_APE1_LIMIT));
3446                 dev_info(adev->dev, "  SH_MEM_BASES=0x%08X\n",
3447                          RREG32(mmSH_MEM_BASES));
3448         }
3449         vi_srbm_select(adev, 0, 0, 0, 0);
3450         mutex_unlock(&adev->srbm_mutex);
3451 }
3452
3453 static int gfx_v8_0_soft_reset(void *handle)
3454 {
3455         u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
3456         u32 tmp;
3457         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3458
3459         /* GRBM_STATUS */
3460         tmp = RREG32(mmGRBM_STATUS);
3461         if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
3462                    GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
3463                    GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
3464                    GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
3465                    GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
3466                    GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) {
3467                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3468                                                 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
3469                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3470                                                 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
3471         }
3472
3473         if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
3474                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3475                                                 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
3476                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
3477                                                 SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
3478         }
3479
3480         /* GRBM_STATUS2 */
3481         tmp = RREG32(mmGRBM_STATUS2);
3482         if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
3483                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3484                                                 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
3485
3486         /* SRBM_STATUS */
3487         tmp = RREG32(mmSRBM_STATUS);
3488         if (REG_GET_FIELD(tmp, SRBM_STATUS, GRBM_RQ_PENDING))
3489                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
3490                                                 SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
3491
3492         if (grbm_soft_reset || srbm_soft_reset) {
3493                 gfx_v8_0_print_status((void *)adev);
3494                 /* stop the rlc */
3495                 gfx_v8_0_rlc_stop(adev);
3496
3497                 /* Disable GFX parsing/prefetching */
3498                 gfx_v8_0_cp_gfx_enable(adev, false);
3499
3500                 /* Disable MEC parsing/prefetching */
3501                 /* XXX todo */
3502
3503                 if (grbm_soft_reset) {
3504                         tmp = RREG32(mmGRBM_SOFT_RESET);
3505                         tmp |= grbm_soft_reset;
3506                         dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
3507                         WREG32(mmGRBM_SOFT_RESET, tmp);
3508                         tmp = RREG32(mmGRBM_SOFT_RESET);
3509
3510                         udelay(50);
3511
3512                         tmp &= ~grbm_soft_reset;
3513                         WREG32(mmGRBM_SOFT_RESET, tmp);
3514                         tmp = RREG32(mmGRBM_SOFT_RESET);
3515                 }
3516
3517                 if (srbm_soft_reset) {
3518                         tmp = RREG32(mmSRBM_SOFT_RESET);
3519                         tmp |= srbm_soft_reset;
3520                         dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
3521                         WREG32(mmSRBM_SOFT_RESET, tmp);
3522                         tmp = RREG32(mmSRBM_SOFT_RESET);
3523
3524                         udelay(50);
3525
3526                         tmp &= ~srbm_soft_reset;
3527                         WREG32(mmSRBM_SOFT_RESET, tmp);
3528                         tmp = RREG32(mmSRBM_SOFT_RESET);
3529                 }
3530                 /* Wait a little for things to settle down */
3531                 udelay(50);
3532                 gfx_v8_0_print_status((void *)adev);
3533         }
3534         return 0;
3535 }
3536
3537 /**
3538  * gfx_v8_0_get_gpu_clock_counter - return GPU clock counter snapshot
3539  *
3540  * @adev: amdgpu_device pointer
3541  *
3542  * Fetches a GPU clock counter snapshot.
3543  * Returns the 64 bit clock counter snapshot.
3544  */
3545 uint64_t gfx_v8_0_get_gpu_clock_counter(struct amdgpu_device *adev)
3546 {
3547         uint64_t clock;
3548
3549         mutex_lock(&adev->gfx.gpu_clock_mutex);
3550         WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
3551         clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
3552                 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
3553         mutex_unlock(&adev->gfx.gpu_clock_mutex);
3554         return clock;
3555 }
3556
3557 static void gfx_v8_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
3558                                           uint32_t vmid,
3559                                           uint32_t gds_base, uint32_t gds_size,
3560                                           uint32_t gws_base, uint32_t gws_size,
3561                                           uint32_t oa_base, uint32_t oa_size)
3562 {
3563         gds_base = gds_base >> AMDGPU_GDS_SHIFT;
3564         gds_size = gds_size >> AMDGPU_GDS_SHIFT;
3565
3566         gws_base = gws_base >> AMDGPU_GWS_SHIFT;
3567         gws_size = gws_size >> AMDGPU_GWS_SHIFT;
3568
3569         oa_base = oa_base >> AMDGPU_OA_SHIFT;
3570         oa_size = oa_size >> AMDGPU_OA_SHIFT;
3571
3572         /* GDS Base */
3573         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3574         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3575                                 WRITE_DATA_DST_SEL(0)));
3576         amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_base);
3577         amdgpu_ring_write(ring, 0);
3578         amdgpu_ring_write(ring, gds_base);
3579
3580         /* GDS Size */
3581         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3582         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3583                                 WRITE_DATA_DST_SEL(0)));
3584         amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_size);
3585         amdgpu_ring_write(ring, 0);
3586         amdgpu_ring_write(ring, gds_size);
3587
3588         /* GWS */
3589         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3590         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3591                                 WRITE_DATA_DST_SEL(0)));
3592         amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].gws);
3593         amdgpu_ring_write(ring, 0);
3594         amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
3595
3596         /* OA */
3597         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3598         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3599                                 WRITE_DATA_DST_SEL(0)));
3600         amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].oa);
3601         amdgpu_ring_write(ring, 0);
3602         amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base));
3603 }
3604
3605 static int gfx_v8_0_early_init(void *handle)
3606 {
3607         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3608
3609         adev->gfx.num_gfx_rings = GFX8_NUM_GFX_RINGS;
3610         adev->gfx.num_compute_rings = GFX8_NUM_COMPUTE_RINGS;
3611         gfx_v8_0_set_ring_funcs(adev);
3612         gfx_v8_0_set_irq_funcs(adev);
3613         gfx_v8_0_set_gds_init(adev);
3614
3615         return 0;
3616 }
3617
3618 static int gfx_v8_0_set_powergating_state(void *handle,
3619                                           enum amd_powergating_state state)
3620 {
3621         return 0;
3622 }
3623
3624 static int gfx_v8_0_set_clockgating_state(void *handle,
3625                                           enum amd_clockgating_state state)
3626 {
3627         return 0;
3628 }
3629
3630 static u32 gfx_v8_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
3631 {
3632         u32 rptr;
3633
3634         rptr = ring->adev->wb.wb[ring->rptr_offs];
3635
3636         return rptr;
3637 }
3638
3639 static u32 gfx_v8_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
3640 {
3641         struct amdgpu_device *adev = ring->adev;
3642         u32 wptr;
3643
3644         if (ring->use_doorbell)
3645                 /* XXX check if swapping is necessary on BE */
3646                 wptr = ring->adev->wb.wb[ring->wptr_offs];
3647         else
3648                 wptr = RREG32(mmCP_RB0_WPTR);
3649
3650         return wptr;
3651 }
3652
3653 static void gfx_v8_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
3654 {
3655         struct amdgpu_device *adev = ring->adev;
3656
3657         if (ring->use_doorbell) {
3658                 /* XXX check if swapping is necessary on BE */
3659                 adev->wb.wb[ring->wptr_offs] = ring->wptr;
3660                 WDOORBELL32(ring->doorbell_index, ring->wptr);
3661         } else {
3662                 WREG32(mmCP_RB0_WPTR, ring->wptr);
3663                 (void)RREG32(mmCP_RB0_WPTR);
3664         }
3665 }
3666
3667 static void gfx_v8_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
3668 {
3669         u32 ref_and_mask, reg_mem_engine;
3670
3671         if (ring->type == AMDGPU_RING_TYPE_COMPUTE) {
3672                 switch (ring->me) {
3673                 case 1:
3674                         ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe;
3675                         break;
3676                 case 2:
3677                         ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe;
3678                         break;
3679                 default:
3680                         return;
3681                 }
3682                 reg_mem_engine = 0;
3683         } else {
3684                 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK;
3685                 reg_mem_engine = WAIT_REG_MEM_ENGINE(1); /* pfp */
3686         }
3687
3688         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3689         amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */
3690                                  WAIT_REG_MEM_FUNCTION(3) |  /* == */
3691                                  reg_mem_engine));
3692         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ);
3693         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE);
3694         amdgpu_ring_write(ring, ref_and_mask);
3695         amdgpu_ring_write(ring, ref_and_mask);
3696         amdgpu_ring_write(ring, 0x20); /* poll interval */
3697 }
3698
3699 static void gfx_v8_0_ring_emit_ib(struct amdgpu_ring *ring,
3700                                   struct amdgpu_ib *ib)
3701 {
3702         bool need_ctx_switch = ring->current_ctx != ib->ctx;
3703         u32 header, control = 0;
3704         u32 next_rptr = ring->wptr + 5;
3705
3706         /* drop the CE preamble IB for the same context */
3707         if ((ring->type == AMDGPU_RING_TYPE_GFX) &&
3708             (ib->flags & AMDGPU_IB_FLAG_PREAMBLE) &&
3709             !need_ctx_switch)
3710                 return;
3711
3712         if (ring->type == AMDGPU_RING_TYPE_COMPUTE)
3713                 control |= INDIRECT_BUFFER_VALID;
3714
3715         if (need_ctx_switch && ring->type == AMDGPU_RING_TYPE_GFX)
3716                 next_rptr += 2;
3717
3718         next_rptr += 4;
3719         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3720         amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM);
3721         amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3722         amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
3723         amdgpu_ring_write(ring, next_rptr);
3724
3725         /* insert SWITCH_BUFFER packet before first IB in the ring frame */
3726         if (need_ctx_switch && ring->type == AMDGPU_RING_TYPE_GFX) {
3727                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3728                 amdgpu_ring_write(ring, 0);
3729         }
3730
3731         if (ib->flags & AMDGPU_IB_FLAG_CE)
3732                 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
3733         else
3734                 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
3735
3736         control |= ib->length_dw |
3737                 (ib->vm ? (ib->vm->ids[ring->idx].id << 24) : 0);
3738
3739         amdgpu_ring_write(ring, header);
3740         amdgpu_ring_write(ring,
3741 #ifdef __BIG_ENDIAN
3742                           (2 << 0) |
3743 #endif
3744                           (ib->gpu_addr & 0xFFFFFFFC));
3745         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
3746         amdgpu_ring_write(ring, control);
3747 }
3748
3749 static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
3750                                          u64 seq, unsigned flags)
3751 {
3752         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
3753         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
3754
3755         /* EVENT_WRITE_EOP - flush caches, send int */
3756         amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
3757         amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
3758                                  EOP_TC_ACTION_EN |
3759                                  EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
3760                                  EVENT_INDEX(5)));
3761         amdgpu_ring_write(ring, addr & 0xfffffffc);
3762         amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
3763                           DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
3764         amdgpu_ring_write(ring, lower_32_bits(seq));
3765         amdgpu_ring_write(ring, upper_32_bits(seq));
3766 }
3767
3768 /**
3769  * gfx_v8_0_ring_emit_semaphore - emit a semaphore on the CP ring
3770  *
3771  * @ring: amdgpu ring buffer object
3772  * @semaphore: amdgpu semaphore object
3773  * @emit_wait: Is this a sempahore wait?
3774  *
3775  * Emits a semaphore signal/wait packet to the CP ring and prevents the PFP
3776  * from running ahead of semaphore waits.
3777  */
3778 static bool gfx_v8_0_ring_emit_semaphore(struct amdgpu_ring *ring,
3779                                          struct amdgpu_semaphore *semaphore,
3780                                          bool emit_wait)
3781 {
3782         uint64_t addr = semaphore->gpu_addr;
3783         unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
3784
3785         if (ring->adev->asic_type == CHIP_TOPAZ ||
3786             ring->adev->asic_type == CHIP_TONGA)
3787                 /* we got a hw semaphore bug in VI TONGA, return false to switch back to sw fence wait */
3788                 return false;
3789         else {
3790                 amdgpu_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 2));
3791                 amdgpu_ring_write(ring, lower_32_bits(addr));
3792                 amdgpu_ring_write(ring, upper_32_bits(addr));
3793                 amdgpu_ring_write(ring, sel);
3794         }
3795
3796         if (emit_wait && (ring->type == AMDGPU_RING_TYPE_GFX)) {
3797                 /* Prevent the PFP from running ahead of the semaphore wait */
3798                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
3799                 amdgpu_ring_write(ring, 0x0);
3800         }
3801
3802         return true;
3803 }
3804
3805 static void gfx_v8_0_ce_sync_me(struct amdgpu_ring *ring)
3806 {
3807         struct amdgpu_device *adev = ring->adev;
3808         u64 gpu_addr = adev->wb.gpu_addr + adev->gfx.ce_sync_offs * 4;
3809
3810         /* instruct DE to set a magic number */
3811         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3812         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3813                                                          WRITE_DATA_DST_SEL(5)));
3814         amdgpu_ring_write(ring, gpu_addr & 0xfffffffc);
3815         amdgpu_ring_write(ring, upper_32_bits(gpu_addr) & 0xffffffff);
3816         amdgpu_ring_write(ring, 1);
3817
3818         /* let CE wait till condition satisfied */
3819         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3820         amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */
3821                                                          WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
3822                                                          WAIT_REG_MEM_FUNCTION(3) |  /* == */
3823                                                          WAIT_REG_MEM_ENGINE(2)));   /* ce */
3824         amdgpu_ring_write(ring, gpu_addr & 0xfffffffc);
3825         amdgpu_ring_write(ring, upper_32_bits(gpu_addr) & 0xffffffff);
3826         amdgpu_ring_write(ring, 1);
3827         amdgpu_ring_write(ring, 0xffffffff);
3828         amdgpu_ring_write(ring, 4); /* poll interval */
3829
3830         /* instruct CE to reset wb of ce_sync to zero */
3831         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3832         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
3833                                                          WRITE_DATA_DST_SEL(5) |
3834                                                          WR_CONFIRM));
3835         amdgpu_ring_write(ring, gpu_addr & 0xfffffffc);
3836         amdgpu_ring_write(ring, upper_32_bits(gpu_addr) & 0xffffffff);
3837         amdgpu_ring_write(ring, 0);
3838 }
3839
3840 static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
3841                                         unsigned vm_id, uint64_t pd_addr)
3842 {
3843         int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
3844
3845         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3846         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
3847                                  WRITE_DATA_DST_SEL(0)));
3848         if (vm_id < 8) {
3849                 amdgpu_ring_write(ring,
3850                                   (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
3851         } else {
3852                 amdgpu_ring_write(ring,
3853                                   (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
3854         }
3855         amdgpu_ring_write(ring, 0);
3856         amdgpu_ring_write(ring, pd_addr >> 12);
3857
3858         /* bits 0-15 are the VM contexts0-15 */
3859         /* invalidate the cache */
3860         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3861         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3862                                  WRITE_DATA_DST_SEL(0)));
3863         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
3864         amdgpu_ring_write(ring, 0);
3865         amdgpu_ring_write(ring, 1 << vm_id);
3866
3867         /* wait for the invalidate to complete */
3868         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3869         amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */
3870                                  WAIT_REG_MEM_FUNCTION(0) |  /* always */
3871                                  WAIT_REG_MEM_ENGINE(0))); /* me */
3872         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
3873         amdgpu_ring_write(ring, 0);
3874         amdgpu_ring_write(ring, 0); /* ref */
3875         amdgpu_ring_write(ring, 0); /* mask */
3876         amdgpu_ring_write(ring, 0x20); /* poll interval */
3877
3878         /* compute doesn't have PFP */
3879         if (usepfp) {
3880                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
3881                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
3882                 amdgpu_ring_write(ring, 0x0);
3883
3884                 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
3885                 gfx_v8_0_ce_sync_me(ring);
3886         }
3887 }
3888
3889 static bool gfx_v8_0_ring_is_lockup(struct amdgpu_ring *ring)
3890 {
3891         if (gfx_v8_0_is_idle(ring->adev)) {
3892                 amdgpu_ring_lockup_update(ring);
3893                 return false;
3894         }
3895         return amdgpu_ring_test_lockup(ring);
3896 }
3897
3898 static u32 gfx_v8_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
3899 {
3900         return ring->adev->wb.wb[ring->rptr_offs];
3901 }
3902
3903 static u32 gfx_v8_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
3904 {
3905         return ring->adev->wb.wb[ring->wptr_offs];
3906 }
3907
3908 static void gfx_v8_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
3909 {
3910         struct amdgpu_device *adev = ring->adev;
3911
3912         /* XXX check if swapping is necessary on BE */
3913         adev->wb.wb[ring->wptr_offs] = ring->wptr;
3914         WDOORBELL32(ring->doorbell_index, ring->wptr);
3915 }
3916
3917 static void gfx_v8_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
3918                                              u64 addr, u64 seq,
3919                                              unsigned flags)
3920 {
3921         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
3922         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
3923
3924         /* RELEASE_MEM - flush caches, send int */
3925         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));
3926         amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
3927                                  EOP_TC_ACTION_EN |
3928                                  EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
3929                                  EVENT_INDEX(5)));
3930         amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
3931         amdgpu_ring_write(ring, addr & 0xfffffffc);
3932         amdgpu_ring_write(ring, upper_32_bits(addr));
3933         amdgpu_ring_write(ring, lower_32_bits(seq));
3934         amdgpu_ring_write(ring, upper_32_bits(seq));
3935 }
3936
3937 static void gfx_v8_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
3938                                                  enum amdgpu_interrupt_state state)
3939 {
3940         u32 cp_int_cntl;
3941
3942         switch (state) {
3943         case AMDGPU_IRQ_STATE_DISABLE:
3944                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3945                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
3946                                             TIME_STAMP_INT_ENABLE, 0);
3947                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3948                 break;
3949         case AMDGPU_IRQ_STATE_ENABLE:
3950                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3951                 cp_int_cntl =
3952                         REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
3953                                       TIME_STAMP_INT_ENABLE, 1);
3954                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3955                 break;
3956         default:
3957                 break;
3958         }
3959 }
3960
3961 static void gfx_v8_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
3962                                                      int me, int pipe,
3963                                                      enum amdgpu_interrupt_state state)
3964 {
3965         u32 mec_int_cntl, mec_int_cntl_reg;
3966
3967         /*
3968          * amdgpu controls only pipe 0 of MEC1. That's why this function only
3969          * handles the setting of interrupts for this specific pipe. All other
3970          * pipes' interrupts are set by amdkfd.
3971          */
3972
3973         if (me == 1) {
3974                 switch (pipe) {
3975                 case 0:
3976                         mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL;
3977                         break;
3978                 default:
3979                         DRM_DEBUG("invalid pipe %d\n", pipe);
3980                         return;
3981                 }
3982         } else {
3983                 DRM_DEBUG("invalid me %d\n", me);
3984                 return;
3985         }
3986
3987         switch (state) {
3988         case AMDGPU_IRQ_STATE_DISABLE:
3989                 mec_int_cntl = RREG32(mec_int_cntl_reg);
3990                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
3991                                              TIME_STAMP_INT_ENABLE, 0);
3992                 WREG32(mec_int_cntl_reg, mec_int_cntl);
3993                 break;
3994         case AMDGPU_IRQ_STATE_ENABLE:
3995                 mec_int_cntl = RREG32(mec_int_cntl_reg);
3996                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
3997                                              TIME_STAMP_INT_ENABLE, 1);
3998                 WREG32(mec_int_cntl_reg, mec_int_cntl);
3999                 break;
4000         default:
4001                 break;
4002         }
4003 }
4004
4005 static int gfx_v8_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
4006                                              struct amdgpu_irq_src *source,
4007                                              unsigned type,
4008                                              enum amdgpu_interrupt_state state)
4009 {
4010         u32 cp_int_cntl;
4011
4012         switch (state) {
4013         case AMDGPU_IRQ_STATE_DISABLE:
4014                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4015                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4016                                             PRIV_REG_INT_ENABLE, 0);
4017                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4018                 break;
4019         case AMDGPU_IRQ_STATE_ENABLE:
4020                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4021                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4022                                             PRIV_REG_INT_ENABLE, 0);
4023                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4024                 break;
4025         default:
4026                 break;
4027         }
4028
4029         return 0;
4030 }
4031
4032 static int gfx_v8_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
4033                                               struct amdgpu_irq_src *source,
4034                                               unsigned type,
4035                                               enum amdgpu_interrupt_state state)
4036 {
4037         u32 cp_int_cntl;
4038
4039         switch (state) {
4040         case AMDGPU_IRQ_STATE_DISABLE:
4041                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4042                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4043                                             PRIV_INSTR_INT_ENABLE, 0);
4044                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4045                 break;
4046         case AMDGPU_IRQ_STATE_ENABLE:
4047                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4048                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4049                                             PRIV_INSTR_INT_ENABLE, 1);
4050                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4051                 break;
4052         default:
4053                 break;
4054         }
4055
4056         return 0;
4057 }
4058
4059 static int gfx_v8_0_set_eop_interrupt_state(struct amdgpu_device *adev,
4060                                             struct amdgpu_irq_src *src,
4061                                             unsigned type,
4062                                             enum amdgpu_interrupt_state state)
4063 {
4064         switch (type) {
4065         case AMDGPU_CP_IRQ_GFX_EOP:
4066                 gfx_v8_0_set_gfx_eop_interrupt_state(adev, state);
4067                 break;
4068         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
4069                 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
4070                 break;
4071         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
4072                 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
4073                 break;
4074         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
4075                 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
4076                 break;
4077         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
4078                 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
4079                 break;
4080         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
4081                 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
4082                 break;
4083         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
4084                 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
4085                 break;
4086         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
4087                 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
4088                 break;
4089         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
4090                 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
4091                 break;
4092         default:
4093                 break;
4094         }
4095         return 0;
4096 }
4097
4098 static int gfx_v8_0_eop_irq(struct amdgpu_device *adev,
4099                             struct amdgpu_irq_src *source,
4100                             struct amdgpu_iv_entry *entry)
4101 {
4102         int i;
4103         u8 me_id, pipe_id, queue_id;
4104         struct amdgpu_ring *ring;
4105
4106         DRM_DEBUG("IH: CP EOP\n");
4107         me_id = (entry->ring_id & 0x0c) >> 2;
4108         pipe_id = (entry->ring_id & 0x03) >> 0;
4109         queue_id = (entry->ring_id & 0x70) >> 4;
4110
4111         switch (me_id) {
4112         case 0:
4113                 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
4114                 break;
4115         case 1:
4116         case 2:
4117                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4118                         ring = &adev->gfx.compute_ring[i];
4119                         /* Per-queue interrupt is supported for MEC starting from VI.
4120                           * The interrupt can only be enabled/disabled per pipe instead of per queue.
4121                           */
4122                         if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
4123                                 amdgpu_fence_process(ring);
4124                 }
4125                 break;
4126         }
4127         return 0;
4128 }
4129
4130 static int gfx_v8_0_priv_reg_irq(struct amdgpu_device *adev,
4131                                  struct amdgpu_irq_src *source,
4132                                  struct amdgpu_iv_entry *entry)
4133 {
4134         DRM_ERROR("Illegal register access in command stream\n");
4135         schedule_work(&adev->reset_work);
4136         return 0;
4137 }
4138
4139 static int gfx_v8_0_priv_inst_irq(struct amdgpu_device *adev,
4140                                   struct amdgpu_irq_src *source,
4141                                   struct amdgpu_iv_entry *entry)
4142 {
4143         DRM_ERROR("Illegal instruction in command stream\n");
4144         schedule_work(&adev->reset_work);
4145         return 0;
4146 }
4147
4148 const struct amd_ip_funcs gfx_v8_0_ip_funcs = {
4149         .early_init = gfx_v8_0_early_init,
4150         .late_init = NULL,
4151         .sw_init = gfx_v8_0_sw_init,
4152         .sw_fini = gfx_v8_0_sw_fini,
4153         .hw_init = gfx_v8_0_hw_init,
4154         .hw_fini = gfx_v8_0_hw_fini,
4155         .suspend = gfx_v8_0_suspend,
4156         .resume = gfx_v8_0_resume,
4157         .is_idle = gfx_v8_0_is_idle,
4158         .wait_for_idle = gfx_v8_0_wait_for_idle,
4159         .soft_reset = gfx_v8_0_soft_reset,
4160         .print_status = gfx_v8_0_print_status,
4161         .set_clockgating_state = gfx_v8_0_set_clockgating_state,
4162         .set_powergating_state = gfx_v8_0_set_powergating_state,
4163 };
4164
4165 static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = {
4166         .get_rptr = gfx_v8_0_ring_get_rptr_gfx,
4167         .get_wptr = gfx_v8_0_ring_get_wptr_gfx,
4168         .set_wptr = gfx_v8_0_ring_set_wptr_gfx,
4169         .parse_cs = NULL,
4170         .emit_ib = gfx_v8_0_ring_emit_ib,
4171         .emit_fence = gfx_v8_0_ring_emit_fence_gfx,
4172         .emit_semaphore = gfx_v8_0_ring_emit_semaphore,
4173         .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
4174         .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
4175         .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
4176         .test_ring = gfx_v8_0_ring_test_ring,
4177         .test_ib = gfx_v8_0_ring_test_ib,
4178         .is_lockup = gfx_v8_0_ring_is_lockup,
4179 };
4180
4181 static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = {
4182         .get_rptr = gfx_v8_0_ring_get_rptr_compute,
4183         .get_wptr = gfx_v8_0_ring_get_wptr_compute,
4184         .set_wptr = gfx_v8_0_ring_set_wptr_compute,
4185         .parse_cs = NULL,
4186         .emit_ib = gfx_v8_0_ring_emit_ib,
4187         .emit_fence = gfx_v8_0_ring_emit_fence_compute,
4188         .emit_semaphore = gfx_v8_0_ring_emit_semaphore,
4189         .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
4190         .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
4191         .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
4192         .test_ring = gfx_v8_0_ring_test_ring,
4193         .test_ib = gfx_v8_0_ring_test_ib,
4194         .is_lockup = gfx_v8_0_ring_is_lockup,
4195 };
4196
4197 static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev)
4198 {
4199         int i;
4200
4201         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4202                 adev->gfx.gfx_ring[i].funcs = &gfx_v8_0_ring_funcs_gfx;
4203
4204         for (i = 0; i < adev->gfx.num_compute_rings; i++)
4205                 adev->gfx.compute_ring[i].funcs = &gfx_v8_0_ring_funcs_compute;
4206 }
4207
4208 static const struct amdgpu_irq_src_funcs gfx_v8_0_eop_irq_funcs = {
4209         .set = gfx_v8_0_set_eop_interrupt_state,
4210         .process = gfx_v8_0_eop_irq,
4211 };
4212
4213 static const struct amdgpu_irq_src_funcs gfx_v8_0_priv_reg_irq_funcs = {
4214         .set = gfx_v8_0_set_priv_reg_fault_state,
4215         .process = gfx_v8_0_priv_reg_irq,
4216 };
4217
4218 static const struct amdgpu_irq_src_funcs gfx_v8_0_priv_inst_irq_funcs = {
4219         .set = gfx_v8_0_set_priv_inst_fault_state,
4220         .process = gfx_v8_0_priv_inst_irq,
4221 };
4222
4223 static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev)
4224 {
4225         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
4226         adev->gfx.eop_irq.funcs = &gfx_v8_0_eop_irq_funcs;
4227
4228         adev->gfx.priv_reg_irq.num_types = 1;
4229         adev->gfx.priv_reg_irq.funcs = &gfx_v8_0_priv_reg_irq_funcs;
4230
4231         adev->gfx.priv_inst_irq.num_types = 1;
4232         adev->gfx.priv_inst_irq.funcs = &gfx_v8_0_priv_inst_irq_funcs;
4233 }
4234
4235 static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev)
4236 {
4237         /* init asci gds info */
4238         adev->gds.mem.total_size = RREG32(mmGDS_VMID0_SIZE);
4239         adev->gds.gws.total_size = 64;
4240         adev->gds.oa.total_size = 16;
4241
4242         if (adev->gds.mem.total_size == 64 * 1024) {
4243                 adev->gds.mem.gfx_partition_size = 4096;
4244                 adev->gds.mem.cs_partition_size = 4096;
4245
4246                 adev->gds.gws.gfx_partition_size = 4;
4247                 adev->gds.gws.cs_partition_size = 4;
4248
4249                 adev->gds.oa.gfx_partition_size = 4;
4250                 adev->gds.oa.cs_partition_size = 1;
4251         } else {
4252                 adev->gds.mem.gfx_partition_size = 1024;
4253                 adev->gds.mem.cs_partition_size = 1024;
4254
4255                 adev->gds.gws.gfx_partition_size = 16;
4256                 adev->gds.gws.cs_partition_size = 16;
4257
4258                 adev->gds.oa.gfx_partition_size = 4;
4259                 adev->gds.oa.cs_partition_size = 4;
4260         }
4261 }
4262
4263 static u32 gfx_v8_0_get_cu_active_bitmap(struct amdgpu_device *adev,
4264                 u32 se, u32 sh)
4265 {
4266         u32 mask = 0, tmp, tmp1;
4267         int i;
4268
4269         gfx_v8_0_select_se_sh(adev, se, sh);
4270         tmp = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG);
4271         tmp1 = RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
4272         gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
4273
4274         tmp &= 0xffff0000;
4275
4276         tmp |= tmp1;
4277         tmp >>= 16;
4278
4279         for (i = 0; i < adev->gfx.config.max_cu_per_sh; i ++) {
4280                 mask <<= 1;
4281                 mask |= 1;
4282         }
4283
4284         return (~tmp) & mask;
4285 }
4286
4287 int gfx_v8_0_get_cu_info(struct amdgpu_device *adev,
4288                                                  struct amdgpu_cu_info *cu_info)
4289 {
4290         int i, j, k, counter, active_cu_number = 0;
4291         u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
4292
4293         if (!adev || !cu_info)
4294                 return -EINVAL;
4295
4296         mutex_lock(&adev->grbm_idx_mutex);
4297         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4298                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4299                         mask = 1;
4300                         ao_bitmap = 0;
4301                         counter = 0;
4302                         bitmap = gfx_v8_0_get_cu_active_bitmap(adev, i, j);
4303                         cu_info->bitmap[i][j] = bitmap;
4304
4305                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
4306                                 if (bitmap & mask) {
4307                                         if (counter < 2)
4308                                                 ao_bitmap |= mask;
4309                                         counter ++;
4310                                 }
4311                                 mask <<= 1;
4312                         }
4313                         active_cu_number += counter;
4314                         ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
4315                 }
4316         }
4317
4318         cu_info->number = active_cu_number;
4319         cu_info->ao_cu_mask = ao_cu_mask;
4320         mutex_unlock(&adev->grbm_idx_mutex);
4321         return 0;
4322 }