2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/delay.h>
25 #include <linux/kernel.h>
26 #include <linux/firmware.h>
27 #include <linux/module.h>
28 #include <linux/pci.h>
31 #include "amdgpu_gfx.h"
33 #include "vi_structs.h"
35 #include "amdgpu_ucode.h"
36 #include "amdgpu_atombios.h"
37 #include "atombios_i2c.h"
38 #include "clearstate_vi.h"
40 #include "gmc/gmc_8_2_d.h"
41 #include "gmc/gmc_8_2_sh_mask.h"
43 #include "oss/oss_3_0_d.h"
44 #include "oss/oss_3_0_sh_mask.h"
46 #include "bif/bif_5_0_d.h"
47 #include "bif/bif_5_0_sh_mask.h"
48 #include "gca/gfx_8_0_d.h"
49 #include "gca/gfx_8_0_enum.h"
50 #include "gca/gfx_8_0_sh_mask.h"
52 #include "dce/dce_10_0_d.h"
53 #include "dce/dce_10_0_sh_mask.h"
55 #include "smu/smu_7_1_3_d.h"
57 #include "ivsrcid/ivsrcid_vislands30.h"
59 #define GFX8_NUM_GFX_RINGS 1
60 #define GFX8_MEC_HPD_SIZE 4096
62 #define TOPAZ_GB_ADDR_CONFIG_GOLDEN 0x22010001
63 #define CARRIZO_GB_ADDR_CONFIG_GOLDEN 0x22010001
64 #define POLARIS11_GB_ADDR_CONFIG_GOLDEN 0x22011002
65 #define TONGA_GB_ADDR_CONFIG_GOLDEN 0x22011003
67 #define ARRAY_MODE(x) ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT)
68 #define PIPE_CONFIG(x) ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT)
69 #define TILE_SPLIT(x) ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT)
70 #define MICRO_TILE_MODE_NEW(x) ((x) << GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT)
71 #define SAMPLE_SPLIT(x) ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT)
72 #define BANK_WIDTH(x) ((x) << GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT)
73 #define BANK_HEIGHT(x) ((x) << GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT)
74 #define MACRO_TILE_ASPECT(x) ((x) << GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT)
75 #define NUM_BANKS(x) ((x) << GB_MACROTILE_MODE0__NUM_BANKS__SHIFT)
77 #define RLC_CGTT_MGCG_OVERRIDE__CPF_MASK 0x00000001L
78 #define RLC_CGTT_MGCG_OVERRIDE__RLC_MASK 0x00000002L
79 #define RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK 0x00000004L
80 #define RLC_CGTT_MGCG_OVERRIDE__CGCG_MASK 0x00000008L
81 #define RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK 0x00000010L
82 #define RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK 0x00000020L
85 #define SET_BPM_SERDES_CMD 1
86 #define CLE_BPM_SERDES_CMD 0
88 /* BPM Register Address*/
90 BPM_REG_CGLS_EN = 0, /* Enable/Disable CGLS */
91 BPM_REG_CGLS_ON, /* ON/OFF CGLS: shall be controlled by RLC FW */
92 BPM_REG_CGCG_OVERRIDE, /* Set/Clear CGCG Override */
93 BPM_REG_MGCG_OVERRIDE, /* Set/Clear MGCG Override */
94 BPM_REG_FGCG_OVERRIDE, /* Set/Clear FGCG Override */
98 #define RLC_FormatDirectRegListLength 14
100 MODULE_FIRMWARE("amdgpu/carrizo_ce.bin");
101 MODULE_FIRMWARE("amdgpu/carrizo_pfp.bin");
102 MODULE_FIRMWARE("amdgpu/carrizo_me.bin");
103 MODULE_FIRMWARE("amdgpu/carrizo_mec.bin");
104 MODULE_FIRMWARE("amdgpu/carrizo_mec2.bin");
105 MODULE_FIRMWARE("amdgpu/carrizo_rlc.bin");
107 MODULE_FIRMWARE("amdgpu/stoney_ce.bin");
108 MODULE_FIRMWARE("amdgpu/stoney_pfp.bin");
109 MODULE_FIRMWARE("amdgpu/stoney_me.bin");
110 MODULE_FIRMWARE("amdgpu/stoney_mec.bin");
111 MODULE_FIRMWARE("amdgpu/stoney_rlc.bin");
113 MODULE_FIRMWARE("amdgpu/tonga_ce.bin");
114 MODULE_FIRMWARE("amdgpu/tonga_pfp.bin");
115 MODULE_FIRMWARE("amdgpu/tonga_me.bin");
116 MODULE_FIRMWARE("amdgpu/tonga_mec.bin");
117 MODULE_FIRMWARE("amdgpu/tonga_mec2.bin");
118 MODULE_FIRMWARE("amdgpu/tonga_rlc.bin");
120 MODULE_FIRMWARE("amdgpu/topaz_ce.bin");
121 MODULE_FIRMWARE("amdgpu/topaz_pfp.bin");
122 MODULE_FIRMWARE("amdgpu/topaz_me.bin");
123 MODULE_FIRMWARE("amdgpu/topaz_mec.bin");
124 MODULE_FIRMWARE("amdgpu/topaz_rlc.bin");
126 MODULE_FIRMWARE("amdgpu/fiji_ce.bin");
127 MODULE_FIRMWARE("amdgpu/fiji_pfp.bin");
128 MODULE_FIRMWARE("amdgpu/fiji_me.bin");
129 MODULE_FIRMWARE("amdgpu/fiji_mec.bin");
130 MODULE_FIRMWARE("amdgpu/fiji_mec2.bin");
131 MODULE_FIRMWARE("amdgpu/fiji_rlc.bin");
133 MODULE_FIRMWARE("amdgpu/polaris10_ce.bin");
134 MODULE_FIRMWARE("amdgpu/polaris10_ce_2.bin");
135 MODULE_FIRMWARE("amdgpu/polaris10_pfp.bin");
136 MODULE_FIRMWARE("amdgpu/polaris10_pfp_2.bin");
137 MODULE_FIRMWARE("amdgpu/polaris10_me.bin");
138 MODULE_FIRMWARE("amdgpu/polaris10_me_2.bin");
139 MODULE_FIRMWARE("amdgpu/polaris10_mec.bin");
140 MODULE_FIRMWARE("amdgpu/polaris10_mec_2.bin");
141 MODULE_FIRMWARE("amdgpu/polaris10_mec2.bin");
142 MODULE_FIRMWARE("amdgpu/polaris10_mec2_2.bin");
143 MODULE_FIRMWARE("amdgpu/polaris10_rlc.bin");
145 MODULE_FIRMWARE("amdgpu/polaris11_ce.bin");
146 MODULE_FIRMWARE("amdgpu/polaris11_ce_2.bin");
147 MODULE_FIRMWARE("amdgpu/polaris11_pfp.bin");
148 MODULE_FIRMWARE("amdgpu/polaris11_pfp_2.bin");
149 MODULE_FIRMWARE("amdgpu/polaris11_me.bin");
150 MODULE_FIRMWARE("amdgpu/polaris11_me_2.bin");
151 MODULE_FIRMWARE("amdgpu/polaris11_mec.bin");
152 MODULE_FIRMWARE("amdgpu/polaris11_mec_2.bin");
153 MODULE_FIRMWARE("amdgpu/polaris11_mec2.bin");
154 MODULE_FIRMWARE("amdgpu/polaris11_mec2_2.bin");
155 MODULE_FIRMWARE("amdgpu/polaris11_rlc.bin");
157 MODULE_FIRMWARE("amdgpu/polaris12_ce.bin");
158 MODULE_FIRMWARE("amdgpu/polaris12_ce_2.bin");
159 MODULE_FIRMWARE("amdgpu/polaris12_pfp.bin");
160 MODULE_FIRMWARE("amdgpu/polaris12_pfp_2.bin");
161 MODULE_FIRMWARE("amdgpu/polaris12_me.bin");
162 MODULE_FIRMWARE("amdgpu/polaris12_me_2.bin");
163 MODULE_FIRMWARE("amdgpu/polaris12_mec.bin");
164 MODULE_FIRMWARE("amdgpu/polaris12_mec_2.bin");
165 MODULE_FIRMWARE("amdgpu/polaris12_mec2.bin");
166 MODULE_FIRMWARE("amdgpu/polaris12_mec2_2.bin");
167 MODULE_FIRMWARE("amdgpu/polaris12_rlc.bin");
169 MODULE_FIRMWARE("amdgpu/vegam_ce.bin");
170 MODULE_FIRMWARE("amdgpu/vegam_pfp.bin");
171 MODULE_FIRMWARE("amdgpu/vegam_me.bin");
172 MODULE_FIRMWARE("amdgpu/vegam_mec.bin");
173 MODULE_FIRMWARE("amdgpu/vegam_mec2.bin");
174 MODULE_FIRMWARE("amdgpu/vegam_rlc.bin");
176 static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
178 {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
179 {mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1},
180 {mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2},
181 {mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3},
182 {mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4},
183 {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5},
184 {mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6},
185 {mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7},
186 {mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8},
187 {mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9},
188 {mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10},
189 {mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11},
190 {mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12},
191 {mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13},
192 {mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14},
193 {mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15}
196 static const u32 golden_settings_tonga_a11[] =
198 mmCB_HW_CONTROL, 0xfffdf3cf, 0x00007208,
199 mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
200 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
201 mmGB_GPU_ID, 0x0000000f, 0x00000000,
202 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
203 mmPA_SC_FIFO_DEPTH_CNTL, 0x000003ff, 0x000000fc,
204 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
205 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c,
206 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
207 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
208 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
209 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
210 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000002fb,
211 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x0000543b,
212 mmTCP_CHAN_STEER_LO, 0xffffffff, 0xa9210876,
213 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
216 static const u32 tonga_golden_common_all[] =
218 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
219 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012,
220 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002A,
221 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
222 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
223 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
224 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
225 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF
228 static const u32 tonga_mgcg_cgcg_init[] =
230 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
231 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
232 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
233 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
234 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
235 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
236 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
237 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
238 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
239 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
240 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
241 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
242 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
243 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
244 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
245 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
246 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
247 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
248 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
249 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
250 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
251 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
252 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
253 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
254 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
255 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
256 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
257 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
258 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
259 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
260 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
261 mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
262 mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
263 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
264 mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
265 mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
266 mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
267 mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
268 mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
269 mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
270 mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
271 mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
272 mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
273 mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
274 mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
275 mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
276 mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
277 mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
278 mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
279 mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
280 mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
281 mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
282 mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
283 mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
284 mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
285 mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
286 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
287 mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
288 mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
289 mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
290 mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
291 mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
292 mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
293 mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
294 mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
295 mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
296 mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
297 mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
298 mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
299 mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
300 mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
301 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
302 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
303 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
304 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
307 static const u32 golden_settings_vegam_a11[] =
309 mmCB_HW_CONTROL, 0x0001f3cf, 0x00007208,
310 mmCB_HW_CONTROL_2, 0x0f000000, 0x0d000000,
311 mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
312 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
313 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
314 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
315 mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x3a00161a,
316 mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x0000002e,
317 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
318 mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c,
319 mmSQ_CONFIG, 0x07f80000, 0x01180000,
320 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
321 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
322 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f7,
323 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
324 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x32761054,
325 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
328 static const u32 vegam_golden_common_all[] =
330 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
331 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
332 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
333 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
334 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
335 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
338 static const u32 golden_settings_polaris11_a11[] =
340 mmCB_HW_CONTROL, 0x0000f3cf, 0x00007208,
341 mmCB_HW_CONTROL_2, 0x0f000000, 0x0f000000,
342 mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
343 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
344 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
345 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
346 mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x16000012,
347 mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000,
348 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
349 mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c,
350 mmSQ_CONFIG, 0x07f80000, 0x01180000,
351 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
352 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
353 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f3,
354 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
355 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003210,
356 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
359 static const u32 polaris11_golden_common_all[] =
361 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
362 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011002,
363 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
364 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
365 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
366 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
369 static const u32 golden_settings_polaris10_a11[] =
371 mmATC_MISC_CG, 0x000c0fc0, 0x000c0200,
372 mmCB_HW_CONTROL, 0x0001f3cf, 0x00007208,
373 mmCB_HW_CONTROL_2, 0x0f000000, 0x0f000000,
374 mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
375 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
376 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
377 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
378 mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x16000012,
379 mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x0000002a,
380 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
381 mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c,
382 mmSQ_CONFIG, 0x07f80000, 0x07180000,
383 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
384 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
385 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f7,
386 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
387 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
390 static const u32 polaris10_golden_common_all[] =
392 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
393 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012,
394 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002A,
395 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
396 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
397 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
398 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
399 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
402 static const u32 fiji_golden_common_all[] =
404 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
405 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x3a00161a,
406 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002e,
407 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
408 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
409 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
410 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
411 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
412 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
413 mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x00000009,
416 static const u32 golden_settings_fiji_a10[] =
418 mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
419 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
420 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
421 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
422 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
423 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
424 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
425 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
426 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
427 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000ff,
428 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
431 static const u32 fiji_mgcg_cgcg_init[] =
433 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
434 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
435 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
436 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
437 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
438 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
439 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
440 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
441 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
442 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
443 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
444 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
445 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
446 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
447 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
448 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
449 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
450 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
451 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
452 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
453 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
454 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
455 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
456 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
457 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
458 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
459 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
460 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
461 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
462 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
463 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
464 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
465 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
466 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
467 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
470 static const u32 golden_settings_iceland_a11[] =
472 mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
473 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
474 mmDB_DEBUG3, 0xc0000000, 0xc0000000,
475 mmGB_GPU_ID, 0x0000000f, 0x00000000,
476 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
477 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
478 mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x00000002,
479 mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000,
480 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c,
481 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
482 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
483 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
484 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
485 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f1,
486 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
487 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010,
490 static const u32 iceland_golden_common_all[] =
492 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
493 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
494 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
495 mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
496 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
497 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
498 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
499 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF
502 static const u32 iceland_mgcg_cgcg_init[] =
504 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
505 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
506 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
507 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
508 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0xc0000100,
509 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0xc0000100,
510 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0xc0000100,
511 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
512 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
513 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
514 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
515 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
516 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
517 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
518 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
519 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
520 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
521 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
522 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
523 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
524 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
525 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
526 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0xff000100,
527 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
528 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
529 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
530 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
531 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
532 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
533 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
534 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
535 mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
536 mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
537 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
538 mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
539 mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
540 mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
541 mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
542 mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
543 mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
544 mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
545 mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
546 mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
547 mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
548 mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
549 mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
550 mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
551 mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
552 mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
553 mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
554 mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
555 mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
556 mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
557 mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
558 mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
559 mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
560 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
561 mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
562 mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
563 mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
564 mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
565 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
566 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
567 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
570 static const u32 cz_golden_settings_a11[] =
572 mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
573 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
574 mmGB_GPU_ID, 0x0000000f, 0x00000000,
575 mmPA_SC_ENHANCE, 0xffffffff, 0x00000001,
576 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
577 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c,
578 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
579 mmTA_CNTL_AUX, 0x000f000f, 0x00010000,
580 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
581 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
582 mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f3,
583 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00001302
586 static const u32 cz_golden_common_all[] =
588 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
589 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
590 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
591 mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
592 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
593 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
594 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
595 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF
598 static const u32 cz_mgcg_cgcg_init[] =
600 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
601 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
602 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
603 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
604 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
605 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
606 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x00000100,
607 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
608 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
609 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
610 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
611 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
612 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
613 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
614 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
615 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
616 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
617 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
618 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
619 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
620 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
621 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
622 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
623 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
624 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
625 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
626 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
627 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
628 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
629 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
630 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
631 mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
632 mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
633 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
634 mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
635 mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
636 mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
637 mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
638 mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
639 mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
640 mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
641 mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
642 mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
643 mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
644 mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
645 mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
646 mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
647 mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
648 mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
649 mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
650 mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
651 mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
652 mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
653 mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
654 mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
655 mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
656 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
657 mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
658 mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
659 mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
660 mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
661 mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
662 mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
663 mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
664 mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
665 mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
666 mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
667 mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
668 mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
669 mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
670 mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
671 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
672 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
673 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
674 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
677 static const u32 stoney_golden_settings_a11[] =
679 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
680 mmGB_GPU_ID, 0x0000000f, 0x00000000,
681 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
682 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
683 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
684 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
685 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
686 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
687 mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f1,
688 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x10101010,
691 static const u32 stoney_golden_common_all[] =
693 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
694 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000000,
695 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
696 mmGB_ADDR_CONFIG, 0xffffffff, 0x12010001,
697 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
698 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
699 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00FF7FBF,
700 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00FF7FAF,
703 static const u32 stoney_mgcg_cgcg_init[] =
705 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
706 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
707 mmCP_MEM_SLP_CNTL, 0xffffffff, 0x00020201,
708 mmRLC_MEM_SLP_CNTL, 0xffffffff, 0x00020201,
709 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200,
713 static const char * const sq_edc_source_names[] = {
714 "SQ_EDC_INFO_SOURCE_INVALID: No EDC error has occurred",
715 "SQ_EDC_INFO_SOURCE_INST: EDC source is Instruction Fetch",
716 "SQ_EDC_INFO_SOURCE_SGPR: EDC source is SGPR or SQC data return",
717 "SQ_EDC_INFO_SOURCE_VGPR: EDC source is VGPR",
718 "SQ_EDC_INFO_SOURCE_LDS: EDC source is LDS",
719 "SQ_EDC_INFO_SOURCE_GDS: EDC source is GDS",
720 "SQ_EDC_INFO_SOURCE_TA: EDC source is TA",
723 static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev);
724 static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev);
725 static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev);
726 static void gfx_v8_0_set_rlc_funcs(struct amdgpu_device *adev);
727 static u32 gfx_v8_0_get_csb_size(struct amdgpu_device *adev);
728 static void gfx_v8_0_get_cu_info(struct amdgpu_device *adev);
729 static void gfx_v8_0_ring_emit_ce_meta(struct amdgpu_ring *ring);
730 static void gfx_v8_0_ring_emit_de_meta(struct amdgpu_ring *ring);
732 static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev)
734 switch (adev->asic_type) {
736 amdgpu_device_program_register_sequence(adev,
737 iceland_mgcg_cgcg_init,
738 ARRAY_SIZE(iceland_mgcg_cgcg_init));
739 amdgpu_device_program_register_sequence(adev,
740 golden_settings_iceland_a11,
741 ARRAY_SIZE(golden_settings_iceland_a11));
742 amdgpu_device_program_register_sequence(adev,
743 iceland_golden_common_all,
744 ARRAY_SIZE(iceland_golden_common_all));
747 amdgpu_device_program_register_sequence(adev,
749 ARRAY_SIZE(fiji_mgcg_cgcg_init));
750 amdgpu_device_program_register_sequence(adev,
751 golden_settings_fiji_a10,
752 ARRAY_SIZE(golden_settings_fiji_a10));
753 amdgpu_device_program_register_sequence(adev,
754 fiji_golden_common_all,
755 ARRAY_SIZE(fiji_golden_common_all));
759 amdgpu_device_program_register_sequence(adev,
760 tonga_mgcg_cgcg_init,
761 ARRAY_SIZE(tonga_mgcg_cgcg_init));
762 amdgpu_device_program_register_sequence(adev,
763 golden_settings_tonga_a11,
764 ARRAY_SIZE(golden_settings_tonga_a11));
765 amdgpu_device_program_register_sequence(adev,
766 tonga_golden_common_all,
767 ARRAY_SIZE(tonga_golden_common_all));
770 amdgpu_device_program_register_sequence(adev,
771 golden_settings_vegam_a11,
772 ARRAY_SIZE(golden_settings_vegam_a11));
773 amdgpu_device_program_register_sequence(adev,
774 vegam_golden_common_all,
775 ARRAY_SIZE(vegam_golden_common_all));
779 amdgpu_device_program_register_sequence(adev,
780 golden_settings_polaris11_a11,
781 ARRAY_SIZE(golden_settings_polaris11_a11));
782 amdgpu_device_program_register_sequence(adev,
783 polaris11_golden_common_all,
784 ARRAY_SIZE(polaris11_golden_common_all));
787 amdgpu_device_program_register_sequence(adev,
788 golden_settings_polaris10_a11,
789 ARRAY_SIZE(golden_settings_polaris10_a11));
790 amdgpu_device_program_register_sequence(adev,
791 polaris10_golden_common_all,
792 ARRAY_SIZE(polaris10_golden_common_all));
793 WREG32_SMC(ixCG_ACLK_CNTL, 0x0000001C);
794 if (adev->pdev->revision == 0xc7 &&
795 ((adev->pdev->subsystem_device == 0xb37 && adev->pdev->subsystem_vendor == 0x1002) ||
796 (adev->pdev->subsystem_device == 0x4a8 && adev->pdev->subsystem_vendor == 0x1043) ||
797 (adev->pdev->subsystem_device == 0x9480 && adev->pdev->subsystem_vendor == 0x1682))) {
798 amdgpu_atombios_i2c_channel_trans(adev, 0x10, 0x96, 0x1E, 0xDD);
799 amdgpu_atombios_i2c_channel_trans(adev, 0x10, 0x96, 0x1F, 0xD0);
803 amdgpu_device_program_register_sequence(adev,
805 ARRAY_SIZE(cz_mgcg_cgcg_init));
806 amdgpu_device_program_register_sequence(adev,
807 cz_golden_settings_a11,
808 ARRAY_SIZE(cz_golden_settings_a11));
809 amdgpu_device_program_register_sequence(adev,
810 cz_golden_common_all,
811 ARRAY_SIZE(cz_golden_common_all));
814 amdgpu_device_program_register_sequence(adev,
815 stoney_mgcg_cgcg_init,
816 ARRAY_SIZE(stoney_mgcg_cgcg_init));
817 amdgpu_device_program_register_sequence(adev,
818 stoney_golden_settings_a11,
819 ARRAY_SIZE(stoney_golden_settings_a11));
820 amdgpu_device_program_register_sequence(adev,
821 stoney_golden_common_all,
822 ARRAY_SIZE(stoney_golden_common_all));
829 static void gfx_v8_0_scratch_init(struct amdgpu_device *adev)
831 adev->gfx.scratch.num_reg = 8;
832 adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
833 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
836 static int gfx_v8_0_ring_test_ring(struct amdgpu_ring *ring)
838 struct amdgpu_device *adev = ring->adev;
844 r = amdgpu_gfx_scratch_get(adev, &scratch);
848 WREG32(scratch, 0xCAFEDEAD);
849 r = amdgpu_ring_alloc(ring, 3);
851 goto error_free_scratch;
853 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
854 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
855 amdgpu_ring_write(ring, 0xDEADBEEF);
856 amdgpu_ring_commit(ring);
858 for (i = 0; i < adev->usec_timeout; i++) {
859 tmp = RREG32(scratch);
860 if (tmp == 0xDEADBEEF)
865 if (i >= adev->usec_timeout)
869 amdgpu_gfx_scratch_free(adev, scratch);
873 static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
875 struct amdgpu_device *adev = ring->adev;
877 struct dma_fence *f = NULL;
884 r = amdgpu_device_wb_get(adev, &index);
888 gpu_addr = adev->wb.gpu_addr + (index * 4);
889 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
890 memset(&ib, 0, sizeof(ib));
891 r = amdgpu_ib_get(adev, NULL, 16, &ib);
895 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
896 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
897 ib.ptr[2] = lower_32_bits(gpu_addr);
898 ib.ptr[3] = upper_32_bits(gpu_addr);
899 ib.ptr[4] = 0xDEADBEEF;
902 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
906 r = dma_fence_wait_timeout(f, false, timeout);
914 tmp = adev->wb.wb[index];
915 if (tmp == 0xDEADBEEF)
921 amdgpu_ib_free(adev, &ib, NULL);
924 amdgpu_device_wb_free(adev, index);
929 static void gfx_v8_0_free_microcode(struct amdgpu_device *adev)
931 release_firmware(adev->gfx.pfp_fw);
932 adev->gfx.pfp_fw = NULL;
933 release_firmware(adev->gfx.me_fw);
934 adev->gfx.me_fw = NULL;
935 release_firmware(adev->gfx.ce_fw);
936 adev->gfx.ce_fw = NULL;
937 release_firmware(adev->gfx.rlc_fw);
938 adev->gfx.rlc_fw = NULL;
939 release_firmware(adev->gfx.mec_fw);
940 adev->gfx.mec_fw = NULL;
941 if ((adev->asic_type != CHIP_STONEY) &&
942 (adev->asic_type != CHIP_TOPAZ))
943 release_firmware(adev->gfx.mec2_fw);
944 adev->gfx.mec2_fw = NULL;
946 kfree(adev->gfx.rlc.register_list_format);
949 static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
951 const char *chip_name;
954 struct amdgpu_firmware_info *info = NULL;
955 const struct common_firmware_header *header = NULL;
956 const struct gfx_firmware_header_v1_0 *cp_hdr;
957 const struct rlc_firmware_header_v2_0 *rlc_hdr;
958 unsigned int *tmp = NULL, i;
962 switch (adev->asic_type) {
970 chip_name = "carrizo";
976 chip_name = "stoney";
979 chip_name = "polaris10";
982 chip_name = "polaris11";
985 chip_name = "polaris12";
994 if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
995 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp_2.bin", chip_name);
996 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
997 if (err == -ENOENT) {
998 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
999 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
1002 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
1003 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
1007 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
1010 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
1011 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
1012 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
1014 if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
1015 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me_2.bin", chip_name);
1016 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
1017 if (err == -ENOENT) {
1018 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
1019 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
1022 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
1023 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
1027 err = amdgpu_ucode_validate(adev->gfx.me_fw);
1030 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
1031 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
1033 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
1035 if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
1036 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce_2.bin", chip_name);
1037 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
1038 if (err == -ENOENT) {
1039 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
1040 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
1043 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
1044 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
1048 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
1051 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
1052 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
1053 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
1056 * Support for MCBP/Virtualization in combination with chained IBs is
1057 * formal released on feature version #46
1059 if (adev->gfx.ce_feature_version >= 46 &&
1060 adev->gfx.pfp_feature_version >= 46) {
1061 adev->virt.chained_ib_support = true;
1062 DRM_INFO("Chained IB support enabled!\n");
1064 adev->virt.chained_ib_support = false;
1066 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
1067 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
1070 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
1071 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
1072 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
1073 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
1075 adev->gfx.rlc.save_and_restore_offset =
1076 le32_to_cpu(rlc_hdr->save_and_restore_offset);
1077 adev->gfx.rlc.clear_state_descriptor_offset =
1078 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
1079 adev->gfx.rlc.avail_scratch_ram_locations =
1080 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
1081 adev->gfx.rlc.reg_restore_list_size =
1082 le32_to_cpu(rlc_hdr->reg_restore_list_size);
1083 adev->gfx.rlc.reg_list_format_start =
1084 le32_to_cpu(rlc_hdr->reg_list_format_start);
1085 adev->gfx.rlc.reg_list_format_separate_start =
1086 le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
1087 adev->gfx.rlc.starting_offsets_start =
1088 le32_to_cpu(rlc_hdr->starting_offsets_start);
1089 adev->gfx.rlc.reg_list_format_size_bytes =
1090 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
1091 adev->gfx.rlc.reg_list_size_bytes =
1092 le32_to_cpu(rlc_hdr->reg_list_size_bytes);
1094 adev->gfx.rlc.register_list_format =
1095 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
1096 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
1098 if (!adev->gfx.rlc.register_list_format) {
1103 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
1104 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
1105 for (i = 0 ; i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2); i++)
1106 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
1108 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
1110 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
1111 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
1112 for (i = 0 ; i < (adev->gfx.rlc.reg_list_size_bytes >> 2); i++)
1113 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
1115 if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
1116 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec_2.bin", chip_name);
1117 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
1118 if (err == -ENOENT) {
1119 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
1120 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
1123 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
1124 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
1128 err = amdgpu_ucode_validate(adev->gfx.mec_fw);
1131 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
1132 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
1133 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
1135 if ((adev->asic_type != CHIP_STONEY) &&
1136 (adev->asic_type != CHIP_TOPAZ)) {
1137 if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
1138 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2_2.bin", chip_name);
1139 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
1140 if (err == -ENOENT) {
1141 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
1142 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
1145 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
1146 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
1149 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
1152 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1153 adev->gfx.mec2_fw->data;
1154 adev->gfx.mec2_fw_version =
1155 le32_to_cpu(cp_hdr->header.ucode_version);
1156 adev->gfx.mec2_feature_version =
1157 le32_to_cpu(cp_hdr->ucode_feature_version);
1160 adev->gfx.mec2_fw = NULL;
1164 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
1165 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
1166 info->fw = adev->gfx.pfp_fw;
1167 header = (const struct common_firmware_header *)info->fw->data;
1168 adev->firmware.fw_size +=
1169 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1171 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
1172 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
1173 info->fw = adev->gfx.me_fw;
1174 header = (const struct common_firmware_header *)info->fw->data;
1175 adev->firmware.fw_size +=
1176 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1178 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
1179 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
1180 info->fw = adev->gfx.ce_fw;
1181 header = (const struct common_firmware_header *)info->fw->data;
1182 adev->firmware.fw_size +=
1183 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1185 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
1186 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
1187 info->fw = adev->gfx.rlc_fw;
1188 header = (const struct common_firmware_header *)info->fw->data;
1189 adev->firmware.fw_size +=
1190 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1192 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
1193 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
1194 info->fw = adev->gfx.mec_fw;
1195 header = (const struct common_firmware_header *)info->fw->data;
1196 adev->firmware.fw_size +=
1197 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1199 /* we need account JT in */
1200 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
1201 adev->firmware.fw_size +=
1202 ALIGN(le32_to_cpu(cp_hdr->jt_size) << 2, PAGE_SIZE);
1204 if (amdgpu_sriov_vf(adev)) {
1205 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_STORAGE];
1206 info->ucode_id = AMDGPU_UCODE_ID_STORAGE;
1207 info->fw = adev->gfx.mec_fw;
1208 adev->firmware.fw_size +=
1209 ALIGN(le32_to_cpu(64 * PAGE_SIZE), PAGE_SIZE);
1212 if (adev->gfx.mec2_fw) {
1213 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
1214 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
1215 info->fw = adev->gfx.mec2_fw;
1216 header = (const struct common_firmware_header *)info->fw->data;
1217 adev->firmware.fw_size +=
1218 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
1224 "gfx8: Failed to load firmware \"%s\"\n",
1226 release_firmware(adev->gfx.pfp_fw);
1227 adev->gfx.pfp_fw = NULL;
1228 release_firmware(adev->gfx.me_fw);
1229 adev->gfx.me_fw = NULL;
1230 release_firmware(adev->gfx.ce_fw);
1231 adev->gfx.ce_fw = NULL;
1232 release_firmware(adev->gfx.rlc_fw);
1233 adev->gfx.rlc_fw = NULL;
1234 release_firmware(adev->gfx.mec_fw);
1235 adev->gfx.mec_fw = NULL;
1236 release_firmware(adev->gfx.mec2_fw);
1237 adev->gfx.mec2_fw = NULL;
1242 static void gfx_v8_0_get_csb_buffer(struct amdgpu_device *adev,
1243 volatile u32 *buffer)
1246 const struct cs_section_def *sect = NULL;
1247 const struct cs_extent_def *ext = NULL;
1249 if (adev->gfx.rlc.cs_data == NULL)
1254 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1255 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1257 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
1258 buffer[count++] = cpu_to_le32(0x80000000);
1259 buffer[count++] = cpu_to_le32(0x80000000);
1261 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
1262 for (ext = sect->section; ext->extent != NULL; ++ext) {
1263 if (sect->id == SECT_CONTEXT) {
1265 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
1266 buffer[count++] = cpu_to_le32(ext->reg_index -
1267 PACKET3_SET_CONTEXT_REG_START);
1268 for (i = 0; i < ext->reg_count; i++)
1269 buffer[count++] = cpu_to_le32(ext->extent[i]);
1276 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2));
1277 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG -
1278 PACKET3_SET_CONTEXT_REG_START);
1279 buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config);
1280 buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config_1);
1282 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1283 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
1285 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
1286 buffer[count++] = cpu_to_le32(0);
1289 static int gfx_v8_0_cp_jump_table_num(struct amdgpu_device *adev)
1291 if (adev->asic_type == CHIP_CARRIZO)
1297 static int gfx_v8_0_rlc_init(struct amdgpu_device *adev)
1299 const struct cs_section_def *cs_data;
1302 adev->gfx.rlc.cs_data = vi_cs_data;
1304 cs_data = adev->gfx.rlc.cs_data;
1307 /* init clear state block */
1308 r = amdgpu_gfx_rlc_init_csb(adev);
1313 if ((adev->asic_type == CHIP_CARRIZO) ||
1314 (adev->asic_type == CHIP_STONEY)) {
1315 adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */
1316 r = amdgpu_gfx_rlc_init_cpt(adev);
1324 static int gfx_v8_0_csb_vram_pin(struct amdgpu_device *adev)
1328 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
1329 if (unlikely(r != 0))
1332 r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj,
1333 AMDGPU_GEM_DOMAIN_VRAM);
1335 adev->gfx.rlc.clear_state_gpu_addr =
1336 amdgpu_bo_gpu_offset(adev->gfx.rlc.clear_state_obj);
1338 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
1343 static void gfx_v8_0_csb_vram_unpin(struct amdgpu_device *adev)
1347 if (!adev->gfx.rlc.clear_state_obj)
1350 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, true);
1351 if (likely(r == 0)) {
1352 amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
1353 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
1357 static void gfx_v8_0_mec_fini(struct amdgpu_device *adev)
1359 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
1362 static int gfx_v8_0_mec_init(struct amdgpu_device *adev)
1366 size_t mec_hpd_size;
1368 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
1370 /* take ownership of the relevant compute queues */
1371 amdgpu_gfx_compute_queue_acquire(adev);
1373 mec_hpd_size = adev->gfx.num_compute_rings * GFX8_MEC_HPD_SIZE;
1375 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
1376 AMDGPU_GEM_DOMAIN_VRAM,
1377 &adev->gfx.mec.hpd_eop_obj,
1378 &adev->gfx.mec.hpd_eop_gpu_addr,
1381 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
1385 memset(hpd, 0, mec_hpd_size);
1387 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
1388 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
1393 static const u32 vgpr_init_compute_shader[] =
1395 0x7e000209, 0x7e020208,
1396 0x7e040207, 0x7e060206,
1397 0x7e080205, 0x7e0a0204,
1398 0x7e0c0203, 0x7e0e0202,
1399 0x7e100201, 0x7e120200,
1400 0x7e140209, 0x7e160208,
1401 0x7e180207, 0x7e1a0206,
1402 0x7e1c0205, 0x7e1e0204,
1403 0x7e200203, 0x7e220202,
1404 0x7e240201, 0x7e260200,
1405 0x7e280209, 0x7e2a0208,
1406 0x7e2c0207, 0x7e2e0206,
1407 0x7e300205, 0x7e320204,
1408 0x7e340203, 0x7e360202,
1409 0x7e380201, 0x7e3a0200,
1410 0x7e3c0209, 0x7e3e0208,
1411 0x7e400207, 0x7e420206,
1412 0x7e440205, 0x7e460204,
1413 0x7e480203, 0x7e4a0202,
1414 0x7e4c0201, 0x7e4e0200,
1415 0x7e500209, 0x7e520208,
1416 0x7e540207, 0x7e560206,
1417 0x7e580205, 0x7e5a0204,
1418 0x7e5c0203, 0x7e5e0202,
1419 0x7e600201, 0x7e620200,
1420 0x7e640209, 0x7e660208,
1421 0x7e680207, 0x7e6a0206,
1422 0x7e6c0205, 0x7e6e0204,
1423 0x7e700203, 0x7e720202,
1424 0x7e740201, 0x7e760200,
1425 0x7e780209, 0x7e7a0208,
1426 0x7e7c0207, 0x7e7e0206,
1427 0xbf8a0000, 0xbf810000,
1430 static const u32 sgpr_init_compute_shader[] =
1432 0xbe8a0100, 0xbe8c0102,
1433 0xbe8e0104, 0xbe900106,
1434 0xbe920108, 0xbe940100,
1435 0xbe960102, 0xbe980104,
1436 0xbe9a0106, 0xbe9c0108,
1437 0xbe9e0100, 0xbea00102,
1438 0xbea20104, 0xbea40106,
1439 0xbea60108, 0xbea80100,
1440 0xbeaa0102, 0xbeac0104,
1441 0xbeae0106, 0xbeb00108,
1442 0xbeb20100, 0xbeb40102,
1443 0xbeb60104, 0xbeb80106,
1444 0xbeba0108, 0xbebc0100,
1445 0xbebe0102, 0xbec00104,
1446 0xbec20106, 0xbec40108,
1447 0xbec60100, 0xbec80102,
1448 0xbee60004, 0xbee70005,
1449 0xbeea0006, 0xbeeb0007,
1450 0xbee80008, 0xbee90009,
1451 0xbefc0000, 0xbf8a0000,
1452 0xbf810000, 0x00000000,
1455 static const u32 vgpr_init_regs[] =
1457 mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0xffffffff,
1458 mmCOMPUTE_RESOURCE_LIMITS, 0x1000000, /* CU_GROUP_COUNT=1 */
1459 mmCOMPUTE_NUM_THREAD_X, 256*4,
1460 mmCOMPUTE_NUM_THREAD_Y, 1,
1461 mmCOMPUTE_NUM_THREAD_Z, 1,
1462 mmCOMPUTE_PGM_RSRC1, 0x100004f, /* VGPRS=15 (64 logical VGPRs), SGPRS=1 (16 SGPRs), BULKY=1 */
1463 mmCOMPUTE_PGM_RSRC2, 20,
1464 mmCOMPUTE_USER_DATA_0, 0xedcedc00,
1465 mmCOMPUTE_USER_DATA_1, 0xedcedc01,
1466 mmCOMPUTE_USER_DATA_2, 0xedcedc02,
1467 mmCOMPUTE_USER_DATA_3, 0xedcedc03,
1468 mmCOMPUTE_USER_DATA_4, 0xedcedc04,
1469 mmCOMPUTE_USER_DATA_5, 0xedcedc05,
1470 mmCOMPUTE_USER_DATA_6, 0xedcedc06,
1471 mmCOMPUTE_USER_DATA_7, 0xedcedc07,
1472 mmCOMPUTE_USER_DATA_8, 0xedcedc08,
1473 mmCOMPUTE_USER_DATA_9, 0xedcedc09,
1476 static const u32 sgpr1_init_regs[] =
1478 mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0x0f,
1479 mmCOMPUTE_RESOURCE_LIMITS, 0x1000000, /* CU_GROUP_COUNT=1 */
1480 mmCOMPUTE_NUM_THREAD_X, 256*5,
1481 mmCOMPUTE_NUM_THREAD_Y, 1,
1482 mmCOMPUTE_NUM_THREAD_Z, 1,
1483 mmCOMPUTE_PGM_RSRC1, 0x240, /* SGPRS=9 (80 GPRS) */
1484 mmCOMPUTE_PGM_RSRC2, 20,
1485 mmCOMPUTE_USER_DATA_0, 0xedcedc00,
1486 mmCOMPUTE_USER_DATA_1, 0xedcedc01,
1487 mmCOMPUTE_USER_DATA_2, 0xedcedc02,
1488 mmCOMPUTE_USER_DATA_3, 0xedcedc03,
1489 mmCOMPUTE_USER_DATA_4, 0xedcedc04,
1490 mmCOMPUTE_USER_DATA_5, 0xedcedc05,
1491 mmCOMPUTE_USER_DATA_6, 0xedcedc06,
1492 mmCOMPUTE_USER_DATA_7, 0xedcedc07,
1493 mmCOMPUTE_USER_DATA_8, 0xedcedc08,
1494 mmCOMPUTE_USER_DATA_9, 0xedcedc09,
1497 static const u32 sgpr2_init_regs[] =
1499 mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0xf0,
1500 mmCOMPUTE_RESOURCE_LIMITS, 0x1000000,
1501 mmCOMPUTE_NUM_THREAD_X, 256*5,
1502 mmCOMPUTE_NUM_THREAD_Y, 1,
1503 mmCOMPUTE_NUM_THREAD_Z, 1,
1504 mmCOMPUTE_PGM_RSRC1, 0x240, /* SGPRS=9 (80 GPRS) */
1505 mmCOMPUTE_PGM_RSRC2, 20,
1506 mmCOMPUTE_USER_DATA_0, 0xedcedc00,
1507 mmCOMPUTE_USER_DATA_1, 0xedcedc01,
1508 mmCOMPUTE_USER_DATA_2, 0xedcedc02,
1509 mmCOMPUTE_USER_DATA_3, 0xedcedc03,
1510 mmCOMPUTE_USER_DATA_4, 0xedcedc04,
1511 mmCOMPUTE_USER_DATA_5, 0xedcedc05,
1512 mmCOMPUTE_USER_DATA_6, 0xedcedc06,
1513 mmCOMPUTE_USER_DATA_7, 0xedcedc07,
1514 mmCOMPUTE_USER_DATA_8, 0xedcedc08,
1515 mmCOMPUTE_USER_DATA_9, 0xedcedc09,
1518 static const u32 sec_ded_counter_registers[] =
1521 mmCPC_EDC_SCRATCH_CNT,
1522 mmCPC_EDC_UCODE_CNT,
1529 mmDC_EDC_CSINVOC_CNT,
1530 mmDC_EDC_RESTORE_CNT,
1536 mmSQC_ATC_EDC_GATCL1_CNT,
1542 mmTCP_ATC_EDC_GATCL1_CNT,
1547 static int gfx_v8_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
1549 struct amdgpu_ring *ring = &adev->gfx.compute_ring[0];
1550 struct amdgpu_ib ib;
1551 struct dma_fence *f = NULL;
1554 unsigned total_size, vgpr_offset, sgpr_offset;
1557 /* only supported on CZ */
1558 if (adev->asic_type != CHIP_CARRIZO)
1561 /* bail if the compute ring is not ready */
1562 if (!ring->sched.ready)
1565 tmp = RREG32(mmGB_EDC_MODE);
1566 WREG32(mmGB_EDC_MODE, 0);
1569 (((ARRAY_SIZE(vgpr_init_regs) / 2) * 3) + 4 + 5 + 2) * 4;
1571 (((ARRAY_SIZE(sgpr1_init_regs) / 2) * 3) + 4 + 5 + 2) * 4;
1573 (((ARRAY_SIZE(sgpr2_init_regs) / 2) * 3) + 4 + 5 + 2) * 4;
1574 total_size = ALIGN(total_size, 256);
1575 vgpr_offset = total_size;
1576 total_size += ALIGN(sizeof(vgpr_init_compute_shader), 256);
1577 sgpr_offset = total_size;
1578 total_size += sizeof(sgpr_init_compute_shader);
1580 /* allocate an indirect buffer to put the commands in */
1581 memset(&ib, 0, sizeof(ib));
1582 r = amdgpu_ib_get(adev, NULL, total_size, &ib);
1584 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
1588 /* load the compute shaders */
1589 for (i = 0; i < ARRAY_SIZE(vgpr_init_compute_shader); i++)
1590 ib.ptr[i + (vgpr_offset / 4)] = vgpr_init_compute_shader[i];
1592 for (i = 0; i < ARRAY_SIZE(sgpr_init_compute_shader); i++)
1593 ib.ptr[i + (sgpr_offset / 4)] = sgpr_init_compute_shader[i];
1595 /* init the ib length to 0 */
1599 /* write the register state for the compute dispatch */
1600 for (i = 0; i < ARRAY_SIZE(vgpr_init_regs); i += 2) {
1601 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
1602 ib.ptr[ib.length_dw++] = vgpr_init_regs[i] - PACKET3_SET_SH_REG_START;
1603 ib.ptr[ib.length_dw++] = vgpr_init_regs[i + 1];
1605 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
1606 gpu_addr = (ib.gpu_addr + (u64)vgpr_offset) >> 8;
1607 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
1608 ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START;
1609 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
1610 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
1612 /* write dispatch packet */
1613 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
1614 ib.ptr[ib.length_dw++] = 8; /* x */
1615 ib.ptr[ib.length_dw++] = 1; /* y */
1616 ib.ptr[ib.length_dw++] = 1; /* z */
1617 ib.ptr[ib.length_dw++] =
1618 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
1620 /* write CS partial flush packet */
1621 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
1622 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
1625 /* write the register state for the compute dispatch */
1626 for (i = 0; i < ARRAY_SIZE(sgpr1_init_regs); i += 2) {
1627 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
1628 ib.ptr[ib.length_dw++] = sgpr1_init_regs[i] - PACKET3_SET_SH_REG_START;
1629 ib.ptr[ib.length_dw++] = sgpr1_init_regs[i + 1];
1631 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
1632 gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8;
1633 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
1634 ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START;
1635 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
1636 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
1638 /* write dispatch packet */
1639 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
1640 ib.ptr[ib.length_dw++] = 8; /* x */
1641 ib.ptr[ib.length_dw++] = 1; /* y */
1642 ib.ptr[ib.length_dw++] = 1; /* z */
1643 ib.ptr[ib.length_dw++] =
1644 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
1646 /* write CS partial flush packet */
1647 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
1648 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
1651 /* write the register state for the compute dispatch */
1652 for (i = 0; i < ARRAY_SIZE(sgpr2_init_regs); i += 2) {
1653 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
1654 ib.ptr[ib.length_dw++] = sgpr2_init_regs[i] - PACKET3_SET_SH_REG_START;
1655 ib.ptr[ib.length_dw++] = sgpr2_init_regs[i + 1];
1657 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
1658 gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8;
1659 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
1660 ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START;
1661 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);
1662 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr);
1664 /* write dispatch packet */
1665 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
1666 ib.ptr[ib.length_dw++] = 8; /* x */
1667 ib.ptr[ib.length_dw++] = 1; /* y */
1668 ib.ptr[ib.length_dw++] = 1; /* z */
1669 ib.ptr[ib.length_dw++] =
1670 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
1672 /* write CS partial flush packet */
1673 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0);
1674 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
1676 /* shedule the ib on the ring */
1677 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1679 DRM_ERROR("amdgpu: ib submit failed (%d).\n", r);
1683 /* wait for the GPU to finish processing the IB */
1684 r = dma_fence_wait(f, false);
1686 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
1690 tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, DED_MODE, 2);
1691 tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, PROP_FED, 1);
1692 WREG32(mmGB_EDC_MODE, tmp);
1694 tmp = RREG32(mmCC_GC_EDC_CONFIG);
1695 tmp = REG_SET_FIELD(tmp, CC_GC_EDC_CONFIG, DIS_EDC, 0) | 1;
1696 WREG32(mmCC_GC_EDC_CONFIG, tmp);
1699 /* read back registers to clear the counters */
1700 for (i = 0; i < ARRAY_SIZE(sec_ded_counter_registers); i++)
1701 RREG32(sec_ded_counter_registers[i]);
1704 amdgpu_ib_free(adev, &ib, NULL);
1710 static int gfx_v8_0_gpu_early_init(struct amdgpu_device *adev)
1713 u32 mc_shared_chmap, mc_arb_ramcfg;
1714 u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
1718 switch (adev->asic_type) {
1720 adev->gfx.config.max_shader_engines = 1;
1721 adev->gfx.config.max_tile_pipes = 2;
1722 adev->gfx.config.max_cu_per_sh = 6;
1723 adev->gfx.config.max_sh_per_se = 1;
1724 adev->gfx.config.max_backends_per_se = 2;
1725 adev->gfx.config.max_texture_channel_caches = 2;
1726 adev->gfx.config.max_gprs = 256;
1727 adev->gfx.config.max_gs_threads = 32;
1728 adev->gfx.config.max_hw_contexts = 8;
1730 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1731 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1732 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1733 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1734 gb_addr_config = TOPAZ_GB_ADDR_CONFIG_GOLDEN;
1737 adev->gfx.config.max_shader_engines = 4;
1738 adev->gfx.config.max_tile_pipes = 16;
1739 adev->gfx.config.max_cu_per_sh = 16;
1740 adev->gfx.config.max_sh_per_se = 1;
1741 adev->gfx.config.max_backends_per_se = 4;
1742 adev->gfx.config.max_texture_channel_caches = 16;
1743 adev->gfx.config.max_gprs = 256;
1744 adev->gfx.config.max_gs_threads = 32;
1745 adev->gfx.config.max_hw_contexts = 8;
1747 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1748 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1749 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1750 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1751 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1753 case CHIP_POLARIS11:
1754 case CHIP_POLARIS12:
1755 ret = amdgpu_atombios_get_gfx_info(adev);
1758 adev->gfx.config.max_gprs = 256;
1759 adev->gfx.config.max_gs_threads = 32;
1760 adev->gfx.config.max_hw_contexts = 8;
1762 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1763 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1764 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1765 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1766 gb_addr_config = POLARIS11_GB_ADDR_CONFIG_GOLDEN;
1768 case CHIP_POLARIS10:
1770 ret = amdgpu_atombios_get_gfx_info(adev);
1773 adev->gfx.config.max_gprs = 256;
1774 adev->gfx.config.max_gs_threads = 32;
1775 adev->gfx.config.max_hw_contexts = 8;
1777 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1778 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1779 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1780 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1781 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1784 adev->gfx.config.max_shader_engines = 4;
1785 adev->gfx.config.max_tile_pipes = 8;
1786 adev->gfx.config.max_cu_per_sh = 8;
1787 adev->gfx.config.max_sh_per_se = 1;
1788 adev->gfx.config.max_backends_per_se = 2;
1789 adev->gfx.config.max_texture_channel_caches = 8;
1790 adev->gfx.config.max_gprs = 256;
1791 adev->gfx.config.max_gs_threads = 32;
1792 adev->gfx.config.max_hw_contexts = 8;
1794 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1795 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1796 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1797 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1798 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1801 adev->gfx.config.max_shader_engines = 1;
1802 adev->gfx.config.max_tile_pipes = 2;
1803 adev->gfx.config.max_sh_per_se = 1;
1804 adev->gfx.config.max_backends_per_se = 2;
1805 adev->gfx.config.max_cu_per_sh = 8;
1806 adev->gfx.config.max_texture_channel_caches = 2;
1807 adev->gfx.config.max_gprs = 256;
1808 adev->gfx.config.max_gs_threads = 32;
1809 adev->gfx.config.max_hw_contexts = 8;
1811 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1812 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1813 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1814 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1815 gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN;
1818 adev->gfx.config.max_shader_engines = 1;
1819 adev->gfx.config.max_tile_pipes = 2;
1820 adev->gfx.config.max_sh_per_se = 1;
1821 adev->gfx.config.max_backends_per_se = 1;
1822 adev->gfx.config.max_cu_per_sh = 3;
1823 adev->gfx.config.max_texture_channel_caches = 2;
1824 adev->gfx.config.max_gprs = 256;
1825 adev->gfx.config.max_gs_threads = 16;
1826 adev->gfx.config.max_hw_contexts = 8;
1828 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1829 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1830 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1831 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1832 gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN;
1835 adev->gfx.config.max_shader_engines = 2;
1836 adev->gfx.config.max_tile_pipes = 4;
1837 adev->gfx.config.max_cu_per_sh = 2;
1838 adev->gfx.config.max_sh_per_se = 1;
1839 adev->gfx.config.max_backends_per_se = 2;
1840 adev->gfx.config.max_texture_channel_caches = 4;
1841 adev->gfx.config.max_gprs = 256;
1842 adev->gfx.config.max_gs_threads = 32;
1843 adev->gfx.config.max_hw_contexts = 8;
1845 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1846 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1847 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1848 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1849 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1853 mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
1854 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
1855 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
1857 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
1858 adev->gfx.config.mem_max_burst_length_bytes = 256;
1859 if (adev->flags & AMD_IS_APU) {
1860 /* Get memory bank mapping mode. */
1861 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
1862 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
1863 dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
1865 tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
1866 dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
1867 dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
1869 /* Validate settings in case only one DIMM installed. */
1870 if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12))
1871 dimm00_addr_map = 0;
1872 if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12))
1873 dimm01_addr_map = 0;
1874 if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12))
1875 dimm10_addr_map = 0;
1876 if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12))
1877 dimm11_addr_map = 0;
1879 /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */
1880 /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */
1881 if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11))
1882 adev->gfx.config.mem_row_size_in_kb = 2;
1884 adev->gfx.config.mem_row_size_in_kb = 1;
1886 tmp = REG_GET_FIELD(mc_arb_ramcfg, MC_ARB_RAMCFG, NOOFCOLS);
1887 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
1888 if (adev->gfx.config.mem_row_size_in_kb > 4)
1889 adev->gfx.config.mem_row_size_in_kb = 4;
1892 adev->gfx.config.shader_engine_tile_size = 32;
1893 adev->gfx.config.num_gpus = 1;
1894 adev->gfx.config.multi_gpu_tile_size = 64;
1896 /* fix up row size */
1897 switch (adev->gfx.config.mem_row_size_in_kb) {
1900 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 0);
1903 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 1);
1906 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 2);
1909 adev->gfx.config.gb_addr_config = gb_addr_config;
1914 static int gfx_v8_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
1915 int mec, int pipe, int queue)
1919 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
1921 ring = &adev->gfx.compute_ring[ring_id];
1926 ring->queue = queue;
1928 ring->ring_obj = NULL;
1929 ring->use_doorbell = true;
1930 ring->doorbell_index = adev->doorbell_index.mec_ring0 + ring_id;
1931 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
1932 + (ring_id * GFX8_MEC_HPD_SIZE);
1933 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
1935 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
1936 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
1939 /* type-2 packets are deprecated on MEC, use type-3 instead */
1940 r = amdgpu_ring_init(adev, ring, 1024,
1941 &adev->gfx.eop_irq, irq_type);
1949 static void gfx_v8_0_sq_irq_work_func(struct work_struct *work);
1951 static int gfx_v8_0_sw_init(void *handle)
1953 int i, j, k, r, ring_id;
1954 struct amdgpu_ring *ring;
1955 struct amdgpu_kiq *kiq;
1956 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1958 switch (adev->asic_type) {
1962 case CHIP_POLARIS10:
1963 case CHIP_POLARIS11:
1964 case CHIP_POLARIS12:
1966 adev->gfx.mec.num_mec = 2;
1971 adev->gfx.mec.num_mec = 1;
1975 adev->gfx.mec.num_pipe_per_mec = 4;
1976 adev->gfx.mec.num_queue_per_pipe = 8;
1979 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_END_OF_PIPE, &adev->gfx.eop_irq);
1983 /* Privileged reg */
1984 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_PRIV_REG_FAULT,
1985 &adev->gfx.priv_reg_irq);
1989 /* Privileged inst */
1990 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_PRIV_INSTR_FAULT,
1991 &adev->gfx.priv_inst_irq);
1995 /* Add CP EDC/ECC irq */
1996 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_ECC_ERROR,
1997 &adev->gfx.cp_ecc_error_irq);
2001 /* SQ interrupts. */
2002 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SQ_INTERRUPT_MSG,
2005 DRM_ERROR("amdgpu_irq_add() for SQ failed: %d\n", r);
2009 INIT_WORK(&adev->gfx.sq_work.work, gfx_v8_0_sq_irq_work_func);
2011 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
2013 gfx_v8_0_scratch_init(adev);
2015 r = gfx_v8_0_init_microcode(adev);
2017 DRM_ERROR("Failed to load gfx firmware!\n");
2021 r = adev->gfx.rlc.funcs->init(adev);
2023 DRM_ERROR("Failed to init rlc BOs!\n");
2027 r = gfx_v8_0_mec_init(adev);
2029 DRM_ERROR("Failed to init MEC BOs!\n");
2033 /* set up the gfx ring */
2034 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
2035 ring = &adev->gfx.gfx_ring[i];
2036 ring->ring_obj = NULL;
2037 sprintf(ring->name, "gfx");
2038 /* no gfx doorbells on iceland */
2039 if (adev->asic_type != CHIP_TOPAZ) {
2040 ring->use_doorbell = true;
2041 ring->doorbell_index = adev->doorbell_index.gfx_ring0;
2044 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq,
2045 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP);
2051 /* set up the compute queues - allocate horizontally across pipes */
2053 for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
2054 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
2055 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
2056 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, j))
2059 r = gfx_v8_0_compute_ring_init(adev,
2070 r = amdgpu_gfx_kiq_init(adev, GFX8_MEC_HPD_SIZE);
2072 DRM_ERROR("Failed to init KIQ BOs!\n");
2076 kiq = &adev->gfx.kiq;
2077 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
2081 /* create MQD for all compute queues as well as KIQ for SRIOV case */
2082 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct vi_mqd_allocation));
2086 adev->gfx.ce_ram_size = 0x8000;
2088 r = gfx_v8_0_gpu_early_init(adev);
2095 static int gfx_v8_0_sw_fini(void *handle)
2097 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2100 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2101 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
2102 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2103 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
2105 amdgpu_gfx_mqd_sw_fini(adev);
2106 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq);
2107 amdgpu_gfx_kiq_fini(adev);
2109 gfx_v8_0_mec_fini(adev);
2110 amdgpu_gfx_rlc_fini(adev);
2111 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
2112 &adev->gfx.rlc.clear_state_gpu_addr,
2113 (void **)&adev->gfx.rlc.cs_ptr);
2114 if ((adev->asic_type == CHIP_CARRIZO) ||
2115 (adev->asic_type == CHIP_STONEY)) {
2116 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
2117 &adev->gfx.rlc.cp_table_gpu_addr,
2118 (void **)&adev->gfx.rlc.cp_table_ptr);
2120 gfx_v8_0_free_microcode(adev);
2125 static void gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev)
2127 uint32_t *modearray, *mod2array;
2128 const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array);
2129 const u32 num_secondary_tile_mode_states = ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
2132 modearray = adev->gfx.config.tile_mode_array;
2133 mod2array = adev->gfx.config.macrotile_mode_array;
2135 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2136 modearray[reg_offset] = 0;
2138 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2139 mod2array[reg_offset] = 0;
2141 switch (adev->asic_type) {
2143 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2144 PIPE_CONFIG(ADDR_SURF_P2) |
2145 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2146 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2147 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2148 PIPE_CONFIG(ADDR_SURF_P2) |
2149 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2150 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2151 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2152 PIPE_CONFIG(ADDR_SURF_P2) |
2153 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2154 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2155 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2156 PIPE_CONFIG(ADDR_SURF_P2) |
2157 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2158 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2159 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2160 PIPE_CONFIG(ADDR_SURF_P2) |
2161 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2162 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2163 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2164 PIPE_CONFIG(ADDR_SURF_P2) |
2165 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2166 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2167 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2168 PIPE_CONFIG(ADDR_SURF_P2) |
2169 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2170 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2171 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2172 PIPE_CONFIG(ADDR_SURF_P2));
2173 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2174 PIPE_CONFIG(ADDR_SURF_P2) |
2175 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2176 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2177 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2178 PIPE_CONFIG(ADDR_SURF_P2) |
2179 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2180 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2181 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2182 PIPE_CONFIG(ADDR_SURF_P2) |
2183 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2184 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2185 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2186 PIPE_CONFIG(ADDR_SURF_P2) |
2187 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2188 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2189 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2190 PIPE_CONFIG(ADDR_SURF_P2) |
2191 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2192 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2193 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2194 PIPE_CONFIG(ADDR_SURF_P2) |
2195 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2196 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2197 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2198 PIPE_CONFIG(ADDR_SURF_P2) |
2199 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2200 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2201 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2202 PIPE_CONFIG(ADDR_SURF_P2) |
2203 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2204 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2205 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2206 PIPE_CONFIG(ADDR_SURF_P2) |
2207 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2208 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2209 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2210 PIPE_CONFIG(ADDR_SURF_P2) |
2211 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2212 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2213 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2214 PIPE_CONFIG(ADDR_SURF_P2) |
2215 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2216 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2217 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2218 PIPE_CONFIG(ADDR_SURF_P2) |
2219 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2220 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2221 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2222 PIPE_CONFIG(ADDR_SURF_P2) |
2223 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2224 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2225 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2226 PIPE_CONFIG(ADDR_SURF_P2) |
2227 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2228 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2229 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2230 PIPE_CONFIG(ADDR_SURF_P2) |
2231 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2232 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2233 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2234 PIPE_CONFIG(ADDR_SURF_P2) |
2235 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2236 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2237 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2238 PIPE_CONFIG(ADDR_SURF_P2) |
2239 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2240 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2241 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2242 PIPE_CONFIG(ADDR_SURF_P2) |
2243 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2244 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2246 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2247 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2248 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2249 NUM_BANKS(ADDR_SURF_8_BANK));
2250 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2251 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2252 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2253 NUM_BANKS(ADDR_SURF_8_BANK));
2254 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2255 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2256 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2257 NUM_BANKS(ADDR_SURF_8_BANK));
2258 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2259 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2260 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2261 NUM_BANKS(ADDR_SURF_8_BANK));
2262 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2263 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2264 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2265 NUM_BANKS(ADDR_SURF_8_BANK));
2266 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2267 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2268 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2269 NUM_BANKS(ADDR_SURF_8_BANK));
2270 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2271 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2272 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2273 NUM_BANKS(ADDR_SURF_8_BANK));
2274 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2275 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2276 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2277 NUM_BANKS(ADDR_SURF_16_BANK));
2278 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2279 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2280 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2281 NUM_BANKS(ADDR_SURF_16_BANK));
2282 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2283 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2284 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2285 NUM_BANKS(ADDR_SURF_16_BANK));
2286 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2287 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2288 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2289 NUM_BANKS(ADDR_SURF_16_BANK));
2290 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2291 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2292 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2293 NUM_BANKS(ADDR_SURF_16_BANK));
2294 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2295 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2296 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2297 NUM_BANKS(ADDR_SURF_16_BANK));
2298 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2299 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2300 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2301 NUM_BANKS(ADDR_SURF_8_BANK));
2303 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2304 if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 &&
2306 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2308 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2309 if (reg_offset != 7)
2310 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
2315 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2316 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2317 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2318 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2319 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2320 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2321 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2322 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2323 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2324 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2325 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2326 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2327 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2328 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2329 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2330 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2331 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2332 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2333 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2334 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2335 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2336 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2337 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2338 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2339 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2340 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2341 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2342 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2343 modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2344 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2345 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2346 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2347 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2348 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
2349 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2350 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2351 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2352 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2353 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2354 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2355 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2356 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2357 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2358 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2359 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2360 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2361 modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2362 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2363 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2364 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2365 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2366 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2367 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2368 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2369 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2370 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2371 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2372 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2373 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2374 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2375 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2376 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2377 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2378 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2379 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2380 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2381 modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2382 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2383 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2384 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2385 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2386 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2387 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2388 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2389 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2390 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2391 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2392 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2393 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2394 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2395 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2396 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2397 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2398 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2399 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2400 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2401 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2402 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2403 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2404 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2405 modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2406 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2407 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2408 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2409 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2410 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2411 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2412 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2413 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2414 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2415 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2416 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2417 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2418 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2419 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2420 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2421 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2422 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2423 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2424 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2425 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2426 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2427 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2428 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2429 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2430 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2431 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2432 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2433 modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2434 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2435 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2436 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2438 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2439 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2440 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2441 NUM_BANKS(ADDR_SURF_8_BANK));
2442 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2443 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2444 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2445 NUM_BANKS(ADDR_SURF_8_BANK));
2446 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2447 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2448 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2449 NUM_BANKS(ADDR_SURF_8_BANK));
2450 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2451 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2452 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2453 NUM_BANKS(ADDR_SURF_8_BANK));
2454 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2455 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2456 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2457 NUM_BANKS(ADDR_SURF_8_BANK));
2458 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2459 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2460 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2461 NUM_BANKS(ADDR_SURF_8_BANK));
2462 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2463 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2464 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2465 NUM_BANKS(ADDR_SURF_8_BANK));
2466 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2467 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2468 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2469 NUM_BANKS(ADDR_SURF_8_BANK));
2470 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2471 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2472 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2473 NUM_BANKS(ADDR_SURF_8_BANK));
2474 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2475 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2476 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2477 NUM_BANKS(ADDR_SURF_8_BANK));
2478 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2479 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2480 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2481 NUM_BANKS(ADDR_SURF_8_BANK));
2482 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2483 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2484 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2485 NUM_BANKS(ADDR_SURF_8_BANK));
2486 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2487 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2488 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2489 NUM_BANKS(ADDR_SURF_8_BANK));
2490 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2491 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2492 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2493 NUM_BANKS(ADDR_SURF_4_BANK));
2495 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2496 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2498 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2499 if (reg_offset != 7)
2500 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
2504 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2505 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2506 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2507 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2508 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2509 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2510 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2511 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2512 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2513 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2514 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2515 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2516 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2517 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2518 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2519 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2520 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2521 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2522 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2523 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2524 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2525 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2526 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2527 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2528 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2529 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2530 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2531 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2532 modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2533 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2534 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2535 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2536 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2537 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16));
2538 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2539 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2540 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2541 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2542 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2543 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2544 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2545 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2546 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2547 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2548 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2549 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2550 modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2551 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2552 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2553 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2554 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2555 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2556 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2557 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2558 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2559 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2560 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2561 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2562 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2563 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2564 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2565 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2566 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2567 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2568 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2569 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2570 modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2571 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2572 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2573 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2574 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2575 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2576 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2577 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2578 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2579 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2580 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2581 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2582 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2583 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2584 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2585 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2586 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2587 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2588 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2589 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2590 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2591 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2592 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2593 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2594 modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2595 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2596 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2597 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2598 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2599 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2600 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2601 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2602 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2603 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2604 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2605 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2606 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2607 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2608 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2609 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2610 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2611 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2612 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2613 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2614 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2615 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2616 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2617 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2618 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2619 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2620 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2621 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2622 modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2623 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2624 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2625 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2627 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2628 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2629 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2630 NUM_BANKS(ADDR_SURF_16_BANK));
2631 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2632 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2633 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2634 NUM_BANKS(ADDR_SURF_16_BANK));
2635 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2636 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2637 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2638 NUM_BANKS(ADDR_SURF_16_BANK));
2639 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2640 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2641 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2642 NUM_BANKS(ADDR_SURF_16_BANK));
2643 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2644 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2645 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2646 NUM_BANKS(ADDR_SURF_16_BANK));
2647 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2648 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2649 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2650 NUM_BANKS(ADDR_SURF_16_BANK));
2651 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2652 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2653 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2654 NUM_BANKS(ADDR_SURF_16_BANK));
2655 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2656 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2657 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2658 NUM_BANKS(ADDR_SURF_16_BANK));
2659 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2660 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2661 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2662 NUM_BANKS(ADDR_SURF_16_BANK));
2663 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2664 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2665 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2666 NUM_BANKS(ADDR_SURF_16_BANK));
2667 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2668 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2669 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2670 NUM_BANKS(ADDR_SURF_16_BANK));
2671 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2672 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2673 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2674 NUM_BANKS(ADDR_SURF_8_BANK));
2675 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2676 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2677 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2678 NUM_BANKS(ADDR_SURF_4_BANK));
2679 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2680 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2681 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2682 NUM_BANKS(ADDR_SURF_4_BANK));
2684 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2685 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2687 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2688 if (reg_offset != 7)
2689 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
2692 case CHIP_POLARIS11:
2693 case CHIP_POLARIS12:
2694 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2695 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2696 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2697 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2698 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2699 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2700 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2701 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2702 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2703 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2704 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2705 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2706 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2707 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2708 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2709 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2710 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2711 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2712 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2713 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2714 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2715 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2716 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2717 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2718 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2719 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2720 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2721 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2722 modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2723 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2724 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2725 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2726 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2727 PIPE_CONFIG(ADDR_SURF_P4_16x16));
2728 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2729 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2730 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2731 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2732 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2733 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2734 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2735 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2736 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2737 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2738 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2739 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2740 modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2741 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2742 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2743 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2744 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2745 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2746 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2747 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2748 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2749 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2750 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2751 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2752 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2753 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2754 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2755 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2756 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2757 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2758 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2759 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2760 modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2761 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2762 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2763 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2764 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2765 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2766 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2767 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2768 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2769 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2770 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2771 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2772 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2773 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2774 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2775 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2776 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2777 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2778 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2779 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2780 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2781 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2782 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2783 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2784 modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2785 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2786 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2787 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2788 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2789 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2790 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2791 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2792 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2793 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2794 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2795 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2796 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2797 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2798 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2799 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2800 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2801 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2802 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2803 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2804 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2805 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2806 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2807 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2808 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2809 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2810 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2811 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2812 modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2813 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2814 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2815 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2817 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2818 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2819 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2820 NUM_BANKS(ADDR_SURF_16_BANK));
2822 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2823 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2824 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2825 NUM_BANKS(ADDR_SURF_16_BANK));
2827 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2828 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2829 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2830 NUM_BANKS(ADDR_SURF_16_BANK));
2832 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2833 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2834 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2835 NUM_BANKS(ADDR_SURF_16_BANK));
2837 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2838 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2839 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2840 NUM_BANKS(ADDR_SURF_16_BANK));
2842 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2843 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2844 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2845 NUM_BANKS(ADDR_SURF_16_BANK));
2847 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2848 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2849 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2850 NUM_BANKS(ADDR_SURF_16_BANK));
2852 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2853 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2854 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2855 NUM_BANKS(ADDR_SURF_16_BANK));
2857 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2858 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2859 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2860 NUM_BANKS(ADDR_SURF_16_BANK));
2862 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2863 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2864 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2865 NUM_BANKS(ADDR_SURF_16_BANK));
2867 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2868 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2869 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2870 NUM_BANKS(ADDR_SURF_16_BANK));
2872 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2873 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2874 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2875 NUM_BANKS(ADDR_SURF_16_BANK));
2877 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2878 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2879 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2880 NUM_BANKS(ADDR_SURF_8_BANK));
2882 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2883 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2884 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2885 NUM_BANKS(ADDR_SURF_4_BANK));
2887 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
2888 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2890 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
2891 if (reg_offset != 7)
2892 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
2895 case CHIP_POLARIS10:
2896 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2897 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2898 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2899 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2900 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2901 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2902 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2903 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2904 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2905 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2906 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2907 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2908 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2909 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2910 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2911 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2912 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2913 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2914 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2915 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2916 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2917 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2918 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2919 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2920 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2921 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2922 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2923 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2924 modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2925 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2926 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2927 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2928 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2929 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16));
2930 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2931 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2932 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2933 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2934 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2935 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2936 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2937 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2938 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2939 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2940 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2941 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2942 modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2943 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2944 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2945 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2946 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2947 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2948 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2949 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2950 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2951 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2952 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2953 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2954 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2955 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2956 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2957 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2958 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2959 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2960 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2961 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2962 modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2963 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2964 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2965 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2966 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2967 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2968 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2969 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2970 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2971 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2972 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2973 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2974 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2975 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2976 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2977 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2978 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2979 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2980 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2981 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2982 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2983 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2984 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2985 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2986 modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2987 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2988 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2989 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2990 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2991 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2992 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2993 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2994 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2995 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2996 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2997 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2998 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2999 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
3000 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3001 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3002 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3003 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
3004 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3005 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3006 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3007 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
3008 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3009 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3010 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3011 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
3012 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3013 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3014 modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3015 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
3016 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3017 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3019 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3020 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3021 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3022 NUM_BANKS(ADDR_SURF_16_BANK));
3024 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3025 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3026 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3027 NUM_BANKS(ADDR_SURF_16_BANK));
3029 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3030 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3031 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3032 NUM_BANKS(ADDR_SURF_16_BANK));
3034 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3035 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3036 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3037 NUM_BANKS(ADDR_SURF_16_BANK));
3039 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3040 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3041 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3042 NUM_BANKS(ADDR_SURF_16_BANK));
3044 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3045 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3046 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
3047 NUM_BANKS(ADDR_SURF_16_BANK));
3049 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3050 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3051 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
3052 NUM_BANKS(ADDR_SURF_16_BANK));
3054 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3055 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
3056 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3057 NUM_BANKS(ADDR_SURF_16_BANK));
3059 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3060 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3061 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3062 NUM_BANKS(ADDR_SURF_16_BANK));
3064 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3065 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3066 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3067 NUM_BANKS(ADDR_SURF_16_BANK));
3069 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3070 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3071 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3072 NUM_BANKS(ADDR_SURF_16_BANK));
3074 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3075 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3076 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
3077 NUM_BANKS(ADDR_SURF_8_BANK));
3079 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3080 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3081 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
3082 NUM_BANKS(ADDR_SURF_4_BANK));
3084 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3085 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3086 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
3087 NUM_BANKS(ADDR_SURF_4_BANK));
3089 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
3090 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
3092 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
3093 if (reg_offset != 7)
3094 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
3098 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3099 PIPE_CONFIG(ADDR_SURF_P2) |
3100 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
3101 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3102 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3103 PIPE_CONFIG(ADDR_SURF_P2) |
3104 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
3105 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3106 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3107 PIPE_CONFIG(ADDR_SURF_P2) |
3108 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
3109 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3110 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3111 PIPE_CONFIG(ADDR_SURF_P2) |
3112 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
3113 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3114 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3115 PIPE_CONFIG(ADDR_SURF_P2) |
3116 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
3117 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3118 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3119 PIPE_CONFIG(ADDR_SURF_P2) |
3120 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
3121 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3122 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3123 PIPE_CONFIG(ADDR_SURF_P2) |
3124 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
3125 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3126 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
3127 PIPE_CONFIG(ADDR_SURF_P2));
3128 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3129 PIPE_CONFIG(ADDR_SURF_P2) |
3130 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3131 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3132 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3133 PIPE_CONFIG(ADDR_SURF_P2) |
3134 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3135 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3136 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3137 PIPE_CONFIG(ADDR_SURF_P2) |
3138 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3139 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3140 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3141 PIPE_CONFIG(ADDR_SURF_P2) |
3142 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3143 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3144 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3145 PIPE_CONFIG(ADDR_SURF_P2) |
3146 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3147 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3148 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
3149 PIPE_CONFIG(ADDR_SURF_P2) |
3150 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3151 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3152 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3153 PIPE_CONFIG(ADDR_SURF_P2) |
3154 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3155 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3156 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
3157 PIPE_CONFIG(ADDR_SURF_P2) |
3158 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3159 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3160 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
3161 PIPE_CONFIG(ADDR_SURF_P2) |
3162 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3163 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3164 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
3165 PIPE_CONFIG(ADDR_SURF_P2) |
3166 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3167 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3168 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
3169 PIPE_CONFIG(ADDR_SURF_P2) |
3170 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3171 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3172 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
3173 PIPE_CONFIG(ADDR_SURF_P2) |
3174 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3175 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3176 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
3177 PIPE_CONFIG(ADDR_SURF_P2) |
3178 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3179 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3180 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
3181 PIPE_CONFIG(ADDR_SURF_P2) |
3182 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3183 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3184 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
3185 PIPE_CONFIG(ADDR_SURF_P2) |
3186 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3187 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3188 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3189 PIPE_CONFIG(ADDR_SURF_P2) |
3190 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3191 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3192 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3193 PIPE_CONFIG(ADDR_SURF_P2) |
3194 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3195 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3196 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3197 PIPE_CONFIG(ADDR_SURF_P2) |
3198 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3199 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3201 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3202 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3203 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3204 NUM_BANKS(ADDR_SURF_8_BANK));
3205 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3206 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3207 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3208 NUM_BANKS(ADDR_SURF_8_BANK));
3209 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3210 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3211 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3212 NUM_BANKS(ADDR_SURF_8_BANK));
3213 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3214 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3215 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3216 NUM_BANKS(ADDR_SURF_8_BANK));
3217 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3218 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3219 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3220 NUM_BANKS(ADDR_SURF_8_BANK));
3221 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3222 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3223 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3224 NUM_BANKS(ADDR_SURF_8_BANK));
3225 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3226 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3227 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3228 NUM_BANKS(ADDR_SURF_8_BANK));
3229 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
3230 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
3231 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3232 NUM_BANKS(ADDR_SURF_16_BANK));
3233 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
3234 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3235 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3236 NUM_BANKS(ADDR_SURF_16_BANK));
3237 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
3238 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3239 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3240 NUM_BANKS(ADDR_SURF_16_BANK));
3241 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
3242 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3243 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3244 NUM_BANKS(ADDR_SURF_16_BANK));
3245 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3246 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3247 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3248 NUM_BANKS(ADDR_SURF_16_BANK));
3249 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3250 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3251 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3252 NUM_BANKS(ADDR_SURF_16_BANK));
3253 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3254 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3255 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3256 NUM_BANKS(ADDR_SURF_8_BANK));
3258 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
3259 if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 &&
3261 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
3263 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
3264 if (reg_offset != 7)
3265 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
3270 "Unknown chip type (%d) in function gfx_v8_0_tiling_mode_table_init() falling through to CHIP_CARRIZO\n",
3275 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3276 PIPE_CONFIG(ADDR_SURF_P2) |
3277 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
3278 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3279 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3280 PIPE_CONFIG(ADDR_SURF_P2) |
3281 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
3282 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3283 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3284 PIPE_CONFIG(ADDR_SURF_P2) |
3285 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
3286 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3287 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3288 PIPE_CONFIG(ADDR_SURF_P2) |
3289 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
3290 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3291 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3292 PIPE_CONFIG(ADDR_SURF_P2) |
3293 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
3294 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3295 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3296 PIPE_CONFIG(ADDR_SURF_P2) |
3297 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
3298 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3299 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3300 PIPE_CONFIG(ADDR_SURF_P2) |
3301 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
3302 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
3303 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
3304 PIPE_CONFIG(ADDR_SURF_P2));
3305 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3306 PIPE_CONFIG(ADDR_SURF_P2) |
3307 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3308 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3309 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3310 PIPE_CONFIG(ADDR_SURF_P2) |
3311 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3312 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3313 modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3314 PIPE_CONFIG(ADDR_SURF_P2) |
3315 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
3316 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3317 modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3318 PIPE_CONFIG(ADDR_SURF_P2) |
3319 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3320 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3321 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3322 PIPE_CONFIG(ADDR_SURF_P2) |
3323 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3324 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3325 modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
3326 PIPE_CONFIG(ADDR_SURF_P2) |
3327 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3328 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3329 modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3330 PIPE_CONFIG(ADDR_SURF_P2) |
3331 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3332 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3333 modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
3334 PIPE_CONFIG(ADDR_SURF_P2) |
3335 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3336 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3337 modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
3338 PIPE_CONFIG(ADDR_SURF_P2) |
3339 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3340 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3341 modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
3342 PIPE_CONFIG(ADDR_SURF_P2) |
3343 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3344 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3345 modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
3346 PIPE_CONFIG(ADDR_SURF_P2) |
3347 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3348 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3349 modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
3350 PIPE_CONFIG(ADDR_SURF_P2) |
3351 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3352 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3353 modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
3354 PIPE_CONFIG(ADDR_SURF_P2) |
3355 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
3356 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3357 modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
3358 PIPE_CONFIG(ADDR_SURF_P2) |
3359 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3360 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3361 modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
3362 PIPE_CONFIG(ADDR_SURF_P2) |
3363 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
3364 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
3365 modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
3366 PIPE_CONFIG(ADDR_SURF_P2) |
3367 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3368 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3369 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
3370 PIPE_CONFIG(ADDR_SURF_P2) |
3371 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3372 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
3373 modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
3374 PIPE_CONFIG(ADDR_SURF_P2) |
3375 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
3376 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
3378 mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3379 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3380 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3381 NUM_BANKS(ADDR_SURF_8_BANK));
3382 mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3383 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3384 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3385 NUM_BANKS(ADDR_SURF_8_BANK));
3386 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3387 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3388 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3389 NUM_BANKS(ADDR_SURF_8_BANK));
3390 mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3391 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3392 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3393 NUM_BANKS(ADDR_SURF_8_BANK));
3394 mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3395 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3396 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3397 NUM_BANKS(ADDR_SURF_8_BANK));
3398 mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3399 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3400 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3401 NUM_BANKS(ADDR_SURF_8_BANK));
3402 mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3403 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3404 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3405 NUM_BANKS(ADDR_SURF_8_BANK));
3406 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
3407 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
3408 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3409 NUM_BANKS(ADDR_SURF_16_BANK));
3410 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
3411 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3412 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3413 NUM_BANKS(ADDR_SURF_16_BANK));
3414 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
3415 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
3416 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3417 NUM_BANKS(ADDR_SURF_16_BANK));
3418 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
3419 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3420 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3421 NUM_BANKS(ADDR_SURF_16_BANK));
3422 mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3423 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
3424 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3425 NUM_BANKS(ADDR_SURF_16_BANK));
3426 mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3427 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3428 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
3429 NUM_BANKS(ADDR_SURF_16_BANK));
3430 mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
3431 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
3432 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
3433 NUM_BANKS(ADDR_SURF_8_BANK));
3435 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
3436 if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 &&
3438 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
3440 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
3441 if (reg_offset != 7)
3442 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);
3448 static void gfx_v8_0_select_se_sh(struct amdgpu_device *adev,
3449 u32 se_num, u32 sh_num, u32 instance)
3453 if (instance == 0xffffffff)
3454 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
3456 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
3458 if (se_num == 0xffffffff)
3459 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
3461 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
3463 if (sh_num == 0xffffffff)
3464 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
3466 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
3468 WREG32(mmGRBM_GFX_INDEX, data);
3471 static void gfx_v8_0_select_me_pipe_q(struct amdgpu_device *adev,
3472 u32 me, u32 pipe, u32 q, u32 vm)
3474 vi_srbm_select(adev, me, pipe, q, vm);
3477 static u32 gfx_v8_0_get_rb_active_bitmap(struct amdgpu_device *adev)
3481 data = RREG32(mmCC_RB_BACKEND_DISABLE) |
3482 RREG32(mmGC_USER_RB_BACKEND_DISABLE);
3484 data = REG_GET_FIELD(data, GC_USER_RB_BACKEND_DISABLE, BACKEND_DISABLE);
3486 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
3487 adev->gfx.config.max_sh_per_se);
3489 return (~data) & mask;
3493 gfx_v8_0_raster_config(struct amdgpu_device *adev, u32 *rconf, u32 *rconf1)
3495 switch (adev->asic_type) {
3498 *rconf |= RB_MAP_PKR0(2) | RB_MAP_PKR1(2) |
3499 RB_XSEL2(1) | PKR_MAP(2) |
3500 PKR_XSEL(1) | PKR_YSEL(1) |
3501 SE_MAP(2) | SE_XSEL(2) | SE_YSEL(3);
3502 *rconf1 |= SE_PAIR_MAP(2) | SE_PAIR_XSEL(3) |
3506 case CHIP_POLARIS10:
3507 *rconf |= RB_MAP_PKR0(2) | RB_XSEL2(1) | SE_MAP(2) |
3508 SE_XSEL(1) | SE_YSEL(1);
3509 *rconf1 |= SE_PAIR_MAP(2) | SE_PAIR_XSEL(2) |
3514 *rconf |= RB_MAP_PKR0(2);
3517 case CHIP_POLARIS11:
3518 case CHIP_POLARIS12:
3519 *rconf |= RB_MAP_PKR0(2) | RB_XSEL2(1) | SE_MAP(2) |
3520 SE_XSEL(1) | SE_YSEL(1);
3528 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
3534 gfx_v8_0_write_harvested_raster_configs(struct amdgpu_device *adev,
3535 u32 raster_config, u32 raster_config_1,
3536 unsigned rb_mask, unsigned num_rb)
3538 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1);
3539 unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1);
3540 unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2);
3541 unsigned rb_per_se = num_rb / num_se;
3542 unsigned se_mask[4];
3545 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
3546 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
3547 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
3548 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
3550 WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4));
3551 WARN_ON(!(sh_per_se == 1 || sh_per_se == 2));
3552 WARN_ON(!(rb_per_pkr == 1 || rb_per_pkr == 2));
3554 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
3555 (!se_mask[2] && !se_mask[3]))) {
3556 raster_config_1 &= ~SE_PAIR_MAP_MASK;
3558 if (!se_mask[0] && !se_mask[1]) {
3560 SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_3);
3563 SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_0);
3567 for (se = 0; se < num_se; se++) {
3568 unsigned raster_config_se = raster_config;
3569 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
3570 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
3571 int idx = (se / 2) * 2;
3573 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
3574 raster_config_se &= ~SE_MAP_MASK;
3576 if (!se_mask[idx]) {
3577 raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_3);
3579 raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_0);
3583 pkr0_mask &= rb_mask;
3584 pkr1_mask &= rb_mask;
3585 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
3586 raster_config_se &= ~PKR_MAP_MASK;
3589 raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_3);
3591 raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_0);
3595 if (rb_per_se >= 2) {
3596 unsigned rb0_mask = 1 << (se * rb_per_se);
3597 unsigned rb1_mask = rb0_mask << 1;
3599 rb0_mask &= rb_mask;
3600 rb1_mask &= rb_mask;
3601 if (!rb0_mask || !rb1_mask) {
3602 raster_config_se &= ~RB_MAP_PKR0_MASK;
3606 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_3);
3609 RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_0);
3613 if (rb_per_se > 2) {
3614 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
3615 rb1_mask = rb0_mask << 1;
3616 rb0_mask &= rb_mask;
3617 rb1_mask &= rb_mask;
3618 if (!rb0_mask || !rb1_mask) {
3619 raster_config_se &= ~RB_MAP_PKR1_MASK;
3623 RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_3);
3626 RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_0);
3632 /* GRBM_GFX_INDEX has a different offset on VI */
3633 gfx_v8_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff);
3634 WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se);
3635 WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1);
3638 /* GRBM_GFX_INDEX has a different offset on VI */
3639 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3642 static void gfx_v8_0_setup_rb(struct amdgpu_device *adev)
3646 u32 raster_config = 0, raster_config_1 = 0;
3648 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
3649 adev->gfx.config.max_sh_per_se;
3650 unsigned num_rb_pipes;
3652 mutex_lock(&adev->grbm_idx_mutex);
3653 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3654 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3655 gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff);
3656 data = gfx_v8_0_get_rb_active_bitmap(adev);
3657 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
3658 rb_bitmap_width_per_sh);
3661 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3663 adev->gfx.config.backend_enable_mask = active_rbs;
3664 adev->gfx.config.num_rbs = hweight32(active_rbs);
3666 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se *
3667 adev->gfx.config.max_shader_engines, 16);
3669 gfx_v8_0_raster_config(adev, &raster_config, &raster_config_1);
3671 if (!adev->gfx.config.backend_enable_mask ||
3672 adev->gfx.config.num_rbs >= num_rb_pipes) {
3673 WREG32(mmPA_SC_RASTER_CONFIG, raster_config);
3674 WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1);
3676 gfx_v8_0_write_harvested_raster_configs(adev, raster_config, raster_config_1,
3677 adev->gfx.config.backend_enable_mask,
3681 /* cache the values for userspace */
3682 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3683 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3684 gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff);
3685 adev->gfx.config.rb_config[i][j].rb_backend_disable =
3686 RREG32(mmCC_RB_BACKEND_DISABLE);
3687 adev->gfx.config.rb_config[i][j].user_rb_backend_disable =
3688 RREG32(mmGC_USER_RB_BACKEND_DISABLE);
3689 adev->gfx.config.rb_config[i][j].raster_config =
3690 RREG32(mmPA_SC_RASTER_CONFIG);
3691 adev->gfx.config.rb_config[i][j].raster_config_1 =
3692 RREG32(mmPA_SC_RASTER_CONFIG_1);
3695 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3696 mutex_unlock(&adev->grbm_idx_mutex);
3700 * gfx_v8_0_init_compute_vmid - gart enable
3702 * @adev: amdgpu_device pointer
3704 * Initialize compute vmid sh_mem registers
3707 #define DEFAULT_SH_MEM_BASES (0x6000)
3708 #define FIRST_COMPUTE_VMID (8)
3709 #define LAST_COMPUTE_VMID (16)
3710 static void gfx_v8_0_init_compute_vmid(struct amdgpu_device *adev)
3713 uint32_t sh_mem_config;
3714 uint32_t sh_mem_bases;
3717 * Configure apertures:
3718 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
3719 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
3720 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
3722 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
3724 sh_mem_config = SH_MEM_ADDRESS_MODE_HSA64 <<
3725 SH_MEM_CONFIG__ADDRESS_MODE__SHIFT |
3726 SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
3727 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT |
3728 MTYPE_CC << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT |
3729 SH_MEM_CONFIG__PRIVATE_ATC_MASK;
3731 mutex_lock(&adev->srbm_mutex);
3732 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
3733 vi_srbm_select(adev, 0, 0, 0, i);
3734 /* CP and shaders */
3735 WREG32(mmSH_MEM_CONFIG, sh_mem_config);
3736 WREG32(mmSH_MEM_APE1_BASE, 1);
3737 WREG32(mmSH_MEM_APE1_LIMIT, 0);
3738 WREG32(mmSH_MEM_BASES, sh_mem_bases);
3740 vi_srbm_select(adev, 0, 0, 0, 0);
3741 mutex_unlock(&adev->srbm_mutex);
3744 static void gfx_v8_0_init_gds_vmid(struct amdgpu_device *adev)
3749 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
3750 * access. Compute VMIDs should be enabled by FW for target VMIDs,
3751 * the driver can enable them for graphics. VMID0 should maintain
3752 * access so that HWS firmware can save/restore entries.
3754 for (vmid = 1; vmid < 16; vmid++) {
3755 WREG32(amdgpu_gds_reg_offset[vmid].mem_base, 0);
3756 WREG32(amdgpu_gds_reg_offset[vmid].mem_size, 0);
3757 WREG32(amdgpu_gds_reg_offset[vmid].gws, 0);
3758 WREG32(amdgpu_gds_reg_offset[vmid].oa, 0);
3762 static void gfx_v8_0_config_init(struct amdgpu_device *adev)
3764 switch (adev->asic_type) {
3766 adev->gfx.config.double_offchip_lds_buf = 1;
3770 adev->gfx.config.double_offchip_lds_buf = 0;
3775 static void gfx_v8_0_constants_init(struct amdgpu_device *adev)
3777 u32 tmp, sh_static_mem_cfg;
3780 WREG32_FIELD(GRBM_CNTL, READ_TIMEOUT, 0xFF);
3781 WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
3782 WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
3783 WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config);
3785 gfx_v8_0_tiling_mode_table_init(adev);
3786 gfx_v8_0_setup_rb(adev);
3787 gfx_v8_0_get_cu_info(adev);
3788 gfx_v8_0_config_init(adev);
3790 /* XXX SH_MEM regs */
3791 /* where to put LDS, scratch, GPUVM in FSA64 space */
3792 sh_static_mem_cfg = REG_SET_FIELD(0, SH_STATIC_MEM_CONFIG,
3794 sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG,
3796 sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG,
3798 WREG32(mmSH_STATIC_MEM_CONFIG, sh_static_mem_cfg);
3800 mutex_lock(&adev->srbm_mutex);
3801 for (i = 0; i < adev->vm_manager.id_mgr[0].num_ids; i++) {
3802 vi_srbm_select(adev, 0, 0, 0, i);
3803 /* CP and shaders */
3805 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_UC);
3806 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC);
3807 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
3808 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
3809 WREG32(mmSH_MEM_CONFIG, tmp);
3810 WREG32(mmSH_MEM_BASES, 0);
3812 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_NC);
3813 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC);
3814 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
3815 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
3816 WREG32(mmSH_MEM_CONFIG, tmp);
3817 tmp = adev->gmc.shared_aperture_start >> 48;
3818 WREG32(mmSH_MEM_BASES, tmp);
3821 WREG32(mmSH_MEM_APE1_BASE, 1);
3822 WREG32(mmSH_MEM_APE1_LIMIT, 0);
3824 vi_srbm_select(adev, 0, 0, 0, 0);
3825 mutex_unlock(&adev->srbm_mutex);
3827 gfx_v8_0_init_compute_vmid(adev);
3828 gfx_v8_0_init_gds_vmid(adev);
3830 mutex_lock(&adev->grbm_idx_mutex);
3832 * making sure that the following register writes will be broadcasted
3833 * to all the shaders
3835 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3837 WREG32(mmPA_SC_FIFO_SIZE,
3838 (adev->gfx.config.sc_prim_fifo_size_frontend <<
3839 PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
3840 (adev->gfx.config.sc_prim_fifo_size_backend <<
3841 PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
3842 (adev->gfx.config.sc_hiz_tile_fifo_size <<
3843 PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
3844 (adev->gfx.config.sc_earlyz_tile_fifo_size <<
3845 PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT));
3847 tmp = RREG32(mmSPI_ARB_PRIORITY);
3848 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS0, 2);
3849 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS1, 2);
3850 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS2, 2);
3851 tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS3, 2);
3852 WREG32(mmSPI_ARB_PRIORITY, tmp);
3854 mutex_unlock(&adev->grbm_idx_mutex);
3858 static void gfx_v8_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
3863 mutex_lock(&adev->grbm_idx_mutex);
3864 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3865 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3866 gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff);
3867 for (k = 0; k < adev->usec_timeout; k++) {
3868 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0)
3872 if (k == adev->usec_timeout) {
3873 gfx_v8_0_select_se_sh(adev, 0xffffffff,
3874 0xffffffff, 0xffffffff);
3875 mutex_unlock(&adev->grbm_idx_mutex);
3876 DRM_INFO("Timeout wait for RLC serdes %u,%u\n",
3882 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3883 mutex_unlock(&adev->grbm_idx_mutex);
3885 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
3886 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
3887 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
3888 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
3889 for (k = 0; k < adev->usec_timeout; k++) {
3890 if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
3896 static void gfx_v8_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
3899 u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
3901 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
3902 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
3903 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
3904 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);
3906 WREG32(mmCP_INT_CNTL_RING0, tmp);
3909 static void gfx_v8_0_init_csb(struct amdgpu_device *adev)
3912 WREG32(mmRLC_CSIB_ADDR_HI,
3913 adev->gfx.rlc.clear_state_gpu_addr >> 32);
3914 WREG32(mmRLC_CSIB_ADDR_LO,
3915 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
3916 WREG32(mmRLC_CSIB_LENGTH,
3917 adev->gfx.rlc.clear_state_size);
3920 static void gfx_v8_0_parse_ind_reg_list(int *register_list_format,
3923 int *unique_indices,
3926 int *ind_start_offsets,
3931 bool new_entry = true;
3933 for (; ind_offset < list_size; ind_offset++) {
3937 ind_start_offsets[*offset_count] = ind_offset;
3938 *offset_count = *offset_count + 1;
3939 BUG_ON(*offset_count >= max_offset);
3942 if (register_list_format[ind_offset] == 0xFFFFFFFF) {
3949 /* look for the matching indice */
3951 indices < *indices_count;
3953 if (unique_indices[indices] ==
3954 register_list_format[ind_offset])
3958 if (indices >= *indices_count) {
3959 unique_indices[*indices_count] =
3960 register_list_format[ind_offset];
3961 indices = *indices_count;
3962 *indices_count = *indices_count + 1;
3963 BUG_ON(*indices_count >= max_indices);
3966 register_list_format[ind_offset] = indices;
3970 static int gfx_v8_0_init_save_restore_list(struct amdgpu_device *adev)
3973 int unique_indices[] = {0, 0, 0, 0, 0, 0, 0, 0};
3974 int indices_count = 0;
3975 int indirect_start_offsets[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
3976 int offset_count = 0;
3979 unsigned int *register_list_format =
3980 kmemdup(adev->gfx.rlc.register_list_format,
3981 adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL);
3982 if (!register_list_format)
3985 gfx_v8_0_parse_ind_reg_list(register_list_format,
3986 RLC_FormatDirectRegListLength,
3987 adev->gfx.rlc.reg_list_format_size_bytes >> 2,
3990 ARRAY_SIZE(unique_indices),
3991 indirect_start_offsets,
3993 ARRAY_SIZE(indirect_start_offsets));
3995 /* save and restore list */
3996 WREG32_FIELD(RLC_SRM_CNTL, AUTO_INCR_ADDR, 1);
3998 WREG32(mmRLC_SRM_ARAM_ADDR, 0);
3999 for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++)
4000 WREG32(mmRLC_SRM_ARAM_DATA, adev->gfx.rlc.register_restore[i]);
4003 WREG32(mmRLC_GPM_SCRATCH_ADDR, adev->gfx.rlc.reg_list_format_start);
4004 for (i = 0; i < adev->gfx.rlc.reg_list_format_size_bytes >> 2; i++)
4005 WREG32(mmRLC_GPM_SCRATCH_DATA, register_list_format[i]);
4007 list_size = adev->gfx.rlc.reg_list_size_bytes >> 2;
4008 list_size = list_size >> 1;
4009 WREG32(mmRLC_GPM_SCRATCH_ADDR, adev->gfx.rlc.reg_restore_list_size);
4010 WREG32(mmRLC_GPM_SCRATCH_DATA, list_size);
4012 /* starting offsets starts */
4013 WREG32(mmRLC_GPM_SCRATCH_ADDR,
4014 adev->gfx.rlc.starting_offsets_start);
4015 for (i = 0; i < ARRAY_SIZE(indirect_start_offsets); i++)
4016 WREG32(mmRLC_GPM_SCRATCH_DATA,
4017 indirect_start_offsets[i]);
4019 /* unique indices */
4020 temp = mmRLC_SRM_INDEX_CNTL_ADDR_0;
4021 data = mmRLC_SRM_INDEX_CNTL_DATA_0;
4022 for (i = 0; i < ARRAY_SIZE(unique_indices); i++) {
4023 if (unique_indices[i] != 0) {
4024 WREG32(temp + i, unique_indices[i] & 0x3FFFF);
4025 WREG32(data + i, unique_indices[i] >> 20);
4028 kfree(register_list_format);
4033 static void gfx_v8_0_enable_save_restore_machine(struct amdgpu_device *adev)
4035 WREG32_FIELD(RLC_SRM_CNTL, SRM_ENABLE, 1);
4038 static void gfx_v8_0_init_power_gating(struct amdgpu_device *adev)
4042 WREG32_FIELD(CP_RB_WPTR_POLL_CNTL, IDLE_POLL_COUNT, 0x60);
4044 data = REG_SET_FIELD(0, RLC_PG_DELAY, POWER_UP_DELAY, 0x10);
4045 data = REG_SET_FIELD(data, RLC_PG_DELAY, POWER_DOWN_DELAY, 0x10);
4046 data = REG_SET_FIELD(data, RLC_PG_DELAY, CMD_PROPAGATE_DELAY, 0x10);
4047 data = REG_SET_FIELD(data, RLC_PG_DELAY, MEM_SLEEP_DELAY, 0x10);
4048 WREG32(mmRLC_PG_DELAY, data);
4050 WREG32_FIELD(RLC_PG_DELAY_2, SERDES_CMD_DELAY, 0x3);
4051 WREG32_FIELD(RLC_AUTO_PG_CTRL, GRBM_REG_SAVE_GFX_IDLE_THRESHOLD, 0x55f0);
4055 static void cz_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev,
4058 WREG32_FIELD(RLC_PG_CNTL, SMU_CLK_SLOWDOWN_ON_PU_ENABLE, enable ? 1 : 0);
4061 static void cz_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev,
4064 WREG32_FIELD(RLC_PG_CNTL, SMU_CLK_SLOWDOWN_ON_PD_ENABLE, enable ? 1 : 0);
4067 static void cz_enable_cp_power_gating(struct amdgpu_device *adev, bool enable)
4069 WREG32_FIELD(RLC_PG_CNTL, CP_PG_DISABLE, enable ? 0 : 1);
4072 static void gfx_v8_0_init_pg(struct amdgpu_device *adev)
4074 if ((adev->asic_type == CHIP_CARRIZO) ||
4075 (adev->asic_type == CHIP_STONEY)) {
4076 gfx_v8_0_init_csb(adev);
4077 gfx_v8_0_init_save_restore_list(adev);
4078 gfx_v8_0_enable_save_restore_machine(adev);
4079 WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8);
4080 gfx_v8_0_init_power_gating(adev);
4081 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask);
4082 } else if ((adev->asic_type == CHIP_POLARIS11) ||
4083 (adev->asic_type == CHIP_POLARIS12) ||
4084 (adev->asic_type == CHIP_VEGAM)) {
4085 gfx_v8_0_init_csb(adev);
4086 gfx_v8_0_init_save_restore_list(adev);
4087 gfx_v8_0_enable_save_restore_machine(adev);
4088 gfx_v8_0_init_power_gating(adev);
4093 static void gfx_v8_0_rlc_stop(struct amdgpu_device *adev)
4095 WREG32_FIELD(RLC_CNTL, RLC_ENABLE_F32, 0);
4097 gfx_v8_0_enable_gui_idle_interrupt(adev, false);
4098 gfx_v8_0_wait_for_rlc_serdes(adev);
4101 static void gfx_v8_0_rlc_reset(struct amdgpu_device *adev)
4103 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
4106 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
4110 static void gfx_v8_0_rlc_start(struct amdgpu_device *adev)
4112 WREG32_FIELD(RLC_CNTL, RLC_ENABLE_F32, 1);
4114 /* carrizo do enable cp interrupt after cp inited */
4115 if (!(adev->flags & AMD_IS_APU))
4116 gfx_v8_0_enable_gui_idle_interrupt(adev, true);
4121 static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev)
4123 if (amdgpu_sriov_vf(adev)) {
4124 gfx_v8_0_init_csb(adev);
4128 adev->gfx.rlc.funcs->stop(adev);
4129 adev->gfx.rlc.funcs->reset(adev);
4130 gfx_v8_0_init_pg(adev);
4131 adev->gfx.rlc.funcs->start(adev);
4136 static void gfx_v8_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
4139 u32 tmp = RREG32(mmCP_ME_CNTL);
4142 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 0);
4143 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 0);
4144 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 0);
4146 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1);
4147 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1);
4148 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1);
4149 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4150 adev->gfx.gfx_ring[i].sched.ready = false;
4152 WREG32(mmCP_ME_CNTL, tmp);
4156 static u32 gfx_v8_0_get_csb_size(struct amdgpu_device *adev)
4159 const struct cs_section_def *sect = NULL;
4160 const struct cs_extent_def *ext = NULL;
4162 /* begin clear state */
4164 /* context control state */
4167 for (sect = vi_cs_data; sect->section != NULL; ++sect) {
4168 for (ext = sect->section; ext->extent != NULL; ++ext) {
4169 if (sect->id == SECT_CONTEXT)
4170 count += 2 + ext->reg_count;
4175 /* pa_sc_raster_config/pa_sc_raster_config1 */
4177 /* end clear state */
4185 static int gfx_v8_0_cp_gfx_start(struct amdgpu_device *adev)
4187 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
4188 const struct cs_section_def *sect = NULL;
4189 const struct cs_extent_def *ext = NULL;
4193 WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
4194 WREG32(mmCP_ENDIAN_SWAP, 0);
4195 WREG32(mmCP_DEVICE_ID, 1);
4197 gfx_v8_0_cp_gfx_enable(adev, true);
4199 r = amdgpu_ring_alloc(ring, gfx_v8_0_get_csb_size(adev) + 4);
4201 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
4205 /* clear state buffer */
4206 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4207 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
4209 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4210 amdgpu_ring_write(ring, 0x80000000);
4211 amdgpu_ring_write(ring, 0x80000000);
4213 for (sect = vi_cs_data; sect->section != NULL; ++sect) {
4214 for (ext = sect->section; ext->extent != NULL; ++ext) {
4215 if (sect->id == SECT_CONTEXT) {
4216 amdgpu_ring_write(ring,
4217 PACKET3(PACKET3_SET_CONTEXT_REG,
4219 amdgpu_ring_write(ring,
4220 ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
4221 for (i = 0; i < ext->reg_count; i++)
4222 amdgpu_ring_write(ring, ext->extent[i]);
4227 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
4228 amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
4229 amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config);
4230 amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config_1);
4232 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4233 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
4235 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
4236 amdgpu_ring_write(ring, 0);
4238 /* init the CE partitions */
4239 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
4240 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
4241 amdgpu_ring_write(ring, 0x8000);
4242 amdgpu_ring_write(ring, 0x8000);
4244 amdgpu_ring_commit(ring);
4248 static void gfx_v8_0_set_cpg_door_bell(struct amdgpu_device *adev, struct amdgpu_ring *ring)
4251 /* no gfx doorbells on iceland */
4252 if (adev->asic_type == CHIP_TOPAZ)
4255 tmp = RREG32(mmCP_RB_DOORBELL_CONTROL);
4257 if (ring->use_doorbell) {
4258 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
4259 DOORBELL_OFFSET, ring->doorbell_index);
4260 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
4262 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
4265 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0);
4268 WREG32(mmCP_RB_DOORBELL_CONTROL, tmp);
4270 if (adev->flags & AMD_IS_APU)
4273 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
4274 DOORBELL_RANGE_LOWER,
4275 adev->doorbell_index.gfx_ring0);
4276 WREG32(mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
4278 WREG32(mmCP_RB_DOORBELL_RANGE_UPPER,
4279 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
4282 static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device *adev)
4284 struct amdgpu_ring *ring;
4287 u64 rb_addr, rptr_addr, wptr_gpu_addr;
4289 /* Set the write pointer delay */
4290 WREG32(mmCP_RB_WPTR_DELAY, 0);
4292 /* set the RB to use vmid 0 */
4293 WREG32(mmCP_RB_VMID, 0);
4295 /* Set ring buffer size */
4296 ring = &adev->gfx.gfx_ring[0];
4297 rb_bufsz = order_base_2(ring->ring_size / 8);
4298 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
4299 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
4300 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MTYPE, 3);
4301 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MIN_IB_AVAILSZ, 1);
4303 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
4305 WREG32(mmCP_RB0_CNTL, tmp);
4307 /* Initialize the ring buffer's read and write pointers */
4308 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
4310 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
4312 /* set the wb address wether it's enabled or not */
4313 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
4314 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
4315 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
4317 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
4318 WREG32(mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr));
4319 WREG32(mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr));
4321 WREG32(mmCP_RB0_CNTL, tmp);
4323 rb_addr = ring->gpu_addr >> 8;
4324 WREG32(mmCP_RB0_BASE, rb_addr);
4325 WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
4327 gfx_v8_0_set_cpg_door_bell(adev, ring);
4328 /* start the ring */
4329 amdgpu_ring_clear_ring(ring);
4330 gfx_v8_0_cp_gfx_start(adev);
4331 ring->sched.ready = true;
4336 static void gfx_v8_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
4341 WREG32(mmCP_MEC_CNTL, 0);
4343 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
4344 for (i = 0; i < adev->gfx.num_compute_rings; i++)
4345 adev->gfx.compute_ring[i].sched.ready = false;
4346 adev->gfx.kiq.ring.sched.ready = false;
4352 static void gfx_v8_0_kiq_setting(struct amdgpu_ring *ring)
4355 struct amdgpu_device *adev = ring->adev;
4357 /* tell RLC which is KIQ queue */
4358 tmp = RREG32(mmRLC_CP_SCHEDULERS);
4360 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
4361 WREG32(mmRLC_CP_SCHEDULERS, tmp);
4363 WREG32(mmRLC_CP_SCHEDULERS, tmp);
4366 static int gfx_v8_0_kiq_kcq_enable(struct amdgpu_device *adev)
4368 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
4369 uint64_t queue_mask = 0;
4372 for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) {
4373 if (!test_bit(i, adev->gfx.mec.queue_bitmap))
4376 /* This situation may be hit in the future if a new HW
4377 * generation exposes more than 64 queues. If so, the
4378 * definition of queue_mask needs updating */
4379 if (WARN_ON(i >= (sizeof(queue_mask)*8))) {
4380 DRM_ERROR("Invalid KCQ enabled: %d\n", i);
4384 queue_mask |= (1ull << i);
4387 r = amdgpu_ring_alloc(kiq_ring, (8 * adev->gfx.num_compute_rings) + 8);
4389 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
4393 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
4394 amdgpu_ring_write(kiq_ring, 0); /* vmid_mask:0 queue_type:0 (KIQ) */
4395 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
4396 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
4397 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
4398 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
4399 amdgpu_ring_write(kiq_ring, 0); /* oac mask */
4400 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
4401 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4402 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
4403 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
4404 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
4407 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
4408 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
4409 amdgpu_ring_write(kiq_ring,
4410 PACKET3_MAP_QUEUES_NUM_QUEUES(1));
4411 amdgpu_ring_write(kiq_ring,
4412 PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index) |
4413 PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
4414 PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
4415 PACKET3_MAP_QUEUES_ME(ring->me == 1 ? 0 : 1)); /* doorbell */
4416 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
4417 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
4418 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
4419 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
4422 amdgpu_ring_commit(kiq_ring);
4427 static int gfx_v8_0_deactivate_hqd(struct amdgpu_device *adev, u32 req)
4431 if (RREG32(mmCP_HQD_ACTIVE) & CP_HQD_ACTIVE__ACTIVE_MASK) {
4432 WREG32_FIELD(CP_HQD_DEQUEUE_REQUEST, DEQUEUE_REQ, req);
4433 for (i = 0; i < adev->usec_timeout; i++) {
4434 if (!(RREG32(mmCP_HQD_ACTIVE) & CP_HQD_ACTIVE__ACTIVE_MASK))
4438 if (i == adev->usec_timeout)
4441 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 0);
4442 WREG32(mmCP_HQD_PQ_RPTR, 0);
4443 WREG32(mmCP_HQD_PQ_WPTR, 0);
4448 static int gfx_v8_0_mqd_init(struct amdgpu_ring *ring)
4450 struct amdgpu_device *adev = ring->adev;
4451 struct vi_mqd *mqd = ring->mqd_ptr;
4452 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
4455 mqd->header = 0xC0310800;
4456 mqd->compute_pipelinestat_enable = 0x00000001;
4457 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
4458 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
4459 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
4460 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
4461 mqd->compute_misc_reserved = 0x00000003;
4462 mqd->dynamic_cu_mask_addr_lo = lower_32_bits(ring->mqd_gpu_addr
4463 + offsetof(struct vi_mqd_allocation, dynamic_cu_mask));
4464 mqd->dynamic_cu_mask_addr_hi = upper_32_bits(ring->mqd_gpu_addr
4465 + offsetof(struct vi_mqd_allocation, dynamic_cu_mask));
4466 eop_base_addr = ring->eop_gpu_addr >> 8;
4467 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
4468 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
4470 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
4471 tmp = RREG32(mmCP_HQD_EOP_CONTROL);
4472 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
4473 (order_base_2(GFX8_MEC_HPD_SIZE / 4) - 1));
4475 mqd->cp_hqd_eop_control = tmp;
4477 /* enable doorbell? */
4478 tmp = REG_SET_FIELD(RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL),
4479 CP_HQD_PQ_DOORBELL_CONTROL,
4481 ring->use_doorbell ? 1 : 0);
4483 mqd->cp_hqd_pq_doorbell_control = tmp;
4485 /* set the pointer to the MQD */
4486 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
4487 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
4489 /* set MQD vmid to 0 */
4490 tmp = RREG32(mmCP_MQD_CONTROL);
4491 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
4492 mqd->cp_mqd_control = tmp;
4494 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
4495 hqd_gpu_addr = ring->gpu_addr >> 8;
4496 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
4497 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
4499 /* set up the HQD, this is similar to CP_RB0_CNTL */
4500 tmp = RREG32(mmCP_HQD_PQ_CONTROL);
4501 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
4502 (order_base_2(ring->ring_size / 4) - 1));
4503 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
4504 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
4506 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
4508 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
4509 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
4510 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
4511 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
4512 mqd->cp_hqd_pq_control = tmp;
4514 /* set the wb address whether it's enabled or not */
4515 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
4516 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
4517 mqd->cp_hqd_pq_rptr_report_addr_hi =
4518 upper_32_bits(wb_gpu_addr) & 0xffff;
4520 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
4521 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
4522 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
4523 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
4526 /* enable the doorbell if requested */
4527 if (ring->use_doorbell) {
4528 tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
4529 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
4530 DOORBELL_OFFSET, ring->doorbell_index);
4532 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
4534 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
4535 DOORBELL_SOURCE, 0);
4536 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
4540 mqd->cp_hqd_pq_doorbell_control = tmp;
4542 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
4544 mqd->cp_hqd_pq_wptr = ring->wptr;
4545 mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
4547 /* set the vmid for the queue */
4548 mqd->cp_hqd_vmid = 0;
4550 tmp = RREG32(mmCP_HQD_PERSISTENT_STATE);
4551 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
4552 mqd->cp_hqd_persistent_state = tmp;
4555 tmp = RREG32(mmCP_HQD_IB_CONTROL);
4556 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
4557 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MTYPE, 3);
4558 mqd->cp_hqd_ib_control = tmp;
4560 tmp = RREG32(mmCP_HQD_IQ_TIMER);
4561 tmp = REG_SET_FIELD(tmp, CP_HQD_IQ_TIMER, MTYPE, 3);
4562 mqd->cp_hqd_iq_timer = tmp;
4564 tmp = RREG32(mmCP_HQD_CTX_SAVE_CONTROL);
4565 tmp = REG_SET_FIELD(tmp, CP_HQD_CTX_SAVE_CONTROL, MTYPE, 3);
4566 mqd->cp_hqd_ctx_save_control = tmp;
4569 mqd->cp_hqd_eop_rptr = RREG32(mmCP_HQD_EOP_RPTR);
4570 mqd->cp_hqd_eop_wptr = RREG32(mmCP_HQD_EOP_WPTR);
4571 mqd->cp_hqd_pipe_priority = RREG32(mmCP_HQD_PIPE_PRIORITY);
4572 mqd->cp_hqd_queue_priority = RREG32(mmCP_HQD_QUEUE_PRIORITY);
4573 mqd->cp_hqd_quantum = RREG32(mmCP_HQD_QUANTUM);
4574 mqd->cp_hqd_ctx_save_base_addr_lo = RREG32(mmCP_HQD_CTX_SAVE_BASE_ADDR_LO);
4575 mqd->cp_hqd_ctx_save_base_addr_hi = RREG32(mmCP_HQD_CTX_SAVE_BASE_ADDR_HI);
4576 mqd->cp_hqd_cntl_stack_offset = RREG32(mmCP_HQD_CNTL_STACK_OFFSET);
4577 mqd->cp_hqd_cntl_stack_size = RREG32(mmCP_HQD_CNTL_STACK_SIZE);
4578 mqd->cp_hqd_wg_state_offset = RREG32(mmCP_HQD_WG_STATE_OFFSET);
4579 mqd->cp_hqd_ctx_save_size = RREG32(mmCP_HQD_CTX_SAVE_SIZE);
4580 mqd->cp_hqd_eop_done_events = RREG32(mmCP_HQD_EOP_EVENTS);
4581 mqd->cp_hqd_error = RREG32(mmCP_HQD_ERROR);
4582 mqd->cp_hqd_eop_wptr_mem = RREG32(mmCP_HQD_EOP_WPTR_MEM);
4583 mqd->cp_hqd_eop_dones = RREG32(mmCP_HQD_EOP_DONES);
4585 /* activate the queue */
4586 mqd->cp_hqd_active = 1;
4591 int gfx_v8_0_mqd_commit(struct amdgpu_device *adev,
4597 /* HQD registers extend from mmCP_MQD_BASE_ADDR to mmCP_HQD_ERROR */
4598 mqd_data = &mqd->cp_mqd_base_addr_lo;
4600 /* disable wptr polling */
4601 WREG32_FIELD(CP_PQ_WPTR_POLL_CNTL, EN, 0);
4603 /* program all HQD registers */
4604 for (mqd_reg = mmCP_HQD_VMID; mqd_reg <= mmCP_HQD_EOP_CONTROL; mqd_reg++)
4605 WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]);
4607 /* Tonga errata: EOP RPTR/WPTR should be left unmodified.
4608 * This is safe since EOP RPTR==WPTR for any inactive HQD
4609 * on ASICs that do not support context-save.
4610 * EOP writes/reads can start anywhere in the ring.
4612 if (adev->asic_type != CHIP_TONGA) {
4613 WREG32(mmCP_HQD_EOP_RPTR, mqd->cp_hqd_eop_rptr);
4614 WREG32(mmCP_HQD_EOP_WPTR, mqd->cp_hqd_eop_wptr);
4615 WREG32(mmCP_HQD_EOP_WPTR_MEM, mqd->cp_hqd_eop_wptr_mem);
4618 for (mqd_reg = mmCP_HQD_EOP_EVENTS; mqd_reg <= mmCP_HQD_ERROR; mqd_reg++)
4619 WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]);
4621 /* activate the HQD */
4622 for (mqd_reg = mmCP_MQD_BASE_ADDR; mqd_reg <= mmCP_HQD_ACTIVE; mqd_reg++)
4623 WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]);
4628 static int gfx_v8_0_kiq_init_queue(struct amdgpu_ring *ring)
4630 struct amdgpu_device *adev = ring->adev;
4631 struct vi_mqd *mqd = ring->mqd_ptr;
4632 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
4634 gfx_v8_0_kiq_setting(ring);
4636 if (adev->in_gpu_reset) { /* for GPU_RESET case */
4637 /* reset MQD to a clean status */
4638 if (adev->gfx.mec.mqd_backup[mqd_idx])
4639 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct vi_mqd_allocation));
4641 /* reset ring buffer */
4643 amdgpu_ring_clear_ring(ring);
4644 mutex_lock(&adev->srbm_mutex);
4645 vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
4646 gfx_v8_0_mqd_commit(adev, mqd);
4647 vi_srbm_select(adev, 0, 0, 0, 0);
4648 mutex_unlock(&adev->srbm_mutex);
4650 memset((void *)mqd, 0, sizeof(struct vi_mqd_allocation));
4651 ((struct vi_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
4652 ((struct vi_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
4653 mutex_lock(&adev->srbm_mutex);
4654 vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
4655 gfx_v8_0_mqd_init(ring);
4656 gfx_v8_0_mqd_commit(adev, mqd);
4657 vi_srbm_select(adev, 0, 0, 0, 0);
4658 mutex_unlock(&adev->srbm_mutex);
4660 if (adev->gfx.mec.mqd_backup[mqd_idx])
4661 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct vi_mqd_allocation));
4667 static int gfx_v8_0_kcq_init_queue(struct amdgpu_ring *ring)
4669 struct amdgpu_device *adev = ring->adev;
4670 struct vi_mqd *mqd = ring->mqd_ptr;
4671 int mqd_idx = ring - &adev->gfx.compute_ring[0];
4673 if (!adev->in_gpu_reset && !adev->in_suspend) {
4674 memset((void *)mqd, 0, sizeof(struct vi_mqd_allocation));
4675 ((struct vi_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
4676 ((struct vi_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
4677 mutex_lock(&adev->srbm_mutex);
4678 vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
4679 gfx_v8_0_mqd_init(ring);
4680 vi_srbm_select(adev, 0, 0, 0, 0);
4681 mutex_unlock(&adev->srbm_mutex);
4683 if (adev->gfx.mec.mqd_backup[mqd_idx])
4684 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct vi_mqd_allocation));
4685 } else if (adev->in_gpu_reset) { /* for GPU_RESET case */
4686 /* reset MQD to a clean status */
4687 if (adev->gfx.mec.mqd_backup[mqd_idx])
4688 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct vi_mqd_allocation));
4689 /* reset ring buffer */
4691 amdgpu_ring_clear_ring(ring);
4693 amdgpu_ring_clear_ring(ring);
4698 static void gfx_v8_0_set_mec_doorbell_range(struct amdgpu_device *adev)
4700 if (adev->asic_type > CHIP_TONGA) {
4701 WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER, adev->doorbell_index.kiq << 2);
4702 WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER, adev->doorbell_index.mec_ring7 << 2);
4704 /* enable doorbells */
4705 WREG32_FIELD(CP_PQ_STATUS, DOORBELL_ENABLE, 1);
4708 static int gfx_v8_0_kiq_resume(struct amdgpu_device *adev)
4710 struct amdgpu_ring *ring;
4713 ring = &adev->gfx.kiq.ring;
4715 r = amdgpu_bo_reserve(ring->mqd_obj, false);
4716 if (unlikely(r != 0))
4719 r = amdgpu_bo_kmap(ring->mqd_obj, &ring->mqd_ptr);
4720 if (unlikely(r != 0))
4723 gfx_v8_0_kiq_init_queue(ring);
4724 amdgpu_bo_kunmap(ring->mqd_obj);
4725 ring->mqd_ptr = NULL;
4726 amdgpu_bo_unreserve(ring->mqd_obj);
4727 ring->sched.ready = true;
4731 static int gfx_v8_0_kcq_resume(struct amdgpu_device *adev)
4733 struct amdgpu_ring *ring = NULL;
4736 gfx_v8_0_cp_compute_enable(adev, true);
4738 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4739 ring = &adev->gfx.compute_ring[i];
4741 r = amdgpu_bo_reserve(ring->mqd_obj, false);
4742 if (unlikely(r != 0))
4744 r = amdgpu_bo_kmap(ring->mqd_obj, &ring->mqd_ptr);
4746 r = gfx_v8_0_kcq_init_queue(ring);
4747 amdgpu_bo_kunmap(ring->mqd_obj);
4748 ring->mqd_ptr = NULL;
4750 amdgpu_bo_unreserve(ring->mqd_obj);
4755 gfx_v8_0_set_mec_doorbell_range(adev);
4757 r = gfx_v8_0_kiq_kcq_enable(adev);
4765 static int gfx_v8_0_cp_test_all_rings(struct amdgpu_device *adev)
4768 struct amdgpu_ring *ring;
4770 /* collect all the ring_tests here, gfx, kiq, compute */
4771 ring = &adev->gfx.gfx_ring[0];
4772 r = amdgpu_ring_test_helper(ring);
4776 ring = &adev->gfx.kiq.ring;
4777 r = amdgpu_ring_test_helper(ring);
4781 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4782 ring = &adev->gfx.compute_ring[i];
4783 amdgpu_ring_test_helper(ring);
4789 static int gfx_v8_0_cp_resume(struct amdgpu_device *adev)
4793 if (!(adev->flags & AMD_IS_APU))
4794 gfx_v8_0_enable_gui_idle_interrupt(adev, false);
4796 r = gfx_v8_0_kiq_resume(adev);
4800 r = gfx_v8_0_cp_gfx_resume(adev);
4804 r = gfx_v8_0_kcq_resume(adev);
4808 r = gfx_v8_0_cp_test_all_rings(adev);
4812 gfx_v8_0_enable_gui_idle_interrupt(adev, true);
4817 static void gfx_v8_0_cp_enable(struct amdgpu_device *adev, bool enable)
4819 gfx_v8_0_cp_gfx_enable(adev, enable);
4820 gfx_v8_0_cp_compute_enable(adev, enable);
4823 static int gfx_v8_0_hw_init(void *handle)
4826 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4828 gfx_v8_0_init_golden_registers(adev);
4829 gfx_v8_0_constants_init(adev);
4831 r = gfx_v8_0_csb_vram_pin(adev);
4835 r = adev->gfx.rlc.funcs->resume(adev);
4839 r = gfx_v8_0_cp_resume(adev);
4844 static int gfx_v8_0_kcq_disable(struct amdgpu_device *adev)
4847 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
4849 r = amdgpu_ring_alloc(kiq_ring, 6 * adev->gfx.num_compute_rings);
4851 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
4853 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4854 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
4856 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
4857 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
4858 PACKET3_UNMAP_QUEUES_ACTION(1) | /* RESET_QUEUES */
4859 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
4860 PACKET3_UNMAP_QUEUES_ENGINE_SEL(0) |
4861 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
4862 amdgpu_ring_write(kiq_ring, PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
4863 amdgpu_ring_write(kiq_ring, 0);
4864 amdgpu_ring_write(kiq_ring, 0);
4865 amdgpu_ring_write(kiq_ring, 0);
4867 r = amdgpu_ring_test_helper(kiq_ring);
4869 DRM_ERROR("KCQ disable failed\n");
4874 static bool gfx_v8_0_is_idle(void *handle)
4876 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4878 if (REG_GET_FIELD(RREG32(mmGRBM_STATUS), GRBM_STATUS, GUI_ACTIVE)
4879 || RREG32(mmGRBM_STATUS2) != 0x8)
4885 static bool gfx_v8_0_rlc_is_idle(void *handle)
4887 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4889 if (RREG32(mmGRBM_STATUS2) != 0x8)
4895 static int gfx_v8_0_wait_for_rlc_idle(void *handle)
4898 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4900 for (i = 0; i < adev->usec_timeout; i++) {
4901 if (gfx_v8_0_rlc_is_idle(handle))
4909 static int gfx_v8_0_wait_for_idle(void *handle)
4912 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4914 for (i = 0; i < adev->usec_timeout; i++) {
4915 if (gfx_v8_0_is_idle(handle))
4923 static int gfx_v8_0_hw_fini(void *handle)
4925 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4927 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
4928 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
4930 amdgpu_irq_put(adev, &adev->gfx.cp_ecc_error_irq, 0);
4932 amdgpu_irq_put(adev, &adev->gfx.sq_irq, 0);
4934 /* disable KCQ to avoid CPC touch memory not valid anymore */
4935 gfx_v8_0_kcq_disable(adev);
4937 if (amdgpu_sriov_vf(adev)) {
4938 pr_debug("For SRIOV client, shouldn't do anything.\n");
4941 amdgpu_gfx_rlc_enter_safe_mode(adev);
4942 if (!gfx_v8_0_wait_for_idle(adev))
4943 gfx_v8_0_cp_enable(adev, false);
4945 pr_err("cp is busy, skip halt cp\n");
4946 if (!gfx_v8_0_wait_for_rlc_idle(adev))
4947 adev->gfx.rlc.funcs->stop(adev);
4949 pr_err("rlc is busy, skip halt rlc\n");
4950 amdgpu_gfx_rlc_exit_safe_mode(adev);
4952 gfx_v8_0_csb_vram_unpin(adev);
4957 static int gfx_v8_0_suspend(void *handle)
4959 return gfx_v8_0_hw_fini(handle);
4962 static int gfx_v8_0_resume(void *handle)
4964 return gfx_v8_0_hw_init(handle);
4967 static bool gfx_v8_0_check_soft_reset(void *handle)
4969 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4970 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
4974 tmp = RREG32(mmGRBM_STATUS);
4975 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
4976 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
4977 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
4978 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
4979 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
4980 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK |
4981 GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
4982 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
4983 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
4984 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
4985 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
4986 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
4987 SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
4991 tmp = RREG32(mmGRBM_STATUS2);
4992 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
4993 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
4994 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
4996 if (REG_GET_FIELD(tmp, GRBM_STATUS2, CPF_BUSY) ||
4997 REG_GET_FIELD(tmp, GRBM_STATUS2, CPC_BUSY) ||
4998 REG_GET_FIELD(tmp, GRBM_STATUS2, CPG_BUSY)) {
4999 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
5001 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
5003 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
5005 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET,
5006 SOFT_RESET_GRBM, 1);
5010 tmp = RREG32(mmSRBM_STATUS);
5011 if (REG_GET_FIELD(tmp, SRBM_STATUS, GRBM_RQ_PENDING))
5012 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
5013 SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
5014 if (REG_GET_FIELD(tmp, SRBM_STATUS, SEM_BUSY))
5015 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
5016 SRBM_SOFT_RESET, SOFT_RESET_SEM, 1);
5018 if (grbm_soft_reset || srbm_soft_reset) {
5019 adev->gfx.grbm_soft_reset = grbm_soft_reset;
5020 adev->gfx.srbm_soft_reset = srbm_soft_reset;
5023 adev->gfx.grbm_soft_reset = 0;
5024 adev->gfx.srbm_soft_reset = 0;
5029 static int gfx_v8_0_pre_soft_reset(void *handle)
5031 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5032 u32 grbm_soft_reset = 0;
5034 if ((!adev->gfx.grbm_soft_reset) &&
5035 (!adev->gfx.srbm_soft_reset))
5038 grbm_soft_reset = adev->gfx.grbm_soft_reset;
5041 adev->gfx.rlc.funcs->stop(adev);
5043 if (REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP) ||
5044 REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_GFX))
5045 /* Disable GFX parsing/prefetching */
5046 gfx_v8_0_cp_gfx_enable(adev, false);
5048 if (REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP) ||
5049 REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPF) ||
5050 REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPC) ||
5051 REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPG)) {
5054 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
5055 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
5057 mutex_lock(&adev->srbm_mutex);
5058 vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
5059 gfx_v8_0_deactivate_hqd(adev, 2);
5060 vi_srbm_select(adev, 0, 0, 0, 0);
5061 mutex_unlock(&adev->srbm_mutex);
5063 /* Disable MEC parsing/prefetching */
5064 gfx_v8_0_cp_compute_enable(adev, false);
5070 static int gfx_v8_0_soft_reset(void *handle)
5072 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5073 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
5076 if ((!adev->gfx.grbm_soft_reset) &&
5077 (!adev->gfx.srbm_soft_reset))
5080 grbm_soft_reset = adev->gfx.grbm_soft_reset;
5081 srbm_soft_reset = adev->gfx.srbm_soft_reset;
5083 if (grbm_soft_reset || srbm_soft_reset) {
5084 tmp = RREG32(mmGMCON_DEBUG);
5085 tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_STALL, 1);
5086 tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_CLEAR, 1);
5087 WREG32(mmGMCON_DEBUG, tmp);
5091 if (grbm_soft_reset) {
5092 tmp = RREG32(mmGRBM_SOFT_RESET);
5093 tmp |= grbm_soft_reset;
5094 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
5095 WREG32(mmGRBM_SOFT_RESET, tmp);
5096 tmp = RREG32(mmGRBM_SOFT_RESET);
5100 tmp &= ~grbm_soft_reset;
5101 WREG32(mmGRBM_SOFT_RESET, tmp);
5102 tmp = RREG32(mmGRBM_SOFT_RESET);
5105 if (srbm_soft_reset) {
5106 tmp = RREG32(mmSRBM_SOFT_RESET);
5107 tmp |= srbm_soft_reset;
5108 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
5109 WREG32(mmSRBM_SOFT_RESET, tmp);
5110 tmp = RREG32(mmSRBM_SOFT_RESET);
5114 tmp &= ~srbm_soft_reset;
5115 WREG32(mmSRBM_SOFT_RESET, tmp);
5116 tmp = RREG32(mmSRBM_SOFT_RESET);
5119 if (grbm_soft_reset || srbm_soft_reset) {
5120 tmp = RREG32(mmGMCON_DEBUG);
5121 tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_STALL, 0);
5122 tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_CLEAR, 0);
5123 WREG32(mmGMCON_DEBUG, tmp);
5126 /* Wait a little for things to settle down */
5132 static int gfx_v8_0_post_soft_reset(void *handle)
5134 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5135 u32 grbm_soft_reset = 0;
5137 if ((!adev->gfx.grbm_soft_reset) &&
5138 (!adev->gfx.srbm_soft_reset))
5141 grbm_soft_reset = adev->gfx.grbm_soft_reset;
5143 if (REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP) ||
5144 REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPF) ||
5145 REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPC) ||
5146 REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPG)) {
5149 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
5150 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
5152 mutex_lock(&adev->srbm_mutex);
5153 vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
5154 gfx_v8_0_deactivate_hqd(adev, 2);
5155 vi_srbm_select(adev, 0, 0, 0, 0);
5156 mutex_unlock(&adev->srbm_mutex);
5158 gfx_v8_0_kiq_resume(adev);
5159 gfx_v8_0_kcq_resume(adev);
5162 if (REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP) ||
5163 REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_GFX))
5164 gfx_v8_0_cp_gfx_resume(adev);
5166 gfx_v8_0_cp_test_all_rings(adev);
5168 adev->gfx.rlc.funcs->start(adev);
5174 * gfx_v8_0_get_gpu_clock_counter - return GPU clock counter snapshot
5176 * @adev: amdgpu_device pointer
5178 * Fetches a GPU clock counter snapshot.
5179 * Returns the 64 bit clock counter snapshot.
5181 static uint64_t gfx_v8_0_get_gpu_clock_counter(struct amdgpu_device *adev)
5185 mutex_lock(&adev->gfx.gpu_clock_mutex);
5186 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
5187 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
5188 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
5189 mutex_unlock(&adev->gfx.gpu_clock_mutex);
5193 static void gfx_v8_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
5195 uint32_t gds_base, uint32_t gds_size,
5196 uint32_t gws_base, uint32_t gws_size,
5197 uint32_t oa_base, uint32_t oa_size)
5200 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5201 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5202 WRITE_DATA_DST_SEL(0)));
5203 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_base);
5204 amdgpu_ring_write(ring, 0);
5205 amdgpu_ring_write(ring, gds_base);
5208 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5209 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5210 WRITE_DATA_DST_SEL(0)));
5211 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_size);
5212 amdgpu_ring_write(ring, 0);
5213 amdgpu_ring_write(ring, gds_size);
5216 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5217 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5218 WRITE_DATA_DST_SEL(0)));
5219 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].gws);
5220 amdgpu_ring_write(ring, 0);
5221 amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
5224 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5225 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5226 WRITE_DATA_DST_SEL(0)));
5227 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].oa);
5228 amdgpu_ring_write(ring, 0);
5229 amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base));
5232 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
5234 WREG32(mmSQ_IND_INDEX,
5235 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
5236 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
5237 (address << SQ_IND_INDEX__INDEX__SHIFT) |
5238 (SQ_IND_INDEX__FORCE_READ_MASK));
5239 return RREG32(mmSQ_IND_DATA);
5242 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
5243 uint32_t wave, uint32_t thread,
5244 uint32_t regno, uint32_t num, uint32_t *out)
5246 WREG32(mmSQ_IND_INDEX,
5247 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
5248 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
5249 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
5250 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
5251 (SQ_IND_INDEX__FORCE_READ_MASK) |
5252 (SQ_IND_INDEX__AUTO_INCR_MASK));
5254 *(out++) = RREG32(mmSQ_IND_DATA);
5257 static void gfx_v8_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
5259 /* type 0 wave data */
5260 dst[(*no_fields)++] = 0;
5261 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
5262 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
5263 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
5264 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
5265 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
5266 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
5267 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
5268 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
5269 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
5270 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
5271 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
5272 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
5273 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO);
5274 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI);
5275 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO);
5276 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI);
5277 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
5278 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
5281 static void gfx_v8_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
5282 uint32_t wave, uint32_t start,
5283 uint32_t size, uint32_t *dst)
5286 adev, simd, wave, 0,
5287 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
5291 static const struct amdgpu_gfx_funcs gfx_v8_0_gfx_funcs = {
5292 .get_gpu_clock_counter = &gfx_v8_0_get_gpu_clock_counter,
5293 .select_se_sh = &gfx_v8_0_select_se_sh,
5294 .read_wave_data = &gfx_v8_0_read_wave_data,
5295 .read_wave_sgprs = &gfx_v8_0_read_wave_sgprs,
5296 .select_me_pipe_q = &gfx_v8_0_select_me_pipe_q
5299 static int gfx_v8_0_early_init(void *handle)
5301 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5303 adev->gfx.num_gfx_rings = GFX8_NUM_GFX_RINGS;
5304 adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS;
5305 adev->gfx.funcs = &gfx_v8_0_gfx_funcs;
5306 gfx_v8_0_set_ring_funcs(adev);
5307 gfx_v8_0_set_irq_funcs(adev);
5308 gfx_v8_0_set_gds_init(adev);
5309 gfx_v8_0_set_rlc_funcs(adev);
5314 static int gfx_v8_0_late_init(void *handle)
5316 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5319 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
5323 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
5327 /* requires IBs so do in late init after IB pool is initialized */
5328 r = gfx_v8_0_do_edc_gpr_workarounds(adev);
5332 r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0);
5334 DRM_ERROR("amdgpu_irq_get() failed to get IRQ for EDC, r: %d.\n", r);
5338 r = amdgpu_irq_get(adev, &adev->gfx.sq_irq, 0);
5341 "amdgpu_irq_get() failed to get IRQ for SQ, r: %d.\n",
5349 static void gfx_v8_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev,
5352 if (((adev->asic_type == CHIP_POLARIS11) ||
5353 (adev->asic_type == CHIP_POLARIS12) ||
5354 (adev->asic_type == CHIP_VEGAM)) &&
5355 adev->powerplay.pp_funcs->set_powergating_by_smu)
5356 /* Send msg to SMU via Powerplay */
5357 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, enable);
5359 WREG32_FIELD(RLC_PG_CNTL, STATIC_PER_CU_PG_ENABLE, enable ? 1 : 0);
5362 static void gfx_v8_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev,
5365 WREG32_FIELD(RLC_PG_CNTL, DYN_PER_CU_PG_ENABLE, enable ? 1 : 0);
5368 static void polaris11_enable_gfx_quick_mg_power_gating(struct amdgpu_device *adev,
5371 WREG32_FIELD(RLC_PG_CNTL, QUICK_PG_ENABLE, enable ? 1 : 0);
5374 static void cz_enable_gfx_cg_power_gating(struct amdgpu_device *adev,
5377 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_ENABLE, enable ? 1 : 0);
5380 static void cz_enable_gfx_pipeline_power_gating(struct amdgpu_device *adev,
5383 WREG32_FIELD(RLC_PG_CNTL, GFX_PIPELINE_PG_ENABLE, enable ? 1 : 0);
5385 /* Read any GFX register to wake up GFX. */
5387 RREG32(mmDB_RENDER_CONTROL);
5390 static void cz_update_gfx_cg_power_gating(struct amdgpu_device *adev,
5393 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) {
5394 cz_enable_gfx_cg_power_gating(adev, true);
5395 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE)
5396 cz_enable_gfx_pipeline_power_gating(adev, true);
5398 cz_enable_gfx_cg_power_gating(adev, false);
5399 cz_enable_gfx_pipeline_power_gating(adev, false);
5403 static int gfx_v8_0_set_powergating_state(void *handle,
5404 enum amd_powergating_state state)
5406 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5407 bool enable = (state == AMD_PG_STATE_GATE);
5409 if (amdgpu_sriov_vf(adev))
5412 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_SMG |
5413 AMD_PG_SUPPORT_RLC_SMU_HS |
5415 AMD_PG_SUPPORT_GFX_DMG))
5416 amdgpu_gfx_rlc_enter_safe_mode(adev);
5417 switch (adev->asic_type) {
5421 if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
5422 cz_enable_sck_slow_down_on_power_up(adev, true);
5423 cz_enable_sck_slow_down_on_power_down(adev, true);
5425 cz_enable_sck_slow_down_on_power_up(adev, false);
5426 cz_enable_sck_slow_down_on_power_down(adev, false);
5428 if (adev->pg_flags & AMD_PG_SUPPORT_CP)
5429 cz_enable_cp_power_gating(adev, true);
5431 cz_enable_cp_power_gating(adev, false);
5433 cz_update_gfx_cg_power_gating(adev, enable);
5435 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable)
5436 gfx_v8_0_enable_gfx_static_mg_power_gating(adev, true);
5438 gfx_v8_0_enable_gfx_static_mg_power_gating(adev, false);
5440 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable)
5441 gfx_v8_0_enable_gfx_dynamic_mg_power_gating(adev, true);
5443 gfx_v8_0_enable_gfx_dynamic_mg_power_gating(adev, false);
5445 case CHIP_POLARIS11:
5446 case CHIP_POLARIS12:
5448 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable)
5449 gfx_v8_0_enable_gfx_static_mg_power_gating(adev, true);
5451 gfx_v8_0_enable_gfx_static_mg_power_gating(adev, false);
5453 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable)
5454 gfx_v8_0_enable_gfx_dynamic_mg_power_gating(adev, true);
5456 gfx_v8_0_enable_gfx_dynamic_mg_power_gating(adev, false);
5458 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_QUICK_MG) && enable)
5459 polaris11_enable_gfx_quick_mg_power_gating(adev, true);
5461 polaris11_enable_gfx_quick_mg_power_gating(adev, false);
5466 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_SMG |
5467 AMD_PG_SUPPORT_RLC_SMU_HS |
5469 AMD_PG_SUPPORT_GFX_DMG))
5470 amdgpu_gfx_rlc_exit_safe_mode(adev);
5474 static void gfx_v8_0_get_clockgating_state(void *handle, u32 *flags)
5476 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5479 if (amdgpu_sriov_vf(adev))
5482 /* AMD_CG_SUPPORT_GFX_MGCG */
5483 data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
5484 if (!(data & RLC_CGTT_MGCG_OVERRIDE__CPF_MASK))
5485 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
5487 /* AMD_CG_SUPPORT_GFX_CGLG */
5488 data = RREG32(mmRLC_CGCG_CGLS_CTRL);
5489 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
5490 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
5492 /* AMD_CG_SUPPORT_GFX_CGLS */
5493 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
5494 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
5496 /* AMD_CG_SUPPORT_GFX_CGTS */
5497 data = RREG32(mmCGTS_SM_CTRL_REG);
5498 if (!(data & CGTS_SM_CTRL_REG__OVERRIDE_MASK))
5499 *flags |= AMD_CG_SUPPORT_GFX_CGTS;
5501 /* AMD_CG_SUPPORT_GFX_CGTS_LS */
5502 if (!(data & CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK))
5503 *flags |= AMD_CG_SUPPORT_GFX_CGTS_LS;
5505 /* AMD_CG_SUPPORT_GFX_RLC_LS */
5506 data = RREG32(mmRLC_MEM_SLP_CNTL);
5507 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
5508 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
5510 /* AMD_CG_SUPPORT_GFX_CP_LS */
5511 data = RREG32(mmCP_MEM_SLP_CNTL);
5512 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
5513 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
5516 static void gfx_v8_0_send_serdes_cmd(struct amdgpu_device *adev,
5517 uint32_t reg_addr, uint32_t cmd)
5521 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
5523 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
5524 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
5526 data = RREG32(mmRLC_SERDES_WR_CTRL);
5527 if (adev->asic_type == CHIP_STONEY)
5528 data &= ~(RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK |
5529 RLC_SERDES_WR_CTRL__READ_COMMAND_MASK |
5530 RLC_SERDES_WR_CTRL__P1_SELECT_MASK |
5531 RLC_SERDES_WR_CTRL__P2_SELECT_MASK |
5532 RLC_SERDES_WR_CTRL__RDDATA_RESET_MASK |
5533 RLC_SERDES_WR_CTRL__POWER_DOWN_MASK |
5534 RLC_SERDES_WR_CTRL__POWER_UP_MASK |
5535 RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK |
5536 RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK);
5538 data &= ~(RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK |
5539 RLC_SERDES_WR_CTRL__READ_COMMAND_MASK |
5540 RLC_SERDES_WR_CTRL__P1_SELECT_MASK |
5541 RLC_SERDES_WR_CTRL__P2_SELECT_MASK |
5542 RLC_SERDES_WR_CTRL__RDDATA_RESET_MASK |
5543 RLC_SERDES_WR_CTRL__POWER_DOWN_MASK |
5544 RLC_SERDES_WR_CTRL__POWER_UP_MASK |
5545 RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK |
5546 RLC_SERDES_WR_CTRL__BPM_DATA_MASK |
5547 RLC_SERDES_WR_CTRL__REG_ADDR_MASK |
5548 RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK);
5549 data |= (RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR_MASK |
5550 (cmd << RLC_SERDES_WR_CTRL__BPM_DATA__SHIFT) |
5551 (reg_addr << RLC_SERDES_WR_CTRL__REG_ADDR__SHIFT) |
5552 (0xff << RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT));
5554 WREG32(mmRLC_SERDES_WR_CTRL, data);
5557 #define MSG_ENTER_RLC_SAFE_MODE 1
5558 #define MSG_EXIT_RLC_SAFE_MODE 0
5559 #define RLC_GPR_REG2__REQ_MASK 0x00000001
5560 #define RLC_GPR_REG2__REQ__SHIFT 0
5561 #define RLC_GPR_REG2__MESSAGE__SHIFT 0x00000001
5562 #define RLC_GPR_REG2__MESSAGE_MASK 0x0000001e
5564 static bool gfx_v8_0_is_rlc_enabled(struct amdgpu_device *adev)
5566 uint32_t rlc_setting;
5568 rlc_setting = RREG32(mmRLC_CNTL);
5569 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
5575 static void gfx_v8_0_set_safe_mode(struct amdgpu_device *adev)
5579 data = RREG32(mmRLC_CNTL);
5580 data |= RLC_SAFE_MODE__CMD_MASK;
5581 data &= ~RLC_SAFE_MODE__MESSAGE_MASK;
5582 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
5583 WREG32(mmRLC_SAFE_MODE, data);
5585 /* wait for RLC_SAFE_MODE */
5586 for (i = 0; i < adev->usec_timeout; i++) {
5587 if ((RREG32(mmRLC_GPM_STAT) &
5588 (RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK |
5589 RLC_GPM_STAT__GFX_POWER_STATUS_MASK)) ==
5590 (RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK |
5591 RLC_GPM_STAT__GFX_POWER_STATUS_MASK))
5595 for (i = 0; i < adev->usec_timeout; i++) {
5596 if (!REG_GET_FIELD(RREG32(mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
5602 static void gfx_v8_0_unset_safe_mode(struct amdgpu_device *adev)
5607 data = RREG32(mmRLC_CNTL);
5608 data |= RLC_SAFE_MODE__CMD_MASK;
5609 data &= ~RLC_SAFE_MODE__MESSAGE_MASK;
5610 WREG32(mmRLC_SAFE_MODE, data);
5612 for (i = 0; i < adev->usec_timeout; i++) {
5613 if (!REG_GET_FIELD(RREG32(mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
5619 static const struct amdgpu_rlc_funcs iceland_rlc_funcs = {
5620 .is_rlc_enabled = gfx_v8_0_is_rlc_enabled,
5621 .set_safe_mode = gfx_v8_0_set_safe_mode,
5622 .unset_safe_mode = gfx_v8_0_unset_safe_mode,
5623 .init = gfx_v8_0_rlc_init,
5624 .get_csb_size = gfx_v8_0_get_csb_size,
5625 .get_csb_buffer = gfx_v8_0_get_csb_buffer,
5626 .get_cp_table_num = gfx_v8_0_cp_jump_table_num,
5627 .resume = gfx_v8_0_rlc_resume,
5628 .stop = gfx_v8_0_rlc_stop,
5629 .reset = gfx_v8_0_rlc_reset,
5630 .start = gfx_v8_0_rlc_start
5633 static void gfx_v8_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
5636 uint32_t temp, data;
5638 amdgpu_gfx_rlc_enter_safe_mode(adev);
5640 /* It is disabled by HW by default */
5641 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
5642 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
5643 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS)
5644 /* 1 - RLC memory Light sleep */
5645 WREG32_FIELD(RLC_MEM_SLP_CNTL, RLC_MEM_LS_EN, 1);
5647 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS)
5648 WREG32_FIELD(CP_MEM_SLP_CNTL, CP_MEM_LS_EN, 1);
5651 /* 3 - RLC_CGTT_MGCG_OVERRIDE */
5652 temp = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
5653 if (adev->flags & AMD_IS_APU)
5654 data &= ~(RLC_CGTT_MGCG_OVERRIDE__CPF_MASK |
5655 RLC_CGTT_MGCG_OVERRIDE__RLC_MASK |
5656 RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK);
5658 data &= ~(RLC_CGTT_MGCG_OVERRIDE__CPF_MASK |
5659 RLC_CGTT_MGCG_OVERRIDE__RLC_MASK |
5660 RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK |
5661 RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK);
5664 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
5666 /* 4 - wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5667 gfx_v8_0_wait_for_rlc_serdes(adev);
5669 /* 5 - clear mgcg override */
5670 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_MGCG_OVERRIDE, CLE_BPM_SERDES_CMD);
5672 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS) {
5673 /* 6 - Enable CGTS(Tree Shade) MGCG /MGLS */
5674 temp = data = RREG32(mmCGTS_SM_CTRL_REG);
5675 data &= ~(CGTS_SM_CTRL_REG__SM_MODE_MASK);
5676 data |= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT);
5677 data |= CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK;
5678 data &= ~CGTS_SM_CTRL_REG__OVERRIDE_MASK;
5679 if ((adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) &&
5680 (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS_LS))
5681 data &= ~CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
5682 data |= CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK;
5683 data |= (0x96 << CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT);
5685 WREG32(mmCGTS_SM_CTRL_REG, data);
5689 /* 7 - wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5690 gfx_v8_0_wait_for_rlc_serdes(adev);
5692 /* 1 - MGCG_OVERRIDE[0] for CP and MGCG_OVERRIDE[1] for RLC */
5693 temp = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
5694 data |= (RLC_CGTT_MGCG_OVERRIDE__CPF_MASK |
5695 RLC_CGTT_MGCG_OVERRIDE__RLC_MASK |
5696 RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK |
5697 RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK);
5699 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
5701 /* 2 - disable MGLS in RLC */
5702 data = RREG32(mmRLC_MEM_SLP_CNTL);
5703 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
5704 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
5705 WREG32(mmRLC_MEM_SLP_CNTL, data);
5708 /* 3 - disable MGLS in CP */
5709 data = RREG32(mmCP_MEM_SLP_CNTL);
5710 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
5711 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
5712 WREG32(mmCP_MEM_SLP_CNTL, data);
5715 /* 4 - Disable CGTS(Tree Shade) MGCG and MGLS */
5716 temp = data = RREG32(mmCGTS_SM_CTRL_REG);
5717 data |= (CGTS_SM_CTRL_REG__OVERRIDE_MASK |
5718 CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK);
5720 WREG32(mmCGTS_SM_CTRL_REG, data);
5722 /* 5 - wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5723 gfx_v8_0_wait_for_rlc_serdes(adev);
5725 /* 6 - set mgcg override */
5726 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_MGCG_OVERRIDE, SET_BPM_SERDES_CMD);
5730 /* 7- wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5731 gfx_v8_0_wait_for_rlc_serdes(adev);
5734 amdgpu_gfx_rlc_exit_safe_mode(adev);
5737 static void gfx_v8_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
5740 uint32_t temp, temp1, data, data1;
5742 temp = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
5744 amdgpu_gfx_rlc_enter_safe_mode(adev);
5746 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
5747 temp1 = data1 = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
5748 data1 &= ~RLC_CGTT_MGCG_OVERRIDE__CGCG_MASK;
5750 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data1);
5752 /* : wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5753 gfx_v8_0_wait_for_rlc_serdes(adev);
5755 /* 2 - clear cgcg override */
5756 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGCG_OVERRIDE, CLE_BPM_SERDES_CMD);
5758 /* wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5759 gfx_v8_0_wait_for_rlc_serdes(adev);
5761 /* 3 - write cmd to set CGLS */
5762 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGLS_EN, SET_BPM_SERDES_CMD);
5764 /* 4 - enable cgcg */
5765 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
5767 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) {
5769 data |= RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
5771 temp1 = data1 = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
5772 data1 &= ~RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK;
5775 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data1);
5777 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
5781 WREG32(mmRLC_CGCG_CGLS_CTRL, data);
5783 /* 5 enable cntx_empty_int_enable/cntx_busy_int_enable/
5784 * Cmp_busy/GFX_Idle interrupts
5786 gfx_v8_0_enable_gui_idle_interrupt(adev, true);
5788 /* disable cntx_empty_int_enable & GFX Idle interrupt */
5789 gfx_v8_0_enable_gui_idle_interrupt(adev, false);
5792 temp1 = data1 = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
5793 data1 |= (RLC_CGTT_MGCG_OVERRIDE__CGCG_MASK |
5794 RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK);
5796 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data1);
5798 /* read gfx register to wake up cgcg */
5799 RREG32(mmCB_CGTT_SCLK_CTRL);
5800 RREG32(mmCB_CGTT_SCLK_CTRL);
5801 RREG32(mmCB_CGTT_SCLK_CTRL);
5802 RREG32(mmCB_CGTT_SCLK_CTRL);
5804 /* wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5805 gfx_v8_0_wait_for_rlc_serdes(adev);
5807 /* write cmd to Set CGCG Overrride */
5808 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGCG_OVERRIDE, SET_BPM_SERDES_CMD);
5810 /* wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
5811 gfx_v8_0_wait_for_rlc_serdes(adev);
5813 /* write cmd to Clear CGLS */
5814 gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGLS_EN, CLE_BPM_SERDES_CMD);
5816 /* disable cgcg, cgls should be disabled too. */
5817 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK |
5818 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
5820 WREG32(mmRLC_CGCG_CGLS_CTRL, data);
5821 /* enable interrupts again for PG */
5822 gfx_v8_0_enable_gui_idle_interrupt(adev, true);
5825 gfx_v8_0_wait_for_rlc_serdes(adev);
5827 amdgpu_gfx_rlc_exit_safe_mode(adev);
5829 static int gfx_v8_0_update_gfx_clock_gating(struct amdgpu_device *adev,
5833 /* CGCG/CGLS should be enabled after MGCG/MGLS/TS(CG/LS)
5834 * === MGCG + MGLS + TS(CG/LS) ===
5836 gfx_v8_0_update_medium_grain_clock_gating(adev, enable);
5837 gfx_v8_0_update_coarse_grain_clock_gating(adev, enable);
5839 /* CGCG/CGLS should be disabled before MGCG/MGLS/TS(CG/LS)
5840 * === CGCG + CGLS ===
5842 gfx_v8_0_update_coarse_grain_clock_gating(adev, enable);
5843 gfx_v8_0_update_medium_grain_clock_gating(adev, enable);
5848 static int gfx_v8_0_tonga_update_gfx_clock_gating(struct amdgpu_device *adev,
5849 enum amd_clockgating_state state)
5851 uint32_t msg_id, pp_state = 0;
5852 uint32_t pp_support_state = 0;
5854 if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS)) {
5855 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) {
5856 pp_support_state = PP_STATE_SUPPORT_LS;
5857 pp_state = PP_STATE_LS;
5859 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) {
5860 pp_support_state |= PP_STATE_SUPPORT_CG;
5861 pp_state |= PP_STATE_CG;
5863 if (state == AMD_CG_STATE_UNGATE)
5866 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
5870 if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
5871 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
5874 if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)) {
5875 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
5876 pp_support_state = PP_STATE_SUPPORT_LS;
5877 pp_state = PP_STATE_LS;
5880 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) {
5881 pp_support_state |= PP_STATE_SUPPORT_CG;
5882 pp_state |= PP_STATE_CG;
5885 if (state == AMD_CG_STATE_UNGATE)
5888 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
5892 if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
5893 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
5899 static int gfx_v8_0_polaris_update_gfx_clock_gating(struct amdgpu_device *adev,
5900 enum amd_clockgating_state state)
5903 uint32_t msg_id, pp_state = 0;
5904 uint32_t pp_support_state = 0;
5906 if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS)) {
5907 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) {
5908 pp_support_state = PP_STATE_SUPPORT_LS;
5909 pp_state = PP_STATE_LS;
5911 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) {
5912 pp_support_state |= PP_STATE_SUPPORT_CG;
5913 pp_state |= PP_STATE_CG;
5915 if (state == AMD_CG_STATE_UNGATE)
5918 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
5922 if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
5923 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
5926 if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS)) {
5927 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) {
5928 pp_support_state = PP_STATE_SUPPORT_LS;
5929 pp_state = PP_STATE_LS;
5931 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) {
5932 pp_support_state |= PP_STATE_SUPPORT_CG;
5933 pp_state |= PP_STATE_CG;
5935 if (state == AMD_CG_STATE_UNGATE)
5938 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
5942 if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
5943 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
5946 if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)) {
5947 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
5948 pp_support_state = PP_STATE_SUPPORT_LS;
5949 pp_state = PP_STATE_LS;
5952 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) {
5953 pp_support_state |= PP_STATE_SUPPORT_CG;
5954 pp_state |= PP_STATE_CG;
5957 if (state == AMD_CG_STATE_UNGATE)
5960 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
5964 if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
5965 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
5968 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
5969 pp_support_state = PP_STATE_SUPPORT_LS;
5971 if (state == AMD_CG_STATE_UNGATE)
5974 pp_state = PP_STATE_LS;
5976 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
5980 if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
5981 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
5984 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
5985 pp_support_state = PP_STATE_SUPPORT_LS;
5987 if (state == AMD_CG_STATE_UNGATE)
5990 pp_state = PP_STATE_LS;
5991 msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
5995 if (adev->powerplay.pp_funcs->set_clockgating_by_smu)
5996 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
6002 static int gfx_v8_0_set_clockgating_state(void *handle,
6003 enum amd_clockgating_state state)
6005 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6007 if (amdgpu_sriov_vf(adev))
6010 switch (adev->asic_type) {
6014 gfx_v8_0_update_gfx_clock_gating(adev,
6015 state == AMD_CG_STATE_GATE);
6018 gfx_v8_0_tonga_update_gfx_clock_gating(adev, state);
6020 case CHIP_POLARIS10:
6021 case CHIP_POLARIS11:
6022 case CHIP_POLARIS12:
6024 gfx_v8_0_polaris_update_gfx_clock_gating(adev, state);
6032 static u64 gfx_v8_0_ring_get_rptr(struct amdgpu_ring *ring)
6034 return ring->adev->wb.wb[ring->rptr_offs];
6037 static u64 gfx_v8_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
6039 struct amdgpu_device *adev = ring->adev;
6041 if (ring->use_doorbell)
6042 /* XXX check if swapping is necessary on BE */
6043 return ring->adev->wb.wb[ring->wptr_offs];
6045 return RREG32(mmCP_RB0_WPTR);
6048 static void gfx_v8_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
6050 struct amdgpu_device *adev = ring->adev;
6052 if (ring->use_doorbell) {
6053 /* XXX check if swapping is necessary on BE */
6054 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
6055 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
6057 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
6058 (void)RREG32(mmCP_RB0_WPTR);
6062 static void gfx_v8_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
6064 u32 ref_and_mask, reg_mem_engine;
6066 if ((ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) ||
6067 (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)) {
6070 ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe;
6073 ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe;
6080 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK;
6081 reg_mem_engine = WAIT_REG_MEM_ENGINE(1); /* pfp */
6084 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
6085 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */
6086 WAIT_REG_MEM_FUNCTION(3) | /* == */
6088 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ);
6089 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE);
6090 amdgpu_ring_write(ring, ref_and_mask);
6091 amdgpu_ring_write(ring, ref_and_mask);
6092 amdgpu_ring_write(ring, 0x20); /* poll interval */
6095 static void gfx_v8_0_ring_emit_vgt_flush(struct amdgpu_ring *ring)
6097 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
6098 amdgpu_ring_write(ring, EVENT_TYPE(VS_PARTIAL_FLUSH) |
6101 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
6102 amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) |
6106 static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
6107 struct amdgpu_job *job,
6108 struct amdgpu_ib *ib,
6111 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
6112 u32 header, control = 0;
6114 if (ib->flags & AMDGPU_IB_FLAG_CE)
6115 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
6117 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
6119 control |= ib->length_dw | (vmid << 24);
6121 if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
6122 control |= INDIRECT_BUFFER_PRE_ENB(1);
6124 if (!(ib->flags & AMDGPU_IB_FLAG_CE))
6125 gfx_v8_0_ring_emit_de_meta(ring);
6128 amdgpu_ring_write(ring, header);
6129 amdgpu_ring_write(ring,
6133 (ib->gpu_addr & 0xFFFFFFFC));
6134 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
6135 amdgpu_ring_write(ring, control);
6138 static void gfx_v8_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
6139 struct amdgpu_job *job,
6140 struct amdgpu_ib *ib,
6143 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
6144 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
6146 /* Currently, there is a high possibility to get wave ID mismatch
6147 * between ME and GDS, leading to a hw deadlock, because ME generates
6148 * different wave IDs than the GDS expects. This situation happens
6149 * randomly when at least 5 compute pipes use GDS ordered append.
6150 * The wave IDs generated by ME are also wrong after suspend/resume.
6151 * Those are probably bugs somewhere else in the kernel driver.
6153 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
6154 * GDS to 0 for this ring (me/pipe).
6156 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
6157 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
6158 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID - PACKET3_SET_CONFIG_REG_START);
6159 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
6162 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
6163 amdgpu_ring_write(ring,
6167 (ib->gpu_addr & 0xFFFFFFFC));
6168 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
6169 amdgpu_ring_write(ring, control);
6172 static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
6173 u64 seq, unsigned flags)
6175 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
6176 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
6178 /* EVENT_WRITE_EOP - flush caches, send int */
6179 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
6180 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
6182 EOP_TC_WB_ACTION_EN |
6183 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
6185 amdgpu_ring_write(ring, addr & 0xfffffffc);
6186 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
6187 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
6188 amdgpu_ring_write(ring, lower_32_bits(seq));
6189 amdgpu_ring_write(ring, upper_32_bits(seq));
6193 static void gfx_v8_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
6195 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
6196 uint32_t seq = ring->fence_drv.sync_seq;
6197 uint64_t addr = ring->fence_drv.gpu_addr;
6199 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
6200 amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
6201 WAIT_REG_MEM_FUNCTION(3) | /* equal */
6202 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */
6203 amdgpu_ring_write(ring, addr & 0xfffffffc);
6204 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
6205 amdgpu_ring_write(ring, seq);
6206 amdgpu_ring_write(ring, 0xffffffff);
6207 amdgpu_ring_write(ring, 4); /* poll interval */
6210 static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
6211 unsigned vmid, uint64_t pd_addr)
6213 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
6215 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
6217 /* wait for the invalidate to complete */
6218 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
6219 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */
6220 WAIT_REG_MEM_FUNCTION(0) | /* always */
6221 WAIT_REG_MEM_ENGINE(0))); /* me */
6222 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
6223 amdgpu_ring_write(ring, 0);
6224 amdgpu_ring_write(ring, 0); /* ref */
6225 amdgpu_ring_write(ring, 0); /* mask */
6226 amdgpu_ring_write(ring, 0x20); /* poll interval */
6228 /* compute doesn't have PFP */
6230 /* sync PFP to ME, otherwise we might get invalid PFP reads */
6231 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
6232 amdgpu_ring_write(ring, 0x0);
6236 static u64 gfx_v8_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
6238 return ring->adev->wb.wb[ring->wptr_offs];
6241 static void gfx_v8_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
6243 struct amdgpu_device *adev = ring->adev;
6245 /* XXX check if swapping is necessary on BE */
6246 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
6247 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
6250 static void gfx_v8_0_ring_set_pipe_percent(struct amdgpu_ring *ring,
6253 struct amdgpu_device *adev = ring->adev;
6254 int pipe_num, tmp, reg;
6255 int pipe_percent = acquire ? SPI_WCL_PIPE_PERCENT_GFX__VALUE_MASK : 0x1;
6257 pipe_num = ring->me * adev->gfx.mec.num_pipe_per_mec + ring->pipe;
6259 /* first me only has 2 entries, GFX and HP3D */
6263 reg = mmSPI_WCL_PIPE_PERCENT_GFX + pipe_num;
6265 tmp = REG_SET_FIELD(tmp, SPI_WCL_PIPE_PERCENT_GFX, VALUE, pipe_percent);
6269 static void gfx_v8_0_pipe_reserve_resources(struct amdgpu_device *adev,
6270 struct amdgpu_ring *ring,
6275 struct amdgpu_ring *iring;
6277 mutex_lock(&adev->gfx.pipe_reserve_mutex);
6278 pipe = amdgpu_gfx_mec_queue_to_bit(adev, ring->me, ring->pipe, 0);
6280 set_bit(pipe, adev->gfx.pipe_reserve_bitmap);
6282 clear_bit(pipe, adev->gfx.pipe_reserve_bitmap);
6284 if (!bitmap_weight(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES)) {
6285 /* Clear all reservations - everyone reacquires all resources */
6286 for (i = 0; i < adev->gfx.num_gfx_rings; ++i)
6287 gfx_v8_0_ring_set_pipe_percent(&adev->gfx.gfx_ring[i],
6290 for (i = 0; i < adev->gfx.num_compute_rings; ++i)
6291 gfx_v8_0_ring_set_pipe_percent(&adev->gfx.compute_ring[i],
6294 /* Lower all pipes without a current reservation */
6295 for (i = 0; i < adev->gfx.num_gfx_rings; ++i) {
6296 iring = &adev->gfx.gfx_ring[i];
6297 pipe = amdgpu_gfx_mec_queue_to_bit(adev,
6301 reserve = test_bit(pipe, adev->gfx.pipe_reserve_bitmap);
6302 gfx_v8_0_ring_set_pipe_percent(iring, reserve);
6305 for (i = 0; i < adev->gfx.num_compute_rings; ++i) {
6306 iring = &adev->gfx.compute_ring[i];
6307 pipe = amdgpu_gfx_mec_queue_to_bit(adev,
6311 reserve = test_bit(pipe, adev->gfx.pipe_reserve_bitmap);
6312 gfx_v8_0_ring_set_pipe_percent(iring, reserve);
6316 mutex_unlock(&adev->gfx.pipe_reserve_mutex);
6319 static void gfx_v8_0_hqd_set_priority(struct amdgpu_device *adev,
6320 struct amdgpu_ring *ring,
6323 uint32_t pipe_priority = acquire ? 0x2 : 0x0;
6324 uint32_t queue_priority = acquire ? 0xf : 0x0;
6326 mutex_lock(&adev->srbm_mutex);
6327 vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6329 WREG32(mmCP_HQD_PIPE_PRIORITY, pipe_priority);
6330 WREG32(mmCP_HQD_QUEUE_PRIORITY, queue_priority);
6332 vi_srbm_select(adev, 0, 0, 0, 0);
6333 mutex_unlock(&adev->srbm_mutex);
6335 static void gfx_v8_0_ring_set_priority_compute(struct amdgpu_ring *ring,
6336 enum drm_sched_priority priority)
6338 struct amdgpu_device *adev = ring->adev;
6339 bool acquire = priority == DRM_SCHED_PRIORITY_HIGH_HW;
6341 if (ring->funcs->type != AMDGPU_RING_TYPE_COMPUTE)
6344 gfx_v8_0_hqd_set_priority(adev, ring, acquire);
6345 gfx_v8_0_pipe_reserve_resources(adev, ring, acquire);
6348 static void gfx_v8_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
6352 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
6353 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
6355 /* RELEASE_MEM - flush caches, send int */
6356 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));
6357 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
6359 EOP_TC_WB_ACTION_EN |
6360 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
6362 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
6363 amdgpu_ring_write(ring, addr & 0xfffffffc);
6364 amdgpu_ring_write(ring, upper_32_bits(addr));
6365 amdgpu_ring_write(ring, lower_32_bits(seq));
6366 amdgpu_ring_write(ring, upper_32_bits(seq));
6369 static void gfx_v8_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
6370 u64 seq, unsigned int flags)
6372 /* we only allocate 32bit for each seq wb address */
6373 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
6375 /* write fence seq to the "addr" */
6376 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
6377 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
6378 WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
6379 amdgpu_ring_write(ring, lower_32_bits(addr));
6380 amdgpu_ring_write(ring, upper_32_bits(addr));
6381 amdgpu_ring_write(ring, lower_32_bits(seq));
6383 if (flags & AMDGPU_FENCE_FLAG_INT) {
6384 /* set register to trigger INT */
6385 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
6386 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
6387 WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
6388 amdgpu_ring_write(ring, mmCPC_INT_STATUS);
6389 amdgpu_ring_write(ring, 0);
6390 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
6394 static void gfx_v8_ring_emit_sb(struct amdgpu_ring *ring)
6396 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
6397 amdgpu_ring_write(ring, 0);
6400 static void gfx_v8_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
6404 if (amdgpu_sriov_vf(ring->adev))
6405 gfx_v8_0_ring_emit_ce_meta(ring);
6407 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
6408 if (flags & AMDGPU_HAVE_CTX_SWITCH) {
6409 gfx_v8_0_ring_emit_vgt_flush(ring);
6410 /* set load_global_config & load_global_uconfig */
6412 /* set load_cs_sh_regs */
6414 /* set load_per_context_state & load_gfx_sh_regs for GFX */
6417 /* set load_ce_ram if preamble presented */
6418 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
6421 /* still load_ce_ram if this is the first time preamble presented
6422 * although there is no context switch happens.
6424 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
6428 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
6429 amdgpu_ring_write(ring, dw2);
6430 amdgpu_ring_write(ring, 0);
6433 static unsigned gfx_v8_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
6437 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
6438 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
6439 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
6440 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
6441 ret = ring->wptr & ring->buf_mask;
6442 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
6446 static void gfx_v8_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
6450 BUG_ON(offset > ring->buf_mask);
6451 BUG_ON(ring->ring[offset] != 0x55aa55aa);
6453 cur = (ring->wptr & ring->buf_mask) - 1;
6454 if (likely(cur > offset))
6455 ring->ring[offset] = cur - offset;
6457 ring->ring[offset] = (ring->ring_size >> 2) - offset + cur;
6460 static void gfx_v8_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
6462 struct amdgpu_device *adev = ring->adev;
6464 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
6465 amdgpu_ring_write(ring, 0 | /* src: register*/
6466 (5 << 8) | /* dst: memory */
6467 (1 << 20)); /* write confirm */
6468 amdgpu_ring_write(ring, reg);
6469 amdgpu_ring_write(ring, 0);
6470 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
6471 adev->virt.reg_val_offs * 4));
6472 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
6473 adev->virt.reg_val_offs * 4));
6476 static void gfx_v8_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
6481 switch (ring->funcs->type) {
6482 case AMDGPU_RING_TYPE_GFX:
6483 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
6485 case AMDGPU_RING_TYPE_KIQ:
6486 cmd = 1 << 16; /* no inc addr */
6493 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
6494 amdgpu_ring_write(ring, cmd);
6495 amdgpu_ring_write(ring, reg);
6496 amdgpu_ring_write(ring, 0);
6497 amdgpu_ring_write(ring, val);
6500 static void gfx_v8_0_ring_soft_recovery(struct amdgpu_ring *ring, unsigned vmid)
6502 struct amdgpu_device *adev = ring->adev;
6505 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
6506 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
6507 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
6508 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
6509 WREG32(mmSQ_CMD, value);
6512 static void gfx_v8_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
6513 enum amdgpu_interrupt_state state)
6515 WREG32_FIELD(CP_INT_CNTL_RING0, TIME_STAMP_INT_ENABLE,
6516 state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1);
6519 static void gfx_v8_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
6521 enum amdgpu_interrupt_state state)
6523 u32 mec_int_cntl, mec_int_cntl_reg;
6526 * amdgpu controls only the first MEC. That's why this function only
6527 * handles the setting of interrupts for this specific MEC. All other
6528 * pipes' interrupts are set by amdkfd.
6534 mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL;
6537 mec_int_cntl_reg = mmCP_ME1_PIPE1_INT_CNTL;
6540 mec_int_cntl_reg = mmCP_ME1_PIPE2_INT_CNTL;
6543 mec_int_cntl_reg = mmCP_ME1_PIPE3_INT_CNTL;
6546 DRM_DEBUG("invalid pipe %d\n", pipe);
6550 DRM_DEBUG("invalid me %d\n", me);
6555 case AMDGPU_IRQ_STATE_DISABLE:
6556 mec_int_cntl = RREG32(mec_int_cntl_reg);
6557 mec_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
6558 WREG32(mec_int_cntl_reg, mec_int_cntl);
6560 case AMDGPU_IRQ_STATE_ENABLE:
6561 mec_int_cntl = RREG32(mec_int_cntl_reg);
6562 mec_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
6563 WREG32(mec_int_cntl_reg, mec_int_cntl);
6570 static int gfx_v8_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
6571 struct amdgpu_irq_src *source,
6573 enum amdgpu_interrupt_state state)
6575 WREG32_FIELD(CP_INT_CNTL_RING0, PRIV_REG_INT_ENABLE,
6576 state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1);
6581 static int gfx_v8_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
6582 struct amdgpu_irq_src *source,
6584 enum amdgpu_interrupt_state state)
6586 WREG32_FIELD(CP_INT_CNTL_RING0, PRIV_INSTR_INT_ENABLE,
6587 state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1);
6592 static int gfx_v8_0_set_eop_interrupt_state(struct amdgpu_device *adev,
6593 struct amdgpu_irq_src *src,
6595 enum amdgpu_interrupt_state state)
6598 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
6599 gfx_v8_0_set_gfx_eop_interrupt_state(adev, state);
6601 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
6602 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
6604 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
6605 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
6607 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
6608 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
6610 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
6611 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
6613 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
6614 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
6616 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
6617 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
6619 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
6620 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
6622 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
6623 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
6631 static int gfx_v8_0_set_cp_ecc_int_state(struct amdgpu_device *adev,
6632 struct amdgpu_irq_src *source,
6634 enum amdgpu_interrupt_state state)
6639 case AMDGPU_IRQ_STATE_DISABLE:
6643 case AMDGPU_IRQ_STATE_ENABLE:
6651 WREG32_FIELD(CP_INT_CNTL, CP_ECC_ERROR_INT_ENABLE, enable_flag);
6652 WREG32_FIELD(CP_INT_CNTL_RING0, CP_ECC_ERROR_INT_ENABLE, enable_flag);
6653 WREG32_FIELD(CP_INT_CNTL_RING1, CP_ECC_ERROR_INT_ENABLE, enable_flag);
6654 WREG32_FIELD(CP_INT_CNTL_RING2, CP_ECC_ERROR_INT_ENABLE, enable_flag);
6655 WREG32_FIELD(CPC_INT_CNTL, CP_ECC_ERROR_INT_ENABLE, enable_flag);
6656 WREG32_FIELD(CP_ME1_PIPE0_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,
6658 WREG32_FIELD(CP_ME1_PIPE1_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,
6660 WREG32_FIELD(CP_ME1_PIPE2_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,
6662 WREG32_FIELD(CP_ME1_PIPE3_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,
6664 WREG32_FIELD(CP_ME2_PIPE0_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,
6666 WREG32_FIELD(CP_ME2_PIPE1_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,
6668 WREG32_FIELD(CP_ME2_PIPE2_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,
6670 WREG32_FIELD(CP_ME2_PIPE3_INT_CNTL, CP_ECC_ERROR_INT_ENABLE,
6676 static int gfx_v8_0_set_sq_int_state(struct amdgpu_device *adev,
6677 struct amdgpu_irq_src *source,
6679 enum amdgpu_interrupt_state state)
6684 case AMDGPU_IRQ_STATE_DISABLE:
6688 case AMDGPU_IRQ_STATE_ENABLE:
6696 WREG32_FIELD(SQ_INTERRUPT_MSG_CTRL, STALL,
6702 static int gfx_v8_0_eop_irq(struct amdgpu_device *adev,
6703 struct amdgpu_irq_src *source,
6704 struct amdgpu_iv_entry *entry)
6707 u8 me_id, pipe_id, queue_id;
6708 struct amdgpu_ring *ring;
6710 DRM_DEBUG("IH: CP EOP\n");
6711 me_id = (entry->ring_id & 0x0c) >> 2;
6712 pipe_id = (entry->ring_id & 0x03) >> 0;
6713 queue_id = (entry->ring_id & 0x70) >> 4;
6717 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
6721 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6722 ring = &adev->gfx.compute_ring[i];
6723 /* Per-queue interrupt is supported for MEC starting from VI.
6724 * The interrupt can only be enabled/disabled per pipe instead of per queue.
6726 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
6727 amdgpu_fence_process(ring);
6734 static void gfx_v8_0_fault(struct amdgpu_device *adev,
6735 struct amdgpu_iv_entry *entry)
6737 u8 me_id, pipe_id, queue_id;
6738 struct amdgpu_ring *ring;
6741 me_id = (entry->ring_id & 0x0c) >> 2;
6742 pipe_id = (entry->ring_id & 0x03) >> 0;
6743 queue_id = (entry->ring_id & 0x70) >> 4;
6747 drm_sched_fault(&adev->gfx.gfx_ring[0].sched);
6751 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6752 ring = &adev->gfx.compute_ring[i];
6753 if (ring->me == me_id && ring->pipe == pipe_id &&
6754 ring->queue == queue_id)
6755 drm_sched_fault(&ring->sched);
6761 static int gfx_v8_0_priv_reg_irq(struct amdgpu_device *adev,
6762 struct amdgpu_irq_src *source,
6763 struct amdgpu_iv_entry *entry)
6765 DRM_ERROR("Illegal register access in command stream\n");
6766 gfx_v8_0_fault(adev, entry);
6770 static int gfx_v8_0_priv_inst_irq(struct amdgpu_device *adev,
6771 struct amdgpu_irq_src *source,
6772 struct amdgpu_iv_entry *entry)
6774 DRM_ERROR("Illegal instruction in command stream\n");
6775 gfx_v8_0_fault(adev, entry);
6779 static int gfx_v8_0_cp_ecc_error_irq(struct amdgpu_device *adev,
6780 struct amdgpu_irq_src *source,
6781 struct amdgpu_iv_entry *entry)
6783 DRM_ERROR("CP EDC/ECC error detected.");
6787 static void gfx_v8_0_parse_sq_irq(struct amdgpu_device *adev, unsigned ih_data)
6789 u32 enc, se_id, sh_id, cu_id;
6791 int sq_edc_source = -1;
6793 enc = REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_CMN, ENCODING);
6794 se_id = REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_CMN, SE_ID);
6798 DRM_INFO("SQ general purpose intr detected:"
6799 "se_id %d, immed_overflow %d, host_reg_overflow %d,"
6800 "host_cmd_overflow %d, cmd_timestamp %d,"
6801 "reg_timestamp %d, thread_trace_buff_full %d,"
6802 "wlt %d, thread_trace %d.\n",
6804 REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, IMMED_OVERFLOW),
6805 REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, HOST_REG_OVERFLOW),
6806 REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, HOST_CMD_OVERFLOW),
6807 REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, CMD_TIMESTAMP),
6808 REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, REG_TIMESTAMP),
6809 REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, THREAD_TRACE_BUF_FULL),
6810 REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, WLT),
6811 REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_AUTO, THREAD_TRACE)
6817 cu_id = REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, CU_ID);
6818 sh_id = REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, SH_ID);
6821 * This function can be called either directly from ISR
6822 * or from BH in which case we can access SQ_EDC_INFO
6826 mutex_lock(&adev->grbm_idx_mutex);
6827 gfx_v8_0_select_se_sh(adev, se_id, sh_id, cu_id);
6829 sq_edc_source = REG_GET_FIELD(RREG32(mmSQ_EDC_INFO), SQ_EDC_INFO, SOURCE);
6831 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
6832 mutex_unlock(&adev->grbm_idx_mutex);
6836 sprintf(type, "instruction intr");
6838 sprintf(type, "EDC/ECC error");
6842 "se_id %d, sh_id %d, cu_id %d, simd_id %d, wave_id %d, vm_id %d "
6843 "trap %s, sq_ed_info.source %s.\n",
6844 type, se_id, sh_id, cu_id,
6845 REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, SIMD_ID),
6846 REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, WAVE_ID),
6847 REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, VM_ID),
6848 REG_GET_FIELD(ih_data, SQ_INTERRUPT_WORD_WAVE, PRIV) ? "true" : "false",
6849 (sq_edc_source != -1) ? sq_edc_source_names[sq_edc_source] : "unavailable"
6853 DRM_ERROR("SQ invalid encoding type\n.");
6857 static void gfx_v8_0_sq_irq_work_func(struct work_struct *work)
6860 struct amdgpu_device *adev = container_of(work, struct amdgpu_device, gfx.sq_work.work);
6861 struct sq_work *sq_work = container_of(work, struct sq_work, work);
6863 gfx_v8_0_parse_sq_irq(adev, sq_work->ih_data);
6866 static int gfx_v8_0_sq_irq(struct amdgpu_device *adev,
6867 struct amdgpu_irq_src *source,
6868 struct amdgpu_iv_entry *entry)
6870 unsigned ih_data = entry->src_data[0];
6873 * Try to submit work so SQ_EDC_INFO can be accessed from
6874 * BH. If previous work submission hasn't finished yet
6875 * just print whatever info is possible directly from the ISR.
6877 if (work_pending(&adev->gfx.sq_work.work)) {
6878 gfx_v8_0_parse_sq_irq(adev, ih_data);
6880 adev->gfx.sq_work.ih_data = ih_data;
6881 schedule_work(&adev->gfx.sq_work.work);
6887 static const struct amd_ip_funcs gfx_v8_0_ip_funcs = {
6889 .early_init = gfx_v8_0_early_init,
6890 .late_init = gfx_v8_0_late_init,
6891 .sw_init = gfx_v8_0_sw_init,
6892 .sw_fini = gfx_v8_0_sw_fini,
6893 .hw_init = gfx_v8_0_hw_init,
6894 .hw_fini = gfx_v8_0_hw_fini,
6895 .suspend = gfx_v8_0_suspend,
6896 .resume = gfx_v8_0_resume,
6897 .is_idle = gfx_v8_0_is_idle,
6898 .wait_for_idle = gfx_v8_0_wait_for_idle,
6899 .check_soft_reset = gfx_v8_0_check_soft_reset,
6900 .pre_soft_reset = gfx_v8_0_pre_soft_reset,
6901 .soft_reset = gfx_v8_0_soft_reset,
6902 .post_soft_reset = gfx_v8_0_post_soft_reset,
6903 .set_clockgating_state = gfx_v8_0_set_clockgating_state,
6904 .set_powergating_state = gfx_v8_0_set_powergating_state,
6905 .get_clockgating_state = gfx_v8_0_get_clockgating_state,
6908 static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = {
6909 .type = AMDGPU_RING_TYPE_GFX,
6911 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
6912 .support_64bit_ptrs = false,
6913 .get_rptr = gfx_v8_0_ring_get_rptr,
6914 .get_wptr = gfx_v8_0_ring_get_wptr_gfx,
6915 .set_wptr = gfx_v8_0_ring_set_wptr_gfx,
6916 .emit_frame_size = /* maximum 215dw if count 16 IBs in */
6918 7 + /* PIPELINE_SYNC */
6919 VI_FLUSH_GPU_TLB_NUM_WREG * 5 + 9 + /* VM_FLUSH */
6920 8 + /* FENCE for VM_FLUSH */
6921 20 + /* GDS switch */
6922 4 + /* double SWITCH_BUFFER,
6923 the first COND_EXEC jump to the place just
6924 prior to this double SWITCH_BUFFER */
6932 8 + 8 + /* FENCE x2 */
6933 2, /* SWITCH_BUFFER */
6934 .emit_ib_size = 4, /* gfx_v8_0_ring_emit_ib_gfx */
6935 .emit_ib = gfx_v8_0_ring_emit_ib_gfx,
6936 .emit_fence = gfx_v8_0_ring_emit_fence_gfx,
6937 .emit_pipeline_sync = gfx_v8_0_ring_emit_pipeline_sync,
6938 .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
6939 .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
6940 .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
6941 .test_ring = gfx_v8_0_ring_test_ring,
6942 .test_ib = gfx_v8_0_ring_test_ib,
6943 .insert_nop = amdgpu_ring_insert_nop,
6944 .pad_ib = amdgpu_ring_generic_pad_ib,
6945 .emit_switch_buffer = gfx_v8_ring_emit_sb,
6946 .emit_cntxcntl = gfx_v8_ring_emit_cntxcntl,
6947 .init_cond_exec = gfx_v8_0_ring_emit_init_cond_exec,
6948 .patch_cond_exec = gfx_v8_0_ring_emit_patch_cond_exec,
6949 .emit_wreg = gfx_v8_0_ring_emit_wreg,
6950 .soft_recovery = gfx_v8_0_ring_soft_recovery,
6953 static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = {
6954 .type = AMDGPU_RING_TYPE_COMPUTE,
6956 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
6957 .support_64bit_ptrs = false,
6958 .get_rptr = gfx_v8_0_ring_get_rptr,
6959 .get_wptr = gfx_v8_0_ring_get_wptr_compute,
6960 .set_wptr = gfx_v8_0_ring_set_wptr_compute,
6962 20 + /* gfx_v8_0_ring_emit_gds_switch */
6963 7 + /* gfx_v8_0_ring_emit_hdp_flush */
6964 5 + /* hdp_invalidate */
6965 7 + /* gfx_v8_0_ring_emit_pipeline_sync */
6966 VI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + /* gfx_v8_0_ring_emit_vm_flush */
6967 7 + 7 + 7, /* gfx_v8_0_ring_emit_fence_compute x3 for user fence, vm fence */
6968 .emit_ib_size = 7, /* gfx_v8_0_ring_emit_ib_compute */
6969 .emit_ib = gfx_v8_0_ring_emit_ib_compute,
6970 .emit_fence = gfx_v8_0_ring_emit_fence_compute,
6971 .emit_pipeline_sync = gfx_v8_0_ring_emit_pipeline_sync,
6972 .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
6973 .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
6974 .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
6975 .test_ring = gfx_v8_0_ring_test_ring,
6976 .test_ib = gfx_v8_0_ring_test_ib,
6977 .insert_nop = amdgpu_ring_insert_nop,
6978 .pad_ib = amdgpu_ring_generic_pad_ib,
6979 .set_priority = gfx_v8_0_ring_set_priority_compute,
6980 .emit_wreg = gfx_v8_0_ring_emit_wreg,
6983 static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_kiq = {
6984 .type = AMDGPU_RING_TYPE_KIQ,
6986 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
6987 .support_64bit_ptrs = false,
6988 .get_rptr = gfx_v8_0_ring_get_rptr,
6989 .get_wptr = gfx_v8_0_ring_get_wptr_compute,
6990 .set_wptr = gfx_v8_0_ring_set_wptr_compute,
6992 20 + /* gfx_v8_0_ring_emit_gds_switch */
6993 7 + /* gfx_v8_0_ring_emit_hdp_flush */
6994 5 + /* hdp_invalidate */
6995 7 + /* gfx_v8_0_ring_emit_pipeline_sync */
6996 17 + /* gfx_v8_0_ring_emit_vm_flush */
6997 7 + 7 + 7, /* gfx_v8_0_ring_emit_fence_kiq x3 for user fence, vm fence */
6998 .emit_ib_size = 7, /* gfx_v8_0_ring_emit_ib_compute */
6999 .emit_fence = gfx_v8_0_ring_emit_fence_kiq,
7000 .test_ring = gfx_v8_0_ring_test_ring,
7001 .insert_nop = amdgpu_ring_insert_nop,
7002 .pad_ib = amdgpu_ring_generic_pad_ib,
7003 .emit_rreg = gfx_v8_0_ring_emit_rreg,
7004 .emit_wreg = gfx_v8_0_ring_emit_wreg,
7007 static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev)
7011 adev->gfx.kiq.ring.funcs = &gfx_v8_0_ring_funcs_kiq;
7013 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
7014 adev->gfx.gfx_ring[i].funcs = &gfx_v8_0_ring_funcs_gfx;
7016 for (i = 0; i < adev->gfx.num_compute_rings; i++)
7017 adev->gfx.compute_ring[i].funcs = &gfx_v8_0_ring_funcs_compute;
7020 static const struct amdgpu_irq_src_funcs gfx_v8_0_eop_irq_funcs = {
7021 .set = gfx_v8_0_set_eop_interrupt_state,
7022 .process = gfx_v8_0_eop_irq,
7025 static const struct amdgpu_irq_src_funcs gfx_v8_0_priv_reg_irq_funcs = {
7026 .set = gfx_v8_0_set_priv_reg_fault_state,
7027 .process = gfx_v8_0_priv_reg_irq,
7030 static const struct amdgpu_irq_src_funcs gfx_v8_0_priv_inst_irq_funcs = {
7031 .set = gfx_v8_0_set_priv_inst_fault_state,
7032 .process = gfx_v8_0_priv_inst_irq,
7035 static const struct amdgpu_irq_src_funcs gfx_v8_0_cp_ecc_error_irq_funcs = {
7036 .set = gfx_v8_0_set_cp_ecc_int_state,
7037 .process = gfx_v8_0_cp_ecc_error_irq,
7040 static const struct amdgpu_irq_src_funcs gfx_v8_0_sq_irq_funcs = {
7041 .set = gfx_v8_0_set_sq_int_state,
7042 .process = gfx_v8_0_sq_irq,
7045 static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev)
7047 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
7048 adev->gfx.eop_irq.funcs = &gfx_v8_0_eop_irq_funcs;
7050 adev->gfx.priv_reg_irq.num_types = 1;
7051 adev->gfx.priv_reg_irq.funcs = &gfx_v8_0_priv_reg_irq_funcs;
7053 adev->gfx.priv_inst_irq.num_types = 1;
7054 adev->gfx.priv_inst_irq.funcs = &gfx_v8_0_priv_inst_irq_funcs;
7056 adev->gfx.cp_ecc_error_irq.num_types = 1;
7057 adev->gfx.cp_ecc_error_irq.funcs = &gfx_v8_0_cp_ecc_error_irq_funcs;
7059 adev->gfx.sq_irq.num_types = 1;
7060 adev->gfx.sq_irq.funcs = &gfx_v8_0_sq_irq_funcs;
7063 static void gfx_v8_0_set_rlc_funcs(struct amdgpu_device *adev)
7065 adev->gfx.rlc.funcs = &iceland_rlc_funcs;
7068 static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev)
7070 /* init asci gds info */
7071 adev->gds.gds_size = RREG32(mmGDS_VMID0_SIZE);
7072 adev->gds.gws_size = 64;
7073 adev->gds.oa_size = 16;
7074 adev->gds.gds_compute_max_wave_id = RREG32(mmGDS_COMPUTE_MAX_WAVE_ID);
7077 static void gfx_v8_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
7085 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
7086 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
7088 WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data);
7091 static u32 gfx_v8_0_get_cu_active_bitmap(struct amdgpu_device *adev)
7095 data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG) |
7096 RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
7098 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
7100 return ~REG_GET_FIELD(data, CC_GC_SHADER_ARRAY_CONFIG, INACTIVE_CUS) & mask;
7103 static void gfx_v8_0_get_cu_info(struct amdgpu_device *adev)
7105 int i, j, k, counter, active_cu_number = 0;
7106 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
7107 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
7108 unsigned disable_masks[4 * 2];
7111 memset(cu_info, 0, sizeof(*cu_info));
7113 if (adev->flags & AMD_IS_APU)
7116 ao_cu_num = adev->gfx.config.max_cu_per_sh;
7118 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
7120 mutex_lock(&adev->grbm_idx_mutex);
7121 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
7122 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
7126 gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff);
7128 gfx_v8_0_set_user_cu_inactive_bitmap(
7129 adev, disable_masks[i * 2 + j]);
7130 bitmap = gfx_v8_0_get_cu_active_bitmap(adev);
7131 cu_info->bitmap[i][j] = bitmap;
7133 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
7134 if (bitmap & mask) {
7135 if (counter < ao_cu_num)
7141 active_cu_number += counter;
7143 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
7144 cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
7147 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
7148 mutex_unlock(&adev->grbm_idx_mutex);
7150 cu_info->number = active_cu_number;
7151 cu_info->ao_cu_mask = ao_cu_mask;
7152 cu_info->simd_per_cu = NUM_SIMD_PER_CU;
7153 cu_info->max_waves_per_simd = 10;
7154 cu_info->max_scratch_slots_per_cu = 32;
7155 cu_info->wave_front_size = 64;
7156 cu_info->lds_size = 64;
7159 const struct amdgpu_ip_block_version gfx_v8_0_ip_block =
7161 .type = AMD_IP_BLOCK_TYPE_GFX,
7165 .funcs = &gfx_v8_0_ip_funcs,
7168 const struct amdgpu_ip_block_version gfx_v8_1_ip_block =
7170 .type = AMD_IP_BLOCK_TYPE_GFX,
7174 .funcs = &gfx_v8_0_ip_funcs,
7177 static void gfx_v8_0_ring_emit_ce_meta(struct amdgpu_ring *ring)
7179 uint64_t ce_payload_addr;
7182 struct vi_ce_ib_state regular;
7183 struct vi_ce_ib_state_chained_ib chained;
7186 if (ring->adev->virt.chained_ib_support) {
7187 ce_payload_addr = amdgpu_csa_vaddr(ring->adev) +
7188 offsetof(struct vi_gfx_meta_data_chained_ib, ce_payload);
7189 cnt_ce = (sizeof(ce_payload.chained) >> 2) + 4 - 2;
7191 ce_payload_addr = amdgpu_csa_vaddr(ring->adev) +
7192 offsetof(struct vi_gfx_meta_data, ce_payload);
7193 cnt_ce = (sizeof(ce_payload.regular) >> 2) + 4 - 2;
7196 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt_ce));
7197 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
7198 WRITE_DATA_DST_SEL(8) |
7200 WRITE_DATA_CACHE_POLICY(0));
7201 amdgpu_ring_write(ring, lower_32_bits(ce_payload_addr));
7202 amdgpu_ring_write(ring, upper_32_bits(ce_payload_addr));
7203 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, cnt_ce - 2);
7206 static void gfx_v8_0_ring_emit_de_meta(struct amdgpu_ring *ring)
7208 uint64_t de_payload_addr, gds_addr, csa_addr;
7211 struct vi_de_ib_state regular;
7212 struct vi_de_ib_state_chained_ib chained;
7215 csa_addr = amdgpu_csa_vaddr(ring->adev);
7216 gds_addr = csa_addr + 4096;
7217 if (ring->adev->virt.chained_ib_support) {
7218 de_payload.chained.gds_backup_addrlo = lower_32_bits(gds_addr);
7219 de_payload.chained.gds_backup_addrhi = upper_32_bits(gds_addr);
7220 de_payload_addr = csa_addr + offsetof(struct vi_gfx_meta_data_chained_ib, de_payload);
7221 cnt_de = (sizeof(de_payload.chained) >> 2) + 4 - 2;
7223 de_payload.regular.gds_backup_addrlo = lower_32_bits(gds_addr);
7224 de_payload.regular.gds_backup_addrhi = upper_32_bits(gds_addr);
7225 de_payload_addr = csa_addr + offsetof(struct vi_gfx_meta_data, de_payload);
7226 cnt_de = (sizeof(de_payload.regular) >> 2) + 4 - 2;
7229 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt_de));
7230 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
7231 WRITE_DATA_DST_SEL(8) |
7233 WRITE_DATA_CACHE_POLICY(0));
7234 amdgpu_ring_write(ring, lower_32_bits(de_payload_addr));
7235 amdgpu_ring_write(ring, upper_32_bits(de_payload_addr));
7236 amdgpu_ring_write_multiple(ring, (void *)&de_payload, cnt_de - 2);