2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/firmware.h>
26 #include "amdgpu_ih.h"
27 #include "amdgpu_gfx.h"
31 #include "amdgpu_ucode.h"
32 #include "clearstate_ci.h"
34 #include "dce/dce_8_0_d.h"
35 #include "dce/dce_8_0_sh_mask.h"
37 #include "bif/bif_4_1_d.h"
38 #include "bif/bif_4_1_sh_mask.h"
40 #include "gca/gfx_7_0_d.h"
41 #include "gca/gfx_7_2_enum.h"
42 #include "gca/gfx_7_2_sh_mask.h"
44 #include "gmc/gmc_7_0_d.h"
45 #include "gmc/gmc_7_0_sh_mask.h"
47 #include "oss/oss_2_0_d.h"
48 #include "oss/oss_2_0_sh_mask.h"
50 #define GFX7_NUM_GFX_RINGS 1
51 #define GFX7_NUM_COMPUTE_RINGS 8
53 static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev);
54 static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev);
55 static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev);
57 MODULE_FIRMWARE("radeon/bonaire_pfp.bin");
58 MODULE_FIRMWARE("radeon/bonaire_me.bin");
59 MODULE_FIRMWARE("radeon/bonaire_ce.bin");
60 MODULE_FIRMWARE("radeon/bonaire_rlc.bin");
61 MODULE_FIRMWARE("radeon/bonaire_mec.bin");
63 MODULE_FIRMWARE("radeon/hawaii_pfp.bin");
64 MODULE_FIRMWARE("radeon/hawaii_me.bin");
65 MODULE_FIRMWARE("radeon/hawaii_ce.bin");
66 MODULE_FIRMWARE("radeon/hawaii_rlc.bin");
67 MODULE_FIRMWARE("radeon/hawaii_mec.bin");
69 MODULE_FIRMWARE("radeon/kaveri_pfp.bin");
70 MODULE_FIRMWARE("radeon/kaveri_me.bin");
71 MODULE_FIRMWARE("radeon/kaveri_ce.bin");
72 MODULE_FIRMWARE("radeon/kaveri_rlc.bin");
73 MODULE_FIRMWARE("radeon/kaveri_mec.bin");
74 MODULE_FIRMWARE("radeon/kaveri_mec2.bin");
76 MODULE_FIRMWARE("radeon/kabini_pfp.bin");
77 MODULE_FIRMWARE("radeon/kabini_me.bin");
78 MODULE_FIRMWARE("radeon/kabini_ce.bin");
79 MODULE_FIRMWARE("radeon/kabini_rlc.bin");
80 MODULE_FIRMWARE("radeon/kabini_mec.bin");
82 MODULE_FIRMWARE("radeon/mullins_pfp.bin");
83 MODULE_FIRMWARE("radeon/mullins_me.bin");
84 MODULE_FIRMWARE("radeon/mullins_ce.bin");
85 MODULE_FIRMWARE("radeon/mullins_rlc.bin");
86 MODULE_FIRMWARE("radeon/mullins_mec.bin");
88 static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
90 {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
91 {mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1},
92 {mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2},
93 {mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3},
94 {mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4},
95 {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5},
96 {mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6},
97 {mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7},
98 {mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8},
99 {mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9},
100 {mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10},
101 {mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11},
102 {mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12},
103 {mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13},
104 {mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14},
105 {mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15}
108 static const u32 spectre_rlc_save_restore_register_list[] =
110 (0x0e00 << 16) | (0xc12c >> 2),
112 (0x0e00 << 16) | (0xc140 >> 2),
114 (0x0e00 << 16) | (0xc150 >> 2),
116 (0x0e00 << 16) | (0xc15c >> 2),
118 (0x0e00 << 16) | (0xc168 >> 2),
120 (0x0e00 << 16) | (0xc170 >> 2),
122 (0x0e00 << 16) | (0xc178 >> 2),
124 (0x0e00 << 16) | (0xc204 >> 2),
126 (0x0e00 << 16) | (0xc2b4 >> 2),
128 (0x0e00 << 16) | (0xc2b8 >> 2),
130 (0x0e00 << 16) | (0xc2bc >> 2),
132 (0x0e00 << 16) | (0xc2c0 >> 2),
134 (0x0e00 << 16) | (0x8228 >> 2),
136 (0x0e00 << 16) | (0x829c >> 2),
138 (0x0e00 << 16) | (0x869c >> 2),
140 (0x0600 << 16) | (0x98f4 >> 2),
142 (0x0e00 << 16) | (0x98f8 >> 2),
144 (0x0e00 << 16) | (0x9900 >> 2),
146 (0x0e00 << 16) | (0xc260 >> 2),
148 (0x0e00 << 16) | (0x90e8 >> 2),
150 (0x0e00 << 16) | (0x3c000 >> 2),
152 (0x0e00 << 16) | (0x3c00c >> 2),
154 (0x0e00 << 16) | (0x8c1c >> 2),
156 (0x0e00 << 16) | (0x9700 >> 2),
158 (0x0e00 << 16) | (0xcd20 >> 2),
160 (0x4e00 << 16) | (0xcd20 >> 2),
162 (0x5e00 << 16) | (0xcd20 >> 2),
164 (0x6e00 << 16) | (0xcd20 >> 2),
166 (0x7e00 << 16) | (0xcd20 >> 2),
168 (0x8e00 << 16) | (0xcd20 >> 2),
170 (0x9e00 << 16) | (0xcd20 >> 2),
172 (0xae00 << 16) | (0xcd20 >> 2),
174 (0xbe00 << 16) | (0xcd20 >> 2),
176 (0x0e00 << 16) | (0x89bc >> 2),
178 (0x0e00 << 16) | (0x8900 >> 2),
181 (0x0e00 << 16) | (0xc130 >> 2),
183 (0x0e00 << 16) | (0xc134 >> 2),
185 (0x0e00 << 16) | (0xc1fc >> 2),
187 (0x0e00 << 16) | (0xc208 >> 2),
189 (0x0e00 << 16) | (0xc264 >> 2),
191 (0x0e00 << 16) | (0xc268 >> 2),
193 (0x0e00 << 16) | (0xc26c >> 2),
195 (0x0e00 << 16) | (0xc270 >> 2),
197 (0x0e00 << 16) | (0xc274 >> 2),
199 (0x0e00 << 16) | (0xc278 >> 2),
201 (0x0e00 << 16) | (0xc27c >> 2),
203 (0x0e00 << 16) | (0xc280 >> 2),
205 (0x0e00 << 16) | (0xc284 >> 2),
207 (0x0e00 << 16) | (0xc288 >> 2),
209 (0x0e00 << 16) | (0xc28c >> 2),
211 (0x0e00 << 16) | (0xc290 >> 2),
213 (0x0e00 << 16) | (0xc294 >> 2),
215 (0x0e00 << 16) | (0xc298 >> 2),
217 (0x0e00 << 16) | (0xc29c >> 2),
219 (0x0e00 << 16) | (0xc2a0 >> 2),
221 (0x0e00 << 16) | (0xc2a4 >> 2),
223 (0x0e00 << 16) | (0xc2a8 >> 2),
225 (0x0e00 << 16) | (0xc2ac >> 2),
227 (0x0e00 << 16) | (0xc2b0 >> 2),
229 (0x0e00 << 16) | (0x301d0 >> 2),
231 (0x0e00 << 16) | (0x30238 >> 2),
233 (0x0e00 << 16) | (0x30250 >> 2),
235 (0x0e00 << 16) | (0x30254 >> 2),
237 (0x0e00 << 16) | (0x30258 >> 2),
239 (0x0e00 << 16) | (0x3025c >> 2),
241 (0x4e00 << 16) | (0xc900 >> 2),
243 (0x5e00 << 16) | (0xc900 >> 2),
245 (0x6e00 << 16) | (0xc900 >> 2),
247 (0x7e00 << 16) | (0xc900 >> 2),
249 (0x8e00 << 16) | (0xc900 >> 2),
251 (0x9e00 << 16) | (0xc900 >> 2),
253 (0xae00 << 16) | (0xc900 >> 2),
255 (0xbe00 << 16) | (0xc900 >> 2),
257 (0x4e00 << 16) | (0xc904 >> 2),
259 (0x5e00 << 16) | (0xc904 >> 2),
261 (0x6e00 << 16) | (0xc904 >> 2),
263 (0x7e00 << 16) | (0xc904 >> 2),
265 (0x8e00 << 16) | (0xc904 >> 2),
267 (0x9e00 << 16) | (0xc904 >> 2),
269 (0xae00 << 16) | (0xc904 >> 2),
271 (0xbe00 << 16) | (0xc904 >> 2),
273 (0x4e00 << 16) | (0xc908 >> 2),
275 (0x5e00 << 16) | (0xc908 >> 2),
277 (0x6e00 << 16) | (0xc908 >> 2),
279 (0x7e00 << 16) | (0xc908 >> 2),
281 (0x8e00 << 16) | (0xc908 >> 2),
283 (0x9e00 << 16) | (0xc908 >> 2),
285 (0xae00 << 16) | (0xc908 >> 2),
287 (0xbe00 << 16) | (0xc908 >> 2),
289 (0x4e00 << 16) | (0xc90c >> 2),
291 (0x5e00 << 16) | (0xc90c >> 2),
293 (0x6e00 << 16) | (0xc90c >> 2),
295 (0x7e00 << 16) | (0xc90c >> 2),
297 (0x8e00 << 16) | (0xc90c >> 2),
299 (0x9e00 << 16) | (0xc90c >> 2),
301 (0xae00 << 16) | (0xc90c >> 2),
303 (0xbe00 << 16) | (0xc90c >> 2),
305 (0x4e00 << 16) | (0xc910 >> 2),
307 (0x5e00 << 16) | (0xc910 >> 2),
309 (0x6e00 << 16) | (0xc910 >> 2),
311 (0x7e00 << 16) | (0xc910 >> 2),
313 (0x8e00 << 16) | (0xc910 >> 2),
315 (0x9e00 << 16) | (0xc910 >> 2),
317 (0xae00 << 16) | (0xc910 >> 2),
319 (0xbe00 << 16) | (0xc910 >> 2),
321 (0x0e00 << 16) | (0xc99c >> 2),
323 (0x0e00 << 16) | (0x9834 >> 2),
325 (0x0000 << 16) | (0x30f00 >> 2),
327 (0x0001 << 16) | (0x30f00 >> 2),
329 (0x0000 << 16) | (0x30f04 >> 2),
331 (0x0001 << 16) | (0x30f04 >> 2),
333 (0x0000 << 16) | (0x30f08 >> 2),
335 (0x0001 << 16) | (0x30f08 >> 2),
337 (0x0000 << 16) | (0x30f0c >> 2),
339 (0x0001 << 16) | (0x30f0c >> 2),
341 (0x0600 << 16) | (0x9b7c >> 2),
343 (0x0e00 << 16) | (0x8a14 >> 2),
345 (0x0e00 << 16) | (0x8a18 >> 2),
347 (0x0600 << 16) | (0x30a00 >> 2),
349 (0x0e00 << 16) | (0x8bf0 >> 2),
351 (0x0e00 << 16) | (0x8bcc >> 2),
353 (0x0e00 << 16) | (0x8b24 >> 2),
355 (0x0e00 << 16) | (0x30a04 >> 2),
357 (0x0600 << 16) | (0x30a10 >> 2),
359 (0x0600 << 16) | (0x30a14 >> 2),
361 (0x0600 << 16) | (0x30a18 >> 2),
363 (0x0600 << 16) | (0x30a2c >> 2),
365 (0x0e00 << 16) | (0xc700 >> 2),
367 (0x0e00 << 16) | (0xc704 >> 2),
369 (0x0e00 << 16) | (0xc708 >> 2),
371 (0x0e00 << 16) | (0xc768 >> 2),
373 (0x0400 << 16) | (0xc770 >> 2),
375 (0x0400 << 16) | (0xc774 >> 2),
377 (0x0400 << 16) | (0xc778 >> 2),
379 (0x0400 << 16) | (0xc77c >> 2),
381 (0x0400 << 16) | (0xc780 >> 2),
383 (0x0400 << 16) | (0xc784 >> 2),
385 (0x0400 << 16) | (0xc788 >> 2),
387 (0x0400 << 16) | (0xc78c >> 2),
389 (0x0400 << 16) | (0xc798 >> 2),
391 (0x0400 << 16) | (0xc79c >> 2),
393 (0x0400 << 16) | (0xc7a0 >> 2),
395 (0x0400 << 16) | (0xc7a4 >> 2),
397 (0x0400 << 16) | (0xc7a8 >> 2),
399 (0x0400 << 16) | (0xc7ac >> 2),
401 (0x0400 << 16) | (0xc7b0 >> 2),
403 (0x0400 << 16) | (0xc7b4 >> 2),
405 (0x0e00 << 16) | (0x9100 >> 2),
407 (0x0e00 << 16) | (0x3c010 >> 2),
409 (0x0e00 << 16) | (0x92a8 >> 2),
411 (0x0e00 << 16) | (0x92ac >> 2),
413 (0x0e00 << 16) | (0x92b4 >> 2),
415 (0x0e00 << 16) | (0x92b8 >> 2),
417 (0x0e00 << 16) | (0x92bc >> 2),
419 (0x0e00 << 16) | (0x92c0 >> 2),
421 (0x0e00 << 16) | (0x92c4 >> 2),
423 (0x0e00 << 16) | (0x92c8 >> 2),
425 (0x0e00 << 16) | (0x92cc >> 2),
427 (0x0e00 << 16) | (0x92d0 >> 2),
429 (0x0e00 << 16) | (0x8c00 >> 2),
431 (0x0e00 << 16) | (0x8c04 >> 2),
433 (0x0e00 << 16) | (0x8c20 >> 2),
435 (0x0e00 << 16) | (0x8c38 >> 2),
437 (0x0e00 << 16) | (0x8c3c >> 2),
439 (0x0e00 << 16) | (0xae00 >> 2),
441 (0x0e00 << 16) | (0x9604 >> 2),
443 (0x0e00 << 16) | (0xac08 >> 2),
445 (0x0e00 << 16) | (0xac0c >> 2),
447 (0x0e00 << 16) | (0xac10 >> 2),
449 (0x0e00 << 16) | (0xac14 >> 2),
451 (0x0e00 << 16) | (0xac58 >> 2),
453 (0x0e00 << 16) | (0xac68 >> 2),
455 (0x0e00 << 16) | (0xac6c >> 2),
457 (0x0e00 << 16) | (0xac70 >> 2),
459 (0x0e00 << 16) | (0xac74 >> 2),
461 (0x0e00 << 16) | (0xac78 >> 2),
463 (0x0e00 << 16) | (0xac7c >> 2),
465 (0x0e00 << 16) | (0xac80 >> 2),
467 (0x0e00 << 16) | (0xac84 >> 2),
469 (0x0e00 << 16) | (0xac88 >> 2),
471 (0x0e00 << 16) | (0xac8c >> 2),
473 (0x0e00 << 16) | (0x970c >> 2),
475 (0x0e00 << 16) | (0x9714 >> 2),
477 (0x0e00 << 16) | (0x9718 >> 2),
479 (0x0e00 << 16) | (0x971c >> 2),
481 (0x0e00 << 16) | (0x31068 >> 2),
483 (0x4e00 << 16) | (0x31068 >> 2),
485 (0x5e00 << 16) | (0x31068 >> 2),
487 (0x6e00 << 16) | (0x31068 >> 2),
489 (0x7e00 << 16) | (0x31068 >> 2),
491 (0x8e00 << 16) | (0x31068 >> 2),
493 (0x9e00 << 16) | (0x31068 >> 2),
495 (0xae00 << 16) | (0x31068 >> 2),
497 (0xbe00 << 16) | (0x31068 >> 2),
499 (0x0e00 << 16) | (0xcd10 >> 2),
501 (0x0e00 << 16) | (0xcd14 >> 2),
503 (0x0e00 << 16) | (0x88b0 >> 2),
505 (0x0e00 << 16) | (0x88b4 >> 2),
507 (0x0e00 << 16) | (0x88b8 >> 2),
509 (0x0e00 << 16) | (0x88bc >> 2),
511 (0x0400 << 16) | (0x89c0 >> 2),
513 (0x0e00 << 16) | (0x88c4 >> 2),
515 (0x0e00 << 16) | (0x88c8 >> 2),
517 (0x0e00 << 16) | (0x88d0 >> 2),
519 (0x0e00 << 16) | (0x88d4 >> 2),
521 (0x0e00 << 16) | (0x88d8 >> 2),
523 (0x0e00 << 16) | (0x8980 >> 2),
525 (0x0e00 << 16) | (0x30938 >> 2),
527 (0x0e00 << 16) | (0x3093c >> 2),
529 (0x0e00 << 16) | (0x30940 >> 2),
531 (0x0e00 << 16) | (0x89a0 >> 2),
533 (0x0e00 << 16) | (0x30900 >> 2),
535 (0x0e00 << 16) | (0x30904 >> 2),
537 (0x0e00 << 16) | (0x89b4 >> 2),
539 (0x0e00 << 16) | (0x3c210 >> 2),
541 (0x0e00 << 16) | (0x3c214 >> 2),
543 (0x0e00 << 16) | (0x3c218 >> 2),
545 (0x0e00 << 16) | (0x8904 >> 2),
548 (0x0e00 << 16) | (0x8c28 >> 2),
549 (0x0e00 << 16) | (0x8c2c >> 2),
550 (0x0e00 << 16) | (0x8c30 >> 2),
551 (0x0e00 << 16) | (0x8c34 >> 2),
552 (0x0e00 << 16) | (0x9600 >> 2),
555 static const u32 kalindi_rlc_save_restore_register_list[] =
557 (0x0e00 << 16) | (0xc12c >> 2),
559 (0x0e00 << 16) | (0xc140 >> 2),
561 (0x0e00 << 16) | (0xc150 >> 2),
563 (0x0e00 << 16) | (0xc15c >> 2),
565 (0x0e00 << 16) | (0xc168 >> 2),
567 (0x0e00 << 16) | (0xc170 >> 2),
569 (0x0e00 << 16) | (0xc204 >> 2),
571 (0x0e00 << 16) | (0xc2b4 >> 2),
573 (0x0e00 << 16) | (0xc2b8 >> 2),
575 (0x0e00 << 16) | (0xc2bc >> 2),
577 (0x0e00 << 16) | (0xc2c0 >> 2),
579 (0x0e00 << 16) | (0x8228 >> 2),
581 (0x0e00 << 16) | (0x829c >> 2),
583 (0x0e00 << 16) | (0x869c >> 2),
585 (0x0600 << 16) | (0x98f4 >> 2),
587 (0x0e00 << 16) | (0x98f8 >> 2),
589 (0x0e00 << 16) | (0x9900 >> 2),
591 (0x0e00 << 16) | (0xc260 >> 2),
593 (0x0e00 << 16) | (0x90e8 >> 2),
595 (0x0e00 << 16) | (0x3c000 >> 2),
597 (0x0e00 << 16) | (0x3c00c >> 2),
599 (0x0e00 << 16) | (0x8c1c >> 2),
601 (0x0e00 << 16) | (0x9700 >> 2),
603 (0x0e00 << 16) | (0xcd20 >> 2),
605 (0x4e00 << 16) | (0xcd20 >> 2),
607 (0x5e00 << 16) | (0xcd20 >> 2),
609 (0x6e00 << 16) | (0xcd20 >> 2),
611 (0x7e00 << 16) | (0xcd20 >> 2),
613 (0x0e00 << 16) | (0x89bc >> 2),
615 (0x0e00 << 16) | (0x8900 >> 2),
618 (0x0e00 << 16) | (0xc130 >> 2),
620 (0x0e00 << 16) | (0xc134 >> 2),
622 (0x0e00 << 16) | (0xc1fc >> 2),
624 (0x0e00 << 16) | (0xc208 >> 2),
626 (0x0e00 << 16) | (0xc264 >> 2),
628 (0x0e00 << 16) | (0xc268 >> 2),
630 (0x0e00 << 16) | (0xc26c >> 2),
632 (0x0e00 << 16) | (0xc270 >> 2),
634 (0x0e00 << 16) | (0xc274 >> 2),
636 (0x0e00 << 16) | (0xc28c >> 2),
638 (0x0e00 << 16) | (0xc290 >> 2),
640 (0x0e00 << 16) | (0xc294 >> 2),
642 (0x0e00 << 16) | (0xc298 >> 2),
644 (0x0e00 << 16) | (0xc2a0 >> 2),
646 (0x0e00 << 16) | (0xc2a4 >> 2),
648 (0x0e00 << 16) | (0xc2a8 >> 2),
650 (0x0e00 << 16) | (0xc2ac >> 2),
652 (0x0e00 << 16) | (0x301d0 >> 2),
654 (0x0e00 << 16) | (0x30238 >> 2),
656 (0x0e00 << 16) | (0x30250 >> 2),
658 (0x0e00 << 16) | (0x30254 >> 2),
660 (0x0e00 << 16) | (0x30258 >> 2),
662 (0x0e00 << 16) | (0x3025c >> 2),
664 (0x4e00 << 16) | (0xc900 >> 2),
666 (0x5e00 << 16) | (0xc900 >> 2),
668 (0x6e00 << 16) | (0xc900 >> 2),
670 (0x7e00 << 16) | (0xc900 >> 2),
672 (0x4e00 << 16) | (0xc904 >> 2),
674 (0x5e00 << 16) | (0xc904 >> 2),
676 (0x6e00 << 16) | (0xc904 >> 2),
678 (0x7e00 << 16) | (0xc904 >> 2),
680 (0x4e00 << 16) | (0xc908 >> 2),
682 (0x5e00 << 16) | (0xc908 >> 2),
684 (0x6e00 << 16) | (0xc908 >> 2),
686 (0x7e00 << 16) | (0xc908 >> 2),
688 (0x4e00 << 16) | (0xc90c >> 2),
690 (0x5e00 << 16) | (0xc90c >> 2),
692 (0x6e00 << 16) | (0xc90c >> 2),
694 (0x7e00 << 16) | (0xc90c >> 2),
696 (0x4e00 << 16) | (0xc910 >> 2),
698 (0x5e00 << 16) | (0xc910 >> 2),
700 (0x6e00 << 16) | (0xc910 >> 2),
702 (0x7e00 << 16) | (0xc910 >> 2),
704 (0x0e00 << 16) | (0xc99c >> 2),
706 (0x0e00 << 16) | (0x9834 >> 2),
708 (0x0000 << 16) | (0x30f00 >> 2),
710 (0x0000 << 16) | (0x30f04 >> 2),
712 (0x0000 << 16) | (0x30f08 >> 2),
714 (0x0000 << 16) | (0x30f0c >> 2),
716 (0x0600 << 16) | (0x9b7c >> 2),
718 (0x0e00 << 16) | (0x8a14 >> 2),
720 (0x0e00 << 16) | (0x8a18 >> 2),
722 (0x0600 << 16) | (0x30a00 >> 2),
724 (0x0e00 << 16) | (0x8bf0 >> 2),
726 (0x0e00 << 16) | (0x8bcc >> 2),
728 (0x0e00 << 16) | (0x8b24 >> 2),
730 (0x0e00 << 16) | (0x30a04 >> 2),
732 (0x0600 << 16) | (0x30a10 >> 2),
734 (0x0600 << 16) | (0x30a14 >> 2),
736 (0x0600 << 16) | (0x30a18 >> 2),
738 (0x0600 << 16) | (0x30a2c >> 2),
740 (0x0e00 << 16) | (0xc700 >> 2),
742 (0x0e00 << 16) | (0xc704 >> 2),
744 (0x0e00 << 16) | (0xc708 >> 2),
746 (0x0e00 << 16) | (0xc768 >> 2),
748 (0x0400 << 16) | (0xc770 >> 2),
750 (0x0400 << 16) | (0xc774 >> 2),
752 (0x0400 << 16) | (0xc798 >> 2),
754 (0x0400 << 16) | (0xc79c >> 2),
756 (0x0e00 << 16) | (0x9100 >> 2),
758 (0x0e00 << 16) | (0x3c010 >> 2),
760 (0x0e00 << 16) | (0x8c00 >> 2),
762 (0x0e00 << 16) | (0x8c04 >> 2),
764 (0x0e00 << 16) | (0x8c20 >> 2),
766 (0x0e00 << 16) | (0x8c38 >> 2),
768 (0x0e00 << 16) | (0x8c3c >> 2),
770 (0x0e00 << 16) | (0xae00 >> 2),
772 (0x0e00 << 16) | (0x9604 >> 2),
774 (0x0e00 << 16) | (0xac08 >> 2),
776 (0x0e00 << 16) | (0xac0c >> 2),
778 (0x0e00 << 16) | (0xac10 >> 2),
780 (0x0e00 << 16) | (0xac14 >> 2),
782 (0x0e00 << 16) | (0xac58 >> 2),
784 (0x0e00 << 16) | (0xac68 >> 2),
786 (0x0e00 << 16) | (0xac6c >> 2),
788 (0x0e00 << 16) | (0xac70 >> 2),
790 (0x0e00 << 16) | (0xac74 >> 2),
792 (0x0e00 << 16) | (0xac78 >> 2),
794 (0x0e00 << 16) | (0xac7c >> 2),
796 (0x0e00 << 16) | (0xac80 >> 2),
798 (0x0e00 << 16) | (0xac84 >> 2),
800 (0x0e00 << 16) | (0xac88 >> 2),
802 (0x0e00 << 16) | (0xac8c >> 2),
804 (0x0e00 << 16) | (0x970c >> 2),
806 (0x0e00 << 16) | (0x9714 >> 2),
808 (0x0e00 << 16) | (0x9718 >> 2),
810 (0x0e00 << 16) | (0x971c >> 2),
812 (0x0e00 << 16) | (0x31068 >> 2),
814 (0x4e00 << 16) | (0x31068 >> 2),
816 (0x5e00 << 16) | (0x31068 >> 2),
818 (0x6e00 << 16) | (0x31068 >> 2),
820 (0x7e00 << 16) | (0x31068 >> 2),
822 (0x0e00 << 16) | (0xcd10 >> 2),
824 (0x0e00 << 16) | (0xcd14 >> 2),
826 (0x0e00 << 16) | (0x88b0 >> 2),
828 (0x0e00 << 16) | (0x88b4 >> 2),
830 (0x0e00 << 16) | (0x88b8 >> 2),
832 (0x0e00 << 16) | (0x88bc >> 2),
834 (0x0400 << 16) | (0x89c0 >> 2),
836 (0x0e00 << 16) | (0x88c4 >> 2),
838 (0x0e00 << 16) | (0x88c8 >> 2),
840 (0x0e00 << 16) | (0x88d0 >> 2),
842 (0x0e00 << 16) | (0x88d4 >> 2),
844 (0x0e00 << 16) | (0x88d8 >> 2),
846 (0x0e00 << 16) | (0x8980 >> 2),
848 (0x0e00 << 16) | (0x30938 >> 2),
850 (0x0e00 << 16) | (0x3093c >> 2),
852 (0x0e00 << 16) | (0x30940 >> 2),
854 (0x0e00 << 16) | (0x89a0 >> 2),
856 (0x0e00 << 16) | (0x30900 >> 2),
858 (0x0e00 << 16) | (0x30904 >> 2),
860 (0x0e00 << 16) | (0x89b4 >> 2),
862 (0x0e00 << 16) | (0x3e1fc >> 2),
864 (0x0e00 << 16) | (0x3c210 >> 2),
866 (0x0e00 << 16) | (0x3c214 >> 2),
868 (0x0e00 << 16) | (0x3c218 >> 2),
870 (0x0e00 << 16) | (0x8904 >> 2),
873 (0x0e00 << 16) | (0x8c28 >> 2),
874 (0x0e00 << 16) | (0x8c2c >> 2),
875 (0x0e00 << 16) | (0x8c30 >> 2),
876 (0x0e00 << 16) | (0x8c34 >> 2),
877 (0x0e00 << 16) | (0x9600 >> 2),
880 static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev);
881 static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer);
882 static void gfx_v7_0_init_cp_pg_table(struct amdgpu_device *adev);
883 static void gfx_v7_0_init_pg(struct amdgpu_device *adev);
884 static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev);
890 * gfx_v7_0_init_microcode - load ucode images from disk
892 * @adev: amdgpu_device pointer
894 * Use the firmware interface to load the ucode images into
895 * the driver (not loaded into hw).
896 * Returns 0 on success, error on failure.
898 static int gfx_v7_0_init_microcode(struct amdgpu_device *adev)
900 const char *chip_name;
906 switch (adev->asic_type) {
908 chip_name = "bonaire";
911 chip_name = "hawaii";
914 chip_name = "kaveri";
917 chip_name = "kabini";
920 chip_name = "mullins";
925 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
926 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
929 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
933 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
934 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
937 err = amdgpu_ucode_validate(adev->gfx.me_fw);
941 snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name);
942 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
945 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
949 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec.bin", chip_name);
950 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
953 err = amdgpu_ucode_validate(adev->gfx.mec_fw);
957 if (adev->asic_type == CHIP_KAVERI) {
958 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec2.bin", chip_name);
959 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
962 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
967 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", chip_name);
968 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
971 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
976 "gfx7: Failed to load firmware \"%s\"\n",
978 release_firmware(adev->gfx.pfp_fw);
979 adev->gfx.pfp_fw = NULL;
980 release_firmware(adev->gfx.me_fw);
981 adev->gfx.me_fw = NULL;
982 release_firmware(adev->gfx.ce_fw);
983 adev->gfx.ce_fw = NULL;
984 release_firmware(adev->gfx.mec_fw);
985 adev->gfx.mec_fw = NULL;
986 release_firmware(adev->gfx.mec2_fw);
987 adev->gfx.mec2_fw = NULL;
988 release_firmware(adev->gfx.rlc_fw);
989 adev->gfx.rlc_fw = NULL;
995 * gfx_v7_0_tiling_mode_table_init - init the hw tiling table
997 * @adev: amdgpu_device pointer
999 * Starting with SI, the tiling setup is done globally in a
1000 * set of 32 tiling modes. Rather than selecting each set of
1001 * parameters per surface as on older asics, we just select
1002 * which index in the tiling table we want to use, and the
1003 * surface uses those parameters (CIK).
1005 static void gfx_v7_0_tiling_mode_table_init(struct amdgpu_device *adev)
1007 const u32 num_tile_mode_states =
1008 ARRAY_SIZE(adev->gfx.config.tile_mode_array);
1009 const u32 num_secondary_tile_mode_states =
1010 ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
1011 u32 reg_offset, split_equal_to_row_size;
1012 uint32_t *tile, *macrotile;
1014 tile = adev->gfx.config.tile_mode_array;
1015 macrotile = adev->gfx.config.macrotile_mode_array;
1017 switch (adev->gfx.config.mem_row_size_in_kb) {
1019 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
1023 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
1026 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
1030 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1031 tile[reg_offset] = 0;
1032 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1033 macrotile[reg_offset] = 0;
1035 switch (adev->asic_type) {
1037 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1038 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1039 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1040 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1041 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1042 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1043 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1044 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1045 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1046 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1047 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1048 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1049 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1050 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1051 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1052 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1053 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1054 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1055 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1056 TILE_SPLIT(split_equal_to_row_size));
1057 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1058 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1059 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1060 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1061 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1062 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1063 TILE_SPLIT(split_equal_to_row_size));
1064 tile[7] = (TILE_SPLIT(split_equal_to_row_size));
1065 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1066 PIPE_CONFIG(ADDR_SURF_P4_16x16));
1067 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1068 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1069 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1070 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1071 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1072 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1073 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1074 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1075 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1076 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1077 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1078 tile[12] = (TILE_SPLIT(split_equal_to_row_size));
1079 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1080 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1081 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1082 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1083 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1084 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1085 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1086 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1087 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1088 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1089 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1090 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1091 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1092 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1093 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1094 tile[17] = (TILE_SPLIT(split_equal_to_row_size));
1095 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1096 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1097 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1098 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1099 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1100 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1101 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1102 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1103 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1104 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1105 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1106 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1107 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1108 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1109 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1110 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1111 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1112 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1113 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1114 tile[23] = (TILE_SPLIT(split_equal_to_row_size));
1115 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1116 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1117 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1118 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1119 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1120 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1121 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1122 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1123 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1124 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1125 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1126 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1127 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1128 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1129 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1130 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1131 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1132 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1133 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1134 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1135 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1136 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1137 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1138 tile[30] = (TILE_SPLIT(split_equal_to_row_size));
1140 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1141 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1142 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1143 NUM_BANKS(ADDR_SURF_16_BANK));
1144 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1145 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1146 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1147 NUM_BANKS(ADDR_SURF_16_BANK));
1148 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1149 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1150 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1151 NUM_BANKS(ADDR_SURF_16_BANK));
1152 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1153 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1154 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1155 NUM_BANKS(ADDR_SURF_16_BANK));
1156 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1157 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1158 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1159 NUM_BANKS(ADDR_SURF_16_BANK));
1160 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1161 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1162 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1163 NUM_BANKS(ADDR_SURF_8_BANK));
1164 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1165 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1166 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1167 NUM_BANKS(ADDR_SURF_4_BANK));
1168 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1169 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1170 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1171 NUM_BANKS(ADDR_SURF_16_BANK));
1172 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1173 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1174 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1175 NUM_BANKS(ADDR_SURF_16_BANK));
1176 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1177 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1178 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1179 NUM_BANKS(ADDR_SURF_16_BANK));
1180 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1181 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1182 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1183 NUM_BANKS(ADDR_SURF_16_BANK));
1184 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1185 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1186 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1187 NUM_BANKS(ADDR_SURF_16_BANK));
1188 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1189 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1190 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1191 NUM_BANKS(ADDR_SURF_8_BANK));
1192 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1193 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1194 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1195 NUM_BANKS(ADDR_SURF_4_BANK));
1197 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1198 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
1199 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1200 if (reg_offset != 7)
1201 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
1204 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1205 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1206 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1207 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1208 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1209 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1210 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1211 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1212 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1213 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1214 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1215 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1216 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1217 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1218 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1219 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1220 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1221 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1222 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1223 TILE_SPLIT(split_equal_to_row_size));
1224 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1225 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1226 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1227 TILE_SPLIT(split_equal_to_row_size));
1228 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1229 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1230 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1231 TILE_SPLIT(split_equal_to_row_size));
1232 tile[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1233 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1234 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1235 TILE_SPLIT(split_equal_to_row_size));
1236 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1237 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
1238 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1239 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1240 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1241 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1242 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1243 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1244 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1245 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1246 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1247 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1248 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1249 tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
1250 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1251 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1252 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1253 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1254 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1255 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1256 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1257 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1258 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1259 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1260 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1261 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1262 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1263 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1264 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1265 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1266 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1267 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1268 tile[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1269 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1270 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1271 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1272 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1273 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1274 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1275 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1276 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1277 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1278 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING));
1279 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1280 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1281 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1282 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1283 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1284 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1285 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1286 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1287 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1288 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1289 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1290 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1291 tile[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1292 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1293 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1294 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1295 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1296 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1297 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1298 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1299 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1300 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1301 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1302 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1303 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1304 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1305 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1306 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1307 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1308 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1309 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1310 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1311 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1312 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1313 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1314 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1315 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1316 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1317 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1318 tile[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1319 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1320 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1321 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1323 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1324 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1325 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1326 NUM_BANKS(ADDR_SURF_16_BANK));
1327 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1328 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1329 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1330 NUM_BANKS(ADDR_SURF_16_BANK));
1331 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1332 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1333 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1334 NUM_BANKS(ADDR_SURF_16_BANK));
1335 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1336 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1337 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1338 NUM_BANKS(ADDR_SURF_16_BANK));
1339 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1340 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1341 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1342 NUM_BANKS(ADDR_SURF_8_BANK));
1343 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1344 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1345 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1346 NUM_BANKS(ADDR_SURF_4_BANK));
1347 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1348 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1349 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1350 NUM_BANKS(ADDR_SURF_4_BANK));
1351 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1352 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1353 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1354 NUM_BANKS(ADDR_SURF_16_BANK));
1355 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1356 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1357 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1358 NUM_BANKS(ADDR_SURF_16_BANK));
1359 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1360 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1361 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1362 NUM_BANKS(ADDR_SURF_16_BANK));
1363 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1364 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1365 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1366 NUM_BANKS(ADDR_SURF_8_BANK));
1367 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1368 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1369 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1370 NUM_BANKS(ADDR_SURF_16_BANK));
1371 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1372 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1373 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1374 NUM_BANKS(ADDR_SURF_8_BANK));
1375 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1376 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1377 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1378 NUM_BANKS(ADDR_SURF_4_BANK));
1380 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1381 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
1382 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1383 if (reg_offset != 7)
1384 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
1390 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1391 PIPE_CONFIG(ADDR_SURF_P2) |
1392 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1393 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1394 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1395 PIPE_CONFIG(ADDR_SURF_P2) |
1396 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1397 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1398 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1399 PIPE_CONFIG(ADDR_SURF_P2) |
1400 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1401 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1402 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1403 PIPE_CONFIG(ADDR_SURF_P2) |
1404 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1405 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1406 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1407 PIPE_CONFIG(ADDR_SURF_P2) |
1408 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1409 TILE_SPLIT(split_equal_to_row_size));
1410 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1411 PIPE_CONFIG(ADDR_SURF_P2) |
1412 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1413 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1414 PIPE_CONFIG(ADDR_SURF_P2) |
1415 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1416 TILE_SPLIT(split_equal_to_row_size));
1417 tile[7] = (TILE_SPLIT(split_equal_to_row_size));
1418 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1419 PIPE_CONFIG(ADDR_SURF_P2));
1420 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1421 PIPE_CONFIG(ADDR_SURF_P2) |
1422 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1423 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1424 PIPE_CONFIG(ADDR_SURF_P2) |
1425 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1426 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1427 tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1428 PIPE_CONFIG(ADDR_SURF_P2) |
1429 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1430 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1431 tile[12] = (TILE_SPLIT(split_equal_to_row_size));
1432 tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1433 PIPE_CONFIG(ADDR_SURF_P2) |
1434 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1435 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1436 PIPE_CONFIG(ADDR_SURF_P2) |
1437 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1438 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1439 tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1440 PIPE_CONFIG(ADDR_SURF_P2) |
1441 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1442 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1443 tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1444 PIPE_CONFIG(ADDR_SURF_P2) |
1445 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1446 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1447 tile[17] = (TILE_SPLIT(split_equal_to_row_size));
1448 tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1449 PIPE_CONFIG(ADDR_SURF_P2) |
1450 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1451 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1452 tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1453 PIPE_CONFIG(ADDR_SURF_P2) |
1454 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING));
1455 tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1456 PIPE_CONFIG(ADDR_SURF_P2) |
1457 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1458 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1459 tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1460 PIPE_CONFIG(ADDR_SURF_P2) |
1461 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1462 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1463 tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1464 PIPE_CONFIG(ADDR_SURF_P2) |
1465 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1466 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1467 tile[23] = (TILE_SPLIT(split_equal_to_row_size));
1468 tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1469 PIPE_CONFIG(ADDR_SURF_P2) |
1470 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1471 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1472 tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1473 PIPE_CONFIG(ADDR_SURF_P2) |
1474 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1475 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1476 tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1477 PIPE_CONFIG(ADDR_SURF_P2) |
1478 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1479 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1480 tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1481 PIPE_CONFIG(ADDR_SURF_P2) |
1482 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1483 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1484 PIPE_CONFIG(ADDR_SURF_P2) |
1485 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1486 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1487 tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1488 PIPE_CONFIG(ADDR_SURF_P2) |
1489 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1490 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1491 tile[30] = (TILE_SPLIT(split_equal_to_row_size));
1493 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1494 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1495 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1496 NUM_BANKS(ADDR_SURF_8_BANK));
1497 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1498 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1499 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1500 NUM_BANKS(ADDR_SURF_8_BANK));
1501 macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1502 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1503 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1504 NUM_BANKS(ADDR_SURF_8_BANK));
1505 macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1506 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1507 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1508 NUM_BANKS(ADDR_SURF_8_BANK));
1509 macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1510 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1511 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1512 NUM_BANKS(ADDR_SURF_8_BANK));
1513 macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1514 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1515 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1516 NUM_BANKS(ADDR_SURF_8_BANK));
1517 macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1518 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1519 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1520 NUM_BANKS(ADDR_SURF_8_BANK));
1521 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1522 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1523 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1524 NUM_BANKS(ADDR_SURF_16_BANK));
1525 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1526 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1527 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1528 NUM_BANKS(ADDR_SURF_16_BANK));
1529 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1530 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1531 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1532 NUM_BANKS(ADDR_SURF_16_BANK));
1533 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1534 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1535 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1536 NUM_BANKS(ADDR_SURF_16_BANK));
1537 macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1538 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1539 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1540 NUM_BANKS(ADDR_SURF_16_BANK));
1541 macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1542 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1543 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1544 NUM_BANKS(ADDR_SURF_16_BANK));
1545 macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1546 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1547 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1548 NUM_BANKS(ADDR_SURF_8_BANK));
1550 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1551 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
1552 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1553 if (reg_offset != 7)
1554 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
1560 * gfx_v7_0_select_se_sh - select which SE, SH to address
1562 * @adev: amdgpu_device pointer
1563 * @se_num: shader engine to address
1564 * @sh_num: sh block to address
1566 * Select which SE, SH combinations to address. Certain
1567 * registers are instanced per SE or SH. 0xffffffff means
1568 * broadcast to all SEs or SHs (CIK).
1570 void gfx_v7_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num)
1572 u32 data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK;
1574 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
1575 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1576 GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK;
1577 else if (se_num == 0xffffffff)
1578 data |= GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK |
1579 (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT);
1580 else if (sh_num == 0xffffffff)
1581 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1582 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1584 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) |
1585 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1586 WREG32(mmGRBM_GFX_INDEX, data);
1590 * gfx_v7_0_create_bitmask - create a bitmask
1592 * @bit_width: length of the mask
1594 * create a variable length bit mask (CIK).
1595 * Returns the bitmask.
1597 static u32 gfx_v7_0_create_bitmask(u32 bit_width)
1599 return (u32)((1ULL << bit_width) - 1);
1603 * gfx_v7_0_get_rb_active_bitmap - computes the mask of enabled RBs
1605 * @adev: amdgpu_device pointer
1607 * Calculates the bitmask of enabled RBs (CIK).
1608 * Returns the enabled RB bitmask.
1610 static u32 gfx_v7_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1614 data = RREG32(mmCC_RB_BACKEND_DISABLE);
1615 data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1617 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
1618 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1620 mask = gfx_v7_0_create_bitmask(adev->gfx.config.max_backends_per_se /
1621 adev->gfx.config.max_sh_per_se);
1623 return (~data) & mask;
1627 * gfx_v7_0_setup_rb - setup the RBs on the asic
1629 * @adev: amdgpu_device pointer
1630 * @se_num: number of SEs (shader engines) for the asic
1631 * @sh_per_se: number of SH blocks per SE for the asic
1633 * Configures per-SE/SH RB registers (CIK).
1635 static void gfx_v7_0_setup_rb(struct amdgpu_device *adev)
1640 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1641 adev->gfx.config.max_sh_per_se;
1643 mutex_lock(&adev->grbm_idx_mutex);
1644 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1645 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1646 gfx_v7_0_select_se_sh(adev, i, j);
1647 data = gfx_v7_0_get_rb_active_bitmap(adev);
1648 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
1649 rb_bitmap_width_per_sh);
1652 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
1653 mutex_unlock(&adev->grbm_idx_mutex);
1655 adev->gfx.config.backend_enable_mask = active_rbs;
1656 adev->gfx.config.num_rbs = hweight32(active_rbs);
1660 * gmc_v7_0_init_compute_vmid - gart enable
1662 * @rdev: amdgpu_device pointer
1664 * Initialize compute vmid sh_mem registers
1667 #define DEFAULT_SH_MEM_BASES (0x6000)
1668 #define FIRST_COMPUTE_VMID (8)
1669 #define LAST_COMPUTE_VMID (16)
1670 static void gmc_v7_0_init_compute_vmid(struct amdgpu_device *adev)
1673 uint32_t sh_mem_config;
1674 uint32_t sh_mem_bases;
1677 * Configure apertures:
1678 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
1679 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
1680 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
1682 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
1683 sh_mem_config = SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
1684 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
1685 sh_mem_config |= MTYPE_NONCACHED << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT;
1686 mutex_lock(&adev->srbm_mutex);
1687 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
1688 cik_srbm_select(adev, 0, 0, 0, i);
1689 /* CP and shaders */
1690 WREG32(mmSH_MEM_CONFIG, sh_mem_config);
1691 WREG32(mmSH_MEM_APE1_BASE, 1);
1692 WREG32(mmSH_MEM_APE1_LIMIT, 0);
1693 WREG32(mmSH_MEM_BASES, sh_mem_bases);
1695 cik_srbm_select(adev, 0, 0, 0, 0);
1696 mutex_unlock(&adev->srbm_mutex);
1700 * gfx_v7_0_gpu_init - setup the 3D engine
1702 * @adev: amdgpu_device pointer
1704 * Configures the 3D engine and tiling configuration
1705 * registers so that the 3D engine is usable.
1707 static void gfx_v7_0_gpu_init(struct amdgpu_device *adev)
1709 u32 tmp, sh_mem_cfg;
1712 WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT));
1714 WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
1715 WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
1716 WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config);
1718 gfx_v7_0_tiling_mode_table_init(adev);
1720 gfx_v7_0_setup_rb(adev);
1721 gfx_v7_0_get_cu_info(adev);
1723 /* set HW defaults for 3D engine */
1724 WREG32(mmCP_MEQ_THRESHOLDS,
1725 (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) |
1726 (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT));
1728 mutex_lock(&adev->grbm_idx_mutex);
1730 * making sure that the following register writes will be broadcasted
1731 * to all the shaders
1733 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
1735 /* XXX SH_MEM regs */
1736 /* where to put LDS, scratch, GPUVM in FSA64 space */
1737 sh_mem_cfg = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
1738 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
1740 mutex_lock(&adev->srbm_mutex);
1741 for (i = 0; i < 16; i++) {
1742 cik_srbm_select(adev, 0, 0, 0, i);
1743 /* CP and shaders */
1744 WREG32(mmSH_MEM_CONFIG, sh_mem_cfg);
1745 WREG32(mmSH_MEM_APE1_BASE, 1);
1746 WREG32(mmSH_MEM_APE1_LIMIT, 0);
1747 WREG32(mmSH_MEM_BASES, 0);
1749 cik_srbm_select(adev, 0, 0, 0, 0);
1750 mutex_unlock(&adev->srbm_mutex);
1752 gmc_v7_0_init_compute_vmid(adev);
1754 WREG32(mmSX_DEBUG_1, 0x20);
1756 WREG32(mmTA_CNTL_AUX, 0x00010000);
1758 tmp = RREG32(mmSPI_CONFIG_CNTL);
1760 WREG32(mmSPI_CONFIG_CNTL, tmp);
1762 WREG32(mmSQ_CONFIG, 1);
1764 WREG32(mmDB_DEBUG, 0);
1766 tmp = RREG32(mmDB_DEBUG2) & ~0xf00fffff;
1768 WREG32(mmDB_DEBUG2, tmp);
1770 tmp = RREG32(mmDB_DEBUG3) & ~0x0002021c;
1772 WREG32(mmDB_DEBUG3, tmp);
1774 tmp = RREG32(mmCB_HW_CONTROL) & ~0x00010000;
1776 WREG32(mmCB_HW_CONTROL, tmp);
1778 WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT));
1780 WREG32(mmPA_SC_FIFO_SIZE,
1781 ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
1782 (adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
1783 (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
1784 (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT)));
1786 WREG32(mmVGT_NUM_INSTANCES, 1);
1788 WREG32(mmCP_PERFMON_CNTL, 0);
1790 WREG32(mmSQ_CONFIG, 0);
1792 WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS,
1793 ((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT) |
1794 (255 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT)));
1796 WREG32(mmVGT_CACHE_INVALIDATION,
1797 (VC_AND_TC << VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT) |
1798 (ES_AND_GS_AUTO << VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT));
1800 WREG32(mmVGT_GS_VERTEX_REUSE, 16);
1801 WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0);
1803 WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK |
1804 (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT));
1805 WREG32(mmPA_SC_ENHANCE, PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK);
1806 mutex_unlock(&adev->grbm_idx_mutex);
1812 * GPU scratch registers helpers function.
1815 * gfx_v7_0_scratch_init - setup driver info for CP scratch regs
1817 * @adev: amdgpu_device pointer
1819 * Set up the number and offset of the CP scratch registers.
1820 * NOTE: use of CP scratch registers is a legacy inferface and
1821 * is not used by default on newer asics (r6xx+). On newer asics,
1822 * memory buffers are used for fences rather than scratch regs.
1824 static void gfx_v7_0_scratch_init(struct amdgpu_device *adev)
1828 adev->gfx.scratch.num_reg = 7;
1829 adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
1830 for (i = 0; i < adev->gfx.scratch.num_reg; i++) {
1831 adev->gfx.scratch.free[i] = true;
1832 adev->gfx.scratch.reg[i] = adev->gfx.scratch.reg_base + i;
1837 * gfx_v7_0_ring_test_ring - basic gfx ring test
1839 * @adev: amdgpu_device pointer
1840 * @ring: amdgpu_ring structure holding ring information
1842 * Allocate a scratch register and write to it using the gfx ring (CIK).
1843 * Provides a basic gfx ring test to verify that the ring is working.
1844 * Used by gfx_v7_0_cp_gfx_resume();
1845 * Returns 0 on success, error on failure.
1847 static int gfx_v7_0_ring_test_ring(struct amdgpu_ring *ring)
1849 struct amdgpu_device *adev = ring->adev;
1855 r = amdgpu_gfx_scratch_get(adev, &scratch);
1857 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
1860 WREG32(scratch, 0xCAFEDEAD);
1861 r = amdgpu_ring_alloc(ring, 3);
1863 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", ring->idx, r);
1864 amdgpu_gfx_scratch_free(adev, scratch);
1867 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
1868 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
1869 amdgpu_ring_write(ring, 0xDEADBEEF);
1870 amdgpu_ring_commit(ring);
1872 for (i = 0; i < adev->usec_timeout; i++) {
1873 tmp = RREG32(scratch);
1874 if (tmp == 0xDEADBEEF)
1878 if (i < adev->usec_timeout) {
1879 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
1881 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
1882 ring->idx, scratch, tmp);
1885 amdgpu_gfx_scratch_free(adev, scratch);
1890 * gfx_v7_0_ring_emit_hdp - emit an hdp flush on the cp
1892 * @adev: amdgpu_device pointer
1893 * @ridx: amdgpu ring index
1895 * Emits an hdp flush on the cp.
1897 static void gfx_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
1900 int usepfp = ring->type == AMDGPU_RING_TYPE_COMPUTE ? 0 : 1;
1902 if (ring->type == AMDGPU_RING_TYPE_COMPUTE) {
1905 ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe;
1908 ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe;
1914 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK;
1917 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
1918 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */
1919 WAIT_REG_MEM_FUNCTION(3) | /* == */
1920 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */
1921 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ);
1922 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE);
1923 amdgpu_ring_write(ring, ref_and_mask);
1924 amdgpu_ring_write(ring, ref_and_mask);
1925 amdgpu_ring_write(ring, 0x20); /* poll interval */
1929 * gfx_v7_0_ring_emit_hdp_invalidate - emit an hdp invalidate on the cp
1931 * @adev: amdgpu_device pointer
1932 * @ridx: amdgpu ring index
1934 * Emits an hdp invalidate on the cp.
1936 static void gfx_v7_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
1938 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
1939 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
1940 WRITE_DATA_DST_SEL(0) |
1942 amdgpu_ring_write(ring, mmHDP_DEBUG0);
1943 amdgpu_ring_write(ring, 0);
1944 amdgpu_ring_write(ring, 1);
1948 * gfx_v7_0_ring_emit_fence_gfx - emit a fence on the gfx ring
1950 * @adev: amdgpu_device pointer
1951 * @fence: amdgpu fence object
1953 * Emits a fence sequnce number on the gfx ring and flushes
1956 static void gfx_v7_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
1957 u64 seq, unsigned flags)
1959 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
1960 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
1961 /* Workaround for cache flush problems. First send a dummy EOP
1962 * event down the pipe with seq one below.
1964 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1965 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
1967 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
1969 amdgpu_ring_write(ring, addr & 0xfffffffc);
1970 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
1971 DATA_SEL(1) | INT_SEL(0));
1972 amdgpu_ring_write(ring, lower_32_bits(seq - 1));
1973 amdgpu_ring_write(ring, upper_32_bits(seq - 1));
1975 /* Then send the real EOP event down the pipe. */
1976 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1977 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
1979 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
1981 amdgpu_ring_write(ring, addr & 0xfffffffc);
1982 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
1983 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
1984 amdgpu_ring_write(ring, lower_32_bits(seq));
1985 amdgpu_ring_write(ring, upper_32_bits(seq));
1989 * gfx_v7_0_ring_emit_fence_compute - emit a fence on the compute ring
1991 * @adev: amdgpu_device pointer
1992 * @fence: amdgpu fence object
1994 * Emits a fence sequnce number on the compute ring and flushes
1997 static void gfx_v7_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
2001 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
2002 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
2004 /* RELEASE_MEM - flush caches, send int */
2005 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));
2006 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
2008 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
2010 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
2011 amdgpu_ring_write(ring, addr & 0xfffffffc);
2012 amdgpu_ring_write(ring, upper_32_bits(addr));
2013 amdgpu_ring_write(ring, lower_32_bits(seq));
2014 amdgpu_ring_write(ring, upper_32_bits(seq));
2021 * gfx_v7_0_ring_emit_ib - emit an IB (Indirect Buffer) on the ring
2023 * @ring: amdgpu_ring structure holding ring information
2024 * @ib: amdgpu indirect buffer object
2026 * Emits an DE (drawing engine) or CE (constant engine) IB
2027 * on the gfx ring. IBs are usually generated by userspace
2028 * acceleration drivers and submitted to the kernel for
2029 * sheduling on the ring. This function schedules the IB
2030 * on the gfx ring for execution by the GPU.
2032 static void gfx_v7_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
2033 struct amdgpu_ib *ib,
2034 unsigned vm_id, bool ctx_switch)
2036 u32 header, control = 0;
2037 u32 next_rptr = ring->wptr + 5;
2043 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2044 amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM);
2045 amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
2046 amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
2047 amdgpu_ring_write(ring, next_rptr);
2049 /* insert SWITCH_BUFFER packet before first IB in the ring frame */
2051 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2052 amdgpu_ring_write(ring, 0);
2055 if (ib->flags & AMDGPU_IB_FLAG_CE)
2056 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
2058 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
2060 control |= ib->length_dw | (vm_id << 24);
2062 amdgpu_ring_write(ring, header);
2063 amdgpu_ring_write(ring,
2067 (ib->gpu_addr & 0xFFFFFFFC));
2068 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
2069 amdgpu_ring_write(ring, control);
2072 static void gfx_v7_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
2073 struct amdgpu_ib *ib,
2074 unsigned vm_id, bool ctx_switch)
2076 u32 header, control = 0;
2077 u32 next_rptr = ring->wptr + 5;
2079 control |= INDIRECT_BUFFER_VALID;
2081 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2082 amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM);
2083 amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
2084 amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
2085 amdgpu_ring_write(ring, next_rptr);
2087 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
2089 control |= ib->length_dw | (vm_id << 24);
2091 amdgpu_ring_write(ring, header);
2092 amdgpu_ring_write(ring,
2096 (ib->gpu_addr & 0xFFFFFFFC));
2097 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
2098 amdgpu_ring_write(ring, control);
2102 * gfx_v7_0_ring_test_ib - basic ring IB test
2104 * @ring: amdgpu_ring structure holding ring information
2106 * Allocate an IB and execute it on the gfx ring (CIK).
2107 * Provides a basic gfx ring test to verify that IBs are working.
2108 * Returns 0 on success, error on failure.
2110 static int gfx_v7_0_ring_test_ib(struct amdgpu_ring *ring)
2112 struct amdgpu_device *adev = ring->adev;
2113 struct amdgpu_ib ib;
2114 struct fence *f = NULL;
2120 r = amdgpu_gfx_scratch_get(adev, &scratch);
2122 DRM_ERROR("amdgpu: failed to get scratch reg (%d).\n", r);
2125 WREG32(scratch, 0xCAFEDEAD);
2126 memset(&ib, 0, sizeof(ib));
2127 r = amdgpu_ib_get(adev, NULL, 256, &ib);
2129 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
2132 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
2133 ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
2134 ib.ptr[2] = 0xDEADBEEF;
2137 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f);
2141 r = fence_wait(f, false);
2143 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
2146 for (i = 0; i < adev->usec_timeout; i++) {
2147 tmp = RREG32(scratch);
2148 if (tmp == 0xDEADBEEF)
2152 if (i < adev->usec_timeout) {
2153 DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
2157 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
2164 amdgpu_ib_free(adev, &ib, NULL);
2167 amdgpu_gfx_scratch_free(adev, scratch);
2173 * On CIK, gfx and compute now have independant command processors.
2176 * Gfx consists of a single ring and can process both gfx jobs and
2177 * compute jobs. The gfx CP consists of three microengines (ME):
2178 * PFP - Pre-Fetch Parser
2180 * CE - Constant Engine
2181 * The PFP and ME make up what is considered the Drawing Engine (DE).
2182 * The CE is an asynchronous engine used for updating buffer desciptors
2183 * used by the DE so that they can be loaded into cache in parallel
2184 * while the DE is processing state update packets.
2187 * The compute CP consists of two microengines (ME):
2188 * MEC1 - Compute MicroEngine 1
2189 * MEC2 - Compute MicroEngine 2
2190 * Each MEC supports 4 compute pipes and each pipe supports 8 queues.
2191 * The queues are exposed to userspace and are programmed directly
2192 * by the compute runtime.
2195 * gfx_v7_0_cp_gfx_enable - enable/disable the gfx CP MEs
2197 * @adev: amdgpu_device pointer
2198 * @enable: enable or disable the MEs
2200 * Halts or unhalts the gfx MEs.
2202 static void gfx_v7_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2207 WREG32(mmCP_ME_CNTL, 0);
2209 WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK));
2210 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2211 adev->gfx.gfx_ring[i].ready = false;
2217 * gfx_v7_0_cp_gfx_load_microcode - load the gfx CP ME ucode
2219 * @adev: amdgpu_device pointer
2221 * Loads the gfx PFP, ME, and CE ucode.
2222 * Returns 0 for success, -EINVAL if the ucode is not available.
2224 static int gfx_v7_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2226 const struct gfx_firmware_header_v1_0 *pfp_hdr;
2227 const struct gfx_firmware_header_v1_0 *ce_hdr;
2228 const struct gfx_firmware_header_v1_0 *me_hdr;
2229 const __le32 *fw_data;
2230 unsigned i, fw_size;
2232 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2235 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
2236 ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
2237 me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
2239 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2240 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2241 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2242 adev->gfx.pfp_fw_version = le32_to_cpu(pfp_hdr->header.ucode_version);
2243 adev->gfx.ce_fw_version = le32_to_cpu(ce_hdr->header.ucode_version);
2244 adev->gfx.me_fw_version = le32_to_cpu(me_hdr->header.ucode_version);
2245 adev->gfx.me_feature_version = le32_to_cpu(me_hdr->ucode_feature_version);
2246 adev->gfx.ce_feature_version = le32_to_cpu(ce_hdr->ucode_feature_version);
2247 adev->gfx.pfp_feature_version = le32_to_cpu(pfp_hdr->ucode_feature_version);
2249 gfx_v7_0_cp_gfx_enable(adev, false);
2252 fw_data = (const __le32 *)
2253 (adev->gfx.pfp_fw->data +
2254 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2255 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
2256 WREG32(mmCP_PFP_UCODE_ADDR, 0);
2257 for (i = 0; i < fw_size; i++)
2258 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
2259 WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
2262 fw_data = (const __le32 *)
2263 (adev->gfx.ce_fw->data +
2264 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2265 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
2266 WREG32(mmCP_CE_UCODE_ADDR, 0);
2267 for (i = 0; i < fw_size; i++)
2268 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
2269 WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
2272 fw_data = (const __le32 *)
2273 (adev->gfx.me_fw->data +
2274 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2275 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
2276 WREG32(mmCP_ME_RAM_WADDR, 0);
2277 for (i = 0; i < fw_size; i++)
2278 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2279 WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
2285 * gfx_v7_0_cp_gfx_start - start the gfx ring
2287 * @adev: amdgpu_device pointer
2289 * Enables the ring and loads the clear state context and other
2290 * packets required to init the ring.
2291 * Returns 0 for success, error for failure.
2293 static int gfx_v7_0_cp_gfx_start(struct amdgpu_device *adev)
2295 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2296 const struct cs_section_def *sect = NULL;
2297 const struct cs_extent_def *ext = NULL;
2301 WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
2302 WREG32(mmCP_ENDIAN_SWAP, 0);
2303 WREG32(mmCP_DEVICE_ID, 1);
2305 gfx_v7_0_cp_gfx_enable(adev, true);
2307 r = amdgpu_ring_alloc(ring, gfx_v7_0_get_csb_size(adev) + 8);
2309 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2313 /* init the CE partitions. CE only used for gfx on CIK */
2314 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2315 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2316 amdgpu_ring_write(ring, 0x8000);
2317 amdgpu_ring_write(ring, 0x8000);
2319 /* clear state buffer */
2320 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2321 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2323 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2324 amdgpu_ring_write(ring, 0x80000000);
2325 amdgpu_ring_write(ring, 0x80000000);
2327 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2328 for (ext = sect->section; ext->extent != NULL; ++ext) {
2329 if (sect->id == SECT_CONTEXT) {
2330 amdgpu_ring_write(ring,
2331 PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
2332 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2333 for (i = 0; i < ext->reg_count; i++)
2334 amdgpu_ring_write(ring, ext->extent[i]);
2339 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2340 amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
2341 switch (adev->asic_type) {
2343 amdgpu_ring_write(ring, 0x16000012);
2344 amdgpu_ring_write(ring, 0x00000000);
2347 amdgpu_ring_write(ring, 0x00000000); /* XXX */
2348 amdgpu_ring_write(ring, 0x00000000);
2352 amdgpu_ring_write(ring, 0x00000000); /* XXX */
2353 amdgpu_ring_write(ring, 0x00000000);
2356 amdgpu_ring_write(ring, 0x3a00161a);
2357 amdgpu_ring_write(ring, 0x0000002e);
2360 amdgpu_ring_write(ring, 0x00000000);
2361 amdgpu_ring_write(ring, 0x00000000);
2365 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2366 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2368 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2369 amdgpu_ring_write(ring, 0);
2371 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2372 amdgpu_ring_write(ring, 0x00000316);
2373 amdgpu_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
2374 amdgpu_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */
2376 amdgpu_ring_commit(ring);
2382 * gfx_v7_0_cp_gfx_resume - setup the gfx ring buffer registers
2384 * @adev: amdgpu_device pointer
2386 * Program the location and size of the gfx ring buffer
2387 * and test it to make sure it's working.
2388 * Returns 0 for success, error for failure.
2390 static int gfx_v7_0_cp_gfx_resume(struct amdgpu_device *adev)
2392 struct amdgpu_ring *ring;
2395 u64 rb_addr, rptr_addr;
2398 WREG32(mmCP_SEM_WAIT_TIMER, 0x0);
2399 if (adev->asic_type != CHIP_HAWAII)
2400 WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
2402 /* Set the write pointer delay */
2403 WREG32(mmCP_RB_WPTR_DELAY, 0);
2405 /* set the RB to use vmid 0 */
2406 WREG32(mmCP_RB_VMID, 0);
2408 WREG32(mmSCRATCH_ADDR, 0);
2410 /* ring 0 - compute and gfx */
2411 /* Set ring buffer size */
2412 ring = &adev->gfx.gfx_ring[0];
2413 rb_bufsz = order_base_2(ring->ring_size / 8);
2414 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2416 tmp |= 2 << CP_RB0_CNTL__BUF_SWAP__SHIFT;
2418 WREG32(mmCP_RB0_CNTL, tmp);
2420 /* Initialize the ring buffer's read and write pointers */
2421 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
2423 WREG32(mmCP_RB0_WPTR, ring->wptr);
2425 /* set the wb address wether it's enabled or not */
2426 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2427 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2428 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2430 /* scratch register shadowing is no longer supported */
2431 WREG32(mmSCRATCH_UMSK, 0);
2434 WREG32(mmCP_RB0_CNTL, tmp);
2436 rb_addr = ring->gpu_addr >> 8;
2437 WREG32(mmCP_RB0_BASE, rb_addr);
2438 WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
2440 /* start the ring */
2441 gfx_v7_0_cp_gfx_start(adev);
2443 r = amdgpu_ring_test_ring(ring);
2445 ring->ready = false;
2452 static u32 gfx_v7_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
2454 return ring->adev->wb.wb[ring->rptr_offs];
2457 static u32 gfx_v7_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
2459 struct amdgpu_device *adev = ring->adev;
2461 return RREG32(mmCP_RB0_WPTR);
2464 static void gfx_v7_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
2466 struct amdgpu_device *adev = ring->adev;
2468 WREG32(mmCP_RB0_WPTR, ring->wptr);
2469 (void)RREG32(mmCP_RB0_WPTR);
2472 static u32 gfx_v7_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
2474 return ring->adev->wb.wb[ring->rptr_offs];
2477 static u32 gfx_v7_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
2479 /* XXX check if swapping is necessary on BE */
2480 return ring->adev->wb.wb[ring->wptr_offs];
2483 static void gfx_v7_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
2485 struct amdgpu_device *adev = ring->adev;
2487 /* XXX check if swapping is necessary on BE */
2488 adev->wb.wb[ring->wptr_offs] = ring->wptr;
2489 WDOORBELL32(ring->doorbell_index, ring->wptr);
2493 * gfx_v7_0_cp_compute_enable - enable/disable the compute CP MEs
2495 * @adev: amdgpu_device pointer
2496 * @enable: enable or disable the MEs
2498 * Halts or unhalts the compute MEs.
2500 static void gfx_v7_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
2505 WREG32(mmCP_MEC_CNTL, 0);
2507 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
2508 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2509 adev->gfx.compute_ring[i].ready = false;
2515 * gfx_v7_0_cp_compute_load_microcode - load the compute CP ME ucode
2517 * @adev: amdgpu_device pointer
2519 * Loads the compute MEC1&2 ucode.
2520 * Returns 0 for success, -EINVAL if the ucode is not available.
2522 static int gfx_v7_0_cp_compute_load_microcode(struct amdgpu_device *adev)
2524 const struct gfx_firmware_header_v1_0 *mec_hdr;
2525 const __le32 *fw_data;
2526 unsigned i, fw_size;
2528 if (!adev->gfx.mec_fw)
2531 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2532 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
2533 adev->gfx.mec_fw_version = le32_to_cpu(mec_hdr->header.ucode_version);
2534 adev->gfx.mec_feature_version = le32_to_cpu(
2535 mec_hdr->ucode_feature_version);
2537 gfx_v7_0_cp_compute_enable(adev, false);
2540 fw_data = (const __le32 *)
2541 (adev->gfx.mec_fw->data +
2542 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
2543 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
2544 WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
2545 for (i = 0; i < fw_size; i++)
2546 WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data++));
2547 WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
2549 if (adev->asic_type == CHIP_KAVERI) {
2550 const struct gfx_firmware_header_v1_0 *mec2_hdr;
2552 if (!adev->gfx.mec2_fw)
2555 mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
2556 amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header);
2557 adev->gfx.mec2_fw_version = le32_to_cpu(mec2_hdr->header.ucode_version);
2558 adev->gfx.mec2_feature_version = le32_to_cpu(
2559 mec2_hdr->ucode_feature_version);
2562 fw_data = (const __le32 *)
2563 (adev->gfx.mec2_fw->data +
2564 le32_to_cpu(mec2_hdr->header.ucode_array_offset_bytes));
2565 fw_size = le32_to_cpu(mec2_hdr->header.ucode_size_bytes) / 4;
2566 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
2567 for (i = 0; i < fw_size; i++)
2568 WREG32(mmCP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data++));
2569 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
2576 * gfx_v7_0_cp_compute_fini - stop the compute queues
2578 * @adev: amdgpu_device pointer
2580 * Stop the compute queues and tear down the driver queue
2583 static void gfx_v7_0_cp_compute_fini(struct amdgpu_device *adev)
2587 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2588 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
2590 if (ring->mqd_obj) {
2591 r = amdgpu_bo_reserve(ring->mqd_obj, false);
2592 if (unlikely(r != 0))
2593 dev_warn(adev->dev, "(%d) reserve MQD bo failed\n", r);
2595 amdgpu_bo_unpin(ring->mqd_obj);
2596 amdgpu_bo_unreserve(ring->mqd_obj);
2598 amdgpu_bo_unref(&ring->mqd_obj);
2599 ring->mqd_obj = NULL;
2604 static void gfx_v7_0_mec_fini(struct amdgpu_device *adev)
2608 if (adev->gfx.mec.hpd_eop_obj) {
2609 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
2610 if (unlikely(r != 0))
2611 dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r);
2612 amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj);
2613 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
2615 amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj);
2616 adev->gfx.mec.hpd_eop_obj = NULL;
2620 #define MEC_HPD_SIZE 2048
2622 static int gfx_v7_0_mec_init(struct amdgpu_device *adev)
2628 * KV: 2 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 64 Queues total
2629 * CI/KB: 1 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 32 Queues total
2630 * Nonetheless, we assign only 1 pipe because all other pipes will
2633 adev->gfx.mec.num_mec = 1;
2634 adev->gfx.mec.num_pipe = 1;
2635 adev->gfx.mec.num_queue = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * 8;
2637 if (adev->gfx.mec.hpd_eop_obj == NULL) {
2638 r = amdgpu_bo_create(adev,
2639 adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2,
2641 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
2642 &adev->gfx.mec.hpd_eop_obj);
2644 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
2649 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
2650 if (unlikely(r != 0)) {
2651 gfx_v7_0_mec_fini(adev);
2654 r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT,
2655 &adev->gfx.mec.hpd_eop_gpu_addr);
2657 dev_warn(adev->dev, "(%d) pin HDP EOP bo failed\n", r);
2658 gfx_v7_0_mec_fini(adev);
2661 r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd);
2663 dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r);
2664 gfx_v7_0_mec_fini(adev);
2668 /* clear memory. Not sure if this is required or not */
2669 memset(hpd, 0, adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2);
2671 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
2672 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
2677 struct hqd_registers
2679 u32 cp_mqd_base_addr;
2680 u32 cp_mqd_base_addr_hi;
2683 u32 cp_hqd_persistent_state;
2684 u32 cp_hqd_pipe_priority;
2685 u32 cp_hqd_queue_priority;
2688 u32 cp_hqd_pq_base_hi;
2690 u32 cp_hqd_pq_rptr_report_addr;
2691 u32 cp_hqd_pq_rptr_report_addr_hi;
2692 u32 cp_hqd_pq_wptr_poll_addr;
2693 u32 cp_hqd_pq_wptr_poll_addr_hi;
2694 u32 cp_hqd_pq_doorbell_control;
2696 u32 cp_hqd_pq_control;
2697 u32 cp_hqd_ib_base_addr;
2698 u32 cp_hqd_ib_base_addr_hi;
2700 u32 cp_hqd_ib_control;
2701 u32 cp_hqd_iq_timer;
2703 u32 cp_hqd_dequeue_request;
2704 u32 cp_hqd_dma_offload;
2705 u32 cp_hqd_sema_cmd;
2706 u32 cp_hqd_msg_type;
2707 u32 cp_hqd_atomic0_preop_lo;
2708 u32 cp_hqd_atomic0_preop_hi;
2709 u32 cp_hqd_atomic1_preop_lo;
2710 u32 cp_hqd_atomic1_preop_hi;
2711 u32 cp_hqd_hq_scheduler0;
2712 u32 cp_hqd_hq_scheduler1;
2719 u32 dispatch_initiator;
2723 u32 pipeline_stat_enable;
2724 u32 perf_counter_enable;
2730 u32 resource_limits;
2731 u32 static_thread_mgmt01[2];
2733 u32 static_thread_mgmt23[2];
2735 u32 thread_trace_enable;
2738 u32 vgtcs_invoke_count[2];
2739 struct hqd_registers queue_state;
2741 u32 interrupt_queue[64];
2745 * gfx_v7_0_cp_compute_resume - setup the compute queue registers
2747 * @adev: amdgpu_device pointer
2749 * Program the compute queues and test them to make sure they
2751 * Returns 0 for success, error for failure.
2753 static int gfx_v7_0_cp_compute_resume(struct amdgpu_device *adev)
2757 bool use_doorbell = true;
2763 struct bonaire_mqd *mqd;
2765 gfx_v7_0_cp_compute_enable(adev, true);
2767 /* fix up chicken bits */
2768 tmp = RREG32(mmCP_CPF_DEBUG);
2770 WREG32(mmCP_CPF_DEBUG, tmp);
2772 /* init the pipes */
2773 mutex_lock(&adev->srbm_mutex);
2774 for (i = 0; i < (adev->gfx.mec.num_pipe * adev->gfx.mec.num_mec); i++) {
2775 int me = (i < 4) ? 1 : 2;
2776 int pipe = (i < 4) ? i : (i - 4);
2778 eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE * 2);
2780 cik_srbm_select(adev, me, pipe, 0, 0);
2782 /* write the EOP addr */
2783 WREG32(mmCP_HPD_EOP_BASE_ADDR, eop_gpu_addr >> 8);
2784 WREG32(mmCP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr) >> 8);
2786 /* set the VMID assigned */
2787 WREG32(mmCP_HPD_EOP_VMID, 0);
2789 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
2790 tmp = RREG32(mmCP_HPD_EOP_CONTROL);
2791 tmp &= ~CP_HPD_EOP_CONTROL__EOP_SIZE_MASK;
2792 tmp |= order_base_2(MEC_HPD_SIZE / 8);
2793 WREG32(mmCP_HPD_EOP_CONTROL, tmp);
2795 cik_srbm_select(adev, 0, 0, 0, 0);
2796 mutex_unlock(&adev->srbm_mutex);
2798 /* init the queues. Just two for now. */
2799 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2800 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
2802 if (ring->mqd_obj == NULL) {
2803 r = amdgpu_bo_create(adev,
2804 sizeof(struct bonaire_mqd),
2806 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
2809 dev_warn(adev->dev, "(%d) create MQD bo failed\n", r);
2814 r = amdgpu_bo_reserve(ring->mqd_obj, false);
2815 if (unlikely(r != 0)) {
2816 gfx_v7_0_cp_compute_fini(adev);
2819 r = amdgpu_bo_pin(ring->mqd_obj, AMDGPU_GEM_DOMAIN_GTT,
2822 dev_warn(adev->dev, "(%d) pin MQD bo failed\n", r);
2823 gfx_v7_0_cp_compute_fini(adev);
2826 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&buf);
2828 dev_warn(adev->dev, "(%d) map MQD bo failed\n", r);
2829 gfx_v7_0_cp_compute_fini(adev);
2833 /* init the mqd struct */
2834 memset(buf, 0, sizeof(struct bonaire_mqd));
2836 mqd = (struct bonaire_mqd *)buf;
2837 mqd->header = 0xC0310800;
2838 mqd->static_thread_mgmt01[0] = 0xffffffff;
2839 mqd->static_thread_mgmt01[1] = 0xffffffff;
2840 mqd->static_thread_mgmt23[0] = 0xffffffff;
2841 mqd->static_thread_mgmt23[1] = 0xffffffff;
2843 mutex_lock(&adev->srbm_mutex);
2844 cik_srbm_select(adev, ring->me,
2848 /* disable wptr polling */
2849 tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL);
2850 tmp &= ~CP_PQ_WPTR_POLL_CNTL__EN_MASK;
2851 WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp);
2853 /* enable doorbell? */
2854 mqd->queue_state.cp_hqd_pq_doorbell_control =
2855 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
2857 mqd->queue_state.cp_hqd_pq_doorbell_control |= CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
2859 mqd->queue_state.cp_hqd_pq_doorbell_control &= ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
2860 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL,
2861 mqd->queue_state.cp_hqd_pq_doorbell_control);
2863 /* disable the queue if it's active */
2864 mqd->queue_state.cp_hqd_dequeue_request = 0;
2865 mqd->queue_state.cp_hqd_pq_rptr = 0;
2866 mqd->queue_state.cp_hqd_pq_wptr= 0;
2867 if (RREG32(mmCP_HQD_ACTIVE) & 1) {
2868 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1);
2869 for (j = 0; j < adev->usec_timeout; j++) {
2870 if (!(RREG32(mmCP_HQD_ACTIVE) & 1))
2874 WREG32(mmCP_HQD_DEQUEUE_REQUEST, mqd->queue_state.cp_hqd_dequeue_request);
2875 WREG32(mmCP_HQD_PQ_RPTR, mqd->queue_state.cp_hqd_pq_rptr);
2876 WREG32(mmCP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr);
2879 /* set the pointer to the MQD */
2880 mqd->queue_state.cp_mqd_base_addr = mqd_gpu_addr & 0xfffffffc;
2881 mqd->queue_state.cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);
2882 WREG32(mmCP_MQD_BASE_ADDR, mqd->queue_state.cp_mqd_base_addr);
2883 WREG32(mmCP_MQD_BASE_ADDR_HI, mqd->queue_state.cp_mqd_base_addr_hi);
2884 /* set MQD vmid to 0 */
2885 mqd->queue_state.cp_mqd_control = RREG32(mmCP_MQD_CONTROL);
2886 mqd->queue_state.cp_mqd_control &= ~CP_MQD_CONTROL__VMID_MASK;
2887 WREG32(mmCP_MQD_CONTROL, mqd->queue_state.cp_mqd_control);
2889 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
2890 hqd_gpu_addr = ring->gpu_addr >> 8;
2891 mqd->queue_state.cp_hqd_pq_base = hqd_gpu_addr;
2892 mqd->queue_state.cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
2893 WREG32(mmCP_HQD_PQ_BASE, mqd->queue_state.cp_hqd_pq_base);
2894 WREG32(mmCP_HQD_PQ_BASE_HI, mqd->queue_state.cp_hqd_pq_base_hi);
2896 /* set up the HQD, this is similar to CP_RB0_CNTL */
2897 mqd->queue_state.cp_hqd_pq_control = RREG32(mmCP_HQD_PQ_CONTROL);
2898 mqd->queue_state.cp_hqd_pq_control &=
2899 ~(CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK |
2900 CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK);
2902 mqd->queue_state.cp_hqd_pq_control |=
2903 order_base_2(ring->ring_size / 8);
2904 mqd->queue_state.cp_hqd_pq_control |=
2905 (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8);
2907 mqd->queue_state.cp_hqd_pq_control |=
2908 2 << CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT;
2910 mqd->queue_state.cp_hqd_pq_control &=
2911 ~(CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK |
2912 CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK |
2913 CP_HQD_PQ_CONTROL__PQ_VOLATILE_MASK);
2914 mqd->queue_state.cp_hqd_pq_control |=
2915 CP_HQD_PQ_CONTROL__PRIV_STATE_MASK |
2916 CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK; /* assuming kernel queue control */
2917 WREG32(mmCP_HQD_PQ_CONTROL, mqd->queue_state.cp_hqd_pq_control);
2919 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
2920 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2921 mqd->queue_state.cp_hqd_pq_wptr_poll_addr = wb_gpu_addr & 0xfffffffc;
2922 mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
2923 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, mqd->queue_state.cp_hqd_pq_wptr_poll_addr);
2924 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
2925 mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi);
2927 /* set the wb address wether it's enabled or not */
2928 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2929 mqd->queue_state.cp_hqd_pq_rptr_report_addr = wb_gpu_addr & 0xfffffffc;
2930 mqd->queue_state.cp_hqd_pq_rptr_report_addr_hi =
2931 upper_32_bits(wb_gpu_addr) & 0xffff;
2932 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR,
2933 mqd->queue_state.cp_hqd_pq_rptr_report_addr);
2934 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
2935 mqd->queue_state.cp_hqd_pq_rptr_report_addr_hi);
2937 /* enable the doorbell if requested */
2939 mqd->queue_state.cp_hqd_pq_doorbell_control =
2940 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
2941 mqd->queue_state.cp_hqd_pq_doorbell_control &=
2942 ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK;
2943 mqd->queue_state.cp_hqd_pq_doorbell_control |=
2944 (ring->doorbell_index <<
2945 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT);
2946 mqd->queue_state.cp_hqd_pq_doorbell_control |=
2947 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
2948 mqd->queue_state.cp_hqd_pq_doorbell_control &=
2949 ~(CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK |
2950 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK);
2953 mqd->queue_state.cp_hqd_pq_doorbell_control = 0;
2955 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL,
2956 mqd->queue_state.cp_hqd_pq_doorbell_control);
2958 /* read and write pointers, similar to CP_RB0_WPTR/_RPTR */
2960 mqd->queue_state.cp_hqd_pq_wptr = ring->wptr;
2961 WREG32(mmCP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr);
2962 mqd->queue_state.cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
2964 /* set the vmid for the queue */
2965 mqd->queue_state.cp_hqd_vmid = 0;
2966 WREG32(mmCP_HQD_VMID, mqd->queue_state.cp_hqd_vmid);
2968 /* activate the queue */
2969 mqd->queue_state.cp_hqd_active = 1;
2970 WREG32(mmCP_HQD_ACTIVE, mqd->queue_state.cp_hqd_active);
2972 cik_srbm_select(adev, 0, 0, 0, 0);
2973 mutex_unlock(&adev->srbm_mutex);
2975 amdgpu_bo_kunmap(ring->mqd_obj);
2976 amdgpu_bo_unreserve(ring->mqd_obj);
2979 r = amdgpu_ring_test_ring(ring);
2981 ring->ready = false;
2987 static void gfx_v7_0_cp_enable(struct amdgpu_device *adev, bool enable)
2989 gfx_v7_0_cp_gfx_enable(adev, enable);
2990 gfx_v7_0_cp_compute_enable(adev, enable);
2993 static int gfx_v7_0_cp_load_microcode(struct amdgpu_device *adev)
2997 r = gfx_v7_0_cp_gfx_load_microcode(adev);
3000 r = gfx_v7_0_cp_compute_load_microcode(adev);
3007 static void gfx_v7_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
3010 u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
3013 tmp |= (CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK |
3014 CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK);
3016 tmp &= ~(CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK |
3017 CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK);
3018 WREG32(mmCP_INT_CNTL_RING0, tmp);
3021 static int gfx_v7_0_cp_resume(struct amdgpu_device *adev)
3025 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3027 r = gfx_v7_0_cp_load_microcode(adev);
3031 r = gfx_v7_0_cp_gfx_resume(adev);
3034 r = gfx_v7_0_cp_compute_resume(adev);
3038 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3044 * gfx_v7_0_ring_emit_vm_flush - cik vm flush using the CP
3046 * @ring: the ring to emmit the commands to
3048 * Sync the command pipeline with the PFP. E.g. wait for everything
3051 static void gfx_v7_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
3053 int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
3054 uint32_t seq = ring->fence_drv.sync_seq;
3055 uint64_t addr = ring->fence_drv.gpu_addr;
3057 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3058 amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
3059 WAIT_REG_MEM_FUNCTION(3) | /* equal */
3060 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */
3061 amdgpu_ring_write(ring, addr & 0xfffffffc);
3062 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
3063 amdgpu_ring_write(ring, seq);
3064 amdgpu_ring_write(ring, 0xffffffff);
3065 amdgpu_ring_write(ring, 4); /* poll interval */
3068 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
3069 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3070 amdgpu_ring_write(ring, 0);
3071 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3072 amdgpu_ring_write(ring, 0);
3078 * VMID 0 is the physical GPU addresses as used by the kernel.
3079 * VMIDs 1-15 are used for userspace clients and are handled
3080 * by the amdgpu vm/hsa code.
3083 * gfx_v7_0_ring_emit_vm_flush - cik vm flush using the CP
3085 * @adev: amdgpu_device pointer
3087 * Update the page table base and flush the VM TLB
3088 * using the CP (CIK).
3090 static void gfx_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
3091 unsigned vm_id, uint64_t pd_addr)
3093 int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
3095 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3096 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
3097 WRITE_DATA_DST_SEL(0)));
3099 amdgpu_ring_write(ring,
3100 (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
3102 amdgpu_ring_write(ring,
3103 (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
3105 amdgpu_ring_write(ring, 0);
3106 amdgpu_ring_write(ring, pd_addr >> 12);
3108 /* bits 0-15 are the VM contexts0-15 */
3109 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3110 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3111 WRITE_DATA_DST_SEL(0)));
3112 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
3113 amdgpu_ring_write(ring, 0);
3114 amdgpu_ring_write(ring, 1 << vm_id);
3116 /* wait for the invalidate to complete */
3117 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3118 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */
3119 WAIT_REG_MEM_FUNCTION(0) | /* always */
3120 WAIT_REG_MEM_ENGINE(0))); /* me */
3121 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
3122 amdgpu_ring_write(ring, 0);
3123 amdgpu_ring_write(ring, 0); /* ref */
3124 amdgpu_ring_write(ring, 0); /* mask */
3125 amdgpu_ring_write(ring, 0x20); /* poll interval */
3127 /* compute doesn't have PFP */
3129 /* sync PFP to ME, otherwise we might get invalid PFP reads */
3130 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
3131 amdgpu_ring_write(ring, 0x0);
3133 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
3134 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3135 amdgpu_ring_write(ring, 0);
3136 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3137 amdgpu_ring_write(ring, 0);
3143 * The RLC is a multi-purpose microengine that handles a
3144 * variety of functions.
3146 static void gfx_v7_0_rlc_fini(struct amdgpu_device *adev)
3150 /* save restore block */
3151 if (adev->gfx.rlc.save_restore_obj) {
3152 r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false);
3153 if (unlikely(r != 0))
3154 dev_warn(adev->dev, "(%d) reserve RLC sr bo failed\n", r);
3155 amdgpu_bo_unpin(adev->gfx.rlc.save_restore_obj);
3156 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
3158 amdgpu_bo_unref(&adev->gfx.rlc.save_restore_obj);
3159 adev->gfx.rlc.save_restore_obj = NULL;
3162 /* clear state block */
3163 if (adev->gfx.rlc.clear_state_obj) {
3164 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
3165 if (unlikely(r != 0))
3166 dev_warn(adev->dev, "(%d) reserve RLC c bo failed\n", r);
3167 amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
3168 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
3170 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj);
3171 adev->gfx.rlc.clear_state_obj = NULL;
3174 /* clear state block */
3175 if (adev->gfx.rlc.cp_table_obj) {
3176 r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false);
3177 if (unlikely(r != 0))
3178 dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r);
3179 amdgpu_bo_unpin(adev->gfx.rlc.cp_table_obj);
3180 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
3182 amdgpu_bo_unref(&adev->gfx.rlc.cp_table_obj);
3183 adev->gfx.rlc.cp_table_obj = NULL;
3187 static int gfx_v7_0_rlc_init(struct amdgpu_device *adev)
3190 volatile u32 *dst_ptr;
3192 const struct cs_section_def *cs_data;
3195 /* allocate rlc buffers */
3196 if (adev->flags & AMD_IS_APU) {
3197 if (adev->asic_type == CHIP_KAVERI) {
3198 adev->gfx.rlc.reg_list = spectre_rlc_save_restore_register_list;
3199 adev->gfx.rlc.reg_list_size =
3200 (u32)ARRAY_SIZE(spectre_rlc_save_restore_register_list);
3202 adev->gfx.rlc.reg_list = kalindi_rlc_save_restore_register_list;
3203 adev->gfx.rlc.reg_list_size =
3204 (u32)ARRAY_SIZE(kalindi_rlc_save_restore_register_list);
3207 adev->gfx.rlc.cs_data = ci_cs_data;
3208 adev->gfx.rlc.cp_table_size = CP_ME_TABLE_SIZE * 5 * 4;
3210 src_ptr = adev->gfx.rlc.reg_list;
3211 dws = adev->gfx.rlc.reg_list_size;
3212 dws += (5 * 16) + 48 + 48 + 64;
3214 cs_data = adev->gfx.rlc.cs_data;
3217 /* save restore block */
3218 if (adev->gfx.rlc.save_restore_obj == NULL) {
3219 r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true,
3220 AMDGPU_GEM_DOMAIN_VRAM,
3221 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
3223 &adev->gfx.rlc.save_restore_obj);
3225 dev_warn(adev->dev, "(%d) create RLC sr bo failed\n", r);
3230 r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false);
3231 if (unlikely(r != 0)) {
3232 gfx_v7_0_rlc_fini(adev);
3235 r = amdgpu_bo_pin(adev->gfx.rlc.save_restore_obj, AMDGPU_GEM_DOMAIN_VRAM,
3236 &adev->gfx.rlc.save_restore_gpu_addr);
3238 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
3239 dev_warn(adev->dev, "(%d) pin RLC sr bo failed\n", r);
3240 gfx_v7_0_rlc_fini(adev);
3244 r = amdgpu_bo_kmap(adev->gfx.rlc.save_restore_obj, (void **)&adev->gfx.rlc.sr_ptr);
3246 dev_warn(adev->dev, "(%d) map RLC sr bo failed\n", r);
3247 gfx_v7_0_rlc_fini(adev);
3250 /* write the sr buffer */
3251 dst_ptr = adev->gfx.rlc.sr_ptr;
3252 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)
3253 dst_ptr[i] = cpu_to_le32(src_ptr[i]);
3254 amdgpu_bo_kunmap(adev->gfx.rlc.save_restore_obj);
3255 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
3259 /* clear state block */
3260 adev->gfx.rlc.clear_state_size = dws = gfx_v7_0_get_csb_size(adev);
3262 if (adev->gfx.rlc.clear_state_obj == NULL) {
3263 r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true,
3264 AMDGPU_GEM_DOMAIN_VRAM,
3265 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
3267 &adev->gfx.rlc.clear_state_obj);
3269 dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r);
3270 gfx_v7_0_rlc_fini(adev);
3274 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
3275 if (unlikely(r != 0)) {
3276 gfx_v7_0_rlc_fini(adev);
3279 r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj, AMDGPU_GEM_DOMAIN_VRAM,
3280 &adev->gfx.rlc.clear_state_gpu_addr);
3282 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
3283 dev_warn(adev->dev, "(%d) pin RLC c bo failed\n", r);
3284 gfx_v7_0_rlc_fini(adev);
3288 r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, (void **)&adev->gfx.rlc.cs_ptr);
3290 dev_warn(adev->dev, "(%d) map RLC c bo failed\n", r);
3291 gfx_v7_0_rlc_fini(adev);
3294 /* set up the cs buffer */
3295 dst_ptr = adev->gfx.rlc.cs_ptr;
3296 gfx_v7_0_get_csb_buffer(adev, dst_ptr);
3297 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
3298 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
3301 if (adev->gfx.rlc.cp_table_size) {
3302 if (adev->gfx.rlc.cp_table_obj == NULL) {
3303 r = amdgpu_bo_create(adev, adev->gfx.rlc.cp_table_size, PAGE_SIZE, true,
3304 AMDGPU_GEM_DOMAIN_VRAM,
3305 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
3307 &adev->gfx.rlc.cp_table_obj);
3309 dev_warn(adev->dev, "(%d) create RLC cp table bo failed\n", r);
3310 gfx_v7_0_rlc_fini(adev);
3315 r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false);
3316 if (unlikely(r != 0)) {
3317 dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r);
3318 gfx_v7_0_rlc_fini(adev);
3321 r = amdgpu_bo_pin(adev->gfx.rlc.cp_table_obj, AMDGPU_GEM_DOMAIN_VRAM,
3322 &adev->gfx.rlc.cp_table_gpu_addr);
3324 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
3325 dev_warn(adev->dev, "(%d) pin RLC cp_table bo failed\n", r);
3326 gfx_v7_0_rlc_fini(adev);
3329 r = amdgpu_bo_kmap(adev->gfx.rlc.cp_table_obj, (void **)&adev->gfx.rlc.cp_table_ptr);
3331 dev_warn(adev->dev, "(%d) map RLC cp table bo failed\n", r);
3332 gfx_v7_0_rlc_fini(adev);
3336 gfx_v7_0_init_cp_pg_table(adev);
3338 amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj);
3339 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
3346 static void gfx_v7_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
3350 tmp = RREG32(mmRLC_LB_CNTL);
3352 tmp |= RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK;
3354 tmp &= ~RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK;
3355 WREG32(mmRLC_LB_CNTL, tmp);
3358 static void gfx_v7_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
3363 mutex_lock(&adev->grbm_idx_mutex);
3364 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3365 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3366 gfx_v7_0_select_se_sh(adev, i, j);
3367 for (k = 0; k < adev->usec_timeout; k++) {
3368 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0)
3374 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
3375 mutex_unlock(&adev->grbm_idx_mutex);
3377 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
3378 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
3379 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
3380 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
3381 for (k = 0; k < adev->usec_timeout; k++) {
3382 if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
3388 static void gfx_v7_0_update_rlc(struct amdgpu_device *adev, u32 rlc)
3392 tmp = RREG32(mmRLC_CNTL);
3394 WREG32(mmRLC_CNTL, rlc);
3397 static u32 gfx_v7_0_halt_rlc(struct amdgpu_device *adev)
3401 orig = data = RREG32(mmRLC_CNTL);
3403 if (data & RLC_CNTL__RLC_ENABLE_F32_MASK) {
3406 data &= ~RLC_CNTL__RLC_ENABLE_F32_MASK;
3407 WREG32(mmRLC_CNTL, data);
3409 for (i = 0; i < adev->usec_timeout; i++) {
3410 if ((RREG32(mmRLC_GPM_STAT) & RLC_GPM_STAT__RLC_BUSY_MASK) == 0)
3415 gfx_v7_0_wait_for_rlc_serdes(adev);
3421 void gfx_v7_0_enter_rlc_safe_mode(struct amdgpu_device *adev)
3425 tmp = 0x1 | (1 << 1);
3426 WREG32(mmRLC_GPR_REG2, tmp);
3428 mask = RLC_GPM_STAT__GFX_POWER_STATUS_MASK |
3429 RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK;
3430 for (i = 0; i < adev->usec_timeout; i++) {
3431 if ((RREG32(mmRLC_GPM_STAT) & mask) == mask)
3436 for (i = 0; i < adev->usec_timeout; i++) {
3437 if ((RREG32(mmRLC_GPR_REG2) & 0x1) == 0)
3443 void gfx_v7_0_exit_rlc_safe_mode(struct amdgpu_device *adev)
3447 tmp = 0x1 | (0 << 1);
3448 WREG32(mmRLC_GPR_REG2, tmp);
3452 * gfx_v7_0_rlc_stop - stop the RLC ME
3454 * @adev: amdgpu_device pointer
3456 * Halt the RLC ME (MicroEngine) (CIK).
3458 void gfx_v7_0_rlc_stop(struct amdgpu_device *adev)
3460 WREG32(mmRLC_CNTL, 0);
3462 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3464 gfx_v7_0_wait_for_rlc_serdes(adev);
3468 * gfx_v7_0_rlc_start - start the RLC ME
3470 * @adev: amdgpu_device pointer
3472 * Unhalt the RLC ME (MicroEngine) (CIK).
3474 static void gfx_v7_0_rlc_start(struct amdgpu_device *adev)
3476 WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK);
3478 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3483 static void gfx_v7_0_rlc_reset(struct amdgpu_device *adev)
3485 u32 tmp = RREG32(mmGRBM_SOFT_RESET);
3487 tmp |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
3488 WREG32(mmGRBM_SOFT_RESET, tmp);
3490 tmp &= ~GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
3491 WREG32(mmGRBM_SOFT_RESET, tmp);
3496 * gfx_v7_0_rlc_resume - setup the RLC hw
3498 * @adev: amdgpu_device pointer
3500 * Initialize the RLC registers, load the ucode,
3501 * and start the RLC (CIK).
3502 * Returns 0 for success, -EINVAL if the ucode is not available.
3504 static int gfx_v7_0_rlc_resume(struct amdgpu_device *adev)
3506 const struct rlc_firmware_header_v1_0 *hdr;
3507 const __le32 *fw_data;
3508 unsigned i, fw_size;
3511 if (!adev->gfx.rlc_fw)
3514 hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
3515 amdgpu_ucode_print_rlc_hdr(&hdr->header);
3516 adev->gfx.rlc_fw_version = le32_to_cpu(hdr->header.ucode_version);
3517 adev->gfx.rlc_feature_version = le32_to_cpu(
3518 hdr->ucode_feature_version);
3520 gfx_v7_0_rlc_stop(adev);
3523 tmp = RREG32(mmRLC_CGCG_CGLS_CTRL) & 0xfffffffc;
3524 WREG32(mmRLC_CGCG_CGLS_CTRL, tmp);
3526 gfx_v7_0_rlc_reset(adev);
3528 gfx_v7_0_init_pg(adev);
3530 WREG32(mmRLC_LB_CNTR_INIT, 0);
3531 WREG32(mmRLC_LB_CNTR_MAX, 0x00008000);
3533 mutex_lock(&adev->grbm_idx_mutex);
3534 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
3535 WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff);
3536 WREG32(mmRLC_LB_PARAMS, 0x00600408);
3537 WREG32(mmRLC_LB_CNTL, 0x80000004);
3538 mutex_unlock(&adev->grbm_idx_mutex);
3540 WREG32(mmRLC_MC_CNTL, 0);
3541 WREG32(mmRLC_UCODE_CNTL, 0);
3543 fw_data = (const __le32 *)
3544 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3545 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
3546 WREG32(mmRLC_GPM_UCODE_ADDR, 0);
3547 for (i = 0; i < fw_size; i++)
3548 WREG32(mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
3549 WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
3551 /* XXX - find out what chips support lbpw */
3552 gfx_v7_0_enable_lbpw(adev, false);
3554 if (adev->asic_type == CHIP_BONAIRE)
3555 WREG32(mmRLC_DRIVER_CPDMA_STATUS, 0);
3557 gfx_v7_0_rlc_start(adev);
3562 static void gfx_v7_0_enable_cgcg(struct amdgpu_device *adev, bool enable)
3564 u32 data, orig, tmp, tmp2;
3566 orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
3568 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
3569 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3571 tmp = gfx_v7_0_halt_rlc(adev);
3573 mutex_lock(&adev->grbm_idx_mutex);
3574 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
3575 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
3576 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
3577 tmp2 = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK |
3578 RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_0_MASK |
3579 RLC_SERDES_WR_CTRL__CGLS_ENABLE_MASK;
3580 WREG32(mmRLC_SERDES_WR_CTRL, tmp2);
3581 mutex_unlock(&adev->grbm_idx_mutex);
3583 gfx_v7_0_update_rlc(adev, tmp);
3585 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
3587 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3589 RREG32(mmCB_CGTT_SCLK_CTRL);
3590 RREG32(mmCB_CGTT_SCLK_CTRL);
3591 RREG32(mmCB_CGTT_SCLK_CTRL);
3592 RREG32(mmCB_CGTT_SCLK_CTRL);
3594 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
3598 WREG32(mmRLC_CGCG_CGLS_CTRL, data);
3602 static void gfx_v7_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
3604 u32 data, orig, tmp = 0;
3606 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
3607 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
3608 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
3609 orig = data = RREG32(mmCP_MEM_SLP_CNTL);
3610 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3612 WREG32(mmCP_MEM_SLP_CNTL, data);
3616 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
3620 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
3622 tmp = gfx_v7_0_halt_rlc(adev);
3624 mutex_lock(&adev->grbm_idx_mutex);
3625 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
3626 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
3627 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
3628 data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK |
3629 RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_0_MASK;
3630 WREG32(mmRLC_SERDES_WR_CTRL, data);
3631 mutex_unlock(&adev->grbm_idx_mutex);
3633 gfx_v7_0_update_rlc(adev, tmp);
3635 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS) {
3636 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
3637 data &= ~CGTS_SM_CTRL_REG__SM_MODE_MASK;
3638 data |= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT);
3639 data |= CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK;
3640 data &= ~CGTS_SM_CTRL_REG__OVERRIDE_MASK;
3641 if ((adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) &&
3642 (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGTS_LS))
3643 data &= ~CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
3644 data &= ~CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK;
3645 data |= CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK;
3646 data |= (0x96 << CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT);
3648 WREG32(mmCGTS_SM_CTRL_REG, data);
3651 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
3654 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
3656 data = RREG32(mmRLC_MEM_SLP_CNTL);
3657 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
3658 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
3659 WREG32(mmRLC_MEM_SLP_CNTL, data);
3662 data = RREG32(mmCP_MEM_SLP_CNTL);
3663 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
3664 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3665 WREG32(mmCP_MEM_SLP_CNTL, data);
3668 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
3669 data |= CGTS_SM_CTRL_REG__OVERRIDE_MASK | CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
3671 WREG32(mmCGTS_SM_CTRL_REG, data);
3673 tmp = gfx_v7_0_halt_rlc(adev);
3675 mutex_lock(&adev->grbm_idx_mutex);
3676 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
3677 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
3678 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
3679 data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK | RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_1_MASK;
3680 WREG32(mmRLC_SERDES_WR_CTRL, data);
3681 mutex_unlock(&adev->grbm_idx_mutex);
3683 gfx_v7_0_update_rlc(adev, tmp);
3687 static void gfx_v7_0_update_cg(struct amdgpu_device *adev,
3690 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3691 /* order matters! */
3693 gfx_v7_0_enable_mgcg(adev, true);
3694 gfx_v7_0_enable_cgcg(adev, true);
3696 gfx_v7_0_enable_cgcg(adev, false);
3697 gfx_v7_0_enable_mgcg(adev, false);
3699 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3702 static void gfx_v7_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev,
3707 orig = data = RREG32(mmRLC_PG_CNTL);
3708 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS))
3709 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
3711 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
3713 WREG32(mmRLC_PG_CNTL, data);
3716 static void gfx_v7_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev,
3721 orig = data = RREG32(mmRLC_PG_CNTL);
3722 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS))
3723 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
3725 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
3727 WREG32(mmRLC_PG_CNTL, data);
3730 static void gfx_v7_0_enable_cp_pg(struct amdgpu_device *adev, bool enable)
3734 orig = data = RREG32(mmRLC_PG_CNTL);
3735 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP))
3740 WREG32(mmRLC_PG_CNTL, data);
3743 static void gfx_v7_0_enable_gds_pg(struct amdgpu_device *adev, bool enable)
3747 orig = data = RREG32(mmRLC_PG_CNTL);
3748 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GDS))
3753 WREG32(mmRLC_PG_CNTL, data);
3756 static void gfx_v7_0_init_cp_pg_table(struct amdgpu_device *adev)
3758 const __le32 *fw_data;
3759 volatile u32 *dst_ptr;
3760 int me, i, max_me = 4;
3762 u32 table_offset, table_size;
3764 if (adev->asic_type == CHIP_KAVERI)
3767 if (adev->gfx.rlc.cp_table_ptr == NULL)
3770 /* write the cp table buffer */
3771 dst_ptr = adev->gfx.rlc.cp_table_ptr;
3772 for (me = 0; me < max_me; me++) {
3774 const struct gfx_firmware_header_v1_0 *hdr =
3775 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
3776 fw_data = (const __le32 *)
3777 (adev->gfx.ce_fw->data +
3778 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3779 table_offset = le32_to_cpu(hdr->jt_offset);
3780 table_size = le32_to_cpu(hdr->jt_size);
3781 } else if (me == 1) {
3782 const struct gfx_firmware_header_v1_0 *hdr =
3783 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
3784 fw_data = (const __le32 *)
3785 (adev->gfx.pfp_fw->data +
3786 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3787 table_offset = le32_to_cpu(hdr->jt_offset);
3788 table_size = le32_to_cpu(hdr->jt_size);
3789 } else if (me == 2) {
3790 const struct gfx_firmware_header_v1_0 *hdr =
3791 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
3792 fw_data = (const __le32 *)
3793 (adev->gfx.me_fw->data +
3794 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3795 table_offset = le32_to_cpu(hdr->jt_offset);
3796 table_size = le32_to_cpu(hdr->jt_size);
3797 } else if (me == 3) {
3798 const struct gfx_firmware_header_v1_0 *hdr =
3799 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
3800 fw_data = (const __le32 *)
3801 (adev->gfx.mec_fw->data +
3802 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3803 table_offset = le32_to_cpu(hdr->jt_offset);
3804 table_size = le32_to_cpu(hdr->jt_size);
3806 const struct gfx_firmware_header_v1_0 *hdr =
3807 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
3808 fw_data = (const __le32 *)
3809 (adev->gfx.mec2_fw->data +
3810 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3811 table_offset = le32_to_cpu(hdr->jt_offset);
3812 table_size = le32_to_cpu(hdr->jt_size);
3815 for (i = 0; i < table_size; i ++) {
3816 dst_ptr[bo_offset + i] =
3817 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
3820 bo_offset += table_size;
3824 static void gfx_v7_0_enable_gfx_cgpg(struct amdgpu_device *adev,
3829 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
3830 orig = data = RREG32(mmRLC_PG_CNTL);
3831 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
3833 WREG32(mmRLC_PG_CNTL, data);
3835 orig = data = RREG32(mmRLC_AUTO_PG_CTRL);
3836 data |= RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK;
3838 WREG32(mmRLC_AUTO_PG_CTRL, data);
3840 orig = data = RREG32(mmRLC_PG_CNTL);
3841 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
3843 WREG32(mmRLC_PG_CNTL, data);
3845 orig = data = RREG32(mmRLC_AUTO_PG_CTRL);
3846 data &= ~RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK;
3848 WREG32(mmRLC_AUTO_PG_CTRL, data);
3850 data = RREG32(mmDB_RENDER_CONTROL);
3854 static u32 gfx_v7_0_get_cu_active_bitmap(struct amdgpu_device *adev)
3858 data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG);
3859 data |= RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
3861 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
3862 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
3864 mask = gfx_v7_0_create_bitmask(adev->gfx.config.max_cu_per_sh);
3866 return (~data) & mask;
3869 static void gfx_v7_0_init_ao_cu_mask(struct amdgpu_device *adev)
3873 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask);
3875 tmp = RREG32(mmRLC_MAX_PG_CU);
3876 tmp &= ~RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK;
3877 tmp |= (adev->gfx.cu_info.number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT);
3878 WREG32(mmRLC_MAX_PG_CU, tmp);
3881 static void gfx_v7_0_enable_gfx_static_mgpg(struct amdgpu_device *adev,
3886 orig = data = RREG32(mmRLC_PG_CNTL);
3887 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG))
3888 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
3890 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
3892 WREG32(mmRLC_PG_CNTL, data);
3895 static void gfx_v7_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev,
3900 orig = data = RREG32(mmRLC_PG_CNTL);
3901 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG))
3902 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
3904 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
3906 WREG32(mmRLC_PG_CNTL, data);
3909 #define RLC_SAVE_AND_RESTORE_STARTING_OFFSET 0x90
3910 #define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET 0x3D
3912 static void gfx_v7_0_init_gfx_cgpg(struct amdgpu_device *adev)
3917 if (adev->gfx.rlc.cs_data) {
3918 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET);
3919 WREG32(mmRLC_GPM_SCRATCH_DATA, upper_32_bits(adev->gfx.rlc.clear_state_gpu_addr));
3920 WREG32(mmRLC_GPM_SCRATCH_DATA, lower_32_bits(adev->gfx.rlc.clear_state_gpu_addr));
3921 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.clear_state_size);
3923 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET);
3924 for (i = 0; i < 3; i++)
3925 WREG32(mmRLC_GPM_SCRATCH_DATA, 0);
3927 if (adev->gfx.rlc.reg_list) {
3928 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_SAVE_AND_RESTORE_STARTING_OFFSET);
3929 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)
3930 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.reg_list[i]);
3933 orig = data = RREG32(mmRLC_PG_CNTL);
3934 data |= RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK;
3936 WREG32(mmRLC_PG_CNTL, data);
3938 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
3939 WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8);
3941 data = RREG32(mmCP_RB_WPTR_POLL_CNTL);
3942 data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK;
3943 data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
3944 WREG32(mmCP_RB_WPTR_POLL_CNTL, data);
3947 WREG32(mmRLC_PG_DELAY, data);
3949 data = RREG32(mmRLC_PG_DELAY_2);
3952 WREG32(mmRLC_PG_DELAY_2, data);
3954 data = RREG32(mmRLC_AUTO_PG_CTRL);
3955 data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
3956 data |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
3957 WREG32(mmRLC_AUTO_PG_CTRL, data);
3961 static void gfx_v7_0_update_gfx_pg(struct amdgpu_device *adev, bool enable)
3963 gfx_v7_0_enable_gfx_cgpg(adev, enable);
3964 gfx_v7_0_enable_gfx_static_mgpg(adev, enable);
3965 gfx_v7_0_enable_gfx_dynamic_mgpg(adev, enable);
3968 static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev)
3971 const struct cs_section_def *sect = NULL;
3972 const struct cs_extent_def *ext = NULL;
3974 if (adev->gfx.rlc.cs_data == NULL)
3977 /* begin clear state */
3979 /* context control state */
3982 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
3983 for (ext = sect->section; ext->extent != NULL; ++ext) {
3984 if (sect->id == SECT_CONTEXT)
3985 count += 2 + ext->reg_count;
3990 /* pa_sc_raster_config/pa_sc_raster_config1 */
3992 /* end clear state */
4000 static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev,
4001 volatile u32 *buffer)
4004 const struct cs_section_def *sect = NULL;
4005 const struct cs_extent_def *ext = NULL;
4007 if (adev->gfx.rlc.cs_data == NULL)
4012 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4013 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
4015 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4016 buffer[count++] = cpu_to_le32(0x80000000);
4017 buffer[count++] = cpu_to_le32(0x80000000);
4019 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
4020 for (ext = sect->section; ext->extent != NULL; ++ext) {
4021 if (sect->id == SECT_CONTEXT) {
4023 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
4024 buffer[count++] = cpu_to_le32(ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
4025 for (i = 0; i < ext->reg_count; i++)
4026 buffer[count++] = cpu_to_le32(ext->extent[i]);
4033 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2));
4034 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
4035 switch (adev->asic_type) {
4037 buffer[count++] = cpu_to_le32(0x16000012);
4038 buffer[count++] = cpu_to_le32(0x00000000);
4041 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */
4042 buffer[count++] = cpu_to_le32(0x00000000);
4046 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */
4047 buffer[count++] = cpu_to_le32(0x00000000);
4050 buffer[count++] = cpu_to_le32(0x3a00161a);
4051 buffer[count++] = cpu_to_le32(0x0000002e);
4054 buffer[count++] = cpu_to_le32(0x00000000);
4055 buffer[count++] = cpu_to_le32(0x00000000);
4059 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4060 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
4062 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
4063 buffer[count++] = cpu_to_le32(0);
4066 static void gfx_v7_0_init_pg(struct amdgpu_device *adev)
4068 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
4069 AMD_PG_SUPPORT_GFX_SMG |
4070 AMD_PG_SUPPORT_GFX_DMG |
4072 AMD_PG_SUPPORT_GDS |
4073 AMD_PG_SUPPORT_RLC_SMU_HS)) {
4074 gfx_v7_0_enable_sclk_slowdown_on_pu(adev, true);
4075 gfx_v7_0_enable_sclk_slowdown_on_pd(adev, true);
4076 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
4077 gfx_v7_0_init_gfx_cgpg(adev);
4078 gfx_v7_0_enable_cp_pg(adev, true);
4079 gfx_v7_0_enable_gds_pg(adev, true);
4081 gfx_v7_0_init_ao_cu_mask(adev);
4082 gfx_v7_0_update_gfx_pg(adev, true);
4086 static void gfx_v7_0_fini_pg(struct amdgpu_device *adev)
4088 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
4089 AMD_PG_SUPPORT_GFX_SMG |
4090 AMD_PG_SUPPORT_GFX_DMG |
4092 AMD_PG_SUPPORT_GDS |
4093 AMD_PG_SUPPORT_RLC_SMU_HS)) {
4094 gfx_v7_0_update_gfx_pg(adev, false);
4095 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
4096 gfx_v7_0_enable_cp_pg(adev, false);
4097 gfx_v7_0_enable_gds_pg(adev, false);
4103 * gfx_v7_0_get_gpu_clock_counter - return GPU clock counter snapshot
4105 * @adev: amdgpu_device pointer
4107 * Fetches a GPU clock counter snapshot (SI).
4108 * Returns the 64 bit clock counter snapshot.
4110 uint64_t gfx_v7_0_get_gpu_clock_counter(struct amdgpu_device *adev)
4114 mutex_lock(&adev->gfx.gpu_clock_mutex);
4115 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
4116 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
4117 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
4118 mutex_unlock(&adev->gfx.gpu_clock_mutex);
4122 static void gfx_v7_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
4124 uint32_t gds_base, uint32_t gds_size,
4125 uint32_t gws_base, uint32_t gws_size,
4126 uint32_t oa_base, uint32_t oa_size)
4128 gds_base = gds_base >> AMDGPU_GDS_SHIFT;
4129 gds_size = gds_size >> AMDGPU_GDS_SHIFT;
4131 gws_base = gws_base >> AMDGPU_GWS_SHIFT;
4132 gws_size = gws_size >> AMDGPU_GWS_SHIFT;
4134 oa_base = oa_base >> AMDGPU_OA_SHIFT;
4135 oa_size = oa_size >> AMDGPU_OA_SHIFT;
4138 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4139 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4140 WRITE_DATA_DST_SEL(0)));
4141 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_base);
4142 amdgpu_ring_write(ring, 0);
4143 amdgpu_ring_write(ring, gds_base);
4146 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4147 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4148 WRITE_DATA_DST_SEL(0)));
4149 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_size);
4150 amdgpu_ring_write(ring, 0);
4151 amdgpu_ring_write(ring, gds_size);
4154 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4155 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4156 WRITE_DATA_DST_SEL(0)));
4157 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].gws);
4158 amdgpu_ring_write(ring, 0);
4159 amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
4162 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4163 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4164 WRITE_DATA_DST_SEL(0)));
4165 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].oa);
4166 amdgpu_ring_write(ring, 0);
4167 amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base));
4170 static int gfx_v7_0_early_init(void *handle)
4172 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4174 adev->gfx.num_gfx_rings = GFX7_NUM_GFX_RINGS;
4175 adev->gfx.num_compute_rings = GFX7_NUM_COMPUTE_RINGS;
4176 gfx_v7_0_set_ring_funcs(adev);
4177 gfx_v7_0_set_irq_funcs(adev);
4178 gfx_v7_0_set_gds_init(adev);
4183 static int gfx_v7_0_late_init(void *handle)
4185 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4188 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
4192 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
4199 static void gfx_v7_0_gpu_early_init(struct amdgpu_device *adev)
4202 u32 mc_shared_chmap, mc_arb_ramcfg;
4203 u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
4206 switch (adev->asic_type) {
4208 adev->gfx.config.max_shader_engines = 2;
4209 adev->gfx.config.max_tile_pipes = 4;
4210 adev->gfx.config.max_cu_per_sh = 7;
4211 adev->gfx.config.max_sh_per_se = 1;
4212 adev->gfx.config.max_backends_per_se = 2;
4213 adev->gfx.config.max_texture_channel_caches = 4;
4214 adev->gfx.config.max_gprs = 256;
4215 adev->gfx.config.max_gs_threads = 32;
4216 adev->gfx.config.max_hw_contexts = 8;
4218 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4219 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4220 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4221 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4222 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
4225 adev->gfx.config.max_shader_engines = 4;
4226 adev->gfx.config.max_tile_pipes = 16;
4227 adev->gfx.config.max_cu_per_sh = 11;
4228 adev->gfx.config.max_sh_per_se = 1;
4229 adev->gfx.config.max_backends_per_se = 4;
4230 adev->gfx.config.max_texture_channel_caches = 16;
4231 adev->gfx.config.max_gprs = 256;
4232 adev->gfx.config.max_gs_threads = 32;
4233 adev->gfx.config.max_hw_contexts = 8;
4235 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4236 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4237 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4238 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4239 gb_addr_config = HAWAII_GB_ADDR_CONFIG_GOLDEN;
4242 adev->gfx.config.max_shader_engines = 1;
4243 adev->gfx.config.max_tile_pipes = 4;
4244 if ((adev->pdev->device == 0x1304) ||
4245 (adev->pdev->device == 0x1305) ||
4246 (adev->pdev->device == 0x130C) ||
4247 (adev->pdev->device == 0x130F) ||
4248 (adev->pdev->device == 0x1310) ||
4249 (adev->pdev->device == 0x1311) ||
4250 (adev->pdev->device == 0x131C)) {
4251 adev->gfx.config.max_cu_per_sh = 8;
4252 adev->gfx.config.max_backends_per_se = 2;
4253 } else if ((adev->pdev->device == 0x1309) ||
4254 (adev->pdev->device == 0x130A) ||
4255 (adev->pdev->device == 0x130D) ||
4256 (adev->pdev->device == 0x1313) ||
4257 (adev->pdev->device == 0x131D)) {
4258 adev->gfx.config.max_cu_per_sh = 6;
4259 adev->gfx.config.max_backends_per_se = 2;
4260 } else if ((adev->pdev->device == 0x1306) ||
4261 (adev->pdev->device == 0x1307) ||
4262 (adev->pdev->device == 0x130B) ||
4263 (adev->pdev->device == 0x130E) ||
4264 (adev->pdev->device == 0x1315) ||
4265 (adev->pdev->device == 0x131B)) {
4266 adev->gfx.config.max_cu_per_sh = 4;
4267 adev->gfx.config.max_backends_per_se = 1;
4269 adev->gfx.config.max_cu_per_sh = 3;
4270 adev->gfx.config.max_backends_per_se = 1;
4272 adev->gfx.config.max_sh_per_se = 1;
4273 adev->gfx.config.max_texture_channel_caches = 4;
4274 adev->gfx.config.max_gprs = 256;
4275 adev->gfx.config.max_gs_threads = 16;
4276 adev->gfx.config.max_hw_contexts = 8;
4278 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4279 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4280 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4281 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4282 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
4287 adev->gfx.config.max_shader_engines = 1;
4288 adev->gfx.config.max_tile_pipes = 2;
4289 adev->gfx.config.max_cu_per_sh = 2;
4290 adev->gfx.config.max_sh_per_se = 1;
4291 adev->gfx.config.max_backends_per_se = 1;
4292 adev->gfx.config.max_texture_channel_caches = 2;
4293 adev->gfx.config.max_gprs = 256;
4294 adev->gfx.config.max_gs_threads = 16;
4295 adev->gfx.config.max_hw_contexts = 8;
4297 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4298 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4299 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4300 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4301 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
4305 mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
4306 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
4307 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
4309 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
4310 adev->gfx.config.mem_max_burst_length_bytes = 256;
4311 if (adev->flags & AMD_IS_APU) {
4312 /* Get memory bank mapping mode. */
4313 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
4314 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
4315 dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
4317 tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
4318 dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
4319 dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
4321 /* Validate settings in case only one DIMM installed. */
4322 if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12))
4323 dimm00_addr_map = 0;
4324 if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12))
4325 dimm01_addr_map = 0;
4326 if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12))
4327 dimm10_addr_map = 0;
4328 if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12))
4329 dimm11_addr_map = 0;
4331 /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */
4332 /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */
4333 if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11))
4334 adev->gfx.config.mem_row_size_in_kb = 2;
4336 adev->gfx.config.mem_row_size_in_kb = 1;
4338 tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT;
4339 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
4340 if (adev->gfx.config.mem_row_size_in_kb > 4)
4341 adev->gfx.config.mem_row_size_in_kb = 4;
4343 /* XXX use MC settings? */
4344 adev->gfx.config.shader_engine_tile_size = 32;
4345 adev->gfx.config.num_gpus = 1;
4346 adev->gfx.config.multi_gpu_tile_size = 64;
4348 /* fix up row size */
4349 gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK;
4350 switch (adev->gfx.config.mem_row_size_in_kb) {
4353 gb_addr_config |= (0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
4356 gb_addr_config |= (1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
4359 gb_addr_config |= (2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
4362 adev->gfx.config.gb_addr_config = gb_addr_config;
4365 static int gfx_v7_0_sw_init(void *handle)
4367 struct amdgpu_ring *ring;
4368 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4372 r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq);
4376 /* Privileged reg */
4377 r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq);
4381 /* Privileged inst */
4382 r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq);
4386 gfx_v7_0_scratch_init(adev);
4388 r = gfx_v7_0_init_microcode(adev);
4390 DRM_ERROR("Failed to load gfx firmware!\n");
4394 r = gfx_v7_0_rlc_init(adev);
4396 DRM_ERROR("Failed to init rlc BOs!\n");
4400 /* allocate mec buffers */
4401 r = gfx_v7_0_mec_init(adev);
4403 DRM_ERROR("Failed to init MEC BOs!\n");
4407 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
4408 ring = &adev->gfx.gfx_ring[i];
4409 ring->ring_obj = NULL;
4410 sprintf(ring->name, "gfx");
4411 r = amdgpu_ring_init(adev, ring, 1024,
4412 PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
4413 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP,
4414 AMDGPU_RING_TYPE_GFX);
4419 /* set up the compute queues */
4420 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4423 /* max 32 queues per MEC */
4424 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) {
4425 DRM_ERROR("Too many (%d) compute rings!\n", i);
4428 ring = &adev->gfx.compute_ring[i];
4429 ring->ring_obj = NULL;
4430 ring->use_doorbell = true;
4431 ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + i;
4432 ring->me = 1; /* first MEC */
4434 ring->queue = i % 8;
4435 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4436 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
4437 /* type-2 packets are deprecated on MEC, use type-3 instead */
4438 r = amdgpu_ring_init(adev, ring, 1024,
4439 PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
4440 &adev->gfx.eop_irq, irq_type,
4441 AMDGPU_RING_TYPE_COMPUTE);
4446 /* reserve GDS, GWS and OA resource for gfx */
4447 r = amdgpu_bo_create(adev, adev->gds.mem.gfx_partition_size,
4449 AMDGPU_GEM_DOMAIN_GDS, 0,
4450 NULL, NULL, &adev->gds.gds_gfx_bo);
4454 r = amdgpu_bo_create(adev, adev->gds.gws.gfx_partition_size,
4456 AMDGPU_GEM_DOMAIN_GWS, 0,
4457 NULL, NULL, &adev->gds.gws_gfx_bo);
4461 r = amdgpu_bo_create(adev, adev->gds.oa.gfx_partition_size,
4463 AMDGPU_GEM_DOMAIN_OA, 0,
4464 NULL, NULL, &adev->gds.oa_gfx_bo);
4468 adev->gfx.ce_ram_size = 0x8000;
4470 gfx_v7_0_gpu_early_init(adev);
4475 static int gfx_v7_0_sw_fini(void *handle)
4478 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4480 amdgpu_bo_unref(&adev->gds.oa_gfx_bo);
4481 amdgpu_bo_unref(&adev->gds.gws_gfx_bo);
4482 amdgpu_bo_unref(&adev->gds.gds_gfx_bo);
4484 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4485 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
4486 for (i = 0; i < adev->gfx.num_compute_rings; i++)
4487 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
4489 gfx_v7_0_cp_compute_fini(adev);
4490 gfx_v7_0_rlc_fini(adev);
4491 gfx_v7_0_mec_fini(adev);
4496 static int gfx_v7_0_hw_init(void *handle)
4499 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4501 gfx_v7_0_gpu_init(adev);
4504 r = gfx_v7_0_rlc_resume(adev);
4508 r = gfx_v7_0_cp_resume(adev);
4515 static int gfx_v7_0_hw_fini(void *handle)
4517 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4519 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
4520 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
4521 gfx_v7_0_cp_enable(adev, false);
4522 gfx_v7_0_rlc_stop(adev);
4523 gfx_v7_0_fini_pg(adev);
4528 static int gfx_v7_0_suspend(void *handle)
4530 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4532 return gfx_v7_0_hw_fini(adev);
4535 static int gfx_v7_0_resume(void *handle)
4537 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4539 return gfx_v7_0_hw_init(adev);
4542 static bool gfx_v7_0_is_idle(void *handle)
4544 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4546 if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK)
4552 static int gfx_v7_0_wait_for_idle(void *handle)
4556 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4558 for (i = 0; i < adev->usec_timeout; i++) {
4559 /* read MC_STATUS */
4560 tmp = RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK;
4569 static int gfx_v7_0_soft_reset(void *handle)
4571 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
4573 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4576 tmp = RREG32(mmGRBM_STATUS);
4577 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
4578 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
4579 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
4580 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
4581 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
4582 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK))
4583 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK |
4584 GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK;
4586 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
4587 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK;
4588 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK;
4592 tmp = RREG32(mmGRBM_STATUS2);
4593 if (tmp & GRBM_STATUS2__RLC_BUSY_MASK)
4594 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
4597 tmp = RREG32(mmSRBM_STATUS);
4598 if (tmp & SRBM_STATUS__GRBM_RQ_PENDING_MASK)
4599 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK;
4601 if (grbm_soft_reset || srbm_soft_reset) {
4603 gfx_v7_0_fini_pg(adev);
4604 gfx_v7_0_update_cg(adev, false);
4607 gfx_v7_0_rlc_stop(adev);
4609 /* Disable GFX parsing/prefetching */
4610 WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK);
4612 /* Disable MEC parsing/prefetching */
4613 WREG32(mmCP_MEC_CNTL, CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK);
4615 if (grbm_soft_reset) {
4616 tmp = RREG32(mmGRBM_SOFT_RESET);
4617 tmp |= grbm_soft_reset;
4618 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
4619 WREG32(mmGRBM_SOFT_RESET, tmp);
4620 tmp = RREG32(mmGRBM_SOFT_RESET);
4624 tmp &= ~grbm_soft_reset;
4625 WREG32(mmGRBM_SOFT_RESET, tmp);
4626 tmp = RREG32(mmGRBM_SOFT_RESET);
4629 if (srbm_soft_reset) {
4630 tmp = RREG32(mmSRBM_SOFT_RESET);
4631 tmp |= srbm_soft_reset;
4632 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
4633 WREG32(mmSRBM_SOFT_RESET, tmp);
4634 tmp = RREG32(mmSRBM_SOFT_RESET);
4638 tmp &= ~srbm_soft_reset;
4639 WREG32(mmSRBM_SOFT_RESET, tmp);
4640 tmp = RREG32(mmSRBM_SOFT_RESET);
4642 /* Wait a little for things to settle down */
4648 static void gfx_v7_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
4649 enum amdgpu_interrupt_state state)
4654 case AMDGPU_IRQ_STATE_DISABLE:
4655 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4656 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4657 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4659 case AMDGPU_IRQ_STATE_ENABLE:
4660 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4661 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4662 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4669 static void gfx_v7_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
4671 enum amdgpu_interrupt_state state)
4673 u32 mec_int_cntl, mec_int_cntl_reg;
4676 * amdgpu controls only pipe 0 of MEC1. That's why this function only
4677 * handles the setting of interrupts for this specific pipe. All other
4678 * pipes' interrupts are set by amdkfd.
4684 mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL;
4687 DRM_DEBUG("invalid pipe %d\n", pipe);
4691 DRM_DEBUG("invalid me %d\n", me);
4696 case AMDGPU_IRQ_STATE_DISABLE:
4697 mec_int_cntl = RREG32(mec_int_cntl_reg);
4698 mec_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4699 WREG32(mec_int_cntl_reg, mec_int_cntl);
4701 case AMDGPU_IRQ_STATE_ENABLE:
4702 mec_int_cntl = RREG32(mec_int_cntl_reg);
4703 mec_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
4704 WREG32(mec_int_cntl_reg, mec_int_cntl);
4711 static int gfx_v7_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
4712 struct amdgpu_irq_src *src,
4714 enum amdgpu_interrupt_state state)
4719 case AMDGPU_IRQ_STATE_DISABLE:
4720 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4721 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
4722 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4724 case AMDGPU_IRQ_STATE_ENABLE:
4725 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4726 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
4727 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4736 static int gfx_v7_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
4737 struct amdgpu_irq_src *src,
4739 enum amdgpu_interrupt_state state)
4744 case AMDGPU_IRQ_STATE_DISABLE:
4745 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4746 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
4747 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4749 case AMDGPU_IRQ_STATE_ENABLE:
4750 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4751 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
4752 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4761 static int gfx_v7_0_set_eop_interrupt_state(struct amdgpu_device *adev,
4762 struct amdgpu_irq_src *src,
4764 enum amdgpu_interrupt_state state)
4767 case AMDGPU_CP_IRQ_GFX_EOP:
4768 gfx_v7_0_set_gfx_eop_interrupt_state(adev, state);
4770 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
4771 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
4773 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
4774 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
4776 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
4777 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
4779 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
4780 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
4782 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
4783 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
4785 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
4786 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
4788 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
4789 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
4791 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
4792 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
4800 static int gfx_v7_0_eop_irq(struct amdgpu_device *adev,
4801 struct amdgpu_irq_src *source,
4802 struct amdgpu_iv_entry *entry)
4805 struct amdgpu_ring *ring;
4808 DRM_DEBUG("IH: CP EOP\n");
4809 me_id = (entry->ring_id & 0x0c) >> 2;
4810 pipe_id = (entry->ring_id & 0x03) >> 0;
4813 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
4817 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4818 ring = &adev->gfx.compute_ring[i];
4819 if ((ring->me == me_id) & (ring->pipe == pipe_id))
4820 amdgpu_fence_process(ring);
4827 static int gfx_v7_0_priv_reg_irq(struct amdgpu_device *adev,
4828 struct amdgpu_irq_src *source,
4829 struct amdgpu_iv_entry *entry)
4831 DRM_ERROR("Illegal register access in command stream\n");
4832 schedule_work(&adev->reset_work);
4836 static int gfx_v7_0_priv_inst_irq(struct amdgpu_device *adev,
4837 struct amdgpu_irq_src *source,
4838 struct amdgpu_iv_entry *entry)
4840 DRM_ERROR("Illegal instruction in command stream\n");
4841 // XXX soft reset the gfx block only
4842 schedule_work(&adev->reset_work);
4846 static int gfx_v7_0_set_clockgating_state(void *handle,
4847 enum amd_clockgating_state state)
4850 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4852 if (state == AMD_CG_STATE_GATE)
4855 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
4856 /* order matters! */
4858 gfx_v7_0_enable_mgcg(adev, true);
4859 gfx_v7_0_enable_cgcg(adev, true);
4861 gfx_v7_0_enable_cgcg(adev, false);
4862 gfx_v7_0_enable_mgcg(adev, false);
4864 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
4869 static int gfx_v7_0_set_powergating_state(void *handle,
4870 enum amd_powergating_state state)
4873 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4875 if (state == AMD_PG_STATE_GATE)
4878 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
4879 AMD_PG_SUPPORT_GFX_SMG |
4880 AMD_PG_SUPPORT_GFX_DMG |
4882 AMD_PG_SUPPORT_GDS |
4883 AMD_PG_SUPPORT_RLC_SMU_HS)) {
4884 gfx_v7_0_update_gfx_pg(adev, gate);
4885 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
4886 gfx_v7_0_enable_cp_pg(adev, gate);
4887 gfx_v7_0_enable_gds_pg(adev, gate);
4894 const struct amd_ip_funcs gfx_v7_0_ip_funcs = {
4896 .early_init = gfx_v7_0_early_init,
4897 .late_init = gfx_v7_0_late_init,
4898 .sw_init = gfx_v7_0_sw_init,
4899 .sw_fini = gfx_v7_0_sw_fini,
4900 .hw_init = gfx_v7_0_hw_init,
4901 .hw_fini = gfx_v7_0_hw_fini,
4902 .suspend = gfx_v7_0_suspend,
4903 .resume = gfx_v7_0_resume,
4904 .is_idle = gfx_v7_0_is_idle,
4905 .wait_for_idle = gfx_v7_0_wait_for_idle,
4906 .soft_reset = gfx_v7_0_soft_reset,
4907 .set_clockgating_state = gfx_v7_0_set_clockgating_state,
4908 .set_powergating_state = gfx_v7_0_set_powergating_state,
4911 static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = {
4912 .get_rptr = gfx_v7_0_ring_get_rptr_gfx,
4913 .get_wptr = gfx_v7_0_ring_get_wptr_gfx,
4914 .set_wptr = gfx_v7_0_ring_set_wptr_gfx,
4916 .emit_ib = gfx_v7_0_ring_emit_ib_gfx,
4917 .emit_fence = gfx_v7_0_ring_emit_fence_gfx,
4918 .emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync,
4919 .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush,
4920 .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch,
4921 .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush,
4922 .emit_hdp_invalidate = gfx_v7_0_ring_emit_hdp_invalidate,
4923 .test_ring = gfx_v7_0_ring_test_ring,
4924 .test_ib = gfx_v7_0_ring_test_ib,
4925 .insert_nop = amdgpu_ring_insert_nop,
4926 .pad_ib = amdgpu_ring_generic_pad_ib,
4929 static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = {
4930 .get_rptr = gfx_v7_0_ring_get_rptr_compute,
4931 .get_wptr = gfx_v7_0_ring_get_wptr_compute,
4932 .set_wptr = gfx_v7_0_ring_set_wptr_compute,
4934 .emit_ib = gfx_v7_0_ring_emit_ib_compute,
4935 .emit_fence = gfx_v7_0_ring_emit_fence_compute,
4936 .emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync,
4937 .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush,
4938 .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch,
4939 .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush,
4940 .emit_hdp_invalidate = gfx_v7_0_ring_emit_hdp_invalidate,
4941 .test_ring = gfx_v7_0_ring_test_ring,
4942 .test_ib = gfx_v7_0_ring_test_ib,
4943 .insert_nop = amdgpu_ring_insert_nop,
4944 .pad_ib = amdgpu_ring_generic_pad_ib,
4947 static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev)
4951 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4952 adev->gfx.gfx_ring[i].funcs = &gfx_v7_0_ring_funcs_gfx;
4953 for (i = 0; i < adev->gfx.num_compute_rings; i++)
4954 adev->gfx.compute_ring[i].funcs = &gfx_v7_0_ring_funcs_compute;
4957 static const struct amdgpu_irq_src_funcs gfx_v7_0_eop_irq_funcs = {
4958 .set = gfx_v7_0_set_eop_interrupt_state,
4959 .process = gfx_v7_0_eop_irq,
4962 static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_reg_irq_funcs = {
4963 .set = gfx_v7_0_set_priv_reg_fault_state,
4964 .process = gfx_v7_0_priv_reg_irq,
4967 static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_inst_irq_funcs = {
4968 .set = gfx_v7_0_set_priv_inst_fault_state,
4969 .process = gfx_v7_0_priv_inst_irq,
4972 static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev)
4974 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
4975 adev->gfx.eop_irq.funcs = &gfx_v7_0_eop_irq_funcs;
4977 adev->gfx.priv_reg_irq.num_types = 1;
4978 adev->gfx.priv_reg_irq.funcs = &gfx_v7_0_priv_reg_irq_funcs;
4980 adev->gfx.priv_inst_irq.num_types = 1;
4981 adev->gfx.priv_inst_irq.funcs = &gfx_v7_0_priv_inst_irq_funcs;
4984 static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev)
4986 /* init asci gds info */
4987 adev->gds.mem.total_size = RREG32(mmGDS_VMID0_SIZE);
4988 adev->gds.gws.total_size = 64;
4989 adev->gds.oa.total_size = 16;
4991 if (adev->gds.mem.total_size == 64 * 1024) {
4992 adev->gds.mem.gfx_partition_size = 4096;
4993 adev->gds.mem.cs_partition_size = 4096;
4995 adev->gds.gws.gfx_partition_size = 4;
4996 adev->gds.gws.cs_partition_size = 4;
4998 adev->gds.oa.gfx_partition_size = 4;
4999 adev->gds.oa.cs_partition_size = 1;
5001 adev->gds.mem.gfx_partition_size = 1024;
5002 adev->gds.mem.cs_partition_size = 1024;
5004 adev->gds.gws.gfx_partition_size = 16;
5005 adev->gds.gws.cs_partition_size = 16;
5007 adev->gds.oa.gfx_partition_size = 4;
5008 adev->gds.oa.cs_partition_size = 4;
5013 static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev)
5015 int i, j, k, counter, active_cu_number = 0;
5016 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
5017 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
5019 memset(cu_info, 0, sizeof(*cu_info));
5021 mutex_lock(&adev->grbm_idx_mutex);
5022 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5023 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5027 gfx_v7_0_select_se_sh(adev, i, j);
5028 bitmap = gfx_v7_0_get_cu_active_bitmap(adev);
5029 cu_info->bitmap[i][j] = bitmap;
5031 for (k = 0; k < 16; k ++) {
5032 if (bitmap & mask) {
5039 active_cu_number += counter;
5040 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
5043 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
5044 mutex_unlock(&adev->grbm_idx_mutex);
5046 cu_info->number = active_cu_number;
5047 cu_info->ao_cu_mask = ao_cu_mask;